system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
column
A[][] = ---------------------threadIdx.y
|
|
|
|
row |
|
|
|
|
threadIdx.x
*/
#define TILE_WIDTH 16
#define TILE_WIDTH 16
#define ar 311
#define ac_br 312
#define bc 115
using namespace std;
__global__ void mat_mul_shared(int *d_A, int *d_B, int *d_C, int rowA, int colA, int rowB, int colB, int rowC, int colC)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int row = tx + bx*TILE_WIDTH; // 0 to rowA/rowC
int col = ty + by*TILE_WIDTH; // 0 to colB/colC
__shared__ int s_A[TILE_WIDTH][TILE_WIDTH], s_B[TILE_WIDTH][TILE_WIDTH];
int cvalue = 0;
for(int i = 0; i < (colA+TILE_WIDTH-1)/TILE_WIDTH; i++)
{
if(row < rowA && i*TILE_WIDTH+ty < colA)
s_A[tx][ty] = d_A[row*colA + i*TILE_WIDTH+ty];
else
s_A[tx][ty] = 0;
if(i*TILE_WIDTH+tx < rowB && col < colB)
s_B[tx][ty] = d_B[(i*TILE_WIDTH+tx)*colB + col];
else
s_B[tx][ty] = 0;
__syncthreads();
for(int k = 0; k < TILE_WIDTH; k++)
cvalue += s_A[tx][k]*s_B[k][ty];
__syncthreads();
}
if(row < rowC && col < colC)
d_C[row*colC + col] = cvalue;
}// End of mat_mul_shared function | .file "tmpxft_000deea1_00000000-6_mat_mul_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii
.type _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii, @function
_Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14mat_mul_sharedPiS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii, .-_Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii
.globl _Z14mat_mul_sharedPiS_S_iiiiii
.type _Z14mat_mul_sharedPiS_S_iiiiii, @function
_Z14mat_mul_sharedPiS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14mat_mul_sharedPiS_S_iiiiii, .-_Z14mat_mul_sharedPiS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14mat_mul_sharedPiS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14mat_mul_sharedPiS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
column
A[][] = ---------------------threadIdx.y
|
|
|
|
row |
|
|
|
|
threadIdx.x
*/
#define TILE_WIDTH 16
#define TILE_WIDTH 16
#define ar 311
#define ac_br 312
#define bc 115
using namespace std;
__global__ void mat_mul_shared(int *d_A, int *d_B, int *d_C, int rowA, int colA, int rowB, int colB, int rowC, int colC)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int row = tx + bx*TILE_WIDTH; // 0 to rowA/rowC
int col = ty + by*TILE_WIDTH; // 0 to colB/colC
__shared__ int s_A[TILE_WIDTH][TILE_WIDTH], s_B[TILE_WIDTH][TILE_WIDTH];
int cvalue = 0;
for(int i = 0; i < (colA+TILE_WIDTH-1)/TILE_WIDTH; i++)
{
if(row < rowA && i*TILE_WIDTH+ty < colA)
s_A[tx][ty] = d_A[row*colA + i*TILE_WIDTH+ty];
else
s_A[tx][ty] = 0;
if(i*TILE_WIDTH+tx < rowB && col < colB)
s_B[tx][ty] = d_B[(i*TILE_WIDTH+tx)*colB + col];
else
s_B[tx][ty] = 0;
__syncthreads();
for(int k = 0; k < TILE_WIDTH; k++)
cvalue += s_A[tx][k]*s_B[k][ty];
__syncthreads();
}
if(row < rowC && col < colC)
d_C[row*colC + col] = cvalue;
}// End of mat_mul_shared function | #include <hip/hip_runtime.h>
#include "includes.h"
/*
column
A[][] = ---------------------threadIdx.y
|
|
|
|
row |
|
|
|
|
threadIdx.x
*/
#define TILE_WIDTH 16
#define TILE_WIDTH 16
#define ar 311
#define ac_br 312
#define bc 115
using namespace std;
__global__ void mat_mul_shared(int *d_A, int *d_B, int *d_C, int rowA, int colA, int rowB, int colB, int rowC, int colC)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int row = tx + bx*TILE_WIDTH; // 0 to rowA/rowC
int col = ty + by*TILE_WIDTH; // 0 to colB/colC
__shared__ int s_A[TILE_WIDTH][TILE_WIDTH], s_B[TILE_WIDTH][TILE_WIDTH];
int cvalue = 0;
for(int i = 0; i < (colA+TILE_WIDTH-1)/TILE_WIDTH; i++)
{
if(row < rowA && i*TILE_WIDTH+ty < colA)
s_A[tx][ty] = d_A[row*colA + i*TILE_WIDTH+ty];
else
s_A[tx][ty] = 0;
if(i*TILE_WIDTH+tx < rowB && col < colB)
s_B[tx][ty] = d_B[(i*TILE_WIDTH+tx)*colB + col];
else
s_B[tx][ty] = 0;
__syncthreads();
for(int k = 0; k < TILE_WIDTH; k++)
cvalue += s_A[tx][k]*s_B[k][ty];
__syncthreads();
}
if(row < rowC && col < colC)
d_C[row*colC + col] = cvalue;
}// End of mat_mul_shared function |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
column
A[][] = ---------------------threadIdx.y
|
|
|
|
row |
|
|
|
|
threadIdx.x
*/
#define TILE_WIDTH 16
#define TILE_WIDTH 16
#define ar 311
#define ac_br 312
#define bc 115
using namespace std;
__global__ void mat_mul_shared(int *d_A, int *d_B, int *d_C, int rowA, int colA, int rowB, int colB, int rowC, int colC)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int row = tx + bx*TILE_WIDTH; // 0 to rowA/rowC
int col = ty + by*TILE_WIDTH; // 0 to colB/colC
__shared__ int s_A[TILE_WIDTH][TILE_WIDTH], s_B[TILE_WIDTH][TILE_WIDTH];
int cvalue = 0;
for(int i = 0; i < (colA+TILE_WIDTH-1)/TILE_WIDTH; i++)
{
if(row < rowA && i*TILE_WIDTH+ty < colA)
s_A[tx][ty] = d_A[row*colA + i*TILE_WIDTH+ty];
else
s_A[tx][ty] = 0;
if(i*TILE_WIDTH+tx < rowB && col < colB)
s_B[tx][ty] = d_B[(i*TILE_WIDTH+tx)*colB + col];
else
s_B[tx][ty] = 0;
__syncthreads();
for(int k = 0; k < TILE_WIDTH; k++)
cvalue += s_A[tx][k]*s_B[k][ty];
__syncthreads();
}
if(row < rowC && col < colC)
d_C[row*colC + col] = cvalue;
}// End of mat_mul_shared function | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14mat_mul_sharedPiS_S_iiiiii
.globl _Z14mat_mul_sharedPiS_S_iiiiii
.p2align 8
.type _Z14mat_mul_sharedPiS_S_iiiiii,@function
_Z14mat_mul_sharedPiS_S_iiiiii:
s_load_b32 s3, s[0:1], 0x1c
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s14, 4, v6
v_lshl_add_u32 v0, s15, 4, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_15
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v7, 6, v6
s_add_i32 s10, s3, 15
s_mov_b32 s12, 0
s_lshr_b32 s11, s10, 4
v_mad_u64_u32 v[3:4], null, v5, s3, v[1:2]
v_add_nc_u32_e32 v4, 0x400, v2
v_add_nc_u32_e32 v8, v7, v2
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v10, 0
s_max_i32 s11, s11, 1
v_add_nc_u32_e32 v9, v4, v7
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v5
v_cmp_le_i32_e64 s10, s2, v5
v_cmp_gt_i32_e64 s2, s9, v0
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s13, s2, -1
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2)
s_mov_b32 s2, s10
s_mov_b32 s14, 0
s_and_saveexec_b32 s15, vcc_lo
s_lshl_b32 s16, s12, 4
s_mov_b32 s14, exec_lo
v_add_nc_u32_e32 v11, s16, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s2, s3, v11
v_mov_b32_e32 v11, s16
s_and_not1_b32 s16, s10, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s16, s2
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_6
s_and_not1_b32 s14, s14, exec_lo
ds_store_b32 v8, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v12, v3, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s4, v12
v_add_co_ci_u32_e64 v13, s2, s5, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s15
v_lshl_add_u32 v12, s12, 4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s8, v12
s_or_b32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_xor_b32 s2, exec_lo, s14
s_cbranch_execz .LBB0_10
ds_store_b32 v9, v10
.LBB0_10:
s_and_not1_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[13:14], null, v12, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[12:13], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v12, v4
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_13:
v_add_nc_u32_e32 v13, s2, v7
s_add_i32 s2, s2, 4
ds_load_b32 v15, v12
ds_load_b32 v16, v13
v_add_nc_u32_e32 v12, 64, v12
s_cmp_eq_u32 s2, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[13:14], null, v15, v16, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v13
s_cbranch_scc0 .LBB0_13
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_16
.LBB0_15:
v_mov_b32_e32 v2, 0
.LBB0_16:
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v5
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_18
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14mat_mul_sharedPiS_S_iiiiii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14mat_mul_sharedPiS_S_iiiiii, .Lfunc_end0-_Z14mat_mul_sharedPiS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14mat_mul_sharedPiS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z14mat_mul_sharedPiS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
column
A[][] = ---------------------threadIdx.y
|
|
|
|
row |
|
|
|
|
threadIdx.x
*/
#define TILE_WIDTH 16
#define TILE_WIDTH 16
#define ar 311
#define ac_br 312
#define bc 115
using namespace std;
__global__ void mat_mul_shared(int *d_A, int *d_B, int *d_C, int rowA, int colA, int rowB, int colB, int rowC, int colC)
{
int bx = blockIdx.x, by = blockIdx.y;
int tx = threadIdx.x, ty = threadIdx.y;
int row = tx + bx*TILE_WIDTH; // 0 to rowA/rowC
int col = ty + by*TILE_WIDTH; // 0 to colB/colC
__shared__ int s_A[TILE_WIDTH][TILE_WIDTH], s_B[TILE_WIDTH][TILE_WIDTH];
int cvalue = 0;
for(int i = 0; i < (colA+TILE_WIDTH-1)/TILE_WIDTH; i++)
{
if(row < rowA && i*TILE_WIDTH+ty < colA)
s_A[tx][ty] = d_A[row*colA + i*TILE_WIDTH+ty];
else
s_A[tx][ty] = 0;
if(i*TILE_WIDTH+tx < rowB && col < colB)
s_B[tx][ty] = d_B[(i*TILE_WIDTH+tx)*colB + col];
else
s_B[tx][ty] = 0;
__syncthreads();
for(int k = 0; k < TILE_WIDTH; k++)
cvalue += s_A[tx][k]*s_B[k][ty];
__syncthreads();
}
if(row < rowC && col < colC)
d_C[row*colC + col] = cvalue;
}// End of mat_mul_shared function | .text
.file "mat_mul_shared.hip"
.globl _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii # -- Begin function _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.p2align 4, 0x90
.type _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii,@function
_Z29__device_stub__mat_mul_sharedPiS_S_iiiiii: # @_Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14mat_mul_sharedPiS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii, .Lfunc_end0-_Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14mat_mul_sharedPiS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14mat_mul_sharedPiS_S_iiiiii,@object # @_Z14mat_mul_sharedPiS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z14mat_mul_sharedPiS_S_iiiiii
.p2align 3, 0x0
_Z14mat_mul_sharedPiS_S_iiiiii:
.quad _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.size _Z14mat_mul_sharedPiS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14mat_mul_sharedPiS_S_iiiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14mat_mul_sharedPiS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14mat_mul_sharedPiS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f26270 */
/*0070*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0090*/ LEA R0, R9, R12, 0x4 ; /* 0x0000000c09007211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x18c], PT ; /* 0x0000630000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x188], P0 ; /* 0x0000620003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x5b0 ; /* 0x000004d000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R6, R6, 0xf, RZ ; /* 0x0000000f06067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.L.U32 R15, R2.reuse, 0x6, RZ ; /* 0x00000006020f7819 */
/* 0x040fe200000006ff */
/*0110*/ IMAD R4, R3, c[0x0][0x17c], R12 ; /* 0x00005f0003047a24 */
/* 0x000fe200078e020c */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0130*/ IMAD R16, R2, c[0x0][0x184], R12 ; /* 0x0000610002107a24 */
/* 0x000fe200078e020c */
/*0140*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0160*/ LEA.HI R7, R7, R6, RZ, 0x4 ; /* 0x0000000607077211 */
/* 0x000fe200078f20ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ LEA R16, R9, R16, 0x4 ; /* 0x0000001009107211 */
/* 0x000fe200078e20ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*01a0*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R12.reuse, 0x4, R15 ; /* 0x000000040c137824 */
/* 0x040fe200078e020f */
/*01c0*/ LEA R18, R12, 0x400, 0x2 ; /* 0x000004000c127811 */
/* 0x000fc400078e10ff */
/*01d0*/ SHF.R.S32.HI R17, RZ, 0x4, R7 ; /* 0x00000004ff117819 */
/* 0x000fe40000011407 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe20003f26270 */
/*01f0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f46270 */
/*0210*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x184], P1 ; /* 0x0000610000007a0c */
/* 0x000fe40000f26670 */
/*0230*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*0240*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R4, R14 ; /* 0x0000000e0004a202 */
/* 0x000fe40000000f00 */
/*0260*/ @!P2 MOV R5, R13 ; /* 0x0000000d0005a202 */
/* 0x000fe20000000f00 */
/*0270*/ @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; /* 0x00005a0010189625 */
/* 0x000fc800078e0219 */
/*0280*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02b0*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f5e0ff */
/*02c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.LE.AND P1, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe4000bf23270 */
/*02f0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0300*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R29, [R18] ; /* 0x00000000121d7984 */
/* 0x000fe80000000800 */
/*0340*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0350*/ LDS R24, [R18+0x40] ; /* 0x0000400012187984 */
/* 0x000e680000000800 */
/*0360*/ LDS R27, [R18+0x80] ; /* 0x00008000121b7984 */
/* 0x000ea80000000800 */
/*0370*/ LDS R26, [R18+0xc0] ; /* 0x0000c000121a7984 */
/* 0x000ee80000000800 */
/*0380*/ LDS R23, [R18+0x100] ; /* 0x0001000012177984 */
/* 0x000fe80000000800 */
/*0390*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*03a0*/ LDS R20, [R18+0x140] ; /* 0x0001400012147984 */
/* 0x000f680000000800 */
/*03b0*/ LDS R25, [R18+0x180] ; /* 0x0001800012197984 */
/* 0x000f680000000800 */
/*03c0*/ LDS R22, [R18+0x1c0] ; /* 0x0001c00012167984 */
/* 0x000f620000000800 */
/*03d0*/ IMAD R8, R29, R8, R21 ; /* 0x000000081d087224 */
/* 0x001fc600078e0215 */
/*03e0*/ LDS R21, [R18+0x200] ; /* 0x0002000012157984 */
/* 0x000fe20000000800 */
/*03f0*/ IMAD R8, R24, R9, R8 ; /* 0x0000000918087224 */
/* 0x002fc600078e0208 */
/*0400*/ LDS R24, [R18+0x240] ; /* 0x0002400012187984 */
/* 0x000fe20000000800 */
/*0410*/ IMAD R8, R27, R10, R8 ; /* 0x0000000a1b087224 */
/* 0x004fc800078e0208 */
/*0420*/ IMAD R26, R26, R11, R8 ; /* 0x0000000b1a1a7224 */
/* 0x008fe400078e0208 */
/*0430*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e240000000c00 */
/*0440*/ IMAD R4, R23, R4, R26 ; /* 0x0000000417047224 */
/* 0x010fe400078e021a */
/*0450*/ LDS R23, [R18+0x280] ; /* 0x0002800012177984 */
/* 0x000e640000000800 */
/*0460*/ IMAD R4, R20, R5, R4 ; /* 0x0000000514047224 */
/* 0x020fe400078e0204 */
/*0470*/ LDS R20, [R18+0x2c0] ; /* 0x0002c00012147984 */
/* 0x000ea40000000800 */
/*0480*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc400078e0204 */
/*0490*/ LDS R25, [R18+0x300] ; /* 0x0003000012197984 */
/* 0x000fe40000000800 */
/*04a0*/ IMAD R26, R22, R7, R4 ; /* 0x00000007161a7224 */
/* 0x000fe400078e0204 */
/*04b0*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000ee80000000c00 */
/*04c0*/ LDS R22, [R18+0x340] ; /* 0x0003400012167984 */
/* 0x000f220000000800 */
/*04d0*/ IMAD R26, R21, R8, R26 ; /* 0x00000008151a7224 */
/* 0x001fc600078e021a */
/*04e0*/ LDS R21, [R18+0x380] ; /* 0x0003800012157984 */
/* 0x000e220000000800 */
/*04f0*/ IMAD R9, R24, R9, R26 ; /* 0x0000000918097224 */
/* 0x000fc600078e021a */
/*0500*/ LDS R8, [R18+0x3c0] ; /* 0x0003c00012087984 */
/* 0x000f620000000800 */
/*0510*/ IMAD R9, R23, R10, R9 ; /* 0x0000000a17097224 */
/* 0x002fc800078e0209 */
/*0520*/ IMAD R9, R20, R11, R9 ; /* 0x0000000b14097224 */
/* 0x004fc800078e0209 */
/*0530*/ IMAD R4, R25, R4, R9 ; /* 0x0000000419047224 */
/* 0x008fc800078e0209 */
/*0540*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x010fe400078e0204 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD R16, R5, c[0x0][0x184], R16 ; /* 0x0000610005107a24 */
/* 0x000fe400078e0210 */
/*0570*/ IMAD R21, R21, R6, R4 ; /* 0x0000000615157224 */
/* 0x001fc800078e0204 */
/*0580*/ IMAD R21, R8, R7, R21 ; /* 0x0000000708157224 */
/* 0x020fe200078e0215 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @!P1 BRA 0x1e0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*05b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*05d0*/ IMAD R3, R3, c[0x0][0x18c], R0 ; /* 0x0000630003037a24 */
/* 0x000fd200078e0200 */
/*05e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14mat_mul_sharedPiS_S_iiiiii
.globl _Z14mat_mul_sharedPiS_S_iiiiii
.p2align 8
.type _Z14mat_mul_sharedPiS_S_iiiiii,@function
_Z14mat_mul_sharedPiS_S_iiiiii:
s_load_b32 s3, s[0:1], 0x1c
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s14, 4, v6
v_lshl_add_u32 v0, s15, 4, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_15
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v7, 6, v6
s_add_i32 s10, s3, 15
s_mov_b32 s12, 0
s_lshr_b32 s11, s10, 4
v_mad_u64_u32 v[3:4], null, v5, s3, v[1:2]
v_add_nc_u32_e32 v4, 0x400, v2
v_add_nc_u32_e32 v8, v7, v2
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v10, 0
s_max_i32 s11, s11, 1
v_add_nc_u32_e32 v9, v4, v7
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v5
v_cmp_le_i32_e64 s10, s2, v5
v_cmp_gt_i32_e64 s2, s9, v0
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s13, s2, -1
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2)
s_mov_b32 s2, s10
s_mov_b32 s14, 0
s_and_saveexec_b32 s15, vcc_lo
s_lshl_b32 s16, s12, 4
s_mov_b32 s14, exec_lo
v_add_nc_u32_e32 v11, s16, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s2, s3, v11
v_mov_b32_e32 v11, s16
s_and_not1_b32 s16, s10, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s16, s2
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_6
s_and_not1_b32 s14, s14, exec_lo
ds_store_b32 v8, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v12, v3, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s4, v12
v_add_co_ci_u32_e64 v13, s2, s5, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s15
v_lshl_add_u32 v12, s12, 4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s8, v12
s_or_b32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_xor_b32 s2, exec_lo, s14
s_cbranch_execz .LBB0_10
ds_store_b32 v9, v10
.LBB0_10:
s_and_not1_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[13:14], null, v12, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[12:13], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v12, v4
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_13:
v_add_nc_u32_e32 v13, s2, v7
s_add_i32 s2, s2, 4
ds_load_b32 v15, v12
ds_load_b32 v16, v13
v_add_nc_u32_e32 v12, 64, v12
s_cmp_eq_u32 s2, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[13:14], null, v15, v16, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v13
s_cbranch_scc0 .LBB0_13
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_16
.LBB0_15:
v_mov_b32_e32 v2, 0
.LBB0_16:
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v5
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_18
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14mat_mul_sharedPiS_S_iiiiii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14mat_mul_sharedPiS_S_iiiiii, .Lfunc_end0-_Z14mat_mul_sharedPiS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14mat_mul_sharedPiS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z14mat_mul_sharedPiS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000deea1_00000000-6_mat_mul_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii
.type _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii, @function
_Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14mat_mul_sharedPiS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii, .-_Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii
.globl _Z14mat_mul_sharedPiS_S_iiiiii
.type _Z14mat_mul_sharedPiS_S_iiiiii, @function
_Z14mat_mul_sharedPiS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z14mat_mul_sharedPiS_S_iiiiiiPiS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14mat_mul_sharedPiS_S_iiiiii, .-_Z14mat_mul_sharedPiS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14mat_mul_sharedPiS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14mat_mul_sharedPiS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mul_shared.hip"
.globl _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii # -- Begin function _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.p2align 4, 0x90
.type _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii,@function
_Z29__device_stub__mat_mul_sharedPiS_S_iiiiii: # @_Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14mat_mul_sharedPiS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii, .Lfunc_end0-_Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14mat_mul_sharedPiS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14mat_mul_sharedPiS_S_iiiiii,@object # @_Z14mat_mul_sharedPiS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z14mat_mul_sharedPiS_S_iiiiii
.p2align 3, 0x0
_Z14mat_mul_sharedPiS_S_iiiiii:
.quad _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.size _Z14mat_mul_sharedPiS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14mat_mul_sharedPiS_S_iiiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__mat_mul_sharedPiS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14mat_mul_sharedPiS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuda_multiply_f32(float *input_output, size_t size, float multipler)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size) input_output[idx] = input_output[idx] * multipler; // 7-bit (1-bit sign)
} | code for sm_80
Function : _Z17cuda_multiply_f32Pfmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R5, R0, c[0x0][0x170] ; /* 0x00005c0000057a20 */
/* 0x004fca0000400000 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_multiply_f32(float *input_output, size_t size, float multipler)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size) input_output[idx] = input_output[idx] * multipler; // 7-bit (1-bit sign)
} | .file "tmpxft_001218bd_00000000-6_cuda_multiply_f32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf
.type _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf, @function
_Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17cuda_multiply_f32Pfmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf, .-_Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf
.globl _Z17cuda_multiply_f32Pfmf
.type _Z17cuda_multiply_f32Pfmf, @function
_Z17cuda_multiply_f32Pfmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cuda_multiply_f32Pfmf, .-_Z17cuda_multiply_f32Pfmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cuda_multiply_f32Pfmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cuda_multiply_f32Pfmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_multiply_f32(float *input_output, size_t size, float multipler)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size) input_output[idx] = input_output[idx] * multipler; // 7-bit (1-bit sign)
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_multiply_f32(float *input_output, size_t size, float multipler)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size) input_output[idx] = input_output[idx] * multipler; // 7-bit (1-bit sign)
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_multiply_f32(float *input_output, size_t size, float multipler)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size) input_output[idx] = input_output[idx] * multipler; // 7-bit (1-bit sign)
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cuda_multiply_f32Pfmf
.globl _Z17cuda_multiply_f32Pfmf
.p2align 8
.type _Z17cuda_multiply_f32Pfmf,@function
_Z17cuda_multiply_f32Pfmf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cuda_multiply_f32Pfmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cuda_multiply_f32Pfmf, .Lfunc_end0-_Z17cuda_multiply_f32Pfmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cuda_multiply_f32Pfmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cuda_multiply_f32Pfmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_multiply_f32(float *input_output, size_t size, float multipler)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size) input_output[idx] = input_output[idx] * multipler; // 7-bit (1-bit sign)
} | .text
.file "cuda_multiply_f32.hip"
.globl _Z32__device_stub__cuda_multiply_f32Pfmf # -- Begin function _Z32__device_stub__cuda_multiply_f32Pfmf
.p2align 4, 0x90
.type _Z32__device_stub__cuda_multiply_f32Pfmf,@function
_Z32__device_stub__cuda_multiply_f32Pfmf: # @_Z32__device_stub__cuda_multiply_f32Pfmf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17cuda_multiply_f32Pfmf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__cuda_multiply_f32Pfmf, .Lfunc_end0-_Z32__device_stub__cuda_multiply_f32Pfmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cuda_multiply_f32Pfmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cuda_multiply_f32Pfmf,@object # @_Z17cuda_multiply_f32Pfmf
.section .rodata,"a",@progbits
.globl _Z17cuda_multiply_f32Pfmf
.p2align 3, 0x0
_Z17cuda_multiply_f32Pfmf:
.quad _Z32__device_stub__cuda_multiply_f32Pfmf
.size _Z17cuda_multiply_f32Pfmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cuda_multiply_f32Pfmf"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cuda_multiply_f32Pfmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cuda_multiply_f32Pfmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17cuda_multiply_f32Pfmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R5, R0, c[0x0][0x170] ; /* 0x00005c0000057a20 */
/* 0x004fca0000400000 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cuda_multiply_f32Pfmf
.globl _Z17cuda_multiply_f32Pfmf
.p2align 8
.type _Z17cuda_multiply_f32Pfmf,@function
_Z17cuda_multiply_f32Pfmf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cuda_multiply_f32Pfmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cuda_multiply_f32Pfmf, .Lfunc_end0-_Z17cuda_multiply_f32Pfmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cuda_multiply_f32Pfmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cuda_multiply_f32Pfmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001218bd_00000000-6_cuda_multiply_f32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf
.type _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf, @function
_Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17cuda_multiply_f32Pfmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf, .-_Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf
.globl _Z17cuda_multiply_f32Pfmf
.type _Z17cuda_multiply_f32Pfmf, @function
_Z17cuda_multiply_f32Pfmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17cuda_multiply_f32PfmfPfmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cuda_multiply_f32Pfmf, .-_Z17cuda_multiply_f32Pfmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cuda_multiply_f32Pfmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cuda_multiply_f32Pfmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_multiply_f32.hip"
.globl _Z32__device_stub__cuda_multiply_f32Pfmf # -- Begin function _Z32__device_stub__cuda_multiply_f32Pfmf
.p2align 4, 0x90
.type _Z32__device_stub__cuda_multiply_f32Pfmf,@function
_Z32__device_stub__cuda_multiply_f32Pfmf: # @_Z32__device_stub__cuda_multiply_f32Pfmf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17cuda_multiply_f32Pfmf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__cuda_multiply_f32Pfmf, .Lfunc_end0-_Z32__device_stub__cuda_multiply_f32Pfmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cuda_multiply_f32Pfmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cuda_multiply_f32Pfmf,@object # @_Z17cuda_multiply_f32Pfmf
.section .rodata,"a",@progbits
.globl _Z17cuda_multiply_f32Pfmf
.p2align 3, 0x0
_Z17cuda_multiply_f32Pfmf:
.quad _Z32__device_stub__cuda_multiply_f32Pfmf
.size _Z17cuda_multiply_f32Pfmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cuda_multiply_f32Pfmf"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cuda_multiply_f32Pfmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cuda_multiply_f32Pfmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <stdlib.h>
unsigned int N = 1;
unsigned int S = 4;
unsigned int D = 3;
// среднее для скользящего окна
__global__ void add(double *inputArr, double *outputArr, int inputSize, int outputSize) {
int col = threadIdx.x;
int row = blockIdx.x;
//printf("%d, %d \n", col,row);
int result = 0;
for (int k = row*2; k < row*2+4; k++) {
for (int m = col*2; m < col*2+4; m++) {
result += inputArr[k*inputSize + m];
// if (col == 1 && row == 1) printf("%d, %d: %f, %d \n",row,col, inputArr[k*inputSize + m], k*inputSize+m);
}
}
outputArr[row*(outputSize) + col] = result / 16;
//printf("%f, \n", result/16);
}
void fillRandArr(double *Arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
int tmp = rand() % 100; // допустим не больше 100
Arr[i*powS + j] = tmp;
printf("%d, ", (int)Arr[i*powS + j]);
}
printf("\n");
}
printf("\n");
}
void formExpandedArr(double *inputArr, double *expandedArr, int powD, int powS){
// верх лево
expandedArr[0] = inputArr[0];
// верх
for (int j = 1; j < powS + 1; j++) {
expandedArr[j] = inputArr[j-1];
}
// верх право
expandedArr[powS + 1] = inputArr[powS-1];
// право
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2) + powS + 1] = inputArr[(i-1)*powS + powS-1];
}
// низ право
expandedArr[(powS + 2)*(powD + 1) + powS + 1] = inputArr[powS*(powD-1) + powS-1];
// низ
for (int j = 1; j < powS + 1; j++) {
expandedArr[(powS + 2)*(powD + 1) + j] = inputArr[(powS)*(powD-1) + j-1];
}
// низ лево
expandedArr[(powD + 1)*(powS + 2)] = inputArr[(powD-1)*powS];
// лево
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2)] = inputArr[(i-1)*powS];
}
//центр
for (int i = 1; i < powD + 1; i++) {
for (int j = 1; j < powS + 1; j++) {
expandedArr[i*(powS + 2) + j] = inputArr[(i-1)*powS + j-1];
}
}
}
void printArr(double *arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
printf("%d, ", (int)arr[i*powS+j]);
}
printf("\n");
}
printf("\n");
}
void printVerificationArr(double *expandedArr, int powDres, int powSres, int powS){
double ArrResultCh[powDres*powSres]; // конечный
for (int i = 0; i < powDres; i++) {
for (int j = 0; j < powSres; j++) {
int result = 0;
for (int k = i*2; k < i*2+4; k++) {
for (int m = j*2; m < j*2+4; m++) {
result += expandedArr[k*(powS + 2) + m];
}
}
ArrResultCh[i*powSres + j] = result / 16;
printf("%d, ", (int)ArrResultCh[i*powSres + j]);
}
printf("\n");
}
}
int main(void) {
srand(time(NULL));
double *dev_i, *dev_o;
int powD = (int)(pow( 2.0, (double)D ));
int powS = (int)(pow( 2.0, (double)S ));
int powDres = (int)(pow( 2.0, (double)(D - 1) ));
int powSres = (int)(pow( 2.0, (double)(S - 1) ));
//Выделить память на GPU
cudaMalloc( (void**)&dev_i,
(powD + 2) * (powS + 2) * sizeof(double) );
cudaMalloc( (void**)&dev_o,
powDres * powSres * sizeof(double) );
double ArrM[powD*powS]; // начальный массив М
fillRandArr(ArrM, powD, powS);
while (N > 0) {
double ArrMPlus[(powD + 2) * (powS + 2)]; // начальный массив М с добавлением крайних рядов
formExpandedArr(ArrM, ArrMPlus, powD, powS);
printArr(ArrMPlus, powD+2, powS+2);
//Копируем массив ArrMPlus в dev_i
cudaMemcpy( dev_i, ArrMPlus,
(powD + 2) * (powS + 2) * sizeof(double),
cudaMemcpyHostToDevice );
add<<<powDres, powSres>>>(dev_i, dev_o, powS+2, powSres);
cudaDeviceSynchronize();
double ArrResult[powDres * powSres]; // конечный
//Копируем массив с GPU на CPU
cudaMemcpy( ArrResult, dev_o, powDres * powSres * sizeof(double), cudaMemcpyDeviceToHost );
printArr(ArrResult, powDres, powSres);
printVerificationArr(ArrMPlus, powDres, powSres, powS);
D--;
S--;
powD = powDres;
powS = powSres;
powDres = (int)(pow( 2.0, (double)(D - 1) ));
powSres = (int)(pow( 2.0, (double)(S - 1) ));
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
ArrM[i*powS + j] = ArrResult[i*powS + j];
}
}
printf("New Array:\n");
printArr(ArrM, powD, powS);
N--;
}
cudaFree( dev_i );
cudaFree( dev_o );
return 0;
} | code for sm_80
Function : _Z3addPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R16, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff107435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ SHF.L.U32 R2, R17, 0x1, RZ ; /* 0x0000000111027819 */
/* 0x001fe400000006ff */
/*0060*/ SHF.L.U32 R3, R0, 0x1, RZ ; /* 0x0000000100037819 */
/* 0x002fca00000006ff */
/*0070*/ IMAD R3, R2, c[0x0][0x170], R3 ; /* 0x00005c0002037a24 */
/* 0x000fc800078e0203 */
/*0080*/ IMAD.WIDE R22, R3, R16, c[0x0][0x160] ; /* 0x0000580003167625 */
/* 0x000fca00078e0210 */
/*0090*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R22.64+0x8] ; /* 0x00000804160a7981 */
/* 0x000ee8000c1e1b00 */
/*00b0*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x00001004160c7981 */
/* 0x000128000c1e1b00 */
/*00c0*/ LDG.E.64 R20, [R22.64+0x18] ; /* 0x0000180416147981 */
/* 0x0000e2000c1e1b00 */
/*00d0*/ IMAD.WIDE R28, R16, c[0x0][0x170], R22 ; /* 0x00005c00101c7a25 */
/* 0x000fca00078e0216 */
/*00e0*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0008e8000c1e1b00 */
/*00f0*/ LDG.E.64 R2, [R28.64+0x8] ; /* 0x000008041c027981 */
/* 0x0008e8000c1e1b00 */
/*0100*/ LDG.E.64 R4, [R28.64+0x10] ; /* 0x000010041c047981 */
/* 0x0008e8000c1e1b00 */
/*0110*/ LDG.E.64 R6, [R28.64+0x18] ; /* 0x000018041c067981 */
/* 0x0008e2000c1e1b00 */
/*0120*/ IMAD.WIDE R18, R16, c[0x0][0x170], R28 ; /* 0x00005c0010127a25 */
/* 0x000fe200078e021c */
/*0130*/ DADD R24, RZ, R8 ; /* 0x00000000ff187229 */
/* 0x0042880000000008 */
/*0140*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x00236c000c1e1b00 */
/*0150*/ F2I.F64.TRUNC R24, R24 ; /* 0x0000001800187311 */
/* 0x004eb0000030d100 */
/*0160*/ I2F.F64 R26, R24 ; /* 0x00000018001a7312 */
/* 0x004ee40000201c00 */
/*0170*/ DADD R26, R10, R26 ; /* 0x000000000a1a7229 */
/* 0x0084c4000000001a */
/*0180*/ LDG.E.64 R10, [R18.64+0x8] ; /* 0x00000804120a7981 */
/* 0x0042b0000c1e1b00 */
/*0190*/ F2I.F64.TRUNC R26, R26 ; /* 0x0000001a001a7311 */
/* 0x008e30000030d100 */
/*01a0*/ I2F.F64 R22, R26 ; /* 0x0000001a00167312 */
/* 0x001f240000201c00 */
/*01b0*/ DADD R28, R12, R22 ; /* 0x000000000c1c7229 */
/* 0x0100c40000000016 */
/*01c0*/ LDG.E.64 R12, [R18.64+0x10] ; /* 0x00001004120c7981 */
/* 0x001330000c1e1b00 */
/*01d0*/ F2I.F64.TRUNC R28, R28 ; /* 0x0000001c001c7311 */
/* 0x008e30000030d100 */
/*01e0*/ I2F.F64 R22, R28 ; /* 0x0000001c00167312 */
/* 0x001e240000201c00 */
/*01f0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0010c40000000016 */
/*0200*/ LDG.E.64 R20, [R18.64+0x18] ; /* 0x0000180412147981 */
/* 0x001330000c1e1b00 */
/*0210*/ F2I.F64.TRUNC R22, R22 ; /* 0x0000001600167311 */
/* 0x008e30000030d100 */
/*0220*/ I2F.F64 R24, R22 ; /* 0x0000001600187312 */
/* 0x0010e40000201c00 */
/*0230*/ IMAD.WIDE R22, R16, c[0x0][0x170], R18 ; /* 0x00005c0010167a25 */
/* 0x001fe200078e0212 */
/*0240*/ DADD R24, R14, R24 ; /* 0x000000000e187229 */
/* 0x0080c80000000018 */
/*0250*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x001f2c000c1e1b00 */
/*0260*/ F2I.F64.TRUNC R24, R24 ; /* 0x0000001800187311 */
/* 0x008e30000030d100 */
/*0270*/ I2F.F64 R26, R24 ; /* 0x00000018001a7312 */
/* 0x001e240000201c00 */
/*0280*/ DADD R26, R2, R26 ; /* 0x00000000021a7229 */
/* 0x0010c4000000001a */
/*0290*/ LDG.E.64 R2, [R22.64+0x8] ; /* 0x0000080416027981 */
/* 0x001f30000c1e1b00 */
/*02a0*/ F2I.F64.TRUNC R26, R26 ; /* 0x0000001a001a7311 */
/* 0x008e70000030d100 */
/*02b0*/ I2F.F64 R18, R26 ; /* 0x0000001a00127312 */
/* 0x002e240000201c00 */
/*02c0*/ DADD R18, R4, R18 ; /* 0x0000000004127229 */
/* 0x0010440000000012 */
/*02d0*/ LDG.E.64 R4, [R22.64+0x10] ; /* 0x0000100416047981 */
/* 0x001ef0000c1e1b00 */
/*02e0*/ F2I.F64.TRUNC R18, R18 ; /* 0x0000001200127311 */
/* 0x002e30000030d100 */
/*02f0*/ I2F.F64 R28, R18 ; /* 0x00000012001c7312 */
/* 0x001e240000201c00 */
/*0300*/ DADD R28, R6, R28 ; /* 0x00000000061c7229 */
/* 0x001044000000001c */
/*0310*/ LDG.E.64 R6, [R22.64+0x18] ; /* 0x0000180416067981 */
/* 0x001ee2000c1e1b00 */
/*0320*/ IMAD R17, R17, c[0x0][0x174], R0 ; /* 0x00005d0011117a24 */
/* 0x000fc800078e0200 */
/*0330*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc600078e0210 */
/*0340*/ F2I.F64.TRUNC R28, R28 ; /* 0x0000001c001c7311 */
/* 0x002e30000030d100 */
/*0350*/ I2F.F64 R24, R28 ; /* 0x0000001c00187312 */
/* 0x001f640000201c00 */
/*0360*/ DADD R8, R8, R24 ; /* 0x0000000008087229 */
/* 0x020e140000000018 */
/*0370*/ F2I.F64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x001e30000030d100 */
/*0380*/ I2F.F64 R24, R8 ; /* 0x0000000800187312 */
/* 0x001ea40000201c00 */
/*0390*/ DADD R10, R10, R24 ; /* 0x000000000a0a7229 */
/* 0x004e140000000018 */
/*03a0*/ F2I.F64.TRUNC R10, R10 ; /* 0x0000000a000a7311 */
/* 0x001e30000030d100 */
/*03b0*/ I2F.F64 R18, R10 ; /* 0x0000000a00127312 */
/* 0x001f240000201c00 */
/*03c0*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x010e140000000012 */
/*03d0*/ F2I.F64.TRUNC R12, R12 ; /* 0x0000000c000c7311 */
/* 0x001e30000030d100 */
/*03e0*/ I2F.F64 R18, R12 ; /* 0x0000000c00127312 */
/* 0x001e240000201c00 */
/*03f0*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x001e140000000012 */
/*0400*/ F2I.F64.TRUNC R18, R18 ; /* 0x0000001200127311 */
/* 0x001e30000030d100 */
/*0410*/ I2F.F64 R20, R18 ; /* 0x0000001200147312 */
/* 0x001e240000201c00 */
/*0420*/ DADD R14, R14, R20 ; /* 0x000000000e0e7229 */
/* 0x001e140000000014 */
/*0430*/ F2I.F64.TRUNC R14, R14 ; /* 0x0000000e000e7311 */
/* 0x001e30000030d100 */
/*0440*/ I2F.F64 R8, R14 ; /* 0x0000000e00087312 */
/* 0x001e240000201c00 */
/*0450*/ DADD R2, R2, R8 ; /* 0x0000000002027229 */
/* 0x001e140000000008 */
/*0460*/ F2I.F64.TRUNC R2, R2 ; /* 0x0000000200027311 */
/* 0x001e30000030d100 */
/*0470*/ I2F.F64 R8, R2 ; /* 0x0000000200087312 */
/* 0x001ee40000201c00 */
/*0480*/ DADD R4, R4, R8 ; /* 0x0000000004047229 */
/* 0x008e140000000008 */
/*0490*/ F2I.F64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x001e30000030d100 */
/*04a0*/ I2F.F64 R8, R4 ; /* 0x0000000400087312 */
/* 0x001e240000201c00 */
/*04b0*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e140000000008 */
/*04c0*/ F2I.F64.TRUNC R6, R6 ; /* 0x0000000600067311 */
/* 0x001e24000030d100 */
/*04d0*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x001fc80000011406 */
/*04e0*/ LEA.HI R9, R9, R6, RZ, 0x4 ; /* 0x0000000609097211 */
/* 0x000fc800078f20ff */
/*04f0*/ SHF.R.S32.HI R9, RZ, 0x4, R9 ; /* 0x00000004ff097819 */
/* 0x000fcc0000011409 */
/*0500*/ I2F.F64 R8, R9 ; /* 0x0000000900087312 */
/* 0x000e240000201c00 */
/*0510*/ STG.E.64 [R16.64], R8 ; /* 0x0000000810007986 */
/* 0x001fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <stdlib.h>
unsigned int N = 1;
unsigned int S = 4;
unsigned int D = 3;
// среднее для скользящего окна
__global__ void add(double *inputArr, double *outputArr, int inputSize, int outputSize) {
int col = threadIdx.x;
int row = blockIdx.x;
//printf("%d, %d \n", col,row);
int result = 0;
for (int k = row*2; k < row*2+4; k++) {
for (int m = col*2; m < col*2+4; m++) {
result += inputArr[k*inputSize + m];
// if (col == 1 && row == 1) printf("%d, %d: %f, %d \n",row,col, inputArr[k*inputSize + m], k*inputSize+m);
}
}
outputArr[row*(outputSize) + col] = result / 16;
//printf("%f, \n", result/16);
}
void fillRandArr(double *Arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
int tmp = rand() % 100; // допустим не больше 100
Arr[i*powS + j] = tmp;
printf("%d, ", (int)Arr[i*powS + j]);
}
printf("\n");
}
printf("\n");
}
void formExpandedArr(double *inputArr, double *expandedArr, int powD, int powS){
// верх лево
expandedArr[0] = inputArr[0];
// верх
for (int j = 1; j < powS + 1; j++) {
expandedArr[j] = inputArr[j-1];
}
// верх право
expandedArr[powS + 1] = inputArr[powS-1];
// право
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2) + powS + 1] = inputArr[(i-1)*powS + powS-1];
}
// низ право
expandedArr[(powS + 2)*(powD + 1) + powS + 1] = inputArr[powS*(powD-1) + powS-1];
// низ
for (int j = 1; j < powS + 1; j++) {
expandedArr[(powS + 2)*(powD + 1) + j] = inputArr[(powS)*(powD-1) + j-1];
}
// низ лево
expandedArr[(powD + 1)*(powS + 2)] = inputArr[(powD-1)*powS];
// лево
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2)] = inputArr[(i-1)*powS];
}
//центр
for (int i = 1; i < powD + 1; i++) {
for (int j = 1; j < powS + 1; j++) {
expandedArr[i*(powS + 2) + j] = inputArr[(i-1)*powS + j-1];
}
}
}
void printArr(double *arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
printf("%d, ", (int)arr[i*powS+j]);
}
printf("\n");
}
printf("\n");
}
void printVerificationArr(double *expandedArr, int powDres, int powSres, int powS){
double ArrResultCh[powDres*powSres]; // конечный
for (int i = 0; i < powDres; i++) {
for (int j = 0; j < powSres; j++) {
int result = 0;
for (int k = i*2; k < i*2+4; k++) {
for (int m = j*2; m < j*2+4; m++) {
result += expandedArr[k*(powS + 2) + m];
}
}
ArrResultCh[i*powSres + j] = result / 16;
printf("%d, ", (int)ArrResultCh[i*powSres + j]);
}
printf("\n");
}
}
int main(void) {
srand(time(NULL));
double *dev_i, *dev_o;
int powD = (int)(pow( 2.0, (double)D ));
int powS = (int)(pow( 2.0, (double)S ));
int powDres = (int)(pow( 2.0, (double)(D - 1) ));
int powSres = (int)(pow( 2.0, (double)(S - 1) ));
//Выделить память на GPU
cudaMalloc( (void**)&dev_i,
(powD + 2) * (powS + 2) * sizeof(double) );
cudaMalloc( (void**)&dev_o,
powDres * powSres * sizeof(double) );
double ArrM[powD*powS]; // начальный массив М
fillRandArr(ArrM, powD, powS);
while (N > 0) {
double ArrMPlus[(powD + 2) * (powS + 2)]; // начальный массив М с добавлением крайних рядов
formExpandedArr(ArrM, ArrMPlus, powD, powS);
printArr(ArrMPlus, powD+2, powS+2);
//Копируем массив ArrMPlus в dev_i
cudaMemcpy( dev_i, ArrMPlus,
(powD + 2) * (powS + 2) * sizeof(double),
cudaMemcpyHostToDevice );
add<<<powDres, powSres>>>(dev_i, dev_o, powS+2, powSres);
cudaDeviceSynchronize();
double ArrResult[powDres * powSres]; // конечный
//Копируем массив с GPU на CPU
cudaMemcpy( ArrResult, dev_o, powDres * powSres * sizeof(double), cudaMemcpyDeviceToHost );
printArr(ArrResult, powDres, powSres);
printVerificationArr(ArrMPlus, powDres, powSres, powS);
D--;
S--;
powD = powDres;
powS = powSres;
powDres = (int)(pow( 2.0, (double)(D - 1) ));
powSres = (int)(pow( 2.0, (double)(S - 1) ));
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
ArrM[i*powS + j] = ArrResult[i*powS + j];
}
}
printf("New Array:\n");
printArr(ArrM, powD, powS);
N--;
}
cudaFree( dev_i );
cudaFree( dev_o );
return 0;
} | .file "tmpxft_001a3ef1_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, "
.LC1:
.string "\n"
.text
.globl _Z11fillRandArrPdii
.type _Z11fillRandArrPdii, @function
_Z11fillRandArrPdii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L4
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rdi
leaq (%rdi,%rax,8), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rdi,%rax,8), %rbp
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %ecx
subl %ecx, %eax
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L4
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11fillRandArrPdii, .-_Z11fillRandArrPdii
.globl _Z15formExpandedArrPdS_ii
.type _Z15formExpandedArrPdS_ii, @function
_Z15formExpandedArrPdS_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r8
movq %rsi, %r9
movl %edx, %esi
movl %ecx, %edi
movsd (%r8), %xmm0
movsd %xmm0, (%r9)
testl %ecx, %ecx
jle .L12
movl %ecx, %edx
movl $0, %eax
.L13:
movsd (%r8,%rax,8), %xmm0
movsd %xmm0, 8(%r9,%rax,8)
addq $1, %rax
cmpq %rdx, %rax
jne .L13
.L12:
movslq %edi, %rax
leaq 1(%rax), %rdx
leaq 0(,%rdx,8), %r10
movsd -8(%r8,%rax,8), %xmm0
movsd %xmm0, (%r9,%rdx,8)
testl %esi, %esi
jle .L14
leaq -8(%r10), %r11
leaq (%r8,%r11), %rcx
leaq 8(%r10), %rbp
salq $4, %rax
addq %r9, %rax
leal 1(%rsi), %ebx
movl $1, %edx
.L15:
movsd -8(%rcx), %xmm0
movsd %xmm0, 24(%rax)
addl $1, %edx
addq %r11, %rcx
addq %rbp, %rax
cmpl %ebx, %edx
jne .L15
.L14:
leal -1(%rsi), %r12d
imull %edi, %r12d
leal 2(%rdi), %ebp
leal 1(%rsi), %ebx
imull %ebp, %ebx
leal (%r12,%rdi), %eax
cltq
movsd -8(%r8,%rax,8), %xmm0
leal (%rbx,%rdi), %eax
cltq
movsd %xmm0, 8(%r9,%rax,8)
testl %edi, %edi
jle .L16
movl %edi, %r11d
movslq %r12d, %rax
leaq (%r8,%rax,8), %rcx
movslq %ebx, %rax
leaq (%r9,%rax,8), %rdx
movl $0, %eax
.L17:
movsd (%rcx,%rax,8), %xmm0
movsd %xmm0, 8(%rdx,%rax,8)
addq $1, %rax
cmpq %r11, %rax
jne .L17
.L16:
movslq %r12d, %r12
movsd (%r8,%r12,8), %xmm0
movslq %ebx, %rbx
movsd %xmm0, (%r9,%rbx,8)
testl %esi, %esi
jle .L11
leaq -8(%r10), %r11
movq %r8, %rcx
addq $8, %r10
leaq (%r9,%r10), %rdx
addl $1, %esi
movl $1, %eax
.L19:
movsd (%rcx), %xmm0
movsd %xmm0, (%rdx)
movl %eax, %r12d
addl $1, %eax
addq %r11, %rcx
addq %r10, %rdx
cmpl %esi, %eax
jne .L19
movl %ebp, %ebx
movl $0, %r11d
movl $1, %r10d
movl %edi, %esi
jmp .L20
.L22:
movslq %r11d, %rax
leaq (%r8,%rax,8), %rcx
movslq %ebx, %rax
leaq (%r9,%rax,8), %rdx
movl $0, %eax
.L21:
movsd (%rcx,%rax,8), %xmm0
movsd %xmm0, 8(%rdx,%rax,8)
addq $1, %rax
cmpq %rsi, %rax
jne .L21
.L23:
leal 1(%r10), %eax
addl %edi, %r11d
addl %ebp, %ebx
cmpl %r10d, %r12d
je .L11
movl %eax, %r10d
.L20:
testl %edi, %edi
jg .L22
jmp .L23
.L11:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15formExpandedArrPdS_ii, .-_Z15formExpandedArrPdS_ii
.globl _Z8printArrPdii
.type _Z8printArrPdii, @function
_Z8printArrPdii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L31
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L32
.L34:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,8), %rbx
movq 24(%rsp), %rdi
addq %rdi, %rax
leaq (%rcx,%rax,8), %rbp
.L33:
cvttsd2sil (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L33
.L35:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L31
.L32:
testl %r15d, %r15d
jg .L34
jmp .L35
.L31:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8printArrPdii, .-_Z8printArrPdii
.globl _Z20printVerificationArrPdiii
.type _Z20printVerificationArrPdiii, @function
_Z20printVerificationArrPdiii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, -96(%rbp)
movl %edx, %edi
movl %edx, -72(%rbp)
movl %ecx, %eax
movq %fs:40, %rdx
movq %rdx, -56(%rbp)
xorl %edx, %edx
imull %esi, %edi
movslq %edi, %rdx
leaq 15(,%rdx,8), %rcx
movq %rcx, %rdx
andq $-16, %rdx
andq $-4096, %rcx
movq %rsp, %rdi
subq %rcx, %rdi
.L39:
cmpq %rdi, %rsp
je .L40
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L39
.L40:
movq %rdx, %rcx
andl $4095, %ecx
subq %rcx, %rsp
testq %rcx, %rcx
je .L41
orq $0, -8(%rsp,%rcx)
.L41:
movq %rsp, -104(%rbp)
testl %esi, %esi
jle .L38
leal 4(%rax,%rax), %edi
movl %edi, -84(%rbp)
leal (%rsi,%rsi), %edi
movl %edi, -88(%rbp)
movslq -72(%rbp), %r15
addq %r15, %r15
cltq
leaq 16(,%rax,8), %r12
movl $0, -80(%rbp)
movl $0, -68(%rbp)
movl $0, -76(%rbp)
jmp .L43
.L54:
leal 15(%rdx), %eax
testl %edx, %edx
cmovs %eax, %edx
sarl $4, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%r14,%rbx,4)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $2, %rbx
addq $16, %r13
cmpq %r15, %rbx
je .L48
.L46:
movq %r13, %rcx
movl $4, %esi
movl $0, %edx
.L45:
movl $0, %eax
.L44:
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
addsd (%rcx,%rax,8), %xmm0
cvttsd2sil %xmm0, %edx
addq $1, %rax
cmpq $4, %rax
jne .L44
addq %r12, %rcx
subl $1, %esi
jne .L45
jmp .L54
.L48:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -72(%rbp), %edi
addl %edi, -76(%rbp)
addl $2, -68(%rbp)
movl -68(%rbp), %eax
movl -84(%rbp), %ebx
addl %ebx, -80(%rbp)
movl -88(%rbp), %edi
cmpl %edi, %eax
je .L38
.L43:
cmpl $0, -72(%rbp)
jle .L48
movslq -80(%rbp), %rax
movq -96(%rbp), %rdi
leaq (%rdi,%rax,8), %r13
movslq -76(%rbp), %rax
movq -104(%rbp), %rdi
leaq (%rdi,%rax,8), %r14
movl $0, %ebx
jmp .L46
.L38:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L55
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z20printVerificationArrPdiii, .-_Z20printVerificationArrPdiii
.globl _Z26__device_stub__Z3addPdS_iiPdS_ii
.type _Z26__device_stub__Z3addPdS_iiPdS_ii, @function
_Z26__device_stub__Z3addPdS_iiPdS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z26__device_stub__Z3addPdS_iiPdS_ii, .-_Z26__device_stub__Z3addPdS_iiPdS_ii
.globl _Z3addPdS_ii
.type _Z3addPdS_ii, @function
_Z3addPdS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3addPdS_ii, .-_Z3addPdS_ii
.section .rodata.str1.1
.LC3:
.string "New Array:\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl D(%rip), %r12d
movl %r12d, %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %ebx
movl %ebx, %r15d
movl %ebx, -112(%rbp)
movl S(%rip), %ebx
movl %ebx, %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r14d
movl %r14d, -100(%rbp)
leal -1(%r12), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r13d
leal -1(%rbx), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
leal 2(%r15), %esi
leal 2(%r14), %eax
imull %eax, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq -96(%rbp), %rdi
call cudaMalloc@PLT
movl %r13d, %esi
imull %r12d, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq -88(%rbp), %rdi
call cudaMalloc@PLT
movl %r15d, %eax
imull %r14d, %eax
cltq
leaq 15(,%rax,8), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L73:
cmpq %rcx, %rsp
je .L74
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L73
.L74:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L75
orq $0, -8(%rsp,%rdx)
.L75:
movq %rsp, %rbx
movl -100(%rbp), %edx
movl -112(%rbp), %r15d
movl %r15d, %esi
movq %rbx, %rdi
call _Z11fillRandArrPdii
cmpl $0, N(%rip)
je .L76
movl %r15d, %esi
jmp .L93
.L78:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L79
orq $0, -8(%rsp,%rdx)
.L79:
movq %rsp, %rax
movl -100(%rbp), %ecx
movl %esi, %edx
movq %rax, -120(%rbp)
movq %rax, %rsi
movq %rbx, %rdi
call _Z15formExpandedArrPdS_ii
movl -104(%rbp), %edx
movl %r15d, %esi
movq -120(%rbp), %r15
movq %r15, %rdi
call _Z8printArrPdii
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl %r12d, %r15d
movl %r12d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl %r13d, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L80
movl %r12d, %ecx
movl -104(%rbp), %edx
movq -88(%rbp), %rsi
movq -96(%rbp), %rdi
call _Z26__device_stub__Z3addPdS_iiPdS_ii
.L80:
call cudaDeviceSynchronize@PLT
movl %r13d, %esi
imull %r12d, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 15(%rsi), %rax
movl $16, %edi
movl $0, %edx
divq %rdi
salq $4, %rax
movq %rax, %rcx
andq $-4096, %rcx
movq %rsp, %rdx
subq %rcx, %rdx
.L81:
cmpq %rdx, %rsp
je .L82
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L81
.L82:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L83
orq $0, -8(%rsp,%rdx)
.L83:
movq %rsp, %r14
movl $2, %ecx
movq %rsi, %rdx
movq -88(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %r12d, %edx
movl %r13d, %esi
movq %r14, %rdi
call _Z8printArrPdii
movl -100(%rbp), %ecx
movl %r12d, %edx
movl %r13d, %esi
movq -120(%rbp), %rdi
call _Z20printVerificationArrPdiii
movl D(%rip), %eax
leal -1(%rax), %edx
movl %edx, D(%rip)
movl S(%rip), %edi
movl %edi, -100(%rbp)
leal -1(%rdi), %edx
movl %edx, S(%rip)
leal -2(%rax), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, -104(%rbp)
movl -100(%rbp), %edi
leal -2(%rdi), %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, -120(%rbp)
movl $0, %esi
movl $0, %ecx
movslq %r12d, %rdi
testl %r13d, %r13d
jg .L88
.L89:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
movl %r13d, %esi
movq %rbx, %rdi
call _Z8printArrPdii
subl $1, N(%rip)
movq -112(%rbp), %rsp
movl %r13d, %esi
movl %r12d, -100(%rbp)
cmpl $0, N(%rip)
je .L76
movl -120(%rbp), %r12d
movl -104(%rbp), %r13d
.L93:
movq %rsp, -112(%rbp)
leal 2(%rsi), %r15d
movl -100(%rbp), %eax
addl $2, %eax
movl %eax, -104(%rbp)
movl %eax, %r14d
imull %r15d, %r14d
movslq %r14d, %r14
salq $3, %r14
leaq 15(%r14), %rax
movl $16, %edi
movl $0, %edx
divq %rdi
salq $4, %rax
movq %rax, %rcx
andq $-4096, %rcx
movq %rsp, %rdx
subq %rcx, %rdx
.L77:
cmpq %rdx, %rsp
je .L78
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L77
.L91:
movslq %esi, %rdx
leaq 0(,%rdx,8), %rax
addq %rdi, %rdx
salq $3, %rdx
.L90:
movsd (%r14,%rax), %xmm0
movsd %xmm0, (%rbx,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L90
.L92:
addl $1, %ecx
addl %r15d, %esi
cmpl %r13d, %ecx
je .L89
.L88:
testl %r12d, %r12d
jg .L91
jmp .L92
.L76:
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L102
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L102:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl D
.data
.align 4
.type D, @object
.size D, 4
D:
.long 3
.globl S
.align 4
.type S, @object
.size S, 4
S:
.long 4
.globl N
.align 4
.type N, @object
.size N, 4
N:
.long 1
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <stdlib.h>
unsigned int N = 1;
unsigned int S = 4;
unsigned int D = 3;
// среднее для скользящего окна
__global__ void add(double *inputArr, double *outputArr, int inputSize, int outputSize) {
int col = threadIdx.x;
int row = blockIdx.x;
//printf("%d, %d \n", col,row);
int result = 0;
for (int k = row*2; k < row*2+4; k++) {
for (int m = col*2; m < col*2+4; m++) {
result += inputArr[k*inputSize + m];
// if (col == 1 && row == 1) printf("%d, %d: %f, %d \n",row,col, inputArr[k*inputSize + m], k*inputSize+m);
}
}
outputArr[row*(outputSize) + col] = result / 16;
//printf("%f, \n", result/16);
}
void fillRandArr(double *Arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
int tmp = rand() % 100; // допустим не больше 100
Arr[i*powS + j] = tmp;
printf("%d, ", (int)Arr[i*powS + j]);
}
printf("\n");
}
printf("\n");
}
void formExpandedArr(double *inputArr, double *expandedArr, int powD, int powS){
// верх лево
expandedArr[0] = inputArr[0];
// верх
for (int j = 1; j < powS + 1; j++) {
expandedArr[j] = inputArr[j-1];
}
// верх право
expandedArr[powS + 1] = inputArr[powS-1];
// право
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2) + powS + 1] = inputArr[(i-1)*powS + powS-1];
}
// низ право
expandedArr[(powS + 2)*(powD + 1) + powS + 1] = inputArr[powS*(powD-1) + powS-1];
// низ
for (int j = 1; j < powS + 1; j++) {
expandedArr[(powS + 2)*(powD + 1) + j] = inputArr[(powS)*(powD-1) + j-1];
}
// низ лево
expandedArr[(powD + 1)*(powS + 2)] = inputArr[(powD-1)*powS];
// лево
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2)] = inputArr[(i-1)*powS];
}
//центр
for (int i = 1; i < powD + 1; i++) {
for (int j = 1; j < powS + 1; j++) {
expandedArr[i*(powS + 2) + j] = inputArr[(i-1)*powS + j-1];
}
}
}
void printArr(double *arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
printf("%d, ", (int)arr[i*powS+j]);
}
printf("\n");
}
printf("\n");
}
void printVerificationArr(double *expandedArr, int powDres, int powSres, int powS){
double ArrResultCh[powDres*powSres]; // конечный
for (int i = 0; i < powDres; i++) {
for (int j = 0; j < powSres; j++) {
int result = 0;
for (int k = i*2; k < i*2+4; k++) {
for (int m = j*2; m < j*2+4; m++) {
result += expandedArr[k*(powS + 2) + m];
}
}
ArrResultCh[i*powSres + j] = result / 16;
printf("%d, ", (int)ArrResultCh[i*powSres + j]);
}
printf("\n");
}
}
int main(void) {
srand(time(NULL));
double *dev_i, *dev_o;
int powD = (int)(pow( 2.0, (double)D ));
int powS = (int)(pow( 2.0, (double)S ));
int powDres = (int)(pow( 2.0, (double)(D - 1) ));
int powSres = (int)(pow( 2.0, (double)(S - 1) ));
//Выделить память на GPU
cudaMalloc( (void**)&dev_i,
(powD + 2) * (powS + 2) * sizeof(double) );
cudaMalloc( (void**)&dev_o,
powDres * powSres * sizeof(double) );
double ArrM[powD*powS]; // начальный массив М
fillRandArr(ArrM, powD, powS);
while (N > 0) {
double ArrMPlus[(powD + 2) * (powS + 2)]; // начальный массив М с добавлением крайних рядов
formExpandedArr(ArrM, ArrMPlus, powD, powS);
printArr(ArrMPlus, powD+2, powS+2);
//Копируем массив ArrMPlus в dev_i
cudaMemcpy( dev_i, ArrMPlus,
(powD + 2) * (powS + 2) * sizeof(double),
cudaMemcpyHostToDevice );
add<<<powDres, powSres>>>(dev_i, dev_o, powS+2, powSres);
cudaDeviceSynchronize();
double ArrResult[powDres * powSres]; // конечный
//Копируем массив с GPU на CPU
cudaMemcpy( ArrResult, dev_o, powDres * powSres * sizeof(double), cudaMemcpyDeviceToHost );
printArr(ArrResult, powDres, powSres);
printVerificationArr(ArrMPlus, powDres, powSres, powS);
D--;
S--;
powD = powDres;
powS = powSres;
powDres = (int)(pow( 2.0, (double)(D - 1) ));
powSres = (int)(pow( 2.0, (double)(S - 1) ));
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
ArrM[i*powS + j] = ArrResult[i*powS + j];
}
}
printf("New Array:\n");
printArr(ArrM, powD, powS);
N--;
}
cudaFree( dev_i );
cudaFree( dev_o );
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <stdlib.h>
unsigned int N = 1;
unsigned int S = 4;
unsigned int D = 3;
// среднее для скользящего окна
__global__ void add(double *inputArr, double *outputArr, int inputSize, int outputSize) {
int col = threadIdx.x;
int row = blockIdx.x;
//printf("%d, %d \n", col,row);
int result = 0;
for (int k = row*2; k < row*2+4; k++) {
for (int m = col*2; m < col*2+4; m++) {
result += inputArr[k*inputSize + m];
// if (col == 1 && row == 1) printf("%d, %d: %f, %d \n",row,col, inputArr[k*inputSize + m], k*inputSize+m);
}
}
outputArr[row*(outputSize) + col] = result / 16;
//printf("%f, \n", result/16);
}
void fillRandArr(double *Arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
int tmp = rand() % 100; // допустим не больше 100
Arr[i*powS + j] = tmp;
printf("%d, ", (int)Arr[i*powS + j]);
}
printf("\n");
}
printf("\n");
}
void formExpandedArr(double *inputArr, double *expandedArr, int powD, int powS){
// верх лево
expandedArr[0] = inputArr[0];
// верх
for (int j = 1; j < powS + 1; j++) {
expandedArr[j] = inputArr[j-1];
}
// верх право
expandedArr[powS + 1] = inputArr[powS-1];
// право
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2) + powS + 1] = inputArr[(i-1)*powS + powS-1];
}
// низ право
expandedArr[(powS + 2)*(powD + 1) + powS + 1] = inputArr[powS*(powD-1) + powS-1];
// низ
for (int j = 1; j < powS + 1; j++) {
expandedArr[(powS + 2)*(powD + 1) + j] = inputArr[(powS)*(powD-1) + j-1];
}
// низ лево
expandedArr[(powD + 1)*(powS + 2)] = inputArr[(powD-1)*powS];
// лево
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2)] = inputArr[(i-1)*powS];
}
//центр
for (int i = 1; i < powD + 1; i++) {
for (int j = 1; j < powS + 1; j++) {
expandedArr[i*(powS + 2) + j] = inputArr[(i-1)*powS + j-1];
}
}
}
void printArr(double *arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
printf("%d, ", (int)arr[i*powS+j]);
}
printf("\n");
}
printf("\n");
}
void printVerificationArr(double *expandedArr, int powDres, int powSres, int powS){
double ArrResultCh[powDres*powSres]; // конечный
for (int i = 0; i < powDres; i++) {
for (int j = 0; j < powSres; j++) {
int result = 0;
for (int k = i*2; k < i*2+4; k++) {
for (int m = j*2; m < j*2+4; m++) {
result += expandedArr[k*(powS + 2) + m];
}
}
ArrResultCh[i*powSres + j] = result / 16;
printf("%d, ", (int)ArrResultCh[i*powSres + j]);
}
printf("\n");
}
}
int main(void) {
srand(time(NULL));
double *dev_i, *dev_o;
int powD = (int)(pow( 2.0, (double)D ));
int powS = (int)(pow( 2.0, (double)S ));
int powDres = (int)(pow( 2.0, (double)(D - 1) ));
int powSres = (int)(pow( 2.0, (double)(S - 1) ));
//Выделить память на GPU
hipMalloc( (void**)&dev_i,
(powD + 2) * (powS + 2) * sizeof(double) );
hipMalloc( (void**)&dev_o,
powDres * powSres * sizeof(double) );
double ArrM[powD*powS]; // начальный массив М
fillRandArr(ArrM, powD, powS);
while (N > 0) {
double ArrMPlus[(powD + 2) * (powS + 2)]; // начальный массив М с добавлением крайних рядов
formExpandedArr(ArrM, ArrMPlus, powD, powS);
printArr(ArrMPlus, powD+2, powS+2);
//Копируем массив ArrMPlus в dev_i
hipMemcpy( dev_i, ArrMPlus,
(powD + 2) * (powS + 2) * sizeof(double),
hipMemcpyHostToDevice );
add<<<powDres, powSres>>>(dev_i, dev_o, powS+2, powSres);
hipDeviceSynchronize();
double ArrResult[powDres * powSres]; // конечный
//Копируем массив с GPU на CPU
hipMemcpy( ArrResult, dev_o, powDres * powSres * sizeof(double), hipMemcpyDeviceToHost );
printArr(ArrResult, powDres, powSres);
printVerificationArr(ArrMPlus, powDres, powSres, powS);
D--;
S--;
powD = powDres;
powS = powSres;
powDres = (int)(pow( 2.0, (double)(D - 1) ));
powSres = (int)(pow( 2.0, (double)(S - 1) ));
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
ArrM[i*powS + j] = ArrResult[i*powS + j];
}
}
printf("New Array:\n");
printArr(ArrM, powD, powS);
N--;
}
hipFree( dev_i );
hipFree( dev_o );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <stdlib.h>
unsigned int N = 1;
unsigned int S = 4;
unsigned int D = 3;
// среднее для скользящего окна
__global__ void add(double *inputArr, double *outputArr, int inputSize, int outputSize) {
int col = threadIdx.x;
int row = blockIdx.x;
//printf("%d, %d \n", col,row);
int result = 0;
for (int k = row*2; k < row*2+4; k++) {
for (int m = col*2; m < col*2+4; m++) {
result += inputArr[k*inputSize + m];
// if (col == 1 && row == 1) printf("%d, %d: %f, %d \n",row,col, inputArr[k*inputSize + m], k*inputSize+m);
}
}
outputArr[row*(outputSize) + col] = result / 16;
//printf("%f, \n", result/16);
}
void fillRandArr(double *Arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
int tmp = rand() % 100; // допустим не больше 100
Arr[i*powS + j] = tmp;
printf("%d, ", (int)Arr[i*powS + j]);
}
printf("\n");
}
printf("\n");
}
void formExpandedArr(double *inputArr, double *expandedArr, int powD, int powS){
// верх лево
expandedArr[0] = inputArr[0];
// верх
for (int j = 1; j < powS + 1; j++) {
expandedArr[j] = inputArr[j-1];
}
// верх право
expandedArr[powS + 1] = inputArr[powS-1];
// право
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2) + powS + 1] = inputArr[(i-1)*powS + powS-1];
}
// низ право
expandedArr[(powS + 2)*(powD + 1) + powS + 1] = inputArr[powS*(powD-1) + powS-1];
// низ
for (int j = 1; j < powS + 1; j++) {
expandedArr[(powS + 2)*(powD + 1) + j] = inputArr[(powS)*(powD-1) + j-1];
}
// низ лево
expandedArr[(powD + 1)*(powS + 2)] = inputArr[(powD-1)*powS];
// лево
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2)] = inputArr[(i-1)*powS];
}
//центр
for (int i = 1; i < powD + 1; i++) {
for (int j = 1; j < powS + 1; j++) {
expandedArr[i*(powS + 2) + j] = inputArr[(i-1)*powS + j-1];
}
}
}
void printArr(double *arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
printf("%d, ", (int)arr[i*powS+j]);
}
printf("\n");
}
printf("\n");
}
void printVerificationArr(double *expandedArr, int powDres, int powSres, int powS){
double ArrResultCh[powDres*powSres]; // конечный
for (int i = 0; i < powDres; i++) {
for (int j = 0; j < powSres; j++) {
int result = 0;
for (int k = i*2; k < i*2+4; k++) {
for (int m = j*2; m < j*2+4; m++) {
result += expandedArr[k*(powS + 2) + m];
}
}
ArrResultCh[i*powSres + j] = result / 16;
printf("%d, ", (int)ArrResultCh[i*powSres + j]);
}
printf("\n");
}
}
int main(void) {
srand(time(NULL));
double *dev_i, *dev_o;
int powD = (int)(pow( 2.0, (double)D ));
int powS = (int)(pow( 2.0, (double)S ));
int powDres = (int)(pow( 2.0, (double)(D - 1) ));
int powSres = (int)(pow( 2.0, (double)(S - 1) ));
//Выделить память на GPU
hipMalloc( (void**)&dev_i,
(powD + 2) * (powS + 2) * sizeof(double) );
hipMalloc( (void**)&dev_o,
powDres * powSres * sizeof(double) );
double ArrM[powD*powS]; // начальный массив М
fillRandArr(ArrM, powD, powS);
while (N > 0) {
double ArrMPlus[(powD + 2) * (powS + 2)]; // начальный массив М с добавлением крайних рядов
formExpandedArr(ArrM, ArrMPlus, powD, powS);
printArr(ArrMPlus, powD+2, powS+2);
//Копируем массив ArrMPlus в dev_i
hipMemcpy( dev_i, ArrMPlus,
(powD + 2) * (powS + 2) * sizeof(double),
hipMemcpyHostToDevice );
add<<<powDres, powSres>>>(dev_i, dev_o, powS+2, powSres);
hipDeviceSynchronize();
double ArrResult[powDres * powSres]; // конечный
//Копируем массив с GPU на CPU
hipMemcpy( ArrResult, dev_o, powDres * powSres * sizeof(double), hipMemcpyDeviceToHost );
printArr(ArrResult, powDres, powSres);
printVerificationArr(ArrMPlus, powDres, powSres, powS);
D--;
S--;
powD = powDres;
powS = powSres;
powDres = (int)(pow( 2.0, (double)(D - 1) ));
powSres = (int)(pow( 2.0, (double)(S - 1) ));
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
ArrM[i*powS + j] = ArrResult[i*powS + j];
}
}
printf("New Array:\n");
printArr(ArrM, powD, powS);
N--;
}
hipFree( dev_i );
hipFree( dev_o );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_ii
.globl _Z3addPdS_ii
.p2align 8
.type _Z3addPdS_ii,@function
_Z3addPdS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
v_mov_b32_e32 v3, 0
s_lshl_b32 s8, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s8, 3
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s15, s6
v_lshl_add_u32 v1, s4, 1, v1
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b64 s[4:5], 0
v_lshlrev_b64 v[4:5], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f64_i32_e32 v[7:8], v3
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
global_load_b64 v[5:6], v[5:6], off
s_cmp_eq_u32 s4, 32
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v3, v[5:6]
s_cbranch_scc0 .LBB0_2
v_add_nc_u32_e32 v1, s6, v1
s_add_i32 s4, s8, 1
s_cmp_ge_i32 s8, s7
s_cbranch_scc1 .LBB0_5
s_mov_b32 s8, s4
s_branch .LBB0_1
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x8
v_lshrrev_b32_e32 v1, 28, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v3, v1
v_ashrrev_i32_e32 v1, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[1:2], v1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_ii, .Lfunc_end0-_Z3addPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <stdlib.h>
unsigned int N = 1;
unsigned int S = 4;
unsigned int D = 3;
// среднее для скользящего окна
__global__ void add(double *inputArr, double *outputArr, int inputSize, int outputSize) {
int col = threadIdx.x;
int row = blockIdx.x;
//printf("%d, %d \n", col,row);
int result = 0;
for (int k = row*2; k < row*2+4; k++) {
for (int m = col*2; m < col*2+4; m++) {
result += inputArr[k*inputSize + m];
// if (col == 1 && row == 1) printf("%d, %d: %f, %d \n",row,col, inputArr[k*inputSize + m], k*inputSize+m);
}
}
outputArr[row*(outputSize) + col] = result / 16;
//printf("%f, \n", result/16);
}
void fillRandArr(double *Arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
int tmp = rand() % 100; // допустим не больше 100
Arr[i*powS + j] = tmp;
printf("%d, ", (int)Arr[i*powS + j]);
}
printf("\n");
}
printf("\n");
}
void formExpandedArr(double *inputArr, double *expandedArr, int powD, int powS){
// верх лево
expandedArr[0] = inputArr[0];
// верх
for (int j = 1; j < powS + 1; j++) {
expandedArr[j] = inputArr[j-1];
}
// верх право
expandedArr[powS + 1] = inputArr[powS-1];
// право
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2) + powS + 1] = inputArr[(i-1)*powS + powS-1];
}
// низ право
expandedArr[(powS + 2)*(powD + 1) + powS + 1] = inputArr[powS*(powD-1) + powS-1];
// низ
for (int j = 1; j < powS + 1; j++) {
expandedArr[(powS + 2)*(powD + 1) + j] = inputArr[(powS)*(powD-1) + j-1];
}
// низ лево
expandedArr[(powD + 1)*(powS + 2)] = inputArr[(powD-1)*powS];
// лево
for (int i = 1; i < powD + 1; i++) {
expandedArr[i*(powS + 2)] = inputArr[(i-1)*powS];
}
//центр
for (int i = 1; i < powD + 1; i++) {
for (int j = 1; j < powS + 1; j++) {
expandedArr[i*(powS + 2) + j] = inputArr[(i-1)*powS + j-1];
}
}
}
void printArr(double *arr, int powD, int powS){
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
printf("%d, ", (int)arr[i*powS+j]);
}
printf("\n");
}
printf("\n");
}
void printVerificationArr(double *expandedArr, int powDres, int powSres, int powS){
double ArrResultCh[powDres*powSres]; // конечный
for (int i = 0; i < powDres; i++) {
for (int j = 0; j < powSres; j++) {
int result = 0;
for (int k = i*2; k < i*2+4; k++) {
for (int m = j*2; m < j*2+4; m++) {
result += expandedArr[k*(powS + 2) + m];
}
}
ArrResultCh[i*powSres + j] = result / 16;
printf("%d, ", (int)ArrResultCh[i*powSres + j]);
}
printf("\n");
}
}
int main(void) {
srand(time(NULL));
double *dev_i, *dev_o;
int powD = (int)(pow( 2.0, (double)D ));
int powS = (int)(pow( 2.0, (double)S ));
int powDres = (int)(pow( 2.0, (double)(D - 1) ));
int powSres = (int)(pow( 2.0, (double)(S - 1) ));
//Выделить память на GPU
hipMalloc( (void**)&dev_i,
(powD + 2) * (powS + 2) * sizeof(double) );
hipMalloc( (void**)&dev_o,
powDres * powSres * sizeof(double) );
double ArrM[powD*powS]; // начальный массив М
fillRandArr(ArrM, powD, powS);
while (N > 0) {
double ArrMPlus[(powD + 2) * (powS + 2)]; // начальный массив М с добавлением крайних рядов
formExpandedArr(ArrM, ArrMPlus, powD, powS);
printArr(ArrMPlus, powD+2, powS+2);
//Копируем массив ArrMPlus в dev_i
hipMemcpy( dev_i, ArrMPlus,
(powD + 2) * (powS + 2) * sizeof(double),
hipMemcpyHostToDevice );
add<<<powDres, powSres>>>(dev_i, dev_o, powS+2, powSres);
hipDeviceSynchronize();
double ArrResult[powDres * powSres]; // конечный
//Копируем массив с GPU на CPU
hipMemcpy( ArrResult, dev_o, powDres * powSres * sizeof(double), hipMemcpyDeviceToHost );
printArr(ArrResult, powDres, powSres);
printVerificationArr(ArrMPlus, powDres, powSres, powS);
D--;
S--;
powD = powDres;
powS = powSres;
powDres = (int)(pow( 2.0, (double)(D - 1) ));
powSres = (int)(pow( 2.0, (double)(S - 1) ));
for (int i = 0; i < powD; i++) {
for (int j = 0; j < powS; j++) {
ArrM[i*powS + j] = ArrResult[i*powS + j];
}
}
printf("New Array:\n");
printArr(ArrM, powD, powS);
N--;
}
hipFree( dev_i );
hipFree( dev_o );
return 0;
} | .text
.file "main.hip"
.globl _Z18__device_stub__addPdS_ii # -- Begin function _Z18__device_stub__addPdS_ii
.p2align 4, 0x90
.type _Z18__device_stub__addPdS_ii,@function
_Z18__device_stub__addPdS_ii: # @_Z18__device_stub__addPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdS_ii, .Lfunc_end0-_Z18__device_stub__addPdS_ii
.cfi_endproc
# -- End function
.globl _Z11fillRandArrPdii # -- Begin function _Z11fillRandArrPdii
.p2align 4, 0x90
.type _Z11fillRandArrPdii,@function
_Z11fillRandArrPdii: # @_Z11fillRandArrPdii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movslq %eax, %rsi
imulq $1374389535, %rsi, %rax # imm = 0x51EB851F
movq %rax, %rcx
shrq $63, %rcx
sarq $37, %rax
addl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %esi
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
movsd %xmm0, (%r14,%r15,8)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge19
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11fillRandArrPdii, .Lfunc_end1-_Z11fillRandArrPdii
.cfi_endproc
# -- End function
.globl _Z15formExpandedArrPdS_ii # -- Begin function _Z15formExpandedArrPdS_ii
.p2align 4, 0x90
.type _Z15formExpandedArrPdS_ii,@function
_Z15formExpandedArrPdS_ii: # @_Z15formExpandedArrPdS_ii
.cfi_startproc
# %bb.0:
# kill: def $ecx killed $ecx def $rcx
# kill: def $edx killed $edx def $rdx
movsd (%rdi), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsi)
movl %ecx, %r8d
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 8(%rsi,%rax,8)
incq %rax
cmpq %rax, %r8
jne .LBB2_2
.LBB2_3: # %._crit_edge
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq %ecx, %rax
movsd -8(%rdi,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 8(%rsi,%rax,8)
testl %edx, %edx
jle .LBB2_6
# %bb.4: # %.lr.ph93
leaq 16(,%rax,8), %r9
movl %edx, %r10d
leaq (,%rax,8), %r11
leaq (%r11,%rax,8), %r11
addq $16, %r11
addq %rsi, %r11
addq $8, %r11
movl %ecx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movslq %ebx, %rbx
movsd -8(%rdi,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r11)
addq %r9, %r11
addl %ecx, %ebx
decq %r10
jne .LBB2_5
.LBB2_6: # %._crit_edge94
leal 1(%rdx), %r9d
leal -1(%rdx), %r11d
imull %ecx, %r11d
movl %ecx, %r10d
imull %edx, %r10d
movslq %r10d, %r10
movsd -8(%rdi,%r10,8), %xmm0 # xmm0 = mem[0],zero
leal 2(%rcx), %r10d
movl %r10d, %ebx
imull %r9d, %ebx
leal (%rbx,%rcx), %ebp
movslq %ebp, %r14
movsd %xmm0, 8(%rsi,%r14,8)
movslq %r11d, %r11
movslq %ebx, %rbx
testl %ecx, %ecx
jle .LBB2_9
# %bb.7: # %.lr.ph100.preheader
leaq (%rsi,%rbx,8), %r14
addq $8, %r14
leaq (%rdi,%r11,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_8: # %.lr.ph100
# =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r14,%r12,8)
incq %r12
cmpq %r12, %r8
jne .LBB2_8
.LBB2_9: # %._crit_edge101
movsd (%rdi,%r11,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsi,%rbx,8)
movslq %r10d, %r8
movl %r9d, %r9d
testl %edx, %edx
jle .LBB2_12
# %bb.10: # %.lr.ph105.preheader
leaq (,%r8,8), %r10
leaq (%rsi,%r8,8), %r11
leaq (,%rax,8), %rbx
leaq -1(%r9), %r14
movq %rdi, %r15
.p2align 4, 0x90
.LBB2_11: # %.lr.ph105
# =>This Inner Loop Header: Depth=1
movsd (%r15), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r11)
addq %r10, %r11
addq %rbx, %r15
decq %r14
jne .LBB2_11
.LBB2_12: # %.preheader83
testl %edx, %edx
jle .LBB2_18
# %bb.13: # %.preheader.lr.ph
leal 1(%rcx), %edx
leaq (%rsi,%r8,8), %rsi
addq $8, %rsi
shlq $3, %r8
shlq $3, %rax
decq %rdx
movl $1, %r10d
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_17: # %._crit_edge111
# in Loop: Header=BB2_14 Depth=1
incq %r10
addq %r8, %rsi
addq %rax, %rdi
cmpq %r9, %r10
je .LBB2_18
.LBB2_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_16 Depth 2
testl %ecx, %ecx
jle .LBB2_17
# %bb.15: # %.lr.ph110
# in Loop: Header=BB2_14 Depth=1
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_16: # Parent Loop BB2_14 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r11,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsi,%r11,8)
incq %r11
cmpq %r11, %rdx
jne .LBB2_16
jmp .LBB2_17
.LBB2_18: # %._crit_edge114
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15formExpandedArrPdS_ii, .Lfunc_end2-_Z15formExpandedArrPdS_ii
.cfi_endproc
# -- End function
.globl _Z8printArrPdii # -- Begin function _Z8printArrPdii
.p2align 4, 0x90
.type _Z8printArrPdii,@function
_Z8printArrPdii: # @_Z8printArrPdii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
cvttsd2si (%r14,%r15,8), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z8printArrPdii, .Lfunc_end3-_Z8printArrPdii
.cfi_endproc
# -- End function
.globl _Z20printVerificationArrPdiii # -- Begin function _Z20printVerificationArrPdiii
.p2align 4, 0x90
.type _Z20printVerificationArrPdiii,@function
_Z20printVerificationArrPdiii: # @_Z20printVerificationArrPdiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 32(%rsp) # 8-byte Spill
movl %esi, 28(%rsp) # 4-byte Spill
testl %esi, %esi
jle .LBB4_10
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
addl $2, %ecx
movslq %ecx, %r15
shlq $3, %r15
movl $0, 12(%rsp) # 4-byte Folded Spill
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_9: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rcx # 8-byte Reload
incl %ecx
addl $2, 12(%rsp) # 4-byte Folded Spill
movq %rcx, %rax
movq %rcx, 16(%rsp) # 8-byte Spill
cmpl 28(%rsp), %ecx # 4-byte Folded Reload
je .LBB4_10
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
# Child Loop BB4_5 Depth 3
# Child Loop BB4_6 Depth 4
testl %ebx, %ebx
jle .LBB4_9
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movslq 12(%rsp), %r14 # 4-byte Folded Reload
movq %r15, %rbp
imulq %r14, %rbp
addq 32(%rsp), %rbp # 8-byte Folded Reload
movq 16(%rsp), %rax # 8-byte Reload
leal 4(,%rax,2), %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_5 Depth 3
# Child Loop BB4_6 Depth 4
movq %rbp, %rcx
movq %r14, %rdx
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_5: # Parent Loop BB4_2 Depth=1
# Parent Loop BB4_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_6 Depth 4
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_2 Depth=1
# Parent Loop BB4_4 Depth=2
# Parent Loop BB4_5 Depth=3
# => This Inner Loop Header: Depth=4
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd (%rcx,%rsi,8), %xmm0
cvttsd2si %xmm0, %eax
incq %rsi
cmpq $4, %rsi
jne .LBB4_6
# %bb.7: # in Loop: Header=BB4_5 Depth=3
incq %rdx
addq %r15, %rcx
cmpl %edx, %r12d
ja .LBB4_5
# %bb.8: # in Loop: Header=BB4_4 Depth=2
leal 15(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $4, %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incl %r13d
addq $16, %rbp
cmpl %ebx, %r13d
jne .LBB4_4
jmp .LBB4_9
.LBB4_10: # %._crit_edge39
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z20printVerificationArrPdiii, .Lfunc_end4-_Z20printVerificationArrPdiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $216, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl D(%rip), %eax
cvtsi2sd %rax, %xmm0
callq exp2@PLT
cvttsd2si %xmm0, %r14d
movl S(%rip), %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
callq exp2@PLT
cvttsd2si %xmm0, %r15d
movl D(%rip), %eax
decl %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
callq exp2@PLT
cvttsd2si %xmm0, %ebx
movl S(%rip), %eax
decl %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
callq exp2@PLT
cvttsd2si %xmm0, %r12d
leal 2(%r14), %eax
leal 2(%r15), %ecx
imull %eax, %ecx
movslq %ecx, %rsi
shlq $3, %rsi
leaq -128(%rbp), %rdi
callq hipMalloc
movl %r12d, -44(%rbp) # 4-byte Spill
movl %r12d, %eax
movl %ebx, -60(%rbp) # 4-byte Spill
imull %ebx, %eax
movslq %eax, %rsi
shlq $3, %rsi
leaq -120(%rbp), %rdi
callq hipMalloc
movq %rsp, -144(%rbp) # 8-byte Spill
movl %r15d, %eax
imull %r14d, %eax
leaq 15(,%rax,8), %rax
andq $-16, %rax
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -104(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %r14, -56(%rbp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB5_6
# %bb.1: # %.preheader.lr.ph.i
movl -56(%rbp), %eax # 4-byte Reload
movq %rax, -80(%rbp) # 8-byte Spill
movl %r15d, %r14d
movl $0, -72(%rbp) # 4-byte Folded Spill
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %._crit_edge.i
# in Loop: Header=BB5_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
movq %r12, %r15
addl %r15d, -72(%rbp) # 4-byte Folded Spill
cmpq -80(%rbp), %r13 # 8-byte Folded Reload
je .LBB5_6
.LBB5_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
movq %r15, %r12
testl %r15d, %r15d
jle .LBB5_5
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB5_2 Depth=1
movl -72(%rbp), %eax # 4-byte Reload
movq -104(%rbp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movslq %eax, %rsi
imulq $1374389535, %rsi, %rax # imm = 0x51EB851F
movq %rax, %rcx
shrq $63, %rcx
sarq $37, %rax
addl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %esi
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
movsd %xmm0, (%rbx,%r15,8)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB5_4
jmp .LBB5_5
.LBB5_6: # %_Z11fillRandArrPdii.exit
movl $10, %edi
callq putchar@PLT
cmpl $0, N(%rip)
movq -56(%rbp), %r13 # 8-byte Reload
movl -44(%rbp), %r14d # 4-byte Reload
jne .LBB5_7
.LBB5_44: # %._crit_edge127
movq -128(%rbp), %rdi
callq hipFree
movq -120(%rbp), %rdi
callq hipFree
movq -144(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.p2align 4, 0x90
.LBB5_43: # %_Z8printArrPdii.exit106
# in Loop: Header=BB5_7 Depth=1
.cfi_def_cfa %rbp, 16
cvttsd2si -56(%rbp), %ebx # 8-byte Folded Reload
cvttsd2si -88(%rbp), %r14d # 8-byte Folded Reload
movl $10, %edi
callq putchar@PLT
decl N(%rip)
movq -152(%rbp), %rsp # 8-byte Reload
cmpl $0, N(%rip)
movl -60(%rbp), %eax # 4-byte Reload
movl %eax, %r13d
movl %r12d, %r15d
movl %ebx, -60(%rbp) # 4-byte Spill
je .LBB5_44
.LBB5_7: # =>This Loop Header: Depth=1
# Child Loop BB5_9 Depth 2
# Child Loop BB5_11 Depth 3
# Child Loop BB5_17 Depth 2
# Child Loop BB5_19 Depth 3
# Child Loop BB5_23 Depth 2
# Child Loop BB5_25 Depth 3
# Child Loop BB5_26 Depth 4
# Child Loop BB5_27 Depth 5
# Child Loop BB5_34 Depth 2
# Child Loop BB5_39 Depth 2
# Child Loop BB5_41 Depth 3
movl %r14d, -44(%rbp) # 4-byte Spill
movq %rsp, -152(%rbp) # 8-byte Spill
leal 2(%r13), %ebx
leal 2(%r15), %eax
movl %ebx, %ecx
movl %eax, -56(%rbp) # 4-byte Spill
imull %eax, %ecx
movq %rcx, -96(%rbp) # 8-byte Spill
leaq 15(,%rcx,8), %rax
andq $-16, %rax
movq %rsp, %rsi
subq %rax, %rsi
movq %rsi, %rsp
movq -104(%rbp), %rdi # 8-byte Reload
movq %rsi, -112(%rbp) # 8-byte Spill
movl %r13d, %edx
movq %r15, -72(%rbp) # 8-byte Spill
movl %r15d, %ecx
callq _Z15formExpandedArrPdS_ii
cmpl $-1, %r13d
jl .LBB5_13
# %bb.8: # %.preheader.lr.ph.i61
# in Loop: Header=BB5_7 Depth=1
movl %ebx, %eax
movq %rax, -80(%rbp) # 8-byte Spill
movl -56(%rbp), %r13d # 4-byte Reload
xorl %ebx, %ebx
xorl %r15d, %r15d
jmp .LBB5_9
.p2align 4, 0x90
.LBB5_12: # %._crit_edge.i63
# in Loop: Header=BB5_9 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r15
addl -56(%rbp), %ebx # 4-byte Folded Reload
cmpq -80(%rbp), %r15 # 8-byte Folded Reload
je .LBB5_13
.LBB5_9: # %.preheader.i62
# Parent Loop BB5_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_11 Depth 3
cmpl $-1, -72(%rbp) # 4-byte Folded Reload
jl .LBB5_12
# %bb.10: # %.lr.ph.i64
# in Loop: Header=BB5_9 Depth=2
movl %ebx, %eax
movq -112(%rbp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_11: # Parent Loop BB5_7 Depth=1
# Parent Loop BB5_9 Depth=2
# => This Inner Loop Header: Depth=3
cvttsd2si (%r12,%r14,8), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r13
jne .LBB5_11
jmp .LBB5_12
.p2align 4, 0x90
.LBB5_13: # %_Z8printArrPdii.exit
# in Loop: Header=BB5_7 Depth=1
movl $10, %edi
callq putchar@PLT
movq -128(%rbp), %rdi
movslq -96(%rbp), %rdx # 4-byte Folded Reload
shlq $3, %rdx
movq -112(%rbp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl -60(%rbp), %r13d # 4-byte Reload
movl %r13d, %edi
movq %rdi, -72(%rbp) # 8-byte Spill
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl -44(%rbp), %r12d # 4-byte Reload
movl %r12d, %ebx
movq %rbx, %rdx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_15
# %bb.14: # in Loop: Header=BB5_7 Depth=1
movq -128(%rbp), %rax
movq -120(%rbp), %rcx
movq %rax, -216(%rbp)
movq %rcx, -208(%rbp)
movl -56(%rbp), %eax # 4-byte Reload
movl %eax, -136(%rbp)
movl %r12d, -132(%rbp)
leaq -216(%rbp), %rax
movq %rax, -256(%rbp)
leaq -208(%rbp), %rax
movq %rax, -248(%rbp)
leaq -136(%rbp), %rax
movq %rax, -240(%rbp)
leaq -132(%rbp), %rax
movq %rax, -232(%rbp)
leaq -200(%rbp), %rdi
leaq -184(%rbp), %rsi
leaq -168(%rbp), %rdx
leaq -160(%rbp), %rcx
callq __hipPopCallConfiguration
movq -200(%rbp), %rsi
movl -192(%rbp), %edx
movq -184(%rbp), %rcx
movl -176(%rbp), %r8d
movl $_Z3addPdS_ii, %edi
leaq -256(%rbp), %r9
pushq -160(%rbp)
pushq -168(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB5_15: # in Loop: Header=BB5_7 Depth=1
movq %rbx, -80(%rbp) # 8-byte Spill
callq hipDeviceSynchronize
movl %r13d, %eax
imull %r12d, %eax
leaq 15(,%rax,8), %rcx
andq $-16, %rcx
movq %rsp, %rdi
subq %rcx, %rdi
movq %rdi, %rsp
movq -120(%rbp), %rsi
movslq %eax, %rdx
shlq $3, %rdx
movq %rdi, -96(%rbp) # 8-byte Spill
movl $2, %ecx
callq hipMemcpy
testl %r13d, %r13d
movl %r13d, -60(%rbp) # 4-byte Spill
jle .LBB5_31
# %bb.16: # %.preheader.lr.ph.i70
# in Loop: Header=BB5_7 Depth=1
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB5_17
.p2align 4, 0x90
.LBB5_20: # %._crit_edge.i74
# in Loop: Header=BB5_17 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r14
movl -44(%rbp), %r12d # 4-byte Reload
addl %r12d, %ebx
cmpq -72(%rbp), %r14 # 8-byte Folded Reload
je .LBB5_21
.LBB5_17: # %.preheader.i72
# Parent Loop BB5_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_19 Depth 3
testl %r12d, %r12d
movq -80(%rbp), %r13 # 8-byte Reload
jle .LBB5_20
# %bb.18: # %.lr.ph.i78
# in Loop: Header=BB5_17 Depth=2
movl %ebx, %eax
movq -96(%rbp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_19: # Parent Loop BB5_7 Depth=1
# Parent Loop BB5_17 Depth=2
# => This Inner Loop Header: Depth=3
cvttsd2si (%r15,%r12,8), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB5_19
jmp .LBB5_20
.p2align 4, 0x90
.LBB5_21: # %_Z8printArrPdii.exit83
# in Loop: Header=BB5_7 Depth=1
movl $10, %edi
callq putchar@PLT
movl -60(%rbp), %r13d # 4-byte Reload
testl %r13d, %r13d
jle .LBB5_32
# %bb.22: # %.preheader.lr.ph.i84
# in Loop: Header=BB5_7 Depth=1
movslq -56(%rbp), %r15 # 4-byte Folded Reload
shlq $3, %r15
movl $0, -88(%rbp) # 4-byte Folded Spill
xorl %eax, %eax
movq %rax, -56(%rbp) # 8-byte Spill
jmp .LBB5_23
.p2align 4, 0x90
.LBB5_30: # %._crit_edge.i86
# in Loop: Header=BB5_23 Depth=2
movl $10, %edi
callq putchar@PLT
movq -56(%rbp), %rcx # 8-byte Reload
incl %ecx
addl $2, -88(%rbp) # 4-byte Folded Spill
movl -60(%rbp), %r13d # 4-byte Reload
movq %rcx, %rax
movq %rcx, -56(%rbp) # 8-byte Spill
cmpl %r13d, %ecx
movl -44(%rbp), %r12d # 4-byte Reload
je .LBB5_32
.LBB5_23: # %.preheader.i85
# Parent Loop BB5_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_25 Depth 3
# Child Loop BB5_26 Depth 4
# Child Loop BB5_27 Depth 5
testl %r12d, %r12d
jle .LBB5_30
# %bb.24: # %.lr.ph.i88
# in Loop: Header=BB5_23 Depth=2
movslq -88(%rbp), %r13 # 4-byte Folded Reload
movq %r15, %r14
imulq %r13, %r14
addq -112(%rbp), %r14 # 8-byte Folded Reload
movq -56(%rbp), %rax # 8-byte Reload
leal 4(,%rax,2), %r12d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_25: # Parent Loop BB5_7 Depth=1
# Parent Loop BB5_23 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB5_26 Depth 4
# Child Loop BB5_27 Depth 5
movq %r14, %rcx
movq %r13, %rdx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_26: # Parent Loop BB5_7 Depth=1
# Parent Loop BB5_23 Depth=2
# Parent Loop BB5_25 Depth=3
# => This Loop Header: Depth=4
# Child Loop BB5_27 Depth 5
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_27: # Parent Loop BB5_7 Depth=1
# Parent Loop BB5_23 Depth=2
# Parent Loop BB5_25 Depth=3
# Parent Loop BB5_26 Depth=4
# => This Inner Loop Header: Depth=5
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
addsd (%rcx,%rsi,8), %xmm0
cvttsd2si %xmm0, %eax
incq %rsi
cmpq $4, %rsi
jne .LBB5_27
# %bb.28: # in Loop: Header=BB5_26 Depth=4
incq %rdx
addq %r15, %rcx
cmpl %edx, %r12d
ja .LBB5_26
# %bb.29: # in Loop: Header=BB5_25 Depth=3
leal 15(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $4, %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incl %ebx
addq $16, %r14
cmpl -44(%rbp), %ebx # 4-byte Folded Reload
jne .LBB5_25
jmp .LBB5_30
.p2align 4, 0x90
.LBB5_31: # %_Z20printVerificationArrPdiii.exit.critedge
# in Loop: Header=BB5_7 Depth=1
movl $10, %edi
callq putchar@PLT
.LBB5_32: # %_Z20printVerificationArrPdiii.exit
# in Loop: Header=BB5_7 Depth=1
movl D(%rip), %eax
leal -1(%rax), %ecx
decl S(%rip)
movl %ecx, D(%rip)
addl $-2, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
callq exp2@PLT
movsd %xmm0, -56(%rbp) # 8-byte Spill
movl S(%rip), %eax
decl %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
callq exp2@PLT
movsd %xmm0, -88(%rbp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB5_37
# %bb.33: # %.preheader.lr.ph
# in Loop: Header=BB5_7 Depth=1
movq -80(%rbp), %rax # 8-byte Reload
leaq (,%rax,8), %r15
xorl %ebx, %ebx
movq -72(%rbp), %r14 # 8-byte Reload
jmp .LBB5_34
.p2align 4, 0x90
.LBB5_36: # %._crit_edge
# in Loop: Header=BB5_34 Depth=2
addl %r12d, %ebx
decq %r14
je .LBB5_37
.LBB5_34: # %.preheader
# Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
testl %r12d, %r12d
jle .LBB5_36
# %bb.35: # %.lr.ph
# in Loop: Header=BB5_34 Depth=2
movl %ebx, %eax
movq -96(%rbp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rsi
movq -104(%rbp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rdi
movq %r15, %rdx
callq memcpy@PLT
jmp .LBB5_36
.p2align 4, 0x90
.LBB5_37: # %._crit_edge118
# in Loop: Header=BB5_7 Depth=1
movl $.Lstr, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB5_43
# %bb.38: # %.preheader.lr.ph.i93
# in Loop: Header=BB5_7 Depth=1
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB5_39
.p2align 4, 0x90
.LBB5_42: # %._crit_edge.i97
# in Loop: Header=BB5_39 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r14
movl -44(%rbp), %r12d # 4-byte Reload
addl %r12d, %ebx
cmpq -72(%rbp), %r14 # 8-byte Folded Reload
je .LBB5_43
.LBB5_39: # %.preheader.i95
# Parent Loop BB5_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_41 Depth 3
testl %r12d, %r12d
movq -80(%rbp), %r13 # 8-byte Reload
jle .LBB5_42
# %bb.40: # %.lr.ph.i101
# in Loop: Header=BB5_39 Depth=2
movl %ebx, %eax
movq -104(%rbp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_41: # Parent Loop BB5_7 Depth=1
# Parent Loop BB5_39 Depth=2
# => This Inner Loop Header: Depth=3
cvttsd2si (%r15,%r12,8), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB5_41
jmp .LBB5_42
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 1 # 0x1
.size N, 4
.type S,@object # @S
.globl S
.p2align 2, 0x0
S:
.long 4 # 0x4
.size S, 4
.type D,@object # @D
.globl D
.p2align 2, 0x0
D:
.long 3 # 0x3
.size D, 4
.type _Z3addPdS_ii,@object # @_Z3addPdS_ii
.section .rodata,"a",@progbits
.globl _Z3addPdS_ii
.p2align 3, 0x0
_Z3addPdS_ii:
.quad _Z18__device_stub__addPdS_ii
.size _Z3addPdS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPdS_ii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "New Array:"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R16, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff107435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ SHF.L.U32 R2, R17, 0x1, RZ ; /* 0x0000000111027819 */
/* 0x001fe400000006ff */
/*0060*/ SHF.L.U32 R3, R0, 0x1, RZ ; /* 0x0000000100037819 */
/* 0x002fca00000006ff */
/*0070*/ IMAD R3, R2, c[0x0][0x170], R3 ; /* 0x00005c0002037a24 */
/* 0x000fc800078e0203 */
/*0080*/ IMAD.WIDE R22, R3, R16, c[0x0][0x160] ; /* 0x0000580003167625 */
/* 0x000fca00078e0210 */
/*0090*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R22.64+0x8] ; /* 0x00000804160a7981 */
/* 0x000ee8000c1e1b00 */
/*00b0*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x00001004160c7981 */
/* 0x000128000c1e1b00 */
/*00c0*/ LDG.E.64 R20, [R22.64+0x18] ; /* 0x0000180416147981 */
/* 0x0000e2000c1e1b00 */
/*00d0*/ IMAD.WIDE R28, R16, c[0x0][0x170], R22 ; /* 0x00005c00101c7a25 */
/* 0x000fca00078e0216 */
/*00e0*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0008e8000c1e1b00 */
/*00f0*/ LDG.E.64 R2, [R28.64+0x8] ; /* 0x000008041c027981 */
/* 0x0008e8000c1e1b00 */
/*0100*/ LDG.E.64 R4, [R28.64+0x10] ; /* 0x000010041c047981 */
/* 0x0008e8000c1e1b00 */
/*0110*/ LDG.E.64 R6, [R28.64+0x18] ; /* 0x000018041c067981 */
/* 0x0008e2000c1e1b00 */
/*0120*/ IMAD.WIDE R18, R16, c[0x0][0x170], R28 ; /* 0x00005c0010127a25 */
/* 0x000fe200078e021c */
/*0130*/ DADD R24, RZ, R8 ; /* 0x00000000ff187229 */
/* 0x0042880000000008 */
/*0140*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x00236c000c1e1b00 */
/*0150*/ F2I.F64.TRUNC R24, R24 ; /* 0x0000001800187311 */
/* 0x004eb0000030d100 */
/*0160*/ I2F.F64 R26, R24 ; /* 0x00000018001a7312 */
/* 0x004ee40000201c00 */
/*0170*/ DADD R26, R10, R26 ; /* 0x000000000a1a7229 */
/* 0x0084c4000000001a */
/*0180*/ LDG.E.64 R10, [R18.64+0x8] ; /* 0x00000804120a7981 */
/* 0x0042b0000c1e1b00 */
/*0190*/ F2I.F64.TRUNC R26, R26 ; /* 0x0000001a001a7311 */
/* 0x008e30000030d100 */
/*01a0*/ I2F.F64 R22, R26 ; /* 0x0000001a00167312 */
/* 0x001f240000201c00 */
/*01b0*/ DADD R28, R12, R22 ; /* 0x000000000c1c7229 */
/* 0x0100c40000000016 */
/*01c0*/ LDG.E.64 R12, [R18.64+0x10] ; /* 0x00001004120c7981 */
/* 0x001330000c1e1b00 */
/*01d0*/ F2I.F64.TRUNC R28, R28 ; /* 0x0000001c001c7311 */
/* 0x008e30000030d100 */
/*01e0*/ I2F.F64 R22, R28 ; /* 0x0000001c00167312 */
/* 0x001e240000201c00 */
/*01f0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0010c40000000016 */
/*0200*/ LDG.E.64 R20, [R18.64+0x18] ; /* 0x0000180412147981 */
/* 0x001330000c1e1b00 */
/*0210*/ F2I.F64.TRUNC R22, R22 ; /* 0x0000001600167311 */
/* 0x008e30000030d100 */
/*0220*/ I2F.F64 R24, R22 ; /* 0x0000001600187312 */
/* 0x0010e40000201c00 */
/*0230*/ IMAD.WIDE R22, R16, c[0x0][0x170], R18 ; /* 0x00005c0010167a25 */
/* 0x001fe200078e0212 */
/*0240*/ DADD R24, R14, R24 ; /* 0x000000000e187229 */
/* 0x0080c80000000018 */
/*0250*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x001f2c000c1e1b00 */
/*0260*/ F2I.F64.TRUNC R24, R24 ; /* 0x0000001800187311 */
/* 0x008e30000030d100 */
/*0270*/ I2F.F64 R26, R24 ; /* 0x00000018001a7312 */
/* 0x001e240000201c00 */
/*0280*/ DADD R26, R2, R26 ; /* 0x00000000021a7229 */
/* 0x0010c4000000001a */
/*0290*/ LDG.E.64 R2, [R22.64+0x8] ; /* 0x0000080416027981 */
/* 0x001f30000c1e1b00 */
/*02a0*/ F2I.F64.TRUNC R26, R26 ; /* 0x0000001a001a7311 */
/* 0x008e70000030d100 */
/*02b0*/ I2F.F64 R18, R26 ; /* 0x0000001a00127312 */
/* 0x002e240000201c00 */
/*02c0*/ DADD R18, R4, R18 ; /* 0x0000000004127229 */
/* 0x0010440000000012 */
/*02d0*/ LDG.E.64 R4, [R22.64+0x10] ; /* 0x0000100416047981 */
/* 0x001ef0000c1e1b00 */
/*02e0*/ F2I.F64.TRUNC R18, R18 ; /* 0x0000001200127311 */
/* 0x002e30000030d100 */
/*02f0*/ I2F.F64 R28, R18 ; /* 0x00000012001c7312 */
/* 0x001e240000201c00 */
/*0300*/ DADD R28, R6, R28 ; /* 0x00000000061c7229 */
/* 0x001044000000001c */
/*0310*/ LDG.E.64 R6, [R22.64+0x18] ; /* 0x0000180416067981 */
/* 0x001ee2000c1e1b00 */
/*0320*/ IMAD R17, R17, c[0x0][0x174], R0 ; /* 0x00005d0011117a24 */
/* 0x000fc800078e0200 */
/*0330*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc600078e0210 */
/*0340*/ F2I.F64.TRUNC R28, R28 ; /* 0x0000001c001c7311 */
/* 0x002e30000030d100 */
/*0350*/ I2F.F64 R24, R28 ; /* 0x0000001c00187312 */
/* 0x001f640000201c00 */
/*0360*/ DADD R8, R8, R24 ; /* 0x0000000008087229 */
/* 0x020e140000000018 */
/*0370*/ F2I.F64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x001e30000030d100 */
/*0380*/ I2F.F64 R24, R8 ; /* 0x0000000800187312 */
/* 0x001ea40000201c00 */
/*0390*/ DADD R10, R10, R24 ; /* 0x000000000a0a7229 */
/* 0x004e140000000018 */
/*03a0*/ F2I.F64.TRUNC R10, R10 ; /* 0x0000000a000a7311 */
/* 0x001e30000030d100 */
/*03b0*/ I2F.F64 R18, R10 ; /* 0x0000000a00127312 */
/* 0x001f240000201c00 */
/*03c0*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x010e140000000012 */
/*03d0*/ F2I.F64.TRUNC R12, R12 ; /* 0x0000000c000c7311 */
/* 0x001e30000030d100 */
/*03e0*/ I2F.F64 R18, R12 ; /* 0x0000000c00127312 */
/* 0x001e240000201c00 */
/*03f0*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x001e140000000012 */
/*0400*/ F2I.F64.TRUNC R18, R18 ; /* 0x0000001200127311 */
/* 0x001e30000030d100 */
/*0410*/ I2F.F64 R20, R18 ; /* 0x0000001200147312 */
/* 0x001e240000201c00 */
/*0420*/ DADD R14, R14, R20 ; /* 0x000000000e0e7229 */
/* 0x001e140000000014 */
/*0430*/ F2I.F64.TRUNC R14, R14 ; /* 0x0000000e000e7311 */
/* 0x001e30000030d100 */
/*0440*/ I2F.F64 R8, R14 ; /* 0x0000000e00087312 */
/* 0x001e240000201c00 */
/*0450*/ DADD R2, R2, R8 ; /* 0x0000000002027229 */
/* 0x001e140000000008 */
/*0460*/ F2I.F64.TRUNC R2, R2 ; /* 0x0000000200027311 */
/* 0x001e30000030d100 */
/*0470*/ I2F.F64 R8, R2 ; /* 0x0000000200087312 */
/* 0x001ee40000201c00 */
/*0480*/ DADD R4, R4, R8 ; /* 0x0000000004047229 */
/* 0x008e140000000008 */
/*0490*/ F2I.F64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x001e30000030d100 */
/*04a0*/ I2F.F64 R8, R4 ; /* 0x0000000400087312 */
/* 0x001e240000201c00 */
/*04b0*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e140000000008 */
/*04c0*/ F2I.F64.TRUNC R6, R6 ; /* 0x0000000600067311 */
/* 0x001e24000030d100 */
/*04d0*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x001fc80000011406 */
/*04e0*/ LEA.HI R9, R9, R6, RZ, 0x4 ; /* 0x0000000609097211 */
/* 0x000fc800078f20ff */
/*04f0*/ SHF.R.S32.HI R9, RZ, 0x4, R9 ; /* 0x00000004ff097819 */
/* 0x000fcc0000011409 */
/*0500*/ I2F.F64 R8, R9 ; /* 0x0000000900087312 */
/* 0x000e240000201c00 */
/*0510*/ STG.E.64 [R16.64], R8 ; /* 0x0000000810007986 */
/* 0x001fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_ii
.globl _Z3addPdS_ii
.p2align 8
.type _Z3addPdS_ii,@function
_Z3addPdS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
v_mov_b32_e32 v3, 0
s_lshl_b32 s8, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s8, 3
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s15, s6
v_lshl_add_u32 v1, s4, 1, v1
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b64 s[4:5], 0
v_lshlrev_b64 v[4:5], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f64_i32_e32 v[7:8], v3
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
global_load_b64 v[5:6], v[5:6], off
s_cmp_eq_u32 s4, 32
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v3, v[5:6]
s_cbranch_scc0 .LBB0_2
v_add_nc_u32_e32 v1, s6, v1
s_add_i32 s4, s8, 1
s_cmp_ge_i32 s8, s7
s_cbranch_scc1 .LBB0_5
s_mov_b32 s8, s4
s_branch .LBB0_1
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x8
v_lshrrev_b32_e32 v1, 28, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v3, v1
v_ashrrev_i32_e32 v1, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[1:2], v1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_ii, .Lfunc_end0-_Z3addPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ==========================================================================
// $Id$
// ==========================================================================
// (C)opyright: 2009-2010
//
// Ulm University
//
// Creator: Hendrik Lensch
// Email: {hendrik.lensch,johannes.hanika}@uni-ulm.de
// ==========================================================================
// $Log$
// ==========================================================================
#include <stdio.h>
#include <vector_types.h>
#include <stdlib.h>
using namespace std;
#define MAX_BLOCKS 256
#define MAX_THREADS 128
#define RTEST // use random initialization of array
/* compute the dot product between a1 and a2. a1 and a2 are of size
dim. The result of each thread should be stored in _dst[blockIdx.x *
blockDim.x + threadIdx.x]. Each thread should accumulate the dot
product of a subset of elements.
*/__global__ void dotProdKernel(float *_dst, const float* _a1, const float* _a2,
int _dim)
{
// program your kernel here
float result = 0.f;
const int thread_index = blockIdx.x * blockDim.x + threadIdx.x;
int elements_per_thread = (_dim + MAX_BLOCKS*MAX_THREADS -1 ) / (MAX_BLOCKS*MAX_THREADS);
int begin = thread_index * elements_per_thread;
int end = begin + elements_per_thread;
if(end > _dim)
end = _dim;
for(int i=begin; i<end; i++)
{
result += _a1[i] * _a2[i];
}
_dst[thread_index] = result;
}
/* This program sets up two large arrays of size dim and computes the
dot product of both arrays.
The arrays are uploaed only once and the dot product is computed
multiple times. While this does not make too much sense it
demonstrated the possible speedup. */
int main(int argc, char* argv[])
{
// parse command line
int acount = 1;
if (argc < 3)
{
printf("usage: testDotProduct <dim> <GPU-flag [0,1]>\n");
exit(1);
}
// number of elements in both vectors
int dim = atoi(argv[acount++]);
// flag indicating weather the CPU or the GPU version should be executed
bool gpuVersion = atoi(argv[acount++]);
printf("dim: %d\n", dim);
float* cpuArray1 = new float[dim];
float* cpuArray2 = new float[dim];
// initialize the two arrays (either random or deterministic)
for (int i = 0; i < dim; ++i)
{
#ifdef RTEST
cpuArray1[i] = drand48();
cpuArray2[i] = drand48();
#else
cpuArray1[i] = 2.0;
cpuArray2[i] = i % 10;
#endif
}
// now the gpu stuff
float* gpuArray1;
float* gpuArray2;
float* gpuResult;
float* h;
if (gpuVersion)
{
const size_t input_size = dim * sizeof(float);
const size_t output_size = MAX_BLOCKS * MAX_THREADS * sizeof(float);
cudaMalloc((void**) &gpuArray1, input_size);
cudaMalloc((void**) &gpuArray2, input_size);
cudaMalloc((void**) &gpuResult, output_size);
cudaMemcpy(gpuArray1, cpuArray1, input_size,
cudaMemcpyHostToDevice);
cudaMemcpy(gpuArray2, cpuArray2, input_size,
cudaMemcpyHostToDevice);
// allocate an array to download the results of all threads
h = new float[MAX_BLOCKS * MAX_THREADS];
}
const int num_iters = 100;
double finalDotProduct;
if (!gpuVersion)
{
printf("cpu: ");
for (int iter = 0; iter < num_iters; ++iter)
{
finalDotProduct = 0.0;
for (int i = 0; i < dim; ++i)
{
finalDotProduct += cpuArray1[i] * cpuArray2[i];
}
}
}
else
{
// Cuda version here
printf("gpu: ");
// a simplistic way of splitting the problem into threads
dim3 blockGrid(MAX_BLOCKS);
dim3 threadBlock(MAX_THREADS);
for (int iter = 0; iter < num_iters; ++iter)
{
dotProdKernel<<<blockGrid, threadBlock>>>(gpuResult, gpuArray1,
gpuArray2, dim);
cudaThreadSynchronize();
}
// download and combine the results of multiple threads on the CPU
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
cudaMemcpy(h, gpuResult, MAX_BLOCKS * MAX_THREADS * sizeof(float), cudaMemcpyDeviceToHost);
finalDotProduct = 0.f;
for(int i=0; i<MAX_BLOCKS * MAX_THREADS; ++i)
finalDotProduct += h[i];
}
printf("Result: %f\n", finalDotProduct);
if (gpuVersion)
{
// cleanup GPU memory
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
delete[] h;
}
delete[] cpuArray2;
delete[] cpuArray1;
printf("done\n");
} | code for sm_80
Function : _Z13dotProdKernelPfPKfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0xa60 ; /* 0x00000a2000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, UR4, 0x7fff, URZ ; /* 0x00007fff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0070*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fc80008011404 */
/*0080*/ ULEA.HI UR5, UR5, UR4, URZ, 0xf ; /* 0x0000000405057291 */
/* 0x000fc8000f8f783f */
/*0090*/ USHF.R.S32.HI UR5, URZ, 0xf, UR5 ; /* 0x0000000f3f057899 */
/* 0x000fe20008011405 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00b0*/ IMAD R9, R0, UR5, RZ ; /* 0x0000000500097c24 */
/* 0x000fca000f8e02ff */
/*00c0*/ IADD3 R6, R9, UR5, RZ ; /* 0x0000000509067c10 */
/* 0x000fe2000fffe0ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMNMX R6, R6, c[0x0][0x178], PT ; /* 0x00005e0006067a17 */
/* 0x000fc80003800200 */
/*00f0*/ ISETP.GE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fda0003f06270 */
/*0100*/ @P0 BRA 0xa50 ; /* 0x0000094000000947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R2, -R9, R6.reuse, RZ ; /* 0x0000000609027210 */
/* 0x080fe20007ffe1ff */
/*0120*/ BSSY B1, 0x2d0 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0130*/ LOP3.LUT R4, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff047212 */
/* 0x000fe200078e33ff */
/*0140*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0150*/ LOP3.LUT P1, R7, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302077812 */
/* 0x000fe4000782c0ff */
/*0160*/ IADD3 R4, -R4, -0x2, -R9 ; /* 0xfffffffe04047810 */
/* 0x000fc80007ffe909 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fce0003f06070 */
/*0180*/ @!P1 BRA 0x2c0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*01b0*/ IMAD.WIDE R2, R9, R4, c[0x0][0x170] ; /* 0x00005c0009027625 */
/* 0x000fc800078e0204 */
/*01c0*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fc800078e0204 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*01e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*01f0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0008 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0230*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f7e0ff */
/*0250*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*0260*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fc40007f5e0ff */
/*0270*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe400017fe4ff */
/*0290*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x002fe20001ffe4ff */
/*02a0*/ FFMA R14, R3, R4, R14 ; /* 0x00000004030e7223 */
/* 0x004fc8000000000e */
/*02b0*/ @P1 BRA 0x1f0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*02c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02d0*/ @!P0 BRA 0xa50 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R3, R6, -R9, RZ ; /* 0x8000000906037210 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0300*/ BSSY B1, 0x730 ; /* 0x0000042000017945 */
/* 0x000fe40003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe20003f24270 */
/*0320*/ IMAD.WIDE R4, R9, R4, c[0x2][0x0] ; /* 0x0080000009047625 */
/* 0x000fca00078e0204 */
/*0330*/ IADD3 R2, P0, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x040fe40007f1e0ff */
/*0340*/ IADD3 R4, P2, R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fe40007f5e0ff */
/*0350*/ IADD3.X R3, R5.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005037a10 */
/* 0x040fe400007fe4ff */
/*0360*/ IADD3.X R5, R5, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0005057a10 */
/* 0x000fe400017fe4ff */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0380*/ @!P1 BRA 0x720 ; /* 0x0000039000009947 */
/* 0x000fee0003800000 */
/*0390*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03a0*/ IADD3 R7, R6, -0xc, RZ ; /* 0xfffffff406077810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R16, [R2.64+-0x8] ; /* 0xfffff80402107981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R24, [R2.64+-0x4] ; /* 0xfffffc0402187981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDG.E R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000f68000c1e1900 */
/*0420*/ LDG.E R20, [R2.64+0x4] ; /* 0x0000040402147981 */
/* 0x000f68000c1e1900 */
/*0430*/ LDG.E R22, [R4.64+0x8] ; /* 0x0000080404167981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x000f68000c1e1900 */
/*0450*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000f68000c1e1900 */
/*0460*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f68000c1e1900 */
/*0470*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000f68000c1e1900 */
/*0480*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001004020d7981 */
/* 0x000f68000c1e1900 */
/*0490*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ FFMA R16, R17, R16, R14 ; /* 0x0000001011107223 */
/* 0x004fc6000000000e */
/*04c0*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x0000a8000c1e1900 */
/*04d0*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180402117981 */
/* 0x0002a2000c1e1900 */
/*04e0*/ FFMA R24, R19, R24, R16 ; /* 0x0000001813187223 */
/* 0x008fc60000000010 */
/*04f0*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0404107981 */
/* 0x0000e8000c1e1900 */
/*0500*/ LDG.E R19, [R2.64+0x1c] ; /* 0x00001c0402137981 */
/* 0x0002e2000c1e1900 */
/*0510*/ FFMA R24, R18, R21, R24 ; /* 0x0000001512187223 */
/* 0x010fc60000000018 */
/*0520*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000128000c1e1900 */
/*0530*/ LDG.E R21, [R2.64+0x20] ; /* 0x0000200402157981 */
/* 0x000322000c1e1900 */
/*0540*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x020fc60000000018 */
/*0550*/ LDG.E R20, [R4.64+0x24] ; /* 0x0000240404147981 */
/* 0x000168000c1e1900 */
/*0560*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000362000c1e1900 */
/*0570*/ FFMA R24, R22, R25, R24 ; /* 0x0000001916187223 */
/* 0x000fc60000000018 */
/*0580*/ LDG.E R22, [R4.64+0x28] ; /* 0x0000280404167981 */
/* 0x000168000c1e1900 */
/*0590*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000362000c1e1900 */
/*05a0*/ FFMA R24, R8, R11, R24 ; /* 0x0000000b08187223 */
/* 0x000fc60000000018 */
/*05b0*/ LDG.E R11, [R4.64+0x2c] ; /* 0x00002c04040b7981 */
/* 0x000168000c1e1900 */
/*05c0*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0402087981 */
/* 0x000362000c1e1900 */
/*05d0*/ FFMA R24, R10, R13, R24 ; /* 0x0000000d0a187223 */
/* 0x000fc60000000018 */
/*05e0*/ LDG.E R13, [R4.64+0x30] ; /* 0x00003004040d7981 */
/* 0x000168000c1e1900 */
/*05f0*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000362000c1e1900 */
/*0600*/ FFMA R24, R12, R15, R24 ; /* 0x0000000f0c187223 */
/* 0x000fc60000000018 */
/*0610*/ LDG.E R12, [R4.64+0x34] ; /* 0x00003404040c7981 */
/* 0x000168000c1e1900 */
/*0620*/ LDG.E R15, [R2.64+0x34] ; /* 0x00003404020f7981 */
/* 0x000362000c1e1900 */
/*0630*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc80007ffe0ff */
/*0640*/ ISETP.GE.AND P1, PT, R9, R7, PT ; /* 0x000000070900720c */
/* 0x000fe40003f26270 */
/*0650*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fe40007f7e0ff */
/*0660*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fe40007f5e0ff */
/*0670*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fc60001ffe4ff */
/*0680*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0690*/ FFMA R14, R14, R17, R24 ; /* 0x000000110e0e7223 */
/* 0x004fc80000000018 */
/*06a0*/ FFMA R14, R16, R19, R14 ; /* 0x00000013100e7223 */
/* 0x008fc8000000000e */
/*06b0*/ FFMA R14, R18, R21, R14 ; /* 0x00000015120e7223 */
/* 0x010fc8000000000e */
/*06c0*/ FFMA R14, R20, R23, R14 ; /* 0x00000017140e7223 */
/* 0x020fc8000000000e */
/*06d0*/ FFMA R14, R22, R25, R14 ; /* 0x00000019160e7223 */
/* 0x000fc8000000000e */
/*06e0*/ FFMA R8, R11, R8, R14 ; /* 0x000000080b087223 */
/* 0x000fc8000000000e */
/*06f0*/ FFMA R8, R13, R10, R8 ; /* 0x0000000a0d087223 */
/* 0x000fc80000000008 */
/*0700*/ FFMA R14, R12, R15, R8 ; /* 0x0000000f0c0e7223 */
/* 0x000fe20000000008 */
/*0710*/ @!P1 BRA 0x3b0 ; /* 0xfffffc9000009947 */
/* 0x000fea000383ffff */
/*0720*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R7, R6, -R9, RZ ; /* 0x8000000906077210 */
/* 0x000fe20007ffe0ff */
/*0740*/ BSSY B1, 0x970 ; /* 0x0000022000017945 */
/* 0x000fe60003800000 */
/*0750*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0x960 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R13, [R4.64+-0x8] ; /* 0xfffff804040d7981 */
/* 0x0000a8000c1e1900 */
/*0780*/ LDG.E R12, [R2.64+-0x8] ; /* 0xfffff804020c7981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R15, [R4.64+-0x4] ; /* 0xfffffc04040f7981 */
/* 0x0000e8000c1e1900 */
/*07a0*/ LDG.E R16, [R2.64+-0x4] ; /* 0xfffffc0402107981 */
/* 0x0002e8000c1e1900 */
/*07b0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000128000c1e1900 */
/*07c0*/ LDG.E R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000328000c1e1900 */
/*07d0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R20, [R2.64+0x4] ; /* 0x0000040402147981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080404157981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R22, [R2.64+0x8] ; /* 0x0000080402167981 */
/* 0x000368000c1e1900 */
/*0810*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000168000c1e1900 */
/*0820*/ LDG.E R24, [R2.64+0xc] ; /* 0x00000c0402187981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000168000c1e1900 */
/*0840*/ LDG.E R7, [R2.64+0x10] ; /* 0x0000100402077981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140404087981 */
/* 0x000168000c1e1900 */
/*0860*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000362000c1e1900 */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f5e0ff */
/*08a0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe400010e0605 */
/*08b0*/ FFMA R12, R13, R12, R14 ; /* 0x0000000c0d0c7223 */
/* 0x004fe2000000000e */
/*08c0*/ IADD3 R13, P1, R2, 0x20, RZ ; /* 0x00000020020d7810 */
/* 0x000fc80007f3e0ff */
/*08d0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*08e0*/ MOV R2, R13 ; /* 0x0000000d00027202 */
/* 0x000fe20000000f00 */
/*08f0*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x008fc8000000000c */
/*0900*/ FFMA R12, R17, R18, R12 ; /* 0x00000012110c7223 */
/* 0x010fc8000000000c */
/*0910*/ FFMA R12, R19, R20, R12 ; /* 0x00000014130c7223 */
/* 0x020fc8000000000c */
/*0920*/ FFMA R12, R21, R22, R12 ; /* 0x00000016150c7223 */
/* 0x000fc8000000000c */
/*0930*/ FFMA R12, R23, R24, R12 ; /* 0x00000018170c7223 */
/* 0x000fc8000000000c */
/*0940*/ FFMA R7, R10, R7, R12 ; /* 0x000000070a077223 */
/* 0x000fc8000000000c */
/*0950*/ FFMA R14, R8, R11, R7 ; /* 0x0000000b080e7223 */
/* 0x000fe40000000007 */
/*0960*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.LT.OR P0, PT, R9, R6, P0 ; /* 0x000000060900720c */
/* 0x000fda0000701670 */
/*0980*/ @!P0 BRA 0xa50 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R7, [R4.64+-0x8] ; /* 0xfffff80404077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R6, [R2.64+-0x8] ; /* 0xfffff80402067981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R9, [R4.64+-0x4] ; /* 0xfffffc0404097981 */
/* 0x000ee8000c1e1900 */
/*09c0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000f62000c1e1900 */
/*0a10*/ FFMA R6, R7, R6, R14 ; /* 0x0000000607067223 */
/* 0x004fc8000000000e */
/*0a20*/ FFMA R6, R9, R8, R6 ; /* 0x0000000809067223 */
/* 0x008fc80000000006 */
/*0a30*/ FFMA R6, R11, R10, R6 ; /* 0x0000000a0b067223 */
/* 0x010fc80000000006 */
/*0a40*/ FFMA R14, R13, R12, R6 ; /* 0x0000000c0d0e7223 */
/* 0x020fe40000000006 */
/*0a50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a60*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0a70*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0a80*/ STG.E [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe2000c101904 */
/*0a90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0aa0*/ BRA 0xaa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ==========================================================================
// $Id$
// ==========================================================================
// (C)opyright: 2009-2010
//
// Ulm University
//
// Creator: Hendrik Lensch
// Email: {hendrik.lensch,johannes.hanika}@uni-ulm.de
// ==========================================================================
// $Log$
// ==========================================================================
#include <stdio.h>
#include <vector_types.h>
#include <stdlib.h>
using namespace std;
#define MAX_BLOCKS 256
#define MAX_THREADS 128
#define RTEST // use random initialization of array
/* compute the dot product between a1 and a2. a1 and a2 are of size
dim. The result of each thread should be stored in _dst[blockIdx.x *
blockDim.x + threadIdx.x]. Each thread should accumulate the dot
product of a subset of elements.
*/__global__ void dotProdKernel(float *_dst, const float* _a1, const float* _a2,
int _dim)
{
// program your kernel here
float result = 0.f;
const int thread_index = blockIdx.x * blockDim.x + threadIdx.x;
int elements_per_thread = (_dim + MAX_BLOCKS*MAX_THREADS -1 ) / (MAX_BLOCKS*MAX_THREADS);
int begin = thread_index * elements_per_thread;
int end = begin + elements_per_thread;
if(end > _dim)
end = _dim;
for(int i=begin; i<end; i++)
{
result += _a1[i] * _a2[i];
}
_dst[thread_index] = result;
}
/* This program sets up two large arrays of size dim and computes the
dot product of both arrays.
The arrays are uploaed only once and the dot product is computed
multiple times. While this does not make too much sense it
demonstrated the possible speedup. */
int main(int argc, char* argv[])
{
// parse command line
int acount = 1;
if (argc < 3)
{
printf("usage: testDotProduct <dim> <GPU-flag [0,1]>\n");
exit(1);
}
// number of elements in both vectors
int dim = atoi(argv[acount++]);
// flag indicating weather the CPU or the GPU version should be executed
bool gpuVersion = atoi(argv[acount++]);
printf("dim: %d\n", dim);
float* cpuArray1 = new float[dim];
float* cpuArray2 = new float[dim];
// initialize the two arrays (either random or deterministic)
for (int i = 0; i < dim; ++i)
{
#ifdef RTEST
cpuArray1[i] = drand48();
cpuArray2[i] = drand48();
#else
cpuArray1[i] = 2.0;
cpuArray2[i] = i % 10;
#endif
}
// now the gpu stuff
float* gpuArray1;
float* gpuArray2;
float* gpuResult;
float* h;
if (gpuVersion)
{
const size_t input_size = dim * sizeof(float);
const size_t output_size = MAX_BLOCKS * MAX_THREADS * sizeof(float);
cudaMalloc((void**) &gpuArray1, input_size);
cudaMalloc((void**) &gpuArray2, input_size);
cudaMalloc((void**) &gpuResult, output_size);
cudaMemcpy(gpuArray1, cpuArray1, input_size,
cudaMemcpyHostToDevice);
cudaMemcpy(gpuArray2, cpuArray2, input_size,
cudaMemcpyHostToDevice);
// allocate an array to download the results of all threads
h = new float[MAX_BLOCKS * MAX_THREADS];
}
const int num_iters = 100;
double finalDotProduct;
if (!gpuVersion)
{
printf("cpu: ");
for (int iter = 0; iter < num_iters; ++iter)
{
finalDotProduct = 0.0;
for (int i = 0; i < dim; ++i)
{
finalDotProduct += cpuArray1[i] * cpuArray2[i];
}
}
}
else
{
// Cuda version here
printf("gpu: ");
// a simplistic way of splitting the problem into threads
dim3 blockGrid(MAX_BLOCKS);
dim3 threadBlock(MAX_THREADS);
for (int iter = 0; iter < num_iters; ++iter)
{
dotProdKernel<<<blockGrid, threadBlock>>>(gpuResult, gpuArray1,
gpuArray2, dim);
cudaThreadSynchronize();
}
// download and combine the results of multiple threads on the CPU
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
cudaMemcpy(h, gpuResult, MAX_BLOCKS * MAX_THREADS * sizeof(float), cudaMemcpyDeviceToHost);
finalDotProduct = 0.f;
for(int i=0; i<MAX_BLOCKS * MAX_THREADS; ++i)
finalDotProduct += h[i];
}
printf("Result: %f\n", finalDotProduct);
if (gpuVersion)
{
// cleanup GPU memory
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
delete[] h;
}
delete[] cpuArray2;
delete[] cpuArray1;
printf("done\n");
} | .file "tmpxft_00101dca_00000000-6_testDotProduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
.type _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i, @function
_Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13dotProdKernelPfPKfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i, .-_Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
.globl _Z13dotProdKernelPfPKfS1_i
.type _Z13dotProdKernelPfPKfS1_i, @function
_Z13dotProdKernelPfPKfS1_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13dotProdKernelPfPKfS1_i, .-_Z13dotProdKernelPfPKfS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: testDotProduct <dim> <GPU-flag [0,1]>\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "dim: %d\n"
.LC3:
.string "gpu: "
.LC4:
.string "Result: %f\n"
.LC5:
.string "done\n"
.LC6:
.string "cpu: "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jle .L36
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, (%rsp)
movl %r15d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r15d, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L13
leaq 0(,%rax,4), %r14
movq %r14, 8(%rsp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbp
leal -1(%r15), %r14d
movl $0, %r13d
testl %r15d, %r15d
jle .L15
.L17:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r13,4)
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%r13,4)
movq %r13, %rax
addq $1, %r13
cmpq %r14, %rax
jne .L17
.L15:
cmpl $0, (%rsp)
jne .L37
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %esi
leal -1(%r15), %ecx
jmp .L26
.L36:
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L16
call __stack_chk_fail@PLT
.L16:
call __cxa_throw_bad_array_new_length@PLT
.L37:
leaq 24(%rsp), %rdi
movq 8(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $131072, %edi
call _Znam@PLT
movq %rax, %r14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $100, %r13d
jmp .L19
.L20:
movss (%rbx,%rax,4), %xmm0
mulss 0(%rbp,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L20
.L23:
subl $1, %esi
je .L21
.L26:
movl $0, %eax
pxor %xmm1, %xmm1
testl %r12d, %r12d
jg .L20
jmp .L23
.L24:
call cudaThreadSynchronize@PLT
subl $1, %r13d
je .L38
.L19:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L24
movl %r12d, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
jmp .L24
.L38:
movl $2, %ecx
movl $131072, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rax
leaq 131072(%r14), %rdx
pxor %xmm0, %xmm0
.L25:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L25
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call _ZdaPv@PLT
.L27:
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movapd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L27
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13dotProdKernelPfPKfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dotProdKernelPfPKfS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ==========================================================================
// $Id$
// ==========================================================================
// (C)opyright: 2009-2010
//
// Ulm University
//
// Creator: Hendrik Lensch
// Email: {hendrik.lensch,johannes.hanika}@uni-ulm.de
// ==========================================================================
// $Log$
// ==========================================================================
#include <stdio.h>
#include <vector_types.h>
#include <stdlib.h>
using namespace std;
#define MAX_BLOCKS 256
#define MAX_THREADS 128
#define RTEST // use random initialization of array
/* compute the dot product between a1 and a2. a1 and a2 are of size
dim. The result of each thread should be stored in _dst[blockIdx.x *
blockDim.x + threadIdx.x]. Each thread should accumulate the dot
product of a subset of elements.
*/__global__ void dotProdKernel(float *_dst, const float* _a1, const float* _a2,
int _dim)
{
// program your kernel here
float result = 0.f;
const int thread_index = blockIdx.x * blockDim.x + threadIdx.x;
int elements_per_thread = (_dim + MAX_BLOCKS*MAX_THREADS -1 ) / (MAX_BLOCKS*MAX_THREADS);
int begin = thread_index * elements_per_thread;
int end = begin + elements_per_thread;
if(end > _dim)
end = _dim;
for(int i=begin; i<end; i++)
{
result += _a1[i] * _a2[i];
}
_dst[thread_index] = result;
}
/* This program sets up two large arrays of size dim and computes the
dot product of both arrays.
The arrays are uploaed only once and the dot product is computed
multiple times. While this does not make too much sense it
demonstrated the possible speedup. */
int main(int argc, char* argv[])
{
// parse command line
int acount = 1;
if (argc < 3)
{
printf("usage: testDotProduct <dim> <GPU-flag [0,1]>\n");
exit(1);
}
// number of elements in both vectors
int dim = atoi(argv[acount++]);
// flag indicating weather the CPU or the GPU version should be executed
bool gpuVersion = atoi(argv[acount++]);
printf("dim: %d\n", dim);
float* cpuArray1 = new float[dim];
float* cpuArray2 = new float[dim];
// initialize the two arrays (either random or deterministic)
for (int i = 0; i < dim; ++i)
{
#ifdef RTEST
cpuArray1[i] = drand48();
cpuArray2[i] = drand48();
#else
cpuArray1[i] = 2.0;
cpuArray2[i] = i % 10;
#endif
}
// now the gpu stuff
float* gpuArray1;
float* gpuArray2;
float* gpuResult;
float* h;
if (gpuVersion)
{
const size_t input_size = dim * sizeof(float);
const size_t output_size = MAX_BLOCKS * MAX_THREADS * sizeof(float);
cudaMalloc((void**) &gpuArray1, input_size);
cudaMalloc((void**) &gpuArray2, input_size);
cudaMalloc((void**) &gpuResult, output_size);
cudaMemcpy(gpuArray1, cpuArray1, input_size,
cudaMemcpyHostToDevice);
cudaMemcpy(gpuArray2, cpuArray2, input_size,
cudaMemcpyHostToDevice);
// allocate an array to download the results of all threads
h = new float[MAX_BLOCKS * MAX_THREADS];
}
const int num_iters = 100;
double finalDotProduct;
if (!gpuVersion)
{
printf("cpu: ");
for (int iter = 0; iter < num_iters; ++iter)
{
finalDotProduct = 0.0;
for (int i = 0; i < dim; ++i)
{
finalDotProduct += cpuArray1[i] * cpuArray2[i];
}
}
}
else
{
// Cuda version here
printf("gpu: ");
// a simplistic way of splitting the problem into threads
dim3 blockGrid(MAX_BLOCKS);
dim3 threadBlock(MAX_THREADS);
for (int iter = 0; iter < num_iters; ++iter)
{
dotProdKernel<<<blockGrid, threadBlock>>>(gpuResult, gpuArray1,
gpuArray2, dim);
cudaThreadSynchronize();
}
// download and combine the results of multiple threads on the CPU
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
cudaMemcpy(h, gpuResult, MAX_BLOCKS * MAX_THREADS * sizeof(float), cudaMemcpyDeviceToHost);
finalDotProduct = 0.f;
for(int i=0; i<MAX_BLOCKS * MAX_THREADS; ++i)
finalDotProduct += h[i];
}
printf("Result: %f\n", finalDotProduct);
if (gpuVersion)
{
// cleanup GPU memory
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
delete[] h;
}
delete[] cpuArray2;
delete[] cpuArray1;
printf("done\n");
} | // ==========================================================================
// $Id$
// ==========================================================================
// (C)opyright: 2009-2010
//
// Ulm University
//
// Creator: Hendrik Lensch
// Email: {hendrik.lensch,johannes.hanika}@uni-ulm.de
// ==========================================================================
// $Log$
// ==========================================================================
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_vector_types.h>
#include <stdlib.h>
using namespace std;
#define MAX_BLOCKS 256
#define MAX_THREADS 128
#define RTEST // use random initialization of array
/* compute the dot product between a1 and a2. a1 and a2 are of size
dim. The result of each thread should be stored in _dst[blockIdx.x *
blockDim.x + threadIdx.x]. Each thread should accumulate the dot
product of a subset of elements.
*/__global__ void dotProdKernel(float *_dst, const float* _a1, const float* _a2,
int _dim)
{
// program your kernel here
float result = 0.f;
const int thread_index = blockIdx.x * blockDim.x + threadIdx.x;
int elements_per_thread = (_dim + MAX_BLOCKS*MAX_THREADS -1 ) / (MAX_BLOCKS*MAX_THREADS);
int begin = thread_index * elements_per_thread;
int end = begin + elements_per_thread;
if(end > _dim)
end = _dim;
for(int i=begin; i<end; i++)
{
result += _a1[i] * _a2[i];
}
_dst[thread_index] = result;
}
/* This program sets up two large arrays of size dim and computes the
dot product of both arrays.
The arrays are uploaed only once and the dot product is computed
multiple times. While this does not make too much sense it
demonstrated the possible speedup. */
int main(int argc, char* argv[])
{
// parse command line
int acount = 1;
if (argc < 3)
{
printf("usage: testDotProduct <dim> <GPU-flag [0,1]>\n");
exit(1);
}
// number of elements in both vectors
int dim = atoi(argv[acount++]);
// flag indicating weather the CPU or the GPU version should be executed
bool gpuVersion = atoi(argv[acount++]);
printf("dim: %d\n", dim);
float* cpuArray1 = new float[dim];
float* cpuArray2 = new float[dim];
// initialize the two arrays (either random or deterministic)
for (int i = 0; i < dim; ++i)
{
#ifdef RTEST
cpuArray1[i] = drand48();
cpuArray2[i] = drand48();
#else
cpuArray1[i] = 2.0;
cpuArray2[i] = i % 10;
#endif
}
// now the gpu stuff
float* gpuArray1;
float* gpuArray2;
float* gpuResult;
float* h;
if (gpuVersion)
{
const size_t input_size = dim * sizeof(float);
const size_t output_size = MAX_BLOCKS * MAX_THREADS * sizeof(float);
hipMalloc((void**) &gpuArray1, input_size);
hipMalloc((void**) &gpuArray2, input_size);
hipMalloc((void**) &gpuResult, output_size);
hipMemcpy(gpuArray1, cpuArray1, input_size,
hipMemcpyHostToDevice);
hipMemcpy(gpuArray2, cpuArray2, input_size,
hipMemcpyHostToDevice);
// allocate an array to download the results of all threads
h = new float[MAX_BLOCKS * MAX_THREADS];
}
const int num_iters = 100;
double finalDotProduct;
if (!gpuVersion)
{
printf("cpu: ");
for (int iter = 0; iter < num_iters; ++iter)
{
finalDotProduct = 0.0;
for (int i = 0; i < dim; ++i)
{
finalDotProduct += cpuArray1[i] * cpuArray2[i];
}
}
}
else
{
// Cuda version here
printf("gpu: ");
// a simplistic way of splitting the problem into threads
dim3 blockGrid(MAX_BLOCKS);
dim3 threadBlock(MAX_THREADS);
for (int iter = 0; iter < num_iters; ++iter)
{
dotProdKernel<<<blockGrid, threadBlock>>>(gpuResult, gpuArray1,
gpuArray2, dim);
hipDeviceSynchronize();
}
// download and combine the results of multiple threads on the CPU
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
hipMemcpy(h, gpuResult, MAX_BLOCKS * MAX_THREADS * sizeof(float), hipMemcpyDeviceToHost);
finalDotProduct = 0.f;
for(int i=0; i<MAX_BLOCKS * MAX_THREADS; ++i)
finalDotProduct += h[i];
}
printf("Result: %f\n", finalDotProduct);
if (gpuVersion)
{
// cleanup GPU memory
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
delete[] h;
}
delete[] cpuArray2;
delete[] cpuArray1;
printf("done\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ==========================================================================
// $Id$
// ==========================================================================
// (C)opyright: 2009-2010
//
// Ulm University
//
// Creator: Hendrik Lensch
// Email: {hendrik.lensch,johannes.hanika}@uni-ulm.de
// ==========================================================================
// $Log$
// ==========================================================================
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_vector_types.h>
#include <stdlib.h>
using namespace std;
#define MAX_BLOCKS 256
#define MAX_THREADS 128
#define RTEST // use random initialization of array
/* compute the dot product between a1 and a2. a1 and a2 are of size
dim. The result of each thread should be stored in _dst[blockIdx.x *
blockDim.x + threadIdx.x]. Each thread should accumulate the dot
product of a subset of elements.
*/__global__ void dotProdKernel(float *_dst, const float* _a1, const float* _a2,
int _dim)
{
// program your kernel here
float result = 0.f;
const int thread_index = blockIdx.x * blockDim.x + threadIdx.x;
int elements_per_thread = (_dim + MAX_BLOCKS*MAX_THREADS -1 ) / (MAX_BLOCKS*MAX_THREADS);
int begin = thread_index * elements_per_thread;
int end = begin + elements_per_thread;
if(end > _dim)
end = _dim;
for(int i=begin; i<end; i++)
{
result += _a1[i] * _a2[i];
}
_dst[thread_index] = result;
}
/* This program sets up two large arrays of size dim and computes the
dot product of both arrays.
The arrays are uploaed only once and the dot product is computed
multiple times. While this does not make too much sense it
demonstrated the possible speedup. */
int main(int argc, char* argv[])
{
// parse command line
int acount = 1;
if (argc < 3)
{
printf("usage: testDotProduct <dim> <GPU-flag [0,1]>\n");
exit(1);
}
// number of elements in both vectors
int dim = atoi(argv[acount++]);
// flag indicating weather the CPU or the GPU version should be executed
bool gpuVersion = atoi(argv[acount++]);
printf("dim: %d\n", dim);
float* cpuArray1 = new float[dim];
float* cpuArray2 = new float[dim];
// initialize the two arrays (either random or deterministic)
for (int i = 0; i < dim; ++i)
{
#ifdef RTEST
cpuArray1[i] = drand48();
cpuArray2[i] = drand48();
#else
cpuArray1[i] = 2.0;
cpuArray2[i] = i % 10;
#endif
}
// now the gpu stuff
float* gpuArray1;
float* gpuArray2;
float* gpuResult;
float* h;
if (gpuVersion)
{
const size_t input_size = dim * sizeof(float);
const size_t output_size = MAX_BLOCKS * MAX_THREADS * sizeof(float);
hipMalloc((void**) &gpuArray1, input_size);
hipMalloc((void**) &gpuArray2, input_size);
hipMalloc((void**) &gpuResult, output_size);
hipMemcpy(gpuArray1, cpuArray1, input_size,
hipMemcpyHostToDevice);
hipMemcpy(gpuArray2, cpuArray2, input_size,
hipMemcpyHostToDevice);
// allocate an array to download the results of all threads
h = new float[MAX_BLOCKS * MAX_THREADS];
}
const int num_iters = 100;
double finalDotProduct;
if (!gpuVersion)
{
printf("cpu: ");
for (int iter = 0; iter < num_iters; ++iter)
{
finalDotProduct = 0.0;
for (int i = 0; i < dim; ++i)
{
finalDotProduct += cpuArray1[i] * cpuArray2[i];
}
}
}
else
{
// Cuda version here
printf("gpu: ");
// a simplistic way of splitting the problem into threads
dim3 blockGrid(MAX_BLOCKS);
dim3 threadBlock(MAX_THREADS);
for (int iter = 0; iter < num_iters; ++iter)
{
dotProdKernel<<<blockGrid, threadBlock>>>(gpuResult, gpuArray1,
gpuArray2, dim);
hipDeviceSynchronize();
}
// download and combine the results of multiple threads on the CPU
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
hipMemcpy(h, gpuResult, MAX_BLOCKS * MAX_THREADS * sizeof(float), hipMemcpyDeviceToHost);
finalDotProduct = 0.f;
for(int i=0; i<MAX_BLOCKS * MAX_THREADS; ++i)
finalDotProduct += h[i];
}
printf("Result: %f\n", finalDotProduct);
if (gpuVersion)
{
// cleanup GPU memory
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
delete[] h;
}
delete[] cpuArray2;
delete[] cpuArray1;
printf("done\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13dotProdKernelPfPKfS1_i
.globl _Z13dotProdKernelPfPKfS1_i
.p2align 8
.type _Z13dotProdKernelPfPKfS1_i,@function
_Z13dotProdKernelPfPKfS1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s3, 0x7fff
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_ashr_i32 s2, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 17
s_add_i32 s4, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s2, s4, 15
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s2, v2
v_min_i32_e32 v0, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v2, v0
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_mov_b32 s4, 0
.p2align 6
.LBB0_2:
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[5:6], off
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v8, v9
v_cmp_ge_i32_e64 s2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s2, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13dotProdKernelPfPKfS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13dotProdKernelPfPKfS1_i, .Lfunc_end0-_Z13dotProdKernelPfPKfS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13dotProdKernelPfPKfS1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13dotProdKernelPfPKfS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ==========================================================================
// $Id$
// ==========================================================================
// (C)opyright: 2009-2010
//
// Ulm University
//
// Creator: Hendrik Lensch
// Email: {hendrik.lensch,johannes.hanika}@uni-ulm.de
// ==========================================================================
// $Log$
// ==========================================================================
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_vector_types.h>
#include <stdlib.h>
using namespace std;
#define MAX_BLOCKS 256
#define MAX_THREADS 128
#define RTEST // use random initialization of array
/* compute the dot product between a1 and a2. a1 and a2 are of size
dim. The result of each thread should be stored in _dst[blockIdx.x *
blockDim.x + threadIdx.x]. Each thread should accumulate the dot
product of a subset of elements.
*/__global__ void dotProdKernel(float *_dst, const float* _a1, const float* _a2,
int _dim)
{
// program your kernel here
float result = 0.f;
const int thread_index = blockIdx.x * blockDim.x + threadIdx.x;
int elements_per_thread = (_dim + MAX_BLOCKS*MAX_THREADS -1 ) / (MAX_BLOCKS*MAX_THREADS);
int begin = thread_index * elements_per_thread;
int end = begin + elements_per_thread;
if(end > _dim)
end = _dim;
for(int i=begin; i<end; i++)
{
result += _a1[i] * _a2[i];
}
_dst[thread_index] = result;
}
/* This program sets up two large arrays of size dim and computes the
dot product of both arrays.
The arrays are uploaed only once and the dot product is computed
multiple times. While this does not make too much sense it
demonstrated the possible speedup. */
int main(int argc, char* argv[])
{
// parse command line
int acount = 1;
if (argc < 3)
{
printf("usage: testDotProduct <dim> <GPU-flag [0,1]>\n");
exit(1);
}
// number of elements in both vectors
int dim = atoi(argv[acount++]);
// flag indicating weather the CPU or the GPU version should be executed
bool gpuVersion = atoi(argv[acount++]);
printf("dim: %d\n", dim);
float* cpuArray1 = new float[dim];
float* cpuArray2 = new float[dim];
// initialize the two arrays (either random or deterministic)
for (int i = 0; i < dim; ++i)
{
#ifdef RTEST
cpuArray1[i] = drand48();
cpuArray2[i] = drand48();
#else
cpuArray1[i] = 2.0;
cpuArray2[i] = i % 10;
#endif
}
// now the gpu stuff
float* gpuArray1;
float* gpuArray2;
float* gpuResult;
float* h;
if (gpuVersion)
{
const size_t input_size = dim * sizeof(float);
const size_t output_size = MAX_BLOCKS * MAX_THREADS * sizeof(float);
hipMalloc((void**) &gpuArray1, input_size);
hipMalloc((void**) &gpuArray2, input_size);
hipMalloc((void**) &gpuResult, output_size);
hipMemcpy(gpuArray1, cpuArray1, input_size,
hipMemcpyHostToDevice);
hipMemcpy(gpuArray2, cpuArray2, input_size,
hipMemcpyHostToDevice);
// allocate an array to download the results of all threads
h = new float[MAX_BLOCKS * MAX_THREADS];
}
const int num_iters = 100;
double finalDotProduct;
if (!gpuVersion)
{
printf("cpu: ");
for (int iter = 0; iter < num_iters; ++iter)
{
finalDotProduct = 0.0;
for (int i = 0; i < dim; ++i)
{
finalDotProduct += cpuArray1[i] * cpuArray2[i];
}
}
}
else
{
// Cuda version here
printf("gpu: ");
// a simplistic way of splitting the problem into threads
dim3 blockGrid(MAX_BLOCKS);
dim3 threadBlock(MAX_THREADS);
for (int iter = 0; iter < num_iters; ++iter)
{
dotProdKernel<<<blockGrid, threadBlock>>>(gpuResult, gpuArray1,
gpuArray2, dim);
hipDeviceSynchronize();
}
// download and combine the results of multiple threads on the CPU
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
hipMemcpy(h, gpuResult, MAX_BLOCKS * MAX_THREADS * sizeof(float), hipMemcpyDeviceToHost);
finalDotProduct = 0.f;
for(int i=0; i<MAX_BLOCKS * MAX_THREADS; ++i)
finalDotProduct += h[i];
}
printf("Result: %f\n", finalDotProduct);
if (gpuVersion)
{
// cleanup GPU memory
//!!!!!!!!! missing !!!!!!!!!!!!!!!!!!!!!!!!
delete[] h;
}
delete[] cpuArray2;
delete[] cpuArray1;
printf("done\n");
} | .text
.file "testDotProduct.hip"
.globl _Z28__device_stub__dotProdKernelPfPKfS1_i # -- Begin function _Z28__device_stub__dotProdKernelPfPKfS1_i
.p2align 4, 0x90
.type _Z28__device_stub__dotProdKernelPfPKfS1_i,@function
_Z28__device_stub__dotProdKernelPfPKfS1_i: # @_Z28__device_stub__dotProdKernelPfPKfS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13dotProdKernelPfPKfS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__dotProdKernelPfPKfS1_i, .Lfunc_end0-_Z28__device_stub__dotProdKernelPfPKfS1_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jle .LBB1_23
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %r14, 8(%rsp) # 8-byte Spill
movslq %r14d, %r12
leaq (,%r12,4), %r13
testl %r12d, %r12d
movq $-1, %rbx
cmovnsq %r13, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
movq %rbx, %rdi
callq _Znam
movq %rax, %r15
testl %r12d, %r12d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl 8(%rsp), %ebx # 4-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %rbx
jne .LBB1_3
.LBB1_4: # %._crit_edge
testl %ebp, %ebp
je .LBB1_5
# %bb.6:
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl $131072, %edi # imm = 0x20000
callq _Znam
movq %rax, %r13
testl %ebp, %ebp
je .LBB1_8
.LBB1_13:
movq %rbp, 48(%rsp) # 8-byte Spill
movabsq $4294967424, %rbp # imm = 0x100000080
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $100, %r12d
leaq 128(%rbp), %rbx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_14 Depth=1
callq hipDeviceSynchronize
decl %r12d
je .LBB1_17
.LBB1_14: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15: # in Loop: Header=BB1_14 Depth=1
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z13dotProdKernelPfPKfS1_i, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_16
.LBB1_17:
movq 24(%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
movq 48(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB1_18: # =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB1_18
.LBB1_19: # %.loopexit
movl $.L.str.4, %edi
movb $1, %al
callq printf
testl %ebp, %ebp
je .LBB1_22
# %bb.20: # %.loopexit
testq %r13, %r13
je .LBB1_22
# %bb.21:
movq %r13, %rdi
callq _ZdaPv
.LBB1_22:
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 224
# implicit-def: $r13
testl %ebp, %ebp
jne .LBB1_13
.LBB1_8:
xorl %ebx, %ebx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdx # 8-byte Reload
movl %edx, %eax
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_10: # %._crit_edge73
# in Loop: Header=BB1_9 Depth=1
incl %ebx
cmpl $100, %ebx
je .LBB1_19
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorps %xmm0, %xmm0
testl %edx, %edx
jle .LBB1_10
# %bb.11: # %.lr.ph72.preheader
# in Loop: Header=BB1_9 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_12: # %.lr.ph72
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15,%rcx,4), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB1_12
jmp .LBB1_10
.LBB1_23:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dotProdKernelPfPKfS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13dotProdKernelPfPKfS1_i,@object # @_Z13dotProdKernelPfPKfS1_i
.section .rodata,"a",@progbits
.globl _Z13dotProdKernelPfPKfS1_i
.p2align 3, 0x0
_Z13dotProdKernelPfPKfS1_i:
.quad _Z28__device_stub__dotProdKernelPfPKfS1_i
.size _Z13dotProdKernelPfPKfS1_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "dim: %d\n"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cpu: "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gpu: "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Result: %f\n"
.size .L.str.4, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13dotProdKernelPfPKfS1_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "usage: testDotProduct <dim> <GPU-flag [0,1]>"
.size .Lstr.1, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__dotProdKernelPfPKfS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13dotProdKernelPfPKfS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13dotProdKernelPfPKfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0xa60 ; /* 0x00000a2000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, UR4, 0x7fff, URZ ; /* 0x00007fff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0070*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fc80008011404 */
/*0080*/ ULEA.HI UR5, UR5, UR4, URZ, 0xf ; /* 0x0000000405057291 */
/* 0x000fc8000f8f783f */
/*0090*/ USHF.R.S32.HI UR5, URZ, 0xf, UR5 ; /* 0x0000000f3f057899 */
/* 0x000fe20008011405 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00b0*/ IMAD R9, R0, UR5, RZ ; /* 0x0000000500097c24 */
/* 0x000fca000f8e02ff */
/*00c0*/ IADD3 R6, R9, UR5, RZ ; /* 0x0000000509067c10 */
/* 0x000fe2000fffe0ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMNMX R6, R6, c[0x0][0x178], PT ; /* 0x00005e0006067a17 */
/* 0x000fc80003800200 */
/*00f0*/ ISETP.GE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fda0003f06270 */
/*0100*/ @P0 BRA 0xa50 ; /* 0x0000094000000947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R2, -R9, R6.reuse, RZ ; /* 0x0000000609027210 */
/* 0x080fe20007ffe1ff */
/*0120*/ BSSY B1, 0x2d0 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0130*/ LOP3.LUT R4, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff047212 */
/* 0x000fe200078e33ff */
/*0140*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0150*/ LOP3.LUT P1, R7, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302077812 */
/* 0x000fe4000782c0ff */
/*0160*/ IADD3 R4, -R4, -0x2, -R9 ; /* 0xfffffffe04047810 */
/* 0x000fc80007ffe909 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fce0003f06070 */
/*0180*/ @!P1 BRA 0x2c0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*01b0*/ IMAD.WIDE R2, R9, R4, c[0x0][0x170] ; /* 0x00005c0009027625 */
/* 0x000fc800078e0204 */
/*01c0*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fc800078e0204 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*01e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*01f0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0008 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0230*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f7e0ff */
/*0250*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*0260*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fc40007f5e0ff */
/*0270*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe400017fe4ff */
/*0290*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x002fe20001ffe4ff */
/*02a0*/ FFMA R14, R3, R4, R14 ; /* 0x00000004030e7223 */
/* 0x004fc8000000000e */
/*02b0*/ @P1 BRA 0x1f0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*02c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02d0*/ @!P0 BRA 0xa50 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R3, R6, -R9, RZ ; /* 0x8000000906037210 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0300*/ BSSY B1, 0x730 ; /* 0x0000042000017945 */
/* 0x000fe40003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe20003f24270 */
/*0320*/ IMAD.WIDE R4, R9, R4, c[0x2][0x0] ; /* 0x0080000009047625 */
/* 0x000fca00078e0204 */
/*0330*/ IADD3 R2, P0, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x040fe40007f1e0ff */
/*0340*/ IADD3 R4, P2, R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fe40007f5e0ff */
/*0350*/ IADD3.X R3, R5.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005037a10 */
/* 0x040fe400007fe4ff */
/*0360*/ IADD3.X R5, R5, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0005057a10 */
/* 0x000fe400017fe4ff */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0380*/ @!P1 BRA 0x720 ; /* 0x0000039000009947 */
/* 0x000fee0003800000 */
/*0390*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03a0*/ IADD3 R7, R6, -0xc, RZ ; /* 0xfffffff406077810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R16, [R2.64+-0x8] ; /* 0xfffff80402107981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R19, [R4.64+-0x4] ; /* 0xfffffc0404137981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R24, [R2.64+-0x4] ; /* 0xfffffc0402187981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDG.E R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000f68000c1e1900 */
/*0420*/ LDG.E R20, [R2.64+0x4] ; /* 0x0000040402147981 */
/* 0x000f68000c1e1900 */
/*0430*/ LDG.E R22, [R4.64+0x8] ; /* 0x0000080404167981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x000f68000c1e1900 */
/*0450*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000f68000c1e1900 */
/*0460*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f68000c1e1900 */
/*0470*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000f68000c1e1900 */
/*0480*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001004020d7981 */
/* 0x000f68000c1e1900 */
/*0490*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001404040c7981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ FFMA R16, R17, R16, R14 ; /* 0x0000001011107223 */
/* 0x004fc6000000000e */
/*04c0*/ LDG.E R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x0000a8000c1e1900 */
/*04d0*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180402117981 */
/* 0x0002a2000c1e1900 */
/*04e0*/ FFMA R24, R19, R24, R16 ; /* 0x0000001813187223 */
/* 0x008fc60000000010 */
/*04f0*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0404107981 */
/* 0x0000e8000c1e1900 */
/*0500*/ LDG.E R19, [R2.64+0x1c] ; /* 0x00001c0402137981 */
/* 0x0002e2000c1e1900 */
/*0510*/ FFMA R24, R18, R21, R24 ; /* 0x0000001512187223 */
/* 0x010fc60000000018 */
/*0520*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000128000c1e1900 */
/*0530*/ LDG.E R21, [R2.64+0x20] ; /* 0x0000200402157981 */
/* 0x000322000c1e1900 */
/*0540*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x020fc60000000018 */
/*0550*/ LDG.E R20, [R4.64+0x24] ; /* 0x0000240404147981 */
/* 0x000168000c1e1900 */
/*0560*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000362000c1e1900 */
/*0570*/ FFMA R24, R22, R25, R24 ; /* 0x0000001916187223 */
/* 0x000fc60000000018 */
/*0580*/ LDG.E R22, [R4.64+0x28] ; /* 0x0000280404167981 */
/* 0x000168000c1e1900 */
/*0590*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000362000c1e1900 */
/*05a0*/ FFMA R24, R8, R11, R24 ; /* 0x0000000b08187223 */
/* 0x000fc60000000018 */
/*05b0*/ LDG.E R11, [R4.64+0x2c] ; /* 0x00002c04040b7981 */
/* 0x000168000c1e1900 */
/*05c0*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0402087981 */
/* 0x000362000c1e1900 */
/*05d0*/ FFMA R24, R10, R13, R24 ; /* 0x0000000d0a187223 */
/* 0x000fc60000000018 */
/*05e0*/ LDG.E R13, [R4.64+0x30] ; /* 0x00003004040d7981 */
/* 0x000168000c1e1900 */
/*05f0*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000362000c1e1900 */
/*0600*/ FFMA R24, R12, R15, R24 ; /* 0x0000000f0c187223 */
/* 0x000fc60000000018 */
/*0610*/ LDG.E R12, [R4.64+0x34] ; /* 0x00003404040c7981 */
/* 0x000168000c1e1900 */
/*0620*/ LDG.E R15, [R2.64+0x34] ; /* 0x00003404020f7981 */
/* 0x000362000c1e1900 */
/*0630*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc80007ffe0ff */
/*0640*/ ISETP.GE.AND P1, PT, R9, R7, PT ; /* 0x000000070900720c */
/* 0x000fe40003f26270 */
/*0650*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fe40007f7e0ff */
/*0660*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fe40007f5e0ff */
/*0670*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fc60001ffe4ff */
/*0680*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0690*/ FFMA R14, R14, R17, R24 ; /* 0x000000110e0e7223 */
/* 0x004fc80000000018 */
/*06a0*/ FFMA R14, R16, R19, R14 ; /* 0x00000013100e7223 */
/* 0x008fc8000000000e */
/*06b0*/ FFMA R14, R18, R21, R14 ; /* 0x00000015120e7223 */
/* 0x010fc8000000000e */
/*06c0*/ FFMA R14, R20, R23, R14 ; /* 0x00000017140e7223 */
/* 0x020fc8000000000e */
/*06d0*/ FFMA R14, R22, R25, R14 ; /* 0x00000019160e7223 */
/* 0x000fc8000000000e */
/*06e0*/ FFMA R8, R11, R8, R14 ; /* 0x000000080b087223 */
/* 0x000fc8000000000e */
/*06f0*/ FFMA R8, R13, R10, R8 ; /* 0x0000000a0d087223 */
/* 0x000fc80000000008 */
/*0700*/ FFMA R14, R12, R15, R8 ; /* 0x0000000f0c0e7223 */
/* 0x000fe20000000008 */
/*0710*/ @!P1 BRA 0x3b0 ; /* 0xfffffc9000009947 */
/* 0x000fea000383ffff */
/*0720*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R7, R6, -R9, RZ ; /* 0x8000000906077210 */
/* 0x000fe20007ffe0ff */
/*0740*/ BSSY B1, 0x970 ; /* 0x0000022000017945 */
/* 0x000fe60003800000 */
/*0750*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0x960 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R13, [R4.64+-0x8] ; /* 0xfffff804040d7981 */
/* 0x0000a8000c1e1900 */
/*0780*/ LDG.E R12, [R2.64+-0x8] ; /* 0xfffff804020c7981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R15, [R4.64+-0x4] ; /* 0xfffffc04040f7981 */
/* 0x0000e8000c1e1900 */
/*07a0*/ LDG.E R16, [R2.64+-0x4] ; /* 0xfffffc0402107981 */
/* 0x0002e8000c1e1900 */
/*07b0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000128000c1e1900 */
/*07c0*/ LDG.E R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000328000c1e1900 */
/*07d0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R20, [R2.64+0x4] ; /* 0x0000040402147981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080404157981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R22, [R2.64+0x8] ; /* 0x0000080402167981 */
/* 0x000368000c1e1900 */
/*0810*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000168000c1e1900 */
/*0820*/ LDG.E R24, [R2.64+0xc] ; /* 0x00000c0402187981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000168000c1e1900 */
/*0840*/ LDG.E R7, [R2.64+0x10] ; /* 0x0000100402077981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140404087981 */
/* 0x000168000c1e1900 */
/*0860*/ LDG.E R11, [R2.64+0x14] ; /* 0x00001404020b7981 */
/* 0x000362000c1e1900 */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f5e0ff */
/*08a0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe400010e0605 */
/*08b0*/ FFMA R12, R13, R12, R14 ; /* 0x0000000c0d0c7223 */
/* 0x004fe2000000000e */
/*08c0*/ IADD3 R13, P1, R2, 0x20, RZ ; /* 0x00000020020d7810 */
/* 0x000fc80007f3e0ff */
/*08d0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*08e0*/ MOV R2, R13 ; /* 0x0000000d00027202 */
/* 0x000fe20000000f00 */
/*08f0*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x008fc8000000000c */
/*0900*/ FFMA R12, R17, R18, R12 ; /* 0x00000012110c7223 */
/* 0x010fc8000000000c */
/*0910*/ FFMA R12, R19, R20, R12 ; /* 0x00000014130c7223 */
/* 0x020fc8000000000c */
/*0920*/ FFMA R12, R21, R22, R12 ; /* 0x00000016150c7223 */
/* 0x000fc8000000000c */
/*0930*/ FFMA R12, R23, R24, R12 ; /* 0x00000018170c7223 */
/* 0x000fc8000000000c */
/*0940*/ FFMA R7, R10, R7, R12 ; /* 0x000000070a077223 */
/* 0x000fc8000000000c */
/*0950*/ FFMA R14, R8, R11, R7 ; /* 0x0000000b080e7223 */
/* 0x000fe40000000007 */
/*0960*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.LT.OR P0, PT, R9, R6, P0 ; /* 0x000000060900720c */
/* 0x000fda0000701670 */
/*0980*/ @!P0 BRA 0xa50 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R7, [R4.64+-0x8] ; /* 0xfffff80404077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R6, [R2.64+-0x8] ; /* 0xfffff80402067981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R9, [R4.64+-0x4] ; /* 0xfffffc0404097981 */
/* 0x000ee8000c1e1900 */
/*09c0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000f62000c1e1900 */
/*0a10*/ FFMA R6, R7, R6, R14 ; /* 0x0000000607067223 */
/* 0x004fc8000000000e */
/*0a20*/ FFMA R6, R9, R8, R6 ; /* 0x0000000809067223 */
/* 0x008fc80000000006 */
/*0a30*/ FFMA R6, R11, R10, R6 ; /* 0x0000000a0b067223 */
/* 0x010fc80000000006 */
/*0a40*/ FFMA R14, R13, R12, R6 ; /* 0x0000000c0d0e7223 */
/* 0x020fe40000000006 */
/*0a50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a60*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0a70*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0a80*/ STG.E [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe2000c101904 */
/*0a90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0aa0*/ BRA 0xaa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13dotProdKernelPfPKfS1_i
.globl _Z13dotProdKernelPfPKfS1_i
.p2align 8
.type _Z13dotProdKernelPfPKfS1_i,@function
_Z13dotProdKernelPfPKfS1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s3, 0x7fff
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_ashr_i32 s2, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 17
s_add_i32 s4, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s2, s4, 15
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s2, v2
v_min_i32_e32 v0, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v2, v0
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_mov_b32 s4, 0
.p2align 6
.LBB0_2:
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[5:6], off
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v8, v9
v_cmp_ge_i32_e64 s2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s2, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13dotProdKernelPfPKfS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13dotProdKernelPfPKfS1_i, .Lfunc_end0-_Z13dotProdKernelPfPKfS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13dotProdKernelPfPKfS1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13dotProdKernelPfPKfS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00101dca_00000000-6_testDotProduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
.type _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i, @function
_Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13dotProdKernelPfPKfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i, .-_Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
.globl _Z13dotProdKernelPfPKfS1_i
.type _Z13dotProdKernelPfPKfS1_i, @function
_Z13dotProdKernelPfPKfS1_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13dotProdKernelPfPKfS1_i, .-_Z13dotProdKernelPfPKfS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: testDotProduct <dim> <GPU-flag [0,1]>\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "dim: %d\n"
.LC3:
.string "gpu: "
.LC4:
.string "Result: %f\n"
.LC5:
.string "done\n"
.LC6:
.string "cpu: "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jle .L36
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, (%rsp)
movl %r15d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r15d, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L13
leaq 0(,%rax,4), %r14
movq %r14, 8(%rsp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbp
leal -1(%r15), %r14d
movl $0, %r13d
testl %r15d, %r15d
jle .L15
.L17:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r13,4)
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%r13,4)
movq %r13, %rax
addq $1, %r13
cmpq %r14, %rax
jne .L17
.L15:
cmpl $0, (%rsp)
jne .L37
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %esi
leal -1(%r15), %ecx
jmp .L26
.L36:
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L16
call __stack_chk_fail@PLT
.L16:
call __cxa_throw_bad_array_new_length@PLT
.L37:
leaq 24(%rsp), %rdi
movq 8(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $131072, %edi
call _Znam@PLT
movq %rax, %r14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $100, %r13d
jmp .L19
.L20:
movss (%rbx,%rax,4), %xmm0
mulss 0(%rbp,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L20
.L23:
subl $1, %esi
je .L21
.L26:
movl $0, %eax
pxor %xmm1, %xmm1
testl %r12d, %r12d
jg .L20
jmp .L23
.L24:
call cudaThreadSynchronize@PLT
subl $1, %r13d
je .L38
.L19:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L24
movl %r12d, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z40__device_stub__Z13dotProdKernelPfPKfS1_iPfPKfS1_i
jmp .L24
.L38:
movl $2, %ecx
movl $131072, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rax
leaq 131072(%r14), %rdx
pxor %xmm0, %xmm0
.L25:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L25
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call _ZdaPv@PLT
.L27:
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movapd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L27
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13dotProdKernelPfPKfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dotProdKernelPfPKfS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testDotProduct.hip"
.globl _Z28__device_stub__dotProdKernelPfPKfS1_i # -- Begin function _Z28__device_stub__dotProdKernelPfPKfS1_i
.p2align 4, 0x90
.type _Z28__device_stub__dotProdKernelPfPKfS1_i,@function
_Z28__device_stub__dotProdKernelPfPKfS1_i: # @_Z28__device_stub__dotProdKernelPfPKfS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13dotProdKernelPfPKfS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__dotProdKernelPfPKfS1_i, .Lfunc_end0-_Z28__device_stub__dotProdKernelPfPKfS1_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jle .LBB1_23
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %r14, 8(%rsp) # 8-byte Spill
movslq %r14d, %r12
leaq (,%r12,4), %r13
testl %r12d, %r12d
movq $-1, %rbx
cmovnsq %r13, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
movq %rbx, %rdi
callq _Znam
movq %rax, %r15
testl %r12d, %r12d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl 8(%rsp), %ebx # 4-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %rbx
jne .LBB1_3
.LBB1_4: # %._crit_edge
testl %ebp, %ebp
je .LBB1_5
# %bb.6:
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl $131072, %edi # imm = 0x20000
callq _Znam
movq %rax, %r13
testl %ebp, %ebp
je .LBB1_8
.LBB1_13:
movq %rbp, 48(%rsp) # 8-byte Spill
movabsq $4294967424, %rbp # imm = 0x100000080
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $100, %r12d
leaq 128(%rbp), %rbx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_14 Depth=1
callq hipDeviceSynchronize
decl %r12d
je .LBB1_17
.LBB1_14: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15: # in Loop: Header=BB1_14 Depth=1
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z13dotProdKernelPfPKfS1_i, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_16
.LBB1_17:
movq 24(%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
movq 48(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB1_18: # =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB1_18
.LBB1_19: # %.loopexit
movl $.L.str.4, %edi
movb $1, %al
callq printf
testl %ebp, %ebp
je .LBB1_22
# %bb.20: # %.loopexit
testq %r13, %r13
je .LBB1_22
# %bb.21:
movq %r13, %rdi
callq _ZdaPv
.LBB1_22:
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 224
# implicit-def: $r13
testl %ebp, %ebp
jne .LBB1_13
.LBB1_8:
xorl %ebx, %ebx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdx # 8-byte Reload
movl %edx, %eax
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_10: # %._crit_edge73
# in Loop: Header=BB1_9 Depth=1
incl %ebx
cmpl $100, %ebx
je .LBB1_19
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorps %xmm0, %xmm0
testl %edx, %edx
jle .LBB1_10
# %bb.11: # %.lr.ph72.preheader
# in Loop: Header=BB1_9 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_12: # %.lr.ph72
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15,%rcx,4), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB1_12
jmp .LBB1_10
.LBB1_23:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dotProdKernelPfPKfS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13dotProdKernelPfPKfS1_i,@object # @_Z13dotProdKernelPfPKfS1_i
.section .rodata,"a",@progbits
.globl _Z13dotProdKernelPfPKfS1_i
.p2align 3, 0x0
_Z13dotProdKernelPfPKfS1_i:
.quad _Z28__device_stub__dotProdKernelPfPKfS1_i
.size _Z13dotProdKernelPfPKfS1_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "dim: %d\n"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cpu: "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gpu: "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Result: %f\n"
.size .L.str.4, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13dotProdKernelPfPKfS1_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "usage: testDotProduct <dim> <GPU-flag [0,1]>"
.size .Lstr.1, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__dotProdKernelPfPKfS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13dotProdKernelPfPKfS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<string.h>
//#include<cublas.h>
//#include<R.h>
#define NTHREADS 512
//computes u = constant * t(X) %*% v
__device__ void cXtv(float con, int rows, int cols, float * X, int ldX, float * v,
float * u){
int i,k;
float sum;
for(k = 0; k < cols; k++){
sum = 0;
for(i = 0; i < rows; i++){
sum += X[i + k*ldX] * v[i];
}
u[k] = con*sum;
}
}
//computes X = X + v %*% u'
__device__ void Xpvut(int rows, int cols, float * X, int ldX, float *v, float *u){
int i, j;
for(i=0; i<rows; i++)
for(j=0; j<cols; j++)
X[i + j*ldX] += v[i] * u[j];
}
//calculates T = V'V where V is upper triangular
__device__ void uVtV(int rows, int cols, float * V, float * T){
int i, j, k;
float sum;
for(i=0; i<cols; i++){
for(j=0; j<cols; j++){
sum = 0;
for(k=0; k<min(i,j); k++)
sum += V[k + i*rows] * V[k + j*rows];
T[i + j*cols] = sum;
}
}
}
//Rounds "length" up the the next multiple of block length
__device__ int alignBlock(int length, unsigned blockExp){
int blockSize = 1 << blockExp;
int out = (length + blockSize - 1) & ( ( (unsigned) - 1) << blockExp);
return out;
}
__device__ void colswap(float *X, int n, int p, int i, int j){
float tmp;
int k;
float * Xi = X + i*n;
float * Xj = X + i*j;
if(i <= p && j <= p){
for(k = 0; k < n; k++){
tmp = Xi[k];
Xi[k] = Xj[k];
Xj[k] = tmp;
}
}
}
__device__ int getMaxIdx(int p, float * ColNorms, int id){
int maxIdx = 0, i, bit;
float max = ColNorms[maxIdx], tmp;
for(i = 1; i < p; i++){
bit = ( id & (1 << i) ) >> 1;
if( bit == 1){
tmp = ColNorms[i];
if(tmp > max){
max = tmp;
maxIdx = i;
}
}
}
return maxIdx;
}
__device__ int idx(int id, int p, int i){
int j, colcount=0, out;
for(j=0; j<p; j++){
if(colcount == i)
out = j;
if( ( id & ( 1 << j ) ) >> j == 1)
colcount += 1;
}
return out;
}
__global__ void getColNorms(int rows, int cols, float * dX, float * ColNorms){
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float sum = 0.f, term, * col;
if(colIndex >= cols)
return;
col = dX + colIndex * rows;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
ColNorms[colIndex] = sqrtf(sum);
}
__global__ void GetQRDecompBlocked(int n, int p, float * X, float * ColNorms,
unsigned int blockSize, int stride, float * scales,
float * Beta, float * qrAux, int * pivot,
float * WtR, int * rank, float * V, float * W,
float * T, float * u){
float tol = 0.0001; //float tolerance
int blockCount, blockEnd = 0, bc, i, kp; //kp is # cols processed
//unsigned int id = threadIDx.x + blockIDx.x * blockDim.x;
int varcount = 0, maxIdx, pm = 1;
//unsigned int * binid;
float * Xm; //model id's model matrix; will eventually contain R in QR decomp
//float * pXcol = X; //pointer to column of X
float * pXmcol; //pointer to column of Xm
float maxNorm;
float * pXmBlock; //pointer to block of Xm
size_t fbytes = sizeof(float);
int rk = 0; // Local value of rank;
int maxRank; //maximum possible rank of the model matrix
float minElt; // Lowest acceptable norm under given tolerance.
int maxCol; //this will be initialized to pm - 1, highest candidate column, not fixed
int maxRow = n - 1;
int rowskp = stride; // # unprocessed rows = stride - kp
int colskp; // # unprocessed cols = cols - kp
float *pVcol; //pointer to column of V
float *pVdiag; //pointer to diagonal element of V
float *pXmdiag; //pointer to diagonal element of dQRBlock
int colIdx;
int a,b;
int l;
//if(id > M)
// return;
//binid = (unsigned int *)calloc(p-1, sizeof(unsigned int));
/*
//copies the relevant columns of X into Xm
do{
int jump = 0;
unsigned int bit = 0;
memcpy(pXmcol, pXcol, n*fbytes); //copy the current column
//any time we copy any column but the first, set binid[col] = 1
if(varcount > 0){
binid[p - varcount] = 1; //actual index is (p - 1) - (varcount - 1)
pm += 1;
}
pXmcol += n; //update pointer on Xm to the next column
//bitwise operations on id to find proper columns
//look for the next used column of X
do{
jump += 1; //increment number of columns of X to move forward
varcount += 1; //increment number of total vars of X checked
//note: each column of X but the first represents a variable
//set bit as the k'th bit of id (1st bit is far right)
bit = ( id & ( 1 << varcount ) ) >> varcount;
//alternative code: declare tmpid above first.
////bit = tmpid & 1; //bit = 1 if last bit of tmpid is 1, 0 otherwise
////tmpid = tmpid >> 1; //bitshift tmpid right - lopping off last bit
}
while(bit == 0 && varcount < p);
pXcol += n*jump; //update pointer on X to the next used column
}
while(varcount < p );
//if varcount = k ( = p - 1 ), we still have to copy this last column, so the
//loop must iterate again
*/
pm = p;
//initialize variables that depend on pm and Xm
//Xm = (float *) calloc(stride*pm,fbytes); //allocate memory for model matrix
Xm = X;
pXmcol = Xm;
pXmBlock = Xm;
maxCol = pm - 1; //maximum possible column
colskp = pm;
maxIdx = getMaxIdx(p, ColNorms, (1 << pm) - 1);
//id);
maxNorm = ColNorms[maxIdx];
if (maxNorm < tol){
maxRank = 0; // Short-circuits the main pivot loop
}
else{
minElt = (1.0 + maxNorm) * tol;
maxRank = n > pm ? pm : n; //min(n,pm)
}
blockCount = (pm + blockSize - 1) / blockSize;
for(bc = 0; bc < blockCount; bc++){
// Determines "blockEnd", which counts the number of columns remaining
// in the upcoming block. Swaps trivial columns with the rightmost
// unvisited column until either a nontrivial column is found or all
// columns have been visited. Note that 'blockEnd <= blockSize', with
// inequality possible only in the rightmost processed block.
//
// This pivoting scheme does not attempt to order columns by norm, nor
// does it recompute norms altered by the rank-one update within the
// upcoming block. A higher-fidelity scheme is implemented in the non-
// blocked form of this function. Sapienti sat.
blockEnd = 0;
for(i = kp; i < kp + blockSize && i < maxRank && i <= maxCol; i++){
float colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
while( (colNorm < minElt) && (maxCol > i) ){
//while colNorm is smaller than the lowest acceptable norm, given tolerance
//and while the maximum column possible is larger than the current column
//keep track of column swap in pivot vector
int tempIdx = pivot[maxCol];
//exchange columns of Xm: current column and maxCol
colswap(Xm, stride, pm, i, maxCol);
pivot[maxCol] = pivot[i];
pivot[i] = tempIdx;
maxCol--;
//set new colNorm as norm of max column, now in i'th spot
colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
}
if (colNorm >= minElt)
blockEnd++;
}
rk += blockEnd;
//set V to 0 everywhere
for(a=0; a<blockSize; a++)
for(b=0; b<rowskp; b++)
*(V + b + a*rowskp) = 0;
pVcol = V; //pointer to column of V
pVdiag = V; //pointer to diagonal element of V
pXmdiag = pXmBlock; //pointer to diagonal element of XmBlock
for(colIdx = 0; colIdx < blockEnd; colIdx++){
float v1;
float v1Abs;
memcpy(pVdiag, pXmdiag, (rowskp - colIdx)*fbytes);
// Builds Householder vector from maximal column just copied.
// For now, uses slow memory transfers to modify leading element:
// V_1 += sign(V_1) * normV.
v1 = *pVdiag;
v1Abs = fabs(v1);
if(kp == maxRow)//botom row is not scaled
qrAux[kp] = v1Abs;
else{ // zero-valued "normV" should already have been ruled out.
int d;
float normV = 0;
float recipNormV;
float fac;
for(d=0; d < rowskp - colIdx; d++){
float diag = pVdiag[d];
normV += diag*diag;
}
normV = sqrtf(normV);
recipNormV = 1.0 / normV;
qrAux[kp] = 1.0 + v1Abs * recipNormV;
scales[colIdx] = (v1 >= 0.f ? 1.f : -1.f) * recipNormV;
// Scales leading nonzero element of vector.
fac = 1.0 + normV / v1Abs;
*pVdiag *= fac;
Beta[colIdx] = -2.0 / (normV * normV + v1Abs * (-1.0 + fac * fac));
// u = Beta[colIdx] * t(pXmBlock) %*% pVcol
// rows of pXmBlock = rowskp
// cols of pXmBlock = min(blockSize, colskp)
// leading dimension of pXmBlock = stride
// elements of pVcol = rowskp
// elements of u = min(blockSize, colskp)
cXtv(Beta[colIdx], rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
//pXmBlock = pXmBlock + pVcol %*% u'
//rows of pXmBlock = rowskp
//cols of pXmBlock = min(blockSize, colsk)
//elements of pVcol = rowskp
//elements of u = min(blockSize, colsk)
//leading dim of pXmBlock = stride
Xpvut(rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
}
pVcol += rowskp;
pVdiag += (rowskp + 1);
pXmdiag += (stride + 1);
kp++;
}
// If more unseen columns remain, updates the remainder of QR lying to
// the right of the block just updated. This must be done unless we
// happen to have exited the inner loop without having applied any
// Householder transformations (i.e., blockEnd == 0).
if (bc < blockCount - 1 && blockEnd > 0) {
// w_m = Beta (I + W V^t) v_m, where the unsubscripted matrices
// refer to those built at step 'i-1', having 'i' columns.
//
// w_i = Beta v_i
//
float *pTcol = T; //pointer to columns of dT
float *pWcol = W; //pointer to columns of dW
int m, a, b, c;
pVcol = V; //pointer to columns of dV
// T = V^t V
//// T = dT
//// V = dV
//rows of V' = blockSize
//cols of V' = rowsk
//leading dim of V = rowsk
//leading dim of T = rowsk
//rows/cols of T = blockSize
uVtV(rowskp, blockSize, V, T);
for (m = 0; m < blockSize; m++, pWcol += rowskp, pVcol += rowskp,
pTcol += blockSize) {
//for m=0,1,..., blockSize - 1
//pdWcol += rowsk
//pdVcol += rowsk
//pdTcol += blockSize
int a;
for(a = 0; a<rowskp; a++)
pWcol[a] = Beta[m]*pVcol[a];
// w_m = w_m + Beta W T(.,m)
//// w_m = pWcol
//// Beta = Beta[m]
//// T(.,m) = pTcol
//// W = dW
if (m > 0) {
int a, b;
for(a = 0; a < rowskp; a++){
float sum = 0;
for(b = 0; b < m; b++){
sum += W[b + a*m] * pTcol[b];
}
pWcol[a] += sum;
}
}
}
// Updates R, beginning at current diagonal by:
// R = (I_m + V W^t) R = R + V (W^t R)
//
// WtR = W^t R
//// WtR = dWtR
//// W = dW
//W is rowskp by blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
//WtR is blockSize by colsk - blockSize
for(a = 0; a < blockSize; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < rowskp; c++)
sum += W[c + rowskp*a] * *(pXmBlock + blockSize*stride + c + b*rowskp);
WtR[a + b*blockSize] = sum;
}
}
// R = V WtR + R
//// V = dV
//// WtR = dWtR
//// R = pdQRBlock + blockSize*stride
// V is rowskp by blockSize
//WtR is blockSize by colskp - blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
for(a = 0; a < rowskp; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < blockSize; c++){
sum += V[a + c*rowskp] * WtR[c + b*blockSize];
}
*(pXmBlock + blockSize*stride + a + b*rowskp) += sum;
}
}
}
// Flushes scaled Householder vectors to the subdiagonals of dQR,
// 'blockSize'-many at a time. The only time a smaller number are
// sent occurs when a partial block remains at the right end.
//
pVdiag = V; //pointer to diagonal of V
pXmdiag = pXmBlock; //pointer to diagonal of pXmBlock / XmBlock
for (l = 0; l < blockEnd; l++, pVdiag += (rowskp + 1),
pXmdiag += (stride + 1)) {
//for l = 0, 1, ..., blockEnd - 1
//// pVdiag += (rowskp + 1)
//// pXmdiag += (stride +1)
int a;
//pVdiag + 1 = scales[l]* (pVdiag + 1)
//pXmdiag + 1 = pVdiag + 1
for(a = 0; a < rowskp - l - 1; a++){
*(pVdiag + 1 + a) *= scales[l];
*(pXmdiag + 1 + a) = *(pVdiag + 1 + a);
}
}
pXmBlock += blockSize * (stride + 1);
colskp -= blockSize;
rowskp -= blockSize;
//end main loop
}
//set rank
*rank = rk;
// Xm now contains the upper-triangular portion of the factorization,
// R.
// V is lower-triangular, and contains the Householder vectors, from
// which the Q portion can be derived. An adjusted form of the
// diagonal is saved in qrAux, while the sub-diagonal portion is
// written onto QR.
}
int main(void){
int n = 10, p = 5;
//, k = p - 1;
int i, j;
size_t fbytes = sizeof(float);
float * X = (float *)malloc(n*p*fbytes);
float * dX, * dColNorms;
int nblocks, nthreads = NTHREADS;
const unsigned blockExp = 7;
unsigned int blockSize = 1 << blockExp;
int stride = (n + blockSize - 1) & (((unsigned) -1) << blockExp);
float * dscales;
float * dBeta;
float * dqrAux;
int * dpivot;
float * dWtR;
int * drank;
float * dV;
float * dW;
float * dT;
float * du;
for(i=0; i<n; i++)
for(j=0; j<p; j++)
X[i + j*n] = i + j;
printf("\n X \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
cudaMalloc( (void **)&dX, n*p*fbytes );
cudaMalloc( (void **)&dColNorms, p*fbytes);
cudaMalloc( (void **)&dscales, blockSize*fbytes);
cudaMalloc( (void **)&dBeta, blockSize*fbytes);
cudaMalloc( (void **)&dqrAux, p*fbytes);
cudaMalloc( (void **)&dpivot, p*sizeof(int));
cudaMalloc( (void **)&dWtR, blockSize*(p - blockSize)*fbytes);
cudaMalloc( (void **)&drank, sizeof(int));
cudaMalloc( (void **)&dV, blockSize*stride*fbytes);
cudaMalloc( (void **)&dW, blockSize*stride*fbytes);
cudaMalloc( (void **)&dT, blockSize*blockSize*fbytes);
cudaMalloc( (void **)&du, stride*fbytes);
cudaMemcpy( dX, X, n*p*fbytes, cudaMemcpyHostToDevice);
nblocks = p / nthreads;
if(nblocks * nthreads < p)
nblocks++;
getColNorms<<<nblocks, nthreads>>>(n, p, dX, dColNorms);
GetQRDecompBlocked<<<1,1>>>(n, p, dX, dColNorms, blockSize, stride, dscales, dBeta,
dqrAux, dpivot, dWtR, drank, dV, dW, dT, du);
cudaMemcpy( X, dX, n*p*fbytes, cudaMemcpyDeviceToHost);
printf("\n R \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
cudaFree(dX);
cudaFree(dColNorms);
free(X);
cudaFree(dscales);
cudaFree(dBeta);
cudaFree(dqrAux);
cudaFree(dpivot);
cudaFree(dWtR);
cudaFree(drank);
cudaFree(dV);
cudaFree(dW);
cudaFree(dT);
cudaFree(du);
return 0;
} | .file "tmpxft_00162aa9_00000000-6_qrdecomp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4cXtvfiiPfiS_S_
.type _Z4cXtvfiiPfiS_S_, @function
_Z4cXtvfiiPfiS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4cXtvfiiPfiS_S_, .-_Z4cXtvfiiPfiS_S_
.globl _Z5XpvutiiPfiS_S_
.type _Z5XpvutiiPfiS_S_, @function
_Z5XpvutiiPfiS_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5XpvutiiPfiS_S_, .-_Z5XpvutiiPfiS_S_
.globl _Z4uVtViiPfS_
.type _Z4uVtViiPfS_, @function
_Z4uVtViiPfS_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z4uVtViiPfS_, .-_Z4uVtViiPfS_
.globl _Z10alignBlockij
.type _Z10alignBlockij, @function
_Z10alignBlockij:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z10alignBlockij, .-_Z10alignBlockij
.globl _Z7colswapPfiiii
.type _Z7colswapPfiiii, @function
_Z7colswapPfiiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z7colswapPfiiii, .-_Z7colswapPfiiii
.globl _Z9getMaxIdxiPfi
.type _Z9getMaxIdxiPfi, @function
_Z9getMaxIdxiPfi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z9getMaxIdxiPfi, .-_Z9getMaxIdxiPfi
.globl _Z3idxiii
.type _Z3idxiii, @function
_Z3idxiii:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z3idxiii, .-_Z3idxiii
.globl _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
.type _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_, @function
_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11getColNormsiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_, .-_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
.globl _Z11getColNormsiiPfS_
.type _Z11getColNormsiiPfS_, @function
_Z11getColNormsiiPfS_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z11getColNormsiiPfS_, .-_Z11getColNormsiiPfS_
.globl _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.type _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_, @function
_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movl %edi, 108(%rsp)
movl %esi, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movl %r8d, 84(%rsp)
movl %r9d, 80(%rsp)
movq 336(%rsp), %rax
movq %rax, 72(%rsp)
movq 344(%rsp), %rax
movq %rax, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 376(%rsp), %rax
movq %rax, 32(%rsp)
movq 384(%rsp), %rax
movq %rax, 24(%rsp)
movq 392(%rsp), %rax
movq %rax, 16(%rsp)
movq 400(%rsp), %rax
movq %rax, 8(%rsp)
movq 408(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 84(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 32(%rsp), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 8(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .-_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.globl _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.type _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, @function
_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 88(%rsp)
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .-_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n X \n"
.LC1:
.string "%.f "
.LC2:
.string "\n"
.LC3:
.string "\n R \n"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, %rdi
movl $5, %ecx
movl $0, %esi
jmp .L34
.L50:
addl $1, %esi
addq $4, %rdi
addl $1, %ecx
cmpl $10, %esi
je .L36
.L34:
movl %esi, %eax
movq %rdi, %rdx
.L35:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
addl $1, %eax
addq $40, %rdx
cmpl %ecx, %eax
jne .L35
jmp .L50
.L36:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 200(%rax), %rbp
movq %rbp, %r12
movl $0, %r14d
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
jmp .L37
.L51:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq $4, %r12
cmpl $10, %r14d
je .L39
.L37:
leaq -200(%r12), %rbx
.L38:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $40, %rbx
cmpq %r12, %rbx
jne .L38
jmp .L51
.L39:
leaq 16(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movabsq $17179806208, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L40:
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
movl $2, %ecx
movl $200, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r14
jmp .L42
.L52:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl $5, %esi
movl $10, %edi
call _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
jmp .L40
.L53:
pushq 104(%rsp)
.cfi_def_cfa_offset 216
pushq 104(%rsp)
.cfi_def_cfa_offset 224
pushq 104(%rsp)
.cfi_def_cfa_offset 232
pushq 104(%rsp)
.cfi_def_cfa_offset 240
pushq 104(%rsp)
.cfi_def_cfa_offset 248
pushq 104(%rsp)
.cfi_def_cfa_offset 256
pushq 104(%rsp)
.cfi_def_cfa_offset 264
pushq 104(%rsp)
.cfi_def_cfa_offset 272
pushq 104(%rsp)
.cfi_def_cfa_offset 280
pushq 104(%rsp)
.cfi_def_cfa_offset 288
movl $128, %r9d
movl $128, %r8d
movq 104(%rsp), %rcx
movq 96(%rsp), %rdx
movl $5, %esi
movl $10, %edi
call _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
addq $80, %rsp
.cfi_def_cfa_offset 208
jmp .L41
.L54:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $4, %rbp
cmpl $10, %r13d
je .L44
.L42:
leaq -200(%rbp), %rbx
.L43:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $40, %rbx
cmpq %rbp, %rbx
jne .L43
jmp .L54
.L44:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_"
.section .rodata.str1.1
.LC5:
.string "_Z11getColNormsiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11getColNormsiiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<string.h>
//#include<cublas.h>
//#include<R.h>
#define NTHREADS 512
//computes u = constant * t(X) %*% v
__device__ void cXtv(float con, int rows, int cols, float * X, int ldX, float * v,
float * u){
int i,k;
float sum;
for(k = 0; k < cols; k++){
sum = 0;
for(i = 0; i < rows; i++){
sum += X[i + k*ldX] * v[i];
}
u[k] = con*sum;
}
}
//computes X = X + v %*% u'
__device__ void Xpvut(int rows, int cols, float * X, int ldX, float *v, float *u){
int i, j;
for(i=0; i<rows; i++)
for(j=0; j<cols; j++)
X[i + j*ldX] += v[i] * u[j];
}
//calculates T = V'V where V is upper triangular
__device__ void uVtV(int rows, int cols, float * V, float * T){
int i, j, k;
float sum;
for(i=0; i<cols; i++){
for(j=0; j<cols; j++){
sum = 0;
for(k=0; k<min(i,j); k++)
sum += V[k + i*rows] * V[k + j*rows];
T[i + j*cols] = sum;
}
}
}
//Rounds "length" up the the next multiple of block length
__device__ int alignBlock(int length, unsigned blockExp){
int blockSize = 1 << blockExp;
int out = (length + blockSize - 1) & ( ( (unsigned) - 1) << blockExp);
return out;
}
__device__ void colswap(float *X, int n, int p, int i, int j){
float tmp;
int k;
float * Xi = X + i*n;
float * Xj = X + i*j;
if(i <= p && j <= p){
for(k = 0; k < n; k++){
tmp = Xi[k];
Xi[k] = Xj[k];
Xj[k] = tmp;
}
}
}
__device__ int getMaxIdx(int p, float * ColNorms, int id){
int maxIdx = 0, i, bit;
float max = ColNorms[maxIdx], tmp;
for(i = 1; i < p; i++){
bit = ( id & (1 << i) ) >> 1;
if( bit == 1){
tmp = ColNorms[i];
if(tmp > max){
max = tmp;
maxIdx = i;
}
}
}
return maxIdx;
}
__device__ int idx(int id, int p, int i){
int j, colcount=0, out;
for(j=0; j<p; j++){
if(colcount == i)
out = j;
if( ( id & ( 1 << j ) ) >> j == 1)
colcount += 1;
}
return out;
}
__global__ void getColNorms(int rows, int cols, float * dX, float * ColNorms){
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float sum = 0.f, term, * col;
if(colIndex >= cols)
return;
col = dX + colIndex * rows;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
ColNorms[colIndex] = sqrtf(sum);
}
__global__ void GetQRDecompBlocked(int n, int p, float * X, float * ColNorms,
unsigned int blockSize, int stride, float * scales,
float * Beta, float * qrAux, int * pivot,
float * WtR, int * rank, float * V, float * W,
float * T, float * u){
float tol = 0.0001; //float tolerance
int blockCount, blockEnd = 0, bc, i, kp; //kp is # cols processed
//unsigned int id = threadIDx.x + blockIDx.x * blockDim.x;
int varcount = 0, maxIdx, pm = 1;
//unsigned int * binid;
float * Xm; //model id's model matrix; will eventually contain R in QR decomp
//float * pXcol = X; //pointer to column of X
float * pXmcol; //pointer to column of Xm
float maxNorm;
float * pXmBlock; //pointer to block of Xm
size_t fbytes = sizeof(float);
int rk = 0; // Local value of rank;
int maxRank; //maximum possible rank of the model matrix
float minElt; // Lowest acceptable norm under given tolerance.
int maxCol; //this will be initialized to pm - 1, highest candidate column, not fixed
int maxRow = n - 1;
int rowskp = stride; // # unprocessed rows = stride - kp
int colskp; // # unprocessed cols = cols - kp
float *pVcol; //pointer to column of V
float *pVdiag; //pointer to diagonal element of V
float *pXmdiag; //pointer to diagonal element of dQRBlock
int colIdx;
int a,b;
int l;
//if(id > M)
// return;
//binid = (unsigned int *)calloc(p-1, sizeof(unsigned int));
/*
//copies the relevant columns of X into Xm
do{
int jump = 0;
unsigned int bit = 0;
memcpy(pXmcol, pXcol, n*fbytes); //copy the current column
//any time we copy any column but the first, set binid[col] = 1
if(varcount > 0){
binid[p - varcount] = 1; //actual index is (p - 1) - (varcount - 1)
pm += 1;
}
pXmcol += n; //update pointer on Xm to the next column
//bitwise operations on id to find proper columns
//look for the next used column of X
do{
jump += 1; //increment number of columns of X to move forward
varcount += 1; //increment number of total vars of X checked
//note: each column of X but the first represents a variable
//set bit as the k'th bit of id (1st bit is far right)
bit = ( id & ( 1 << varcount ) ) >> varcount;
//alternative code: declare tmpid above first.
////bit = tmpid & 1; //bit = 1 if last bit of tmpid is 1, 0 otherwise
////tmpid = tmpid >> 1; //bitshift tmpid right - lopping off last bit
}
while(bit == 0 && varcount < p);
pXcol += n*jump; //update pointer on X to the next used column
}
while(varcount < p );
//if varcount = k ( = p - 1 ), we still have to copy this last column, so the
//loop must iterate again
*/
pm = p;
//initialize variables that depend on pm and Xm
//Xm = (float *) calloc(stride*pm,fbytes); //allocate memory for model matrix
Xm = X;
pXmcol = Xm;
pXmBlock = Xm;
maxCol = pm - 1; //maximum possible column
colskp = pm;
maxIdx = getMaxIdx(p, ColNorms, (1 << pm) - 1);
//id);
maxNorm = ColNorms[maxIdx];
if (maxNorm < tol){
maxRank = 0; // Short-circuits the main pivot loop
}
else{
minElt = (1.0 + maxNorm) * tol;
maxRank = n > pm ? pm : n; //min(n,pm)
}
blockCount = (pm + blockSize - 1) / blockSize;
for(bc = 0; bc < blockCount; bc++){
// Determines "blockEnd", which counts the number of columns remaining
// in the upcoming block. Swaps trivial columns with the rightmost
// unvisited column until either a nontrivial column is found or all
// columns have been visited. Note that 'blockEnd <= blockSize', with
// inequality possible only in the rightmost processed block.
//
// This pivoting scheme does not attempt to order columns by norm, nor
// does it recompute norms altered by the rank-one update within the
// upcoming block. A higher-fidelity scheme is implemented in the non-
// blocked form of this function. Sapienti sat.
blockEnd = 0;
for(i = kp; i < kp + blockSize && i < maxRank && i <= maxCol; i++){
float colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
while( (colNorm < minElt) && (maxCol > i) ){
//while colNorm is smaller than the lowest acceptable norm, given tolerance
//and while the maximum column possible is larger than the current column
//keep track of column swap in pivot vector
int tempIdx = pivot[maxCol];
//exchange columns of Xm: current column and maxCol
colswap(Xm, stride, pm, i, maxCol);
pivot[maxCol] = pivot[i];
pivot[i] = tempIdx;
maxCol--;
//set new colNorm as norm of max column, now in i'th spot
colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
}
if (colNorm >= minElt)
blockEnd++;
}
rk += blockEnd;
//set V to 0 everywhere
for(a=0; a<blockSize; a++)
for(b=0; b<rowskp; b++)
*(V + b + a*rowskp) = 0;
pVcol = V; //pointer to column of V
pVdiag = V; //pointer to diagonal element of V
pXmdiag = pXmBlock; //pointer to diagonal element of XmBlock
for(colIdx = 0; colIdx < blockEnd; colIdx++){
float v1;
float v1Abs;
memcpy(pVdiag, pXmdiag, (rowskp - colIdx)*fbytes);
// Builds Householder vector from maximal column just copied.
// For now, uses slow memory transfers to modify leading element:
// V_1 += sign(V_1) * normV.
v1 = *pVdiag;
v1Abs = fabs(v1);
if(kp == maxRow)//botom row is not scaled
qrAux[kp] = v1Abs;
else{ // zero-valued "normV" should already have been ruled out.
int d;
float normV = 0;
float recipNormV;
float fac;
for(d=0; d < rowskp - colIdx; d++){
float diag = pVdiag[d];
normV += diag*diag;
}
normV = sqrtf(normV);
recipNormV = 1.0 / normV;
qrAux[kp] = 1.0 + v1Abs * recipNormV;
scales[colIdx] = (v1 >= 0.f ? 1.f : -1.f) * recipNormV;
// Scales leading nonzero element of vector.
fac = 1.0 + normV / v1Abs;
*pVdiag *= fac;
Beta[colIdx] = -2.0 / (normV * normV + v1Abs * (-1.0 + fac * fac));
// u = Beta[colIdx] * t(pXmBlock) %*% pVcol
// rows of pXmBlock = rowskp
// cols of pXmBlock = min(blockSize, colskp)
// leading dimension of pXmBlock = stride
// elements of pVcol = rowskp
// elements of u = min(blockSize, colskp)
cXtv(Beta[colIdx], rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
//pXmBlock = pXmBlock + pVcol %*% u'
//rows of pXmBlock = rowskp
//cols of pXmBlock = min(blockSize, colsk)
//elements of pVcol = rowskp
//elements of u = min(blockSize, colsk)
//leading dim of pXmBlock = stride
Xpvut(rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
}
pVcol += rowskp;
pVdiag += (rowskp + 1);
pXmdiag += (stride + 1);
kp++;
}
// If more unseen columns remain, updates the remainder of QR lying to
// the right of the block just updated. This must be done unless we
// happen to have exited the inner loop without having applied any
// Householder transformations (i.e., blockEnd == 0).
if (bc < blockCount - 1 && blockEnd > 0) {
// w_m = Beta (I + W V^t) v_m, where the unsubscripted matrices
// refer to those built at step 'i-1', having 'i' columns.
//
// w_i = Beta v_i
//
float *pTcol = T; //pointer to columns of dT
float *pWcol = W; //pointer to columns of dW
int m, a, b, c;
pVcol = V; //pointer to columns of dV
// T = V^t V
//// T = dT
//// V = dV
//rows of V' = blockSize
//cols of V' = rowsk
//leading dim of V = rowsk
//leading dim of T = rowsk
//rows/cols of T = blockSize
uVtV(rowskp, blockSize, V, T);
for (m = 0; m < blockSize; m++, pWcol += rowskp, pVcol += rowskp,
pTcol += blockSize) {
//for m=0,1,..., blockSize - 1
//pdWcol += rowsk
//pdVcol += rowsk
//pdTcol += blockSize
int a;
for(a = 0; a<rowskp; a++)
pWcol[a] = Beta[m]*pVcol[a];
// w_m = w_m + Beta W T(.,m)
//// w_m = pWcol
//// Beta = Beta[m]
//// T(.,m) = pTcol
//// W = dW
if (m > 0) {
int a, b;
for(a = 0; a < rowskp; a++){
float sum = 0;
for(b = 0; b < m; b++){
sum += W[b + a*m] * pTcol[b];
}
pWcol[a] += sum;
}
}
}
// Updates R, beginning at current diagonal by:
// R = (I_m + V W^t) R = R + V (W^t R)
//
// WtR = W^t R
//// WtR = dWtR
//// W = dW
//W is rowskp by blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
//WtR is blockSize by colsk - blockSize
for(a = 0; a < blockSize; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < rowskp; c++)
sum += W[c + rowskp*a] * *(pXmBlock + blockSize*stride + c + b*rowskp);
WtR[a + b*blockSize] = sum;
}
}
// R = V WtR + R
//// V = dV
//// WtR = dWtR
//// R = pdQRBlock + blockSize*stride
// V is rowskp by blockSize
//WtR is blockSize by colskp - blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
for(a = 0; a < rowskp; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < blockSize; c++){
sum += V[a + c*rowskp] * WtR[c + b*blockSize];
}
*(pXmBlock + blockSize*stride + a + b*rowskp) += sum;
}
}
}
// Flushes scaled Householder vectors to the subdiagonals of dQR,
// 'blockSize'-many at a time. The only time a smaller number are
// sent occurs when a partial block remains at the right end.
//
pVdiag = V; //pointer to diagonal of V
pXmdiag = pXmBlock; //pointer to diagonal of pXmBlock / XmBlock
for (l = 0; l < blockEnd; l++, pVdiag += (rowskp + 1),
pXmdiag += (stride + 1)) {
//for l = 0, 1, ..., blockEnd - 1
//// pVdiag += (rowskp + 1)
//// pXmdiag += (stride +1)
int a;
//pVdiag + 1 = scales[l]* (pVdiag + 1)
//pXmdiag + 1 = pVdiag + 1
for(a = 0; a < rowskp - l - 1; a++){
*(pVdiag + 1 + a) *= scales[l];
*(pXmdiag + 1 + a) = *(pVdiag + 1 + a);
}
}
pXmBlock += blockSize * (stride + 1);
colskp -= blockSize;
rowskp -= blockSize;
//end main loop
}
//set rank
*rank = rk;
// Xm now contains the upper-triangular portion of the factorization,
// R.
// V is lower-triangular, and contains the Householder vectors, from
// which the Q portion can be derived. An adjusted form of the
// diagonal is saved in qrAux, while the sub-diagonal portion is
// written onto QR.
}
int main(void){
int n = 10, p = 5;
//, k = p - 1;
int i, j;
size_t fbytes = sizeof(float);
float * X = (float *)malloc(n*p*fbytes);
float * dX, * dColNorms;
int nblocks, nthreads = NTHREADS;
const unsigned blockExp = 7;
unsigned int blockSize = 1 << blockExp;
int stride = (n + blockSize - 1) & (((unsigned) -1) << blockExp);
float * dscales;
float * dBeta;
float * dqrAux;
int * dpivot;
float * dWtR;
int * drank;
float * dV;
float * dW;
float * dT;
float * du;
for(i=0; i<n; i++)
for(j=0; j<p; j++)
X[i + j*n] = i + j;
printf("\n X \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
cudaMalloc( (void **)&dX, n*p*fbytes );
cudaMalloc( (void **)&dColNorms, p*fbytes);
cudaMalloc( (void **)&dscales, blockSize*fbytes);
cudaMalloc( (void **)&dBeta, blockSize*fbytes);
cudaMalloc( (void **)&dqrAux, p*fbytes);
cudaMalloc( (void **)&dpivot, p*sizeof(int));
cudaMalloc( (void **)&dWtR, blockSize*(p - blockSize)*fbytes);
cudaMalloc( (void **)&drank, sizeof(int));
cudaMalloc( (void **)&dV, blockSize*stride*fbytes);
cudaMalloc( (void **)&dW, blockSize*stride*fbytes);
cudaMalloc( (void **)&dT, blockSize*blockSize*fbytes);
cudaMalloc( (void **)&du, stride*fbytes);
cudaMemcpy( dX, X, n*p*fbytes, cudaMemcpyHostToDevice);
nblocks = p / nthreads;
if(nblocks * nthreads < p)
nblocks++;
getColNorms<<<nblocks, nthreads>>>(n, p, dX, dColNorms);
GetQRDecompBlocked<<<1,1>>>(n, p, dX, dColNorms, blockSize, stride, dscales, dBeta,
dqrAux, dpivot, dWtR, drank, dV, dW, dT, du);
cudaMemcpy( X, dX, n*p*fbytes, cudaMemcpyDeviceToHost);
printf("\n R \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
cudaFree(dX);
cudaFree(dColNorms);
free(X);
cudaFree(dscales);
cudaFree(dBeta);
cudaFree(dqrAux);
cudaFree(dpivot);
cudaFree(dWtR);
cudaFree(drank);
cudaFree(dV);
cudaFree(dW);
cudaFree(dT);
cudaFree(du);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<string.h>
//#include<cublas.h>
//#include<R.h>
#define NTHREADS 512
//computes u = constant * t(X) %*% v
__device__ void cXtv(float con, int rows, int cols, float * X, int ldX, float * v,
float * u){
int i,k;
float sum;
for(k = 0; k < cols; k++){
sum = 0;
for(i = 0; i < rows; i++){
sum += X[i + k*ldX] * v[i];
}
u[k] = con*sum;
}
}
//computes X = X + v %*% u'
__device__ void Xpvut(int rows, int cols, float * X, int ldX, float *v, float *u){
int i, j;
for(i=0; i<rows; i++)
for(j=0; j<cols; j++)
X[i + j*ldX] += v[i] * u[j];
}
//calculates T = V'V where V is upper triangular
__device__ void uVtV(int rows, int cols, float * V, float * T){
int i, j, k;
float sum;
for(i=0; i<cols; i++){
for(j=0; j<cols; j++){
sum = 0;
for(k=0; k<min(i,j); k++)
sum += V[k + i*rows] * V[k + j*rows];
T[i + j*cols] = sum;
}
}
}
//Rounds "length" up the the next multiple of block length
__device__ int alignBlock(int length, unsigned blockExp){
int blockSize = 1 << blockExp;
int out = (length + blockSize - 1) & ( ( (unsigned) - 1) << blockExp);
return out;
}
__device__ void colswap(float *X, int n, int p, int i, int j){
float tmp;
int k;
float * Xi = X + i*n;
float * Xj = X + i*j;
if(i <= p && j <= p){
for(k = 0; k < n; k++){
tmp = Xi[k];
Xi[k] = Xj[k];
Xj[k] = tmp;
}
}
}
__device__ int getMaxIdx(int p, float * ColNorms, int id){
int maxIdx = 0, i, bit;
float max = ColNorms[maxIdx], tmp;
for(i = 1; i < p; i++){
bit = ( id & (1 << i) ) >> 1;
if( bit == 1){
tmp = ColNorms[i];
if(tmp > max){
max = tmp;
maxIdx = i;
}
}
}
return maxIdx;
}
__device__ int idx(int id, int p, int i){
int j, colcount=0, out;
for(j=0; j<p; j++){
if(colcount == i)
out = j;
if( ( id & ( 1 << j ) ) >> j == 1)
colcount += 1;
}
return out;
}
__global__ void getColNorms(int rows, int cols, float * dX, float * ColNorms){
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float sum = 0.f, term, * col;
if(colIndex >= cols)
return;
col = dX + colIndex * rows;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
ColNorms[colIndex] = sqrtf(sum);
}
__global__ void GetQRDecompBlocked(int n, int p, float * X, float * ColNorms,
unsigned int blockSize, int stride, float * scales,
float * Beta, float * qrAux, int * pivot,
float * WtR, int * rank, float * V, float * W,
float * T, float * u){
float tol = 0.0001; //float tolerance
int blockCount, blockEnd = 0, bc, i, kp; //kp is # cols processed
//unsigned int id = threadIDx.x + blockIDx.x * blockDim.x;
int varcount = 0, maxIdx, pm = 1;
//unsigned int * binid;
float * Xm; //model id's model matrix; will eventually contain R in QR decomp
//float * pXcol = X; //pointer to column of X
float * pXmcol; //pointer to column of Xm
float maxNorm;
float * pXmBlock; //pointer to block of Xm
size_t fbytes = sizeof(float);
int rk = 0; // Local value of rank;
int maxRank; //maximum possible rank of the model matrix
float minElt; // Lowest acceptable norm under given tolerance.
int maxCol; //this will be initialized to pm - 1, highest candidate column, not fixed
int maxRow = n - 1;
int rowskp = stride; // # unprocessed rows = stride - kp
int colskp; // # unprocessed cols = cols - kp
float *pVcol; //pointer to column of V
float *pVdiag; //pointer to diagonal element of V
float *pXmdiag; //pointer to diagonal element of dQRBlock
int colIdx;
int a,b;
int l;
//if(id > M)
// return;
//binid = (unsigned int *)calloc(p-1, sizeof(unsigned int));
/*
//copies the relevant columns of X into Xm
do{
int jump = 0;
unsigned int bit = 0;
memcpy(pXmcol, pXcol, n*fbytes); //copy the current column
//any time we copy any column but the first, set binid[col] = 1
if(varcount > 0){
binid[p - varcount] = 1; //actual index is (p - 1) - (varcount - 1)
pm += 1;
}
pXmcol += n; //update pointer on Xm to the next column
//bitwise operations on id to find proper columns
//look for the next used column of X
do{
jump += 1; //increment number of columns of X to move forward
varcount += 1; //increment number of total vars of X checked
//note: each column of X but the first represents a variable
//set bit as the k'th bit of id (1st bit is far right)
bit = ( id & ( 1 << varcount ) ) >> varcount;
//alternative code: declare tmpid above first.
////bit = tmpid & 1; //bit = 1 if last bit of tmpid is 1, 0 otherwise
////tmpid = tmpid >> 1; //bitshift tmpid right - lopping off last bit
}
while(bit == 0 && varcount < p);
pXcol += n*jump; //update pointer on X to the next used column
}
while(varcount < p );
//if varcount = k ( = p - 1 ), we still have to copy this last column, so the
//loop must iterate again
*/
pm = p;
//initialize variables that depend on pm and Xm
//Xm = (float *) calloc(stride*pm,fbytes); //allocate memory for model matrix
Xm = X;
pXmcol = Xm;
pXmBlock = Xm;
maxCol = pm - 1; //maximum possible column
colskp = pm;
maxIdx = getMaxIdx(p, ColNorms, (1 << pm) - 1);
//id);
maxNorm = ColNorms[maxIdx];
if (maxNorm < tol){
maxRank = 0; // Short-circuits the main pivot loop
}
else{
minElt = (1.0 + maxNorm) * tol;
maxRank = n > pm ? pm : n; //min(n,pm)
}
blockCount = (pm + blockSize - 1) / blockSize;
for(bc = 0; bc < blockCount; bc++){
// Determines "blockEnd", which counts the number of columns remaining
// in the upcoming block. Swaps trivial columns with the rightmost
// unvisited column until either a nontrivial column is found or all
// columns have been visited. Note that 'blockEnd <= blockSize', with
// inequality possible only in the rightmost processed block.
//
// This pivoting scheme does not attempt to order columns by norm, nor
// does it recompute norms altered by the rank-one update within the
// upcoming block. A higher-fidelity scheme is implemented in the non-
// blocked form of this function. Sapienti sat.
blockEnd = 0;
for(i = kp; i < kp + blockSize && i < maxRank && i <= maxCol; i++){
float colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
while( (colNorm < minElt) && (maxCol > i) ){
//while colNorm is smaller than the lowest acceptable norm, given tolerance
//and while the maximum column possible is larger than the current column
//keep track of column swap in pivot vector
int tempIdx = pivot[maxCol];
//exchange columns of Xm: current column and maxCol
colswap(Xm, stride, pm, i, maxCol);
pivot[maxCol] = pivot[i];
pivot[i] = tempIdx;
maxCol--;
//set new colNorm as norm of max column, now in i'th spot
colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
}
if (colNorm >= minElt)
blockEnd++;
}
rk += blockEnd;
//set V to 0 everywhere
for(a=0; a<blockSize; a++)
for(b=0; b<rowskp; b++)
*(V + b + a*rowskp) = 0;
pVcol = V; //pointer to column of V
pVdiag = V; //pointer to diagonal element of V
pXmdiag = pXmBlock; //pointer to diagonal element of XmBlock
for(colIdx = 0; colIdx < blockEnd; colIdx++){
float v1;
float v1Abs;
memcpy(pVdiag, pXmdiag, (rowskp - colIdx)*fbytes);
// Builds Householder vector from maximal column just copied.
// For now, uses slow memory transfers to modify leading element:
// V_1 += sign(V_1) * normV.
v1 = *pVdiag;
v1Abs = fabs(v1);
if(kp == maxRow)//botom row is not scaled
qrAux[kp] = v1Abs;
else{ // zero-valued "normV" should already have been ruled out.
int d;
float normV = 0;
float recipNormV;
float fac;
for(d=0; d < rowskp - colIdx; d++){
float diag = pVdiag[d];
normV += diag*diag;
}
normV = sqrtf(normV);
recipNormV = 1.0 / normV;
qrAux[kp] = 1.0 + v1Abs * recipNormV;
scales[colIdx] = (v1 >= 0.f ? 1.f : -1.f) * recipNormV;
// Scales leading nonzero element of vector.
fac = 1.0 + normV / v1Abs;
*pVdiag *= fac;
Beta[colIdx] = -2.0 / (normV * normV + v1Abs * (-1.0 + fac * fac));
// u = Beta[colIdx] * t(pXmBlock) %*% pVcol
// rows of pXmBlock = rowskp
// cols of pXmBlock = min(blockSize, colskp)
// leading dimension of pXmBlock = stride
// elements of pVcol = rowskp
// elements of u = min(blockSize, colskp)
cXtv(Beta[colIdx], rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
//pXmBlock = pXmBlock + pVcol %*% u'
//rows of pXmBlock = rowskp
//cols of pXmBlock = min(blockSize, colsk)
//elements of pVcol = rowskp
//elements of u = min(blockSize, colsk)
//leading dim of pXmBlock = stride
Xpvut(rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
}
pVcol += rowskp;
pVdiag += (rowskp + 1);
pXmdiag += (stride + 1);
kp++;
}
// If more unseen columns remain, updates the remainder of QR lying to
// the right of the block just updated. This must be done unless we
// happen to have exited the inner loop without having applied any
// Householder transformations (i.e., blockEnd == 0).
if (bc < blockCount - 1 && blockEnd > 0) {
// w_m = Beta (I + W V^t) v_m, where the unsubscripted matrices
// refer to those built at step 'i-1', having 'i' columns.
//
// w_i = Beta v_i
//
float *pTcol = T; //pointer to columns of dT
float *pWcol = W; //pointer to columns of dW
int m, a, b, c;
pVcol = V; //pointer to columns of dV
// T = V^t V
//// T = dT
//// V = dV
//rows of V' = blockSize
//cols of V' = rowsk
//leading dim of V = rowsk
//leading dim of T = rowsk
//rows/cols of T = blockSize
uVtV(rowskp, blockSize, V, T);
for (m = 0; m < blockSize; m++, pWcol += rowskp, pVcol += rowskp,
pTcol += blockSize) {
//for m=0,1,..., blockSize - 1
//pdWcol += rowsk
//pdVcol += rowsk
//pdTcol += blockSize
int a;
for(a = 0; a<rowskp; a++)
pWcol[a] = Beta[m]*pVcol[a];
// w_m = w_m + Beta W T(.,m)
//// w_m = pWcol
//// Beta = Beta[m]
//// T(.,m) = pTcol
//// W = dW
if (m > 0) {
int a, b;
for(a = 0; a < rowskp; a++){
float sum = 0;
for(b = 0; b < m; b++){
sum += W[b + a*m] * pTcol[b];
}
pWcol[a] += sum;
}
}
}
// Updates R, beginning at current diagonal by:
// R = (I_m + V W^t) R = R + V (W^t R)
//
// WtR = W^t R
//// WtR = dWtR
//// W = dW
//W is rowskp by blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
//WtR is blockSize by colsk - blockSize
for(a = 0; a < blockSize; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < rowskp; c++)
sum += W[c + rowskp*a] * *(pXmBlock + blockSize*stride + c + b*rowskp);
WtR[a + b*blockSize] = sum;
}
}
// R = V WtR + R
//// V = dV
//// WtR = dWtR
//// R = pdQRBlock + blockSize*stride
// V is rowskp by blockSize
//WtR is blockSize by colskp - blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
for(a = 0; a < rowskp; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < blockSize; c++){
sum += V[a + c*rowskp] * WtR[c + b*blockSize];
}
*(pXmBlock + blockSize*stride + a + b*rowskp) += sum;
}
}
}
// Flushes scaled Householder vectors to the subdiagonals of dQR,
// 'blockSize'-many at a time. The only time a smaller number are
// sent occurs when a partial block remains at the right end.
//
pVdiag = V; //pointer to diagonal of V
pXmdiag = pXmBlock; //pointer to diagonal of pXmBlock / XmBlock
for (l = 0; l < blockEnd; l++, pVdiag += (rowskp + 1),
pXmdiag += (stride + 1)) {
//for l = 0, 1, ..., blockEnd - 1
//// pVdiag += (rowskp + 1)
//// pXmdiag += (stride +1)
int a;
//pVdiag + 1 = scales[l]* (pVdiag + 1)
//pXmdiag + 1 = pVdiag + 1
for(a = 0; a < rowskp - l - 1; a++){
*(pVdiag + 1 + a) *= scales[l];
*(pXmdiag + 1 + a) = *(pVdiag + 1 + a);
}
}
pXmBlock += blockSize * (stride + 1);
colskp -= blockSize;
rowskp -= blockSize;
//end main loop
}
//set rank
*rank = rk;
// Xm now contains the upper-triangular portion of the factorization,
// R.
// V is lower-triangular, and contains the Householder vectors, from
// which the Q portion can be derived. An adjusted form of the
// diagonal is saved in qrAux, while the sub-diagonal portion is
// written onto QR.
}
int main(void){
int n = 10, p = 5;
//, k = p - 1;
int i, j;
size_t fbytes = sizeof(float);
float * X = (float *)malloc(n*p*fbytes);
float * dX, * dColNorms;
int nblocks, nthreads = NTHREADS;
const unsigned blockExp = 7;
unsigned int blockSize = 1 << blockExp;
int stride = (n + blockSize - 1) & (((unsigned) -1) << blockExp);
float * dscales;
float * dBeta;
float * dqrAux;
int * dpivot;
float * dWtR;
int * drank;
float * dV;
float * dW;
float * dT;
float * du;
for(i=0; i<n; i++)
for(j=0; j<p; j++)
X[i + j*n] = i + j;
printf("\n X \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
hipMalloc( (void **)&dX, n*p*fbytes );
hipMalloc( (void **)&dColNorms, p*fbytes);
hipMalloc( (void **)&dscales, blockSize*fbytes);
hipMalloc( (void **)&dBeta, blockSize*fbytes);
hipMalloc( (void **)&dqrAux, p*fbytes);
hipMalloc( (void **)&dpivot, p*sizeof(int));
hipMalloc( (void **)&dWtR, blockSize*(p - blockSize)*fbytes);
hipMalloc( (void **)&drank, sizeof(int));
hipMalloc( (void **)&dV, blockSize*stride*fbytes);
hipMalloc( (void **)&dW, blockSize*stride*fbytes);
hipMalloc( (void **)&dT, blockSize*blockSize*fbytes);
hipMalloc( (void **)&du, stride*fbytes);
hipMemcpy( dX, X, n*p*fbytes, hipMemcpyHostToDevice);
nblocks = p / nthreads;
if(nblocks * nthreads < p)
nblocks++;
getColNorms<<<nblocks, nthreads>>>(n, p, dX, dColNorms);
GetQRDecompBlocked<<<1,1>>>(n, p, dX, dColNorms, blockSize, stride, dscales, dBeta,
dqrAux, dpivot, dWtR, drank, dV, dW, dT, du);
hipMemcpy( X, dX, n*p*fbytes, hipMemcpyDeviceToHost);
printf("\n R \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
hipFree(dX);
hipFree(dColNorms);
free(X);
hipFree(dscales);
hipFree(dBeta);
hipFree(dqrAux);
hipFree(dpivot);
hipFree(dWtR);
hipFree(drank);
hipFree(dV);
hipFree(dW);
hipFree(dT);
hipFree(du);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<string.h>
//#include<cublas.h>
//#include<R.h>
#define NTHREADS 512
//computes u = constant * t(X) %*% v
__device__ void cXtv(float con, int rows, int cols, float * X, int ldX, float * v,
float * u){
int i,k;
float sum;
for(k = 0; k < cols; k++){
sum = 0;
for(i = 0; i < rows; i++){
sum += X[i + k*ldX] * v[i];
}
u[k] = con*sum;
}
}
//computes X = X + v %*% u'
__device__ void Xpvut(int rows, int cols, float * X, int ldX, float *v, float *u){
int i, j;
for(i=0; i<rows; i++)
for(j=0; j<cols; j++)
X[i + j*ldX] += v[i] * u[j];
}
//calculates T = V'V where V is upper triangular
__device__ void uVtV(int rows, int cols, float * V, float * T){
int i, j, k;
float sum;
for(i=0; i<cols; i++){
for(j=0; j<cols; j++){
sum = 0;
for(k=0; k<min(i,j); k++)
sum += V[k + i*rows] * V[k + j*rows];
T[i + j*cols] = sum;
}
}
}
//Rounds "length" up the the next multiple of block length
__device__ int alignBlock(int length, unsigned blockExp){
int blockSize = 1 << blockExp;
int out = (length + blockSize - 1) & ( ( (unsigned) - 1) << blockExp);
return out;
}
__device__ void colswap(float *X, int n, int p, int i, int j){
float tmp;
int k;
float * Xi = X + i*n;
float * Xj = X + i*j;
if(i <= p && j <= p){
for(k = 0; k < n; k++){
tmp = Xi[k];
Xi[k] = Xj[k];
Xj[k] = tmp;
}
}
}
__device__ int getMaxIdx(int p, float * ColNorms, int id){
int maxIdx = 0, i, bit;
float max = ColNorms[maxIdx], tmp;
for(i = 1; i < p; i++){
bit = ( id & (1 << i) ) >> 1;
if( bit == 1){
tmp = ColNorms[i];
if(tmp > max){
max = tmp;
maxIdx = i;
}
}
}
return maxIdx;
}
__device__ int idx(int id, int p, int i){
int j, colcount=0, out;
for(j=0; j<p; j++){
if(colcount == i)
out = j;
if( ( id & ( 1 << j ) ) >> j == 1)
colcount += 1;
}
return out;
}
__global__ void getColNorms(int rows, int cols, float * dX, float * ColNorms){
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float sum = 0.f, term, * col;
if(colIndex >= cols)
return;
col = dX + colIndex * rows;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
ColNorms[colIndex] = sqrtf(sum);
}
__global__ void GetQRDecompBlocked(int n, int p, float * X, float * ColNorms,
unsigned int blockSize, int stride, float * scales,
float * Beta, float * qrAux, int * pivot,
float * WtR, int * rank, float * V, float * W,
float * T, float * u){
float tol = 0.0001; //float tolerance
int blockCount, blockEnd = 0, bc, i, kp; //kp is # cols processed
//unsigned int id = threadIDx.x + blockIDx.x * blockDim.x;
int varcount = 0, maxIdx, pm = 1;
//unsigned int * binid;
float * Xm; //model id's model matrix; will eventually contain R in QR decomp
//float * pXcol = X; //pointer to column of X
float * pXmcol; //pointer to column of Xm
float maxNorm;
float * pXmBlock; //pointer to block of Xm
size_t fbytes = sizeof(float);
int rk = 0; // Local value of rank;
int maxRank; //maximum possible rank of the model matrix
float minElt; // Lowest acceptable norm under given tolerance.
int maxCol; //this will be initialized to pm - 1, highest candidate column, not fixed
int maxRow = n - 1;
int rowskp = stride; // # unprocessed rows = stride - kp
int colskp; // # unprocessed cols = cols - kp
float *pVcol; //pointer to column of V
float *pVdiag; //pointer to diagonal element of V
float *pXmdiag; //pointer to diagonal element of dQRBlock
int colIdx;
int a,b;
int l;
//if(id > M)
// return;
//binid = (unsigned int *)calloc(p-1, sizeof(unsigned int));
/*
//copies the relevant columns of X into Xm
do{
int jump = 0;
unsigned int bit = 0;
memcpy(pXmcol, pXcol, n*fbytes); //copy the current column
//any time we copy any column but the first, set binid[col] = 1
if(varcount > 0){
binid[p - varcount] = 1; //actual index is (p - 1) - (varcount - 1)
pm += 1;
}
pXmcol += n; //update pointer on Xm to the next column
//bitwise operations on id to find proper columns
//look for the next used column of X
do{
jump += 1; //increment number of columns of X to move forward
varcount += 1; //increment number of total vars of X checked
//note: each column of X but the first represents a variable
//set bit as the k'th bit of id (1st bit is far right)
bit = ( id & ( 1 << varcount ) ) >> varcount;
//alternative code: declare tmpid above first.
////bit = tmpid & 1; //bit = 1 if last bit of tmpid is 1, 0 otherwise
////tmpid = tmpid >> 1; //bitshift tmpid right - lopping off last bit
}
while(bit == 0 && varcount < p);
pXcol += n*jump; //update pointer on X to the next used column
}
while(varcount < p );
//if varcount = k ( = p - 1 ), we still have to copy this last column, so the
//loop must iterate again
*/
pm = p;
//initialize variables that depend on pm and Xm
//Xm = (float *) calloc(stride*pm,fbytes); //allocate memory for model matrix
Xm = X;
pXmcol = Xm;
pXmBlock = Xm;
maxCol = pm - 1; //maximum possible column
colskp = pm;
maxIdx = getMaxIdx(p, ColNorms, (1 << pm) - 1);
//id);
maxNorm = ColNorms[maxIdx];
if (maxNorm < tol){
maxRank = 0; // Short-circuits the main pivot loop
}
else{
minElt = (1.0 + maxNorm) * tol;
maxRank = n > pm ? pm : n; //min(n,pm)
}
blockCount = (pm + blockSize - 1) / blockSize;
for(bc = 0; bc < blockCount; bc++){
// Determines "blockEnd", which counts the number of columns remaining
// in the upcoming block. Swaps trivial columns with the rightmost
// unvisited column until either a nontrivial column is found or all
// columns have been visited. Note that 'blockEnd <= blockSize', with
// inequality possible only in the rightmost processed block.
//
// This pivoting scheme does not attempt to order columns by norm, nor
// does it recompute norms altered by the rank-one update within the
// upcoming block. A higher-fidelity scheme is implemented in the non-
// blocked form of this function. Sapienti sat.
blockEnd = 0;
for(i = kp; i < kp + blockSize && i < maxRank && i <= maxCol; i++){
float colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
while( (colNorm < minElt) && (maxCol > i) ){
//while colNorm is smaller than the lowest acceptable norm, given tolerance
//and while the maximum column possible is larger than the current column
//keep track of column swap in pivot vector
int tempIdx = pivot[maxCol];
//exchange columns of Xm: current column and maxCol
colswap(Xm, stride, pm, i, maxCol);
pivot[maxCol] = pivot[i];
pivot[i] = tempIdx;
maxCol--;
//set new colNorm as norm of max column, now in i'th spot
colNorm = ColNorms[i];
//ColNorms[idx(id, p, i)];
}
if (colNorm >= minElt)
blockEnd++;
}
rk += blockEnd;
//set V to 0 everywhere
for(a=0; a<blockSize; a++)
for(b=0; b<rowskp; b++)
*(V + b + a*rowskp) = 0;
pVcol = V; //pointer to column of V
pVdiag = V; //pointer to diagonal element of V
pXmdiag = pXmBlock; //pointer to diagonal element of XmBlock
for(colIdx = 0; colIdx < blockEnd; colIdx++){
float v1;
float v1Abs;
memcpy(pVdiag, pXmdiag, (rowskp - colIdx)*fbytes);
// Builds Householder vector from maximal column just copied.
// For now, uses slow memory transfers to modify leading element:
// V_1 += sign(V_1) * normV.
v1 = *pVdiag;
v1Abs = fabs(v1);
if(kp == maxRow)//botom row is not scaled
qrAux[kp] = v1Abs;
else{ // zero-valued "normV" should already have been ruled out.
int d;
float normV = 0;
float recipNormV;
float fac;
for(d=0; d < rowskp - colIdx; d++){
float diag = pVdiag[d];
normV += diag*diag;
}
normV = sqrtf(normV);
recipNormV = 1.0 / normV;
qrAux[kp] = 1.0 + v1Abs * recipNormV;
scales[colIdx] = (v1 >= 0.f ? 1.f : -1.f) * recipNormV;
// Scales leading nonzero element of vector.
fac = 1.0 + normV / v1Abs;
*pVdiag *= fac;
Beta[colIdx] = -2.0 / (normV * normV + v1Abs * (-1.0 + fac * fac));
// u = Beta[colIdx] * t(pXmBlock) %*% pVcol
// rows of pXmBlock = rowskp
// cols of pXmBlock = min(blockSize, colskp)
// leading dimension of pXmBlock = stride
// elements of pVcol = rowskp
// elements of u = min(blockSize, colskp)
cXtv(Beta[colIdx], rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
//pXmBlock = pXmBlock + pVcol %*% u'
//rows of pXmBlock = rowskp
//cols of pXmBlock = min(blockSize, colsk)
//elements of pVcol = rowskp
//elements of u = min(blockSize, colsk)
//leading dim of pXmBlock = stride
Xpvut(rowskp, min(blockSize, colskp), pXmBlock, stride, pVcol, u);
}
pVcol += rowskp;
pVdiag += (rowskp + 1);
pXmdiag += (stride + 1);
kp++;
}
// If more unseen columns remain, updates the remainder of QR lying to
// the right of the block just updated. This must be done unless we
// happen to have exited the inner loop without having applied any
// Householder transformations (i.e., blockEnd == 0).
if (bc < blockCount - 1 && blockEnd > 0) {
// w_m = Beta (I + W V^t) v_m, where the unsubscripted matrices
// refer to those built at step 'i-1', having 'i' columns.
//
// w_i = Beta v_i
//
float *pTcol = T; //pointer to columns of dT
float *pWcol = W; //pointer to columns of dW
int m, a, b, c;
pVcol = V; //pointer to columns of dV
// T = V^t V
//// T = dT
//// V = dV
//rows of V' = blockSize
//cols of V' = rowsk
//leading dim of V = rowsk
//leading dim of T = rowsk
//rows/cols of T = blockSize
uVtV(rowskp, blockSize, V, T);
for (m = 0; m < blockSize; m++, pWcol += rowskp, pVcol += rowskp,
pTcol += blockSize) {
//for m=0,1,..., blockSize - 1
//pdWcol += rowsk
//pdVcol += rowsk
//pdTcol += blockSize
int a;
for(a = 0; a<rowskp; a++)
pWcol[a] = Beta[m]*pVcol[a];
// w_m = w_m + Beta W T(.,m)
//// w_m = pWcol
//// Beta = Beta[m]
//// T(.,m) = pTcol
//// W = dW
if (m > 0) {
int a, b;
for(a = 0; a < rowskp; a++){
float sum = 0;
for(b = 0; b < m; b++){
sum += W[b + a*m] * pTcol[b];
}
pWcol[a] += sum;
}
}
}
// Updates R, beginning at current diagonal by:
// R = (I_m + V W^t) R = R + V (W^t R)
//
// WtR = W^t R
//// WtR = dWtR
//// W = dW
//W is rowskp by blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
//WtR is blockSize by colsk - blockSize
for(a = 0; a < blockSize; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < rowskp; c++)
sum += W[c + rowskp*a] * *(pXmBlock + blockSize*stride + c + b*rowskp);
WtR[a + b*blockSize] = sum;
}
}
// R = V WtR + R
//// V = dV
//// WtR = dWtR
//// R = pdQRBlock + blockSize*stride
// V is rowskp by blockSize
//WtR is blockSize by colskp - blockSize
//pXmBlock + blockSize*stride is rowskp by colskp - blockSize
for(a = 0; a < rowskp; a++){
for(b = 0; b < colskp - blockSize; b++){
float sum = 0;
for(c = 0; c < blockSize; c++){
sum += V[a + c*rowskp] * WtR[c + b*blockSize];
}
*(pXmBlock + blockSize*stride + a + b*rowskp) += sum;
}
}
}
// Flushes scaled Householder vectors to the subdiagonals of dQR,
// 'blockSize'-many at a time. The only time a smaller number are
// sent occurs when a partial block remains at the right end.
//
pVdiag = V; //pointer to diagonal of V
pXmdiag = pXmBlock; //pointer to diagonal of pXmBlock / XmBlock
for (l = 0; l < blockEnd; l++, pVdiag += (rowskp + 1),
pXmdiag += (stride + 1)) {
//for l = 0, 1, ..., blockEnd - 1
//// pVdiag += (rowskp + 1)
//// pXmdiag += (stride +1)
int a;
//pVdiag + 1 = scales[l]* (pVdiag + 1)
//pXmdiag + 1 = pVdiag + 1
for(a = 0; a < rowskp - l - 1; a++){
*(pVdiag + 1 + a) *= scales[l];
*(pXmdiag + 1 + a) = *(pVdiag + 1 + a);
}
}
pXmBlock += blockSize * (stride + 1);
colskp -= blockSize;
rowskp -= blockSize;
//end main loop
}
//set rank
*rank = rk;
// Xm now contains the upper-triangular portion of the factorization,
// R.
// V is lower-triangular, and contains the Householder vectors, from
// which the Q portion can be derived. An adjusted form of the
// diagonal is saved in qrAux, while the sub-diagonal portion is
// written onto QR.
}
int main(void){
int n = 10, p = 5;
//, k = p - 1;
int i, j;
size_t fbytes = sizeof(float);
float * X = (float *)malloc(n*p*fbytes);
float * dX, * dColNorms;
int nblocks, nthreads = NTHREADS;
const unsigned blockExp = 7;
unsigned int blockSize = 1 << blockExp;
int stride = (n + blockSize - 1) & (((unsigned) -1) << blockExp);
float * dscales;
float * dBeta;
float * dqrAux;
int * dpivot;
float * dWtR;
int * drank;
float * dV;
float * dW;
float * dT;
float * du;
for(i=0; i<n; i++)
for(j=0; j<p; j++)
X[i + j*n] = i + j;
printf("\n X \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
hipMalloc( (void **)&dX, n*p*fbytes );
hipMalloc( (void **)&dColNorms, p*fbytes);
hipMalloc( (void **)&dscales, blockSize*fbytes);
hipMalloc( (void **)&dBeta, blockSize*fbytes);
hipMalloc( (void **)&dqrAux, p*fbytes);
hipMalloc( (void **)&dpivot, p*sizeof(int));
hipMalloc( (void **)&dWtR, blockSize*(p - blockSize)*fbytes);
hipMalloc( (void **)&drank, sizeof(int));
hipMalloc( (void **)&dV, blockSize*stride*fbytes);
hipMalloc( (void **)&dW, blockSize*stride*fbytes);
hipMalloc( (void **)&dT, blockSize*blockSize*fbytes);
hipMalloc( (void **)&du, stride*fbytes);
hipMemcpy( dX, X, n*p*fbytes, hipMemcpyHostToDevice);
nblocks = p / nthreads;
if(nblocks * nthreads < p)
nblocks++;
getColNorms<<<nblocks, nthreads>>>(n, p, dX, dColNorms);
GetQRDecompBlocked<<<1,1>>>(n, p, dX, dColNorms, blockSize, stride, dscales, dBeta,
dqrAux, dpivot, dWtR, drank, dV, dW, dT, du);
hipMemcpy( X, dX, n*p*fbytes, hipMemcpyDeviceToHost);
printf("\n R \n");
for(i=0; i<n; i++){
for(j=0; j<p; j++){
printf("%.f ", X[i + j*n]);
}
printf("\n");
}
hipFree(dX);
hipFree(dColNorms);
free(X);
hipFree(dscales);
hipFree(dBeta);
hipFree(dqrAux);
hipFree(dpivot);
hipFree(dWtR);
hipFree(drank);
hipFree(dV);
hipFree(dW);
hipFree(dT);
hipFree(du);
return 0;
} | .text
.file "qrdecomp.hip"
.globl _Z26__device_stub__getColNormsiiPfS_ # -- Begin function _Z26__device_stub__getColNormsiiPfS_
.p2align 4, 0x90
.type _Z26__device_stub__getColNormsiiPfS_,@function
_Z26__device_stub__getColNormsiiPfS_: # @_Z26__device_stub__getColNormsiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11getColNormsiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__getColNormsiiPfS_, .Lfunc_end0-_Z26__device_stub__getColNormsiiPfS_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_ # -- Begin function _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.p2align 4, 0x90
.type _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_,@function
_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_: # @_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end1:
.size _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .Lfunc_end1-_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $200, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader115
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-200, %rdx
movl %eax, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, 200(%rcx,%rdx)
incl %esi
addq $40, %rdx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $4, %rcx
cmpq $10, %rax
jne .LBB2_1
# %bb.4:
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB2_5: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movq $-200, %r12
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movss 200(%r15,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $40, %r12
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4, %r15
cmpq $10, %r14
jne .LBB2_5
# %bb.8:
movabsq $4294967297, %r14 # imm = 0x100000001
movq %rsp, %rdi
movl $200, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 184(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 176(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 168(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 160(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 152(%rsp), %rdi
movabsq $17179806208, %rsi # imm = 0x3FFFF0A00
callq hipMalloc
leaq 144(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 136(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 128(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 120(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 112(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq (%rsp), %rdi
movl $200, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 511(%r14), %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movl $10, 56(%rsp)
movl $5, 48(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 88(%rsp), %rax
movq %rax, 272(%rsp)
leaq 80(%rsp), %rax
movq %rax, 280(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z11getColNormsiiPfS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 184(%rsp), %rdx
movq 176(%rsp), %rsi
movq 168(%rsp), %rdi
movq 160(%rsp), %r8
movq 152(%rsp), %r9
movq 144(%rsp), %r10
movq 136(%rsp), %r11
movq 128(%rsp), %r14
movq 120(%rsp), %r15
movq 112(%rsp), %r12
movl $10, 108(%rsp)
movl $5, 104(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $128, 100(%rsp)
movl $128, 96(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdi, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 248(%rsp)
movq %r10, 240(%rsp)
movq %r11, 232(%rsp)
movq %r14, 224(%rsp)
movq %r15, 216(%rsp)
movq %r12, 208(%rsp)
leaq 108(%rsp), %rax
movq %rax, 256(%rsp)
leaq 104(%rsp), %rax
movq %rax, 264(%rsp)
leaq 88(%rsp), %rax
movq %rax, 272(%rsp)
leaq 80(%rsp), %rax
movq %rax, 280(%rsp)
leaq 100(%rsp), %rax
movq %rax, 288(%rsp)
leaq 96(%rsp), %rax
movq %rax, 296(%rsp)
leaq 72(%rsp), %rax
movq %rax, 304(%rsp)
leaq 64(%rsp), %rax
movq %rax, 312(%rsp)
leaq 56(%rsp), %rax
movq %rax, 320(%rsp)
leaq 48(%rsp), %rax
movq %rax, 328(%rsp)
leaq 248(%rsp), %rax
movq %rax, 336(%rsp)
leaq 240(%rsp), %rax
movq %rax, 344(%rsp)
leaq 232(%rsp), %rax
movq %rax, 352(%rsp)
leaq 224(%rsp), %rax
movq %rax, 360(%rsp)
leaq 216(%rsp), %rax
movq %rax, 368(%rsp)
leaq 208(%rsp), %rax
movq %rax, 376(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 200(%rsp), %rdx
leaq 192(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %edi
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq (%rsp), %rsi
movl $200, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB2_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movq $-200, %r12
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movss 200(%r15,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $40, %r12
jne .LBB2_14
# %bb.15: # in Loop: Header=BB2_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4, %r15
cmpq $10, %r14
jne .LBB2_13
# %bb.16:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq 184(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
movq 152(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11getColNormsiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11getColNormsiiPfS_,@object # @_Z11getColNormsiiPfS_
.section .rodata,"a",@progbits
.globl _Z11getColNormsiiPfS_
.p2align 3, 0x0
_Z11getColNormsiiPfS_:
.quad _Z26__device_stub__getColNormsiiPfS_
.size _Z11getColNormsiiPfS_, 8
.type _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_,@object # @_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.globl _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.p2align 3, 0x0
_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.quad _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.size _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.f "
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11getColNormsiiPfS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_"
.size .L__unnamed_2, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n X "
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n R "
.size .Lstr.1, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__getColNormsiiPfS_
.addrsig_sym _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11getColNormsiiPfS_
.addrsig_sym _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00162aa9_00000000-6_qrdecomp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4cXtvfiiPfiS_S_
.type _Z4cXtvfiiPfiS_S_, @function
_Z4cXtvfiiPfiS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4cXtvfiiPfiS_S_, .-_Z4cXtvfiiPfiS_S_
.globl _Z5XpvutiiPfiS_S_
.type _Z5XpvutiiPfiS_S_, @function
_Z5XpvutiiPfiS_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5XpvutiiPfiS_S_, .-_Z5XpvutiiPfiS_S_
.globl _Z4uVtViiPfS_
.type _Z4uVtViiPfS_, @function
_Z4uVtViiPfS_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z4uVtViiPfS_, .-_Z4uVtViiPfS_
.globl _Z10alignBlockij
.type _Z10alignBlockij, @function
_Z10alignBlockij:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z10alignBlockij, .-_Z10alignBlockij
.globl _Z7colswapPfiiii
.type _Z7colswapPfiiii, @function
_Z7colswapPfiiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z7colswapPfiiii, .-_Z7colswapPfiiii
.globl _Z9getMaxIdxiPfi
.type _Z9getMaxIdxiPfi, @function
_Z9getMaxIdxiPfi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z9getMaxIdxiPfi, .-_Z9getMaxIdxiPfi
.globl _Z3idxiii
.type _Z3idxiii, @function
_Z3idxiii:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z3idxiii, .-_Z3idxiii
.globl _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
.type _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_, @function
_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11getColNormsiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_, .-_Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
.globl _Z11getColNormsiiPfS_
.type _Z11getColNormsiiPfS_, @function
_Z11getColNormsiiPfS_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z11getColNormsiiPfS_, .-_Z11getColNormsiiPfS_
.globl _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.type _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_, @function
_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movl %edi, 108(%rsp)
movl %esi, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movl %r8d, 84(%rsp)
movl %r9d, 80(%rsp)
movq 336(%rsp), %rax
movq %rax, 72(%rsp)
movq 344(%rsp), %rax
movq %rax, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 376(%rsp), %rax
movq %rax, 32(%rsp)
movq 384(%rsp), %rax
movq %rax, 24(%rsp)
movq 392(%rsp), %rax
movq %rax, 16(%rsp)
movq 400(%rsp), %rax
movq %rax, 8(%rsp)
movq 408(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 84(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 32(%rsp), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 8(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .-_Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.globl _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.type _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, @function
_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 88(%rsp)
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .-_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n X \n"
.LC1:
.string "%.f "
.LC2:
.string "\n"
.LC3:
.string "\n R \n"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, %rdi
movl $5, %ecx
movl $0, %esi
jmp .L34
.L50:
addl $1, %esi
addq $4, %rdi
addl $1, %ecx
cmpl $10, %esi
je .L36
.L34:
movl %esi, %eax
movq %rdi, %rdx
.L35:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
addl $1, %eax
addq $40, %rdx
cmpl %ecx, %eax
jne .L35
jmp .L50
.L36:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 200(%rax), %rbp
movq %rbp, %r12
movl $0, %r14d
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
jmp .L37
.L51:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq $4, %r12
cmpl $10, %r14d
je .L39
.L37:
leaq -200(%r12), %rbx
.L38:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $40, %rbx
cmpq %r12, %rbx
jne .L38
jmp .L51
.L39:
leaq 16(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movabsq $17179806208, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L40:
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
movl $2, %ecx
movl $200, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r14
jmp .L42
.L52:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl $5, %esi
movl $10, %edi
call _Z35__device_stub__Z11getColNormsiiPfS_iiPfS_
jmp .L40
.L53:
pushq 104(%rsp)
.cfi_def_cfa_offset 216
pushq 104(%rsp)
.cfi_def_cfa_offset 224
pushq 104(%rsp)
.cfi_def_cfa_offset 232
pushq 104(%rsp)
.cfi_def_cfa_offset 240
pushq 104(%rsp)
.cfi_def_cfa_offset 248
pushq 104(%rsp)
.cfi_def_cfa_offset 256
pushq 104(%rsp)
.cfi_def_cfa_offset 264
pushq 104(%rsp)
.cfi_def_cfa_offset 272
pushq 104(%rsp)
.cfi_def_cfa_offset 280
pushq 104(%rsp)
.cfi_def_cfa_offset 288
movl $128, %r9d
movl $128, %r8d
movq 104(%rsp), %rcx
movq 96(%rsp), %rdx
movl $5, %esi
movl $10, %edi
call _Z65__device_stub__Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_iiPfS_jiS_S_S_PiS_S0_S_S_S_S_
addq $80, %rsp
.cfi_def_cfa_offset 208
jmp .L41
.L54:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $4, %rbp
cmpl $10, %r13d
je .L44
.L42:
leaq -200(%rbp), %rbx
.L43:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $40, %rbx
cmpq %rbp, %rbx
jne .L43
jmp .L54
.L44:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_"
.section .rodata.str1.1
.LC5:
.string "_Z11getColNormsiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11getColNormsiiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "qrdecomp.hip"
.globl _Z26__device_stub__getColNormsiiPfS_ # -- Begin function _Z26__device_stub__getColNormsiiPfS_
.p2align 4, 0x90
.type _Z26__device_stub__getColNormsiiPfS_,@function
_Z26__device_stub__getColNormsiiPfS_: # @_Z26__device_stub__getColNormsiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11getColNormsiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__getColNormsiiPfS_, .Lfunc_end0-_Z26__device_stub__getColNormsiiPfS_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_ # -- Begin function _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.p2align 4, 0x90
.type _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_,@function
_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_: # @_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end1:
.size _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, .Lfunc_end1-_Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $200, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader115
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-200, %rdx
movl %eax, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, 200(%rcx,%rdx)
incl %esi
addq $40, %rdx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $4, %rcx
cmpq $10, %rax
jne .LBB2_1
# %bb.4:
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB2_5: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movq $-200, %r12
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movss 200(%r15,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $40, %r12
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4, %r15
cmpq $10, %r14
jne .LBB2_5
# %bb.8:
movabsq $4294967297, %r14 # imm = 0x100000001
movq %rsp, %rdi
movl $200, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 184(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 176(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 168(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 160(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 152(%rsp), %rdi
movabsq $17179806208, %rsi # imm = 0x3FFFF0A00
callq hipMalloc
leaq 144(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 136(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 128(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 120(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 112(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq (%rsp), %rdi
movl $200, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 511(%r14), %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movl $10, 56(%rsp)
movl $5, 48(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 88(%rsp), %rax
movq %rax, 272(%rsp)
leaq 80(%rsp), %rax
movq %rax, 280(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z11getColNormsiiPfS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 184(%rsp), %rdx
movq 176(%rsp), %rsi
movq 168(%rsp), %rdi
movq 160(%rsp), %r8
movq 152(%rsp), %r9
movq 144(%rsp), %r10
movq 136(%rsp), %r11
movq 128(%rsp), %r14
movq 120(%rsp), %r15
movq 112(%rsp), %r12
movl $10, 108(%rsp)
movl $5, 104(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $128, 100(%rsp)
movl $128, 96(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdi, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 248(%rsp)
movq %r10, 240(%rsp)
movq %r11, 232(%rsp)
movq %r14, 224(%rsp)
movq %r15, 216(%rsp)
movq %r12, 208(%rsp)
leaq 108(%rsp), %rax
movq %rax, 256(%rsp)
leaq 104(%rsp), %rax
movq %rax, 264(%rsp)
leaq 88(%rsp), %rax
movq %rax, 272(%rsp)
leaq 80(%rsp), %rax
movq %rax, 280(%rsp)
leaq 100(%rsp), %rax
movq %rax, 288(%rsp)
leaq 96(%rsp), %rax
movq %rax, 296(%rsp)
leaq 72(%rsp), %rax
movq %rax, 304(%rsp)
leaq 64(%rsp), %rax
movq %rax, 312(%rsp)
leaq 56(%rsp), %rax
movq %rax, 320(%rsp)
leaq 48(%rsp), %rax
movq %rax, 328(%rsp)
leaq 248(%rsp), %rax
movq %rax, 336(%rsp)
leaq 240(%rsp), %rax
movq %rax, 344(%rsp)
leaq 232(%rsp), %rax
movq %rax, 352(%rsp)
leaq 224(%rsp), %rax
movq %rax, 360(%rsp)
leaq 216(%rsp), %rax
movq %rax, 368(%rsp)
leaq 208(%rsp), %rax
movq %rax, 376(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 200(%rsp), %rdx
leaq 192(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %edi
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq (%rsp), %rsi
movl $200, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB2_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movq $-200, %r12
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movss 200(%r15,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $40, %r12
jne .LBB2_14
# %bb.15: # in Loop: Header=BB2_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4, %r15
cmpq $10, %r14
jne .LBB2_13
# %bb.16:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq 184(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
movq 152(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11getColNormsiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11getColNormsiiPfS_,@object # @_Z11getColNormsiiPfS_
.section .rodata,"a",@progbits
.globl _Z11getColNormsiiPfS_
.p2align 3, 0x0
_Z11getColNormsiiPfS_:
.quad _Z26__device_stub__getColNormsiiPfS_
.size _Z11getColNormsiiPfS_, 8
.type _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_,@object # @_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.globl _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.p2align 3, 0x0
_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_:
.quad _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.size _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.f "
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11getColNormsiiPfS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_"
.size .L__unnamed_2, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n X "
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n R "
.size .Lstr.1, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__getColNormsiiPfS_
.addrsig_sym _Z33__device_stub__GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11getColNormsiiPfS_
.addrsig_sym _Z18GetQRDecompBlockediiPfS_jiS_S_S_PiS_S0_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
cudaMallocManaged(&ptr, len);
cudaDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
cudaDeviceSynchronize();
cudaFree(ptr);
}
};
struct particle2 : public Managed{
int id;
int len;
char *name;
};
struct particle{
int id;
int len;
float *nums;
};
void allocate(struct particle **par){
// **par = &oldpar
cudaMallocManaged( &(*par), sizeof(particle));
cudaMallocManaged( &((*par)->nums), sizeof(float) * 3 );
}
__global__ void change(struct particle *par){
par->nums[0] = 1337.0;
}
__global__ void blesd(){
float weight[2000][2000][2000];
weight[0][0][0] = 99;
for(int i = 0; i < 1; ++i){
printf("weight: %f \n", weight[0][0][0]);
}
}
int main(){
blesd<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z5blesdv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4058c000 ; /* 0x4058c000ff097424 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100a00 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fca00000e06ff */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6changeP8particle
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0040*/ LDG.E.64 R2, [R2.64+0x8] ; /* 0x0000080402027981 */
/* 0x000ea2000c1e1b00 */
/*0050*/ HFMA2.MMA R5, -RZ, RZ, 4.65234375, 0.0078125 ; /* 0x44a72000ff057435 */
/* 0x000fce00000001ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
cudaMallocManaged(&ptr, len);
cudaDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
cudaDeviceSynchronize();
cudaFree(ptr);
}
};
struct particle2 : public Managed{
int id;
int len;
char *name;
};
struct particle{
int id;
int len;
float *nums;
};
void allocate(struct particle **par){
// **par = &oldpar
cudaMallocManaged( &(*par), sizeof(particle));
cudaMallocManaged( &((*par)->nums), sizeof(float) * 3 );
}
__global__ void change(struct particle *par){
par->nums[0] = 1337.0;
}
__global__ void blesd(){
float weight[2000][2000][2000];
weight[0][0][0] = 99;
for(int i = 0; i < 1; ++i){
printf("weight: %f \n", weight[0][0][0]);
}
}
int main(){
blesd<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000e8bef_00000000-6_test2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8allocatePP8particle
.type _Z8allocatePP8particle, @function
_Z8allocatePP8particle:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq (%rbx), %rdi
addq $8, %rdi
movl $1, %edx
movl $12, %esi
call cudaMallocManaged@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z8allocatePP8particle, .-_Z8allocatePP8particle
.globl _Z33__device_stub__Z6changeP8particleP8particle
.type _Z33__device_stub__Z6changeP8particleP8particle, @function
_Z33__device_stub__Z6changeP8particleP8particle:
.LFB3697:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6changeP8particle(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z33__device_stub__Z6changeP8particleP8particle, .-_Z33__device_stub__Z6changeP8particleP8particle
.globl _Z6changeP8particle
.type _Z6changeP8particle, @function
_Z6changeP8particle:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6changeP8particleP8particle
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6changeP8particle, .-_Z6changeP8particle
.globl _Z23__device_stub__Z5blesdvv
.type _Z23__device_stub__Z5blesdvv, @function
_Z23__device_stub__Z5blesdvv:
.LFB3699:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5blesdv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z23__device_stub__Z5blesdvv, .-_Z23__device_stub__Z5blesdvv
.globl _Z5blesdv
.type _Z5blesdv, @function
_Z5blesdv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5blesdvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z5blesdv, .-_Z5blesdv
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L22:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _Z23__device_stub__Z5blesdvv
jmp .L22
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5blesdv"
.LC1:
.string "_Z6changeP8particle"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5blesdv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6changeP8particle(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
cudaMallocManaged(&ptr, len);
cudaDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
cudaDeviceSynchronize();
cudaFree(ptr);
}
};
struct particle2 : public Managed{
int id;
int len;
char *name;
};
struct particle{
int id;
int len;
float *nums;
};
void allocate(struct particle **par){
// **par = &oldpar
cudaMallocManaged( &(*par), sizeof(particle));
cudaMallocManaged( &((*par)->nums), sizeof(float) * 3 );
}
__global__ void change(struct particle *par){
par->nums[0] = 1337.0;
}
__global__ void blesd(){
float weight[2000][2000][2000];
weight[0][0][0] = 99;
for(int i = 0; i < 1; ++i){
printf("weight: %f \n", weight[0][0][0]);
}
}
int main(){
blesd<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
};
struct particle2 : public Managed{
int id;
int len;
char *name;
};
struct particle{
int id;
int len;
float *nums;
};
void allocate(struct particle **par){
// **par = &oldpar
hipMallocManaged( &(*par), sizeof(particle));
hipMallocManaged( &((*par)->nums), sizeof(float) * 3 );
}
__global__ void change(struct particle *par){
par->nums[0] = 1337.0;
}
__global__ void blesd(){
float weight[2000][2000][2000];
weight[0][0][0] = 99;
for(int i = 0; i < 1; ++i){
printf("weight: %f \n", weight[0][0][0]);
}
}
int main(){
blesd<<<1,1>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
};
struct particle2 : public Managed{
int id;
int len;
char *name;
};
struct particle{
int id;
int len;
float *nums;
};
void allocate(struct particle **par){
// **par = &oldpar
hipMallocManaged( &(*par), sizeof(particle));
hipMallocManaged( &((*par)->nums), sizeof(float) * 3 );
}
__global__ void change(struct particle *par){
par->nums[0] = 1337.0;
}
__global__ void blesd(){
float weight[2000][2000][2000];
weight[0][0][0] = 99;
for(int i = 0; i < 1; ++i){
printf("weight: %f \n", weight[0][0][0]);
}
}
int main(){
blesd<<<1,1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "test2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8allocatePP8particle # -- Begin function _Z8allocatePP8particle
.p2align 4, 0x90
.type _Z8allocatePP8particle,@function
_Z8allocatePP8particle: # @_Z8allocatePP8particle
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rbx), %rdi
addq $8, %rdi
movl $12, %esi
movl $1, %edx
popq %rbx
.cfi_def_cfa_offset 8
jmp hipMallocManaged # TAILCALL
.Lfunc_end0:
.size _Z8allocatePP8particle, .Lfunc_end0-_Z8allocatePP8particle
.cfi_endproc
# -- End function
.globl _Z21__device_stub__changeP8particle # -- Begin function _Z21__device_stub__changeP8particle
.p2align 4, 0x90
.type _Z21__device_stub__changeP8particle,@function
_Z21__device_stub__changeP8particle: # @_Z21__device_stub__changeP8particle
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6changeP8particle, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z21__device_stub__changeP8particle, .Lfunc_end1-_Z21__device_stub__changeP8particle
.cfi_endproc
# -- End function
.globl _Z20__device_stub__blesdv # -- Begin function _Z20__device_stub__blesdv
.p2align 4, 0x90
.type _Z20__device_stub__blesdv,@function
_Z20__device_stub__blesdv: # @_Z20__device_stub__blesdv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5blesdv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z20__device_stub__blesdv, .Lfunc_end2-_Z20__device_stub__blesdv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5blesdv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6changeP8particle, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5blesdv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6changeP8particle,@object # @_Z6changeP8particle
.section .rodata,"a",@progbits
.globl _Z6changeP8particle
.p2align 3, 0x0
_Z6changeP8particle:
.quad _Z21__device_stub__changeP8particle
.size _Z6changeP8particle, 8
.type _Z5blesdv,@object # @_Z5blesdv
.globl _Z5blesdv
.p2align 3, 0x0
_Z5blesdv:
.quad _Z20__device_stub__blesdv
.size _Z5blesdv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6changeP8particle"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5blesdv"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__changeP8particle
.addrsig_sym _Z20__device_stub__blesdv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6changeP8particle
.addrsig_sym _Z5blesdv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e8bef_00000000-6_test2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8allocatePP8particle
.type _Z8allocatePP8particle, @function
_Z8allocatePP8particle:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq (%rbx), %rdi
addq $8, %rdi
movl $1, %edx
movl $12, %esi
call cudaMallocManaged@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z8allocatePP8particle, .-_Z8allocatePP8particle
.globl _Z33__device_stub__Z6changeP8particleP8particle
.type _Z33__device_stub__Z6changeP8particleP8particle, @function
_Z33__device_stub__Z6changeP8particleP8particle:
.LFB3697:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6changeP8particle(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z33__device_stub__Z6changeP8particleP8particle, .-_Z33__device_stub__Z6changeP8particleP8particle
.globl _Z6changeP8particle
.type _Z6changeP8particle, @function
_Z6changeP8particle:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6changeP8particleP8particle
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6changeP8particle, .-_Z6changeP8particle
.globl _Z23__device_stub__Z5blesdvv
.type _Z23__device_stub__Z5blesdvv, @function
_Z23__device_stub__Z5blesdvv:
.LFB3699:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5blesdv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z23__device_stub__Z5blesdvv, .-_Z23__device_stub__Z5blesdvv
.globl _Z5blesdv
.type _Z5blesdv, @function
_Z5blesdv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5blesdvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z5blesdv, .-_Z5blesdv
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L22:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _Z23__device_stub__Z5blesdvv
jmp .L22
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5blesdv"
.LC1:
.string "_Z6changeP8particle"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5blesdv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6changeP8particle(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8allocatePP8particle # -- Begin function _Z8allocatePP8particle
.p2align 4, 0x90
.type _Z8allocatePP8particle,@function
_Z8allocatePP8particle: # @_Z8allocatePP8particle
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rbx), %rdi
addq $8, %rdi
movl $12, %esi
movl $1, %edx
popq %rbx
.cfi_def_cfa_offset 8
jmp hipMallocManaged # TAILCALL
.Lfunc_end0:
.size _Z8allocatePP8particle, .Lfunc_end0-_Z8allocatePP8particle
.cfi_endproc
# -- End function
.globl _Z21__device_stub__changeP8particle # -- Begin function _Z21__device_stub__changeP8particle
.p2align 4, 0x90
.type _Z21__device_stub__changeP8particle,@function
_Z21__device_stub__changeP8particle: # @_Z21__device_stub__changeP8particle
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6changeP8particle, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z21__device_stub__changeP8particle, .Lfunc_end1-_Z21__device_stub__changeP8particle
.cfi_endproc
# -- End function
.globl _Z20__device_stub__blesdv # -- Begin function _Z20__device_stub__blesdv
.p2align 4, 0x90
.type _Z20__device_stub__blesdv,@function
_Z20__device_stub__blesdv: # @_Z20__device_stub__blesdv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5blesdv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z20__device_stub__blesdv, .Lfunc_end2-_Z20__device_stub__blesdv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5blesdv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6changeP8particle, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5blesdv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6changeP8particle,@object # @_Z6changeP8particle
.section .rodata,"a",@progbits
.globl _Z6changeP8particle
.p2align 3, 0x0
_Z6changeP8particle:
.quad _Z21__device_stub__changeP8particle
.size _Z6changeP8particle, 8
.type _Z5blesdv,@object # @_Z5blesdv
.globl _Z5blesdv
.p2align 3, 0x0
_Z5blesdv:
.quad _Z20__device_stub__blesdv
.size _Z5blesdv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6changeP8particle"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5blesdv"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__changeP8particle
.addrsig_sym _Z20__device_stub__blesdv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6changeP8particle
.addrsig_sym _Z5blesdv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Matrix Addition **
** **
** This program will add two matrices and store **
** the result in a third matrix using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#define THREADS 10
using namespace std;
__global__ void add(int *a, int *b, int *c,int columns,int rows)
{
// get the global id for the thread
// calculate the index of the input data
// perform addition
}
int main(void)
{
int rows = 100;
int columns = 100;
int elements = rows * columns;
size_t size = rows * columns * sizeof(int);
// create device pointers
int* d_a;
int* d_b;
int* d_c;
// allocate memory on the device
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size); cudaMalloc(&d_c, size);
// initalize host variables
vector<int> h_a(elements, 5);
vector<int> h_b(elements, 5);
vector<int> h_c(elements);
// transfer the host data to the GPU
cudaMemcpy(d_a, &h_a.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b.front(), size, cudaMemcpyHostToDevice);
// calculate the number of threads and blocks
// Launch the add kernel
// get the results from the GPU
cudaMemcpy(&h_c.front(), d_c, size, cudaMemcpyDeviceToHost);
// print top left corner
for(int i = 0; i < 5; i++) {
for(int j = 0; j < 10; j++)
cout << h_c[i * rows + j] << " ";
cout << endl;
}
} | code for sm_80
Function : _Z3addPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Matrix Addition **
** **
** This program will add two matrices and store **
** the result in a third matrix using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#define THREADS 10
using namespace std;
__global__ void add(int *a, int *b, int *c,int columns,int rows)
{
// get the global id for the thread
// calculate the index of the input data
// perform addition
}
int main(void)
{
int rows = 100;
int columns = 100;
int elements = rows * columns;
size_t size = rows * columns * sizeof(int);
// create device pointers
int* d_a;
int* d_b;
int* d_c;
// allocate memory on the device
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size); cudaMalloc(&d_c, size);
// initalize host variables
vector<int> h_a(elements, 5);
vector<int> h_b(elements, 5);
vector<int> h_c(elements);
// transfer the host data to the GPU
cudaMemcpy(d_a, &h_a.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b.front(), size, cudaMemcpyHostToDevice);
// calculate the number of threads and blocks
// Launch the add kernel
// get the results from the GPU
cudaMemcpy(&h_c.front(), d_c, size, cudaMemcpyDeviceToHost);
// print top left corner
for(int i = 0; i < 5; i++) {
for(int j = 0; j < 10; j++)
cout << h_c[i * rows + j] << " ";
cout << endl;
}
} | .file "tmpxft_0005b288_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
.type _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii, @function
_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii, .-_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
.globl _Z3addPiS_S_ii
.type _Z3addPiS_S_ii, @function
_Z3addPiS_S_ii:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z3addPiS_S_ii, .-_Z3addPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4371:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4371:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $40000, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $40000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 32(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 48(%rsp)
.L20:
movl $5, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 40(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $40000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbp
movq %rax, 64(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 80(%rsp)
.L21:
movl $5, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 72(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $40000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %r14
movq %rax, 96(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 112(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L22:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L22
movq %rdx, 104(%rsp)
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 40(%r14), %rbp
addq $2040, %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L23
.L45:
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
je .L44
.L24:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
jmp .L45
.L44:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L46
cmpb $0, 56(%rbx)
je .L27
movzbl 67(%rbx), %esi
.L28:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L47
.L46:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L37:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L31:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L32:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L33
call __stack_chk_fail@PLT
.L48:
call __stack_chk_fail@PLT
.L27:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L47:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE3:
addq $400, %rbp
cmpq %rbp, %r14
je .L29
.L23:
leaq -40(%rbp), %rbx
jmp .L24
.L29:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 32(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L31
.L35:
endbr64
movq %rax, %rbx
jmp .L32
.L33:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L35-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L36-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L37-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*************************************************
** Accelereyes Training Day 1 **
** Matrix Addition **
** **
** This program will add two matrices and store **
** the result in a third matrix using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#define THREADS 10
using namespace std;
__global__ void add(int *a, int *b, int *c,int columns,int rows)
{
// get the global id for the thread
// calculate the index of the input data
// perform addition
}
int main(void)
{
int rows = 100;
int columns = 100;
int elements = rows * columns;
size_t size = rows * columns * sizeof(int);
// create device pointers
int* d_a;
int* d_b;
int* d_c;
// allocate memory on the device
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size); cudaMalloc(&d_c, size);
// initalize host variables
vector<int> h_a(elements, 5);
vector<int> h_b(elements, 5);
vector<int> h_c(elements);
// transfer the host data to the GPU
cudaMemcpy(d_a, &h_a.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b.front(), size, cudaMemcpyHostToDevice);
// calculate the number of threads and blocks
// Launch the add kernel
// get the results from the GPU
cudaMemcpy(&h_c.front(), d_c, size, cudaMemcpyDeviceToHost);
// print top left corner
for(int i = 0; i < 5; i++) {
for(int j = 0; j < 10; j++)
cout << h_c[i * rows + j] << " ";
cout << endl;
}
} | /*************************************************
** Accelereyes Training Day 1 **
** Matrix Addition **
** **
** This program will add two matrices and store **
** the result in a third matrix using the GPU **
*************************************************/
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#define THREADS 10
using namespace std;
__global__ void add(int *a, int *b, int *c,int columns,int rows)
{
// get the global id for the thread
// calculate the index of the input data
// perform addition
}
int main(void)
{
int rows = 100;
int columns = 100;
int elements = rows * columns;
size_t size = rows * columns * sizeof(int);
// create device pointers
int* d_a;
int* d_b;
int* d_c;
// allocate memory on the device
hipMalloc(&d_a, size);
hipMalloc(&d_b, size); hipMalloc(&d_c, size);
// initalize host variables
vector<int> h_a(elements, 5);
vector<int> h_b(elements, 5);
vector<int> h_c(elements);
// transfer the host data to the GPU
hipMemcpy(d_a, &h_a.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b.front(), size, hipMemcpyHostToDevice);
// calculate the number of threads and blocks
// Launch the add kernel
// get the results from the GPU
hipMemcpy(&h_c.front(), d_c, size, hipMemcpyDeviceToHost);
// print top left corner
for(int i = 0; i < 5; i++) {
for(int j = 0; j < 10; j++)
cout << h_c[i * rows + j] << " ";
cout << endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Matrix Addition **
** **
** This program will add two matrices and store **
** the result in a third matrix using the GPU **
*************************************************/
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#define THREADS 10
using namespace std;
__global__ void add(int *a, int *b, int *c,int columns,int rows)
{
// get the global id for the thread
// calculate the index of the input data
// perform addition
}
int main(void)
{
int rows = 100;
int columns = 100;
int elements = rows * columns;
size_t size = rows * columns * sizeof(int);
// create device pointers
int* d_a;
int* d_b;
int* d_c;
// allocate memory on the device
hipMalloc(&d_a, size);
hipMalloc(&d_b, size); hipMalloc(&d_c, size);
// initalize host variables
vector<int> h_a(elements, 5);
vector<int> h_b(elements, 5);
vector<int> h_c(elements);
// transfer the host data to the GPU
hipMemcpy(d_a, &h_a.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b.front(), size, hipMemcpyHostToDevice);
// calculate the number of threads and blocks
// Launch the add kernel
// get the results from the GPU
hipMemcpy(&h_c.front(), d_c, size, hipMemcpyDeviceToHost);
// print top left corner
for(int i = 0; i < 5; i++) {
for(int j = 0; j < 10; j++)
cout << h_c[i * rows + j] << " ";
cout << endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_ii
.globl _Z3addPiS_S_ii
.p2align 8
.type _Z3addPiS_S_ii,@function
_Z3addPiS_S_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_ii, .Lfunc_end0-_Z3addPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Matrix Addition **
** **
** This program will add two matrices and store **
** the result in a third matrix using the GPU **
*************************************************/
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#define THREADS 10
using namespace std;
__global__ void add(int *a, int *b, int *c,int columns,int rows)
{
// get the global id for the thread
// calculate the index of the input data
// perform addition
}
int main(void)
{
int rows = 100;
int columns = 100;
int elements = rows * columns;
size_t size = rows * columns * sizeof(int);
// create device pointers
int* d_a;
int* d_b;
int* d_c;
// allocate memory on the device
hipMalloc(&d_a, size);
hipMalloc(&d_b, size); hipMalloc(&d_c, size);
// initalize host variables
vector<int> h_a(elements, 5);
vector<int> h_b(elements, 5);
vector<int> h_c(elements);
// transfer the host data to the GPU
hipMemcpy(d_a, &h_a.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b.front(), size, hipMemcpyHostToDevice);
// calculate the number of threads and blocks
// Launch the add kernel
// get the results from the GPU
hipMemcpy(&h_c.front(), d_c, size, hipMemcpyDeviceToHost);
// print top left corner
for(int i = 0; i < 5; i++) {
for(int j = 0; j < 10; j++)
cout << h_c[i * rows + j] << " ";
cout << endl;
}
} | .text
.file "matrix_addition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ii # -- Begin function _Z18__device_stub__addPiS_S_ii
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_ii,@function
_Z18__device_stub__addPiS_S_ii: # @_Z18__device_stub__addPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_ii, .Lfunc_end0-_Z18__device_stub__addPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movl $40000, %edi # imm = 0x9C40
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $5, (%rbx,%rax)
addq $4, %rax
cmpq $40000, %rax # imm = 0x9C40
jne .LBB1_1
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
.Ltmp0:
movl $40000, %edi # imm = 0x9C40
callq _Znwm
.Ltmp1:
# %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i34.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i34
# =>This Inner Loop Header: Depth=1
movl $5, (%r14,%rax)
addq $4, %rax
cmpq $40000, %rax # imm = 0x9C40
jne .LBB1_4
# %bb.5: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit38
.Ltmp3:
movl $40000, %edi # imm = 0x9C40
callq _Znwm
.Ltmp4:
# %bb.6: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
movq %rax, %r15
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq 16(%rsp), %rdi
.Ltmp6:
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp7:
# %bb.7:
movq 8(%rsp), %rdi
.Ltmp8:
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp9:
# %bb.8:
movq (%rsp), %rsi
.Ltmp10:
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp11:
# %bb.9: # %.preheader.preheader
xorl %r13d, %r13d
movq %r15, %rbp
.p2align 4, 0x90
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r12,4), %esi
.Ltmp13:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp14:
# %bb.12: # in Loop: Header=BB1_11 Depth=2
.Ltmp15:
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp16:
# %bb.13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_11 Depth=2
incq %r12
cmpq $10, %r12
jne .LBB1_11
# %bb.14: # in Loop: Header=BB1_10 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_15
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_10 Depth=1
cmpb $0, 56(%r12)
je .LBB1_22
# %bb.21: # in Loop: Header=BB1_10 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_10 Depth=1
.Ltmp18:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp19:
# %bb.23: # %.noexc54
# in Loop: Header=BB1_10 Depth=1
movq (%r12), %rax
.Ltmp20:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp21:
.LBB1_24: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_10 Depth=1
.Ltmp22:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp23:
# %bb.25: # %.noexc56
# in Loop: Header=BB1_10 Depth=1
.Ltmp24:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp25:
# %bb.26: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_10 Depth=1
incq %r13
addq $400, %rbp # imm = 0x190
cmpq $5, %r13
jne .LBB1_10
# %bb.27: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq %r15, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 80
.Ltmp27:
callq _ZSt16__throw_bad_castv
.Ltmp28:
# %bb.19: # %.noexc53
.LBB1_17:
.Ltmp5:
movq %rax, %r12
jmp .LBB1_31
.LBB1_16:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_32
.LBB1_18:
.Ltmp12:
jmp .LBB1_30
.LBB1_29: # %.loopexit.split-lp
.Ltmp29:
jmp .LBB1_30
.LBB1_28: # %.loopexit
.Ltmp26:
jmp .LBB1_30
.LBB1_33:
.Ltmp17:
.LBB1_30: # %_ZNSt6vectorIiSaIiEED2Ev.exit47
movq %rax, %r12
movq %r15, %rdi
callq _ZdlPv
.LBB1_31: # %_ZNSt6vectorIiSaIiEED2Ev.exit49
movq %r14, %rdi
callq _ZdlPv
.LBB1_32: # %_ZNSt6vectorIiSaIiEED2Ev.exit51
movq %rbx, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp11-.Ltmp6 # Call between .Ltmp6 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp13 # Call between .Ltmp13 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp25-.Ltmp18 # Call between .Ltmp18 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp28 # Call between .Ltmp28 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_ii,@object # @_Z3addPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_ii
.p2align 3, 0x0
_Z3addPiS_S_ii:
.quad _Z18__device_stub__addPiS_S_ii
.size _Z3addPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_ii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPiS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_ii
.globl _Z3addPiS_S_ii
.p2align 8
.type _Z3addPiS_S_ii,@function
_Z3addPiS_S_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_ii, .Lfunc_end0-_Z3addPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005b288_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
.type _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii, @function
_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii, .-_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
.globl _Z3addPiS_S_ii
.type _Z3addPiS_S_ii, @function
_Z3addPiS_S_ii:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z3addPiS_S_ii, .-_Z3addPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4371:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4371:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $40000, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $40000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 32(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 48(%rsp)
.L20:
movl $5, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 40(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $40000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbp
movq %rax, 64(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 80(%rsp)
.L21:
movl $5, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 72(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $40000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %r14
movq %rax, 96(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 112(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L22:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L22
movq %rdx, 104(%rsp)
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 40(%r14), %rbp
addq $2040, %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L23
.L45:
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
je .L44
.L24:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
jmp .L45
.L44:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L46
cmpb $0, 56(%rbx)
je .L27
movzbl 67(%rbx), %esi
.L28:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L47
.L46:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L37:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L31:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L32:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L33
call __stack_chk_fail@PLT
.L48:
call __stack_chk_fail@PLT
.L27:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L47:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE3:
addq $400, %rbp
cmpq %rbp, %r14
je .L29
.L23:
leaq -40(%rbp), %rbx
jmp .L24
.L29:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 32(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L31
.L35:
endbr64
movq %rax, %rbx
jmp .L32
.L33:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L35-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L36-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L37-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_addition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ii # -- Begin function _Z18__device_stub__addPiS_S_ii
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_ii,@function
_Z18__device_stub__addPiS_S_ii: # @_Z18__device_stub__addPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_ii, .Lfunc_end0-_Z18__device_stub__addPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movl $40000, %edi # imm = 0x9C40
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $5, (%rbx,%rax)
addq $4, %rax
cmpq $40000, %rax # imm = 0x9C40
jne .LBB1_1
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
.Ltmp0:
movl $40000, %edi # imm = 0x9C40
callq _Znwm
.Ltmp1:
# %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i34.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i34
# =>This Inner Loop Header: Depth=1
movl $5, (%r14,%rax)
addq $4, %rax
cmpq $40000, %rax # imm = 0x9C40
jne .LBB1_4
# %bb.5: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit38
.Ltmp3:
movl $40000, %edi # imm = 0x9C40
callq _Znwm
.Ltmp4:
# %bb.6: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
movq %rax, %r15
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq 16(%rsp), %rdi
.Ltmp6:
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp7:
# %bb.7:
movq 8(%rsp), %rdi
.Ltmp8:
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp9:
# %bb.8:
movq (%rsp), %rsi
.Ltmp10:
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp11:
# %bb.9: # %.preheader.preheader
xorl %r13d, %r13d
movq %r15, %rbp
.p2align 4, 0x90
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r12,4), %esi
.Ltmp13:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp14:
# %bb.12: # in Loop: Header=BB1_11 Depth=2
.Ltmp15:
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp16:
# %bb.13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_11 Depth=2
incq %r12
cmpq $10, %r12
jne .LBB1_11
# %bb.14: # in Loop: Header=BB1_10 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_15
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_10 Depth=1
cmpb $0, 56(%r12)
je .LBB1_22
# %bb.21: # in Loop: Header=BB1_10 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_22: # in Loop: Header=BB1_10 Depth=1
.Ltmp18:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp19:
# %bb.23: # %.noexc54
# in Loop: Header=BB1_10 Depth=1
movq (%r12), %rax
.Ltmp20:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp21:
.LBB1_24: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_10 Depth=1
.Ltmp22:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp23:
# %bb.25: # %.noexc56
# in Loop: Header=BB1_10 Depth=1
.Ltmp24:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp25:
# %bb.26: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_10 Depth=1
incq %r13
addq $400, %rbp # imm = 0x190
cmpq $5, %r13
jne .LBB1_10
# %bb.27: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq %r15, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 80
.Ltmp27:
callq _ZSt16__throw_bad_castv
.Ltmp28:
# %bb.19: # %.noexc53
.LBB1_17:
.Ltmp5:
movq %rax, %r12
jmp .LBB1_31
.LBB1_16:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_32
.LBB1_18:
.Ltmp12:
jmp .LBB1_30
.LBB1_29: # %.loopexit.split-lp
.Ltmp29:
jmp .LBB1_30
.LBB1_28: # %.loopexit
.Ltmp26:
jmp .LBB1_30
.LBB1_33:
.Ltmp17:
.LBB1_30: # %_ZNSt6vectorIiSaIiEED2Ev.exit47
movq %rax, %r12
movq %r15, %rdi
callq _ZdlPv
.LBB1_31: # %_ZNSt6vectorIiSaIiEED2Ev.exit49
movq %r14, %rdi
callq _ZdlPv
.LBB1_32: # %_ZNSt6vectorIiSaIiEED2Ev.exit51
movq %rbx, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp11-.Ltmp6 # Call between .Ltmp6 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp13 # Call between .Ltmp13 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp25-.Ltmp18 # Call between .Ltmp18 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp28 # Call between .Ltmp28 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_ii,@object # @_Z3addPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_ii
.p2align 3, 0x0
_Z3addPiS_S_ii:
.quad _Z18__device_stub__addPiS_S_ii
.size _Z3addPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_ii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPiS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define pi 3.141592653589793
using namespace std;
__global__ void remosaic_cuda(float *quad_raw, float *raw, float *in_GX, float *in_GY,int h_hsize,int f_hsize,int types_size, int Qangle, int Qstrength, int Qcoherence, float *stre, float * cohe, float *Q, float *V,float *mark,int row,int col,int width)
{
int x = threadIdx.x+ blockIdx.x* blockDim.x;
int y = threadIdx.y+ blockIdx.y* blockDim.y;
int p_hsize = max(h_hsize, f_hsize);
//int tid = j1 + i1*col;
if(x < p_hsize ||x >= col - p_hsize)
return;
if(y < p_hsize ||y >= row - p_hsize)
return;
int pos = y % types_size * types_size + x % types_size;
float dx_val=0.0;
float dy_val=0.0;
int rect_w=2*p_hsize+1;
int rect_h=2*p_hsize+1;
float g00 = 0.0;
float g01 = 0.0;
float g11 = 0.0;
//for i in range(0-p_hsize,p_hsize+1):
// for j in range(0-p_hsize,p_hsize+1):
// dx_val = dx[(y+i),(x+j)]
// dy_val = dy[(y+i),(x+j)]
// g00 += dx_val * dx_val
// g01 += dx_val * dy_val
// g11 += dy_val * dy_val
for(int i = 0-p_hsize;i<p_hsize+1;i++)
{
for(int j= 0-p_hsize;j<p_hsize+1;j++)
{
float dx_val = in_GX[(y+i)*width+x+j];
float dy_val = in_GY[(y+i)*width+x+j];
g00 += dx_val * dx_val;
g01 += dx_val * dy_val;
g11 += dy_val * dy_val;
}
}
float tmp1 = g00 + g11;
float tmp2 = sqrt((g00 - g11) * (g00 - g11) + 4 * g01 * g01);
float S1 = (tmp1 + tmp2) / 2;
float S2 = (tmp1 - tmp2) / 2;
float theta = 0;
if(fabs(g01)>1e-9)
{
theta =atan((g00-S1)/(-g01))/pi*180;
}
else if(g00>g11)
{
theta = 90;
}
else{
theta = 0;
}
if(theta<0){
theta = theta + 180;
}
int Q_theta = ceil(theta/180*Qangle);
if(Q_theta==0){
Q_theta = 1;
}
Q_theta= Q_theta -1;
float lamda = sqrt(S1);
float u = (sqrt(S1) - sqrt(S2))/(sqrt(S1) + sqrt(S2) + 0.00000000000000001);
//Q_lamda = len(stre)
//Q_u = len(cohe)
//for k in reversed(range(0,len(stre))):
// if(lamda < stre[k]):
// Q_lamda = k
//for k in reversed(range(0,len(cohe))):
// if(u < cohe[k]):
// Q_u = k
int Q_lamda = Qstrength-1;
int Q_u = Qcoherence -1;
for(int k=Qstrength-1; k>=0; k--){
Q_lamda = lamda < stre[k] ? k : Q_lamda;
}
for(int k=Qcoherence-1; k>=0; k--){
Q_u = u < cohe[k] ? k : Q_u;
}
int dim0 = Qangle*Qstrength * Qcoherence;
int index = Q_theta * Qstrength * Qcoherence + Q_lamda * Qcoherence + Q_u;
atomicAdd(mark + pos*dim0+index, 1);
int patchL_shape_2 = (2*h_hsize+1)*(2*h_hsize+1);
int V_offset = pos*dim0*patchL_shape_2+index*patchL_shape_2;
//int Q_offset = pos*dim0*patchL_shape_2*patchL_shape_2 + index*patchL_shape_2*patchL_shape_2;
int Q_offset = V_offset*patchL_shape_2;
float *Q_ptr = Q+Q_offset;
float *V_ptr = V+V_offset;
int patchL_dim0 = 0;
int patchL_dim1 = 0;
for(int i=y-h_hsize;i<y+h_hsize+1;i++)
{
for(int j=x-h_hsize; j< x+h_hsize+1;j++)
{
float val = quad_raw[i*width+j];
for(int k= y-h_hsize;k<y+h_hsize+1;k++)
{
for(int m= x-h_hsize;m<x+h_hsize+1;m++)
{
float ret=val*quad_raw[k*width+m];
atomicAdd(Q_ptr + patchL_dim1, ret);
patchL_dim1+=1;
}
}
float b1 = val*raw[y*width+x];
atomicAdd(V_ptr+patchL_dim0, b1);
patchL_dim0 +=1;
}
}
}; | .file "tmpxft_0011707e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii
.type _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii, @function
_Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii:
.LFB2081:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 352(%rsp), %rax
movq %rax, 32(%rsp)
movq 360(%rsp), %rax
movq %rax, 24(%rsp)
movq 368(%rsp), %rax
movq %rax, 16(%rsp)
movq 376(%rsp), %rax
movq %rax, 8(%rsp)
movq 384(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movq %rsp, %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 328
pushq 88(%rsp)
.cfi_def_cfa_offset 336
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii, .-_Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii
.globl _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.type _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, @function
_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
pushq 104(%rsp)
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
call _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, .-_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define pi 3.141592653589793
using namespace std;
__global__ void remosaic_cuda(float *quad_raw, float *raw, float *in_GX, float *in_GY,int h_hsize,int f_hsize,int types_size, int Qangle, int Qstrength, int Qcoherence, float *stre, float * cohe, float *Q, float *V,float *mark,int row,int col,int width)
{
int x = threadIdx.x+ blockIdx.x* blockDim.x;
int y = threadIdx.y+ blockIdx.y* blockDim.y;
int p_hsize = max(h_hsize, f_hsize);
//int tid = j1 + i1*col;
if(x < p_hsize ||x >= col - p_hsize)
return;
if(y < p_hsize ||y >= row - p_hsize)
return;
int pos = y % types_size * types_size + x % types_size;
float dx_val=0.0;
float dy_val=0.0;
int rect_w=2*p_hsize+1;
int rect_h=2*p_hsize+1;
float g00 = 0.0;
float g01 = 0.0;
float g11 = 0.0;
//for i in range(0-p_hsize,p_hsize+1):
// for j in range(0-p_hsize,p_hsize+1):
// dx_val = dx[(y+i),(x+j)]
// dy_val = dy[(y+i),(x+j)]
// g00 += dx_val * dx_val
// g01 += dx_val * dy_val
// g11 += dy_val * dy_val
for(int i = 0-p_hsize;i<p_hsize+1;i++)
{
for(int j= 0-p_hsize;j<p_hsize+1;j++)
{
float dx_val = in_GX[(y+i)*width+x+j];
float dy_val = in_GY[(y+i)*width+x+j];
g00 += dx_val * dx_val;
g01 += dx_val * dy_val;
g11 += dy_val * dy_val;
}
}
float tmp1 = g00 + g11;
float tmp2 = sqrt((g00 - g11) * (g00 - g11) + 4 * g01 * g01);
float S1 = (tmp1 + tmp2) / 2;
float S2 = (tmp1 - tmp2) / 2;
float theta = 0;
if(fabs(g01)>1e-9)
{
theta =atan((g00-S1)/(-g01))/pi*180;
}
else if(g00>g11)
{
theta = 90;
}
else{
theta = 0;
}
if(theta<0){
theta = theta + 180;
}
int Q_theta = ceil(theta/180*Qangle);
if(Q_theta==0){
Q_theta = 1;
}
Q_theta= Q_theta -1;
float lamda = sqrt(S1);
float u = (sqrt(S1) - sqrt(S2))/(sqrt(S1) + sqrt(S2) + 0.00000000000000001);
//Q_lamda = len(stre)
//Q_u = len(cohe)
//for k in reversed(range(0,len(stre))):
// if(lamda < stre[k]):
// Q_lamda = k
//for k in reversed(range(0,len(cohe))):
// if(u < cohe[k]):
// Q_u = k
int Q_lamda = Qstrength-1;
int Q_u = Qcoherence -1;
for(int k=Qstrength-1; k>=0; k--){
Q_lamda = lamda < stre[k] ? k : Q_lamda;
}
for(int k=Qcoherence-1; k>=0; k--){
Q_u = u < cohe[k] ? k : Q_u;
}
int dim0 = Qangle*Qstrength * Qcoherence;
int index = Q_theta * Qstrength * Qcoherence + Q_lamda * Qcoherence + Q_u;
atomicAdd(mark + pos*dim0+index, 1);
int patchL_shape_2 = (2*h_hsize+1)*(2*h_hsize+1);
int V_offset = pos*dim0*patchL_shape_2+index*patchL_shape_2;
//int Q_offset = pos*dim0*patchL_shape_2*patchL_shape_2 + index*patchL_shape_2*patchL_shape_2;
int Q_offset = V_offset*patchL_shape_2;
float *Q_ptr = Q+Q_offset;
float *V_ptr = V+V_offset;
int patchL_dim0 = 0;
int patchL_dim1 = 0;
for(int i=y-h_hsize;i<y+h_hsize+1;i++)
{
for(int j=x-h_hsize; j< x+h_hsize+1;j++)
{
float val = quad_raw[i*width+j];
for(int k= y-h_hsize;k<y+h_hsize+1;k++)
{
for(int m= x-h_hsize;m<x+h_hsize+1;m++)
{
float ret=val*quad_raw[k*width+m];
atomicAdd(Q_ptr + patchL_dim1, ret);
patchL_dim1+=1;
}
}
float b1 = val*raw[y*width+x];
atomicAdd(V_ptr+patchL_dim0, b1);
patchL_dim0 +=1;
}
}
}; | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define pi 3.141592653589793
using namespace std;
__global__ void remosaic_cuda(float *quad_raw, float *raw, float *in_GX, float *in_GY,int h_hsize,int f_hsize,int types_size, int Qangle, int Qstrength, int Qcoherence, float *stre, float * cohe, float *Q, float *V,float *mark,int row,int col,int width)
{
int x = threadIdx.x+ blockIdx.x* blockDim.x;
int y = threadIdx.y+ blockIdx.y* blockDim.y;
int p_hsize = max(h_hsize, f_hsize);
//int tid = j1 + i1*col;
if(x < p_hsize ||x >= col - p_hsize)
return;
if(y < p_hsize ||y >= row - p_hsize)
return;
int pos = y % types_size * types_size + x % types_size;
float dx_val=0.0;
float dy_val=0.0;
int rect_w=2*p_hsize+1;
int rect_h=2*p_hsize+1;
float g00 = 0.0;
float g01 = 0.0;
float g11 = 0.0;
//for i in range(0-p_hsize,p_hsize+1):
// for j in range(0-p_hsize,p_hsize+1):
// dx_val = dx[(y+i),(x+j)]
// dy_val = dy[(y+i),(x+j)]
// g00 += dx_val * dx_val
// g01 += dx_val * dy_val
// g11 += dy_val * dy_val
for(int i = 0-p_hsize;i<p_hsize+1;i++)
{
for(int j= 0-p_hsize;j<p_hsize+1;j++)
{
float dx_val = in_GX[(y+i)*width+x+j];
float dy_val = in_GY[(y+i)*width+x+j];
g00 += dx_val * dx_val;
g01 += dx_val * dy_val;
g11 += dy_val * dy_val;
}
}
float tmp1 = g00 + g11;
float tmp2 = sqrt((g00 - g11) * (g00 - g11) + 4 * g01 * g01);
float S1 = (tmp1 + tmp2) / 2;
float S2 = (tmp1 - tmp2) / 2;
float theta = 0;
if(fabs(g01)>1e-9)
{
theta =atan((g00-S1)/(-g01))/pi*180;
}
else if(g00>g11)
{
theta = 90;
}
else{
theta = 0;
}
if(theta<0){
theta = theta + 180;
}
int Q_theta = ceil(theta/180*Qangle);
if(Q_theta==0){
Q_theta = 1;
}
Q_theta= Q_theta -1;
float lamda = sqrt(S1);
float u = (sqrt(S1) - sqrt(S2))/(sqrt(S1) + sqrt(S2) + 0.00000000000000001);
//Q_lamda = len(stre)
//Q_u = len(cohe)
//for k in reversed(range(0,len(stre))):
// if(lamda < stre[k]):
// Q_lamda = k
//for k in reversed(range(0,len(cohe))):
// if(u < cohe[k]):
// Q_u = k
int Q_lamda = Qstrength-1;
int Q_u = Qcoherence -1;
for(int k=Qstrength-1; k>=0; k--){
Q_lamda = lamda < stre[k] ? k : Q_lamda;
}
for(int k=Qcoherence-1; k>=0; k--){
Q_u = u < cohe[k] ? k : Q_u;
}
int dim0 = Qangle*Qstrength * Qcoherence;
int index = Q_theta * Qstrength * Qcoherence + Q_lamda * Qcoherence + Q_u;
atomicAdd(mark + pos*dim0+index, 1);
int patchL_shape_2 = (2*h_hsize+1)*(2*h_hsize+1);
int V_offset = pos*dim0*patchL_shape_2+index*patchL_shape_2;
//int Q_offset = pos*dim0*patchL_shape_2*patchL_shape_2 + index*patchL_shape_2*patchL_shape_2;
int Q_offset = V_offset*patchL_shape_2;
float *Q_ptr = Q+Q_offset;
float *V_ptr = V+V_offset;
int patchL_dim0 = 0;
int patchL_dim1 = 0;
for(int i=y-h_hsize;i<y+h_hsize+1;i++)
{
for(int j=x-h_hsize; j< x+h_hsize+1;j++)
{
float val = quad_raw[i*width+j];
for(int k= y-h_hsize;k<y+h_hsize+1;k++)
{
for(int m= x-h_hsize;m<x+h_hsize+1;m++)
{
float ret=val*quad_raw[k*width+m];
atomicAdd(Q_ptr + patchL_dim1, ret);
patchL_dim1+=1;
}
}
float b1 = val*raw[y*width+x];
atomicAdd(V_ptr+patchL_dim0, b1);
patchL_dim0 +=1;
}
}
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define pi 3.141592653589793
using namespace std;
__global__ void remosaic_cuda(float *quad_raw, float *raw, float *in_GX, float *in_GY,int h_hsize,int f_hsize,int types_size, int Qangle, int Qstrength, int Qcoherence, float *stre, float * cohe, float *Q, float *V,float *mark,int row,int col,int width)
{
int x = threadIdx.x+ blockIdx.x* blockDim.x;
int y = threadIdx.y+ blockIdx.y* blockDim.y;
int p_hsize = max(h_hsize, f_hsize);
//int tid = j1 + i1*col;
if(x < p_hsize ||x >= col - p_hsize)
return;
if(y < p_hsize ||y >= row - p_hsize)
return;
int pos = y % types_size * types_size + x % types_size;
float dx_val=0.0;
float dy_val=0.0;
int rect_w=2*p_hsize+1;
int rect_h=2*p_hsize+1;
float g00 = 0.0;
float g01 = 0.0;
float g11 = 0.0;
//for i in range(0-p_hsize,p_hsize+1):
// for j in range(0-p_hsize,p_hsize+1):
// dx_val = dx[(y+i),(x+j)]
// dy_val = dy[(y+i),(x+j)]
// g00 += dx_val * dx_val
// g01 += dx_val * dy_val
// g11 += dy_val * dy_val
for(int i = 0-p_hsize;i<p_hsize+1;i++)
{
for(int j= 0-p_hsize;j<p_hsize+1;j++)
{
float dx_val = in_GX[(y+i)*width+x+j];
float dy_val = in_GY[(y+i)*width+x+j];
g00 += dx_val * dx_val;
g01 += dx_val * dy_val;
g11 += dy_val * dy_val;
}
}
float tmp1 = g00 + g11;
float tmp2 = sqrt((g00 - g11) * (g00 - g11) + 4 * g01 * g01);
float S1 = (tmp1 + tmp2) / 2;
float S2 = (tmp1 - tmp2) / 2;
float theta = 0;
if(fabs(g01)>1e-9)
{
theta =atan((g00-S1)/(-g01))/pi*180;
}
else if(g00>g11)
{
theta = 90;
}
else{
theta = 0;
}
if(theta<0){
theta = theta + 180;
}
int Q_theta = ceil(theta/180*Qangle);
if(Q_theta==0){
Q_theta = 1;
}
Q_theta= Q_theta -1;
float lamda = sqrt(S1);
float u = (sqrt(S1) - sqrt(S2))/(sqrt(S1) + sqrt(S2) + 0.00000000000000001);
//Q_lamda = len(stre)
//Q_u = len(cohe)
//for k in reversed(range(0,len(stre))):
// if(lamda < stre[k]):
// Q_lamda = k
//for k in reversed(range(0,len(cohe))):
// if(u < cohe[k]):
// Q_u = k
int Q_lamda = Qstrength-1;
int Q_u = Qcoherence -1;
for(int k=Qstrength-1; k>=0; k--){
Q_lamda = lamda < stre[k] ? k : Q_lamda;
}
for(int k=Qcoherence-1; k>=0; k--){
Q_u = u < cohe[k] ? k : Q_u;
}
int dim0 = Qangle*Qstrength * Qcoherence;
int index = Q_theta * Qstrength * Qcoherence + Q_lamda * Qcoherence + Q_u;
atomicAdd(mark + pos*dim0+index, 1);
int patchL_shape_2 = (2*h_hsize+1)*(2*h_hsize+1);
int V_offset = pos*dim0*patchL_shape_2+index*patchL_shape_2;
//int Q_offset = pos*dim0*patchL_shape_2*patchL_shape_2 + index*patchL_shape_2*patchL_shape_2;
int Q_offset = V_offset*patchL_shape_2;
float *Q_ptr = Q+Q_offset;
float *V_ptr = V+V_offset;
int patchL_dim0 = 0;
int patchL_dim1 = 0;
for(int i=y-h_hsize;i<y+h_hsize+1;i++)
{
for(int j=x-h_hsize; j< x+h_hsize+1;j++)
{
float val = quad_raw[i*width+j];
for(int k= y-h_hsize;k<y+h_hsize+1;k++)
{
for(int m= x-h_hsize;m<x+h_hsize+1;m++)
{
float ret=val*quad_raw[k*width+m];
atomicAdd(Q_ptr + patchL_dim1, ret);
patchL_dim1+=1;
}
}
float b1 = val*raw[y*width+x];
atomicAdd(V_ptr+patchL_dim0, b1);
patchL_dim0 +=1;
}
}
}; | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.globl _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.p2align 8
.type _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii,@function
_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x7c
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b32 s6, s[0:1], 0x64
s_add_u32 s4, s0, 0x70
v_and_b32_e32 v10, 0x3ff, v0
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_max_i32 s3, s8, s9
s_mul_i32 s14, s14, s2
s_sub_i32 s2, s6, s3
v_add_nc_u32_e32 v1, s14, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s3, v1
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_35
s_load_b32 s2, s[4:5], 0xc
s_load_b32 s4, s[0:1], 0x60
v_bfe_u32 v11, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_sub_i32 s2, s4, s3
v_add_nc_u32_e32 v12, s15, v11
v_cmp_le_i32_e32 vcc_lo, s3, v12
v_cmp_gt_i32_e64 s2, s2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_35
s_clause 0x1
s_load_b32 s10, s[0:1], 0x28
s_load_b32 s9, s[0:1], 0x68
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v14, 31, v1
v_mov_b32_e32 v17, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v12, v13
v_add_nc_u32_e32 v4, v1, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v15, v3, v13
v_xor_b32_e32 v16, v4, v14
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s10, s2
s_xor_b32 s11, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s11
s_sub_i32 s2, 0, s11
s_cmp_lt_i32 s3, 0
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v15, v0, 0
v_mad_u64_u32 v[2:3], null, v16, v0, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v0, 0
s_cbranch_scc1 .LBB0_8
v_subrev_nc_u32_e32 v0, s3, v12
s_load_b128 s[4:7], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v17, 0
s_sub_i32 s12, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s9, v0
s_not_b32 s2, s3
v_add3_u32 v5, v10, v0, s14
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v5
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s13, s2
v_lshlrev_b64 v[8:9], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
.LBB0_5:
global_load_b32 v18, v[6:7], off
global_load_b32 v19, v[8:9], off
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s13, s3
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v2, v18, v18 :: v_dual_fmac_f32 v17, v19, v19
v_fmac_f32_e32 v0, v18, v19
s_cbranch_scc0 .LBB0_5
v_add_nc_u32_e32 v5, s9, v5
s_add_i32 s13, s12, 1
s_cmp_ge_i32 s12, s3
s_cbranch_scc1 .LBB0_8
s_mov_b32 s12, s13
s_branch .LBB0_4
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_sub_f32 v7, v2, v17 :: v_dual_mul_f32 v8, 4.0, v0
v_cvt_f64_f32_e64 v[5:6], |v0|
s_mov_b32 s3, 0x3e112e0b
s_mov_b32 s2, 0xe826d695
v_mul_f32_e32 v7, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v0, v8
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
v_mul_f32_e32 v8, 0x4f800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_sqrt_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v9, -1, v8
v_cmp_nlt_f64_e64 s2, s[2:3], v[5:6]
v_add_nc_u32_e32 v5, 1, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v9, v8, v7
v_fma_f32 v18, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, 0, v6
v_cndmask_b32_e64 v6, v8, v9, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s3, 0, v18
v_cndmask_b32_e64 v5, v6, v5, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x37800000, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v7, 0x260
v_add_f32_e32 v6, v17, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v5, v7, vcc_lo
v_add_f32_e32 v8, v6, v7
s_and_saveexec_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s3
v_cmp_gt_f32_e32 vcc_lo, v2, v17
v_cndmask_b32_e64 v5, 0, 0x42b40000, vcc_lo
s_or_saveexec_b32 s2, s2
v_mul_f32_e32 v8, 0.5, v8
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v8
s_mov_b32 s3, 0x3b2d2a58
s_mov_b32 s5, 0x400921fb
s_mov_b32 s4, 0x54442d18
v_div_scale_f32 v5, null, -v0, -v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v17, -v5, v9, 1.0
v_fmac_f32_e32 v9, v17, v9
v_div_scale_f32 v18, vcc_lo, v2, -v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v17, v18, v9
v_fma_f32 v19, -v5, v17, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v19, v9
v_fma_f32 v5, -v5, v17, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v9, v17
v_div_fixup_f32 v0, v5, -v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e64 v2, |v0|
v_cmp_gt_f32_e64 vcc_lo, |v0|, 1.0
s_waitcnt_depctr 0xfff
v_cndmask_b32_e64 v2, |v0|, v2, vcc_lo
v_mul_f32_e32 v5, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, s3, v5, 0xbc7a590c
v_fmaak_f32 v9, v5, v9, 0x3d29fb3f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v5, v9, 0xbd97d4d7
v_fmaak_f32 v9, v5, v9, 0x3dd931b2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v5, v9, 0xbe1160e6
v_fmaak_f32 v9, v5, v9, 0x3e4cb8bf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v5, v9, 0xbeaaaa62
v_mul_f32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v2, v5
v_sub_f32_e32 v5, 0x3fc90fdb, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_bfi_b32 v0, 0x7fffffff, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[17:18], v0
v_div_scale_f64 v[19:20], null, s[4:5], s[4:5], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[21:22], v[19:20]
s_waitcnt_depctr 0xfff
v_fma_f64 v[23:24], -v[19:20], v[21:22], 1.0
v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[23:24], -v[19:20], v[21:22], 1.0
v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
v_div_scale_f64 v[23:24], vcc_lo, v[17:18], s[4:5], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[25:26], v[23:24], v[21:22]
v_fma_f64 v[19:20], -v[19:20], v[25:26], v[23:24]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[19:20], v[19:20], v[21:22], v[25:26]
v_div_fixup_f64 v[17:18], v[19:20], s[4:5], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[17:18], 0x40668000
v_cvt_f32_f64_e32 v5, v[17:18]
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f32_e32 v0, 0x4f800000, v8
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v8
s_load_b32 s6, s[0:1], 0x30
s_mov_b32 s3, 0
v_cndmask_b32_e32 v0, v8, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v2, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v9, 1, v2
v_add_nc_u32_e32 v8, -1, v2
v_fma_f32 v18, -v9, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v17, -v8, v2, v0
v_cmp_ge_f32_e64 s2, 0, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v2, v2, v8, s2
v_cmp_lt_f32_e64 s2, 0, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, v9, s2
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s6, -1
s_cmp_lt_i32 s6, 1
v_mul_f32_e32 v8, 0x37800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
v_cndmask_b32_e32 v8, v2, v0, vcc_lo
v_mov_b32_e32 v0, s2
s_cbranch_scc1 .LBB0_15
s_load_b64 s[4:5], s[0:1], 0x38
s_lshl_b64 s[12:13], s[2:3], 2
v_mov_b32_e32 v0, s2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s12
s_addc_u32 s3, s5, s13
s_mov_b32 s4, s6
.LBB0_14:
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, -4
s_addc_u32 s3, s3, -1
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s5, v8
v_cndmask_b32_e64 v0, v0, s4, vcc_lo
s_cbranch_scc0 .LBB0_14
.LBB0_15:
s_load_b32 s7, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s7, -1
s_cmp_lt_i32 s7, 1
v_mov_b32_e32 v2, s4
s_cbranch_scc1 .LBB0_18
v_sub_f32_e32 v2, v6, v7
s_mov_b32 s3, 0x3c670ef5
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[12:13], s[4:5], 2
v_mul_f32_e32 v2, 0.5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v6, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v9, 1, v6
v_fma_f32 v17, -v7, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v18, -v9, v6, v2
v_cmp_ge_f32_e64 s2, 0, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v6, v6, v7, s2
v_cmp_lt_f32_e64 s2, 0, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v6, v9, s2
s_mov_b32 s2, 0x4646d497
v_mul_f32_e32 v7, 0x37800000, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v6, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v8, v2
v_sub_f32_e32 v2, v8, v2
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[8:9], v2
v_mov_b32_e32 v2, s4
s_mov_b32 s4, s7
v_add_f64 v[6:7], v[6:7], s[2:3]
s_load_b64 s[2:3], s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s12
s_addc_u32 s3, s3, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[17:18], null, v[6:7], v[6:7], v[8:9]
v_rcp_f64_e32 v[19:20], v[17:18]
s_waitcnt_depctr 0xfff
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
v_div_scale_f64 v[21:22], vcc_lo, v[8:9], v[6:7], v[8:9]
v_mul_f64 v[23:24], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[17:18], v[23:24], v[21:22]
v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[23:24]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[17:18], v[6:7], v[8:9]
v_cvt_f32_f64_e32 v6, v[6:7]
.LBB0_17:
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, -4
s_addc_u32 s3, s3, -1
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, s5, v6
v_cndmask_b32_e64 v2, v2, s4, vcc_lo
s_cbranch_scc0 .LBB0_17
.LBB0_18:
v_mul_lo_u32 v4, v4, s11
v_add_f32_e32 v6, 0x43340000, v5
v_cmp_gt_f32_e32 vcc_lo, 0, v5
v_mul_lo_u32 v3, v3, s11
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x58
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v15, v4
v_sub_nc_u32_e32 v3, v16, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v15, s11, v4
v_cmp_le_u32_e64 s2, s11, v4
v_subrev_nc_u32_e32 v16, s11, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v15, s2
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s6, s3
v_div_scale_f32 v6, null, 0x43340000, 0x43340000, v5
v_div_scale_f32 v9, vcc_lo, v5, 0x43340000, v5
s_mul_i32 s2, s2, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v17, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v17, v7
v_fma_f32 v6, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v8
v_cmp_le_u32_e32 vcc_lo, s11, v3
v_subrev_nc_u32_e32 v8, s11, v4
v_cvt_f32_i32_e32 v7, s3
v_cndmask_b32_e32 v3, v3, v16, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
v_div_fixup_f32 v5, v6, 0x43340000, v5
v_subrev_nc_u32_e32 v6, s11, v3
v_cmp_le_u32_e32 vcc_lo, s11, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v13
v_mul_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_sub_nc_u32_e32 v6, v4, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ceil_f32_e32 v5, v5
v_xor_b32_e32 v3, v3, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v5, v5
v_sub_nc_u32_e32 v3, v3, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e64 v9, v5, 1 clamp
v_mad_u64_u32 v[4:5], null, v6, s10, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v9, s6, v[0:1]
v_mul_lo_u32 v3, s2, v4
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, s7, v[2:3]
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[13:14], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v0, v13
v_add_co_ci_u32_e32 v7, vcc_lo, v2, v14, vcc_lo
global_load_b32 v9, v[6:7], off
.LBB0_19:
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, 1.0, v9
global_atomic_cmpswap_b32 v0, v[6:7], v[8:9], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v9
v_mov_b32_e32 v9, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_19
s_or_b32 exec_lo, exec_lo, s2
v_subrev_nc_u32_e32 v9, s8, v12
v_add_nc_u32_e32 v0, s8, v12
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, v9, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_35
s_lshl_b32 s2, s8, 1
v_add_nc_u32_e32 v0, v5, v3
s_or_b32 s2, s2, 1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[16:19], s[0:1], 0x48
s_mul_i32 s2, s2, s2
v_mad_u64_u32 v[2:3], null, v12, s9, v[1:2]
v_mul_lo_u32 v4, v0, s2
v_subrev_nc_u32_e32 v12, s8, v1
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, s8, v1
v_add3_u32 v10, s14, s8, v10
v_add3_u32 v11, s15, s8, v11
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, v12, v1
v_mul_lo_u32 v6, v4, s2
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v17, v9
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s0, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v13, s0, s18, v4
v_mov_b32_e32 v4, 0
v_add_co_ci_u32_e64 v14, s0, s19, v5, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v15, s0, s16, v6
v_add_co_ci_u32_e64 v16, s0, s17, v7, s0
s_branch .LBB0_23
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, 1, v17
v_cmp_eq_u32_e64 s0, v17, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v17, v1
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_35
.LBB0_23:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_22
v_mul_lo_u32 v18, v17, s9
v_mov_b32_e32 v19, v12
s_mov_b32 s3, 0
.LBB0_25:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v19, v18
v_mov_b32_e32 v21, v9
s_mov_b32 s6, 0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s0, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_b32 v20, v[5:6], off
.LBB0_26:
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v22, v21, s9
v_mov_b32_e32 v23, v12
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_27:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v23, v22
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s8, 0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_b32 v1, v[5:6], off
v_add_co_u32 v5, s0, v15, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, v16, v8, s0
global_load_b32 v8, v[5:6], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, v20, v1
.LBB0_28:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, v8, v1
global_atomic_cmpswap_b32 v7, v[5:6], v[7:8], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v7, v8
v_mov_b32_e32 v8, v7
s_or_b32 s8, s0, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_28
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v1, 1, v23
v_cmp_eq_u32_e64 s0, v23, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v23, v1 :: v_dual_add_nc_u32 v0, 1, v0
s_or_b32 s7, s0, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_27
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, 1, v21
v_cmp_eq_u32_e64 s0, v21, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v21, v1
s_or_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_26
s_or_b32 exec_lo, exec_lo, s6
v_ashrrev_i32_e32 v5, 31, v4
global_load_b32 v1, v[2:3], off
s_mov_b32 s6, 0
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, v13, v5
v_add_co_ci_u32_e64 v6, s0, v14, v6, s0
global_load_b32 v8, v[5:6], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, v20, v1
.LBB0_32:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, v8, v1
global_atomic_cmpswap_b32 v7, v[5:6], v[7:8], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v7, v8
v_mov_b32_e32 v8, v7
s_or_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_32
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, 1, v19
v_cmp_eq_u32_e64 s0, v19, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v19, v1 :: v_dual_add_nc_u32 v4, 1, v4
s_or_b32 s3, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_25
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_22
.LBB0_35:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 368
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, .Lfunc_end0-_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .offset: 96
.size: 4
.value_kind: by_value
- .offset: 100
.size: 4
.value_kind: by_value
- .offset: 104
.size: 4
.value_kind: by_value
- .offset: 112
.size: 4
.value_kind: hidden_block_count_x
- .offset: 116
.size: 4
.value_kind: hidden_block_count_y
- .offset: 120
.size: 4
.value_kind: hidden_block_count_z
- .offset: 124
.size: 2
.value_kind: hidden_group_size_x
- .offset: 126
.size: 2
.value_kind: hidden_group_size_y
- .offset: 128
.size: 2
.value_kind: hidden_group_size_z
- .offset: 130
.size: 2
.value_kind: hidden_remainder_x
- .offset: 132
.size: 2
.value_kind: hidden_remainder_y
- .offset: 134
.size: 2
.value_kind: hidden_remainder_z
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 176
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 368
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#define pi 3.141592653589793
using namespace std;
__global__ void remosaic_cuda(float *quad_raw, float *raw, float *in_GX, float *in_GY,int h_hsize,int f_hsize,int types_size, int Qangle, int Qstrength, int Qcoherence, float *stre, float * cohe, float *Q, float *V,float *mark,int row,int col,int width)
{
int x = threadIdx.x+ blockIdx.x* blockDim.x;
int y = threadIdx.y+ blockIdx.y* blockDim.y;
int p_hsize = max(h_hsize, f_hsize);
//int tid = j1 + i1*col;
if(x < p_hsize ||x >= col - p_hsize)
return;
if(y < p_hsize ||y >= row - p_hsize)
return;
int pos = y % types_size * types_size + x % types_size;
float dx_val=0.0;
float dy_val=0.0;
int rect_w=2*p_hsize+1;
int rect_h=2*p_hsize+1;
float g00 = 0.0;
float g01 = 0.0;
float g11 = 0.0;
//for i in range(0-p_hsize,p_hsize+1):
// for j in range(0-p_hsize,p_hsize+1):
// dx_val = dx[(y+i),(x+j)]
// dy_val = dy[(y+i),(x+j)]
// g00 += dx_val * dx_val
// g01 += dx_val * dy_val
// g11 += dy_val * dy_val
for(int i = 0-p_hsize;i<p_hsize+1;i++)
{
for(int j= 0-p_hsize;j<p_hsize+1;j++)
{
float dx_val = in_GX[(y+i)*width+x+j];
float dy_val = in_GY[(y+i)*width+x+j];
g00 += dx_val * dx_val;
g01 += dx_val * dy_val;
g11 += dy_val * dy_val;
}
}
float tmp1 = g00 + g11;
float tmp2 = sqrt((g00 - g11) * (g00 - g11) + 4 * g01 * g01);
float S1 = (tmp1 + tmp2) / 2;
float S2 = (tmp1 - tmp2) / 2;
float theta = 0;
if(fabs(g01)>1e-9)
{
theta =atan((g00-S1)/(-g01))/pi*180;
}
else if(g00>g11)
{
theta = 90;
}
else{
theta = 0;
}
if(theta<0){
theta = theta + 180;
}
int Q_theta = ceil(theta/180*Qangle);
if(Q_theta==0){
Q_theta = 1;
}
Q_theta= Q_theta -1;
float lamda = sqrt(S1);
float u = (sqrt(S1) - sqrt(S2))/(sqrt(S1) + sqrt(S2) + 0.00000000000000001);
//Q_lamda = len(stre)
//Q_u = len(cohe)
//for k in reversed(range(0,len(stre))):
// if(lamda < stre[k]):
// Q_lamda = k
//for k in reversed(range(0,len(cohe))):
// if(u < cohe[k]):
// Q_u = k
int Q_lamda = Qstrength-1;
int Q_u = Qcoherence -1;
for(int k=Qstrength-1; k>=0; k--){
Q_lamda = lamda < stre[k] ? k : Q_lamda;
}
for(int k=Qcoherence-1; k>=0; k--){
Q_u = u < cohe[k] ? k : Q_u;
}
int dim0 = Qangle*Qstrength * Qcoherence;
int index = Q_theta * Qstrength * Qcoherence + Q_lamda * Qcoherence + Q_u;
atomicAdd(mark + pos*dim0+index, 1);
int patchL_shape_2 = (2*h_hsize+1)*(2*h_hsize+1);
int V_offset = pos*dim0*patchL_shape_2+index*patchL_shape_2;
//int Q_offset = pos*dim0*patchL_shape_2*patchL_shape_2 + index*patchL_shape_2*patchL_shape_2;
int Q_offset = V_offset*patchL_shape_2;
float *Q_ptr = Q+Q_offset;
float *V_ptr = V+V_offset;
int patchL_dim0 = 0;
int patchL_dim1 = 0;
for(int i=y-h_hsize;i<y+h_hsize+1;i++)
{
for(int j=x-h_hsize; j< x+h_hsize+1;j++)
{
float val = quad_raw[i*width+j];
for(int k= y-h_hsize;k<y+h_hsize+1;k++)
{
for(int m= x-h_hsize;m<x+h_hsize+1;m++)
{
float ret=val*quad_raw[k*width+m];
atomicAdd(Q_ptr + patchL_dim1, ret);
patchL_dim1+=1;
}
}
float b1 = val*raw[y*width+x];
atomicAdd(V_ptr+patchL_dim0, b1);
patchL_dim0 +=1;
}
}
}; | .text
.file "kernel.hip"
.globl _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii # -- Begin function _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii,@function
_Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii: # @_Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, .Lfunc_end0-_Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii,@object # @_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.p2align 3, 0x0
_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii:
.quad _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.size _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011707e_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii
.type _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii, @function
_Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii:
.LFB2081:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 352(%rsp), %rax
movq %rax, 32(%rsp)
movq 360(%rsp), %rax
movq %rax, 24(%rsp)
movq 368(%rsp), %rax
movq %rax, 16(%rsp)
movq 376(%rsp), %rax
movq %rax, 8(%rsp)
movq 384(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movq %rsp, %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 328
pushq 88(%rsp)
.cfi_def_cfa_offset 336
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii, .-_Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii
.globl _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.type _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, @function
_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
pushq 104(%rsp)
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
call _Z58__device_stub__Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iiiPfS_S_S_iiiiiiS_S_S_S_S_iii
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, .-_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii # -- Begin function _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii,@function
_Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii: # @_Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, .Lfunc_end0-_Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii,@object # @_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.p2align 3, 0x0
_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii:
.quad _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.size _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13remosaic_cudaPfS_S_S_iiiiiiS_S_S_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" {
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)
{
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = yIndex * width + xIndex;
if (xIndex < width && yIndex < height){
float3 rgb = d_idata[idx];
d_odata[idx].x = powf(rgb.x, gamma);
d_odata[idx].y = powf(rgb.y, gamma);
d_odata[idx].z = powf(rgb.z, gamma);
}
}
} | code for sm_80
Function : gamma_transform_2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff037435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R4, R5, c[0x0][0x170], R4 ; /* 0x00005c0005047a24 */
/* 0x000fe200078e0204 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R8, R4, R3, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fca00078e0203 */
/*00e0*/ LDG.E R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R0, [R8.64+0x4] ; /* 0x0000040408007981 */
/* 0x000168000c1e1900 */
/*0100*/ LDG.E R2, [R8.64+0x8] ; /* 0x0000080408027981 */
/* 0x000162000c1e1900 */
/*0110*/ BSSY B0, 0x700 ; /* 0x000005e000007945 */
/* 0x000fe20003800000 */
/*0120*/ FMUL R5, |R6|.reuse, 16777216 ; /* 0x4b80000006057820 */
/* 0x044fe20000400200 */
/*0130*/ FSETP.GEU.AND P0, PT, |R6|, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fc80003f0e200 */
/*0140*/ FSEL R5, R5, |R6|, !P0 ; /* 0x4000000605057208 */
/* 0x000fc80004000000 */
/*0150*/ IADD3 R7, R5, -0x3f3504f3, RZ ; /* 0xc0cafb0d05077810 */
/* 0x000fc80007ffe0ff */
/*0160*/ LOP3.LUT R10, R7, 0xff800000, RZ, 0xc0, !PT ; /* 0xff800000070a7812 */
/* 0x000fc800078ec0ff */
/*0170*/ IADD3 R5, R5, -R10, RZ ; /* 0x8000000a05057210 */
/* 0x000fe40007ffe0ff */
/*0180*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000fe60000201400 */
/*0190*/ FADD R12, R5.reuse, 1 ; /* 0x3f800000050c7421 */
/* 0x040fe40000000000 */
/*01a0*/ FADD R11, R5, -1 ; /* 0xbf800000050b7421 */
/* 0x000fe20000000000 */
/*01b0*/ FSEL R5, RZ, -24, P0 ; /* 0xc1c00000ff057808 */
/* 0x000fc60000000000 */
/*01c0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x000e220000001000 */
/*01d0*/ FADD R7, R11, R11 ; /* 0x0000000b0b077221 */
/* 0x000fc80000000000 */
/*01e0*/ FMUL R8, R12, R7 ; /* 0x000000070c087220 */
/* 0x001fe40000400000 */
/*01f0*/ FFMA R7, R10, 1.1920928955078125e-07, R5 ; /* 0x340000000a077823 */
/* 0x000fe20000000005 */
/*0200*/ HFMA2.MMA R5, -RZ, RZ, 0.771484375, 0.21533203125 ; /* 0x3a2c32e4ff057435 */
/* 0x000fe200000001ff */
/*0210*/ FADD R9, R11, -R8 ; /* 0x800000080b097221 */
/* 0x000fe40000000000 */
/*0220*/ FMUL R14, R8.reuse, R8 ; /* 0x00000008080e7220 */
/* 0x040fe40000400000 */
/*0230*/ FADD R9, R9, R9 ; /* 0x0000000909097221 */
/* 0x000fe40000000000 */
/*0240*/ FFMA R16, R8, 1.4426950216293334961, R7 ; /* 0x3fb8aa3b08107823 */
/* 0x000fc40000000007 */
/*0250*/ FFMA R9, R11, -R8, R9 ; /* 0x800000080b097223 */
/* 0x000fe40000000009 */
/*0260*/ FFMA R13, R14.reuse, R5, 0.0032181653659790754318 ; /* 0x3b52e7db0e0d7423 */
/* 0x040fe40000000005 */
/*0270*/ FADD R7, R7, -R16 ; /* 0x8000001007077221 */
/* 0x000fe40000000000 */
/*0280*/ FFMA R13, R14, R13, 0.018033718690276145935 ; /* 0x3c93bb730e0d7423 */
/* 0x000fe4000000000d */
/*0290*/ FMUL R9, R12, R9 ; /* 0x000000090c097220 */
/* 0x000fe40000400000 */
/*02a0*/ FFMA R10, R8, 1.4426950216293334961, R7 ; /* 0x3fb8aa3b080a7823 */
/* 0x000fc40000000007 */
/*02b0*/ FFMA R13, R14.reuse, R13, 0.12022458761930465698 ; /* 0x3df6384f0e0d7423 */
/* 0x040fe4000000000d */
/*02c0*/ FFMA R7, R9, 1.4426950216293334961, R10 ; /* 0x3fb8aa3b09077823 */
/* 0x000fe4000000000a */
/*02d0*/ FMUL R13, R14, R13 ; /* 0x0000000d0e0d7220 */
/* 0x000fe40000400000 */
/*02e0*/ FFMA R10, R8, 1.9251366722983220825e-08, R7 ; /* 0x32a55e34080a7823 */
/* 0x000fe40000000007 */
/*02f0*/ FMUL R7, R13, 3 ; /* 0x404000000d077820 */
/* 0x000fc80000400000 */
/*0300*/ FFMA R7, R9, R7, R10 ; /* 0x0000000709077223 */
/* 0x000fc8000000000a */
/*0310*/ FFMA R7, R8, R13, R7 ; /* 0x0000000d08077223 */
/* 0x000fc80000000007 */
/*0320*/ FADD R8, R16, R7 ; /* 0x0000000710087221 */
/* 0x000fc80000000000 */
/*0330*/ FMUL R9, R8, c[0x0][0x178] ; /* 0x00005e0008097a20 */
/* 0x000fe40000400000 */
/*0340*/ FADD R16, -R16, R8 ; /* 0x0000000810107221 */
/* 0x000fe40000000100 */
/*0350*/ FRND R12, R9 ; /* 0x00000009000c7307 */
/* 0x000e220000201000 */
/*0360*/ FSETP.GT.AND P1, PT, |R9|, 152, PT ; /* 0x431800000900780b */
/* 0x000fe20003f24200 */
/*0370*/ FADD R16, R7, -R16 ; /* 0x8000001007107221 */
/* 0x000fe20000000000 */
/*0380*/ FSETP.GEU.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe20003f4e000 */
/*0390*/ FFMA R7, R8, c[0x0][0x178], -R9 ; /* 0x00005e0008077a23 */
/* 0x000fe20000000809 */
/*03a0*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fc60000000f00 */
/*03b0*/ FFMA R16, R16, c[0x0][0x178], R7 ; /* 0x00005e0010107a23 */
/* 0x000fe20000000007 */
/*03c0*/ MOV R7, 0x391fcb8e ; /* 0x391fcb8e00077802 */
/* 0x000fe20000000f00 */
/*03d0*/ FMUL R10, R8, 0.5 ; /* 0x3f000000080a7820 */
/* 0x000fe20000400000 */
/*03e0*/ F2I.NTZ R13, R9 ; /* 0x00000009000d7305 */
/* 0x000e620000203100 */
/*03f0*/ FADD R11, R9, -R12 ; /* 0x8000000c090b7221 */
/* 0x001fe20000000000 */
/*0400*/ FSETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fcc0003f04000 */
/*0410*/ FRND.TRUNC R10, R10 ; /* 0x0000000a000a7307 */
/* 0x000e22000020d000 */
/*0420*/ FADD R16, R16, R11 ; /* 0x0000000b10107221 */
/* 0x000fe20000000000 */
/*0430*/ SEL R12, RZ, 0x83000000, P0 ; /* 0x83000000ff0c7807 */
/* 0x000fe40000000000 */
/*0440*/ FSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3f8000000600780b */
/* 0x000fe20003f0d000 */
/*0450*/ FFMA R11, R16, R7, 0.0013391353422775864601 ; /* 0x3aaf85ed100b7423 */
/* 0x000fe20000000007 */
/*0460*/ IADD3 R14, R12, 0x7f000000, RZ ; /* 0x7f0000000c0e7810 */
/* 0x000fe40007ffe0ff */
/*0470*/ FSETP.EQ.OR P0, PT, RZ, c[0x0][0x178], !P0 ; /* 0x00005e00ff007a0b */
/* 0x000fe20004702400 */
/*0480*/ FFMA R11, R16, R11, 0.0096188392490148544312 ; /* 0x3c1d9856100b7423 */
/* 0x000fe2000000000b */
/*0490*/ LEA R12, R13, -R12, 0x17 ; /* 0x8000000c0d0c7211 */
/* 0x002fc600078eb8ff */
/*04a0*/ FFMA R11, R16, R11, 0.055503588169813156128 ; /* 0x3d6357bb100b7423 */
/* 0x000fe4000000000b */
/*04b0*/ FADD R9, R10, R10 ; /* 0x0000000a0a097221 */
/* 0x001fe20000000000 */
/*04c0*/ HFMA2.MMA R10, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff0a7435 */
/* 0x000fe200000001ff */
/*04d0*/ FFMA R11, R16.reuse, R11, 0.24022644758224487305 ; /* 0x3e75fdec100b7423 */
/* 0x040fe4000000000b */
/*04e0*/ FADD R9, -R9, c[0x0][0x178] ; /* 0x00005e0009097621 */
/* 0x000fe40000000100 */
/*04f0*/ FFMA R11, R16, R11, 0.69314718246459960938 ; /* 0x3f317218100b7423 */
/* 0x000fc8000000000b */
/*0500*/ FFMA R11, R16, R11, 1 ; /* 0x3f800000100b7423 */
/* 0x000fc8000000000b */
/*0510*/ FMUL R11, R11, R14 ; /* 0x0000000e0b0b7220 */
/* 0x000fc80000400000 */
/*0520*/ FMUL R12, R11, R12 ; /* 0x0000000c0b0c7220 */
/* 0x000fe20000400000 */
/*0530*/ SHF.R.S32.HI R11, RZ, 0x1f, R4 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011404 */
/*0540*/ @P1 FSEL R12, RZ, +INF , !P2 ; /* 0x7f800000ff0c1808 */
/* 0x000fe20005000000 */
/*0550*/ @P0 BRA 0x6f0 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0560*/ FSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fc80003f0c200 */
/*0570*/ FSETP.GTU.OR P0, PT, |R6|, +INF , P0 ; /* 0x7f8000000600780b */
/* 0x000fda000070c600 */
/*0580*/ @P0 BRA 0x6e0 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0590*/ FSETP.NEU.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f0d200 */
/*05a0*/ FSETP.EQ.OR P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720b */
/* 0x000fc80004702400 */
/*05b0*/ FSETP.LEU.OR P1, PT, RZ, c[0x0][0x178], !P0 ; /* 0x00005e00ff007a0b */
/* 0x000fe4000472b400 */
/*05c0*/ FSETP.NEU.AND P2, PT, |R9|, 1, P0 ; /* 0x3f8000000900780b */
/* 0x000fce000074d200 */
/*05d0*/ @P0 FADD R10, R6, R6 ; /* 0x00000006060a0221 */
/* 0x000fca0000000000 */
/*05e0*/ @!P1 LOP3.LUT R10, R10, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f8000000a0a9812 */
/* 0x000fc800078e3cff */
/*05f0*/ @P2 LOP3.LUT R10, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0a0a2812 */
/* 0x000fe200078ec0ff */
/*0600*/ @P0 BRA 0x6f0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0610*/ FSETP.NEU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f0d200 */
/*0620*/ FSETP.EQ.AND P1, PT, R6, -1, PT ; /* 0xbf8000000600780b */
/* 0x000fe40003f22000 */
/*0630*/ MOV R10, 0x3f800000 ; /* 0x3f800000000a7802 */
/* 0x000fd60000000f00 */
/*0640*/ @!P0 BRA P1, 0x6f0 ; /* 0x000000a000008947 */
/* 0x000fea0000800000 */
/*0650*/ FSETP.GEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fe40003f0e000 */
/*0660*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fd60000000f00 */
/*0670*/ @P0 BRA 0x6f0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0680*/ FRND.FLOOR R6, c[0x0][0x178] ; /* 0x00005e0000067b07 */
/* 0x000e220000205000 */
/*0690*/ FSETP.NEU.AND P1, PT, |R9|, 1, PT ; /* 0x3f8000000900780b */
/* 0x000fc80003f2d200 */
/*06a0*/ FSEL R10, -R12, R12, !P1 ; /* 0x0000000c0c0a7208 */
/* 0x000fe40004800100 */
/*06b0*/ FSETP.NEU.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0b */
/* 0x001fc80003f0d000 */
/*06c0*/ FSEL R10, R10, +QNAN , !P0 ; /* 0x7fffffff0a0a7808 */
/* 0x000fe20004000000 */
/*06d0*/ BRA 0x6f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06e0*/ FADD R10, R6, c[0x0][0x178] ; /* 0x00005e00060a7621 */
/* 0x000fe40000000000 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ FMUL R13, |R0|.reuse, 16777216 ; /* 0x4b800000000d7820 */
/* 0x060fe20000400200 */
/*0710*/ FSETP.GEU.AND P0, PT, |R0|, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x000fe20003f0e200 */
/*0720*/ IMAD R11, R11, 0xc, RZ ; /* 0x0000000c0b0b7824 */
/* 0x000fe200078e02ff */
/*0730*/ BSSY B0, 0xcb0 ; /* 0x0000057000007945 */
/* 0x000fe40003800000 */
/*0740*/ FSEL R13, R13, |R0|, !P0 ; /* 0x400000000d0d7208 */
/* 0x000fc80004000000 */
/*0750*/ IADD3 R6, R13, -0x3f3504f3, RZ ; /* 0xc0cafb0d0d067810 */
/* 0x000fc80007ffe0ff */
/*0760*/ LOP3.LUT R14, R6, 0xff800000, RZ, 0xc0, !PT ; /* 0xff800000060e7812 */
/* 0x000fe400078ec0ff */
/*0770*/ FSEL R6, RZ, -24, P0 ; /* 0xc1c00000ff067808 */
/* 0x000fe40000000000 */
/*0780*/ IADD3 R13, R13, -R14, RZ ; /* 0x8000000e0d0d7210 */
/* 0x000fe20007ffe0ff */
/*0790*/ I2F R15, R14 ; /* 0x0000000e000f7306 */
/* 0x000e280000201400 */
/*07a0*/ FADD R16, R13.reuse, 1 ; /* 0x3f8000000d107421 */
/* 0x040fe40000000000 */
/*07b0*/ FADD R13, R13, -1 ; /* 0xbf8000000d0d7421 */
/* 0x000fc80000000000 */
/*07c0*/ MUFU.RCP R16, R16 ; /* 0x0000001000107308 */
/* 0x000e620000001000 */
/*07d0*/ FADD R17, R13, R13 ; /* 0x0000000d0d117221 */
/* 0x000fe40000000000 */
/*07e0*/ FFMA R15, R15, 1.1920928955078125e-07, R6 ; /* 0x340000000f0f7823 */
/* 0x001fe40000000006 */
/*07f0*/ FMUL R12, R16, R17 ; /* 0x00000011100c7220 */
/* 0x002fc80000400000 */
/*0800*/ FADD R17, R13, -R12 ; /* 0x8000000c0d117221 */
/* 0x000fe40000000000 */
/*0810*/ FMUL R18, R12.reuse, R12 ; /* 0x0000000c0c127220 */
/* 0x040fe40000400000 */
/*0820*/ FFMA R6, R12, 1.4426950216293334961, R15 ; /* 0x3fb8aa3b0c067823 */
/* 0x000fe4000000000f */
/*0830*/ FADD R17, R17, R17 ; /* 0x0000001111117221 */
/* 0x000fe40000000000 */
/*0840*/ FFMA R19, R18, R5, 0.0032181653659790754318 ; /* 0x3b52e7db12137423 */
/* 0x000fe40000000005 */
/*0850*/ FADD R15, R15, -R6 ; /* 0x800000060f0f7221 */
/* 0x000fc40000000000 */
/*0860*/ FFMA R17, R13, -R12, R17 ; /* 0x8000000c0d117223 */
/* 0x000fe40000000011 */
/*0870*/ FFMA R19, R18, R19, 0.018033718690276145935 ; /* 0x3c93bb7312137423 */
/* 0x000fe40000000013 */
/*0880*/ FFMA R14, R12, 1.4426950216293334961, R15 ; /* 0x3fb8aa3b0c0e7823 */
/* 0x000fe4000000000f */
/*0890*/ FMUL R17, R16, R17 ; /* 0x0000001110117220 */
/* 0x000fe40000400000 */
/*08a0*/ FFMA R19, R18, R19, 0.12022458761930465698 ; /* 0x3df6384f12137423 */
/* 0x000fe40000000013 */
/*08b0*/ FFMA R13, R17, 1.4426950216293334961, R14 ; /* 0x3fb8aa3b110d7823 */
/* 0x000fc4000000000e */
/*08c0*/ FMUL R19, R18, R19 ; /* 0x0000001312137220 */
/* 0x000fe40000400000 */
/*08d0*/ FFMA R14, R12, 1.9251366722983220825e-08, R13 ; /* 0x32a55e340c0e7823 */
/* 0x000fe4000000000d */
/*08e0*/ FMUL R13, R19, 3 ; /* 0x40400000130d7820 */
/* 0x000fc80000400000 */
/*08f0*/ FFMA R13, R17, R13, R14 ; /* 0x0000000d110d7223 */
/* 0x000fc8000000000e */
/*0900*/ FFMA R13, R12, R19, R13 ; /* 0x000000130c0d7223 */
/* 0x000fc8000000000d */
/*0910*/ FADD R17, R6, R13 ; /* 0x0000000d06117221 */
/* 0x000fc80000000000 */
/*0920*/ FMUL R14, R17.reuse, c[0x0][0x178] ; /* 0x00005e00110e7a20 */
/* 0x040fe40000400000 */
/*0930*/ FADD R6, -R6, R17 ; /* 0x0000001106067221 */
/* 0x000fe40000000100 */
/*0940*/ FRND R15, R14 ; /* 0x0000000e000f7307 */
/* 0x000e220000201000 */
/*0950*/ FFMA R17, R17, c[0x0][0x178], -R14 ; /* 0x00005e0011117a23 */
/* 0x000fe2000000080e */
/*0960*/ FSETP.GT.AND P1, PT, |R14|.reuse, 152, PT ; /* 0x431800000e00780b */
/* 0x040fe20003f24200 */
/*0970*/ FADD R6, R13, -R6 ; /* 0x800000060d067221 */
/* 0x000fe20000000000 */
/*0980*/ FSETP.GEU.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720b */
/* 0x000fc60003f4e000 */
/*0990*/ FFMA R6, R6, c[0x0][0x178], R17 ; /* 0x00005e0006067a23 */
/* 0x000fe40000000011 */
/*09a0*/ FADD R13, R14, -R15 ; /* 0x8000000f0e0d7221 */
/* 0x001fe20000000000 */
/*09b0*/ FSETP.GT.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x000fc60003f04000 */
/*09c0*/ FADD R6, R6, R13 ; /* 0x0000000d06067221 */
/* 0x000fe40000000000 */
/*09d0*/ IMAD.WIDE.U32 R12, R4, R3, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e0003 */
/*09e0*/ SEL R4, RZ, 0x83000000, P0 ; /* 0x83000000ff047807 */
/* 0x000fe20000000000 */
/*09f0*/ F2I.NTZ R3, R14 ; /* 0x0000000e00037305 */
/* 0x000e220000203100 */
/*0a00*/ FSETP.NEU.AND P0, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fe20003f0d000 */
/*0a10*/ FFMA R17, R6.reuse, R7, 0.0013391353422775864601 ; /* 0x3aaf85ed06117423 */
/* 0x040fe20000000007 */
/*0a20*/ IADD3 R13, R13, R11, RZ ; /* 0x0000000b0d0d7210 */
/* 0x000fe40007ffe0ff */
/*0a30*/ FSETP.EQ.OR P0, PT, RZ, c[0x0][0x178], !P0 ; /* 0x00005e00ff007a0b */
/* 0x000fe20004702400 */
/*0a40*/ FFMA R17, R6, R17, 0.0096188392490148544312 ; /* 0x3c1d985606117423 */
/* 0x000fc40000000011 */
/*0a50*/ STG.E [R12.64], R10 ; /* 0x0000000a0c007986 */
/* 0x0003e4000c101904 */
/*0a60*/ FFMA R17, R6, R17, 0.055503588169813156128 ; /* 0x3d6357bb06117423 */
/* 0x000fc80000000011 */
/*0a70*/ FFMA R17, R6, R17, 0.24022644758224487305 ; /* 0x3e75fdec06117423 */
/* 0x000fe20000000011 */
/*0a80*/ LEA R3, R3, -R4, 0x17 ; /* 0x8000000403037211 */
/* 0x001fc600078eb8ff */
/*0a90*/ FFMA R17, R6, R17, 0.69314718246459960938 ; /* 0x3f31721806117423 */
/* 0x000fc80000000011 */
/*0aa0*/ FFMA R17, R6, R17, 1 ; /* 0x3f80000006117423 */
/* 0x000fe20000000011 */
/*0ab0*/ IADD3 R6, R4, 0x7f000000, RZ ; /* 0x7f00000004067810 */
/* 0x000fca0007ffe0ff */
/*0ac0*/ FMUL R6, R17, R6 ; /* 0x0000000611067220 */
/* 0x000fc80000400000 */
/*0ad0*/ FMUL R6, R6, R3 ; /* 0x0000000306067220 */
/* 0x000fe20000400000 */
/*0ae0*/ HFMA2.MMA R3, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff037435 */
/* 0x000fe200000001ff */
/*0af0*/ @P1 FSEL R6, RZ, +INF , !P2 ; /* 0x7f800000ff061808 */
/* 0x000fe20005000000 */
/*0b00*/ @P0 BRA 0xca0 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0b10*/ FSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x002fc80003f0c200 */
/*0b20*/ FSETP.GTU.OR P0, PT, |R0|, +INF , P0 ; /* 0x7f8000000000780b */
/* 0x000fda000070c600 */
/*0b30*/ @P0 BRA 0xc90 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0b40*/ FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f0d200 */
/*0b50*/ FSETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720b */
/* 0x000fc80004702400 */
/*0b60*/ FSETP.LEU.OR P1, PT, RZ, c[0x0][0x178], !P0 ; /* 0x00005e00ff007a0b */
/* 0x000fe4000472b400 */
/*0b70*/ FSETP.NEU.AND P2, PT, |R9|, 1, P0 ; /* 0x3f8000000900780b */
/* 0x000fce000074d200 */
/*0b80*/ @P0 FADD R3, R0, R0 ; /* 0x0000000000030221 */
/* 0x000fca0000000000 */
/*0b90*/ @!P1 LOP3.LUT R3, R3, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000003039812 */
/* 0x000fc800078e3cff */
/*0ba0*/ @P2 LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03032812 */
/* 0x000fe200078ec0ff */
/*0bb0*/ @P0 BRA 0xca0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0bc0*/ FSETP.NEU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f0d200 */
/*0bd0*/ FSETP.EQ.AND P1, PT, R0, -1, PT ; /* 0xbf8000000000780b */
/* 0x000fe40003f22000 */
/*0be0*/ MOV R3, 0x3f800000 ; /* 0x3f80000000037802 */
/* 0x000fd60000000f00 */
/*0bf0*/ @!P0 BRA P1, 0xca0 ; /* 0x000000a000008947 */
/* 0x000fea0000800000 */
/*0c00*/ FSETP.GEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fe40003f0e000 */
/*0c10*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fd60000000f00 */
/*0c20*/ @P0 BRA 0xca0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0c30*/ FRND.FLOOR R0, c[0x0][0x178] ; /* 0x00005e0000007b07 */
/* 0x000e220000205000 */
/*0c40*/ FSETP.NEU.AND P0, PT, |R9|, 1, PT ; /* 0x3f8000000900780b */
/* 0x000fc80003f0d200 */
/*0c50*/ FSEL R3, -R6, R6, !P0 ; /* 0x0000000606037208 */
/* 0x000fe40004000100 */
/*0c60*/ FSETP.NEU.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x001fc80003f2d000 */
/*0c70*/ FSEL R3, R3, +QNAN , !P1 ; /* 0x7fffffff03037808 */
/* 0x000fe20004800000 */
/*0c80*/ BRA 0xca0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c90*/ FADD R3, R0, c[0x0][0x178] ; /* 0x00005e0000037621 */
/* 0x000fe40000000000 */
/*0ca0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0cb0*/ FMUL R11, |R2|.reuse, 16777216 ; /* 0x4b800000020b7820 */
/* 0x040fe20000400200 */
/*0cc0*/ FSETP.GEU.AND P0, PT, |R2|, 1.175494350822287508e-38, PT ; /* 0x008000000200780b */
/* 0x000fe20003f0e200 */
/*0cd0*/ STG.E [R12.64+0x4], R3 ; /* 0x000004030c007986 */
/* 0x0001e2000c101904 */
/*0ce0*/ BSSY B0, 0x1230 ; /* 0x0000054000007945 */
/* 0x000fe40003800000 */
/*0cf0*/ FSEL R11, R11, |R2|, !P0 ; /* 0x400000020b0b7208 */
/* 0x000fe40004000000 */
/*0d00*/ FSEL R4, RZ, -24, P0 ; /* 0xc1c00000ff047808 */
/* 0x000fe40000000000 */
/*0d10*/ IADD3 R0, R11, -0x3f3504f3, RZ ; /* 0xc0cafb0d0b007810 */
/* 0x000fc80007ffe0ff */
/*0d20*/ LOP3.LUT R6, R0, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000000067812 */
/* 0x000fc800078ec0ff */
/*0d30*/ IADD3 R11, R11, -R6, RZ ; /* 0x800000060b0b7210 */
/* 0x000fe20007ffe0ff */
/*0d40*/ I2F R15, R6 ; /* 0x00000006000f7306 */
/* 0x000e680000201400 */
/*0d50*/ FADD R10, R11.reuse, 1 ; /* 0x3f8000000b0a7421 */
/* 0x040fe40000000000 */
/*0d60*/ FADD R11, R11, -1 ; /* 0xbf8000000b0b7421 */
/* 0x000fc80000000000 */
/*0d70*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x000ea20000001000 */
/*0d80*/ FADD R17, R11, R11 ; /* 0x0000000b0b117221 */
/* 0x000fe40000000000 */
/*0d90*/ FFMA R15, R15, 1.1920928955078125e-07, R4 ; /* 0x340000000f0f7823 */
/* 0x002fe40000000004 */
/*0da0*/ FMUL R0, R10, R17 ; /* 0x000000110a007220 */
/* 0x004fc80000400000 */
/*0db0*/ FADD R16, R11, -R0 ; /* 0x800000000b107221 */
/* 0x000fe40000000000 */
/*0dc0*/ FMUL R14, R0.reuse, R0 ; /* 0x00000000000e7220 */
/* 0x040fe40000400000 */
/*0dd0*/ FFMA R4, R0, 1.4426950216293334961, R15 ; /* 0x3fb8aa3b00047823 */
/* 0x000fe4000000000f */
/*0de0*/ FADD R16, R16, R16 ; /* 0x0000001010107221 */
/* 0x000fe40000000000 */
/*0df0*/ FFMA R5, R14, R5, 0.0032181653659790754318 ; /* 0x3b52e7db0e057423 */
/* 0x000fe40000000005 */
/*0e00*/ FADD R15, R15, -R4 ; /* 0x800000040f0f7221 */
/* 0x000fc40000000000 */
/*0e10*/ FFMA R11, R11, -R0, R16 ; /* 0x800000000b0b7223 */
/* 0x000fe40000000010 */
/*0e20*/ FFMA R5, R14, R5, 0.018033718690276145935 ; /* 0x3c93bb730e057423 */
/* 0x000fe40000000005 */
/*0e30*/ FFMA R6, R0, 1.4426950216293334961, R15 ; /* 0x3fb8aa3b00067823 */
/* 0x000fe4000000000f */
/*0e40*/ FMUL R11, R10, R11 ; /* 0x0000000b0a0b7220 */
/* 0x000fe40000400000 */
/*0e50*/ FFMA R5, R14, R5, 0.12022458761930465698 ; /* 0x3df6384f0e057423 */
/* 0x000fe40000000005 */
/*0e60*/ FFMA R15, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b0f7823 */
/* 0x000fc40000000006 */
/*0e70*/ FMUL R5, R14, R5 ; /* 0x000000050e057220 */
/* 0x000fe40000400000 */
/*0e80*/ FFMA R6, R0, 1.9251366722983220825e-08, R15 ; /* 0x32a55e3400067823 */
/* 0x000fe4000000000f */
/*0e90*/ FMUL R10, R5, 3 ; /* 0x40400000050a7820 */
/* 0x000fc80000400000 */
/*0ea0*/ FFMA R6, R11, R10, R6 ; /* 0x0000000a0b067223 */
/* 0x000fc80000000006 */
/*0eb0*/ FFMA R5, R0, R5, R6 ; /* 0x0000000500057223 */
/* 0x000fc80000000006 */
/*0ec0*/ FADD R11, R4, R5 ; /* 0x00000005040b7221 */
/* 0x000fc80000000000 */
/*0ed0*/ FMUL R0, R11.reuse, c[0x0][0x178] ; /* 0x00005e000b007a20 */
/* 0x040fe40000400000 */
/*0ee0*/ FADD R4, -R4, R11 ; /* 0x0000000b04047221 */
/* 0x000fe40000000100 */
/*0ef0*/ FRND R15, R0 ; /* 0x00000000000f7307 */
/* 0x000e620000201000 */
/*0f00*/ FFMA R11, R11, c[0x0][0x178], -R0 ; /* 0x00005e000b0b7a23 */
/* 0x000fe20000000800 */
/*0f10*/ FSETP.GT.AND P1, PT, |R0|.reuse, 152, PT ; /* 0x431800000000780b */
/* 0x040fe20003f24200 */
/*0f20*/ FADD R4, R5, -R4 ; /* 0x8000000405047221 */
/* 0x000fe20000000000 */
/*0f30*/ FSETP.GEU.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fc60003f4e000 */
/*0f40*/ FFMA R4, R4, c[0x0][0x178], R11 ; /* 0x00005e0004047a23 */
/* 0x000fe4000000000b */
/*0f50*/ FADD R5, R0, -R15 ; /* 0x8000000f00057221 */
/* 0x002fe20000000000 */
/*0f60*/ FSETP.GT.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x000fc60003f04000 */
/*0f70*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fe20000000000 */
/*0f80*/ SEL R6, RZ, 0x83000000, P0 ; /* 0x83000000ff067807 */
/* 0x000fe20000000000 */
/*0f90*/ F2I.NTZ R5, R0 ; /* 0x0000000000057305 */
/* 0x000e620000203100 */
/*0fa0*/ FSETP.NEU.AND P0, PT, R2, 1, PT ; /* 0x3f8000000200780b */
/* 0x000fe20003f0d000 */
/*0fb0*/ FFMA R7, R4, R7, 0.0013391353422775864601 ; /* 0x3aaf85ed04077423 */
/* 0x000fc60000000007 */
/*0fc0*/ FSETP.EQ.OR P0, PT, RZ, c[0x0][0x178], !P0 ; /* 0x00005e00ff007a0b */
/* 0x000fe20004702400 */
/*0fd0*/ FFMA R7, R4, R7, 0.0096188392490148544312 ; /* 0x3c1d985604077423 */
/* 0x000fc80000000007 */
/*0fe0*/ FFMA R7, R4, R7, 0.055503588169813156128 ; /* 0x3d6357bb04077423 */
/* 0x000fc80000000007 */
/*0ff0*/ FFMA R7, R4, R7, 0.24022644758224487305 ; /* 0x3e75fdec04077423 */
/* 0x000fe20000000007 */
/*1000*/ LEA R5, R5, -R6, 0x17 ; /* 0x8000000605057211 */
/* 0x002fc600078eb8ff */
/*1010*/ FFMA R7, R4, R7, 0.69314718246459960938 ; /* 0x3f31721804077423 */
/* 0x000fc80000000007 */
/*1020*/ FFMA R7, R4, R7, 1 ; /* 0x3f80000004077423 */
/* 0x000fe20000000007 */
/*1030*/ IADD3 R4, R6, 0x7f000000, RZ ; /* 0x7f00000006047810 */
/* 0x000fca0007ffe0ff */
/*1040*/ FMUL R4, R7, R4 ; /* 0x0000000407047220 */
/* 0x000fc80000400000 */
/*1050*/ FMUL R4, R4, R5 ; /* 0x0000000504047220 */
/* 0x000fe20000400000 */
/*1060*/ HFMA2.MMA R5, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff057435 */
/* 0x000fe200000001ff */
/*1070*/ @P1 FSEL R4, RZ, +INF , !P2 ; /* 0x7f800000ff041808 */
/* 0x000fe20005000000 */
/*1080*/ @P0 BRA 0x1220 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*1090*/ FSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x001fc80003f0c200 */
/*10a0*/ FSETP.GTU.OR P0, PT, |R2|, +INF , P0 ; /* 0x7f8000000200780b */
/* 0x000fda000070c600 */
/*10b0*/ @P0 BRA 0x1210 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*10c0*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f0d200 */
/*10d0*/ FSETP.EQ.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720b */
/* 0x000fc80004702400 */
/*10e0*/ FSETP.LEU.OR P1, PT, RZ, c[0x0][0x178], !P0 ; /* 0x00005e00ff007a0b */
/* 0x000fe4000472b400 */
/*10f0*/ FSETP.NEU.AND P2, PT, |R9|, 1, P0 ; /* 0x3f8000000900780b */
/* 0x000fce000074d200 */
/*1100*/ @P0 FADD R0, R2, R2 ; /* 0x0000000202000221 */
/* 0x000fca0000000000 */
/*1110*/ @!P1 LOP3.LUT R0, R0, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000000009812 */
/* 0x000fc800078e3cff */
/*1120*/ @P2 LOP3.LUT R0, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00002812 */
/* 0x000fc800078ec0ff */
/*1130*/ @P0 MOV R5, R0 ; /* 0x0000000000050202 */
/* 0x000fe20000000f00 */
/*1140*/ @P0 BRA 0x1220 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*1150*/ FSETP.NEU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f0d200 */
/*1160*/ FSETP.EQ.AND P1, PT, R2, -1, PT ; /* 0xbf8000000200780b */
/* 0x000fda0003f22000 */
/*1170*/ @!P0 BRA P1, 0x1220 ; /* 0x000000a000008947 */
/* 0x000fea0000800000 */
/*1180*/ FSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fe40003f0e000 */
/*1190*/ MOV R5, R4 ; /* 0x0000000400057202 */
/* 0x000fd60000000f00 */
/*11a0*/ @P0 BRA 0x1220 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*11b0*/ FRND.FLOOR R0, c[0x0][0x178] ; /* 0x00005e0000007b07 */
/* 0x000e220000205000 */
/*11c0*/ FSETP.NEU.AND P0, PT, |R9|, 1, PT ; /* 0x3f8000000900780b */
/* 0x000fc80003f0d200 */
/*11d0*/ FSEL R4, -R4, R4, !P0 ; /* 0x0000000404047208 */
/* 0x000fe40004000100 */
/*11e0*/ FSETP.NEU.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0b */
/* 0x001fc80003f2d000 */
/*11f0*/ FSEL R5, R4, +QNAN , !P1 ; /* 0x7fffffff04057808 */
/* 0x000fe20004800000 */
/*1200*/ BRA 0x1220 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1210*/ FADD R5, R2, c[0x0][0x178] ; /* 0x00005e0002057621 */
/* 0x000fe40000000000 */
/*1220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*1230*/ STG.E [R12.64+0x8], R5 ; /* 0x000008050c007986 */
/* 0x000fe2000c101904 */
/*1240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1250*/ BRA 0x1250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" {
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)
{
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = yIndex * width + xIndex;
if (xIndex < width && yIndex < height){
float3 rgb = d_idata[idx];
d_odata[idx].x = powf(rgb.x, gamma);
d_odata[idx].y = powf(rgb.y, gamma);
d_odata[idx].z = powf(rgb.z, gamma);
}
}
} | .file "tmpxft_000475c0_00000000-6_06-gamma-transform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
.type _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif, @function
_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gamma_transform_2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif, .-_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
.globl gamma_transform_2
.type gamma_transform_2, @function
gamma_transform_2:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gamma_transform_2, .-gamma_transform_2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gamma_transform_2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gamma_transform_2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" {
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)
{
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = yIndex * width + xIndex;
if (xIndex < width && yIndex < height){
float3 rgb = d_idata[idx];
d_odata[idx].x = powf(rgb.x, gamma);
d_odata[idx].y = powf(rgb.y, gamma);
d_odata[idx].z = powf(rgb.z, gamma);
}
}
} | #include <hip/hip_runtime.h>
extern "C" {
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)
{
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = yIndex * width + xIndex;
if (xIndex < width && yIndex < height){
float3 rgb = d_idata[idx];
d_odata[idx].x = powf(rgb.x, gamma);
d_odata[idx].y = powf(rgb.y, gamma);
d_odata[idx].z = powf(rgb.z, gamma);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" {
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)
{
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = yIndex * width + xIndex;
if (xIndex < width && yIndex < height){
float3 rgb = d_idata[idx];
d_odata[idx].x = powf(rgb.x, gamma);
d_odata[idx].y = powf(rgb.y, gamma);
d_odata[idx].z = powf(rgb.z, gamma);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gamma_transform_2
.globl gamma_transform_2
.p2align 8
.type gamma_transform_2,@function
gamma_transform_2:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s13, 0x3e76c4e1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[0:1], null, v2, 12, s[4:5]
global_load_b96 v[5:7], v[0:1], off
v_mad_i64_i32 v[0:1], null, v2, 12, s[6:7]
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 1.0, v5
v_cndmask_b32_e64 v2, 1.0, s0, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 1.0, v6
s_delay_alu instid0(VALU_DEP_2)
v_trunc_f32_e32 v8, v2
v_cndmask_b32_e64 v3, 1.0, s0, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 1.0, v7
v_mul_f32_e32 v9, 0.5, v2
v_cmp_gt_f32_e64 s5, 0, v2
v_cmp_eq_f32_e64 s2, v8, v2
v_cmp_neq_f32_e64 s12, v3, |v3|
v_cndmask_b32_e64 v4, 1.0, s0, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v2
v_trunc_f32_e32 v8, v9
v_cmp_gt_f32_e64 s6, 0, v3
v_cmp_neq_f32_e64 s7, v2, |v2|
v_trunc_f32_e32 v12, v4
v_cndmask_b32_e32 v5, 1.0, v5, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v3
v_mul_f32_e32 v13, 0.5, v4
v_cmp_neq_f32_e64 s10, v8, v9
v_cmp_eq_f32_e64 s4, v12, v4
v_trunc_f32_e32 v10, v3
v_cndmask_b32_e32 v6, 1.0, v6, vcc_lo
v_frexp_mant_f32_e64 v14, |v5|
v_cmp_neq_f32_e32 vcc_lo, 0, v4
v_trunc_f32_e32 v12, v13
v_cmp_lt_f32_e64 s11, |v5|, 1.0
v_cmp_lt_f32_e64 s18, |v6|, 1.0
v_cmp_gt_f32_e64 s9, 0x3f2aaaab, v14
v_cndmask_b32_e32 v7, 1.0, v7, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0, v5
v_cmp_eq_f32_e64 s0, 0, v6
v_frexp_mant_f32_e64 v16, |v6|
v_cndmask_b32_e64 v20, 0, 1, s9
v_mul_f32_e32 v11, 0.5, v3
s_xor_b32 s5, s5, vcc_lo
s_xor_b32 s7, s7, s11
v_cndmask_b32_e64 v8, 0x7f800000, 0, s5
s_xor_b32 s5, s12, s18
v_cmp_gt_f32_e64 s11, 0x3f2aaaab, v16
v_cndmask_b32_e64 v23, |v3|, 0, s5
s_xor_b32 s5, s6, s0
v_cmp_neq_f32_e64 s6, v12, v13
v_ldexp_f32 v13, v14, v20
v_cmp_neq_f32_e64 s17, v4, |v4|
v_cmp_gt_f32_e64 s8, 0, v4
v_frexp_exp_i32_f32_e32 v15, v5
v_cmp_eq_f32_e64 s3, v10, v3
v_add_f32_e32 v26, -1.0, v13
v_frexp_mant_f32_e64 v18, |v7|
v_cmp_lt_f32_e64 s19, |v7|, 1.0
v_cmp_eq_f32_e64 s1, 0, v7
v_trunc_f32_e32 v10, v11
v_cndmask_b32_e64 v22, 0, 1, s11
v_cmp_gt_f32_e64 s12, 0x3f2aaaab, v18
v_cndmask_b32_e64 v9, 0x7f800000, 0, s5
s_xor_b32 s5, s17, s19
v_cndmask_b32_e64 v21, |v2|, 0, s7
v_cndmask_b32_e64 v12, |v4|, 0, s5
s_xor_b32 s5, s8, s1
v_cmp_neq_f32_e64 s7, v10, v11
v_cndmask_b32_e64 v24, 0, 1, s12
v_cndmask_b32_e64 v10, 0x7f800000, 0, s5
v_subrev_co_ci_u32_e64 v14, s5, 0, v15, s9
v_ldexp_f32 v15, v16, v22
s_delay_alu instid0(VALU_DEP_4)
v_ldexp_f32 v16, v18, v24
v_add_f32_e32 v18, 1.0, v13
v_frexp_exp_i32_f32_e32 v17, v6
v_frexp_exp_i32_f32_e32 v19, v7
v_add_f32_e32 v20, 1.0, v15
v_add_f32_e32 v22, 1.0, v16
v_rcp_f32_e32 v24, v18
v_dual_add_f32 v28, -1.0, v15 :: v_dual_add_f32 v29, -1.0, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v25, v20
v_rcp_f32_e32 v27, v22
v_add_f32_e32 v31, -1.0, v18
v_add_f32_e32 v33, -1.0, v20
v_subrev_co_ci_u32_e64 v17, s8, 0, v17, s11
v_subrev_co_ci_u32_e64 v19, s8, 0, v19, s12
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
v_mul_f32_e32 v30, v26, v24
v_cvt_f32_i32_e32 v14, v14
v_mul_f32_e32 v32, v28, v25
s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mul_f32_e32 v34, v29, v27
v_add_f32_e32 v36, -1.0, v22
v_mul_f32_e32 v35, v18, v30
v_cvt_f32_i32_e32 v17, v17
v_mul_f32_e32 v37, v20, v32
v_dual_sub_f32 v13, v13, v31 :: v_dual_sub_f32 v16, v16, v36
v_sub_f32_e32 v15, v15, v33
v_fma_f32 v18, v30, v18, -v35
s_delay_alu instid0(VALU_DEP_4)
v_fma_f32 v20, v32, v20, -v37
v_mul_f32_e32 v31, v22, v34
v_cvt_f32_i32_e32 v19, v19
v_cmp_eq_f32_e64 s8, |v5|, 1.0
v_dual_fmac_f32 v18, v30, v13 :: v_dual_mul_f32 v13, 0x3f317218, v14
v_fmac_f32_e32 v20, v32, v15
v_fma_f32 v22, v34, v22, -v31
v_mul_f32_e32 v15, 0x3f317218, v17
v_mul_f32_e32 v33, 0x3f317218, v19
v_fma_f32 v38, v14, 0x3f317218, -v13
v_add_f32_e32 v36, v37, v20
v_fmac_f32_e32 v22, v34, v16
v_add_f32_e32 v16, v35, v18
s_and_b32 s5, s2, s10
v_fmac_f32_e32 v38, 0xb102e308, v14
v_cndmask_b32_e64 v11, 1.0, v5, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_dual_add_f32 v39, v31, v22 :: v_dual_sub_f32 v40, v26, v16
v_sub_f32_e32 v41, v28, v36
v_sub_f32_e32 v35, v16, v35
s_and_b32 s7, s3, s7
v_sub_f32_e32 v42, v29, v39
v_dual_sub_f32 v26, v26, v40 :: v_dual_sub_f32 v31, v39, v31
v_sub_f32_e32 v28, v28, v41
v_dual_sub_f32 v37, v36, v37 :: v_dual_sub_f32 v18, v35, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v29, v29, v42 :: v_dual_sub_f32 v16, v26, v16
v_sub_f32_e32 v26, v28, v36
v_sub_f32_e32 v22, v31, v22
s_and_b32 s6, s4, s6
s_delay_alu instid0(VALU_DEP_3)
v_sub_f32_e32 v28, v29, v39
v_add_f32_e32 v16, v18, v16
v_fma_f32 v18, v17, 0x3f317218, -v15
v_cmp_class_f32_e64 s14, v5, 0x204
v_cmp_class_f32_e64 s15, v6, 0x204
v_add_f32_e32 v22, v22, v28
v_sub_f32_e32 v20, v37, v20
v_fmac_f32_e32 v18, 0xb102e308, v17
v_cmp_class_f32_e64 s16, v7, 0x204
s_or_b32 vcc_lo, vcc_lo, s14
v_add_f32_e32 v17, v42, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v22, v15, v18
v_dual_mul_f32 v17, v27, v17 :: v_dual_add_f32 v20, v20, v26
v_fma_f32 v26, v19, 0x3f317218, -v33
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v15, v22, v15
v_dual_add_f32 v27, v34, v17 :: v_dual_add_f32 v14, v41, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v26, 0xb102e308, v19 :: v_dual_add_f32 v19, v13, v38
v_mul_f32_e32 v14, v25, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v25, v33, v26 :: v_dual_add_f32 v16, v40, v16
v_dual_sub_f32 v13, v19, v13 :: v_dual_mul_f32 v16, v24, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v24, v32, v14
v_add_f32_e32 v20, v30, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v31, v24, v24
v_dual_sub_f32 v15, v18, v15 :: v_dual_sub_f32 v28, v20, v30
v_mul_f32_e32 v29, v20, v20
v_sub_f32_e32 v30, v24, v32
v_dual_sub_f32 v32, v27, v34 :: v_dual_sub_f32 v13, v38, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v16, v16, v28
v_fma_f32 v34, v20, v20, -v29
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_f32_e32 v14, v14, v30
v_mul_f32_e32 v28, v27, v27
v_add_f32_e32 v30, v16, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v35, v27, v27, -v28
v_fmac_f32_e32 v34, v20, v30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v30, v29, v34
v_fmaak_f32 v41, s13, v30, 0x3e91f4c4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmaak_f32 v41, v30, v41, 0x3ecccdef
v_sub_f32_e32 v17, v17, v32
v_fma_f32 v32, v24, v24, -v31
v_add_f32_e32 v37, v17, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v35, v27, v37
v_add_f32_e32 v40, v28, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v45, s13, v40, 0x3e91f4c4
v_fmaak_f32 v45, v40, v45, 0x3ecccdef
v_sub_f32_e32 v28, v40, v28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_mul_f32 v49, v40, v45 :: v_dual_sub_f32 v28, v35, v28
v_dual_mul_f32 v46, v27, v40 :: v_dual_sub_f32 v29, v30, v29
v_dual_mul_f32 v42, v20, v30 :: v_dual_mul_f32 v47, v30, v41
v_fma_f32 v35, v40, v27, -v46
v_add_f32_e32 v36, v14, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v29, v34, v29
v_fma_f32 v34, v30, v20, -v42
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v35, v40, v17
v_fmac_f32_e32 v32, v24, v36
v_ldexp_f32 v36, v20, 1
v_ldexp_f32 v17, v17, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v39, v31, v32
v_fmaak_f32 v43, s13, v39, 0x3e91f4c4
v_sub_f32_e32 v31, v39, v31
v_mul_f32_e32 v44, v24, v39
v_ldexp_f32 v37, v24, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmaak_f32 v43, v39, v43, 0x3ecccdef
v_sub_f32_e32 v31, v32, v31
s_delay_alu instid0(VALU_DEP_4)
v_fma_f32 v32, v39, v24, -v44
v_fmac_f32_e32 v34, v30, v16
v_fma_f32 v30, v30, v41, -v47
v_mul_f32_e32 v48, v39, v43
v_ldexp_f32 v16, v16, 1
v_fmac_f32_e32 v32, v39, v14
v_ldexp_f32 v14, v14, 1
v_fmac_f32_e32 v30, v29, v41
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v32, v31, v24
v_fma_f32 v24, v40, v45, -v49
v_fmac_f32_e32 v24, v28, v45
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v41, v49, v24
v_add_f32_e32 v50, 0x3f2aaaaa, v41
v_sub_f32_e32 v49, v41, v49
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v24, v24, v49 :: v_dual_add_f32 v49, 0xbf2aaaaa, v50
v_dual_fmac_f32 v35, v28, v27 :: v_dual_add_f32 v28, v47, v30
v_dual_add_f32 v24, 0x31739010, v24 :: v_dual_sub_f32 v41, v41, v49
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_sub_f32 v45, v28, v47 :: v_dual_fmac_f32 v34, v29, v20
v_fma_f32 v20, v39, v43, -v48
v_add_f32_e32 v24, v24, v41
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v20, v31, v43 :: v_dual_add_f32 v31, v44, v32
v_add_f32_e32 v43, 0x3f2aaaaa, v28
v_add_f32_e32 v39, v48, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v47, 0x3f2aaaaa, v39 :: v_dual_sub_f32 v48, v39, v48
v_sub_f32_e32 v20, v20, v48
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v48, 0xbf2aaaaa, v47
v_dual_sub_f32 v39, v39, v48 :: v_dual_sub_f32 v30, v30, v45
v_add_f32_e32 v45, 0xbf2aaaaa, v43
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v30, 0x31739010, v30
v_sub_f32_e32 v28, v28, v45
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v28, v30, v28
v_dual_add_f32 v40, v46, v35 :: v_dual_add_f32 v41, v43, v28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v43, v43, v41
v_dual_add_f32 v29, v42, v34 :: v_dual_add_f32 v28, v28, v43
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f32_e32 v45, v29, v41
v_sub_f32_e32 v30, v29, v42
v_sub_f32_e32 v42, v40, v46
v_fma_f32 v43, v29, v41, -v45
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v30, v34, v30 :: v_dual_fmac_f32 v43, v29, v28
v_dual_fmac_f32 v43, v30, v41 :: v_dual_add_f32 v20, 0x31739010, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v20, v20, v39 :: v_dual_sub_f32 v39, v31, v44
v_add_f32_e32 v44, v47, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v28, v32, v39
v_sub_f32_e32 v46, v47, v44
v_mul_f32_e32 v47, v31, v44
v_add_f32_e32 v34, v50, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v20, v20, v46
v_fma_f32 v46, v31, v44, -v47
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v48, v50, v34
v_dual_mul_f32 v49, v40, v34 :: v_dual_fmac_f32 v46, v31, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v24, v24, v48
v_fma_f32 v48, v40, v34, -v49
v_sub_f32_e32 v20, v35, v42
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v46, v28, v44
v_fmac_f32_e32 v48, v40, v24
v_ldexp_f32 v24, v27, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v27, v47, v46
v_fmac_f32_e32 v48, v20, v34
v_add_f32_e32 v20, v45, v43
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v31, v27, v47
v_sub_f32_e32 v29, v20, v45
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v30, v36, v20 :: v_dual_sub_f32 v31, v46, v31
v_dual_sub_f32 v29, v43, v29 :: v_dual_sub_f32 v36, v30, v36
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v14, v14, v31
v_add_f32_e32 v16, v16, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v20, v20, v36
v_add_f32_e32 v16, v16, v20
v_sub_f32_e32 v20, v25, v33
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v20, v26, v20
v_add_f32_e32 v28, v49, v48
v_add_f32_e32 v32, v37, v27
v_sub_f32_e32 v34, v28, v49
v_add_f32_e32 v35, v24, v28
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v37, v32, v37
v_sub_f32_e32 v34, v48, v34
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v24, v35, v24
v_sub_f32_e32 v27, v27, v37
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v17, v17, v34 :: v_dual_sub_f32 v24, v28, v24
v_dual_add_f32 v14, v14, v27 :: v_dual_add_f32 v17, v17, v24
v_add_f32_e32 v24, v30, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v26, v35, v17 :: v_dual_sub_f32 v27, v24, v30
v_dual_add_f32 v28, v19, v24 :: v_dual_sub_f32 v31, v26, v35
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v16, v16, v27
v_sub_f32_e32 v27, v28, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v17, v17, v31
v_sub_f32_e32 v33, v28, v27
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v24, v24, v27 :: v_dual_add_f32 v27, v13, v16
v_sub_f32_e32 v19, v19, v33
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v33, v27, v13
v_dual_add_f32 v19, v24, v19 :: v_dual_sub_f32 v24, v27, v33
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v16, v16, v33 :: v_dual_add_f32 v19, v27, v19
v_sub_f32_e32 v13, v13, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v16, v13
v_add_f32_e32 v18, v32, v14
v_dual_sub_f32 v29, v18, v32 :: v_dual_add_f32 v32, v25, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v31, v32, v25
v_sub_f32_e32 v35, v32, v31
v_dual_sub_f32 v26, v26, v31 :: v_dual_add_f32 v31, v20, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v25, v25, v35
v_sub_f32_e32 v35, v31, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v25, v26, v25 :: v_dual_sub_f32 v26, v31, v35
v_dual_sub_f32 v17, v17, v35 :: v_dual_add_f32 v24, v31, v25
v_add_f32_e32 v25, v28, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v20, v20, v26
v_sub_f32_e32 v26, v25, v28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v17, v17, v20 :: v_dual_sub_f32 v16, v19, v26
v_cndmask_b32_e64 v19, v21, |v5|, s8
v_cmp_eq_f32_e64 s8, |v6|, 1.0
v_dual_add_f32 v13, v13, v16 :: v_dual_add_f32 v30, v22, v18
v_sub_f32_e32 v14, v14, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v20, v23, |v6|, s8
v_cmp_eq_f32_e64 s8, |v7|, 1.0
v_cndmask_b32_e64 v16, 1.0, v6, s7
v_sub_f32_e32 v29, v30, v22
v_cndmask_b32_e64 v12, v12, |v7|, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v34, v30, v29
v_dual_sub_f32 v18, v18, v29 :: v_dual_add_f32 v29, v15, v14
v_sub_f32_e32 v22, v22, v34
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v34, v29, v15
v_add_f32_e32 v18, v18, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v22, v29, v34
v_sub_f32_e32 v14, v14, v34
v_add_f32_e32 v18, v29, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v15, v15, v22 :: v_dual_add_f32 v22, v32, v24
v_add_f32_e32 v27, v30, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v14, v14, v15
v_dual_sub_f32 v15, v22, v32 :: v_dual_sub_f32 v28, v27, v30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v15, v24, v15 :: v_dual_sub_f32 v18, v18, v28
v_add_f32_e32 v15, v17, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v17, v25, v13 :: v_dual_add_f32 v14, v14, v18
v_add_f32_e32 v21, v22, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_sub_f32 v23, v17, v25 :: v_dual_add_f32 v18, v27, v14
v_mul_f32_e32 v24, v2, v17
v_sub_f32_e32 v22, v21, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v13, v13, v23
v_dual_sub_f32 v25, v18, v27 :: v_dual_mul_f32 v26, v3, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v17, v2, v17, -v24
v_mul_f32_e32 v27, v4, v21
v_dual_sub_f32 v15, v15, v22 :: v_dual_sub_f32 v14, v14, v25
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v18, v3, v18, -v26
v_fmac_f32_e32 v17, v2, v13
s_delay_alu instid0(VALU_DEP_4)
v_fma_f32 v21, v4, v21, -v27
v_cmp_class_f32_e64 s8, v24, 0x204
v_cndmask_b32_e64 v13, 1.0, v7, s6
v_fmac_f32_e32 v18, v3, v14
v_add_f32_e32 v14, v24, v17
v_fmac_f32_e32 v21, v4, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v15, v26, v18
v_sub_f32_e32 v23, v14, v24
v_cndmask_b32_e64 v14, v14, v24, s8
v_cmp_class_f32_e64 s8, v26, 0x204
v_add_f32_e32 v22, v27, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v24, v15, v26 :: v_dual_sub_f32 v17, v17, v23
v_cndmask_b32_e64 v15, v15, v26, s8
v_cmp_class_f32_e64 s8, v27, 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v18, v18, v24
v_cndmask_b32_e64 v25, v22, v27, s8
v_cmp_eq_f32_e64 s8, 0x42b17218, v14
v_sub_f32_e32 v22, v22, v27
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v26, 0, 0x37000000, s8
v_cmp_eq_f32_e64 s8, 0x42b17218, v15
v_sub_f32_e32 v21, v21, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v30, v14, v26
v_cndmask_b32_e64 v28, 0, 0x37000000, s8
v_cmp_eq_f32_e64 s8, 0x42b17218, v25
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v31, 0x3fb8aa3b, v30
v_sub_f32_e32 v27, v15, v28
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v29, 0, 0x37000000, s8
v_cmp_neq_f32_e64 s8, 0x7f800000, |v14|
v_fma_f32 v32, v30, 0x3fb8aa3b, -v31
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_mul_f32 v24, 0x3fb8aa3b, v27 :: v_dual_sub_f32 v23, v25, v29
v_rndne_f32_e32 v33, v31
v_cndmask_b32_e64 v14, 0, v17, s8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v32, 0x32a5705f, v30
v_fma_f32 v34, v27, 0x3fb8aa3b, -v24
v_mul_f32_e32 v22, 0x3fb8aa3b, v23
v_rndne_f32_e32 v35, v24
v_sub_f32_e32 v31, v31, v33
v_cmp_neq_f32_e64 s8, 0x7f800000, |v15|
v_fmac_f32_e32 v34, 0x32a5705f, v27
v_fma_f32 v36, v23, 0x3fb8aa3b, -v22
v_rndne_f32_e32 v37, v22
v_dual_sub_f32 v24, v24, v35 :: v_dual_add_f32 v17, v31, v32
v_cndmask_b32_e64 v15, 0, v18, s8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v36, 0x32a5705f, v23
v_sub_f32_e32 v22, v22, v37
s_delay_alu instid0(VALU_DEP_4)
v_add_f32_e32 v24, v24, v34
v_exp_f32_e32 v17, v17
v_cmp_neq_f32_e64 s8, 0x7f800000, |v25|
v_cvt_i32_f32_e32 v25, v35
v_add_f32_e32 v22, v22, v36
v_exp_f32_e32 v18, v24
v_cvt_i32_f32_e32 v24, v33
v_cndmask_b32_e64 v21, 0, v21, s8
v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v30
v_exp_f32_e32 v22, v22
v_add_f32_e32 v14, v26, v14
v_ldexp_f32 v17, v17, v24
v_cvt_i32_f32_e32 v26, v37
v_add_f32_e32 v15, v28, v15
v_add_f32_e32 v21, v29, v21
v_ldexp_f32 v18, v18, v25
v_cndmask_b32_e64 v17, 0, v17, s8
v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v27
v_cndmask_b32_e64 v24, 0, v6, s7
v_ldexp_f32 v22, v22, v26
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v18, 0, v18, s8
v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v23
v_bfi_b32 v9, 0x7fffffff, v9, v24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v22, 0, v22, s8
v_cmp_nlt_f32_e64 s8, 0x42b17218, v30
v_cndmask_b32_e64 v17, 0x7f800000, v17, s8
v_cmp_nlt_f32_e64 s8, 0x42b17218, v27
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, v17, v14, v17
v_cndmask_b32_e64 v18, 0x7f800000, v18, s8
v_cmp_nlt_f32_e64 s8, 0x42b17218, v23
v_cndmask_b32_e64 v23, 0, v5, s5
v_cmp_eq_f32_e64 s5, 0x7f800000, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v15, v18, v15, v18
v_cndmask_b32_e64 v22, 0x7f800000, v22, s8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_bfi_b32 v8, 0x7fffffff, v8, v23
v_cndmask_b32_e64 v14, v14, v17, s5
v_cmp_eq_f32_e64 s5, 0x7f800000, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v21, v22, v21, v22
v_bfi_b32 v11, 0x7fffffff, v14, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, v15, v18, s5
v_cmp_eq_f32_e64 s5, 0x7f800000, v22
v_cndmask_b32_e64 v18, 0, v7, s6
v_bfi_b32 v14, 0x7fffffff, v15, v16
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v17, v21, v22, s5
v_cndmask_b32_e64 v15, 0x7fc00000, v11, s2
v_cmp_gt_f32_e64 s2, 0, v5
v_bfi_b32 v10, 0x7fffffff, v10, v18
v_cndmask_b32_e64 v16, 0x7fc00000, v14, s3
v_bfi_b32 v13, 0x7fffffff, v17, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v11, v11, v15, s2
v_cmp_gt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v17, 0x7fc00000, v13, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v14, v14, v16, s2
v_cmp_gt_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v13, v13, v17, s2
v_cmp_class_f32_e64 s2, v2, 0x204
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v11, v11, v19, s2
v_cmp_class_f32_e64 s2, v3, 0x204
v_cndmask_b32_e32 v8, v11, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v14, v14, v20, s2
v_cmp_class_f32_e64 s2, v4, 0x204
s_or_b32 vcc_lo, s0, s15
v_cndmask_b32_e32 v9, v14, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v12, v13, v12, s2
s_or_b32 vcc_lo, s1, s16
v_cndmask_b32_e32 v10, v12, v10, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v5, v2
v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v6, v3
v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v7, v4
v_cndmask_b32_e32 v4, 0x7fc00000, v10, vcc_lo
global_store_b96 v[0:1], v[2:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gamma_transform_2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 51
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gamma_transform_2, .Lfunc_end0-gamma_transform_2
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gamma_transform_2
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: gamma_transform_2.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 51
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" {
__global__ void gamma_transform_2(float3* d_idata, float3* d_odata, int width, int height, float gamma)
{
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = yIndex * width + xIndex;
if (xIndex < width && yIndex < height){
float3 rgb = d_idata[idx];
d_odata[idx].x = powf(rgb.x, gamma);
d_odata[idx].y = powf(rgb.y, gamma);
d_odata[idx].z = powf(rgb.z, gamma);
}
}
} | .text
.file "06-gamma-transform.hip"
.globl __device_stub__gamma_transform_2 # -- Begin function __device_stub__gamma_transform_2
.p2align 4, 0x90
.type __device_stub__gamma_transform_2,@function
__device_stub__gamma_transform_2: # @__device_stub__gamma_transform_2
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gamma_transform_2, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__gamma_transform_2, .Lfunc_end0-__device_stub__gamma_transform_2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gamma_transform_2, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gamma_transform_2,@object # @gamma_transform_2
.section .rodata,"a",@progbits
.globl gamma_transform_2
.p2align 3, 0x0
gamma_transform_2:
.quad __device_stub__gamma_transform_2
.size gamma_transform_2, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gamma_transform_2"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gamma_transform_2
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gamma_transform_2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000475c0_00000000-6_06-gamma-transform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
.type _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif, @function
_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gamma_transform_2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif, .-_Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
.globl gamma_transform_2
.type gamma_transform_2, @function
gamma_transform_2:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z17gamma_transform_2P6float3S0_iifP6float3S0_iif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gamma_transform_2, .-gamma_transform_2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gamma_transform_2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gamma_transform_2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "06-gamma-transform.hip"
.globl __device_stub__gamma_transform_2 # -- Begin function __device_stub__gamma_transform_2
.p2align 4, 0x90
.type __device_stub__gamma_transform_2,@function
__device_stub__gamma_transform_2: # @__device_stub__gamma_transform_2
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gamma_transform_2, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__gamma_transform_2, .Lfunc_end0-__device_stub__gamma_transform_2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gamma_transform_2, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gamma_transform_2,@object # @gamma_transform_2
.section .rodata,"a",@progbits
.globl gamma_transform_2
.p2align 3, 0x0
gamma_transform_2:
.quad __device_stub__gamma_transform_2
.size gamma_transform_2, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gamma_transform_2"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gamma_transform_2
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gamma_transform_2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
// #include <helper_cuda.h>
#define N 1024
#define THREADS_PER_BLOCK 32
__global__ void SingleBlockLoop(){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < N)
printf("%d\n", i);
}
int main(void){
cudaError_t err = cudaSuccess;
SingleBlockLoop<<<(N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>();
if ((err = cudaGetLastError()) != cudaSuccess){
fprintf(stderr, "Failed to launch kernel: %s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z15SingleBlockLoopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x3ff, PT ; /* 0x000003ff0000780c */
/* 0x000fda0003f04270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0090*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e20000100800 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*00c0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fce00078e00ff */
/*00e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00f0*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0140*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0150*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
// #include <helper_cuda.h>
#define N 1024
#define THREADS_PER_BLOCK 32
__global__ void SingleBlockLoop(){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < N)
printf("%d\n", i);
}
int main(void){
cudaError_t err = cudaSuccess;
SingleBlockLoop<<<(N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>();
if ((err = cudaGetLastError()) != cudaSuccess){
fprintf(stderr, "Failed to launch kernel: %s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000546a5_00000000-6_SingleBlockLoop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z15SingleBlockLoopvv
.type _Z34__device_stub__Z15SingleBlockLoopvv, @function
_Z34__device_stub__Z15SingleBlockLoopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z15SingleBlockLoopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z15SingleBlockLoopvv, .-_Z34__device_stub__Z15SingleBlockLoopvv
.globl _Z15SingleBlockLoopv
.type _Z15SingleBlockLoopv, @function
_Z15SingleBlockLoopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15SingleBlockLoopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15SingleBlockLoopv, .-_Z15SingleBlockLoopv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to launch kernel: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z34__device_stub__Z15SingleBlockLoopvv
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15SingleBlockLoopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15SingleBlockLoopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
// #include <helper_cuda.h>
#define N 1024
#define THREADS_PER_BLOCK 32
__global__ void SingleBlockLoop(){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < N)
printf("%d\n", i);
}
int main(void){
cudaError_t err = cudaSuccess;
SingleBlockLoop<<<(N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>();
if ((err = cudaGetLastError()) != cudaSuccess){
fprintf(stderr, "Failed to launch kernel: %s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
// #include <helper_cuda.h>
#define N 1024
#define THREADS_PER_BLOCK 32
__global__ void SingleBlockLoop(){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < N)
printf("%d\n", i);
}
int main(void){
hipError_t err = hipSuccess;
SingleBlockLoop<<<(N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>();
if ((err = hipGetLastError()) != hipSuccess){
fprintf(stderr, "Failed to launch kernel: %s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// #include <helper_cuda.h>
#define N 1024
#define THREADS_PER_BLOCK 32
__global__ void SingleBlockLoop(){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < N)
printf("%d\n", i);
}
int main(void){
hipError_t err = hipSuccess;
SingleBlockLoop<<<(N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>();
if ((err = hipGetLastError()) != hipSuccess){
fprintf(stderr, "Failed to launch kernel: %s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
return 0;
} | .text
.file "SingleBlockLoop.hip"
.globl _Z30__device_stub__SingleBlockLoopv # -- Begin function _Z30__device_stub__SingleBlockLoopv
.p2align 4, 0x90
.type _Z30__device_stub__SingleBlockLoopv,@function
_Z30__device_stub__SingleBlockLoopv: # @_Z30__device_stub__SingleBlockLoopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15SingleBlockLoopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z30__device_stub__SingleBlockLoopv, .Lfunc_end0-_Z30__device_stub__SingleBlockLoopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967328, %rdi # imm = 0x100000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15SingleBlockLoopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15SingleBlockLoopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15SingleBlockLoopv,@object # @_Z15SingleBlockLoopv
.section .rodata,"a",@progbits
.globl _Z15SingleBlockLoopv
.p2align 3, 0x0
_Z15SingleBlockLoopv:
.quad _Z30__device_stub__SingleBlockLoopv
.size _Z15SingleBlockLoopv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to launch kernel: %s\n"
.size .L.str, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15SingleBlockLoopv"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__SingleBlockLoopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15SingleBlockLoopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000546a5_00000000-6_SingleBlockLoop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z15SingleBlockLoopvv
.type _Z34__device_stub__Z15SingleBlockLoopvv, @function
_Z34__device_stub__Z15SingleBlockLoopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z15SingleBlockLoopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z15SingleBlockLoopvv, .-_Z34__device_stub__Z15SingleBlockLoopvv
.globl _Z15SingleBlockLoopv
.type _Z15SingleBlockLoopv, @function
_Z15SingleBlockLoopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15SingleBlockLoopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15SingleBlockLoopv, .-_Z15SingleBlockLoopv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to launch kernel: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z34__device_stub__Z15SingleBlockLoopvv
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15SingleBlockLoopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15SingleBlockLoopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SingleBlockLoop.hip"
.globl _Z30__device_stub__SingleBlockLoopv # -- Begin function _Z30__device_stub__SingleBlockLoopv
.p2align 4, 0x90
.type _Z30__device_stub__SingleBlockLoopv,@function
_Z30__device_stub__SingleBlockLoopv: # @_Z30__device_stub__SingleBlockLoopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15SingleBlockLoopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z30__device_stub__SingleBlockLoopv, .Lfunc_end0-_Z30__device_stub__SingleBlockLoopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967328, %rdi # imm = 0x100000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15SingleBlockLoopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.3:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15SingleBlockLoopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15SingleBlockLoopv,@object # @_Z15SingleBlockLoopv
.section .rodata,"a",@progbits
.globl _Z15SingleBlockLoopv
.p2align 3, 0x0
_Z15SingleBlockLoopv:
.quad _Z30__device_stub__SingleBlockLoopv
.size _Z15SingleBlockLoopv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to launch kernel: %s\n"
.size .L.str, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15SingleBlockLoopv"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__SingleBlockLoopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15SingleBlockLoopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sigmoid32(float* A, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int idx = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (idx >= size) {
return;
}
A[idx] = 1 / (1 + powf((float)(M_E), (-1 * A[idx])));
} | code for sm_80
Function : _Z9sigmoid32Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R5 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0x470 ; /* 0x0000034000007945 */
/* 0x000fe20003800000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff047435 */
/* 0x000fe200000001ff */
/*0140*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x004fda0003f0d000 */
/*0150*/ @!P0 BRA 0x460 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R6, 0x34000000 ; /* 0x3400000000067802 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3dbdd9bd ; /* 0x3dbdd9bdff087424 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R5, 0x3a2c32e4 ; /* 0x3a2c32e400057802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R11, 0x3e9be32a ; /* 0x3e9be32a000b7802 */
/* 0x000fe20000000f00 */
/*01a0*/ FFMA R6, R6, 8388608, RZ ; /* 0x4b00000006067823 */
/* 0x000fe200000000ff */
/*01b0*/ MOV R4, 0x3eb7e150 ; /* 0x3eb7e15000047802 */
/* 0x000fe20000000f00 */
/*01c0*/ FFMA R5, R8, R5, 0.0032181653659790754318 ; /* 0x3b52e7db08057423 */
/* 0x000fe20000000005 */
/*01d0*/ FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f4c200 */
/*01e0*/ FFMA R7, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b077823 */
/* 0x000fe40000000006 */
/*01f0*/ FFMA R4, R4, -R11, 0.10934674739837646484 ; /* 0x3ddff13004047423 */
/* 0x000fc4000000080b */
/*0200*/ FFMA R5, R5, R8.reuse, 0.018033718690276145935 ; /* 0x3c93bb7305057423 */
/* 0x080fe40000000008 */
/*0210*/ FADD R6, R6, -R7 ; /* 0x8000000706067221 */
/* 0x000fe40000000000 */
/*0220*/ FMUL R4, R4, 0.42388311028480529785 ; /* 0x3ed9073504047820 */
/* 0x000fe40000400000 */
/*0230*/ FFMA R5, R5, R8, 0.12022458761930465698 ; /* 0x3df6384f05057423 */
/* 0x000fe40000000008 */
/*0240*/ FFMA R9, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b097823 */
/* 0x000fe40000000006 */
/*0250*/ FMUL R5, R5, 0.092700459063053131104 ; /* 0x3dbdd9bd05057820 */
/* 0x000fc40000400000 */
/*0260*/ FFMA R6, R4.reuse, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b04067823 */
/* 0x040fe40000000009 */
/*0270*/ FMUL R9, R5, 3 ; /* 0x4040000005097820 */
/* 0x000fe40000400000 */
/*0280*/ FFMA R6, R11, 1.9251366722983220825e-08, R6 ; /* 0x32a55e340b067823 */
/* 0x000fe40000000006 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff087424 */
/* 0x000fe400078e00ff */
/*02a0*/ FFMA R6, R4, R9, R6 ; /* 0x0000000904067223 */
/* 0x000fc80000000006 */
/*02b0*/ FFMA R6, R5, 0.3044674992561340332, R6 ; /* 0x3e9be32a05067823 */
/* 0x000fc80000000006 */
/*02c0*/ FADD R5, R7, R6 ; /* 0x0000000607057221 */
/* 0x000fc80000000000 */
/*02d0*/ FMUL R4, R0.reuse, -R5.reuse ; /* 0x8000000500047220 */
/* 0x0c0fe40000400000 */
/*02e0*/ FADD R7, -R7, R5 ; /* 0x0000000507077221 */
/* 0x000fe40000000100 */
/*02f0*/ FRND R9, R4 ; /* 0x0000000400097307 */
/* 0x000e220000201000 */
/*0300*/ FFMA R5, -R0, R5, -R4 ; /* 0x0000000500057223 */
/* 0x000fe20000000904 */
/*0310*/ FSETP.GT.AND P0, PT, |R4|, 152, PT ; /* 0x431800000400780b */
/* 0x000fe20003f04200 */
/*0320*/ FADD R7, R6, -R7 ; /* 0x8000000706077221 */
/* 0x000fc80000000000 */
/*0330*/ FFMA R6, -R0, R7, R5 ; /* 0x0000000700067223 */
/* 0x000fe40000000105 */
/*0340*/ F2I.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000e620000203100 */
/*0350*/ FADD R5, R4, -R9 ; /* 0x8000000904057221 */
/* 0x001fe20000000000 */
/*0360*/ FSETP.GT.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fc60003f24000 */
/*0370*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x000fc80000000000 */
/*0380*/ FFMA R6, R5, R8, 0.0013391353422775864601 ; /* 0x3aaf85ed05067423 */
/* 0x000fc80000000008 */
/*0390*/ FFMA R6, R5, R6, 0.0096188392490148544312 ; /* 0x3c1d985605067423 */
/* 0x000fc80000000006 */
/*03a0*/ FFMA R6, R5, R6, 0.055503588169813156128 ; /* 0x3d6357bb05067423 */
/* 0x000fc80000000006 */
/*03b0*/ FFMA R8, R5.reuse, R6, 0.24022644758224487305 ; /* 0x3e75fdec05087423 */
/* 0x040fe20000000006 */
/*03c0*/ SEL R6, RZ, 0x83000000, P1 ; /* 0x83000000ff067807 */
/* 0x000fe40000800000 */
/*03d0*/ FSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f2e000 */
/*03e0*/ FFMA R10, R5, R8, 0.69314718246459960938 ; /* 0x3f317218050a7423 */
/* 0x000fe20000000008 */
/*03f0*/ IADD3 R8, R6, 0x7f000000, RZ ; /* 0x7f00000006087810 */
/* 0x000fe40007ffe0ff */
/*0400*/ LEA R7, R7, -R6, 0x17 ; /* 0x8000000607077211 */
/* 0x002fe200078eb8ff */
/*0410*/ FFMA R5, R5, R10, 1 ; /* 0x3f80000005057423 */
/* 0x000fe2000000000a */
/*0420*/ FSEL R4, RZ, +INF , !P1 ; /* 0x7f800000ff047808 */
/* 0x000fc60004800000 */
/*0430*/ FMUL R8, R8, R5 ; /* 0x0000000508087220 */
/* 0x000fc80000400000 */
/*0440*/ @!P0 FMUL R4, R7, R8 ; /* 0x0000000807048220 */
/* 0x000fe40000400000 */
/*0450*/ @P2 FADD R4, -R0, 2.7182817459106445312 ; /* 0x402df85400042421 */
/* 0x000fe40000000100 */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ FADD R6, R4, 1 ; /* 0x3f80000004067421 */
/* 0x000fe20000000000 */
/*0480*/ BSSY B0, 0x560 ; /* 0x000000d000007945 */
/* 0x000fe80003800000 */
/*0490*/ IADD3 R0, R6, 0x1800000, RZ ; /* 0x0180000006007810 */
/* 0x000fc80007ffe0ff */
/*04a0*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*04b0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*04c0*/ @P0 BRA 0x510 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*04d0*/ MOV R0, 0x4f0 ; /* 0x000004f000007802 */
/* 0x000fe40000000f00 */
/*04e0*/ CALL.REL.NOINC 0x580 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*04f0*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*0500*/ BRA 0x550 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0510*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e240000001000 */
/*0520*/ FFMA R0, R6, R5, -1 ; /* 0xbf80000006007423 */
/* 0x001fc80000000005 */
/*0530*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0540*/ FFMA R5, R5, R0, R5 ; /* 0x0000000005057223 */
/* 0x000fe40000000005 */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ SHF.L.U32 R4, R6, 0x1, RZ ; /* 0x0000000106047819 */
/* 0x000fe200000006ff */
/*0590*/ BSSY B1, 0x8b0 ; /* 0x0000031000017945 */
/* 0x000fe60003800000 */
/*05a0*/ SHF.R.U32.HI R10, RZ, 0x18, R4 ; /* 0x00000018ff0a7819 */
/* 0x000fe20000011604 */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0006 */
/*05c0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*05d0*/ @P0 BRA 0x680 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*05e0*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x000fc800000006ff */
/*05f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0600*/ @P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004060823 */
/* 0x000fe200000000ff */
/*0610*/ @!P0 MUFU.RCP R5, R4 ; /* 0x0000000400058308 */
/* 0x000ff00000001000 */
/*0620*/ @P0 MUFU.RCP R7, R6 ; /* 0x0000000600070308 */
/* 0x000e240000001000 */
/*0630*/ @P0 FFMA R8, R6, R7, -1 ; /* 0xbf80000006080423 */
/* 0x001fc80000000007 */
/*0640*/ @P0 FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08080221 */
/* 0x000fc80000010100 */
/*0650*/ @P0 FFMA R8, R7, R8, R7 ; /* 0x0000000807080223 */
/* 0x000fc80000000007 */
/*0660*/ @P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008050823 */
/* 0x000fe200000000ff */
/*0670*/ BRA 0x8a0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0680*/ IADD3 R12, R10, -0xfd, RZ ; /* 0xffffff030a0c7810 */
/* 0x000fc80007ffe0ff */
/*0690*/ ISETP.GT.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f04070 */
/*06a0*/ @P0 BRA 0x890 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*06b0*/ LOP3.LUT R5, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04057812 */
/* 0x000fe200078ec0ff */
/*06c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff097435 */
/* 0x000fc600000001ff */
/*06d0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fc800078efcff */
/*06e0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e260000001000 */
/*06f0*/ SHF.L.U32 R9, R9, R12, RZ ; /* 0x0000000c09097219 */
/* 0x000fe200000006ff */
/*0700*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0710*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0720*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0730*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0740*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0750*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0760*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0770*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0780*/ LOP3.LUT R9, R9, R6, RZ, 0xc0, !PT ; /* 0x0000000609097212 */
/* 0x000fe400078ec0ff */
/*0790*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fc40007ffe1ff */
/*07a0*/ SHF.R.U32.HI R9, RZ, R12.reuse, R9 ; /* 0x0000000cff097219 */
/* 0x080fe40000011609 */
/*07b0*/ LOP3.LUT P1, RZ, R7, R12, R6, 0xf8, !PT ; /* 0x0000000c07ff7212 */
/* 0x000fe4000782f806 */
/*07c0*/ LOP3.LUT P0, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe4000780c0ff */
/*07d0*/ LOP3.LUT P2, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fc8000784c0ff */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*07f0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*0800*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0810*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0820*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0830*/ IADD3 R5, R10, -0xfc, RZ ; /* 0xffffff040a057810 */
/* 0x000fc80007ffe0ff */
/*0840*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fce0000011606 */
/*0850*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x000fc80007ffe0ff */
/*0860*/ @!P1 SHF.L.U32 R5, R5, 0x1, RZ ; /* 0x0000000105059819 */
/* 0x000fc800000006ff */
/*0870*/ LOP3.LUT R5, R5, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078ef804 */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x0000640000001000 */
/*08a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08b0*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x002fe20000000f00 */
/*08c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*08d0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x001fca0000000f00 */
/*08e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff71004007950 */
/* 0x000fea0003c3ffff */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sigmoid32(float* A, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int idx = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (idx >= size) {
return;
}
A[idx] = 1 / (1 + powf((float)(M_E), (-1 * A[idx])));
} | .file "tmpxft_000e7c5c_00000000-6_sigmoid32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9sigmoid32PfiPfi
.type _Z29__device_stub__Z9sigmoid32PfiPfi, @function
_Z29__device_stub__Z9sigmoid32PfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9sigmoid32Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9sigmoid32PfiPfi, .-_Z29__device_stub__Z9sigmoid32PfiPfi
.globl _Z9sigmoid32Pfi
.type _Z9sigmoid32Pfi, @function
_Z9sigmoid32Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9sigmoid32PfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9sigmoid32Pfi, .-_Z9sigmoid32Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9sigmoid32Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sigmoid32Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sigmoid32(float* A, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int idx = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (idx >= size) {
return;
}
A[idx] = 1 / (1 + powf((float)(M_E), (-1 * A[idx])));
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoid32(float* A, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int idx = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (idx >= size) {
return;
}
A[idx] = 1 / (1 + powf((float)(M_E), (-1 * A[idx])));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoid32(float* A, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int idx = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (idx >= size) {
return;
}
A[idx] = 1 / (1 + powf((float)(M_E), (-1 * A[idx])));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sigmoid32Pfi
.globl _Z9sigmoid32Pfi
.p2align 8
.type _Z9sigmoid32Pfi,@function
_Z9sigmoid32Pfi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x1c
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x8
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3e76c4e1
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v3, 0x402df854, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v4, v3
v_frexp_exp_i32_f32_e32 v3, v3
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, 1, s0
v_subrev_co_ci_u32_e64 v3, s0, 0, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v4, v4, v5
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, -1.0, v4
v_add_f32_e32 v5, 1.0, v4
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v8, v7, v6 :: v_dual_add_f32 v9, -1.0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, v5, v8
v_sub_f32_e32 v4, v4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v8, v5, -v10
v_fmac_f32_e32 v5, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v10, v5
v_dual_sub_f32 v9, v7, v4 :: v_dual_sub_f32 v10, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v10, v5
v_sub_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v7, v4
v_add_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v9, v4
v_mul_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v8, v4
v_mul_f32_e32 v7, v5, v5
v_sub_f32_e32 v6, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v4, v6
v_fma_f32 v6, v5, v5, -v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v4, v4
v_fmac_f32_e32 v6, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v7, v6
v_fmaak_f32 v9, s1, v8, 0x3e91f4c4
v_sub_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v9, v8, v9, 0x3ecccdef :: v_dual_sub_f32 v6, v6, v7
v_mul_f32_e32 v10, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v8, v9, -v10
v_dual_fmac_f32 v7, v6, v9 :: v_dual_mul_f32 v12, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v10, v7
v_fma_f32 v13, v8, v5, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v10, v9, v10 :: v_dual_fmac_f32 v13, v8, v4
v_add_f32_e32 v11, 0x3f2aaaaa, v9
v_ldexp_f32 v4, v4, 1
v_sub_f32_e32 v7, v7, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v13, v6, v5
v_ldexp_f32 v5, v5, 1
v_add_f32_e32 v7, 0x31739010, v7
v_add_f32_e32 v10, 0xbf2aaaaa, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v9, v10
v_add_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v11, v7
v_dual_add_f32 v8, v12, v13 :: v_dual_sub_f32 v9, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v10, v8, v6
v_sub_f32_e32 v11, v8, v12
v_add_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, v8, v6, -v10
v_sub_f32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v7
v_fmac_f32_e32 v9, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v10, v9
v_sub_f32_e32 v8, v6, v10
v_mul_f32_e32 v10, 0x3f317218, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v9, v8
v_fma_f32 v9, v3, 0x3f317218, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v4, v4, v8 :: v_dual_add_f32 v7, v5, v6
v_sub_f32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v6, v5
v_add_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v4
v_fmamk_f32 v3, v3, 0xb102e308, v9
v_sub_f32_e32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v4, v7
v_add_f32_e32 v5, v10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v5, v6
v_dual_sub_f32 v10, v5, v10 :: v_dual_sub_f32 v9, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v10 :: v_dual_sub_f32 v6, v6, v9
v_add_f32_e32 v7, v3, v4
v_sub_f32_e32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v11
v_dual_add_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v7, v5
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v8, v5
v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v4, v3 :: v_dual_sub_f32 v4, v5, v6
v_add_f32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v9, v3
v_sub_f32_e32 v5, v4, v9
v_mul_f32_e64 v6, v4, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v5
v_fma_f32 v4, -v2, v4, -v6
v_cmp_class_f32_e64 s0, v6, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v2, v3, v4
v_add_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v4, v6, s0
v_sub_f32_e32 v4, v4, v6
v_cmp_eq_f32_e64 s0, 0x42b17218, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v4
v_cndmask_b32_e64 v7, 0, 0x37000000, s0
v_cmp_neq_f32_e64 s0, 0x7f800000, |v5|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v5, v7
v_cndmask_b32_e64 v3, 0, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, 0x3fb8aa3b, v8
v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v8
v_add_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v10, v8, 0x3fb8aa3b, -v9
v_rndne_f32_e32 v11, v9
v_dual_fmamk_f32 v10, v8, 0x32a5705f, v10 :: v_dual_sub_f32 v9, v9, v11
v_cvt_i32_f32_e32 v6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v9, v10
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, v4, s0
v_cmp_nlt_f32_e64 s0, 0x42b17218, v8
v_cndmask_b32_e64 v4, 0x7f800000, v4, s0
v_cmp_eq_f32_e64 s0, |v2|, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v4, v3, v4
v_cndmask_b32_e64 v5, 0, |v2|, s0
v_cmp_class_f32_e64 s0, v2, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, 1.0, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v4
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cndmask_b32_e64 v3, |v3|, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v3
v_div_scale_f32 v4, null, v3, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v5, v7
v_cmp_o_f32_e32 vcc_lo, v2, v2
v_div_fixup_f32 v3, v4, v3, 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sigmoid32Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sigmoid32Pfi, .Lfunc_end0-_Z9sigmoid32Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sigmoid32Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sigmoid32Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoid32(float* A, int size)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z;
int idx = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * (blockDim.x * blockDim.y)) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (idx >= size) {
return;
}
A[idx] = 1 / (1 + powf((float)(M_E), (-1 * A[idx])));
} | .text
.file "sigmoid32.hip"
.globl _Z24__device_stub__sigmoid32Pfi # -- Begin function _Z24__device_stub__sigmoid32Pfi
.p2align 4, 0x90
.type _Z24__device_stub__sigmoid32Pfi,@function
_Z24__device_stub__sigmoid32Pfi: # @_Z24__device_stub__sigmoid32Pfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9sigmoid32Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__sigmoid32Pfi, .Lfunc_end0-_Z24__device_stub__sigmoid32Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sigmoid32Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sigmoid32Pfi,@object # @_Z9sigmoid32Pfi
.section .rodata,"a",@progbits
.globl _Z9sigmoid32Pfi
.p2align 3, 0x0
_Z9sigmoid32Pfi:
.quad _Z24__device_stub__sigmoid32Pfi
.size _Z9sigmoid32Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9sigmoid32Pfi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sigmoid32Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sigmoid32Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9sigmoid32Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R5 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0x470 ; /* 0x0000034000007945 */
/* 0x000fe20003800000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff047435 */
/* 0x000fe200000001ff */
/*0140*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x004fda0003f0d000 */
/*0150*/ @!P0 BRA 0x460 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R6, 0x34000000 ; /* 0x3400000000067802 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3dbdd9bd ; /* 0x3dbdd9bdff087424 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R5, 0x3a2c32e4 ; /* 0x3a2c32e400057802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R11, 0x3e9be32a ; /* 0x3e9be32a000b7802 */
/* 0x000fe20000000f00 */
/*01a0*/ FFMA R6, R6, 8388608, RZ ; /* 0x4b00000006067823 */
/* 0x000fe200000000ff */
/*01b0*/ MOV R4, 0x3eb7e150 ; /* 0x3eb7e15000047802 */
/* 0x000fe20000000f00 */
/*01c0*/ FFMA R5, R8, R5, 0.0032181653659790754318 ; /* 0x3b52e7db08057423 */
/* 0x000fe20000000005 */
/*01d0*/ FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f4c200 */
/*01e0*/ FFMA R7, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b077823 */
/* 0x000fe40000000006 */
/*01f0*/ FFMA R4, R4, -R11, 0.10934674739837646484 ; /* 0x3ddff13004047423 */
/* 0x000fc4000000080b */
/*0200*/ FFMA R5, R5, R8.reuse, 0.018033718690276145935 ; /* 0x3c93bb7305057423 */
/* 0x080fe40000000008 */
/*0210*/ FADD R6, R6, -R7 ; /* 0x8000000706067221 */
/* 0x000fe40000000000 */
/*0220*/ FMUL R4, R4, 0.42388311028480529785 ; /* 0x3ed9073504047820 */
/* 0x000fe40000400000 */
/*0230*/ FFMA R5, R5, R8, 0.12022458761930465698 ; /* 0x3df6384f05057423 */
/* 0x000fe40000000008 */
/*0240*/ FFMA R9, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b097823 */
/* 0x000fe40000000006 */
/*0250*/ FMUL R5, R5, 0.092700459063053131104 ; /* 0x3dbdd9bd05057820 */
/* 0x000fc40000400000 */
/*0260*/ FFMA R6, R4.reuse, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b04067823 */
/* 0x040fe40000000009 */
/*0270*/ FMUL R9, R5, 3 ; /* 0x4040000005097820 */
/* 0x000fe40000400000 */
/*0280*/ FFMA R6, R11, 1.9251366722983220825e-08, R6 ; /* 0x32a55e340b067823 */
/* 0x000fe40000000006 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff087424 */
/* 0x000fe400078e00ff */
/*02a0*/ FFMA R6, R4, R9, R6 ; /* 0x0000000904067223 */
/* 0x000fc80000000006 */
/*02b0*/ FFMA R6, R5, 0.3044674992561340332, R6 ; /* 0x3e9be32a05067823 */
/* 0x000fc80000000006 */
/*02c0*/ FADD R5, R7, R6 ; /* 0x0000000607057221 */
/* 0x000fc80000000000 */
/*02d0*/ FMUL R4, R0.reuse, -R5.reuse ; /* 0x8000000500047220 */
/* 0x0c0fe40000400000 */
/*02e0*/ FADD R7, -R7, R5 ; /* 0x0000000507077221 */
/* 0x000fe40000000100 */
/*02f0*/ FRND R9, R4 ; /* 0x0000000400097307 */
/* 0x000e220000201000 */
/*0300*/ FFMA R5, -R0, R5, -R4 ; /* 0x0000000500057223 */
/* 0x000fe20000000904 */
/*0310*/ FSETP.GT.AND P0, PT, |R4|, 152, PT ; /* 0x431800000400780b */
/* 0x000fe20003f04200 */
/*0320*/ FADD R7, R6, -R7 ; /* 0x8000000706077221 */
/* 0x000fc80000000000 */
/*0330*/ FFMA R6, -R0, R7, R5 ; /* 0x0000000700067223 */
/* 0x000fe40000000105 */
/*0340*/ F2I.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000e620000203100 */
/*0350*/ FADD R5, R4, -R9 ; /* 0x8000000904057221 */
/* 0x001fe20000000000 */
/*0360*/ FSETP.GT.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fc60003f24000 */
/*0370*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x000fc80000000000 */
/*0380*/ FFMA R6, R5, R8, 0.0013391353422775864601 ; /* 0x3aaf85ed05067423 */
/* 0x000fc80000000008 */
/*0390*/ FFMA R6, R5, R6, 0.0096188392490148544312 ; /* 0x3c1d985605067423 */
/* 0x000fc80000000006 */
/*03a0*/ FFMA R6, R5, R6, 0.055503588169813156128 ; /* 0x3d6357bb05067423 */
/* 0x000fc80000000006 */
/*03b0*/ FFMA R8, R5.reuse, R6, 0.24022644758224487305 ; /* 0x3e75fdec05087423 */
/* 0x040fe20000000006 */
/*03c0*/ SEL R6, RZ, 0x83000000, P1 ; /* 0x83000000ff067807 */
/* 0x000fe40000800000 */
/*03d0*/ FSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f2e000 */
/*03e0*/ FFMA R10, R5, R8, 0.69314718246459960938 ; /* 0x3f317218050a7423 */
/* 0x000fe20000000008 */
/*03f0*/ IADD3 R8, R6, 0x7f000000, RZ ; /* 0x7f00000006087810 */
/* 0x000fe40007ffe0ff */
/*0400*/ LEA R7, R7, -R6, 0x17 ; /* 0x8000000607077211 */
/* 0x002fe200078eb8ff */
/*0410*/ FFMA R5, R5, R10, 1 ; /* 0x3f80000005057423 */
/* 0x000fe2000000000a */
/*0420*/ FSEL R4, RZ, +INF , !P1 ; /* 0x7f800000ff047808 */
/* 0x000fc60004800000 */
/*0430*/ FMUL R8, R8, R5 ; /* 0x0000000508087220 */
/* 0x000fc80000400000 */
/*0440*/ @!P0 FMUL R4, R7, R8 ; /* 0x0000000807048220 */
/* 0x000fe40000400000 */
/*0450*/ @P2 FADD R4, -R0, 2.7182817459106445312 ; /* 0x402df85400042421 */
/* 0x000fe40000000100 */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ FADD R6, R4, 1 ; /* 0x3f80000004067421 */
/* 0x000fe20000000000 */
/*0480*/ BSSY B0, 0x560 ; /* 0x000000d000007945 */
/* 0x000fe80003800000 */
/*0490*/ IADD3 R0, R6, 0x1800000, RZ ; /* 0x0180000006007810 */
/* 0x000fc80007ffe0ff */
/*04a0*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*04b0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*04c0*/ @P0 BRA 0x510 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*04d0*/ MOV R0, 0x4f0 ; /* 0x000004f000007802 */
/* 0x000fe40000000f00 */
/*04e0*/ CALL.REL.NOINC 0x580 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*04f0*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*0500*/ BRA 0x550 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0510*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e240000001000 */
/*0520*/ FFMA R0, R6, R5, -1 ; /* 0xbf80000006007423 */
/* 0x001fc80000000005 */
/*0530*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0540*/ FFMA R5, R5, R0, R5 ; /* 0x0000000005057223 */
/* 0x000fe40000000005 */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ SHF.L.U32 R4, R6, 0x1, RZ ; /* 0x0000000106047819 */
/* 0x000fe200000006ff */
/*0590*/ BSSY B1, 0x8b0 ; /* 0x0000031000017945 */
/* 0x000fe60003800000 */
/*05a0*/ SHF.R.U32.HI R10, RZ, 0x18, R4 ; /* 0x00000018ff0a7819 */
/* 0x000fe20000011604 */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0006 */
/*05c0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*05d0*/ @P0 BRA 0x680 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*05e0*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x000fc800000006ff */
/*05f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0600*/ @P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004060823 */
/* 0x000fe200000000ff */
/*0610*/ @!P0 MUFU.RCP R5, R4 ; /* 0x0000000400058308 */
/* 0x000ff00000001000 */
/*0620*/ @P0 MUFU.RCP R7, R6 ; /* 0x0000000600070308 */
/* 0x000e240000001000 */
/*0630*/ @P0 FFMA R8, R6, R7, -1 ; /* 0xbf80000006080423 */
/* 0x001fc80000000007 */
/*0640*/ @P0 FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08080221 */
/* 0x000fc80000010100 */
/*0650*/ @P0 FFMA R8, R7, R8, R7 ; /* 0x0000000807080223 */
/* 0x000fc80000000007 */
/*0660*/ @P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008050823 */
/* 0x000fe200000000ff */
/*0670*/ BRA 0x8a0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0680*/ IADD3 R12, R10, -0xfd, RZ ; /* 0xffffff030a0c7810 */
/* 0x000fc80007ffe0ff */
/*0690*/ ISETP.GT.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f04070 */
/*06a0*/ @P0 BRA 0x890 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*06b0*/ LOP3.LUT R5, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04057812 */
/* 0x000fe200078ec0ff */
/*06c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff097435 */
/* 0x000fc600000001ff */
/*06d0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fc800078efcff */
/*06e0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e260000001000 */
/*06f0*/ SHF.L.U32 R9, R9, R12, RZ ; /* 0x0000000c09097219 */
/* 0x000fe200000006ff */
/*0700*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0710*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0720*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0730*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0740*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0750*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0760*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0770*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0780*/ LOP3.LUT R9, R9, R6, RZ, 0xc0, !PT ; /* 0x0000000609097212 */
/* 0x000fe400078ec0ff */
/*0790*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fc40007ffe1ff */
/*07a0*/ SHF.R.U32.HI R9, RZ, R12.reuse, R9 ; /* 0x0000000cff097219 */
/* 0x080fe40000011609 */
/*07b0*/ LOP3.LUT P1, RZ, R7, R12, R6, 0xf8, !PT ; /* 0x0000000c07ff7212 */
/* 0x000fe4000782f806 */
/*07c0*/ LOP3.LUT P0, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe4000780c0ff */
/*07d0*/ LOP3.LUT P2, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fc8000784c0ff */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*07f0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*0800*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0810*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0820*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0830*/ IADD3 R5, R10, -0xfc, RZ ; /* 0xffffff040a057810 */
/* 0x000fc80007ffe0ff */
/*0840*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fce0000011606 */
/*0850*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x000fc80007ffe0ff */
/*0860*/ @!P1 SHF.L.U32 R5, R5, 0x1, RZ ; /* 0x0000000105059819 */
/* 0x000fc800000006ff */
/*0870*/ LOP3.LUT R5, R5, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078ef804 */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x0000640000001000 */
/*08a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08b0*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x002fe20000000f00 */
/*08c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*08d0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x001fca0000000f00 */
/*08e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff71004007950 */
/* 0x000fea0003c3ffff */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sigmoid32Pfi
.globl _Z9sigmoid32Pfi
.p2align 8
.type _Z9sigmoid32Pfi,@function
_Z9sigmoid32Pfi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x1c
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x8
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3e76c4e1
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v3, 0x402df854, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v4, v3
v_frexp_exp_i32_f32_e32 v3, v3
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, 1, s0
v_subrev_co_ci_u32_e64 v3, s0, 0, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v4, v4, v5
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, -1.0, v4
v_add_f32_e32 v5, 1.0, v4
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v8, v7, v6 :: v_dual_add_f32 v9, -1.0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, v5, v8
v_sub_f32_e32 v4, v4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v8, v5, -v10
v_fmac_f32_e32 v5, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v10, v5
v_dual_sub_f32 v9, v7, v4 :: v_dual_sub_f32 v10, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v10, v5
v_sub_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v7, v4
v_add_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v9, v4
v_mul_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v8, v4
v_mul_f32_e32 v7, v5, v5
v_sub_f32_e32 v6, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v4, v6
v_fma_f32 v6, v5, v5, -v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v4, v4
v_fmac_f32_e32 v6, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v7, v6
v_fmaak_f32 v9, s1, v8, 0x3e91f4c4
v_sub_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v9, v8, v9, 0x3ecccdef :: v_dual_sub_f32 v6, v6, v7
v_mul_f32_e32 v10, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v8, v9, -v10
v_dual_fmac_f32 v7, v6, v9 :: v_dual_mul_f32 v12, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v10, v7
v_fma_f32 v13, v8, v5, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v10, v9, v10 :: v_dual_fmac_f32 v13, v8, v4
v_add_f32_e32 v11, 0x3f2aaaaa, v9
v_ldexp_f32 v4, v4, 1
v_sub_f32_e32 v7, v7, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v13, v6, v5
v_ldexp_f32 v5, v5, 1
v_add_f32_e32 v7, 0x31739010, v7
v_add_f32_e32 v10, 0xbf2aaaaa, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v9, v10
v_add_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v11, v7
v_dual_add_f32 v8, v12, v13 :: v_dual_sub_f32 v9, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v10, v8, v6
v_sub_f32_e32 v11, v8, v12
v_add_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, v8, v6, -v10
v_sub_f32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v7
v_fmac_f32_e32 v9, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v10, v9
v_sub_f32_e32 v8, v6, v10
v_mul_f32_e32 v10, 0x3f317218, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v9, v8
v_fma_f32 v9, v3, 0x3f317218, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v4, v4, v8 :: v_dual_add_f32 v7, v5, v6
v_sub_f32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v6, v5
v_add_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v4
v_fmamk_f32 v3, v3, 0xb102e308, v9
v_sub_f32_e32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v4, v7
v_add_f32_e32 v5, v10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v5, v6
v_dual_sub_f32 v10, v5, v10 :: v_dual_sub_f32 v9, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v10 :: v_dual_sub_f32 v6, v6, v9
v_add_f32_e32 v7, v3, v4
v_sub_f32_e32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v11
v_dual_add_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v7, v5
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v8, v5
v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v4, v3 :: v_dual_sub_f32 v4, v5, v6
v_add_f32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v9, v3
v_sub_f32_e32 v5, v4, v9
v_mul_f32_e64 v6, v4, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v5
v_fma_f32 v4, -v2, v4, -v6
v_cmp_class_f32_e64 s0, v6, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v2, v3, v4
v_add_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v4, v6, s0
v_sub_f32_e32 v4, v4, v6
v_cmp_eq_f32_e64 s0, 0x42b17218, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v4
v_cndmask_b32_e64 v7, 0, 0x37000000, s0
v_cmp_neq_f32_e64 s0, 0x7f800000, |v5|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v5, v7
v_cndmask_b32_e64 v3, 0, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, 0x3fb8aa3b, v8
v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v8
v_add_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v10, v8, 0x3fb8aa3b, -v9
v_rndne_f32_e32 v11, v9
v_dual_fmamk_f32 v10, v8, 0x32a5705f, v10 :: v_dual_sub_f32 v9, v9, v11
v_cvt_i32_f32_e32 v6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v9, v10
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, v4, s0
v_cmp_nlt_f32_e64 s0, 0x42b17218, v8
v_cndmask_b32_e64 v4, 0x7f800000, v4, s0
v_cmp_eq_f32_e64 s0, |v2|, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v4, v3, v4
v_cndmask_b32_e64 v5, 0, |v2|, s0
v_cmp_class_f32_e64 s0, v2, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, 1.0, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v4
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cndmask_b32_e64 v3, |v3|, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v3
v_div_scale_f32 v4, null, v3, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v5, v7
v_cmp_o_f32_e32 vcc_lo, v2, v2
v_div_fixup_f32 v3, v4, v3, 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sigmoid32Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sigmoid32Pfi, .Lfunc_end0-_Z9sigmoid32Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sigmoid32Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sigmoid32Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e7c5c_00000000-6_sigmoid32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9sigmoid32PfiPfi
.type _Z29__device_stub__Z9sigmoid32PfiPfi, @function
_Z29__device_stub__Z9sigmoid32PfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9sigmoid32Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9sigmoid32PfiPfi, .-_Z29__device_stub__Z9sigmoid32PfiPfi
.globl _Z9sigmoid32Pfi
.type _Z9sigmoid32Pfi, @function
_Z9sigmoid32Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9sigmoid32PfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9sigmoid32Pfi, .-_Z9sigmoid32Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9sigmoid32Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sigmoid32Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sigmoid32.hip"
.globl _Z24__device_stub__sigmoid32Pfi # -- Begin function _Z24__device_stub__sigmoid32Pfi
.p2align 4, 0x90
.type _Z24__device_stub__sigmoid32Pfi,@function
_Z24__device_stub__sigmoid32Pfi: # @_Z24__device_stub__sigmoid32Pfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9sigmoid32Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__sigmoid32Pfi, .Lfunc_end0-_Z24__device_stub__sigmoid32Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sigmoid32Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sigmoid32Pfi,@object # @_Z9sigmoid32Pfi
.section .rodata,"a",@progbits
.globl _Z9sigmoid32Pfi
.p2align 3, 0x0
_Z9sigmoid32Pfi:
.quad _Z24__device_stub__sigmoid32Pfi
.size _Z9sigmoid32Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9sigmoid32Pfi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sigmoid32Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sigmoid32Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Lab2Matrix.cu
*
* Created on: 29 Feb 2020
* Author: sc01716
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define BLOCK_SIZE 16
// Matrices are stored in row-major order
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__ void MatrixMultKern(const Matrix A, const Matrix B, const Matrix C) {
// Calculate the column index of C and B
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Calculate the row index of C and of A
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row < A.height) && (col < B.width)) {
float Cvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < A.width; ++k) {
Cvalue += A.elements[row * A.width + k]
* B.elements[k * B.width + col];
}
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication -Host Code
//Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatrixMult(const Matrix h_A, const Matrix h_B, Matrix h_C) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Load A and B into device memory
Matrix d_A;
d_A.width = h_A.width;
d_A.height = h_A.height;
size_t size = h_A.width * h_A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, h_A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = h_B.width;
d_B.height = h_B.height;
size = h_B.width * h_B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, h_B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in Device memory
Matrix d_C;
d_C.width = h_C.width;
d_C.height = h_C.height;
size = h_C.width * h_C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke Kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(d_B.width / dimBlock.x, d_A.height / dimBlock.y);
cudaEventRecord(start);
MatrixMultKern<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaEventRecord(stop);
// Read C from Device to Host
cudaMemcpy(h_C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
//printf("Copy h_C off device: %s\n", cudaGetErrorString(err));
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Elapsed time was: %f\n milliseconds", milliseconds);
// Free Device Memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char* argv[]) {
Matrix A, B, C;
// Read Dimensions of A and B
A.height = atoi(argv[1]);
A.width = atoi(argv[2]);
B.height = A.width;
B.width = atoi(argv[3]);
A.elements = (float*) malloc(A.width * A.height * sizeof(float));
B.elements = (float*) malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*) malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = (float) (rand() % 3);
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = (float) (rand() % 2);
MatrixMult(A, B, C);
//printing full matrix
/*
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
*/
//printing only part of the matrix
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
printf("%d ",C.width);
return 0;
} | code for sm_80
Function : _Z14MatrixMultKern6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x160], RZ ; /* 0x0000580003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x160], R2 ; /* 0x0000580003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x170], R0 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Lab2Matrix.cu
*
* Created on: 29 Feb 2020
* Author: sc01716
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define BLOCK_SIZE 16
// Matrices are stored in row-major order
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__ void MatrixMultKern(const Matrix A, const Matrix B, const Matrix C) {
// Calculate the column index of C and B
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Calculate the row index of C and of A
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row < A.height) && (col < B.width)) {
float Cvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < A.width; ++k) {
Cvalue += A.elements[row * A.width + k]
* B.elements[k * B.width + col];
}
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication -Host Code
//Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatrixMult(const Matrix h_A, const Matrix h_B, Matrix h_C) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Load A and B into device memory
Matrix d_A;
d_A.width = h_A.width;
d_A.height = h_A.height;
size_t size = h_A.width * h_A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, h_A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = h_B.width;
d_B.height = h_B.height;
size = h_B.width * h_B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, h_B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in Device memory
Matrix d_C;
d_C.width = h_C.width;
d_C.height = h_C.height;
size = h_C.width * h_C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke Kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(d_B.width / dimBlock.x, d_A.height / dimBlock.y);
cudaEventRecord(start);
MatrixMultKern<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaEventRecord(stop);
// Read C from Device to Host
cudaMemcpy(h_C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
//printf("Copy h_C off device: %s\n", cudaGetErrorString(err));
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Elapsed time was: %f\n milliseconds", milliseconds);
// Free Device Memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char* argv[]) {
Matrix A, B, C;
// Read Dimensions of A and B
A.height = atoi(argv[1]);
A.width = atoi(argv[2]);
B.height = A.width;
B.width = atoi(argv[3]);
A.elements = (float*) malloc(A.width * A.height * sizeof(float));
B.elements = (float*) malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*) malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = (float) (rand() % 3);
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = (float) (rand() % 2);
MatrixMult(A, B, C);
//printing full matrix
/*
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
*/
//printing only part of the matrix
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
printf("%d ",C.width);
return 0;
} | .file "tmpxft_00193f3f_00000000-6_Lab2Test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
.type _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_, @function
_Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14MatrixMultKern6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_, .-_Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
.globl _Z14MatrixMultKern6MatrixS_S_
.type _Z14MatrixMultKern6MatrixS_S_, @function
_Z14MatrixMultKern6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14MatrixMultKern6MatrixS_S_, .-_Z14MatrixMultKern6MatrixS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Elapsed time was: %f\n milliseconds"
.text
.globl _Z10MatrixMult6MatrixS_S_
.type _Z10MatrixMult6MatrixS_S_, @function
_Z10MatrixMult6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %r14
movq %rsi, 8(%rsp)
movq %rdx, %rbx
movq %rcx, 16(%rsp)
movq %r8, %r13
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, %r12
sarq $32, %r12
movq %rdx, %r15
sarq $32, %r15
movq %r8, %rbp
sarq $32, %rbp
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %r14d, 80(%rsp)
movl %r12d, 84(%rsp)
imull %r14d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 96(%rsp)
movl %r15d, 100(%rsp)
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 112(%rsp)
movl %ebp, 116(%rsp)
imull %r13d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, 64(%rsp)
movl 84(%rsp), %eax
shrl $4, %eax
movl 96(%rsp), %edx
shrl $4, %edx
movl %edx, 68(%rsp)
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 120(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 160(%rsp)
leaq 160(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 160(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
movdqa 112(%rsp), %xmm3
movaps %xmm3, 160(%rsp)
leaq 160(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10MatrixMult6MatrixS_S_, .-_Z10MatrixMult6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.LC4:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, (%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
movl %eax, 8(%rsp)
movl %r13d, %edi
imull %r12d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
movl %r15d, %edi
imull %r12d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r15d, %edi
imull %r13d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
testl %r13d, %r13d
jle .L18
movl %r12d, 12(%rsp)
movl $0, %r15d
leal -1(%r12), %eax
movl %eax, 16(%rsp)
movq %rbx, 40(%rsp)
movq %r12, 48(%rsp)
movq %r13, 56(%rsp)
movq %rbp, %r13
movl %r15d, %ebp
jmp .L19
.L21:
movslq %r15d, %rdi
leaq 0(%r13,%rdi,4), %rbx
movl 16(%rsp), %edx
addq %rdi, %rdx
leaq 4(%r13,%rdx,4), %r12
.L20:
call rand@PLT
movslq %eax, %rdx
imulq $1431655766, %rdx, %rdx
shrq $32, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
.L22:
addl $1, %ebp
movl 12(%rsp), %eax
addl %eax, %r15d
movl (%rsp), %eax
cmpl %eax, %ebp
je .L42
.L19:
testl %r14d, %r14d
jg .L21
jmp .L22
.L42:
movq %r13, %rbp
movq 40(%rsp), %rbx
movq 48(%rsp), %r12
movq 56(%rsp), %r13
.L18:
testl %r12d, %r12d
jle .L23
movq 24(%rsp), %rax
movl %eax, (%rsp)
movl $0, %ecx
movl $0, %r15d
subl $1, %eax
movl %eax, 12(%rsp)
movq %rbp, 16(%rsp)
movq %r12, 40(%rsp)
movl %r14d, %eax
movl %r15d, %r14d
movq %r13, 48(%rsp)
movq %rbx, %r13
movl %ecx, %ebx
movl %eax, %r15d
jmp .L24
.L26:
movslq %ebx, %rdi
leaq 0(%r13,%rdi,4), %rbp
movl 12(%rsp), %eax
addq %rdi, %rax
leaq 4(%r13,%rax,4), %r12
.L25:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L25
.L27:
addl $1, %r14d
movl (%rsp), %eax
addl %eax, %ebx
cmpl %r15d, %r14d
je .L43
.L24:
cmpl $0, 8(%rsp)
jg .L26
jmp .L27
.L43:
movq 16(%rsp), %rbp
movq %r13, %rbx
movq 40(%rsp), %r12
movq 48(%rsp), %r13
.L23:
salq $32, %r13
movl %r12d, %edi
orq %r13, %rdi
movq %r12, %rax
salq $32, %rax
movq 24(%rsp), %rcx
movl %ecx, %edx
orq %rax, %rdx
movl %ecx, %r8d
orq %r13, %r8
movq 32(%rsp), %r9
movq %rbx, %rcx
movq %rbp, %rsi
call _Z10MatrixMult6MatrixS_S_
movslq %r12d, %r12
leaq 0(,%r12,4), %r14
addq $64, %rbp
movl $16, %r13d
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %r15
movq %rbx, (%rsp)
.L28:
leaq -64(%rbp), %rbx
.L29:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r14, %rbp
subl $1, %r13d
jne .L28
movq (%rsp), %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 24(%rsp), %r12
salq $2, %r12
addq $64, %rbx
movl $16, %r14d
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r15
.L31:
leaq -64(%rbx), %rbp
.L32:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %rbx, %rbp
jne .L32
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbx
subl $1, %r14d
jne .L31
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rbp
addq $64, %rbp
movl $16, %r14d
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r15
.L34:
leaq -64(%rbp), %rbx
.L35:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L35
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r14d
jne .L34
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z14MatrixMultKern6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14MatrixMultKern6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Lab2Matrix.cu
*
* Created on: 29 Feb 2020
* Author: sc01716
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define BLOCK_SIZE 16
// Matrices are stored in row-major order
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__ void MatrixMultKern(const Matrix A, const Matrix B, const Matrix C) {
// Calculate the column index of C and B
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Calculate the row index of C and of A
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row < A.height) && (col < B.width)) {
float Cvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < A.width; ++k) {
Cvalue += A.elements[row * A.width + k]
* B.elements[k * B.width + col];
}
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication -Host Code
//Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatrixMult(const Matrix h_A, const Matrix h_B, Matrix h_C) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Load A and B into device memory
Matrix d_A;
d_A.width = h_A.width;
d_A.height = h_A.height;
size_t size = h_A.width * h_A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, h_A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = h_B.width;
d_B.height = h_B.height;
size = h_B.width * h_B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, h_B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in Device memory
Matrix d_C;
d_C.width = h_C.width;
d_C.height = h_C.height;
size = h_C.width * h_C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke Kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(d_B.width / dimBlock.x, d_A.height / dimBlock.y);
cudaEventRecord(start);
MatrixMultKern<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaEventRecord(stop);
// Read C from Device to Host
cudaMemcpy(h_C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
//printf("Copy h_C off device: %s\n", cudaGetErrorString(err));
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Elapsed time was: %f\n milliseconds", milliseconds);
// Free Device Memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char* argv[]) {
Matrix A, B, C;
// Read Dimensions of A and B
A.height = atoi(argv[1]);
A.width = atoi(argv[2]);
B.height = A.width;
B.width = atoi(argv[3]);
A.elements = (float*) malloc(A.width * A.height * sizeof(float));
B.elements = (float*) malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*) malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = (float) (rand() % 3);
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = (float) (rand() % 2);
MatrixMult(A, B, C);
//printing full matrix
/*
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
*/
//printing only part of the matrix
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
printf("%d ",C.width);
return 0;
} | /* Lab2Matrix.cu
*
* Created on: 29 Feb 2020
* Author: sc01716
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
// Matrices are stored in row-major order
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__ void MatrixMultKern(const Matrix A, const Matrix B, const Matrix C) {
// Calculate the column index of C and B
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Calculate the row index of C and of A
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row < A.height) && (col < B.width)) {
float Cvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < A.width; ++k) {
Cvalue += A.elements[row * A.width + k]
* B.elements[k * B.width + col];
}
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication -Host Code
//Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatrixMult(const Matrix h_A, const Matrix h_B, Matrix h_C) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Load A and B into device memory
Matrix d_A;
d_A.width = h_A.width;
d_A.height = h_A.height;
size_t size = h_A.width * h_A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, h_A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = h_B.width;
d_B.height = h_B.height;
size = h_B.width * h_B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, h_B.elements, size, hipMemcpyHostToDevice);
// Allocate C in Device memory
Matrix d_C;
d_C.width = h_C.width;
d_C.height = h_C.height;
size = h_C.width * h_C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke Kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(d_B.width / dimBlock.x, d_A.height / dimBlock.y);
hipEventRecord(start);
MatrixMultKern<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipEventRecord(stop);
// Read C from Device to Host
hipMemcpy(h_C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
//printf("Copy h_C off device: %s\n", cudaGetErrorString(err));
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Elapsed time was: %f\n milliseconds", milliseconds);
// Free Device Memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char* argv[]) {
Matrix A, B, C;
// Read Dimensions of A and B
A.height = atoi(argv[1]);
A.width = atoi(argv[2]);
B.height = A.width;
B.width = atoi(argv[3]);
A.elements = (float*) malloc(A.width * A.height * sizeof(float));
B.elements = (float*) malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*) malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = (float) (rand() % 3);
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = (float) (rand() % 2);
MatrixMult(A, B, C);
//printing full matrix
/*
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
*/
//printing only part of the matrix
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
printf("%d ",C.width);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Lab2Matrix.cu
*
* Created on: 29 Feb 2020
* Author: sc01716
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
// Matrices are stored in row-major order
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__ void MatrixMultKern(const Matrix A, const Matrix B, const Matrix C) {
// Calculate the column index of C and B
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Calculate the row index of C and of A
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row < A.height) && (col < B.width)) {
float Cvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < A.width; ++k) {
Cvalue += A.elements[row * A.width + k]
* B.elements[k * B.width + col];
}
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication -Host Code
//Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatrixMult(const Matrix h_A, const Matrix h_B, Matrix h_C) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Load A and B into device memory
Matrix d_A;
d_A.width = h_A.width;
d_A.height = h_A.height;
size_t size = h_A.width * h_A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, h_A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = h_B.width;
d_B.height = h_B.height;
size = h_B.width * h_B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, h_B.elements, size, hipMemcpyHostToDevice);
// Allocate C in Device memory
Matrix d_C;
d_C.width = h_C.width;
d_C.height = h_C.height;
size = h_C.width * h_C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke Kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(d_B.width / dimBlock.x, d_A.height / dimBlock.y);
hipEventRecord(start);
MatrixMultKern<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipEventRecord(stop);
// Read C from Device to Host
hipMemcpy(h_C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
//printf("Copy h_C off device: %s\n", cudaGetErrorString(err));
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Elapsed time was: %f\n milliseconds", milliseconds);
// Free Device Memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char* argv[]) {
Matrix A, B, C;
// Read Dimensions of A and B
A.height = atoi(argv[1]);
A.width = atoi(argv[2]);
B.height = A.width;
B.width = atoi(argv[3]);
A.elements = (float*) malloc(A.width * A.height * sizeof(float));
B.elements = (float*) malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*) malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = (float) (rand() % 3);
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = (float) (rand() % 2);
MatrixMult(A, B, C);
//printing full matrix
/*
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
*/
//printing only part of the matrix
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
printf("%d ",C.width);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14MatrixMultKern6MatrixS_S_
.globl _Z14MatrixMultKern6MatrixS_S_
.p2align 8
.type _Z14MatrixMultKern6MatrixS_S_,@function
_Z14MatrixMultKern6MatrixS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x4
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s7, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b64 s[4:5], s[4:5], 0x8
v_mul_lo_u32 v2, v0, s7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s7, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14MatrixMultKern6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14MatrixMultKern6MatrixS_S_, .Lfunc_end0-_Z14MatrixMultKern6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14MatrixMultKern6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14MatrixMultKern6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Lab2Matrix.cu
*
* Created on: 29 Feb 2020
* Author: sc01716
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
// Matrices are stored in row-major order
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__ void MatrixMultKern(const Matrix A, const Matrix B, const Matrix C) {
// Calculate the column index of C and B
int col = blockIdx.x * blockDim.x + threadIdx.x;
// Calculate the row index of C and of A
int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row < A.height) && (col < B.width)) {
float Cvalue = 0;
// each thread computes one element of the block sub-matrix
for (int k = 0; k < A.width; ++k) {
Cvalue += A.elements[row * A.width + k]
* B.elements[k * B.width + col];
}
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication -Host Code
//Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatrixMult(const Matrix h_A, const Matrix h_B, Matrix h_C) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Load A and B into device memory
Matrix d_A;
d_A.width = h_A.width;
d_A.height = h_A.height;
size_t size = h_A.width * h_A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, h_A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = h_B.width;
d_B.height = h_B.height;
size = h_B.width * h_B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, h_B.elements, size, hipMemcpyHostToDevice);
// Allocate C in Device memory
Matrix d_C;
d_C.width = h_C.width;
d_C.height = h_C.height;
size = h_C.width * h_C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke Kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(d_B.width / dimBlock.x, d_A.height / dimBlock.y);
hipEventRecord(start);
MatrixMultKern<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipEventRecord(stop);
// Read C from Device to Host
hipMemcpy(h_C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
//printf("Copy h_C off device: %s\n", cudaGetErrorString(err));
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Elapsed time was: %f\n milliseconds", milliseconds);
// Free Device Memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char* argv[]) {
Matrix A, B, C;
// Read Dimensions of A and B
A.height = atoi(argv[1]);
A.width = atoi(argv[2]);
B.height = A.width;
B.width = atoi(argv[3]);
A.elements = (float*) malloc(A.width * A.height * sizeof(float));
B.elements = (float*) malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*) malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = (float) (rand() % 3);
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = (float) (rand() % 2);
MatrixMult(A, B, C);
//printing full matrix
/*
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
*/
//printing only part of the matrix
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", A.elements[i * A.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", B.elements[i * B.width + j]);
printf("\n");
}
printf("\n");
for (int i = 0; i < 16; i++) {
for (int j = 0; j < 16; j++)
printf("%f ", C.elements[i * C.width + j]);
printf("\n");
}
printf("\n");
printf("%d ",C.width);
return 0;
} | .text
.file "Lab2Test.hip"
.globl _Z29__device_stub__MatrixMultKern6MatrixS_S_ # -- Begin function _Z29__device_stub__MatrixMultKern6MatrixS_S_
.p2align 4, 0x90
.type _Z29__device_stub__MatrixMultKern6MatrixS_S_,@function
_Z29__device_stub__MatrixMultKern6MatrixS_S_: # @_Z29__device_stub__MatrixMultKern6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14MatrixMultKern6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__MatrixMultKern6MatrixS_S_, .Lfunc_end0-_Z29__device_stub__MatrixMultKern6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z10MatrixMult6MatrixS_S_ # -- Begin function _Z10MatrixMult6MatrixS_S_
.p2align 4, 0x90
.type _Z10MatrixMult6MatrixS_S_,@function
_Z10MatrixMult6MatrixS_S_: # @_Z10MatrixMult6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 112(%rsp) # 8-byte Spill
movq %r8, %rbx
movq %rcx, 104(%rsp) # 8-byte Spill
movq %rdx, %r15
movq %rsi, 96(%rsp) # 8-byte Spill
movq %rdi, %r13
movq %rdi, %rbp
shrq $32, %rbp
movq %rdx, %r12
shrq $32, %r12
movq %r8, %r14
shrq $32, %r14
leaq 40(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq %r13, 24(%rsp)
imull %r13d, %ebp
movslq %ebp, %rbp
shlq $2, %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, 8(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
shlq $2, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, 48(%rsp)
imull %ebx, %r14d
movslq %r14d, %r14
shlq $2, %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl 8(%rsp), %eax
shrl $4, %eax
movl 28(%rsp), %r15d
shrl $4, %r15d
shlq $32, %r15
orq %rax, %r15
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 24(%rsp), %xmm0
movups 8(%rsp), %xmm1
movups 48(%rsp), %xmm2
movups %xmm0, 200(%rsp)
movups %xmm1, 184(%rsp)
movups %xmm2, 168(%rsp)
leaq 200(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 168(%rsp), %rax
movq %rax, 80(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14MatrixMultKern6MatrixS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rsi
movq 112(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 64(%rsp)
movq 40(%rsp), %rsi
movq (%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10MatrixMult6MatrixS_S_, .Lfunc_end1-_Z10MatrixMult6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq %rax, %r14
shlq $32, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movl %ebp, %eax
movq %rax, 56(%rsp) # 8-byte Spill
movq %rbp, %rax
shlq $32, %rax
movq %rax, 48(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbp, %rdi
imulq %r14, %rdi
sarq $30, %rdi
callq malloc
movq %rax, %r12
movl %ebp, %eax
imull %ebx, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r15
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %rdi
movq %rbx, 32(%rsp) # 8-byte Spill
imulq %rbx, %rdi
sarq $30, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
movq %rbp, 24(%rsp) # 8-byte Spill
jle .LBB2_6
# %bb.1: # %.preheader94.lr.ph
movl %r13d, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %r13d
xorl %ecx, %ecx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 40(%rsp), %rcx # 8-byte Reload
incq %rcx
movq 24(%rsp), %rbp # 8-byte Reload
movq (%rsp), %rax # 8-byte Reload
addl %ebp, %eax
movq %rax, (%rsp) # 8-byte Spill
cmpq 16(%rsp), %rcx # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movq %rcx, 40(%rsp) # 8-byte Spill
testl %ebp, %ebp
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl (%rsp), %eax # 4-byte Reload
leaq (%r12,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1431655766, %rax, %rcx # imm = 0x55555556
movq %rcx, %rdx
shrq $63, %rdx
shrq $32, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %.preheader93
movq 64(%rsp), %rcx # 8-byte Reload
addq %rcx, 56(%rsp) # 8-byte Folded Spill
movq 8(%rsp), %rax # 8-byte Reload
addq %rax, 48(%rsp) # 8-byte Folded Spill
orq %rcx, %rax
movq %rax, 8(%rsp) # 8-byte Spill
testl %ebp, %ebp
movq 32(%rsp), %rax # 8-byte Reload
jle .LBB2_12
# %bb.7: # %.preheader92.lr.ph
movl 24(%rsp), %ecx # 4-byte Reload
movq %rcx, 16(%rsp) # 8-byte Spill
movl %eax, %r13d
xorl %ecx, %ecx
movq %rcx, (%rsp) # 8-byte Spill
xorl %edx, %edx
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_11: # %._crit_edge99
# in Loop: Header=BB2_8 Depth=1
movq 40(%rsp), %rdx # 8-byte Reload
incq %rdx
movq 32(%rsp), %rax # 8-byte Reload
movq (%rsp), %rcx # 8-byte Reload
addl %eax, %ecx
movq %rcx, (%rsp) # 8-byte Spill
cmpq 16(%rsp), %rdx # 8-byte Folded Reload
je .LBB2_12
.LBB2_8: # %.preheader92
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
movq %rdx, 40(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB2_11
# %bb.9: # %.lr.ph98
# in Loop: Header=BB2_8 Depth=1
movl (%rsp), %eax # 4-byte Reload
leaq (%r15,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB2_10
jmp .LBB2_11
.LBB2_12: # %._crit_edge101
movq 56(%rsp), %rdi # 8-byte Reload
movq %r12, %rsi
movq 48(%rsp), %rdx # 8-byte Reload
movq %r15, %rcx
movq 8(%rsp), %r8 # 8-byte Reload
movq %r14, %r9
callq _Z10MatrixMult6MatrixS_S_
movslq 24(%rsp), %rbx # 4-byte Folded Reload
shlq $2, %rbx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_13: # %.preheader91
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $16, %rbp
jne .LBB2_14
# %bb.15: # in Loop: Header=BB2_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq %rbx, %r12
cmpq $16, %r13
jne .LBB2_13
# %bb.16:
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rbp # 8-byte Reload
movslq %ebp, %rbx
shlq $2, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_17: # %.preheader90
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $16, %r13
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq %rbx, %r15
cmpq $16, %r12
jne .LBB2_17
# %bb.20:
movl $10, %edi
callq putchar@PLT
movslq %ebp, %rbx
shlq $2, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_21: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_22 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_22: # Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $16, %r12
jne .LBB2_22
# %bb.23: # in Loop: Header=BB2_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq %rbx, %r14
cmpq $16, %r15
jne .LBB2_21
# %bb.24:
movl $10, %edi
callq putchar@PLT
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14MatrixMultKern6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14MatrixMultKern6MatrixS_S_,@object # @_Z14MatrixMultKern6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z14MatrixMultKern6MatrixS_S_
.p2align 3, 0x0
_Z14MatrixMultKern6MatrixS_S_:
.quad _Z29__device_stub__MatrixMultKern6MatrixS_S_
.size _Z14MatrixMultKern6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time was: %f\n milliseconds"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14MatrixMultKern6MatrixS_S_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__MatrixMultKern6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14MatrixMultKern6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14MatrixMultKern6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x160], RZ ; /* 0x0000580003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x160], R2 ; /* 0x0000580003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x170], R0 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14MatrixMultKern6MatrixS_S_
.globl _Z14MatrixMultKern6MatrixS_S_
.p2align 8
.type _Z14MatrixMultKern6MatrixS_S_,@function
_Z14MatrixMultKern6MatrixS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x4
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s7, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b64 s[4:5], s[4:5], 0x8
v_mul_lo_u32 v2, v0, s7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s7, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14MatrixMultKern6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14MatrixMultKern6MatrixS_S_, .Lfunc_end0-_Z14MatrixMultKern6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14MatrixMultKern6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14MatrixMultKern6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00193f3f_00000000-6_Lab2Test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
.type _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_, @function
_Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14MatrixMultKern6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_, .-_Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
.globl _Z14MatrixMultKern6MatrixS_S_
.type _Z14MatrixMultKern6MatrixS_S_, @function
_Z14MatrixMultKern6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14MatrixMultKern6MatrixS_S_, .-_Z14MatrixMultKern6MatrixS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Elapsed time was: %f\n milliseconds"
.text
.globl _Z10MatrixMult6MatrixS_S_
.type _Z10MatrixMult6MatrixS_S_, @function
_Z10MatrixMult6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %r14
movq %rsi, 8(%rsp)
movq %rdx, %rbx
movq %rcx, 16(%rsp)
movq %r8, %r13
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, %r12
sarq $32, %r12
movq %rdx, %r15
sarq $32, %r15
movq %r8, %rbp
sarq $32, %rbp
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %r14d, 80(%rsp)
movl %r12d, 84(%rsp)
imull %r14d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 96(%rsp)
movl %r15d, 100(%rsp)
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 112(%rsp)
movl %ebp, 116(%rsp)
imull %r13d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, 64(%rsp)
movl 84(%rsp), %eax
shrl $4, %eax
movl 96(%rsp), %edx
shrl $4, %edx
movl %edx, 68(%rsp)
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 120(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 160(%rsp)
leaq 160(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 160(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
movdqa 112(%rsp), %xmm3
movaps %xmm3, 160(%rsp)
leaq 160(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z43__device_stub__Z14MatrixMultKern6MatrixS_S_RK6MatrixS1_S1_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10MatrixMult6MatrixS_S_, .-_Z10MatrixMult6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.LC4:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, (%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
movl %eax, 8(%rsp)
movl %r13d, %edi
imull %r12d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
movl %r15d, %edi
imull %r12d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r15d, %edi
imull %r13d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
testl %r13d, %r13d
jle .L18
movl %r12d, 12(%rsp)
movl $0, %r15d
leal -1(%r12), %eax
movl %eax, 16(%rsp)
movq %rbx, 40(%rsp)
movq %r12, 48(%rsp)
movq %r13, 56(%rsp)
movq %rbp, %r13
movl %r15d, %ebp
jmp .L19
.L21:
movslq %r15d, %rdi
leaq 0(%r13,%rdi,4), %rbx
movl 16(%rsp), %edx
addq %rdi, %rdx
leaq 4(%r13,%rdx,4), %r12
.L20:
call rand@PLT
movslq %eax, %rdx
imulq $1431655766, %rdx, %rdx
shrq $32, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
.L22:
addl $1, %ebp
movl 12(%rsp), %eax
addl %eax, %r15d
movl (%rsp), %eax
cmpl %eax, %ebp
je .L42
.L19:
testl %r14d, %r14d
jg .L21
jmp .L22
.L42:
movq %r13, %rbp
movq 40(%rsp), %rbx
movq 48(%rsp), %r12
movq 56(%rsp), %r13
.L18:
testl %r12d, %r12d
jle .L23
movq 24(%rsp), %rax
movl %eax, (%rsp)
movl $0, %ecx
movl $0, %r15d
subl $1, %eax
movl %eax, 12(%rsp)
movq %rbp, 16(%rsp)
movq %r12, 40(%rsp)
movl %r14d, %eax
movl %r15d, %r14d
movq %r13, 48(%rsp)
movq %rbx, %r13
movl %ecx, %ebx
movl %eax, %r15d
jmp .L24
.L26:
movslq %ebx, %rdi
leaq 0(%r13,%rdi,4), %rbp
movl 12(%rsp), %eax
addq %rdi, %rax
leaq 4(%r13,%rax,4), %r12
.L25:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L25
.L27:
addl $1, %r14d
movl (%rsp), %eax
addl %eax, %ebx
cmpl %r15d, %r14d
je .L43
.L24:
cmpl $0, 8(%rsp)
jg .L26
jmp .L27
.L43:
movq 16(%rsp), %rbp
movq %r13, %rbx
movq 40(%rsp), %r12
movq 48(%rsp), %r13
.L23:
salq $32, %r13
movl %r12d, %edi
orq %r13, %rdi
movq %r12, %rax
salq $32, %rax
movq 24(%rsp), %rcx
movl %ecx, %edx
orq %rax, %rdx
movl %ecx, %r8d
orq %r13, %r8
movq 32(%rsp), %r9
movq %rbx, %rcx
movq %rbp, %rsi
call _Z10MatrixMult6MatrixS_S_
movslq %r12d, %r12
leaq 0(,%r12,4), %r14
addq $64, %rbp
movl $16, %r13d
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %r15
movq %rbx, (%rsp)
.L28:
leaq -64(%rbp), %rbx
.L29:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r14, %rbp
subl $1, %r13d
jne .L28
movq (%rsp), %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 24(%rsp), %r12
salq $2, %r12
addq $64, %rbx
movl $16, %r14d
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r15
.L31:
leaq -64(%rbx), %rbp
.L32:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %rbx, %rbp
jne .L32
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbx
subl $1, %r14d
jne .L31
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rbp
addq $64, %rbp
movl $16, %r14d
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r15
.L34:
leaq -64(%rbp), %rbx
.L35:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L35
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq %r12, %rbp
subl $1, %r14d
jne .L34
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z14MatrixMultKern6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14MatrixMultKern6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Lab2Test.hip"
.globl _Z29__device_stub__MatrixMultKern6MatrixS_S_ # -- Begin function _Z29__device_stub__MatrixMultKern6MatrixS_S_
.p2align 4, 0x90
.type _Z29__device_stub__MatrixMultKern6MatrixS_S_,@function
_Z29__device_stub__MatrixMultKern6MatrixS_S_: # @_Z29__device_stub__MatrixMultKern6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14MatrixMultKern6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__MatrixMultKern6MatrixS_S_, .Lfunc_end0-_Z29__device_stub__MatrixMultKern6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z10MatrixMult6MatrixS_S_ # -- Begin function _Z10MatrixMult6MatrixS_S_
.p2align 4, 0x90
.type _Z10MatrixMult6MatrixS_S_,@function
_Z10MatrixMult6MatrixS_S_: # @_Z10MatrixMult6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 112(%rsp) # 8-byte Spill
movq %r8, %rbx
movq %rcx, 104(%rsp) # 8-byte Spill
movq %rdx, %r15
movq %rsi, 96(%rsp) # 8-byte Spill
movq %rdi, %r13
movq %rdi, %rbp
shrq $32, %rbp
movq %rdx, %r12
shrq $32, %r12
movq %r8, %r14
shrq $32, %r14
leaq 40(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq %r13, 24(%rsp)
imull %r13d, %ebp
movslq %ebp, %rbp
shlq $2, %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, 8(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
shlq $2, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, 48(%rsp)
imull %ebx, %r14d
movslq %r14d, %r14
shlq $2, %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl 8(%rsp), %eax
shrl $4, %eax
movl 28(%rsp), %r15d
shrl $4, %r15d
shlq $32, %r15
orq %rax, %r15
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 24(%rsp), %xmm0
movups 8(%rsp), %xmm1
movups 48(%rsp), %xmm2
movups %xmm0, 200(%rsp)
movups %xmm1, 184(%rsp)
movups %xmm2, 168(%rsp)
leaq 200(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 168(%rsp), %rax
movq %rax, 80(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14MatrixMultKern6MatrixS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rsi
movq 112(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 64(%rsp)
movq 40(%rsp), %rsi
movq (%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10MatrixMult6MatrixS_S_, .Lfunc_end1-_Z10MatrixMult6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq %rax, %r14
shlq $32, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movl %ebp, %eax
movq %rax, 56(%rsp) # 8-byte Spill
movq %rbp, %rax
shlq $32, %rax
movq %rax, 48(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbp, %rdi
imulq %r14, %rdi
sarq $30, %rdi
callq malloc
movq %rax, %r12
movl %ebp, %eax
imull %ebx, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r15
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %rdi
movq %rbx, 32(%rsp) # 8-byte Spill
imulq %rbx, %rdi
sarq $30, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
movq %rbp, 24(%rsp) # 8-byte Spill
jle .LBB2_6
# %bb.1: # %.preheader94.lr.ph
movl %r13d, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %r13d
xorl %ecx, %ecx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 40(%rsp), %rcx # 8-byte Reload
incq %rcx
movq 24(%rsp), %rbp # 8-byte Reload
movq (%rsp), %rax # 8-byte Reload
addl %ebp, %eax
movq %rax, (%rsp) # 8-byte Spill
cmpq 16(%rsp), %rcx # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movq %rcx, 40(%rsp) # 8-byte Spill
testl %ebp, %ebp
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl (%rsp), %eax # 4-byte Reload
leaq (%r12,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1431655766, %rax, %rcx # imm = 0x55555556
movq %rcx, %rdx
shrq $63, %rdx
shrq $32, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %.preheader93
movq 64(%rsp), %rcx # 8-byte Reload
addq %rcx, 56(%rsp) # 8-byte Folded Spill
movq 8(%rsp), %rax # 8-byte Reload
addq %rax, 48(%rsp) # 8-byte Folded Spill
orq %rcx, %rax
movq %rax, 8(%rsp) # 8-byte Spill
testl %ebp, %ebp
movq 32(%rsp), %rax # 8-byte Reload
jle .LBB2_12
# %bb.7: # %.preheader92.lr.ph
movl 24(%rsp), %ecx # 4-byte Reload
movq %rcx, 16(%rsp) # 8-byte Spill
movl %eax, %r13d
xorl %ecx, %ecx
movq %rcx, (%rsp) # 8-byte Spill
xorl %edx, %edx
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_11: # %._crit_edge99
# in Loop: Header=BB2_8 Depth=1
movq 40(%rsp), %rdx # 8-byte Reload
incq %rdx
movq 32(%rsp), %rax # 8-byte Reload
movq (%rsp), %rcx # 8-byte Reload
addl %eax, %ecx
movq %rcx, (%rsp) # 8-byte Spill
cmpq 16(%rsp), %rdx # 8-byte Folded Reload
je .LBB2_12
.LBB2_8: # %.preheader92
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
movq %rdx, 40(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB2_11
# %bb.9: # %.lr.ph98
# in Loop: Header=BB2_8 Depth=1
movl (%rsp), %eax # 4-byte Reload
leaq (%r15,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB2_10
jmp .LBB2_11
.LBB2_12: # %._crit_edge101
movq 56(%rsp), %rdi # 8-byte Reload
movq %r12, %rsi
movq 48(%rsp), %rdx # 8-byte Reload
movq %r15, %rcx
movq 8(%rsp), %r8 # 8-byte Reload
movq %r14, %r9
callq _Z10MatrixMult6MatrixS_S_
movslq 24(%rsp), %rbx # 4-byte Folded Reload
shlq $2, %rbx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_13: # %.preheader91
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $16, %rbp
jne .LBB2_14
# %bb.15: # in Loop: Header=BB2_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq %rbx, %r12
cmpq $16, %r13
jne .LBB2_13
# %bb.16:
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rbp # 8-byte Reload
movslq %ebp, %rbx
shlq $2, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_17: # %.preheader90
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $16, %r13
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq %rbx, %r15
cmpq $16, %r12
jne .LBB2_17
# %bb.20:
movl $10, %edi
callq putchar@PLT
movslq %ebp, %rbx
shlq $2, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_21: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_22 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_22: # Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $16, %r12
jne .LBB2_22
# %bb.23: # in Loop: Header=BB2_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq %rbx, %r14
cmpq $16, %r15
jne .LBB2_21
# %bb.24:
movl $10, %edi
callq putchar@PLT
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14MatrixMultKern6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14MatrixMultKern6MatrixS_S_,@object # @_Z14MatrixMultKern6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z14MatrixMultKern6MatrixS_S_
.p2align 3, 0x0
_Z14MatrixMultKern6MatrixS_S_:
.quad _Z29__device_stub__MatrixMultKern6MatrixS_S_
.size _Z14MatrixMultKern6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time was: %f\n milliseconds"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14MatrixMultKern6MatrixS_S_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__MatrixMultKern6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14MatrixMultKern6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include"cuda_runtime.h"
#include"device_launch_parameters.h"
#include<stdio.h>
#include<string.h>
__global__ void Toggle(char *a, char *b, int n)
{
int tid;
tid = threadIdx.x;
if(a[tid]>='A' && a[tid]<='Z')
{
b[tid]=a[tid]+32;
}
else
{
b[tid]=a[tid]-32;
}
}
int main()
{
char a[100],b[100];
int i,n,size;
char *d_a, *d_b;
printf("\nEnter the string\n");
scanf("%s",a);
n = strlen(a);
printf("\nNo of charcaters is\t%d", n);
size = sizeof(char);
printf("\nSize is \t%d\n", size);
cudaMalloc((void **)&d_a,n*size);
cudaMalloc((void **)&d_b,n*size);
cudaMemcpy(d_a,a,n*size,cudaMemcpyHostToDevice);
Toggle<<<1,n>>>(d_a,d_b,n);
cudaMemcpy(b,d_b,n*size,cudaMemcpyDeviceToHost);
printf("\nToggled string is \n");
for(i=0;i<n;i++)
printf("%c",b[i]);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z6TogglePcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x001fe40000011404 */
/*0040*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0050*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*0060*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0070*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f3e0ff */
/*0080*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe40000ffe4ff */
/*0090*/ IADD3 R0, R2.reuse, -0x41, RZ ; /* 0xffffffbf02007810 */
/* 0x044fe40007ffe0ff */
/*00a0*/ IADD3 R7, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fe40007ffe0ff */
/*00b0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x1a, PT ; /* 0x0000001a0000780c */
/* 0x000fda0003f06070 */
/*00d0*/ @P0 IADD3 R7, R2, 0xffe0, RZ ; /* 0x0000ffe002070810 */
/* 0x000fca0007ffe0ff */
/*00e0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include"cuda_runtime.h"
#include"device_launch_parameters.h"
#include<stdio.h>
#include<string.h>
__global__ void Toggle(char *a, char *b, int n)
{
int tid;
tid = threadIdx.x;
if(a[tid]>='A' && a[tid]<='Z')
{
b[tid]=a[tid]+32;
}
else
{
b[tid]=a[tid]-32;
}
}
int main()
{
char a[100],b[100];
int i,n,size;
char *d_a, *d_b;
printf("\nEnter the string\n");
scanf("%s",a);
n = strlen(a);
printf("\nNo of charcaters is\t%d", n);
size = sizeof(char);
printf("\nSize is \t%d\n", size);
cudaMalloc((void **)&d_a,n*size);
cudaMalloc((void **)&d_b,n*size);
cudaMemcpy(d_a,a,n*size,cudaMemcpyHostToDevice);
Toggle<<<1,n>>>(d_a,d_b,n);
cudaMemcpy(b,d_b,n*size,cudaMemcpyDeviceToHost);
printf("\nToggled string is \n");
for(i=0;i<n;i++)
printf("%c",b[i]);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | .file "tmpxft_00027763_00000000-6_W7P1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6TogglePcS_iPcS_i
.type _Z28__device_stub__Z6TogglePcS_iPcS_i, @function
_Z28__device_stub__Z6TogglePcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6TogglePcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6TogglePcS_iPcS_i, .-_Z28__device_stub__Z6TogglePcS_iPcS_i
.globl _Z6TogglePcS_i
.type _Z6TogglePcS_i, @function
_Z6TogglePcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6TogglePcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6TogglePcS_i, .-_Z6TogglePcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nEnter the string\n"
.LC1:
.string "%s"
.LC2:
.string "\nNo of charcaters is\t%d"
.LC3:
.string "\nSize is \t%d\n"
.LC4:
.string "\nToggled string is \n"
.LC5:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $280, %rsp
.cfi_def_cfa_offset 320
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %r12
movq %r12, %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %r12, %rdi
call strlen@PLT
movq %rax, %rbp
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebp, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
leaq 160(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L13
leaq 160(%rsp), %rbx
leal -1(%rbp), %eax
leaq 161(%rsp,%rax), %r12
leaq .LC5(%rip), %rbp
.L14:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L14
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z6TogglePcS_iPcS_i
jmp .L12
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6TogglePcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6TogglePcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include"cuda_runtime.h"
#include"device_launch_parameters.h"
#include<stdio.h>
#include<string.h>
__global__ void Toggle(char *a, char *b, int n)
{
int tid;
tid = threadIdx.x;
if(a[tid]>='A' && a[tid]<='Z')
{
b[tid]=a[tid]+32;
}
else
{
b[tid]=a[tid]-32;
}
}
int main()
{
char a[100],b[100];
int i,n,size;
char *d_a, *d_b;
printf("\nEnter the string\n");
scanf("%s",a);
n = strlen(a);
printf("\nNo of charcaters is\t%d", n);
size = sizeof(char);
printf("\nSize is \t%d\n", size);
cudaMalloc((void **)&d_a,n*size);
cudaMalloc((void **)&d_b,n*size);
cudaMemcpy(d_a,a,n*size,cudaMemcpyHostToDevice);
Toggle<<<1,n>>>(d_a,d_b,n);
cudaMemcpy(b,d_b,n*size,cudaMemcpyDeviceToHost);
printf("\nToggled string is \n");
for(i=0;i<n;i++)
printf("%c",b[i]);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | #include"hip/hip_runtime.h"
#include<stdio.h>
#include<string.h>
__global__ void Toggle(char *a, char *b, int n)
{
int tid;
tid = threadIdx.x;
if(a[tid]>='A' && a[tid]<='Z')
{
b[tid]=a[tid]+32;
}
else
{
b[tid]=a[tid]-32;
}
}
int main()
{
char a[100],b[100];
int i,n,size;
char *d_a, *d_b;
printf("\nEnter the string\n");
scanf("%s",a);
n = strlen(a);
printf("\nNo of charcaters is\t%d", n);
size = sizeof(char);
printf("\nSize is \t%d\n", size);
hipMalloc((void **)&d_a,n*size);
hipMalloc((void **)&d_b,n*size);
hipMemcpy(d_a,a,n*size,hipMemcpyHostToDevice);
Toggle<<<1,n>>>(d_a,d_b,n);
hipMemcpy(b,d_b,n*size,hipMemcpyDeviceToHost);
printf("\nToggled string is \n");
for(i=0;i<n;i++)
printf("%c",b[i]);
hipFree(d_a);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include"hip/hip_runtime.h"
#include<stdio.h>
#include<string.h>
__global__ void Toggle(char *a, char *b, int n)
{
int tid;
tid = threadIdx.x;
if(a[tid]>='A' && a[tid]<='Z')
{
b[tid]=a[tid]+32;
}
else
{
b[tid]=a[tid]-32;
}
}
int main()
{
char a[100],b[100];
int i,n,size;
char *d_a, *d_b;
printf("\nEnter the string\n");
scanf("%s",a);
n = strlen(a);
printf("\nNo of charcaters is\t%d", n);
size = sizeof(char);
printf("\nSize is \t%d\n", size);
hipMalloc((void **)&d_a,n*size);
hipMalloc((void **)&d_b,n*size);
hipMemcpy(d_a,a,n*size,hipMemcpyHostToDevice);
Toggle<<<1,n>>>(d_a,d_b,n);
hipMemcpy(b,d_b,n*size,hipMemcpyDeviceToHost);
printf("\nToggled string is \n");
for(i=0;i<n;i++)
printf("%c",b[i]);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6TogglePcS_i
.globl _Z6TogglePcS_i
.p2align 8
.type _Z6TogglePcS_i,@function
_Z6TogglePcS_i:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v1, 0xffbf
v_sub_nc_u16 v3, v1, 32
v_or_b32_e32 v1, 32, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 0xff, v2
v_cmp_gt_u16_e32 vcc_lo, 26, v2
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v1, v3, v1, vcc_lo
global_store_b8 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6TogglePcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6TogglePcS_i, .Lfunc_end0-_Z6TogglePcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6TogglePcS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6TogglePcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include"hip/hip_runtime.h"
#include<stdio.h>
#include<string.h>
__global__ void Toggle(char *a, char *b, int n)
{
int tid;
tid = threadIdx.x;
if(a[tid]>='A' && a[tid]<='Z')
{
b[tid]=a[tid]+32;
}
else
{
b[tid]=a[tid]-32;
}
}
int main()
{
char a[100],b[100];
int i,n,size;
char *d_a, *d_b;
printf("\nEnter the string\n");
scanf("%s",a);
n = strlen(a);
printf("\nNo of charcaters is\t%d", n);
size = sizeof(char);
printf("\nSize is \t%d\n", size);
hipMalloc((void **)&d_a,n*size);
hipMalloc((void **)&d_b,n*size);
hipMemcpy(d_a,a,n*size,hipMemcpyHostToDevice);
Toggle<<<1,n>>>(d_a,d_b,n);
hipMemcpy(b,d_b,n*size,hipMemcpyDeviceToHost);
printf("\nToggled string is \n");
for(i=0;i<n;i++)
printf("%c",b[i]);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.file "W7P1.hip"
.globl _Z21__device_stub__TogglePcS_i # -- Begin function _Z21__device_stub__TogglePcS_i
.p2align 4, 0x90
.type _Z21__device_stub__TogglePcS_i,@function
_Z21__device_stub__TogglePcS_i: # @_Z21__device_stub__TogglePcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6TogglePcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__TogglePcS_i, .Lfunc_end0-_Z21__device_stub__TogglePcS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 208(%rsp), %r15
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %r15, %rdi
callq strlen
movq %rax, %rbx
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
movslq %ebx, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r14d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6TogglePcS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbl 96(%rsp,%r14), %edi
callq putchar@PLT
incq %r14
cmpq %r14, %rbx
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6TogglePcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6TogglePcS_i,@object # @_Z6TogglePcS_i
.section .rodata,"a",@progbits
.globl _Z6TogglePcS_i
.p2align 3, 0x0
_Z6TogglePcS_i:
.quad _Z21__device_stub__TogglePcS_i
.size _Z6TogglePcS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNo of charcaters is\t%d"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nSize is \t%d\n"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6TogglePcS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nEnter the string"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nToggled string is "
.size .Lstr.1, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__TogglePcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6TogglePcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6TogglePcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x001fe40000011404 */
/*0040*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0050*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*0060*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0070*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f3e0ff */
/*0080*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe40000ffe4ff */
/*0090*/ IADD3 R0, R2.reuse, -0x41, RZ ; /* 0xffffffbf02007810 */
/* 0x044fe40007ffe0ff */
/*00a0*/ IADD3 R7, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fe40007ffe0ff */
/*00b0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x1a, PT ; /* 0x0000001a0000780c */
/* 0x000fda0003f06070 */
/*00d0*/ @P0 IADD3 R7, R2, 0xffe0, RZ ; /* 0x0000ffe002070810 */
/* 0x000fca0007ffe0ff */
/*00e0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6TogglePcS_i
.globl _Z6TogglePcS_i
.p2align 8
.type _Z6TogglePcS_i,@function
_Z6TogglePcS_i:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v1, 0xffbf
v_sub_nc_u16 v3, v1, 32
v_or_b32_e32 v1, 32, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 0xff, v2
v_cmp_gt_u16_e32 vcc_lo, 26, v2
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v1, v3, v1, vcc_lo
global_store_b8 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6TogglePcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6TogglePcS_i, .Lfunc_end0-_Z6TogglePcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6TogglePcS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6TogglePcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00027763_00000000-6_W7P1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6TogglePcS_iPcS_i
.type _Z28__device_stub__Z6TogglePcS_iPcS_i, @function
_Z28__device_stub__Z6TogglePcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6TogglePcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6TogglePcS_iPcS_i, .-_Z28__device_stub__Z6TogglePcS_iPcS_i
.globl _Z6TogglePcS_i
.type _Z6TogglePcS_i, @function
_Z6TogglePcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6TogglePcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6TogglePcS_i, .-_Z6TogglePcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nEnter the string\n"
.LC1:
.string "%s"
.LC2:
.string "\nNo of charcaters is\t%d"
.LC3:
.string "\nSize is \t%d\n"
.LC4:
.string "\nToggled string is \n"
.LC5:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $280, %rsp
.cfi_def_cfa_offset 320
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %r12
movq %r12, %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %r12, %rdi
call strlen@PLT
movq %rax, %rbp
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebp, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
leaq 160(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L13
leaq 160(%rsp), %rbx
leal -1(%rbp), %eax
leaq 161(%rsp,%rax), %r12
leaq .LC5(%rip), %rbp
.L14:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L14
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z6TogglePcS_iPcS_i
jmp .L12
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6TogglePcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6TogglePcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "W7P1.hip"
.globl _Z21__device_stub__TogglePcS_i # -- Begin function _Z21__device_stub__TogglePcS_i
.p2align 4, 0x90
.type _Z21__device_stub__TogglePcS_i,@function
_Z21__device_stub__TogglePcS_i: # @_Z21__device_stub__TogglePcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6TogglePcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__TogglePcS_i, .Lfunc_end0-_Z21__device_stub__TogglePcS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 208(%rsp), %r15
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %r15, %rdi
callq strlen
movq %rax, %rbx
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
movslq %ebx, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r14d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6TogglePcS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbl 96(%rsp,%r14), %edi
callq putchar@PLT
incq %r14
cmpq %r14, %rbx
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6TogglePcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6TogglePcS_i,@object # @_Z6TogglePcS_i
.section .rodata,"a",@progbits
.globl _Z6TogglePcS_i
.p2align 3, 0x0
_Z6TogglePcS_i:
.quad _Z21__device_stub__TogglePcS_i
.size _Z6TogglePcS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNo of charcaters is\t%d"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nSize is \t%d\n"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6TogglePcS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nEnter the string"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nToggled string is "
.size .Lstr.1, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__TogglePcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6TogglePcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* A very simple cuda implementation of map
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void map(float* out, float* in, int size);
void startClock(char*);
void stopClock(char*);
void printClock(char*);
int main(int argc, char** argv) {
if (argc < 2) {
printf("Usage: %s #-of-floats\n",argv[0]);
exit(1);
}
int size = atoi(argv[1]);
printf("size = %d\n",size);
cudaDeviceProp props;
cudaGetDeviceProperties(&props,0);
printf("maxThreadsPerBlock = %d\n",props.maxThreadsPerBlock);
printf("maxGridSize[0] = %d\n",props.maxGridSize[0]);
if (size > (long)props.maxThreadsPerBlock*props.maxGridSize[0]) {
fprintf(stderr,"Max size for the large model is %d\n",
props.maxThreadsPerBlock*props.maxGridSize[0]);
exit(1);
}
void *d_in; // device data
void *d_out;
float *h_in; // host data
float *h_out;
cudaMalloc(&d_in,size*sizeof(float));
cudaMalloc(&d_out,size*sizeof(float));
h_in = (float*) malloc(size*sizeof(float));
h_out =(float*) malloc(size*sizeof(float));
for (int i = 0; i < size; i++) {
h_in[i] = i;
}
startClock("copy data to device");
cudaMemcpy(d_in,h_in,size*sizeof(float),cudaMemcpyHostToDevice);
stopClock("copy data to device");
startClock("compute");
// use max threads/block and the required # of blocks
int numBlocks = ceil(1.0*size/props.maxThreadsPerBlock);
map<<<numBlocks,props.maxThreadsPerBlock>>>((float*) d_out,(float*) d_in,size);
cudaThreadSynchronize();
stopClock("compute");
startClock("copy data to host");
cudaMemcpy(h_out,d_out,size*sizeof(float),cudaMemcpyDeviceToHost);
stopClock("copy data to host");
for (int i = 0; i < size; i++) {
printf("%f -> %f\n",h_in[i],h_out[i]);
}
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
printClock("copy data to device");
printClock("compute");
printClock("copy data to host");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* A very simple cuda implementation of map
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void map(float* out, float* in, int size);
void startClock(char*);
void stopClock(char*);
void printClock(char*);
int main(int argc, char** argv) {
if (argc < 2) {
printf("Usage: %s #-of-floats\n",argv[0]);
exit(1);
}
int size = atoi(argv[1]);
printf("size = %d\n",size);
cudaDeviceProp props;
cudaGetDeviceProperties(&props,0);
printf("maxThreadsPerBlock = %d\n",props.maxThreadsPerBlock);
printf("maxGridSize[0] = %d\n",props.maxGridSize[0]);
if (size > (long)props.maxThreadsPerBlock*props.maxGridSize[0]) {
fprintf(stderr,"Max size for the large model is %d\n",
props.maxThreadsPerBlock*props.maxGridSize[0]);
exit(1);
}
void *d_in; // device data
void *d_out;
float *h_in; // host data
float *h_out;
cudaMalloc(&d_in,size*sizeof(float));
cudaMalloc(&d_out,size*sizeof(float));
h_in = (float*) malloc(size*sizeof(float));
h_out =(float*) malloc(size*sizeof(float));
for (int i = 0; i < size; i++) {
h_in[i] = i;
}
startClock("copy data to device");
cudaMemcpy(d_in,h_in,size*sizeof(float),cudaMemcpyHostToDevice);
stopClock("copy data to device");
startClock("compute");
// use max threads/block and the required # of blocks
int numBlocks = ceil(1.0*size/props.maxThreadsPerBlock);
map<<<numBlocks,props.maxThreadsPerBlock>>>((float*) d_out,(float*) d_in,size);
cudaThreadSynchronize();
stopClock("compute");
startClock("copy data to host");
cudaMemcpy(h_out,d_out,size*sizeof(float),cudaMemcpyDeviceToHost);
stopClock("copy data to host");
for (int i = 0; i < size; i++) {
printf("%f -> %f\n",h_in[i],h_out[i]);
}
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
printClock("copy data to device");
printClock("compute");
printClock("copy data to host");
} | .file "tmpxft_000c084d_00000000-6_map-cuda-large.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s #-of-floats\n"
.LC1:
.string "size = %d\n"
.LC2:
.string "maxThreadsPerBlock = %d\n"
.LC3:
.string "maxGridSize[0] = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Max size for the large model is %d\n"
.section .rodata.str1.1
.LC5:
.string "copy data to device"
.LC6:
.string "compute"
.LC10:
.string "copy data to host"
.LC11:
.string "%f -> %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L16
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 368(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 384(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 368(%rsp), %edx
movl 384(%rsp), %ecx
movslq %ebx, %rsi
movslq %edx, %rax
movslq %ecx, %rdi
imulq %rdi, %rax
cmpq %rax, %rsi
jg .L17
movslq %ebx, %r13
salq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L6
leal -1(%rbx), %ecx
movl $0, %eax
.L7:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L7
.L6:
leaq .LC5(%rip), %r15
movq %r15, %rdi
call _Z10startClockPc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r15, %rdi
call _Z9stopClockPc@PLT
leaq .LC6(%rip), %rdi
call _Z10startClockPc@PLT
movl 368(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC12(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L8
cvttsd2siq %xmm0, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC9(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L8:
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
cvttsd2sil %xmm3, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L9:
call cudaThreadSynchronize@PLT
leaq .LC6(%rip), %rdi
call _Z9stopClockPc@PLT
leaq .LC10(%rip), %r14
movq %r14, %rdi
call _Z10startClockPc@PLT
movl $2, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r14, %rdi
call _Z9stopClockPc@PLT
testl %ebx, %ebx
jle .L10
leal -1(%rbx), %r14d
movl $0, %ebx
leaq .LC11(%rip), %r13
.L11:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %r14, %rax
jne .L11
.L10:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC5(%rip), %rdi
call _Z10printClockPc@PLT
leaq .LC6(%rip), %rdi
call _Z10printClockPc@PLT
leaq .LC10(%rip), %rdi
call _Z10printClockPc@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
imull %edx, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
movl %r14d, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z3mapPfS_i@PLT
jmp .L9
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1127219200
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC12:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* A very simple cuda implementation of map
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void map(float* out, float* in, int size);
void startClock(char*);
void stopClock(char*);
void printClock(char*);
int main(int argc, char** argv) {
if (argc < 2) {
printf("Usage: %s #-of-floats\n",argv[0]);
exit(1);
}
int size = atoi(argv[1]);
printf("size = %d\n",size);
cudaDeviceProp props;
cudaGetDeviceProperties(&props,0);
printf("maxThreadsPerBlock = %d\n",props.maxThreadsPerBlock);
printf("maxGridSize[0] = %d\n",props.maxGridSize[0]);
if (size > (long)props.maxThreadsPerBlock*props.maxGridSize[0]) {
fprintf(stderr,"Max size for the large model is %d\n",
props.maxThreadsPerBlock*props.maxGridSize[0]);
exit(1);
}
void *d_in; // device data
void *d_out;
float *h_in; // host data
float *h_out;
cudaMalloc(&d_in,size*sizeof(float));
cudaMalloc(&d_out,size*sizeof(float));
h_in = (float*) malloc(size*sizeof(float));
h_out =(float*) malloc(size*sizeof(float));
for (int i = 0; i < size; i++) {
h_in[i] = i;
}
startClock("copy data to device");
cudaMemcpy(d_in,h_in,size*sizeof(float),cudaMemcpyHostToDevice);
stopClock("copy data to device");
startClock("compute");
// use max threads/block and the required # of blocks
int numBlocks = ceil(1.0*size/props.maxThreadsPerBlock);
map<<<numBlocks,props.maxThreadsPerBlock>>>((float*) d_out,(float*) d_in,size);
cudaThreadSynchronize();
stopClock("compute");
startClock("copy data to host");
cudaMemcpy(h_out,d_out,size*sizeof(float),cudaMemcpyDeviceToHost);
stopClock("copy data to host");
for (int i = 0; i < size; i++) {
printf("%f -> %f\n",h_in[i],h_out[i]);
}
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
printClock("copy data to device");
printClock("compute");
printClock("copy data to host");
} | /*
* A very simple cuda implementation of map
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void map(float* out, float* in, int size);
void startClock(char*);
void stopClock(char*);
void printClock(char*);
int main(int argc, char** argv) {
if (argc < 2) {
printf("Usage: %s #-of-floats\n",argv[0]);
exit(1);
}
int size = atoi(argv[1]);
printf("size = %d\n",size);
hipDeviceProp_t props;
hipGetDeviceProperties(&props,0);
printf("maxThreadsPerBlock = %d\n",props.maxThreadsPerBlock);
printf("maxGridSize[0] = %d\n",props.maxGridSize[0]);
if (size > (long)props.maxThreadsPerBlock*props.maxGridSize[0]) {
fprintf(stderr,"Max size for the large model is %d\n",
props.maxThreadsPerBlock*props.maxGridSize[0]);
exit(1);
}
void *d_in; // device data
void *d_out;
float *h_in; // host data
float *h_out;
hipMalloc(&d_in,size*sizeof(float));
hipMalloc(&d_out,size*sizeof(float));
h_in = (float*) malloc(size*sizeof(float));
h_out =(float*) malloc(size*sizeof(float));
for (int i = 0; i < size; i++) {
h_in[i] = i;
}
startClock("copy data to device");
hipMemcpy(d_in,h_in,size*sizeof(float),hipMemcpyHostToDevice);
stopClock("copy data to device");
startClock("compute");
// use max threads/block and the required # of blocks
int numBlocks = ceil(1.0*size/props.maxThreadsPerBlock);
map<<<numBlocks,props.maxThreadsPerBlock>>>((float*) d_out,(float*) d_in,size);
hipDeviceSynchronize();
stopClock("compute");
startClock("copy data to host");
hipMemcpy(h_out,d_out,size*sizeof(float),hipMemcpyDeviceToHost);
stopClock("copy data to host");
for (int i = 0; i < size; i++) {
printf("%f -> %f\n",h_in[i],h_out[i]);
}
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
printClock("copy data to device");
printClock("compute");
printClock("copy data to host");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* A very simple cuda implementation of map
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void map(float* out, float* in, int size);
void startClock(char*);
void stopClock(char*);
void printClock(char*);
int main(int argc, char** argv) {
if (argc < 2) {
printf("Usage: %s #-of-floats\n",argv[0]);
exit(1);
}
int size = atoi(argv[1]);
printf("size = %d\n",size);
hipDeviceProp_t props;
hipGetDeviceProperties(&props,0);
printf("maxThreadsPerBlock = %d\n",props.maxThreadsPerBlock);
printf("maxGridSize[0] = %d\n",props.maxGridSize[0]);
if (size > (long)props.maxThreadsPerBlock*props.maxGridSize[0]) {
fprintf(stderr,"Max size for the large model is %d\n",
props.maxThreadsPerBlock*props.maxGridSize[0]);
exit(1);
}
void *d_in; // device data
void *d_out;
float *h_in; // host data
float *h_out;
hipMalloc(&d_in,size*sizeof(float));
hipMalloc(&d_out,size*sizeof(float));
h_in = (float*) malloc(size*sizeof(float));
h_out =(float*) malloc(size*sizeof(float));
for (int i = 0; i < size; i++) {
h_in[i] = i;
}
startClock("copy data to device");
hipMemcpy(d_in,h_in,size*sizeof(float),hipMemcpyHostToDevice);
stopClock("copy data to device");
startClock("compute");
// use max threads/block and the required # of blocks
int numBlocks = ceil(1.0*size/props.maxThreadsPerBlock);
map<<<numBlocks,props.maxThreadsPerBlock>>>((float*) d_out,(float*) d_in,size);
hipDeviceSynchronize();
stopClock("compute");
startClock("copy data to host");
hipMemcpy(h_out,d_out,size*sizeof(float),hipMemcpyDeviceToHost);
stopClock("copy data to host");
for (int i = 0; i < size; i++) {
printf("%f -> %f\n",h_in[i],h_out[i]);
}
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
printClock("copy data to device");
printClock("compute");
printClock("copy data to host");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* A very simple cuda implementation of map
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void map(float* out, float* in, int size);
void startClock(char*);
void stopClock(char*);
void printClock(char*);
int main(int argc, char** argv) {
if (argc < 2) {
printf("Usage: %s #-of-floats\n",argv[0]);
exit(1);
}
int size = atoi(argv[1]);
printf("size = %d\n",size);
hipDeviceProp_t props;
hipGetDeviceProperties(&props,0);
printf("maxThreadsPerBlock = %d\n",props.maxThreadsPerBlock);
printf("maxGridSize[0] = %d\n",props.maxGridSize[0]);
if (size > (long)props.maxThreadsPerBlock*props.maxGridSize[0]) {
fprintf(stderr,"Max size for the large model is %d\n",
props.maxThreadsPerBlock*props.maxGridSize[0]);
exit(1);
}
void *d_in; // device data
void *d_out;
float *h_in; // host data
float *h_out;
hipMalloc(&d_in,size*sizeof(float));
hipMalloc(&d_out,size*sizeof(float));
h_in = (float*) malloc(size*sizeof(float));
h_out =(float*) malloc(size*sizeof(float));
for (int i = 0; i < size; i++) {
h_in[i] = i;
}
startClock("copy data to device");
hipMemcpy(d_in,h_in,size*sizeof(float),hipMemcpyHostToDevice);
stopClock("copy data to device");
startClock("compute");
// use max threads/block and the required # of blocks
int numBlocks = ceil(1.0*size/props.maxThreadsPerBlock);
map<<<numBlocks,props.maxThreadsPerBlock>>>((float*) d_out,(float*) d_in,size);
hipDeviceSynchronize();
stopClock("compute");
startClock("copy data to host");
hipMemcpy(h_out,d_out,size*sizeof(float),hipMemcpyDeviceToHost);
stopClock("copy data to host");
for (int i = 0; i < size; i++) {
printf("%f -> %f\n",h_in[i],h_out[i]);
}
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
printClock("copy data to device");
printClock("compute");
printClock("copy data to host");
} | .text
.file "map-cuda-large.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jle .LBB0_11
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 336(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movslq %ebx, %rcx
movslq 336(%rsp), %rax
movslq 352(%rsp), %rdx
movq %rdx, %rsi
imulq %rax, %rsi
cmpq %rcx, %rsi
jl .LBB0_12
# %bb.2:
movq %rbx, %r12
shlq $32, %r12
sarq $30, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_4
.LBB0_5: # %._crit_edge
movl $.L.str.5, %edi
callq _Z10startClockPc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
callq _Z9stopClockPc
movl $.L.str.6, %edi
callq _Z10startClockPc
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
movl 336(%rsp), %r13d
cvtsi2sd %r13d, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %r13
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.6:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl %ebx, %edx
callq _Z18__device_stub__mapPfS_i
.LBB0_7:
callq hipDeviceSynchronize
movl $.L.str.6, %edi
callq _Z9stopClockPc
movl $.L.str.7, %edi
callq _Z10startClockPc
movq (%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %edi
callq _Z9stopClockPc
testl %ebx, %ebx
jle .LBB0_10
# %bb.8: # %.lr.ph42.preheader
movl %ebx, %ebx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_9: # %.lr.ph42
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.8, %edi
movb $2, %al
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB0_9
.LBB0_10: # %._crit_edge43
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str.5, %edi
callq _Z10printClockPc
movl $.L.str.6, %edi
callq _Z10printClockPc
movl $.L.str.7, %edi
callq _Z10printClockPc
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 1536
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB0_12:
movq stderr(%rip), %rdi
imull %eax, %edx
movl $.L.str.4, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s #-of-floats\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "size = %d\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "maxThreadsPerBlock = %d\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "maxGridSize[0] = %d\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Max size for the large model is %d\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "copy data to device"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "compute"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "copy data to host"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f -> %f\n"
.size .L.str.8, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c084d_00000000-6_map-cuda-large.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s #-of-floats\n"
.LC1:
.string "size = %d\n"
.LC2:
.string "maxThreadsPerBlock = %d\n"
.LC3:
.string "maxGridSize[0] = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Max size for the large model is %d\n"
.section .rodata.str1.1
.LC5:
.string "copy data to device"
.LC6:
.string "compute"
.LC10:
.string "copy data to host"
.LC11:
.string "%f -> %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L16
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 368(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 384(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 368(%rsp), %edx
movl 384(%rsp), %ecx
movslq %ebx, %rsi
movslq %edx, %rax
movslq %ecx, %rdi
imulq %rdi, %rax
cmpq %rax, %rsi
jg .L17
movslq %ebx, %r13
salq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L6
leal -1(%rbx), %ecx
movl $0, %eax
.L7:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L7
.L6:
leaq .LC5(%rip), %r15
movq %r15, %rdi
call _Z10startClockPc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r15, %rdi
call _Z9stopClockPc@PLT
leaq .LC6(%rip), %rdi
call _Z10startClockPc@PLT
movl 368(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC12(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L8
cvttsd2siq %xmm0, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC9(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L8:
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
cvttsd2sil %xmm3, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L9:
call cudaThreadSynchronize@PLT
leaq .LC6(%rip), %rdi
call _Z9stopClockPc@PLT
leaq .LC10(%rip), %r14
movq %r14, %rdi
call _Z10startClockPc@PLT
movl $2, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r14, %rdi
call _Z9stopClockPc@PLT
testl %ebx, %ebx
jle .L10
leal -1(%rbx), %r14d
movl $0, %ebx
leaq .LC11(%rip), %r13
.L11:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %r14, %rax
jne .L11
.L10:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC5(%rip), %rdi
call _Z10printClockPc@PLT
leaq .LC6(%rip), %rdi
call _Z10printClockPc@PLT
leaq .LC10(%rip), %rdi
call _Z10printClockPc@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
imull %edx, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
movl %r14d, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z3mapPfS_i@PLT
jmp .L9
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1127219200
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC12:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "map-cuda-large.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jle .LBB0_11
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 336(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movslq %ebx, %rcx
movslq 336(%rsp), %rax
movslq 352(%rsp), %rdx
movq %rdx, %rsi
imulq %rax, %rsi
cmpq %rcx, %rsi
jl .LBB0_12
# %bb.2:
movq %rbx, %r12
shlq $32, %r12
sarq $30, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_4
.LBB0_5: # %._crit_edge
movl $.L.str.5, %edi
callq _Z10startClockPc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
callq _Z9stopClockPc
movl $.L.str.6, %edi
callq _Z10startClockPc
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
movl 336(%rsp), %r13d
cvtsi2sd %r13d, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %r13
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.6:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl %ebx, %edx
callq _Z18__device_stub__mapPfS_i
.LBB0_7:
callq hipDeviceSynchronize
movl $.L.str.6, %edi
callq _Z9stopClockPc
movl $.L.str.7, %edi
callq _Z10startClockPc
movq (%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %edi
callq _Z9stopClockPc
testl %ebx, %ebx
jle .LBB0_10
# %bb.8: # %.lr.ph42.preheader
movl %ebx, %ebx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_9: # %.lr.ph42
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.8, %edi
movb $2, %al
callq printf
incq %r12
cmpq %r12, %rbx
jne .LBB0_9
.LBB0_10: # %._crit_edge43
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str.5, %edi
callq _Z10printClockPc
movl $.L.str.6, %edi
callq _Z10printClockPc
movl $.L.str.7, %edi
callq _Z10printClockPc
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 1536
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB0_12:
movq stderr(%rip), %rdi
imull %eax, %edx
movl $.L.str.4, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s #-of-floats\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "size = %d\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "maxThreadsPerBlock = %d\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "maxGridSize[0] = %d\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Max size for the large model is %d\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "copy data to device"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "compute"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "copy data to host"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f -> %f\n"
.size .L.str.8, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCKS 4
#define THREADSPERBLOCK 4
#define VECSIZE 16
__global__ void vector_add(int *a, int *b, int *c) {
int i = (blockIdx.x * THREADSPERBLOCK) + threadIdx.x;
c[i] = a[i] + b[i];
}
void random_ints(int* a, int n) {
int i;
for (i = 0; i < n; ++i) {
a[i] = rand() % n;
}
}
void show_vector(int* vec, int size) {
for(int i = 0; i < size; i++) {
printf("%d\t", vec[i]);
}
printf("\n");
}
int main(void) {
int vector1[VECSIZE];
int vector2[VECSIZE];
int vector_out[VECSIZE];
int *gpu_vector1, *gpu_vector2, *gpu_vector_out;
int size = sizeof(int) * VECSIZE;
// Allocate space for device copies of a, b, c
cudaMalloc((void **) &gpu_vector1, size);
cudaMalloc((void **) &gpu_vector2, size);
cudaMalloc((void **) &gpu_vector_out, size);
// Populate the input vectors with random integers
random_ints(vector1, VECSIZE);
random_ints(vector2, VECSIZE);
// Copy inputs to device
cudaMemcpy(gpu_vector1, &vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_vector2, &vector2, size, cudaMemcpyHostToDevice);
vector_add<<<BLOCKS, THREADSPERBLOCK>>> (gpu_vector1, gpu_vector2, gpu_vector_out);
// Copy result back to host
cudaMemcpy(&vector_out, gpu_vector_out, size, cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(gpu_vector1);
cudaFree(gpu_vector2);
cudaFree(gpu_vector_out);
show_vector(vector1, VECSIZE);
show_vector(vector2, VECSIZE);
printf("\n");
show_vector(vector_out, VECSIZE);
printf("\n");
return 0;
} | code for sm_80
Function : _Z10vector_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R6, R6, R3, 0x2 ; /* 0x0000000306067211 */
/* 0x001fca00078e10ff */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCKS 4
#define THREADSPERBLOCK 4
#define VECSIZE 16
__global__ void vector_add(int *a, int *b, int *c) {
int i = (blockIdx.x * THREADSPERBLOCK) + threadIdx.x;
c[i] = a[i] + b[i];
}
void random_ints(int* a, int n) {
int i;
for (i = 0; i < n; ++i) {
a[i] = rand() % n;
}
}
void show_vector(int* vec, int size) {
for(int i = 0; i < size; i++) {
printf("%d\t", vec[i]);
}
printf("\n");
}
int main(void) {
int vector1[VECSIZE];
int vector2[VECSIZE];
int vector_out[VECSIZE];
int *gpu_vector1, *gpu_vector2, *gpu_vector_out;
int size = sizeof(int) * VECSIZE;
// Allocate space for device copies of a, b, c
cudaMalloc((void **) &gpu_vector1, size);
cudaMalloc((void **) &gpu_vector2, size);
cudaMalloc((void **) &gpu_vector_out, size);
// Populate the input vectors with random integers
random_ints(vector1, VECSIZE);
random_ints(vector2, VECSIZE);
// Copy inputs to device
cudaMemcpy(gpu_vector1, &vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_vector2, &vector2, size, cudaMemcpyHostToDevice);
vector_add<<<BLOCKS, THREADSPERBLOCK>>> (gpu_vector1, gpu_vector2, gpu_vector_out);
// Copy result back to host
cudaMemcpy(&vector_out, gpu_vector_out, size, cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(gpu_vector1);
cudaFree(gpu_vector2);
cudaFree(gpu_vector_out);
show_vector(vector1, VECSIZE);
show_vector(vector2, VECSIZE);
printf("\n");
show_vector(vector_out, VECSIZE);
printf("\n");
return 0;
} | .file "tmpxft_000061ce_00000000-6_vectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rax
leaq (%rdi,%rax,4), %r12
.L5:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n"
.text
.globl _Z11show_vectorPii
.type _Z11show_vectorPii, @function
_Z11show_vectorPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L12
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11show_vectorPii, .-_Z11show_vectorPii
.globl _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.type _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, @function
_Z34__device_stub__Z10vector_addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, .-_Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.globl _Z10vector_addPiS_S_
.type _Z10vector_addPiS_S_, @function
_Z10vector_addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10vector_addPiS_S_, .-_Z10vector_addPiS_S_
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $264, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rbp
movl $16, %esi
movq %rbp, %rdi
call _Z11random_intsPii
leaq 112(%rsp), %rbx
movl $16, %esi
movq %rbx, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
leaq 176(%rsp), %rbp
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 48(%rsp), %rdi
movl $16, %esi
call _Z11show_vectorPii
leaq 112(%rsp), %rdi
movl $16, %esi
call _Z11show_vectorPii
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbp, %rdi
call _Z11show_vectorPii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10vector_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define BLOCKS 4
#define THREADSPERBLOCK 4
#define VECSIZE 16
__global__ void vector_add(int *a, int *b, int *c) {
int i = (blockIdx.x * THREADSPERBLOCK) + threadIdx.x;
c[i] = a[i] + b[i];
}
void random_ints(int* a, int n) {
int i;
for (i = 0; i < n; ++i) {
a[i] = rand() % n;
}
}
void show_vector(int* vec, int size) {
for(int i = 0; i < size; i++) {
printf("%d\t", vec[i]);
}
printf("\n");
}
int main(void) {
int vector1[VECSIZE];
int vector2[VECSIZE];
int vector_out[VECSIZE];
int *gpu_vector1, *gpu_vector2, *gpu_vector_out;
int size = sizeof(int) * VECSIZE;
// Allocate space for device copies of a, b, c
cudaMalloc((void **) &gpu_vector1, size);
cudaMalloc((void **) &gpu_vector2, size);
cudaMalloc((void **) &gpu_vector_out, size);
// Populate the input vectors with random integers
random_ints(vector1, VECSIZE);
random_ints(vector2, VECSIZE);
// Copy inputs to device
cudaMemcpy(gpu_vector1, &vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_vector2, &vector2, size, cudaMemcpyHostToDevice);
vector_add<<<BLOCKS, THREADSPERBLOCK>>> (gpu_vector1, gpu_vector2, gpu_vector_out);
// Copy result back to host
cudaMemcpy(&vector_out, gpu_vector_out, size, cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(gpu_vector1);
cudaFree(gpu_vector2);
cudaFree(gpu_vector_out);
show_vector(vector1, VECSIZE);
show_vector(vector2, VECSIZE);
printf("\n");
show_vector(vector_out, VECSIZE);
printf("\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 4
#define THREADSPERBLOCK 4
#define VECSIZE 16
__global__ void vector_add(int *a, int *b, int *c) {
int i = (blockIdx.x * THREADSPERBLOCK) + threadIdx.x;
c[i] = a[i] + b[i];
}
void random_ints(int* a, int n) {
int i;
for (i = 0; i < n; ++i) {
a[i] = rand() % n;
}
}
void show_vector(int* vec, int size) {
for(int i = 0; i < size; i++) {
printf("%d\t", vec[i]);
}
printf("\n");
}
int main(void) {
int vector1[VECSIZE];
int vector2[VECSIZE];
int vector_out[VECSIZE];
int *gpu_vector1, *gpu_vector2, *gpu_vector_out;
int size = sizeof(int) * VECSIZE;
// Allocate space for device copies of a, b, c
hipMalloc((void **) &gpu_vector1, size);
hipMalloc((void **) &gpu_vector2, size);
hipMalloc((void **) &gpu_vector_out, size);
// Populate the input vectors with random integers
random_ints(vector1, VECSIZE);
random_ints(vector2, VECSIZE);
// Copy inputs to device
hipMemcpy(gpu_vector1, &vector1, size, hipMemcpyHostToDevice);
hipMemcpy(gpu_vector2, &vector2, size, hipMemcpyHostToDevice);
vector_add<<<BLOCKS, THREADSPERBLOCK>>> (gpu_vector1, gpu_vector2, gpu_vector_out);
// Copy result back to host
hipMemcpy(&vector_out, gpu_vector_out, size, hipMemcpyDeviceToHost);
// Cleanup
hipFree(gpu_vector1);
hipFree(gpu_vector2);
hipFree(gpu_vector_out);
show_vector(vector1, VECSIZE);
show_vector(vector2, VECSIZE);
printf("\n");
show_vector(vector_out, VECSIZE);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 4
#define THREADSPERBLOCK 4
#define VECSIZE 16
__global__ void vector_add(int *a, int *b, int *c) {
int i = (blockIdx.x * THREADSPERBLOCK) + threadIdx.x;
c[i] = a[i] + b[i];
}
void random_ints(int* a, int n) {
int i;
for (i = 0; i < n; ++i) {
a[i] = rand() % n;
}
}
void show_vector(int* vec, int size) {
for(int i = 0; i < size; i++) {
printf("%d\t", vec[i]);
}
printf("\n");
}
int main(void) {
int vector1[VECSIZE];
int vector2[VECSIZE];
int vector_out[VECSIZE];
int *gpu_vector1, *gpu_vector2, *gpu_vector_out;
int size = sizeof(int) * VECSIZE;
// Allocate space for device copies of a, b, c
hipMalloc((void **) &gpu_vector1, size);
hipMalloc((void **) &gpu_vector2, size);
hipMalloc((void **) &gpu_vector_out, size);
// Populate the input vectors with random integers
random_ints(vector1, VECSIZE);
random_ints(vector2, VECSIZE);
// Copy inputs to device
hipMemcpy(gpu_vector1, &vector1, size, hipMemcpyHostToDevice);
hipMemcpy(gpu_vector2, &vector2, size, hipMemcpyHostToDevice);
vector_add<<<BLOCKS, THREADSPERBLOCK>>> (gpu_vector1, gpu_vector2, gpu_vector_out);
// Copy result back to host
hipMemcpy(&vector_out, gpu_vector_out, size, hipMemcpyDeviceToHost);
// Cleanup
hipFree(gpu_vector1);
hipFree(gpu_vector2);
hipFree(gpu_vector_out);
show_vector(vector1, VECSIZE);
show_vector(vector2, VECSIZE);
printf("\n");
show_vector(vector_out, VECSIZE);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPiS_S_
.globl _Z10vector_addPiS_S_
.p2align 8
.type _Z10vector_addPiS_S_,@function
_Z10vector_addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPiS_S_, .Lfunc_end0-_Z10vector_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKS 4
#define THREADSPERBLOCK 4
#define VECSIZE 16
__global__ void vector_add(int *a, int *b, int *c) {
int i = (blockIdx.x * THREADSPERBLOCK) + threadIdx.x;
c[i] = a[i] + b[i];
}
void random_ints(int* a, int n) {
int i;
for (i = 0; i < n; ++i) {
a[i] = rand() % n;
}
}
void show_vector(int* vec, int size) {
for(int i = 0; i < size; i++) {
printf("%d\t", vec[i]);
}
printf("\n");
}
int main(void) {
int vector1[VECSIZE];
int vector2[VECSIZE];
int vector_out[VECSIZE];
int *gpu_vector1, *gpu_vector2, *gpu_vector_out;
int size = sizeof(int) * VECSIZE;
// Allocate space for device copies of a, b, c
hipMalloc((void **) &gpu_vector1, size);
hipMalloc((void **) &gpu_vector2, size);
hipMalloc((void **) &gpu_vector_out, size);
// Populate the input vectors with random integers
random_ints(vector1, VECSIZE);
random_ints(vector2, VECSIZE);
// Copy inputs to device
hipMemcpy(gpu_vector1, &vector1, size, hipMemcpyHostToDevice);
hipMemcpy(gpu_vector2, &vector2, size, hipMemcpyHostToDevice);
vector_add<<<BLOCKS, THREADSPERBLOCK>>> (gpu_vector1, gpu_vector2, gpu_vector_out);
// Copy result back to host
hipMemcpy(&vector_out, gpu_vector_out, size, hipMemcpyDeviceToHost);
// Cleanup
hipFree(gpu_vector1);
hipFree(gpu_vector2);
hipFree(gpu_vector_out);
show_vector(vector1, VECSIZE);
show_vector(vector2, VECSIZE);
printf("\n");
show_vector(vector_out, VECSIZE);
printf("\n");
return 0;
} | .text
.file "vectors.hip"
.globl _Z25__device_stub__vector_addPiS_S_ # -- Begin function _Z25__device_stub__vector_addPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPiS_S_,@function
_Z25__device_stub__vector_addPiS_S_: # @_Z25__device_stub__vector_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPiS_S_, .Lfunc_end0-_Z25__device_stub__vector_addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z11show_vectorPii # -- Begin function _Z11show_vectorPii
.p2align 4, 0x90
.type _Z11show_vectorPii,@function
_Z11show_vectorPii: # @_Z11show_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z11show_vectorPii, .Lfunc_end2-_Z11show_vectorPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-16, %ecx
subl %ecx, %eax
movl %eax, 224(%rsp,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB3_1
# %bb.2: # %.lr.ph.i9.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i9
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-16, %ecx
subl %ecx, %eax
movl %eax, 160(%rsp,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB3_3
# %bb.4: # %_Z11random_intsPii.exit13
movq 16(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
movl 224(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_7
# %bb.8: # %_Z11show_vectorPii.exit
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_9: # %.lr.ph.i18
# =>This Inner Loop Header: Depth=1
movl 160(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_9
# %bb.10: # %_Z11show_vectorPii.exit23
movl $10, %edi
callq putchar@PLT
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_11
# %bb.12: # %_Z11show_vectorPii.exit29
movl $10, %edi
callq putchar@PLT
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPiS_S_,@object # @_Z10vector_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z10vector_addPiS_S_
.p2align 3, 0x0
_Z10vector_addPiS_S_:
.quad _Z25__device_stub__vector_addPiS_S_
.size _Z10vector_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R6, R6, R3, 0x2 ; /* 0x0000000306067211 */
/* 0x001fca00078e10ff */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPiS_S_
.globl _Z10vector_addPiS_S_
.p2align 8
.type _Z10vector_addPiS_S_,@function
_Z10vector_addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPiS_S_, .Lfunc_end0-_Z10vector_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000061ce_00000000-6_vectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rax
leaq (%rdi,%rax,4), %r12
.L5:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n"
.text
.globl _Z11show_vectorPii
.type _Z11show_vectorPii, @function
_Z11show_vectorPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L12
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11show_vectorPii, .-_Z11show_vectorPii
.globl _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.type _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, @function
_Z34__device_stub__Z10vector_addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, .-_Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.globl _Z10vector_addPiS_S_
.type _Z10vector_addPiS_S_, @function
_Z10vector_addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10vector_addPiS_S_, .-_Z10vector_addPiS_S_
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $264, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rbp
movl $16, %esi
movq %rbp, %rdi
call _Z11random_intsPii
leaq 112(%rsp), %rbx
movl $16, %esi
movq %rbx, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
leaq 176(%rsp), %rbp
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 48(%rsp), %rdi
movl $16, %esi
call _Z11show_vectorPii
leaq 112(%rsp), %rdi
movl $16, %esi
call _Z11show_vectorPii
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbp, %rdi
call _Z11show_vectorPii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10vector_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectors.hip"
.globl _Z25__device_stub__vector_addPiS_S_ # -- Begin function _Z25__device_stub__vector_addPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPiS_S_,@function
_Z25__device_stub__vector_addPiS_S_: # @_Z25__device_stub__vector_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPiS_S_, .Lfunc_end0-_Z25__device_stub__vector_addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z11show_vectorPii # -- Begin function _Z11show_vectorPii
.p2align 4, 0x90
.type _Z11show_vectorPii,@function
_Z11show_vectorPii: # @_Z11show_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z11show_vectorPii, .Lfunc_end2-_Z11show_vectorPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-16, %ecx
subl %ecx, %eax
movl %eax, 224(%rsp,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB3_1
# %bb.2: # %.lr.ph.i9.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i9
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-16, %ecx
subl %ecx, %eax
movl %eax, 160(%rsp,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB3_3
# %bb.4: # %_Z11random_intsPii.exit13
movq 16(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
movl 224(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_7
# %bb.8: # %_Z11show_vectorPii.exit
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_9: # %.lr.ph.i18
# =>This Inner Loop Header: Depth=1
movl 160(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_9
# %bb.10: # %_Z11show_vectorPii.exit23
movl $10, %edi
callq putchar@PLT
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_11
# %bb.12: # %_Z11show_vectorPii.exit29
movl $10, %edi
callq putchar@PLT
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPiS_S_,@object # @_Z10vector_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z10vector_addPiS_S_
.p2align 3, 0x0
_Z10vector_addPiS_S_:
.quad _Z25__device_stub__vector_addPiS_S_
.size _Z10vector_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <iostream>
template <class scalar_t>
__global__ void axpy (scalar_t a, scalar_t *x, scalar_t *y)
{
y[threadIdx.x] = a * x[threadIdx.x];
}
template <class scalar_t>
void run_it (scalar_t a, scalar_t *x, scalar_t *y, size_t N)
{
axpy<scalar_t><<<1, N>>> (a, x, y);
}
template void run_it (float a, float *x, float *y, size_t N);
template void run_it (double a, double *x, double *y, size_t N); | code for sm_80
Function : _Z4axpyIdEvT_PS0_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fcc00078e0007 */
/*0050*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0070*/ DMUL R4, R2, c[0x0][0x160] ; /* 0x0000580002047a28 */
/* 0x004e0e0000000000 */
/*0080*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4axpyIfEvT_PS0_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0005 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0005 */
/*0070*/ FMUL R7, R2, c[0x0][0x160] ; /* 0x0000580002077a20 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <iostream>
template <class scalar_t>
__global__ void axpy (scalar_t a, scalar_t *x, scalar_t *y)
{
y[threadIdx.x] = a * x[threadIdx.x];
}
template <class scalar_t>
void run_it (scalar_t a, scalar_t *x, scalar_t *y, size_t N)
{
axpy<scalar_t><<<1, N>>> (a, x, y);
}
template void run_it (float a, float *x, float *y, size_t N);
template void run_it (double a, double *x, double *y, size_t N); | .file "tmpxft_00113be1_00000000-6_axpy_cuda_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_, @function
_ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_:
.LFB3696:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyIfEvT_PS0_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_, .-_ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_
.section .text._Z4axpyIfEvT_PS0_S1_,"axG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.weak _Z4axpyIfEvT_PS0_S1_
.type _Z4axpyIfEvT_PS0_S1_, @function
_Z4axpyIfEvT_PS0_S1_:
.LFB4003:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4003:
.size _Z4axpyIfEvT_PS0_S1_, .-_Z4axpyIfEvT_PS0_S1_
.text
.type _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_, @function
_ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_:
.LFB3698:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 24(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyIdEvT_PS0_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_, .-_ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_
.section .text._Z4axpyIdEvT_PS0_S1_,"axG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.weak _Z4axpyIdEvT_PS0_S1_
.type _Z4axpyIdEvT_PS0_S1_, @function
_Z4axpyIdEvT_PS0_S1_:
.LFB4005:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4005:
.size _Z4axpyIdEvT_PS0_S1_, .-_Z4axpyIdEvT_PS0_S1_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._Z6run_itIfEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIfEvT_PS0_S1_m,comdat
.weak _Z6run_itIfEvT_PS0_S1_m
.type _Z6run_itIfEvT_PS0_S1_m, @function
_Z6run_itIfEvT_PS0_S1_m:
.LFB4001:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
movss 12(%rsp), %xmm0
call _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_
jmp .L19
.cfi_endproc
.LFE4001:
.size _Z6run_itIfEvT_PS0_S1_m, .-_Z6run_itIfEvT_PS0_S1_m
.section .text._Z6run_itIdEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIdEvT_PS0_S1_m,comdat
.weak _Z6run_itIdEvT_PS0_S1_m
.type _Z6run_itIdEvT_PS0_S1_m, @function
_Z6run_itIdEvT_PS0_S1_m:
.LFB4002:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movsd %xmm0, 8(%rsp)
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
movsd 8(%rsp), %xmm0
call _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_
jmp .L23
.cfi_endproc
.LFE4002:
.size _Z6run_itIdEvT_PS0_S1_m, .-_Z6run_itIdEvT_PS0_S1_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4axpyIdEvT_PS0_S1_"
.LC1:
.string "_Z4axpyIfEvT_PS0_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyIdEvT_PS0_S1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyIfEvT_PS0_S1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <iostream>
template <class scalar_t>
__global__ void axpy (scalar_t a, scalar_t *x, scalar_t *y)
{
y[threadIdx.x] = a * x[threadIdx.x];
}
template <class scalar_t>
void run_it (scalar_t a, scalar_t *x, scalar_t *y, size_t N)
{
axpy<scalar_t><<<1, N>>> (a, x, y);
}
template void run_it (float a, float *x, float *y, size_t N);
template void run_it (double a, double *x, double *y, size_t N); | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
template <class scalar_t>
__global__ void axpy (scalar_t a, scalar_t *x, scalar_t *y)
{
y[threadIdx.x] = a * x[threadIdx.x];
}
template <class scalar_t>
void run_it (scalar_t a, scalar_t *x, scalar_t *y, size_t N)
{
axpy<scalar_t><<<1, N>>> (a, x, y);
}
template void run_it (float a, float *x, float *y, size_t N);
template void run_it (double a, double *x, double *y, size_t N); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
template <class scalar_t>
__global__ void axpy (scalar_t a, scalar_t *x, scalar_t *y)
{
y[threadIdx.x] = a * x[threadIdx.x];
}
template <class scalar_t>
void run_it (scalar_t a, scalar_t *x, scalar_t *y, size_t N)
{
axpy<scalar_t><<<1, N>>> (a, x, y);
}
template void run_it (float a, float *x, float *y, size_t N);
template void run_it (double a, double *x, double *y, size_t N); | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z4axpyIfEvT_PS0_S1_,"axG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.protected _Z4axpyIfEvT_PS0_S1_
.globl _Z4axpyIfEvT_PS0_S1_
.p2align 8
.type _Z4axpyIfEvT_PS0_S1_,@function
_Z4axpyIfEvT_PS0_S1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, s0, v1
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyIfEvT_PS0_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4axpyIfEvT_PS0_S1_,"axG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.Lfunc_end0:
.size _Z4axpyIfEvT_PS0_S1_, .Lfunc_end0-_Z4axpyIfEvT_PS0_S1_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z4axpyIdEvT_PS0_S1_,"axG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.protected _Z4axpyIdEvT_PS0_S1_
.globl _Z4axpyIdEvT_PS0_S1_
.p2align 8
.type _Z4axpyIdEvT_PS0_S1_,@function
_Z4axpyIdEvT_PS0_S1_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v2, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[0:1], s[4:5]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyIdEvT_PS0_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4axpyIdEvT_PS0_S1_,"axG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.Lfunc_end1:
.size _Z4axpyIdEvT_PS0_S1_, .Lfunc_end1-_Z4axpyIdEvT_PS0_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyIfEvT_PS0_S1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z4axpyIfEvT_PS0_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyIdEvT_PS0_S1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z4axpyIdEvT_PS0_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
template <class scalar_t>
__global__ void axpy (scalar_t a, scalar_t *x, scalar_t *y)
{
y[threadIdx.x] = a * x[threadIdx.x];
}
template <class scalar_t>
void run_it (scalar_t a, scalar_t *x, scalar_t *y, size_t N)
{
axpy<scalar_t><<<1, N>>> (a, x, y);
}
template void run_it (float a, float *x, float *y, size_t N);
template void run_it (double a, double *x, double *y, size_t N); | .text
.file "axpy_cuda_kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .text._Z6run_itIfEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIfEvT_PS0_S1_m,comdat
.weak _Z6run_itIfEvT_PS0_S1_m # -- Begin function _Z6run_itIfEvT_PS0_S1_m
.p2align 4, 0x90
.type _Z6run_itIfEvT_PS0_S1_m,@function
_Z6run_itIfEvT_PS0_S1_m: # @_Z6run_itIfEvT_PS0_S1_m
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %edx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIfEvT_PS0_S1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6run_itIfEvT_PS0_S1_m, .Lfunc_end0-_Z6run_itIfEvT_PS0_S1_m
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__axpyIfEvT_PS0_S1_,"axG",@progbits,_Z19__device_stub__axpyIfEvT_PS0_S1_,comdat
.weak _Z19__device_stub__axpyIfEvT_PS0_S1_ # -- Begin function _Z19__device_stub__axpyIfEvT_PS0_S1_
.p2align 4, 0x90
.type _Z19__device_stub__axpyIfEvT_PS0_S1_,@function
_Z19__device_stub__axpyIfEvT_PS0_S1_: # @_Z19__device_stub__axpyIfEvT_PS0_S1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIfEvT_PS0_S1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z19__device_stub__axpyIfEvT_PS0_S1_, .Lfunc_end1-_Z19__device_stub__axpyIfEvT_PS0_S1_
.cfi_endproc
# -- End function
.section .text._Z6run_itIdEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIdEvT_PS0_S1_m,comdat
.weak _Z6run_itIdEvT_PS0_S1_m # -- Begin function _Z6run_itIdEvT_PS0_S1_m
.p2align 4, 0x90
.type _Z6run_itIdEvT_PS0_S1_m,@function
_Z6run_itIdEvT_PS0_S1_m: # @_Z6run_itIdEvT_PS0_S1_m
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movsd %xmm0, (%rsp) # 8-byte Spill
movl %edx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIdEvT_PS0_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6run_itIdEvT_PS0_S1_m, .Lfunc_end2-_Z6run_itIdEvT_PS0_S1_m
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__axpyIdEvT_PS0_S1_,"axG",@progbits,_Z19__device_stub__axpyIdEvT_PS0_S1_,comdat
.weak _Z19__device_stub__axpyIdEvT_PS0_S1_ # -- Begin function _Z19__device_stub__axpyIdEvT_PS0_S1_
.p2align 4, 0x90
.type _Z19__device_stub__axpyIdEvT_PS0_S1_,@function
_Z19__device_stub__axpyIdEvT_PS0_S1_: # @_Z19__device_stub__axpyIdEvT_PS0_S1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movq %rsi, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIdEvT_PS0_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z19__device_stub__axpyIdEvT_PS0_S1_, .Lfunc_end3-_Z19__device_stub__axpyIdEvT_PS0_S1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyIfEvT_PS0_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyIdEvT_PS0_S1_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4axpyIfEvT_PS0_S1_,@object # @_Z4axpyIfEvT_PS0_S1_
.section .rodata._Z4axpyIfEvT_PS0_S1_,"aG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.weak _Z4axpyIfEvT_PS0_S1_
.p2align 3, 0x0
_Z4axpyIfEvT_PS0_S1_:
.quad _Z19__device_stub__axpyIfEvT_PS0_S1_
.size _Z4axpyIfEvT_PS0_S1_, 8
.type _Z4axpyIdEvT_PS0_S1_,@object # @_Z4axpyIdEvT_PS0_S1_
.section .rodata._Z4axpyIdEvT_PS0_S1_,"aG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.weak _Z4axpyIdEvT_PS0_S1_
.p2align 3, 0x0
_Z4axpyIdEvT_PS0_S1_:
.quad _Z19__device_stub__axpyIdEvT_PS0_S1_
.size _Z4axpyIdEvT_PS0_S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4axpyIfEvT_PS0_S1_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4axpyIdEvT_PS0_S1_"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyIfEvT_PS0_S1_
.addrsig_sym _Z19__device_stub__axpyIdEvT_PS0_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4axpyIfEvT_PS0_S1_
.addrsig_sym _Z4axpyIdEvT_PS0_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4axpyIdEvT_PS0_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fcc00078e0007 */
/*0050*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0070*/ DMUL R4, R2, c[0x0][0x160] ; /* 0x0000580002047a28 */
/* 0x004e0e0000000000 */
/*0080*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4axpyIfEvT_PS0_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0005 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0005 */
/*0070*/ FMUL R7, R2, c[0x0][0x160] ; /* 0x0000580002077a20 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z4axpyIfEvT_PS0_S1_,"axG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.protected _Z4axpyIfEvT_PS0_S1_
.globl _Z4axpyIfEvT_PS0_S1_
.p2align 8
.type _Z4axpyIfEvT_PS0_S1_,@function
_Z4axpyIfEvT_PS0_S1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, s0, v1
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyIfEvT_PS0_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4axpyIfEvT_PS0_S1_,"axG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.Lfunc_end0:
.size _Z4axpyIfEvT_PS0_S1_, .Lfunc_end0-_Z4axpyIfEvT_PS0_S1_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z4axpyIdEvT_PS0_S1_,"axG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.protected _Z4axpyIdEvT_PS0_S1_
.globl _Z4axpyIdEvT_PS0_S1_
.p2align 8
.type _Z4axpyIdEvT_PS0_S1_,@function
_Z4axpyIdEvT_PS0_S1_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v2, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[0:1], s[4:5]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyIdEvT_PS0_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4axpyIdEvT_PS0_S1_,"axG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.Lfunc_end1:
.size _Z4axpyIdEvT_PS0_S1_, .Lfunc_end1-_Z4axpyIdEvT_PS0_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyIfEvT_PS0_S1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z4axpyIfEvT_PS0_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyIdEvT_PS0_S1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z4axpyIdEvT_PS0_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00113be1_00000000-6_axpy_cuda_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_, @function
_ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_:
.LFB3696:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyIfEvT_PS0_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_, .-_ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_
.section .text._Z4axpyIfEvT_PS0_S1_,"axG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.weak _Z4axpyIfEvT_PS0_S1_
.type _Z4axpyIfEvT_PS0_S1_, @function
_Z4axpyIfEvT_PS0_S1_:
.LFB4003:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4003:
.size _Z4axpyIfEvT_PS0_S1_, .-_Z4axpyIfEvT_PS0_S1_
.text
.type _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_, @function
_ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_:
.LFB3698:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 24(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyIdEvT_PS0_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_, .-_ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_
.section .text._Z4axpyIdEvT_PS0_S1_,"axG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.weak _Z4axpyIdEvT_PS0_S1_
.type _Z4axpyIdEvT_PS0_S1_, @function
_Z4axpyIdEvT_PS0_S1_:
.LFB4005:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4005:
.size _Z4axpyIdEvT_PS0_S1_, .-_Z4axpyIdEvT_PS0_S1_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._Z6run_itIfEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIfEvT_PS0_S1_m,comdat
.weak _Z6run_itIfEvT_PS0_S1_m
.type _Z6run_itIfEvT_PS0_S1_m, @function
_Z6run_itIfEvT_PS0_S1_m:
.LFB4001:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
movss 12(%rsp), %xmm0
call _ZL34__device_stub__Z4axpyIfEvT_PS0_S1_fPfS_
jmp .L19
.cfi_endproc
.LFE4001:
.size _Z6run_itIfEvT_PS0_S1_m, .-_Z6run_itIfEvT_PS0_S1_m
.section .text._Z6run_itIdEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIdEvT_PS0_S1_m,comdat
.weak _Z6run_itIdEvT_PS0_S1_m
.type _Z6run_itIdEvT_PS0_S1_m, @function
_Z6run_itIdEvT_PS0_S1_m:
.LFB4002:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movsd %xmm0, 8(%rsp)
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
movsd 8(%rsp), %xmm0
call _ZL34__device_stub__Z4axpyIdEvT_PS0_S1_dPdS_
jmp .L23
.cfi_endproc
.LFE4002:
.size _Z6run_itIdEvT_PS0_S1_m, .-_Z6run_itIdEvT_PS0_S1_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4axpyIdEvT_PS0_S1_"
.LC1:
.string "_Z4axpyIfEvT_PS0_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyIdEvT_PS0_S1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyIfEvT_PS0_S1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "axpy_cuda_kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .text._Z6run_itIfEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIfEvT_PS0_S1_m,comdat
.weak _Z6run_itIfEvT_PS0_S1_m # -- Begin function _Z6run_itIfEvT_PS0_S1_m
.p2align 4, 0x90
.type _Z6run_itIfEvT_PS0_S1_m,@function
_Z6run_itIfEvT_PS0_S1_m: # @_Z6run_itIfEvT_PS0_S1_m
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %edx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIfEvT_PS0_S1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6run_itIfEvT_PS0_S1_m, .Lfunc_end0-_Z6run_itIfEvT_PS0_S1_m
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__axpyIfEvT_PS0_S1_,"axG",@progbits,_Z19__device_stub__axpyIfEvT_PS0_S1_,comdat
.weak _Z19__device_stub__axpyIfEvT_PS0_S1_ # -- Begin function _Z19__device_stub__axpyIfEvT_PS0_S1_
.p2align 4, 0x90
.type _Z19__device_stub__axpyIfEvT_PS0_S1_,@function
_Z19__device_stub__axpyIfEvT_PS0_S1_: # @_Z19__device_stub__axpyIfEvT_PS0_S1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIfEvT_PS0_S1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z19__device_stub__axpyIfEvT_PS0_S1_, .Lfunc_end1-_Z19__device_stub__axpyIfEvT_PS0_S1_
.cfi_endproc
# -- End function
.section .text._Z6run_itIdEvT_PS0_S1_m,"axG",@progbits,_Z6run_itIdEvT_PS0_S1_m,comdat
.weak _Z6run_itIdEvT_PS0_S1_m # -- Begin function _Z6run_itIdEvT_PS0_S1_m
.p2align 4, 0x90
.type _Z6run_itIdEvT_PS0_S1_m,@function
_Z6run_itIdEvT_PS0_S1_m: # @_Z6run_itIdEvT_PS0_S1_m
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movsd %xmm0, (%rsp) # 8-byte Spill
movl %edx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIdEvT_PS0_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6run_itIdEvT_PS0_S1_m, .Lfunc_end2-_Z6run_itIdEvT_PS0_S1_m
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__axpyIdEvT_PS0_S1_,"axG",@progbits,_Z19__device_stub__axpyIdEvT_PS0_S1_,comdat
.weak _Z19__device_stub__axpyIdEvT_PS0_S1_ # -- Begin function _Z19__device_stub__axpyIdEvT_PS0_S1_
.p2align 4, 0x90
.type _Z19__device_stub__axpyIdEvT_PS0_S1_,@function
_Z19__device_stub__axpyIdEvT_PS0_S1_: # @_Z19__device_stub__axpyIdEvT_PS0_S1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movq %rsi, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyIdEvT_PS0_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z19__device_stub__axpyIdEvT_PS0_S1_, .Lfunc_end3-_Z19__device_stub__axpyIdEvT_PS0_S1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyIfEvT_PS0_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyIdEvT_PS0_S1_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4axpyIfEvT_PS0_S1_,@object # @_Z4axpyIfEvT_PS0_S1_
.section .rodata._Z4axpyIfEvT_PS0_S1_,"aG",@progbits,_Z4axpyIfEvT_PS0_S1_,comdat
.weak _Z4axpyIfEvT_PS0_S1_
.p2align 3, 0x0
_Z4axpyIfEvT_PS0_S1_:
.quad _Z19__device_stub__axpyIfEvT_PS0_S1_
.size _Z4axpyIfEvT_PS0_S1_, 8
.type _Z4axpyIdEvT_PS0_S1_,@object # @_Z4axpyIdEvT_PS0_S1_
.section .rodata._Z4axpyIdEvT_PS0_S1_,"aG",@progbits,_Z4axpyIdEvT_PS0_S1_,comdat
.weak _Z4axpyIdEvT_PS0_S1_
.p2align 3, 0x0
_Z4axpyIdEvT_PS0_S1_:
.quad _Z19__device_stub__axpyIdEvT_PS0_S1_
.size _Z4axpyIdEvT_PS0_S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4axpyIfEvT_PS0_S1_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4axpyIdEvT_PS0_S1_"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyIfEvT_PS0_S1_
.addrsig_sym _Z19__device_stub__axpyIdEvT_PS0_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4axpyIfEvT_PS0_S1_
.addrsig_sym _Z4axpyIdEvT_PS0_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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