system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mat_multPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R2, R5, c[0x0][0x4], R2 ; /* 0x0000010005027a24 */
/* 0x001fca00078e0202 */
/*0080*/ LEA R7, R2, R2, 0x2 ; /* 0x0000000202077211 */
/* 0x000fe200078e10ff */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R7, R16, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0210 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R16, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0210 */
/*00c0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140404087981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000f28000c1e1900 */
/*0120*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000f68000c1e1900 */
/*0130*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R14, [R4.64+0x50] ; /* 0x00005004040e7981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000f62000c1e1900 */
/*0160*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x000fe20007ffe0ff */
/*0170*/ FFMA R6, R6, R9, RZ ; /* 0x0000000906067223 */
/* 0x004fc800000000ff */
/*0180*/ FFMA R6, R11, R8, R6 ; /* 0x000000080b067223 */
/* 0x008fc80000000006 */
/*0190*/ FFMA R6, R13, R10, R6 ; /* 0x0000000a0d067223 */
/* 0x010fc80000000006 */
/*01a0*/ FFMA R12, R15, R12, R6 ; /* 0x0000000c0f0c7223 */
/* 0x020fe40000000006 */
/*01b0*/ IMAD.WIDE R6, R7, R16, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fc800078e0210 */
/*01c0*/ FFMA R17, R17, R14, R12 ; /* 0x0000000e11117223 */
/* 0x000fca000000000c */
/*01d0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_
.globl _Z7mat_addPfS_S_
.p2align 8
.type _Z7mat_addPfS_S_,@function
_Z7mat_addPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v2, 2, v2
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_, .Lfunc_end0-_Z7mat_addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 8
.type _Z7mat_subPfS_S_,@function
_Z7mat_subPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v2, 2, v2
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_, .Lfunc_end1-_Z7mat_subPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8mat_multPfS_S_
.globl _Z8mat_multPfS_S_
.p2align 8
.type _Z8mat_multPfS_S_,@function
_Z8mat_multPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v1, 2, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
v_add_co_u32 v3, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_1:
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s2, v2
s_add_i32 s2, s2, 5
s_cmp_eq_u32 s2, 25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v7, v5
s_cbranch_scc0 .LBB2_1
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, 5, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8mat_multPfS_S_, .Lfunc_end2-_Z8mat_multPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8mat_multPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00002f99_00000000-6_matrix_math.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7initMatPf
.type _Z7initMatPf, @function
_Z7initMatPf:
.LFB3669:
.cfi_startproc
endbr64
movl $25, %ecx
.L4:
leal -25(%rcx), %eax
movq %rdi, %rdx
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
addl $5, %eax
addq $20, %rdx
cmpl %ecx, %eax
jne .L5
addq $4, %rdi
addl $1, %ecx
cmpl $30, %ecx
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z7initMatPf, .-_Z7initMatPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z8printResv
.type _Z8printResv, @function
_Z8printResv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $20, %ebp
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %r13
jmp .L13
.L18:
call _ZSt16__throw_bad_castv@PLT
.L10:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L11:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq -20(%rbp), %rbx
.L12:
movq res(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addq $20, %rbp
cmpq $120, %rbp
je .L17
.L13:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L18
cmpb $0, 56(%rbx)
je .L10
movzbl 67(%rbx), %esi
jmp .L11
.L17:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z8printResv, .-_Z8printResv
.globl _Z14mat_add_serialPfS_S_
.type _Z14mat_add_serialPfS_S_, @function
_Z14mat_add_serialPfS_S_:
.LFB3671:
.cfi_startproc
endbr64
movl $0, %eax
.L20:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L20
ret
.cfi_endproc
.LFE3671:
.size _Z14mat_add_serialPfS_S_, .-_Z14mat_add_serialPfS_S_
.globl _Z14mat_sub_serialPfS_S_
.type _Z14mat_sub_serialPfS_S_, @function
_Z14mat_sub_serialPfS_S_:
.LFB3672:
.cfi_startproc
endbr64
movl $0, %eax
.L23:
movss (%rdi,%rax), %xmm0
subss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L23
ret
.cfi_endproc
.LFE3672:
.size _Z14mat_sub_serialPfS_S_, .-_Z14mat_sub_serialPfS_S_
.globl _Z15mat_mult_serialPfS_S_
.type _Z15mat_mult_serialPfS_S_, @function
_Z15mat_mult_serialPfS_S_:
.LFB3673:
.cfi_startproc
endbr64
leaq 100(%rdx), %r10
.L26:
leaq 100(%rsi), %r8
movl $0, %r9d
.L30:
leaq -100(%r8), %rax
movq %rdi, %rcx
pxor %xmm1, %xmm1
.L27:
movss (%rcx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq $20, %rax
cmpq %r8, %rax
jne .L27
movss %xmm1, (%rdx,%r9,4)
addq $1, %r9
addq $4, %r8
cmpq $5, %r9
jne .L30
addq $20, %rdx
addq $20, %rdi
cmpq %r10, %rdx
jne .L26
ret
.cfi_endproc
.LFE3673:
.size _Z15mat_mult_serialPfS_S_, .-_Z15mat_mult_serialPfS_S_
.globl _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_addPfS_S_PfS_S_:
.LFB3699:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.globl _Z7mat_addPfS_S_
.type _Z7mat_addPfS_S_, @function
_Z7mat_addPfS_S_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z7mat_addPfS_S_, .-_Z7mat_addPfS_S_
.globl _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_subPfS_S_PfS_S_:
.LFB3701:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_subPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.globl _Z7mat_subPfS_S_
.type _Z7mat_subPfS_S_, @function
_Z7mat_subPfS_S_:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z7mat_subPfS_S_, .-_Z7mat_subPfS_S_
.globl _Z31__device_stub__Z8mat_multPfS_S_PfS_S_
.type _Z31__device_stub__Z8mat_multPfS_S_PfS_S_, @function
_Z31__device_stub__Z8mat_multPfS_S_PfS_S_:
.LFB3703:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mat_multPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z31__device_stub__Z8mat_multPfS_S_PfS_S_, .-_Z31__device_stub__Z8mat_multPfS_S_PfS_S_
.globl _Z8mat_multPfS_S_
.type _Z8mat_multPfS_S_, @function
_Z8mat_multPfS_S_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8mat_multPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z8mat_multPfS_S_, .-_Z8mat_multPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "###########parallel mat_add test######## "
.align 8
.LC3:
.string "###########parallel mat_mul test######## "
.align 8
.LC4:
.string "###########serial mat_add test######## "
.align 8
.LC5:
.string "###########serial mat_mul test######## "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $100, %esi
leaq dev_matA(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq dev_matB(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq dev_res(%rip), %rdi
call cudaMalloc@PLT
movq matA(%rip), %rdi
call _Z7initMatPf
movq matB(%rip), %rdi
call _Z7initMatPf
movl $1, %ecx
movl $100, %edx
movq matA(%rip), %rsi
movq dev_matA(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq matB(%rip), %rsi
movq dev_matB(%rip), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $16, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L57:
movl $2, %ecx
movl $100, %edx
movq dev_res(%rip), %rsi
movq res(%rip), %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L58:
movl $2, %ecx
movl $100, %edx
movq dev_res(%rip), %rsi
movq res(%rip), %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L59:
movl $2, %ecx
movl $100, %edx
movq dev_res(%rip), %rsi
movq res(%rip), %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movq res(%rip), %rdx
movq matB(%rip), %rsi
movq matA(%rip), %rdi
call _Z14mat_add_serialPfS_S_
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movq res(%rip), %rdx
movq matB(%rip), %rsi
movq matA(%rip), %rdi
call _Z14mat_sub_serialPfS_S_
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movq res(%rip), %rdx
movq matB(%rip), %rsi
movq matA(%rip), %rdi
call _Z15mat_mult_serialPfS_S_
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq dev_res(%rip), %rdx
movq dev_matB(%rip), %rsi
movq dev_matA(%rip), %rdi
call _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
jmp .L57
.L63:
movq dev_res(%rip), %rdx
movq dev_matB(%rip), %rsi
movq dev_matA(%rip), %rdi
call _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
jmp .L58
.L64:
movq dev_res(%rip), %rdx
movq dev_matB(%rip), %rsi
movq dev_matA(%rip), %rdi
call _Z31__device_stub__Z8mat_multPfS_S_PfS_S_
jmp .L59
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8mat_multPfS_S_"
.LC7:
.string "_Z7mat_subPfS_S_"
.LC8:
.string "_Z7mat_addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mat_multPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_subPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_addPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_dev_matA, @function
_GLOBAL__sub_I_dev_matA:
.LFB4335:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %edi
call malloc@PLT
movq %rax, matA(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, matB(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, res(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4335:
.size _GLOBAL__sub_I_dev_matA, .-_GLOBAL__sub_I_dev_matA
.section .init_array
.align 8
.quad _GLOBAL__sub_I_dev_matA
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res
.bss
.align 8
.type res, @object
.size res, 8
res:
.zero 8
.globl matB
.align 8
.type matB, @object
.size matB, 8
matB:
.zero 8
.globl matA
.align 8
.type matA, @object
.size matA, 8
matA:
.zero 8
.globl dev_res
.align 8
.type dev_res, @object
.size dev_res, 8
dev_res:
.zero 8
.globl dev_matB
.align 8
.type dev_matB, @object
.size dev_matB, 8
dev_matB:
.zero 8
.globl dev_matA
.align 8
.type dev_matA, @object
.size dev_matA, 8
dev_matA:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_math.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7initMatPf # -- Begin function _Z7initMatPf
.p2align 4, 0x90
.type _Z7initMatPf,@function
_Z7initMatPf: # @_Z7initMatPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rcx), %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
addq $5, %rcx
cmpq $25, %rcx
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $4, %rdi
cmpq $5, %rax
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z7initMatPf, .Lfunc_end0-_Z7initMatPf
.cfi_endproc
# -- End function
.globl _Z8printResv # -- Begin function _Z8printResv
.p2align 4, 0x90
.type _Z8printResv,@function
_Z8printResv: # @_Z8printResv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_9
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_1 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movq res(%rip), %rax
addq %r14, %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $5, %rbx
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $20, %r14
cmpq $5, %r15
jne .LBB1_1
# %bb.8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z8printResv, .Lfunc_end1-_Z8printResv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_addPfS_S_ # -- Begin function _Z22__device_stub__mat_addPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_,@function
_Z22__device_stub__mat_addPfS_S_: # @_Z22__device_stub__mat_addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__mat_addPfS_S_, .Lfunc_end2-_Z22__device_stub__mat_addPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_subPfS_S_ # -- Begin function _Z22__device_stub__mat_subPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_subPfS_S_,@function
_Z22__device_stub__mat_subPfS_S_: # @_Z22__device_stub__mat_subPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__mat_subPfS_S_, .Lfunc_end3-_Z22__device_stub__mat_subPfS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__mat_multPfS_S_ # -- Begin function _Z23__device_stub__mat_multPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__mat_multPfS_S_,@function
_Z23__device_stub__mat_multPfS_S_: # @_Z23__device_stub__mat_multPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z23__device_stub__mat_multPfS_S_, .Lfunc_end4-_Z23__device_stub__mat_multPfS_S_
.cfi_endproc
# -- End function
.globl _Z14mat_add_serialPfS_S_ # -- Begin function _Z14mat_add_serialPfS_S_
.p2align 4, 0x90
.type _Z14mat_add_serialPfS_S_,@function
_Z14mat_add_serialPfS_S_: # @_Z14mat_add_serialPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB5_1
# %bb.2:
retq
.Lfunc_end5:
.size _Z14mat_add_serialPfS_S_, .Lfunc_end5-_Z14mat_add_serialPfS_S_
.cfi_endproc
# -- End function
.globl _Z14mat_sub_serialPfS_S_ # -- Begin function _Z14mat_sub_serialPfS_S_
.p2align 4, 0x90
.type _Z14mat_sub_serialPfS_S_,@function
_Z14mat_sub_serialPfS_S_: # @_Z14mat_sub_serialPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB6_1
# %bb.2:
retq
.Lfunc_end6:
.size _Z14mat_sub_serialPfS_S_, .Lfunc_end6-_Z14mat_sub_serialPfS_S_
.cfi_endproc
# -- End function
.globl _Z15mat_mult_serialPfS_S_ # -- Begin function _Z15mat_mult_serialPfS_S_
.p2align 4, 0x90
.type _Z15mat_mult_serialPfS_S_,@function
_Z15mat_mult_serialPfS_S_: # @_Z15mat_mult_serialPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
# Child Loop BB7_3 Depth 3
leaq (%rax,%rax,4), %rcx
leaq (%rdx,%rcx,4), %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB7_2: # %.preheader
# Parent Loop BB7_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_3 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_1 Depth=1
# Parent Loop BB7_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
incq %r11
addq $20, %r10
cmpq $5, %r11
jne .LBB7_3
# %bb.4: # in Loop: Header=BB7_2 Depth=2
movss %xmm0, (%rcx,%r9,4)
incq %r9
addq $4, %r8
cmpq $5, %r9
jne .LBB7_2
# %bb.5: # in Loop: Header=BB7_1 Depth=1
incq %rax
addq $20, %rdi
cmpq $5, %rax
jne .LBB7_1
# %bb.6:
retq
.Lfunc_end7:
.size _Z15mat_mult_serialPfS_S_, .Lfunc_end7-_Z15mat_mult_serialPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $dev_matA, %edi
movl $100, %esi
callq hipMalloc
movl $dev_matB, %edi
movl $100, %esi
callq hipMalloc
movl $dev_res, %edi
movl $100, %esi
callq hipMalloc
xorl %eax, %eax
movq matA(%rip), %rsi
movq %rsi, %rcx
.p2align 4, 0x90
.LBB8_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB8_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_2: # Parent Loop BB8_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rcx,%rdx,4)
addq $5, %rdx
cmpq $25, %rdx
jne .LBB8_2
# %bb.3: # in Loop: Header=BB8_1 Depth=1
incq %rax
addq $4, %rcx
cmpq $5, %rax
jne .LBB8_1
# %bb.4: # %_Z7initMatPf.exit
movq matB(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_5: # %.preheader.i25
# =>This Loop Header: Depth=1
# Child Loop BB8_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_6: # Parent Loop BB8_5 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rax,%rdx,4)
addq $5, %rdx
cmpq $25, %rdx
jne .LBB8_6
# %bb.7: # in Loop: Header=BB8_5 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_5
# %bb.8: # %_Z7initMatPf.exit32
movabsq $68719476752, %rbx # imm = 0x1000000010
movabsq $4294967297, %r14 # imm = 0x100000001
movq dev_matA(%rip), %rdi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_matB(%rip), %rdi
movq matB(%rip), %rsi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_10
# %bb.9:
movq dev_matA(%rip), %rax
movq dev_matB(%rip), %rcx
movq dev_res(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_10:
movq res(%rip), %rdi
movq dev_res(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB8_49
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB8_13
# %bb.12:
movzbl 67(%r15), %eax
jmp .LBB8_14
.LBB8_13:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.3, %esi
movl $41, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_16
# %bb.15:
movq dev_matA(%rip), %rax
movq dev_matB(%rip), %rcx
movq dev_res(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_16:
movq res(%rip), %rdi
movq dev_res(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB8_49
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB8_19
# %bb.18:
movzbl 67(%r15), %eax
jmp .LBB8_20
.LBB8_19:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.3, %esi
movl $41, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_22
# %bb.21:
movq dev_matA(%rip), %rax
movq dev_matB(%rip), %rcx
movq dev_res(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_22:
movq res(%rip), %rdi
movq dev_res(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbx)
je .LBB8_25
# %bb.24:
movzbl 67(%rbx), %eax
jmp .LBB8_26
.LBB8_25:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.4, %esi
movl $41, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq matA(%rip), %rax
movq matB(%rip), %rcx
xorl %edx, %edx
movq res(%rip), %rsi
.p2align 4, 0x90
.LBB8_27: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%rdx,4), %xmm0
movss %xmm0, (%rsi,%rdx,4)
incq %rdx
cmpq $25, %rdx
jne .LBB8_27
# %bb.28: # %_Z14mat_add_serialPfS_S_.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%rbx)
je .LBB8_31
# %bb.30:
movzbl 67(%rbx), %eax
jmp .LBB8_32
.LBB8_31:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.5, %esi
movl $39, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq matA(%rip), %rax
movq matB(%rip), %rcx
xorl %edx, %edx
movq res(%rip), %rsi
.p2align 4, 0x90
.LBB8_33: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rcx,%rdx,4), %xmm0
movss %xmm0, (%rsi,%rdx,4)
incq %rdx
cmpq $25, %rdx
jne .LBB8_33
# %bb.34: # %_Z14mat_sub_serialPfS_S_.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%rbx)
je .LBB8_37
# %bb.36:
movzbl 67(%rbx), %eax
jmp .LBB8_38
.LBB8_37:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.5, %esi
movl $39, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq matA(%rip), %rax
movq matB(%rip), %rcx
xorl %edx, %edx
movq res(%rip), %rsi
.p2align 4, 0x90
.LBB8_39: # %.preheader19.i
# =>This Loop Header: Depth=1
# Child Loop BB8_40 Depth 2
# Child Loop BB8_41 Depth 3
leaq (%rdx,%rdx,4), %rdi
leaq (%rsi,%rdi,4), %rdi
movq %rcx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB8_40: # %.preheader.i51
# Parent Loop BB8_39 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_41 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB8_41: # Parent Loop BB8_39 Depth=1
# Parent Loop BB8_40 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
incq %r11
addq $20, %r10
cmpq $5, %r11
jne .LBB8_41
# %bb.42: # in Loop: Header=BB8_40 Depth=2
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq $5, %r9
jne .LBB8_40
# %bb.43: # in Loop: Header=BB8_39 Depth=1
incq %rdx
addq $20, %rax
cmpq $5, %rdx
jne .LBB8_39
# %bb.44: # %_Z15mat_mult_serialPfS_S_.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB8_47
# %bb.46:
movzbl 67(%rbx), %eax
jmp .LBB8_48
.LBB8_47:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.6, %esi
movl $39, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
leaq 80(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB8_49:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_matrix_math.hip
.type _GLOBAL__sub_I_matrix_math.hip,@function
_GLOBAL__sub_I_matrix_math.hip: # @_GLOBAL__sub_I_matrix_math.hip
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $100, %edi
callq malloc
movq %rax, matA(%rip)
movl $100, %edi
callq malloc
movq %rax, matB(%rip)
movl $100, %edi
callq malloc
movq %rax, res(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _GLOBAL__sub_I_matrix_math.hip, .Lfunc_end9-_GLOBAL__sub_I_matrix_math.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_subPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mat_multPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_matA,@object # @dev_matA
.bss
.globl dev_matA
.p2align 3, 0x0
dev_matA:
.quad 0
.size dev_matA, 8
.type dev_matB,@object # @dev_matB
.globl dev_matB
.p2align 3, 0x0
dev_matB:
.quad 0
.size dev_matB, 8
.type dev_res,@object # @dev_res
.globl dev_res
.p2align 3, 0x0
dev_res:
.quad 0
.size dev_res, 8
.type matA,@object # @matA
.globl matA
.p2align 3, 0x0
matA:
.quad 0
.size matA, 8
.type matB,@object # @matB
.globl matB
.p2align 3, 0x0
matB:
.quad 0
.size matB, 8
.type res,@object # @res
.globl res
.p2align 3, 0x0
res:
.quad 0
.size res, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z7mat_addPfS_S_,@object # @_Z7mat_addPfS_S_
.section .rodata,"a",@progbits
.globl _Z7mat_addPfS_S_
.p2align 3, 0x0
_Z7mat_addPfS_S_:
.quad _Z22__device_stub__mat_addPfS_S_
.size _Z7mat_addPfS_S_, 8
.type _Z7mat_subPfS_S_,@object # @_Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 3, 0x0
_Z7mat_subPfS_S_:
.quad _Z22__device_stub__mat_subPfS_S_
.size _Z7mat_subPfS_S_, 8
.type _Z8mat_multPfS_S_,@object # @_Z8mat_multPfS_S_
.globl _Z8mat_multPfS_S_
.p2align 3, 0x0
_Z8mat_multPfS_S_:
.quad _Z23__device_stub__mat_multPfS_S_
.size _Z8mat_multPfS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "###########parallel mat_add test######## "
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "###########parallel mat_mul test######## "
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "###########serial mat_add test######## "
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "###########serial mat_mul test######## "
.size .L.str.6, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_addPfS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mat_subPfS_S_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8mat_multPfS_S_"
.size .L__unnamed_3, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_matrix_math.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_addPfS_S_
.addrsig_sym _Z22__device_stub__mat_subPfS_S_
.addrsig_sym _Z23__device_stub__mat_multPfS_S_
.addrsig_sym _GLOBAL__sub_I_matrix_math.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_matA
.addrsig_sym dev_matB
.addrsig_sym dev_res
.addrsig_sym _ZSt4cout
.addrsig_sym _Z7mat_addPfS_S_
.addrsig_sym _Z7mat_subPfS_S_
.addrsig_sym _Z8mat_multPfS_S_
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <unistd.h>
#include <vector>
#include <assert.h>
#include <signal.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads,int * managed)
{
int index = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
printf("[D] I am %d\n",index );
*managed = 1;
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, error = 0;
while ((opt = getopt(argc, argv, "b:t:e:")) != -1) {
switch (opt)
{
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'e':
error = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
int * managed;
gpuErrchk(cudaMallocManaged((void **) &managed,sizeof(int)));
*managed = 0;
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS, managed);
if(error){
*managed = 2;
gpuErrchk(cudaDeviceSynchronize());
}else{
printf("[H] before cudaDeviceSynchronize\n");
gpuErrchk(cudaDeviceSynchronize());
assert(*managed != 0);
printf("[H] After cudaDeviceSynchronize managed:%d\n",*managed);
*managed = 2;
printf("[H] After cpu access managed:%d\n",*managed);
}
return 0;
} | code for sm_80
Function : _Z6kerneliPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.Z ; /* 0x0000000000037919 */
/* 0x000e220000002300 */
/*0060*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0090*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*00a0*/ IMAD R0, R0, c[0x0][0x8], R3 ; /* 0x0000020000007a24 */
/* 0x001fc400078e0203 */
/*00b0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e240000000a00 */
/*00c0*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fe400078e0205 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0207 */
/*00f0*/ IADD3.X R7, RZ, c[0x0][0x24], RZ, P0, !PT ; /* 0x00000900ff077a10 */
/* 0x000fc800007fe4ff */
/*0100*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e60000100800 */
/*0110*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0120*/ MOV R11, 0x190 ; /* 0x00000190000b7802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0160*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0170*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0180*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*01a0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fca00078e00ff */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101924 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <unistd.h>
#include <vector>
#include <assert.h>
#include <signal.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads,int * managed)
{
int index = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
printf("[D] I am %d\n",index );
*managed = 1;
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, error = 0;
while ((opt = getopt(argc, argv, "b:t:e:")) != -1) {
switch (opt)
{
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'e':
error = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
int * managed;
gpuErrchk(cudaMallocManaged((void **) &managed,sizeof(int)));
*managed = 0;
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS, managed);
if(error){
*managed = 2;
gpuErrchk(cudaDeviceSynchronize());
}else{
printf("[H] before cudaDeviceSynchronize\n");
gpuErrchk(cudaDeviceSynchronize());
assert(*managed != 0);
printf("[H] After cudaDeviceSynchronize managed:%d\n",*managed);
*managed = 2;
printf("[H] After cpu access managed:%d\n",*managed);
}
return 0;
} | .file "tmpxft_00003255_00000000-6_managed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2943:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2943:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2939:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2939:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z26__device_stub__Z6kerneliPiiPi
.type _Z26__device_stub__Z6kerneliPiiPi, @function
_Z26__device_stub__Z6kerneliPiiPi:
.LFB2965:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kerneliPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2965:
.size _Z26__device_stub__Z6kerneliPiiPi, .-_Z26__device_stub__Z6kerneliPiiPi
.globl _Z6kerneliPi
.type _Z6kerneliPi, @function
_Z6kerneliPi:
.LFB2966:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kerneliPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2966:
.size _Z6kerneliPi, .-_Z6kerneliPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Usage: %s -b [blocks] -t [threads]\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "b:t:e:"
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gganagno/GHammer/master/2_indexing_and_synchronisation/managed_sync/managed.cu"
.align 8
.LC4:
.string "[H] before cudaDeviceSynchronize\n"
.align 8
.LC5:
.string "[H] After cudaDeviceSynchronize managed:%d\n"
.align 8
.LC6:
.string "[H] After cpu access managed:%d\n"
.text
.globl main
.type main, @function
main:
.LFB2940:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %r15d
movl $1, %r13d
movl $1, %r12d
leaq .LC2(%rip), %r14
jmp .L20
.L22:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r13d
.L20:
movq %r14, %rdx
movq %rbx, %rsi
movl %ebp, %edi
call getopt@PLT
cmpl $-1, %eax
je .L31
cmpl $101, %eax
je .L21
cmpl $116, %eax
je .L22
cmpl $98, %eax
jne .L23
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r12d
jmp .L20
.L21:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
jmp .L20
.L23:
movq (%rbx), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rax
movl $0, (%rax)
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
testl %r15d, %r15d
je .L27
movq 8(%rsp), %rax
movl $2, (%rax)
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
.L28:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %r12d, %edi
imull %r13d, %edi
movq 8(%rsp), %rsi
call _Z26__device_stub__Z6kerneliPiiPi
jmp .L26
.L27:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rax
movl (%rax), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl $2, (%rax)
movq 8(%rsp), %rax
movl (%rax), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2940:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6kerneliPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2968:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2968:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <unistd.h>
#include <vector>
#include <assert.h>
#include <signal.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads,int * managed)
{
int index = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
printf("[D] I am %d\n",index );
*managed = 1;
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, error = 0;
while ((opt = getopt(argc, argv, "b:t:e:")) != -1) {
switch (opt)
{
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'e':
error = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
int * managed;
gpuErrchk(cudaMallocManaged((void **) &managed,sizeof(int)));
*managed = 0;
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS, managed);
if(error){
*managed = 2;
gpuErrchk(cudaDeviceSynchronize());
}else{
printf("[H] before cudaDeviceSynchronize\n");
gpuErrchk(cudaDeviceSynchronize());
assert(*managed != 0);
printf("[H] After cudaDeviceSynchronize managed:%d\n",*managed);
*managed = 2;
printf("[H] After cpu access managed:%d\n",*managed);
}
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <vector>
#include <assert.h>
#include <signal.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads,int * managed)
{
int index = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
printf("[D] I am %d\n",index );
*managed = 1;
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, error = 0;
while ((opt = getopt(argc, argv, "b:t:e:")) != -1) {
switch (opt)
{
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'e':
error = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
int * managed;
gpuErrchk(hipMallocManaged((void **) &managed,sizeof(int)));
*managed = 0;
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS, managed);
if(error){
*managed = 2;
gpuErrchk(hipDeviceSynchronize());
}else{
printf("[H] before cudaDeviceSynchronize\n");
gpuErrchk(hipDeviceSynchronize());
assert(*managed != 0);
printf("[H] After hipDeviceSynchronize managed:%d\n",*managed);
*managed = 2;
printf("[H] After cpu access managed:%d\n",*managed);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <vector>
#include <assert.h>
#include <signal.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads,int * managed)
{
int index = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
printf("[D] I am %d\n",index );
*managed = 1;
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, error = 0;
while ((opt = getopt(argc, argv, "b:t:e:")) != -1) {
switch (opt)
{
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'e':
error = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
int * managed;
gpuErrchk(hipMallocManaged((void **) &managed,sizeof(int)));
*managed = 0;
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS, managed);
if(error){
*managed = 2;
gpuErrchk(hipDeviceSynchronize());
}else{
printf("[H] before cudaDeviceSynchronize\n");
gpuErrchk(hipDeviceSynchronize());
assert(*managed != 0);
printf("[H] After hipDeviceSynchronize managed:%d\n",*managed);
*managed = 2;
printf("[H] After cpu access managed:%d\n",*managed);
}
return 0;
} | .text
.file "managed.hip"
.globl _Z21__device_stub__kerneliPi # -- Begin function _Z21__device_stub__kerneliPi
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPi,@function
_Z21__device_stub__kerneliPi: # @_Z21__device_stub__kerneliPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kerneliPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPi, .Lfunc_end0-_Z21__device_stub__kerneliPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movl %edi, %ebp
movl $1, %r14d
xorl %ebx, %ebx
movl $1, %r15d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edx
movl %ebp, %edi
movq %r12, %rsi
callq getopt
cmpl $98, %eax
je .LBB1_20
# %bb.2: # in Loop: Header=BB1_1 Depth=1
cmpl $-1, %eax
je .LBB1_8
# %bb.3: # in Loop: Header=BB1_1 Depth=1
cmpl $101, %eax
je .LBB1_6
# %bb.4: # in Loop: Header=BB1_1 Depth=1
cmpl $116, %eax
jne .LBB1_7
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB1_1
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB1_1
.LBB1_8:
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_9
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 8(%rsp), %rax
movl $0, (%rax)
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r14d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_12
# %bb.13:
testl %ebx, %ebx
je .LBB1_16
.LBB1_14:
movq 8(%rsp), %rax
movl $2, (%rax)
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_19
# %bb.15:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %r8d
jmp .LBB1_10
.LBB1_12:
imull %r14d, %r15d
movq 8(%rsp), %rax
movl %r15d, 20(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kerneliPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
testl %ebx, %ebx
jne .LBB1_14
.LBB1_16:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_17
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit20
movq 8(%rsp), %rax
movl (%rax), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rax
movl $2, (%rax)
movl $.L.str.5, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
.LBB1_19: # %_Z9gpuAssert10hipError_tPKcib.exit18
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movq (%r12), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_10
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
.LBB1_10:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPi,@object # @_Z6kerneliPi
.section .rodata,"a",@progbits
.globl _Z6kerneliPi
.p2align 3, 0x0
_Z6kerneliPi:
.quad _Z21__device_stub__kerneliPi
.size _Z6kerneliPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "b:t:e:"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage: %s -b [blocks] -t [threads]\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gganagno/GHammer/master/2_indexing_and_synchronisation/managed_sync/managed.hip"
.size .L.str.2, 137
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[H] After hipDeviceSynchronize managed:%d\n"
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[H] After cpu access managed:%d\n"
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kerneliPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[H] before cudaDeviceSynchronize"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kerneliPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00003255_00000000-6_managed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2943:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2943:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2939:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2939:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z26__device_stub__Z6kerneliPiiPi
.type _Z26__device_stub__Z6kerneliPiiPi, @function
_Z26__device_stub__Z6kerneliPiiPi:
.LFB2965:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kerneliPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2965:
.size _Z26__device_stub__Z6kerneliPiiPi, .-_Z26__device_stub__Z6kerneliPiiPi
.globl _Z6kerneliPi
.type _Z6kerneliPi, @function
_Z6kerneliPi:
.LFB2966:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kerneliPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2966:
.size _Z6kerneliPi, .-_Z6kerneliPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Usage: %s -b [blocks] -t [threads]\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "b:t:e:"
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gganagno/GHammer/master/2_indexing_and_synchronisation/managed_sync/managed.cu"
.align 8
.LC4:
.string "[H] before cudaDeviceSynchronize\n"
.align 8
.LC5:
.string "[H] After cudaDeviceSynchronize managed:%d\n"
.align 8
.LC6:
.string "[H] After cpu access managed:%d\n"
.text
.globl main
.type main, @function
main:
.LFB2940:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %r15d
movl $1, %r13d
movl $1, %r12d
leaq .LC2(%rip), %r14
jmp .L20
.L22:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r13d
.L20:
movq %r14, %rdx
movq %rbx, %rsi
movl %ebp, %edi
call getopt@PLT
cmpl $-1, %eax
je .L31
cmpl $101, %eax
je .L21
cmpl $116, %eax
je .L22
cmpl $98, %eax
jne .L23
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r12d
jmp .L20
.L21:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
jmp .L20
.L23:
movq (%rbx), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rax
movl $0, (%rax)
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
testl %r15d, %r15d
je .L27
movq 8(%rsp), %rax
movl $2, (%rax)
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
.L28:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %r12d, %edi
imull %r13d, %edi
movq 8(%rsp), %rsi
call _Z26__device_stub__Z6kerneliPiiPi
jmp .L26
.L27:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rax
movl (%rax), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl $2, (%rax)
movq 8(%rsp), %rax
movl (%rax), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2940:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6kerneliPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2968:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2968:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "managed.hip"
.globl _Z21__device_stub__kerneliPi # -- Begin function _Z21__device_stub__kerneliPi
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPi,@function
_Z21__device_stub__kerneliPi: # @_Z21__device_stub__kerneliPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kerneliPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPi, .Lfunc_end0-_Z21__device_stub__kerneliPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movl %edi, %ebp
movl $1, %r14d
xorl %ebx, %ebx
movl $1, %r15d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edx
movl %ebp, %edi
movq %r12, %rsi
callq getopt
cmpl $98, %eax
je .LBB1_20
# %bb.2: # in Loop: Header=BB1_1 Depth=1
cmpl $-1, %eax
je .LBB1_8
# %bb.3: # in Loop: Header=BB1_1 Depth=1
cmpl $101, %eax
je .LBB1_6
# %bb.4: # in Loop: Header=BB1_1 Depth=1
cmpl $116, %eax
jne .LBB1_7
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB1_1
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB1_1
.LBB1_8:
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_9
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 8(%rsp), %rax
movl $0, (%rax)
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r14d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_12
# %bb.13:
testl %ebx, %ebx
je .LBB1_16
.LBB1_14:
movq 8(%rsp), %rax
movl $2, (%rax)
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_19
# %bb.15:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %r8d
jmp .LBB1_10
.LBB1_12:
imull %r14d, %r15d
movq 8(%rsp), %rax
movl %r15d, 20(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kerneliPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
testl %ebx, %ebx
jne .LBB1_14
.LBB1_16:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_17
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit20
movq 8(%rsp), %rax
movl (%rax), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rax
movl $2, (%rax)
movl $.L.str.5, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
.LBB1_19: # %_Z9gpuAssert10hipError_tPKcib.exit18
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movq (%r12), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_10
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
.LBB1_10:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPi,@object # @_Z6kerneliPi
.section .rodata,"a",@progbits
.globl _Z6kerneliPi
.p2align 3, 0x0
_Z6kerneliPi:
.quad _Z21__device_stub__kerneliPi
.size _Z6kerneliPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "b:t:e:"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage: %s -b [blocks] -t [threads]\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gganagno/GHammer/master/2_indexing_and_synchronisation/managed_sync/managed.hip"
.size .L.str.2, 137
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[H] After hipDeviceSynchronize managed:%d\n"
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[H] After cpu access managed:%d\n"
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kerneliPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[H] before cudaDeviceSynchronize"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kerneliPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuComplex.h>
// Launch configuration should be as follows:
// 1. blocks of dim3(threads_per_dim, threads_per_dim, 1) size
// where threads_per_dim = min(N, 16)
// 2. grid of dim3((N+threads_per_dim-1)/threads_per_dim, (N-1)/(threads_per_dim * 2)+1, 1) blocks
template <class T>
static __device__ __inline__
void fftshift_kernel_common(T* data, int shift, int N, int pitch){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > N-1 || y > (N+1)/2-1) return;
int x1 = x + shift;
if (x1 > N-1) x1 -= N;
int y1 = y + shift;
if (y1 > N-1) y1 -= N;
int
i = x + y * pitch
, i1 = x1 + y1 * pitch;
T tmp;
tmp = data[i];
data[i] = data[i1];
data[i1] = tmp;
}
extern "C" {
__global__
void fftshift_half_hermitian(cuDoubleComplex* data, int N, int pitch) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= N/4 || y >= N) return;
// shift+mirror
int x1 = N/2 - x - 1; // N - (N + N/2) - 1
int y1 = N/2 - y - 1; // N - (N + N/2) - 1
if (y1 < 0) y1 += N;
// offsets
int i = x+y*pitch,
i1 = x1+y1*pitch;
// Swap + conjugate (note that x == N/2-x1-1!)
cuDoubleComplex tmp;
tmp = data[i];
data[i].x = data[i1].x;
data[i].y = -data[i1].y;
data[i1].x = tmp.x;
data[i1].y = -tmp.y;
}
__global__
void fftshift_kernel_cx(cuDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<cuDoubleComplex>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_cx(cuDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<cuDoubleComplex>(data, N/2 + N%2, N, pitch);
}
__global__
void fftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2 + N%2, N, pitch);
}
} | code for sm_80
Function : ifftshift_kernel_r
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x002fe20000000000 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0202 */
/*00a0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*00b0*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc8000fffe03f */
/*00c0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*00d0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ ULDC UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000800 */
/*0110*/ IADD3 R5, RZ, -c[0x0][0x168], RZ ; /* 0x80005a00ff057a10 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULEA.HI UR4, UR6, UR6, URZ, 0x1 ; /* 0x0000000606047291 */
/* 0x000fc8000f8f083f */
/*0130*/ ULOP3.LUT UR5, UR4, 0xfffffffe, URZ, 0xc0, !UPT ; /* 0xfffffffe04057892 */
/* 0x000fc8000f8ec03f */
/*0140*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc8000fffe13f */
/*0150*/ ULEA.HI.SX32 UR5, UR4, UR5, 0x1f ; /* 0x0000000504057291 */
/* 0x000fcc000f8ffa3f */
/*0160*/ IADD3 R2, R0, UR5, RZ ; /* 0x0000000500027c10 */
/* 0x000fe4000fffe0ff */
/*0170*/ IADD3 R4, R3.reuse, UR5, RZ ; /* 0x0000000503047c10 */
/* 0x040fe2000fffe0ff */
/*0180*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*0190*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06270 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f26270 */
/*01c0*/ SEL R5, R5, RZ, P0 ; /* 0x000000ff05057207 */
/* 0x000fe40000000000 */
/*01d0*/ SEL R7, RZ, c[0x0][0x168], !P1 ; /* 0x00005a00ff077a07 */
/* 0x000fc60004800000 */
/*01e0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x000fe200078e0205 */
/*01f0*/ IADD3 R4, R4, -R7, RZ ; /* 0x8000000704047210 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD R4, R4, c[0x0][0x16c], R5 ; /* 0x00005b0004047a24 */
/* 0x000fc800078e0205 */
/*0220*/ IMAD.WIDE R6, R4, R2, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fc800078e0202 */
/*0230*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0240*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0250*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee8000c1e1b00 */
/*0260*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x004fe8000c101b04 */
/*0270*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x008fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : fftshift_kernel_r
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x002fe20000000000 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0202 */
/*00a0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*00b0*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc8000fffe03f */
/*00c0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*00d0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ IADD3 R5, RZ, -c[0x0][0x168], RZ ; /* 0x80005a00ff057a10 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*0130*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*0140*/ IADD3 R2, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x000fe4000fffe0ff */
/*0150*/ IADD3 R4, R3.reuse, UR4, RZ ; /* 0x0000000403047c10 */
/* 0x040fe2000fffe0ff */
/*0160*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*0170*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06270 */
/*0180*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0190*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f26270 */
/*01a0*/ SEL R5, R5, RZ, P0 ; /* 0x000000ff05057207 */
/* 0x000fe40000000000 */
/*01b0*/ SEL R7, RZ, c[0x0][0x168], !P1 ; /* 0x00005a00ff077a07 */
/* 0x000fc60004800000 */
/*01c0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x000fe200078e0205 */
/*01d0*/ IADD3 R4, R4, -R7, RZ ; /* 0x8000000704047210 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R4, R4, c[0x0][0x16c], R5 ; /* 0x00005b0004047a24 */
/* 0x000fc800078e0205 */
/*0200*/ IMAD.WIDE R6, R4, R2, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fc800078e0202 */
/*0210*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0220*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0230*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee8000c1e1b00 */
/*0240*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x004fe8000c101b04 */
/*0250*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x008fe2000c101b04 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : ifftshift_kernel_cx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x002fe20000000000 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0202 */
/*00a0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*00b0*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc8000fffe03f */
/*00c0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*00d0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ ULDC UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000800 */
/*0110*/ IADD3 R5, RZ, -c[0x0][0x168], RZ ; /* 0x80005a00ff057a10 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULEA.HI UR4, UR6, UR6, URZ, 0x1 ; /* 0x0000000606047291 */
/* 0x000fc8000f8f083f */
/*0130*/ ULOP3.LUT UR5, UR4, 0xfffffffe, URZ, 0xc0, !UPT ; /* 0xfffffffe04057892 */
/* 0x000fc8000f8ec03f */
/*0140*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc8000fffe13f */
/*0150*/ ULEA.HI.SX32 UR5, UR4, UR5, 0x1f ; /* 0x0000000504057291 */
/* 0x000fcc000f8ffa3f */
/*0160*/ IADD3 R2, R0, UR5, RZ ; /* 0x0000000500027c10 */
/* 0x000fe4000fffe0ff */
/*0170*/ IADD3 R4, R3.reuse, UR5, RZ ; /* 0x0000000503047c10 */
/* 0x040fe2000fffe0ff */
/*0180*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*0190*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06270 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f26270 */
/*01c0*/ SEL R5, R5, RZ, P0 ; /* 0x000000ff05057207 */
/* 0x000fe40000000000 */
/*01d0*/ SEL R7, RZ, c[0x0][0x168], !P1 ; /* 0x00005a00ff077a07 */
/* 0x000fc60004800000 */
/*01e0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x000fe200078e0205 */
/*01f0*/ IADD3 R4, R4, -R7, RZ ; /* 0x8000000704047210 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, 0x10 ; /* 0x00000010ff027424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD R4, R4, c[0x0][0x16c], R5 ; /* 0x00005b0004047a24 */
/* 0x000fc800078e0205 */
/*0220*/ IMAD.WIDE R8, R4, R2, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fc800078e0202 */
/*0230*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0240*/ LDG.E.128 R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea8000c1e1d00 */
/*0250*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee8000c1e1d00 */
/*0260*/ STG.E.128 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x004fe8000c101d04 */
/*0270*/ STG.E.128 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x008fe2000c101d04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : fftshift_kernel_cx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x002fe20000000000 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe200078e0202 */
/*00a0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*00b0*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc8000fffe03f */
/*00c0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*00d0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ IADD3 R5, RZ, -c[0x0][0x168], RZ ; /* 0x80005a00ff057a10 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*0130*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*0140*/ IADD3 R2, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x000fe4000fffe0ff */
/*0150*/ IADD3 R4, R3.reuse, UR4, RZ ; /* 0x0000000403047c10 */
/* 0x040fe2000fffe0ff */
/*0160*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*0170*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06270 */
/*0180*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0190*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f26270 */
/*01a0*/ SEL R5, R5, RZ, P0 ; /* 0x000000ff05057207 */
/* 0x000fe40000000000 */
/*01b0*/ SEL R7, RZ, c[0x0][0x168], !P1 ; /* 0x00005a00ff077a07 */
/* 0x000fc60004800000 */
/*01c0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x000fe200078e0205 */
/*01d0*/ IADD3 R4, R4, -R7, RZ ; /* 0x8000000704047210 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x10 ; /* 0x00000010ff027424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R4, R4, c[0x0][0x16c], R5 ; /* 0x00005b0004047a24 */
/* 0x000fc800078e0205 */
/*0200*/ IMAD.WIDE R8, R4, R2, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fc800078e0202 */
/*0210*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0220*/ LDG.E.128 R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea8000c1e1d00 */
/*0230*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee8000c1e1d00 */
/*0240*/ STG.E.128 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x004fe8000c101d04 */
/*0250*/ STG.E.128 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x008fe2000c101d04 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : fftshift_half_hermitian
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR6 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011406 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ ULEA.HI UR4, UR4, UR6, URZ, 0x2 ; /* 0x0000000604047291 */
/* 0x000fe2000f8f103f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e660000002600 */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fe20008011404 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06270 */
/*00b0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*00f0*/ LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff027212 */
/* 0x000fe200078e33ff */
/*0100*/ ULEA.HI UR4, UR6, UR4, URZ, 0x1 ; /* 0x0000000406047291 */
/* 0x000fe2000f8f083f */
/*0110*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fc600078e0200 */
/*0120*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011404 */
/*0130*/ IADD3 R4, R2, UR4, RZ ; /* 0x0000000402047c10 */
/* 0x000fe4000fffe0ff */
/*0140*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe400078e33ff */
/*0150*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0160*/ IADD3 R2, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x000fe2000fffe0ff */
/*0170*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0180*/ LOP3.LUT R5, R5, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0005057a12 */
/* 0x000fc800078ec0ff */
/*0190*/ IADD3 R5, R4, R5, RZ ; /* 0x0000000504057210 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; /* 0x00000010ff047424 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD R2, R5, c[0x0][0x16c], R2 ; /* 0x00005b0005027a24 */
/* 0x000fc800078e0202 */
/*01c0*/ IMAD.WIDE R8, R2, R4, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fc800078e0204 */
/*01d0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0204 */
/*01e0*/ LDG.E.128 R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea8000c1e1d00 */
/*01f0*/ LDG.E.128 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee2000c1e1d00 */
/*0200*/ DADD R14, -RZ, -R14 ; /* 0x00000000ff0e7229 */
/* 0x004e08000000090e */
/*0210*/ DADD R6, -RZ, -R6 ; /* 0x00000000ff067229 */
/* 0x008e460000000906 */
/*0220*/ STG.E.128 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x001fe8000c101d04 */
/*0230*/ STG.E.128 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x002fe2000c101d04 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuComplex.h>
// Launch configuration should be as follows:
// 1. blocks of dim3(threads_per_dim, threads_per_dim, 1) size
// where threads_per_dim = min(N, 16)
// 2. grid of dim3((N+threads_per_dim-1)/threads_per_dim, (N-1)/(threads_per_dim * 2)+1, 1) blocks
template <class T>
static __device__ __inline__
void fftshift_kernel_common(T* data, int shift, int N, int pitch){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > N-1 || y > (N+1)/2-1) return;
int x1 = x + shift;
if (x1 > N-1) x1 -= N;
int y1 = y + shift;
if (y1 > N-1) y1 -= N;
int
i = x + y * pitch
, i1 = x1 + y1 * pitch;
T tmp;
tmp = data[i];
data[i] = data[i1];
data[i1] = tmp;
}
extern "C" {
__global__
void fftshift_half_hermitian(cuDoubleComplex* data, int N, int pitch) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= N/4 || y >= N) return;
// shift+mirror
int x1 = N/2 - x - 1; // N - (N + N/2) - 1
int y1 = N/2 - y - 1; // N - (N + N/2) - 1
if (y1 < 0) y1 += N;
// offsets
int i = x+y*pitch,
i1 = x1+y1*pitch;
// Swap + conjugate (note that x == N/2-x1-1!)
cuDoubleComplex tmp;
tmp = data[i];
data[i].x = data[i1].x;
data[i].y = -data[i1].y;
data[i1].x = tmp.x;
data[i1].y = -tmp.y;
}
__global__
void fftshift_kernel_cx(cuDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<cuDoubleComplex>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_cx(cuDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<cuDoubleComplex>(data, N/2 + N%2, N, pitch);
}
__global__
void fftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2 + N%2, N, pitch);
}
} | .file "tmpxft_00098201_00000000-6_cufftshift.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii
.type _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii, @function
_Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii:
.LFB2075:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq fftshift_half_hermitian(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii, .-_Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii
.globl fftshift_half_hermitian
.type fftshift_half_hermitian, @function
fftshift_half_hermitian:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size fftshift_half_hermitian, .-fftshift_half_hermitian
.globl _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii
.type _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii, @function
_Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii:
.LFB2077:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq fftshift_kernel_cx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii, .-_Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii
.globl fftshift_kernel_cx
.type fftshift_kernel_cx, @function
fftshift_kernel_cx:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size fftshift_kernel_cx, .-fftshift_kernel_cx
.globl _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii
.type _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii, @function
_Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii:
.LFB2079:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq ifftshift_kernel_cx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii, .-_Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii
.globl ifftshift_kernel_cx
.type ifftshift_kernel_cx, @function
ifftshift_kernel_cx:
.LFB2080:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size ifftshift_kernel_cx, .-ifftshift_kernel_cx
.globl _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii
.type _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii, @function
_Z39__device_stub__Z17fftshift_kernel_rPdiiPdii:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq fftshift_kernel_r(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii, .-_Z39__device_stub__Z17fftshift_kernel_rPdiiPdii
.globl fftshift_kernel_r
.type fftshift_kernel_r, @function
fftshift_kernel_r:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size fftshift_kernel_r, .-fftshift_kernel_r
.globl _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii
.type _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii, @function
_Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq ifftshift_kernel_r(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii, .-_Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii
.globl ifftshift_kernel_r
.type ifftshift_kernel_r, @function
ifftshift_kernel_r:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size ifftshift_kernel_r, .-ifftshift_kernel_r
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ifftshift_kernel_r"
.LC1:
.string "fftshift_kernel_r"
.LC2:
.string "ifftshift_kernel_cx"
.LC3:
.string "fftshift_kernel_cx"
.LC4:
.string "fftshift_half_hermitian"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ifftshift_kernel_r(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq fftshift_kernel_r(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq ifftshift_kernel_cx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq fftshift_kernel_cx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq fftshift_half_hermitian(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuComplex.h>
// Launch configuration should be as follows:
// 1. blocks of dim3(threads_per_dim, threads_per_dim, 1) size
// where threads_per_dim = min(N, 16)
// 2. grid of dim3((N+threads_per_dim-1)/threads_per_dim, (N-1)/(threads_per_dim * 2)+1, 1) blocks
template <class T>
static __device__ __inline__
void fftshift_kernel_common(T* data, int shift, int N, int pitch){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > N-1 || y > (N+1)/2-1) return;
int x1 = x + shift;
if (x1 > N-1) x1 -= N;
int y1 = y + shift;
if (y1 > N-1) y1 -= N;
int
i = x + y * pitch
, i1 = x1 + y1 * pitch;
T tmp;
tmp = data[i];
data[i] = data[i1];
data[i1] = tmp;
}
extern "C" {
__global__
void fftshift_half_hermitian(cuDoubleComplex* data, int N, int pitch) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= N/4 || y >= N) return;
// shift+mirror
int x1 = N/2 - x - 1; // N - (N + N/2) - 1
int y1 = N/2 - y - 1; // N - (N + N/2) - 1
if (y1 < 0) y1 += N;
// offsets
int i = x+y*pitch,
i1 = x1+y1*pitch;
// Swap + conjugate (note that x == N/2-x1-1!)
cuDoubleComplex tmp;
tmp = data[i];
data[i].x = data[i1].x;
data[i].y = -data[i1].y;
data[i1].x = tmp.x;
data[i1].y = -tmp.y;
}
__global__
void fftshift_kernel_cx(cuDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<cuDoubleComplex>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_cx(cuDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<cuDoubleComplex>(data, N/2 + N%2, N, pitch);
}
__global__
void fftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2 + N%2, N, pitch);
}
} | #include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
// Launch configuration should be as follows:
// 1. blocks of dim3(threads_per_dim, threads_per_dim, 1) size
// where threads_per_dim = min(N, 16)
// 2. grid of dim3((N+threads_per_dim-1)/threads_per_dim, (N-1)/(threads_per_dim * 2)+1, 1) blocks
template <class T>
static __device__ __inline__
void fftshift_kernel_common(T* data, int shift, int N, int pitch){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > N-1 || y > (N+1)/2-1) return;
int x1 = x + shift;
if (x1 > N-1) x1 -= N;
int y1 = y + shift;
if (y1 > N-1) y1 -= N;
int
i = x + y * pitch
, i1 = x1 + y1 * pitch;
T tmp;
tmp = data[i];
data[i] = data[i1];
data[i1] = tmp;
}
extern "C" {
__global__
void fftshift_half_hermitian(hipDoubleComplex* data, int N, int pitch) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= N/4 || y >= N) return;
// shift+mirror
int x1 = N/2 - x - 1; // N - (N + N/2) - 1
int y1 = N/2 - y - 1; // N - (N + N/2) - 1
if (y1 < 0) y1 += N;
// offsets
int i = x+y*pitch,
i1 = x1+y1*pitch;
// Swap + conjugate (note that x == N/2-x1-1!)
hipDoubleComplex tmp;
tmp = data[i];
data[i].x = data[i1].x;
data[i].y = -data[i1].y;
data[i1].x = tmp.x;
data[i1].y = -tmp.y;
}
__global__
void fftshift_kernel_cx(hipDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<hipDoubleComplex>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_cx(hipDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<hipDoubleComplex>(data, N/2 + N%2, N, pitch);
}
__global__
void fftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2 + N%2, N, pitch);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
// Launch configuration should be as follows:
// 1. blocks of dim3(threads_per_dim, threads_per_dim, 1) size
// where threads_per_dim = min(N, 16)
// 2. grid of dim3((N+threads_per_dim-1)/threads_per_dim, (N-1)/(threads_per_dim * 2)+1, 1) blocks
template <class T>
static __device__ __inline__
void fftshift_kernel_common(T* data, int shift, int N, int pitch){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > N-1 || y > (N+1)/2-1) return;
int x1 = x + shift;
if (x1 > N-1) x1 -= N;
int y1 = y + shift;
if (y1 > N-1) y1 -= N;
int
i = x + y * pitch
, i1 = x1 + y1 * pitch;
T tmp;
tmp = data[i];
data[i] = data[i1];
data[i1] = tmp;
}
extern "C" {
__global__
void fftshift_half_hermitian(hipDoubleComplex* data, int N, int pitch) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= N/4 || y >= N) return;
// shift+mirror
int x1 = N/2 - x - 1; // N - (N + N/2) - 1
int y1 = N/2 - y - 1; // N - (N + N/2) - 1
if (y1 < 0) y1 += N;
// offsets
int i = x+y*pitch,
i1 = x1+y1*pitch;
// Swap + conjugate (note that x == N/2-x1-1!)
hipDoubleComplex tmp;
tmp = data[i];
data[i].x = data[i1].x;
data[i].y = -data[i1].y;
data[i1].x = tmp.x;
data[i1].y = -tmp.y;
}
__global__
void fftshift_kernel_cx(hipDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<hipDoubleComplex>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_cx(hipDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<hipDoubleComplex>(data, N/2 + N%2, N, pitch);
}
__global__
void fftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2 + N%2, N, pitch);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected fftshift_half_hermitian
.globl fftshift_half_hermitian
.p2align 8
.type fftshift_half_hermitian,@function
fftshift_half_hermitian:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_ashr_i32 s5, s3, 31
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_lshr_b32 s2, s5, 30
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_lshr_b32 s2, s3, 31
s_load_b32 s4, s[0:1], 0xc
s_add_i32 s2, s3, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v2, v1, -1, s2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_and_b32_e32 v3, s3, v3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
v_add_nc_u32_e32 v2, v3, v2
v_not_b32_e32 v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v2, s4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, s2, v3, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 4, v[2:3]
v_lshlrev_b64 v[2:3], 4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[10:11], off
s_waitcnt vmcnt(1)
v_xor_b32_e32 v3, 0x80000000, v3
s_waitcnt vmcnt(0)
v_xor_b32_e32 v7, 0x80000000, v7
s_clause 0x1
global_store_b128 v[10:11], v[0:3], off
global_store_b128 v[8:9], v[4:7], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel fftshift_half_hermitian
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size fftshift_half_hermitian, .Lfunc_end0-fftshift_half_hermitian
.section .AMDGPU.csdata,"",@progbits
.text
.protected fftshift_kernel_cx
.globl fftshift_kernel_cx
.p2align 8
.type fftshift_kernel_cx,@function
fftshift_kernel_cx:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_add_i32 s5, s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_lshr_b32 s2, s5, 31
s_add_i32 s5, s5, s2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_ashr_i32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_2
s_lshr_b32 s2, s3, 31
s_load_b32 s4, s[0:1], 0xc
s_add_i32 s2, s3, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s2, v0
v_add_nc_u32_e32 v3, s2, v1
v_cmp_le_i32_e32 vcc_lo, s3, v2
v_cndmask_b32_e64 v4, 0, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s3, v3
v_sub_nc_u32_e32 v2, v2, v4
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v3, v5
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v5, s4, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 4, v[3:4]
v_lshlrev_b64 v[2:3], 4, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[10:11], off
s_waitcnt vmcnt(1)
global_store_b128 v[10:11], v[0:3], off
s_waitcnt vmcnt(0)
global_store_b128 v[8:9], v[4:7], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel fftshift_kernel_cx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size fftshift_kernel_cx, .Lfunc_end1-fftshift_kernel_cx
.section .AMDGPU.csdata,"",@progbits
.text
.protected ifftshift_kernel_cx
.globl ifftshift_kernel_cx
.p2align 8
.type ifftshift_kernel_cx,@function
ifftshift_kernel_cx:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_add_i32 s5, s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_lshr_b32 s2, s5, 31
s_add_i32 s5, s5, s2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_ashr_i32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_2
s_lshr_b32 s2, s3, 31
s_load_b32 s5, s[0:1], 0xc
s_add_i32 s2, s3, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_and_b32 s4, s2, -2
s_ashr_i32 s2, s2, 1
s_sub_i32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
v_add_nc_u32_e32 v2, s2, v0
v_add_nc_u32_e32 v3, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s3, v2
v_cndmask_b32_e64 v4, 0, s3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_sub_nc_u32_e32 v5, v3, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v5, s5, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s5, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 4, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 4, v[5:6]
v_add_co_u32 v8, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[10:11], off
s_waitcnt vmcnt(1)
global_store_b128 v[10:11], v[0:3], off
s_waitcnt vmcnt(0)
global_store_b128 v[8:9], v[4:7], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel ifftshift_kernel_cx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size ifftshift_kernel_cx, .Lfunc_end2-ifftshift_kernel_cx
.section .AMDGPU.csdata,"",@progbits
.text
.protected fftshift_kernel_r
.globl fftshift_kernel_r
.p2align 8
.type fftshift_kernel_r,@function
fftshift_kernel_r:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_add_i32 s5, s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_lshr_b32 s2, s5, 31
s_add_i32 s5, s5, s2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_ashr_i32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB3_2
s_lshr_b32 s2, s3, 31
s_load_b32 s4, s[0:1], 0xc
s_add_i32 s2, s3, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s2, v0
v_add_nc_u32_e32 v3, s2, v1
v_cmp_le_i32_e32 vcc_lo, s3, v2
v_cndmask_b32_e64 v4, 0, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s3, v3
v_sub_nc_u32_e32 v2, v2, v4
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v3, v5
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v5, s4, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[3:4]
v_lshlrev_b64 v[2:3], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[0:1], off
global_load_b64 v[6:7], v[2:3], off
s_waitcnt vmcnt(1)
global_store_b64 v[2:3], v[4:5], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[6:7], off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel fftshift_kernel_r
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size fftshift_kernel_r, .Lfunc_end3-fftshift_kernel_r
.section .AMDGPU.csdata,"",@progbits
.text
.protected ifftshift_kernel_r
.globl ifftshift_kernel_r
.p2align 8
.type ifftshift_kernel_r,@function
ifftshift_kernel_r:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_add_i32 s5, s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_lshr_b32 s2, s5, 31
s_add_i32 s5, s5, s2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_ashr_i32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB4_2
s_lshr_b32 s2, s3, 31
s_load_b32 s5, s[0:1], 0xc
s_add_i32 s2, s3, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_and_b32 s4, s2, -2
s_ashr_i32 s2, s2, 1
s_sub_i32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
v_add_nc_u32_e32 v2, s2, v0
v_add_nc_u32_e32 v3, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s3, v2
v_cndmask_b32_e64 v4, 0, s3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_sub_nc_u32_e32 v5, v3, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v5, s5, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s5, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[5:6]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[0:1], off
global_load_b64 v[6:7], v[2:3], off
s_waitcnt vmcnt(1)
global_store_b64 v[2:3], v[4:5], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[6:7], off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel ifftshift_kernel_r
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size ifftshift_kernel_r, .Lfunc_end4-ifftshift_kernel_r
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: fftshift_half_hermitian
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: fftshift_half_hermitian.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: fftshift_kernel_cx
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: fftshift_kernel_cx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: ifftshift_kernel_cx
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: ifftshift_kernel_cx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: fftshift_kernel_r
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: fftshift_kernel_r.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: ifftshift_kernel_r
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: ifftshift_kernel_r.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
// Launch configuration should be as follows:
// 1. blocks of dim3(threads_per_dim, threads_per_dim, 1) size
// where threads_per_dim = min(N, 16)
// 2. grid of dim3((N+threads_per_dim-1)/threads_per_dim, (N-1)/(threads_per_dim * 2)+1, 1) blocks
template <class T>
static __device__ __inline__
void fftshift_kernel_common(T* data, int shift, int N, int pitch){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x > N-1 || y > (N+1)/2-1) return;
int x1 = x + shift;
if (x1 > N-1) x1 -= N;
int y1 = y + shift;
if (y1 > N-1) y1 -= N;
int
i = x + y * pitch
, i1 = x1 + y1 * pitch;
T tmp;
tmp = data[i];
data[i] = data[i1];
data[i1] = tmp;
}
extern "C" {
__global__
void fftshift_half_hermitian(hipDoubleComplex* data, int N, int pitch) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= N/4 || y >= N) return;
// shift+mirror
int x1 = N/2 - x - 1; // N - (N + N/2) - 1
int y1 = N/2 - y - 1; // N - (N + N/2) - 1
if (y1 < 0) y1 += N;
// offsets
int i = x+y*pitch,
i1 = x1+y1*pitch;
// Swap + conjugate (note that x == N/2-x1-1!)
hipDoubleComplex tmp;
tmp = data[i];
data[i].x = data[i1].x;
data[i].y = -data[i1].y;
data[i1].x = tmp.x;
data[i1].y = -tmp.y;
}
__global__
void fftshift_kernel_cx(hipDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<hipDoubleComplex>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_cx(hipDoubleComplex* data, int N, int pitch) {
fftshift_kernel_common<hipDoubleComplex>(data, N/2 + N%2, N, pitch);
}
__global__
void fftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2, N, pitch);
}
__global__
void ifftshift_kernel_r(double* data, int N, int pitch) {
fftshift_kernel_common<double>(data, N/2 + N%2, N, pitch);
}
} | .text
.file "cufftshift.hip"
.globl __device_stub__fftshift_half_hermitian # -- Begin function __device_stub__fftshift_half_hermitian
.p2align 4, 0x90
.type __device_stub__fftshift_half_hermitian,@function
__device_stub__fftshift_half_hermitian: # @__device_stub__fftshift_half_hermitian
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $fftshift_half_hermitian, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__fftshift_half_hermitian, .Lfunc_end0-__device_stub__fftshift_half_hermitian
.cfi_endproc
# -- End function
.globl __device_stub__fftshift_kernel_cx # -- Begin function __device_stub__fftshift_kernel_cx
.p2align 4, 0x90
.type __device_stub__fftshift_kernel_cx,@function
__device_stub__fftshift_kernel_cx: # @__device_stub__fftshift_kernel_cx
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $fftshift_kernel_cx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__fftshift_kernel_cx, .Lfunc_end1-__device_stub__fftshift_kernel_cx
.cfi_endproc
# -- End function
.globl __device_stub__ifftshift_kernel_cx # -- Begin function __device_stub__ifftshift_kernel_cx
.p2align 4, 0x90
.type __device_stub__ifftshift_kernel_cx,@function
__device_stub__ifftshift_kernel_cx: # @__device_stub__ifftshift_kernel_cx
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $ifftshift_kernel_cx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__ifftshift_kernel_cx, .Lfunc_end2-__device_stub__ifftshift_kernel_cx
.cfi_endproc
# -- End function
.globl __device_stub__fftshift_kernel_r # -- Begin function __device_stub__fftshift_kernel_r
.p2align 4, 0x90
.type __device_stub__fftshift_kernel_r,@function
__device_stub__fftshift_kernel_r: # @__device_stub__fftshift_kernel_r
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $fftshift_kernel_r, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__fftshift_kernel_r, .Lfunc_end3-__device_stub__fftshift_kernel_r
.cfi_endproc
# -- End function
.globl __device_stub__ifftshift_kernel_r # -- Begin function __device_stub__ifftshift_kernel_r
.p2align 4, 0x90
.type __device_stub__ifftshift_kernel_r,@function
__device_stub__ifftshift_kernel_r: # @__device_stub__ifftshift_kernel_r
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $ifftshift_kernel_r, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size __device_stub__ifftshift_kernel_r, .Lfunc_end4-__device_stub__ifftshift_kernel_r
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fftshift_half_hermitian, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fftshift_kernel_cx, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ifftshift_kernel_cx, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fftshift_kernel_r, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ifftshift_kernel_r, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type fftshift_half_hermitian,@object # @fftshift_half_hermitian
.section .rodata,"a",@progbits
.globl fftshift_half_hermitian
.p2align 3, 0x0
fftshift_half_hermitian:
.quad __device_stub__fftshift_half_hermitian
.size fftshift_half_hermitian, 8
.type fftshift_kernel_cx,@object # @fftshift_kernel_cx
.globl fftshift_kernel_cx
.p2align 3, 0x0
fftshift_kernel_cx:
.quad __device_stub__fftshift_kernel_cx
.size fftshift_kernel_cx, 8
.type ifftshift_kernel_cx,@object # @ifftshift_kernel_cx
.globl ifftshift_kernel_cx
.p2align 3, 0x0
ifftshift_kernel_cx:
.quad __device_stub__ifftshift_kernel_cx
.size ifftshift_kernel_cx, 8
.type fftshift_kernel_r,@object # @fftshift_kernel_r
.globl fftshift_kernel_r
.p2align 3, 0x0
fftshift_kernel_r:
.quad __device_stub__fftshift_kernel_r
.size fftshift_kernel_r, 8
.type ifftshift_kernel_r,@object # @ifftshift_kernel_r
.globl ifftshift_kernel_r
.p2align 3, 0x0
ifftshift_kernel_r:
.quad __device_stub__ifftshift_kernel_r
.size ifftshift_kernel_r, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "fftshift_half_hermitian"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "fftshift_kernel_cx"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "ifftshift_kernel_cx"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "fftshift_kernel_r"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "ifftshift_kernel_r"
.size .L__unnamed_5, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__fftshift_half_hermitian
.addrsig_sym __device_stub__fftshift_kernel_cx
.addrsig_sym __device_stub__ifftshift_kernel_cx
.addrsig_sym __device_stub__fftshift_kernel_r
.addrsig_sym __device_stub__ifftshift_kernel_r
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fftshift_half_hermitian
.addrsig_sym fftshift_kernel_cx
.addrsig_sym ifftshift_kernel_cx
.addrsig_sym fftshift_kernel_r
.addrsig_sym ifftshift_kernel_r
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098201_00000000-6_cufftshift.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii
.type _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii, @function
_Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii:
.LFB2075:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq fftshift_half_hermitian(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii, .-_Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii
.globl fftshift_half_hermitian
.type fftshift_half_hermitian, @function
fftshift_half_hermitian:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z23fftshift_half_hermitianP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size fftshift_half_hermitian, .-fftshift_half_hermitian
.globl _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii
.type _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii, @function
_Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii:
.LFB2077:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq fftshift_kernel_cx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii, .-_Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii
.globl fftshift_kernel_cx
.type fftshift_kernel_cx, @function
fftshift_kernel_cx:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z18fftshift_kernel_cxP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size fftshift_kernel_cx, .-fftshift_kernel_cx
.globl _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii
.type _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii, @function
_Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii:
.LFB2079:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq ifftshift_kernel_cx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii, .-_Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii
.globl ifftshift_kernel_cx
.type ifftshift_kernel_cx, @function
ifftshift_kernel_cx:
.LFB2080:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z19ifftshift_kernel_cxP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size ifftshift_kernel_cx, .-ifftshift_kernel_cx
.globl _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii
.type _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii, @function
_Z39__device_stub__Z17fftshift_kernel_rPdiiPdii:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq fftshift_kernel_r(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii, .-_Z39__device_stub__Z17fftshift_kernel_rPdiiPdii
.globl fftshift_kernel_r
.type fftshift_kernel_r, @function
fftshift_kernel_r:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17fftshift_kernel_rPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size fftshift_kernel_r, .-fftshift_kernel_r
.globl _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii
.type _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii, @function
_Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq ifftshift_kernel_r(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii, .-_Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii
.globl ifftshift_kernel_r
.type ifftshift_kernel_r, @function
ifftshift_kernel_r:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18ifftshift_kernel_rPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size ifftshift_kernel_r, .-ifftshift_kernel_r
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ifftshift_kernel_r"
.LC1:
.string "fftshift_kernel_r"
.LC2:
.string "ifftshift_kernel_cx"
.LC3:
.string "fftshift_kernel_cx"
.LC4:
.string "fftshift_half_hermitian"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ifftshift_kernel_r(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq fftshift_kernel_r(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq ifftshift_kernel_cx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq fftshift_kernel_cx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq fftshift_half_hermitian(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cufftshift.hip"
.globl __device_stub__fftshift_half_hermitian # -- Begin function __device_stub__fftshift_half_hermitian
.p2align 4, 0x90
.type __device_stub__fftshift_half_hermitian,@function
__device_stub__fftshift_half_hermitian: # @__device_stub__fftshift_half_hermitian
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $fftshift_half_hermitian, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__fftshift_half_hermitian, .Lfunc_end0-__device_stub__fftshift_half_hermitian
.cfi_endproc
# -- End function
.globl __device_stub__fftshift_kernel_cx # -- Begin function __device_stub__fftshift_kernel_cx
.p2align 4, 0x90
.type __device_stub__fftshift_kernel_cx,@function
__device_stub__fftshift_kernel_cx: # @__device_stub__fftshift_kernel_cx
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $fftshift_kernel_cx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__fftshift_kernel_cx, .Lfunc_end1-__device_stub__fftshift_kernel_cx
.cfi_endproc
# -- End function
.globl __device_stub__ifftshift_kernel_cx # -- Begin function __device_stub__ifftshift_kernel_cx
.p2align 4, 0x90
.type __device_stub__ifftshift_kernel_cx,@function
__device_stub__ifftshift_kernel_cx: # @__device_stub__ifftshift_kernel_cx
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $ifftshift_kernel_cx, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__ifftshift_kernel_cx, .Lfunc_end2-__device_stub__ifftshift_kernel_cx
.cfi_endproc
# -- End function
.globl __device_stub__fftshift_kernel_r # -- Begin function __device_stub__fftshift_kernel_r
.p2align 4, 0x90
.type __device_stub__fftshift_kernel_r,@function
__device_stub__fftshift_kernel_r: # @__device_stub__fftshift_kernel_r
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $fftshift_kernel_r, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__fftshift_kernel_r, .Lfunc_end3-__device_stub__fftshift_kernel_r
.cfi_endproc
# -- End function
.globl __device_stub__ifftshift_kernel_r # -- Begin function __device_stub__ifftshift_kernel_r
.p2align 4, 0x90
.type __device_stub__ifftshift_kernel_r,@function
__device_stub__ifftshift_kernel_r: # @__device_stub__ifftshift_kernel_r
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $ifftshift_kernel_r, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size __device_stub__ifftshift_kernel_r, .Lfunc_end4-__device_stub__ifftshift_kernel_r
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fftshift_half_hermitian, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fftshift_kernel_cx, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ifftshift_kernel_cx, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fftshift_kernel_r, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ifftshift_kernel_r, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type fftshift_half_hermitian,@object # @fftshift_half_hermitian
.section .rodata,"a",@progbits
.globl fftshift_half_hermitian
.p2align 3, 0x0
fftshift_half_hermitian:
.quad __device_stub__fftshift_half_hermitian
.size fftshift_half_hermitian, 8
.type fftshift_kernel_cx,@object # @fftshift_kernel_cx
.globl fftshift_kernel_cx
.p2align 3, 0x0
fftshift_kernel_cx:
.quad __device_stub__fftshift_kernel_cx
.size fftshift_kernel_cx, 8
.type ifftshift_kernel_cx,@object # @ifftshift_kernel_cx
.globl ifftshift_kernel_cx
.p2align 3, 0x0
ifftshift_kernel_cx:
.quad __device_stub__ifftshift_kernel_cx
.size ifftshift_kernel_cx, 8
.type fftshift_kernel_r,@object # @fftshift_kernel_r
.globl fftshift_kernel_r
.p2align 3, 0x0
fftshift_kernel_r:
.quad __device_stub__fftshift_kernel_r
.size fftshift_kernel_r, 8
.type ifftshift_kernel_r,@object # @ifftshift_kernel_r
.globl ifftshift_kernel_r
.p2align 3, 0x0
ifftshift_kernel_r:
.quad __device_stub__ifftshift_kernel_r
.size ifftshift_kernel_r, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "fftshift_half_hermitian"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "fftshift_kernel_cx"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "ifftshift_kernel_cx"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "fftshift_kernel_r"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "ifftshift_kernel_r"
.size .L__unnamed_5, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__fftshift_half_hermitian
.addrsig_sym __device_stub__fftshift_kernel_cx
.addrsig_sym __device_stub__ifftshift_kernel_cx
.addrsig_sym __device_stub__fftshift_kernel_r
.addrsig_sym __device_stub__ifftshift_kernel_r
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fftshift_half_hermitian
.addrsig_sym fftshift_kernel_cx
.addrsig_sym ifftshift_kernel_cx
.addrsig_sym fftshift_kernel_r
.addrsig_sym ifftshift_kernel_r
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <math.h>
#define N 4 //Filas
#define M 4 //Columnas
__global__ void sumaMatrices(float *c, float *a, float *b){ //Kernel, salto a la GPU. Esta funcion es ejecutada por todos los hilos al mismo tiempo.
int i = (blockIdx.y*blockDim.y+threadIdx.y)*N+(blockIdx.x*blockDim.x+threadIdx.x);
c[i]=a[i]+b[i];
}
int main() {
int memsize = sizeof(float )*N*M;
float *h_a,*h_b,*h_c; //Arrays en el host (CPU & RAM)
h_a=(float *)malloc(memsize);
h_b=(float *)malloc(memsize);
h_c=(float *)malloc(memsize);
float *d_a,*d_b,*d_c; //Arrays en la GPU
cudaMalloc(&d_a, memsize);
cudaMalloc(&d_b, memsize);
cudaMalloc(&d_c, memsize);
for(int i=0; i<N*M; ++i)
h_a[i]=h_b[i]=(float) i;
cudaMemcpy(d_a, h_a, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, memsize, cudaMemcpyHostToDevice);
dim3 block(2,2);
dim3 thread(2,2);
printf("El numero de bloques es %d, y el numero de hilos es %d\n", block.x, thread.x);
sumaMatrices <<<block,thread>>> (d_c, d_a, d_b);//El multiplicar ambos numeros tiene que darme N
//Envio el contenido del array(d_c) CONTENIDO ! Al espacio de memoria ya reservado en la CPU(h_c). GPU -> CPU | Device -> Host
cudaMemcpy(h_c, d_c, memsize, cudaMemcpyDeviceToHost);
printf("Resultado del tercer vector, c: \n");
for(int i=0; i<N*M; ++i){
printf("%f, ", h_c[i]);
if(i%N==0)
printf("\n");
}
printf("\n");
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z12sumaMatricesPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0090*/ LEA R0, R0, R3, 0x2 ; /* 0x0000000300007211 */
/* 0x000fca00078e10ff */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <math.h>
#define N 4 //Filas
#define M 4 //Columnas
__global__ void sumaMatrices(float *c, float *a, float *b){ //Kernel, salto a la GPU. Esta funcion es ejecutada por todos los hilos al mismo tiempo.
int i = (blockIdx.y*blockDim.y+threadIdx.y)*N+(blockIdx.x*blockDim.x+threadIdx.x);
c[i]=a[i]+b[i];
}
int main() {
int memsize = sizeof(float )*N*M;
float *h_a,*h_b,*h_c; //Arrays en el host (CPU & RAM)
h_a=(float *)malloc(memsize);
h_b=(float *)malloc(memsize);
h_c=(float *)malloc(memsize);
float *d_a,*d_b,*d_c; //Arrays en la GPU
cudaMalloc(&d_a, memsize);
cudaMalloc(&d_b, memsize);
cudaMalloc(&d_c, memsize);
for(int i=0; i<N*M; ++i)
h_a[i]=h_b[i]=(float) i;
cudaMemcpy(d_a, h_a, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, memsize, cudaMemcpyHostToDevice);
dim3 block(2,2);
dim3 thread(2,2);
printf("El numero de bloques es %d, y el numero de hilos es %d\n", block.x, thread.x);
sumaMatrices <<<block,thread>>> (d_c, d_a, d_b);//El multiplicar ambos numeros tiene que darme N
//Envio el contenido del array(d_c) CONTENIDO ! Al espacio de memoria ya reservado en la CPU(h_c). GPU -> CPU | Device -> Host
cudaMemcpy(h_c, d_c, memsize, cudaMemcpyDeviceToHost);
printf("Resultado del tercer vector, c: \n");
for(int i=0; i<N*M; ++i){
printf("%f, ", h_c[i]);
if(i%N==0)
printf("\n");
}
printf("\n");
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000004f4_00000000-6_sumamatrices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
.type _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_, @function
_Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sumaMatricesPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_, .-_Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
.globl _Z12sumaMatricesPfS_S_
.type _Z12sumaMatricesPfS_S_, @function
_Z12sumaMatricesPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12sumaMatricesPfS_S_, .-_Z12sumaMatricesPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "El numero de bloques es %d, y el numero de hilos es %d\n"
.align 8
.LC1:
.string "Resultado del tercer vector, c: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f, "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %r13
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
movl $1, %ecx
movl $64, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $2, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 32(%rsp)
movl $2, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r15
jmp .L15
.L20:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
jmp .L13
.L14:
addq $1, %rbx
cmpq $16, %rbx
je .L21
.L15:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $3, %bl
jne .L14
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12sumaMatricesPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumaMatricesPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <math.h>
#define N 4 //Filas
#define M 4 //Columnas
__global__ void sumaMatrices(float *c, float *a, float *b){ //Kernel, salto a la GPU. Esta funcion es ejecutada por todos los hilos al mismo tiempo.
int i = (blockIdx.y*blockDim.y+threadIdx.y)*N+(blockIdx.x*blockDim.x+threadIdx.x);
c[i]=a[i]+b[i];
}
int main() {
int memsize = sizeof(float )*N*M;
float *h_a,*h_b,*h_c; //Arrays en el host (CPU & RAM)
h_a=(float *)malloc(memsize);
h_b=(float *)malloc(memsize);
h_c=(float *)malloc(memsize);
float *d_a,*d_b,*d_c; //Arrays en la GPU
cudaMalloc(&d_a, memsize);
cudaMalloc(&d_b, memsize);
cudaMalloc(&d_c, memsize);
for(int i=0; i<N*M; ++i)
h_a[i]=h_b[i]=(float) i;
cudaMemcpy(d_a, h_a, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, memsize, cudaMemcpyHostToDevice);
dim3 block(2,2);
dim3 thread(2,2);
printf("El numero de bloques es %d, y el numero de hilos es %d\n", block.x, thread.x);
sumaMatrices <<<block,thread>>> (d_c, d_a, d_b);//El multiplicar ambos numeros tiene que darme N
//Envio el contenido del array(d_c) CONTENIDO ! Al espacio de memoria ya reservado en la CPU(h_c). GPU -> CPU | Device -> Host
cudaMemcpy(h_c, d_c, memsize, cudaMemcpyDeviceToHost);
printf("Resultado del tercer vector, c: \n");
for(int i=0; i<N*M; ++i){
printf("%f, ", h_c[i]);
if(i%N==0)
printf("\n");
}
printf("\n");
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <math.h>
#define N 4 //Filas
#define M 4 //Columnas
__global__ void sumaMatrices(float *c, float *a, float *b){ //Kernel, salto a la GPU. Esta funcion es ejecutada por todos los hilos al mismo tiempo.
int i = (blockIdx.y*blockDim.y+threadIdx.y)*N+(blockIdx.x*blockDim.x+threadIdx.x);
c[i]=a[i]+b[i];
}
int main() {
int memsize = sizeof(float )*N*M;
float *h_a,*h_b,*h_c; //Arrays en el host (CPU & RAM)
h_a=(float *)malloc(memsize);
h_b=(float *)malloc(memsize);
h_c=(float *)malloc(memsize);
float *d_a,*d_b,*d_c; //Arrays en la GPU
hipMalloc(&d_a, memsize);
hipMalloc(&d_b, memsize);
hipMalloc(&d_c, memsize);
for(int i=0; i<N*M; ++i)
h_a[i]=h_b[i]=(float) i;
hipMemcpy(d_a, h_a, memsize, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, memsize, hipMemcpyHostToDevice);
dim3 block(2,2);
dim3 thread(2,2);
printf("El numero de bloques es %d, y el numero de hilos es %d\n", block.x, thread.x);
sumaMatrices <<<block,thread>>> (d_c, d_a, d_b);//El multiplicar ambos numeros tiene que darme N
//Envio el contenido del array(d_c) CONTENIDO ! Al espacio de memoria ya reservado en la CPU(h_c). GPU -> CPU | Device -> Host
hipMemcpy(h_c, d_c, memsize, hipMemcpyDeviceToHost);
printf("Resultado del tercer vector, c: \n");
for(int i=0; i<N*M; ++i){
printf("%f, ", h_c[i]);
if(i%N==0)
printf("\n");
}
printf("\n");
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <math.h>
#define N 4 //Filas
#define M 4 //Columnas
__global__ void sumaMatrices(float *c, float *a, float *b){ //Kernel, salto a la GPU. Esta funcion es ejecutada por todos los hilos al mismo tiempo.
int i = (blockIdx.y*blockDim.y+threadIdx.y)*N+(blockIdx.x*blockDim.x+threadIdx.x);
c[i]=a[i]+b[i];
}
int main() {
int memsize = sizeof(float )*N*M;
float *h_a,*h_b,*h_c; //Arrays en el host (CPU & RAM)
h_a=(float *)malloc(memsize);
h_b=(float *)malloc(memsize);
h_c=(float *)malloc(memsize);
float *d_a,*d_b,*d_c; //Arrays en la GPU
hipMalloc(&d_a, memsize);
hipMalloc(&d_b, memsize);
hipMalloc(&d_c, memsize);
for(int i=0; i<N*M; ++i)
h_a[i]=h_b[i]=(float) i;
hipMemcpy(d_a, h_a, memsize, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, memsize, hipMemcpyHostToDevice);
dim3 block(2,2);
dim3 thread(2,2);
printf("El numero de bloques es %d, y el numero de hilos es %d\n", block.x, thread.x);
sumaMatrices <<<block,thread>>> (d_c, d_a, d_b);//El multiplicar ambos numeros tiene que darme N
//Envio el contenido del array(d_c) CONTENIDO ! Al espacio de memoria ya reservado en la CPU(h_c). GPU -> CPU | Device -> Host
hipMemcpy(h_c, d_c, memsize, hipMemcpyDeviceToHost);
printf("Resultado del tercer vector, c: \n");
for(int i=0; i<N*M; ++i){
printf("%f, ", h_c[i]);
if(i%N==0)
printf("\n");
}
printf("\n");
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sumaMatricesPfS_S_
.globl _Z12sumaMatricesPfS_S_
.p2align 8
.type _Z12sumaMatricesPfS_S_,@function
_Z12sumaMatricesPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sumaMatricesPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sumaMatricesPfS_S_, .Lfunc_end0-_Z12sumaMatricesPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sumaMatricesPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sumaMatricesPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <math.h>
#define N 4 //Filas
#define M 4 //Columnas
__global__ void sumaMatrices(float *c, float *a, float *b){ //Kernel, salto a la GPU. Esta funcion es ejecutada por todos los hilos al mismo tiempo.
int i = (blockIdx.y*blockDim.y+threadIdx.y)*N+(blockIdx.x*blockDim.x+threadIdx.x);
c[i]=a[i]+b[i];
}
int main() {
int memsize = sizeof(float )*N*M;
float *h_a,*h_b,*h_c; //Arrays en el host (CPU & RAM)
h_a=(float *)malloc(memsize);
h_b=(float *)malloc(memsize);
h_c=(float *)malloc(memsize);
float *d_a,*d_b,*d_c; //Arrays en la GPU
hipMalloc(&d_a, memsize);
hipMalloc(&d_b, memsize);
hipMalloc(&d_c, memsize);
for(int i=0; i<N*M; ++i)
h_a[i]=h_b[i]=(float) i;
hipMemcpy(d_a, h_a, memsize, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, memsize, hipMemcpyHostToDevice);
dim3 block(2,2);
dim3 thread(2,2);
printf("El numero de bloques es %d, y el numero de hilos es %d\n", block.x, thread.x);
sumaMatrices <<<block,thread>>> (d_c, d_a, d_b);//El multiplicar ambos numeros tiene que darme N
//Envio el contenido del array(d_c) CONTENIDO ! Al espacio de memoria ya reservado en la CPU(h_c). GPU -> CPU | Device -> Host
hipMemcpy(h_c, d_c, memsize, hipMemcpyDeviceToHost);
printf("Resultado del tercer vector, c: \n");
for(int i=0; i<N*M; ++i){
printf("%f, ", h_c[i]);
if(i%N==0)
printf("\n");
}
printf("\n");
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "sumamatrices.hip"
.globl _Z27__device_stub__sumaMatricesPfS_S_ # -- Begin function _Z27__device_stub__sumaMatricesPfS_S_
.p2align 4, 0x90
.type _Z27__device_stub__sumaMatricesPfS_S_,@function
_Z27__device_stub__sumaMatricesPfS_S_: # @_Z27__device_stub__sumaMatricesPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumaMatricesPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__sumaMatricesPfS_S_, .Lfunc_end0-_Z27__device_stub__sumaMatricesPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $2, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sumaMatricesPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r12
cmpq $16, %r12
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
testb $3, %r12b
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumaMatricesPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sumaMatricesPfS_S_,@object # @_Z12sumaMatricesPfS_S_
.section .rodata,"a",@progbits
.globl _Z12sumaMatricesPfS_S_
.p2align 3, 0x0
_Z12sumaMatricesPfS_S_:
.quad _Z27__device_stub__sumaMatricesPfS_S_
.size _Z12sumaMatricesPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "El numero de bloques es %d, y el numero de hilos es %d\n"
.size .L.str, 56
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f, "
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sumaMatricesPfS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Resultado del tercer vector, c: "
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sumaMatricesPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sumaMatricesPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12sumaMatricesPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0090*/ LEA R0, R0, R3, 0x2 ; /* 0x0000000300007211 */
/* 0x000fca00078e10ff */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sumaMatricesPfS_S_
.globl _Z12sumaMatricesPfS_S_
.p2align 8
.type _Z12sumaMatricesPfS_S_,@function
_Z12sumaMatricesPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sumaMatricesPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sumaMatricesPfS_S_, .Lfunc_end0-_Z12sumaMatricesPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sumaMatricesPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sumaMatricesPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000004f4_00000000-6_sumamatrices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
.type _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_, @function
_Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sumaMatricesPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_, .-_Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
.globl _Z12sumaMatricesPfS_S_
.type _Z12sumaMatricesPfS_S_, @function
_Z12sumaMatricesPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12sumaMatricesPfS_S_, .-_Z12sumaMatricesPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "El numero de bloques es %d, y el numero de hilos es %d\n"
.align 8
.LC1:
.string "Resultado del tercer vector, c: \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f, "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %r13
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
movl $1, %ecx
movl $64, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $2, 48(%rsp)
movl $1, 52(%rsp)
movl $2, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 32(%rsp)
movl $2, 44(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r15
jmp .L15
.L20:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z12sumaMatricesPfS_S_PfS_S_
jmp .L13
.L14:
addq $1, %rbx
cmpq $16, %rbx
je .L21
.L15:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $3, %bl
jne .L14
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12sumaMatricesPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumaMatricesPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumamatrices.hip"
.globl _Z27__device_stub__sumaMatricesPfS_S_ # -- Begin function _Z27__device_stub__sumaMatricesPfS_S_
.p2align 4, 0x90
.type _Z27__device_stub__sumaMatricesPfS_S_,@function
_Z27__device_stub__sumaMatricesPfS_S_: # @_Z27__device_stub__sumaMatricesPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumaMatricesPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__sumaMatricesPfS_S_, .Lfunc_end0-_Z27__device_stub__sumaMatricesPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $2, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sumaMatricesPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r12
cmpq $16, %r12
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
testb $3, %r12b
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumaMatricesPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sumaMatricesPfS_S_,@object # @_Z12sumaMatricesPfS_S_
.section .rodata,"a",@progbits
.globl _Z12sumaMatricesPfS_S_
.p2align 3, 0x0
_Z12sumaMatricesPfS_S_:
.quad _Z27__device_stub__sumaMatricesPfS_S_
.size _Z12sumaMatricesPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "El numero de bloques es %d, y el numero de hilos es %d\n"
.size .L.str, 56
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f, "
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sumaMatricesPfS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Resultado del tercer vector, c: "
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sumaMatricesPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sumaMatricesPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include "cuda.h"
void StartKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream);
void StopKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream, float* ptimer);
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h );
int main(int argc , char *argv[])
{
if(argc != 3)
{
printf("\n Usage: %s <HEIGHT> <WIDTH> \n",argv[0]);
return 1;
}
int h=atoi(argv[1]);
int w=atoi(argv[2]);
int n;
const unsigned int THREADS_PER_BLOCK = 512;
double *hostMat = (double*) calloc(h*w, sizeof(double));
double *hostVec = (double*) calloc(w, sizeof(double));
double *hostResVec = (double*) calloc(w, sizeof(double));
for(n=0;n<h*w;++n){
hostMat[n]=rand() % 100;
}
for(n=0;n<w;++n)
{
hostVec[n] = rand() % 100;
}
// allocate memory
double *gpuMat, *gpuVec, *gpuResVec;
cudaMalloc( (void**)&gpuMat, w*h* sizeof(double) );
cudaMalloc( (void**)&gpuVec, w * sizeof(double) );
cudaMalloc( (void**)&gpuResVec, h * sizeof(double) );
// upload M and x
cudaMemcpy( gpuMat, (void*) hostMat, w*h * sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy( gpuVec, (void*) hostVec, w * sizeof(double),cudaMemcpyHostToDevice );
// compute the block and grid dimensions
dim3 threadBlock( THREADS_PER_BLOCK, 1 );
const unsigned int numBlocks = (n - 1)/THREADS_PER_BLOCK + 1;
dim3 blockGrid( numBlocks, 1, 1);
//xronometrhsh
cudaEvent_t tic, toc;
float elapsed_time = 0.f;
StartKernelTiming(tic, toc, 0);
vecMat1<<< blockGrid, threadBlock >>>( gpuResVec, gpuMat, gpuVec,w,h);
cudaThreadSynchronize() ;
// download result y
cudaMemcpy( hostResVec, gpuResVec, h * sizeof(double), cudaMemcpyDeviceToHost) ;
StopKernelTiming(tic,toc, 0, &elapsed_time); /*telos xronometrhshs*/
/*int k=0;
for(k=0; k<h; k++)
{
printf("gpu: %f\n", hostResVec[k]);
/*}
/* convert from miliseconds to seconds */
elapsed_time /= 1000.0;
/* output elapsed time */
printf("elapsed time:%g sec \n", elapsed_time);
cudaFree( gpuMat );
cudaFree( gpuVec );
cudaFree( gpuResVec );
free(hostMat);
free(hostVec);
free(hostResVec);
}
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h )
{
// row index the thread is operating on
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < _h) {
float res = 0.;
// dot product of one line
for (int j = 0; j < _w; ++j) {
res += _mat[i*_w + j] * _v[j];
}
// write result to global memory
_dst[i] = res;
}
}
void StartKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream)
{
cudaEventCreate(&tic);
cudaEventCreate(&toc);
cudaEventRecord(tic, iStream);
}
void StopKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream, float* ptimer)
{
float kt;
cudaEventRecord(toc, iStream);
cudaEventSynchronize(toc);
cudaEventElapsedTime(&kt, tic, toc);
cudaEventDestroy(tic); cudaEventDestroy(toc);
(*ptimer) += kt;
} | code for sm_80
Function : _Z7vecMat1PdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fc6000001ff00 */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xde0 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*00e0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0xc60 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R3, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002037a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0140*/ IMAD R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0205 */
/*01a0*/ @!P0 BRA 0xaa0 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x770 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E.64 R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000ea8000c1e1b00 */
/*0200*/ LDG.E.64 R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x000ea8000c1e1b00 */
/*0210*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ee8000c1e1b00 */
/*0220*/ LDG.E.64 R26, [R4.64+0x8] ; /* 0x00000804041a7981 */
/* 0x000ee8000c1e1b00 */
/*0230*/ LDG.E.64 R10, [R6.64+0x10] ; /* 0x00001004060a7981 */
/* 0x000f28000c1e1b00 */
/*0240*/ LDG.E.64 R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000f28000c1e1b00 */
/*0250*/ LDG.E.64 R8, [R6.64+0x18] ; /* 0x0000180406087981 */
/* 0x001f68000c1e1b00 */
/*0260*/ LDG.E.64 R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000f62000c1e1b00 */
/*0270*/ DFMA R24, R14, R24, R20 ; /* 0x000000180e18722b */
/* 0x0060460000000014 */
/*0280*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x001ea8000c1e1b00 */
/*0290*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ea2000c1e1b00 */
/*02a0*/ F2F.F32.F64 R28, R24 ; /* 0x00000018001c7310 */
/* 0x0020660000301000 */
/*02b0*/ LDG.E.64 R24, [R6.64+0x28] ; /* 0x0000280406187981 */
/* 0x001eaa000c1e1b00 */
/*02c0*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x002ee40000201800 */
/*02d0*/ DFMA R26, R12, R26, R16 ; /* 0x0000001a0c1a722b */
/* 0x0080440000000010 */
/*02e0*/ LDG.E.64 R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x001ef0000c1e1b00 */
/*02f0*/ F2F.F32.F64 R26, R26 ; /* 0x0000001a001a7310 */
/* 0x002e300000301000 */
/*0300*/ F2F.F64.F32 R16, R26 ; /* 0x0000001a00107310 */
/* 0x0011240000201800 */
/*0310*/ LDG.E.64 R26, [R6.64+0x30] ; /* 0x00003004061a7981 */
/* 0x001ee2000c1e1b00 */
/*0320*/ DFMA R22, R10, R22, R16 ; /* 0x000000160a16722b */
/* 0x0100460000000010 */
/*0330*/ LDG.E.64 R10, [R4.64+0x30] ; /* 0x00003004040a7981 */
/* 0x001f2e000c1e1b00 */
/*0340*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x002e300000301000 */
/*0350*/ F2F.F64.F32 R16, R22 ; /* 0x0000001600107310 */
/* 0x0011640000201800 */
/*0360*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001f22000c1e1b00 */
/*0370*/ DFMA R18, R8, R18, R16 ; /* 0x000000120812722b */
/* 0x0200460000000010 */
/*0380*/ LDG.E.64 R8, [R4.64+0x38] ; /* 0x0000380404087981 */
/* 0x001f66000c1e1b00 */
/*0390*/ F2F.F32.F64 R28, R18 ; /* 0x00000012001c7310 */
/* 0x0020680000301000 */
/*03a0*/ LDG.E.64 R18, [R6.64+0x40] ; /* 0x0000400406127981 */
/* 0x001f68000c1e1b00 */
/*03b0*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x002ea40000201800 */
/*03c0*/ DFMA R20, R20, R14, R16 ; /* 0x0000000e1414722b */
/* 0x0040440000000010 */
/*03d0*/ LDG.E.64 R16, [R4.64+0x40] ; /* 0x0000400404107981 */
/* 0x001ea8000c1e1b00 */
/*03e0*/ F2F.F32.F64 R14, R20 ; /* 0x00000014000e7310 */
/* 0x002e300000301000 */
/*03f0*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001ee40000201800 */
/*0400*/ DFMA R24, R24, R12, R14 ; /* 0x0000000c1818722b */
/* 0x008044000000000e */
/*0410*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001ee8000c1e1b00 */
/*0420*/ LDG.E.64 R12, [R4.64+0x48] ; /* 0x00004804040c7981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x002e300000301000 */
/*0440*/ F2F.F64.F32 R20, R24 ; /* 0x0000001800147310 */
/* 0x0011240000201800 */
/*0450*/ LDG.E.64 R24, [R6.64+0x50] ; /* 0x0000500406187981 */
/* 0x001ee2000c1e1b00 */
/*0460*/ DFMA R26, R26, R10, R20 ; /* 0x0000000a1a1a722b */
/* 0x0100460000000014 */
/*0470*/ LDG.E.64 R10, [R4.64+0x50] ; /* 0x00005004040a7981 */
/* 0x001f26000c1e1b00 */
/*0480*/ F2F.F32.F64 R28, R26 ; /* 0x0000001a001c7310 */
/* 0x0020680000301000 */
/*0490*/ LDG.E.64 R26, [R6.64+0x58] ; /* 0x00005804061a7981 */
/* 0x001f28000c1e1b00 */
/*04a0*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x002f640000201800 */
/*04b0*/ DFMA R22, R22, R8, R20 ; /* 0x000000081616722b */
/* 0x0200440000000014 */
/*04c0*/ LDG.E.64 R8, [R4.64+0x58] ; /* 0x0000580404087981 */
/* 0x001f68000c1e1b00 */
/*04d0*/ F2F.F32.F64 R20, R22 ; /* 0x0000001600147310 */
/* 0x0020680000301000 */
/*04e0*/ LDG.E.64 R22, [R4.64+0x60] ; /* 0x0000600404167981 */
/* 0x001f68000c1e1b00 */
/*04f0*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x002ea40000201800 */
/*0500*/ DFMA R18, R18, R16, R20 ; /* 0x000000101212722b */
/* 0x0040440000000014 */
/*0510*/ LDG.E.64 R20, [R6.64+0x60] ; /* 0x0000600406147981 */
/* 0x001ea8000c1e1b00 */
/*0520*/ F2F.F32.F64 R16, R18 ; /* 0x0000001200107310 */
/* 0x0020680000301000 */
/*0530*/ LDG.E.64 R18, [R4.64+0x68] ; /* 0x0000680404127981 */
/* 0x001ea8000c1e1b00 */
/*0540*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x002ee40000201800 */
/*0550*/ DFMA R14, R14, R12, R16 ; /* 0x0000000c0e0e722b */
/* 0x0080440000000010 */
/*0560*/ LDG.E.64 R16, [R6.64+0x68] ; /* 0x0000680406107981 */
/* 0x001ee8000c1e1b00 */
/*0570*/ F2F.F32.F64 R28, R14 ; /* 0x0000000e001c7310 */
/* 0x0020680000301000 */
/*0580*/ LDG.E.64 R14, [R4.64+0x70] ; /* 0x00007004040e7981 */
/* 0x001ee8000c1e1b00 */
/*0590*/ F2F.F64.F32 R12, R28 ; /* 0x0000001c000c7310 */
/* 0x002f240000201800 */
/*05a0*/ DFMA R24, R24, R10, R12 ; /* 0x0000000a1818722b */
/* 0x010044000000000c */
/*05b0*/ LDG.E.64 R12, [R6.64+0x70] ; /* 0x00007004060c7981 */
/* 0x001f28000c1e1b00 */
/*05c0*/ F2F.F32.F64 R10, R24 ; /* 0x00000018000a7310 */
/* 0x002e300000301000 */
/*05d0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001f640000201800 */
/*05e0*/ DFMA R26, R26, R8, R10 ; /* 0x000000081a1a722b */
/* 0x020044000000000a */
/*05f0*/ LDG.E.64 R8, [R6.64+0x78] ; /* 0x0000780406087981 */
/* 0x001f68000c1e1b00 */
/*0600*/ LDG.E.64 R10, [R4.64+0x78] ; /* 0x00007804040a7981 */
/* 0x000f68000c1e1b00 */
/*0610*/ F2F.F32.F64 R26, R26 ; /* 0x0000001a001a7310 */
/* 0x002e300000301000 */
/*0620*/ F2F.F64.F32 R24, R26 ; /* 0x0000001a00187310 */
/* 0x001ea20000201800 */
/*0630*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fc80007ffe0ff */
/*0640*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe20003f24270 */
/*0650*/ DFMA R20, R20, R22, R24 ; /* 0x000000161414722b */
/* 0x004e0c0000000018 */
/*0660*/ F2F.F32.F64 R22, R20 ; /* 0x0000001400167310 */
/* 0x001e300000301000 */
/*0670*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x001ee40000201800 */
/*0680*/ DFMA R16, R16, R18, R22 ; /* 0x000000121010722b */
/* 0x008e140000000016 */
/*0690*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*06a0*/ F2F.F64.F32 R18, R16 ; /* 0x0000001000127310 */
/* 0x001f240000201800 */
/*06b0*/ DFMA R12, R12, R14, R18 ; /* 0x0000000e0c0c722b */
/* 0x010e140000000012 */
/*06c0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*06d0*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001f640000201800 */
/*06e0*/ DFMA R8, R8, R10, R14 ; /* 0x0000000a0808722b */
/* 0x020e14000000000e */
/*06f0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e220000301000 */
/*0700*/ IADD3 R6, P3, R6, 0x80, RZ ; /* 0x0000008006067810 */
/* 0x000fe40007f7e0ff */
/*0710*/ IADD3 R4, P2, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x000fca0007f5e0ff */
/*0720*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x0010620000201800 */
/*0730*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0607 */
/*0740*/ IADD3 R29, R29, 0x10, RZ ; /* 0x000000101d1d7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0760*/ @P1 BRA 0x1f0 ; /* 0xfffffa8000001947 */
/* 0x000fea000383ffff */
/*0770*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*0780*/ @!P1 BRA 0xa80 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E.64 R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea8000c1e1b00 */
/*07a0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ee8000c1e1b00 */
/*07c0*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee8000c1e1b00 */
/*07d0*/ LDG.E.64 R26, [R6.64+0x10] ; /* 0x00001004061a7981 */
/* 0x000f28000c1e1b00 */
/*07e0*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000f28000c1e1b00 */
/*07f0*/ LDG.E.64 R24, [R6.64+0x18] ; /* 0x0000180406187981 */
/* 0x000ee8000c1e1b00 */
/*0800*/ LDG.E.64 R8, [R4.64+0x18] ; /* 0x0000180404087981 */
/* 0x001ee8000c1e1b00 */
/*0810*/ LDG.E.64 R22, [R4.64+0x20] ; /* 0x0000200404167981 */
/* 0x0000e2000c1e1b00 */
/*0820*/ DFMA R18, R18, R16, R20 ; /* 0x000000101212722b */
/* 0x0062860000000014 */
/*0830*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x002366000c1e1b00 */
/*0840*/ F2F.F32.F64 R28, R18 ; /* 0x00000012001c7310 */
/* 0x0044280000301000 */
/*0850*/ LDG.E.64 R18, [R4.64+0x28] ; /* 0x0000280404127981 */
/* 0x004568000c1e1b00 */
/*0860*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x001ee40000201800 */
/*0870*/ DFMA R14, R14, R12, R16 ; /* 0x0000000c0e0e722b */
/* 0x0080c40000000010 */
/*0880*/ LDG.E.64 R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x001368000c1e1b00 */
/*0890*/ F2F.F32.F64 R12, R14 ; /* 0x0000000e000c7310 */
/* 0x0080e80000301000 */
/*08a0*/ LDG.E.64 R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x001568000c1e1b00 */
/*08b0*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x008f240000201800 */
/*08c0*/ DFMA R26, R26, R10, R12 ; /* 0x0000000a1a1a722b */
/* 0x0100c4000000000c */
/*08d0*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x001328000c1e1b00 */
/*08e0*/ F2F.F32.F64 R10, R26 ; /* 0x0000001a000a7310 */
/* 0x008e300000301000 */
/*08f0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e240000201800 */
/*0900*/ DFMA R24, R24, R8, R10 ; /* 0x000000081818722b */
/* 0x0010c4000000000a */
/*0910*/ LDG.E.64 R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x001328000c1e1b00 */
/*0920*/ LDG.E.64 R10, [R4.64+0x38] ; /* 0x00003804040a7981 */
/* 0x000528000c1e1b00 */
/*0930*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x008e300000301000 */
/*0940*/ F2F.F64.F32 R26, R24 ; /* 0x00000018001a7310 */
/* 0x001f620000201800 */
/*0950*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x004fc40007f3e0ff */
/*0960*/ IADD3 R6, P2, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x002fe20007f5e0ff */
/*0970*/ DFMA R22, R20, R22, R26 ; /* 0x000000161416722b */
/* 0x020e14000000001a */
/*0980*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x001e300000301000 */
/*0990*/ F2F.F64.F32 R20, R22 ; /* 0x0000001600147310 */
/* 0x001e240000201800 */
/*09a0*/ DFMA R16, R16, R18, R20 ; /* 0x000000121010722b */
/* 0x001e140000000014 */
/*09b0*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*09c0*/ F2F.F64.F32 R18, R16 ; /* 0x0000001000127310 */
/* 0x001f240000201800 */
/*09d0*/ DFMA R12, R12, R14, R18 ; /* 0x0000000e0c0c722b */
/* 0x010e140000000012 */
/*09e0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*09f0*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0a00*/ DFMA R8, R8, R10, R14 ; /* 0x0000000a0808722b */
/* 0x001e14000000000e */
/*0a10*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e220000301000 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0a40*/ IADD3 R29, R29, 0x8, RZ ; /* 0x000000081d1d7810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fc800010e0607 */
/*0a60*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x0010620000201800 */
/*0a70*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fce0007ffe0ff */
/*0a80*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0a90*/ @!P0 BRA 0xc60 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E.64 R24, [R6.64] ; /* 0x0000000406187981 */
/* 0x0004e8000c1e1b00 */
/*0ab0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0010e8000c1e1b00 */
/*0ac0*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000528000c1e1b00 */
/*0ad0*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000128000c1e1b00 */
/*0ae0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000568000c1e1b00 */
/*0af0*/ LDG.E.64 R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000168000c1e1b00 */
/*0b00*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x000528000c1e1b00 */
/*0b10*/ LDG.E.64 R22, [R4.64+0x18] ; /* 0x0000180404167981 */
/* 0x000122000c1e1b00 */
/*0b20*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fc40007ffe0ff */
/*0b30*/ IADD3 R29, R29, 0x4, RZ ; /* 0x000000041d1d7810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0b50*/ IADD3 R6, P2, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x004fe40007f5e0ff */
/*0b60*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fc60007f3e0ff */
/*0b70*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0b80*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0b90*/ DFMA R8, R24, R8, R20 ; /* 0x000000081808722b */
/* 0x00ae140000000014 */
/*0ba0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*0bb0*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x001f240000201800 */
/*0bc0*/ DFMA R10, R10, R12, R20 ; /* 0x0000000c0a0a722b */
/* 0x010e140000000014 */
/*0bd0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0be0*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */
/* 0x001f640000201800 */
/*0bf0*/ DFMA R12, R14, R16, R12 ; /* 0x000000100e0c722b */
/* 0x020e14000000000c */
/*0c00*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0c10*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0c20*/ DFMA R14, R18, R22, R14 ; /* 0x00000016120e722b */
/* 0x001e14000000000e */
/*0c30*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*0c40*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x0010640000201800 */
/*0c50*/ @P0 BRA 0xaa0 ; /* 0xfffffe4000000947 */
/* 0x003fea000383ffff */
/*0c60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0c70*/ @!P0 BRA 0xde0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0c80*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*0c90*/ IMAD R6, R0, c[0x0][0x178], R29 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e021d */
/*0ca0*/ IMAD.WIDE R4, R29, R7, c[0x0][0x170] ; /* 0x00005c001d047625 */
/* 0x000fc800078e0207 */
/*0cb0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0207 */
/*0cc0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0004 */
/*0cd0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0ce0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0cf0*/ IMAD.MOV.U32 R10, RZ, RZ, R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0007 */
/*0d00*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0003 */
/*0d10*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0010a2000c1e1b00 */
/*0d20*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e000a */
/*0d30*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0d40*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0d60*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x001fe40007f3e0ff */
/*0d70*/ IADD3 R3, P2, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fc60007f5e0ff */
/*0d80*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*0d90*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200010e060a */
/*0da0*/ DFMA R4, R4, R6, R20 ; /* 0x000000060404722b */
/* 0x006e140000000014 */
/*0db0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x001e300000301000 */
/*0dc0*/ F2F.F64.F32 R20, R4 ; /* 0x0000000400147310 */
/* 0x0010620000201800 */
/*0dd0*/ @P0 BRA 0xd00 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0de0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0df0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0e00*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101b04 */
/*0e10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include "cuda.h"
void StartKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream);
void StopKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream, float* ptimer);
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h );
int main(int argc , char *argv[])
{
if(argc != 3)
{
printf("\n Usage: %s <HEIGHT> <WIDTH> \n",argv[0]);
return 1;
}
int h=atoi(argv[1]);
int w=atoi(argv[2]);
int n;
const unsigned int THREADS_PER_BLOCK = 512;
double *hostMat = (double*) calloc(h*w, sizeof(double));
double *hostVec = (double*) calloc(w, sizeof(double));
double *hostResVec = (double*) calloc(w, sizeof(double));
for(n=0;n<h*w;++n){
hostMat[n]=rand() % 100;
}
for(n=0;n<w;++n)
{
hostVec[n] = rand() % 100;
}
// allocate memory
double *gpuMat, *gpuVec, *gpuResVec;
cudaMalloc( (void**)&gpuMat, w*h* sizeof(double) );
cudaMalloc( (void**)&gpuVec, w * sizeof(double) );
cudaMalloc( (void**)&gpuResVec, h * sizeof(double) );
// upload M and x
cudaMemcpy( gpuMat, (void*) hostMat, w*h * sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy( gpuVec, (void*) hostVec, w * sizeof(double),cudaMemcpyHostToDevice );
// compute the block and grid dimensions
dim3 threadBlock( THREADS_PER_BLOCK, 1 );
const unsigned int numBlocks = (n - 1)/THREADS_PER_BLOCK + 1;
dim3 blockGrid( numBlocks, 1, 1);
//xronometrhsh
cudaEvent_t tic, toc;
float elapsed_time = 0.f;
StartKernelTiming(tic, toc, 0);
vecMat1<<< blockGrid, threadBlock >>>( gpuResVec, gpuMat, gpuVec,w,h);
cudaThreadSynchronize() ;
// download result y
cudaMemcpy( hostResVec, gpuResVec, h * sizeof(double), cudaMemcpyDeviceToHost) ;
StopKernelTiming(tic,toc, 0, &elapsed_time); /*telos xronometrhshs*/
/*int k=0;
for(k=0; k<h; k++)
{
printf("gpu: %f\n", hostResVec[k]);
/*}
/* convert from miliseconds to seconds */
elapsed_time /= 1000.0;
/* output elapsed time */
printf("elapsed time:%g sec \n", elapsed_time);
cudaFree( gpuMat );
cudaFree( gpuVec );
cudaFree( gpuResVec );
free(hostMat);
free(hostVec);
free(hostResVec);
}
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h )
{
// row index the thread is operating on
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < _h) {
float res = 0.;
// dot product of one line
for (int j = 0; j < _w; ++j) {
res += _mat[i*_w + j] * _v[j];
}
// write result to global memory
_dst[i] = res;
}
}
void StartKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream)
{
cudaEventCreate(&tic);
cudaEventCreate(&toc);
cudaEventRecord(tic, iStream);
}
void StopKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream, float* ptimer)
{
float kt;
cudaEventRecord(toc, iStream);
cudaEventSynchronize(toc);
cudaEventElapsedTime(&kt, tic, toc);
cudaEventDestroy(tic); cudaEventDestroy(toc);
(*ptimer) += kt;
} | .file "tmpxft_001aee51_00000000-6_er2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st
.type _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st, @function
_Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %rbp
call cudaEventCreate@PLT
movq %r12, %rdi
call cudaEventCreate@PLT
movq (%rbx), %rdi
movq %rbp, %rsi
call cudaEventRecord@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st, .-_Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st
.globl _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf
.type _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf, @function
_Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rsi
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq (%rbx), %rdi
call cudaEventRecord@PLT
movq (%rbx), %rdi
call cudaEventSynchronize@PLT
movq (%rbx), %rdx
movq (%r12), %rsi
leaq 4(%rsp), %rdi
call cudaEventElapsedTime@PLT
movq (%r12), %rdi
call cudaEventDestroy@PLT
movq (%rbx), %rdi
call cudaEventDestroy@PLT
movss 0(%rbp), %xmm0
addss 4(%rsp), %xmm0
movss %xmm0, 0(%rbp)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf, .-_Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf
.globl _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
.type _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii, @function
_Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7vecMat1PdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii, .-_Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
.globl _Z7vecMat1PdS_S_ii
.type _Z7vecMat1PdS_S_ii, @function
_Z7vecMat1PdS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7vecMat1PdS_S_ii, .-_Z7vecMat1PdS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n Usage: %s <HEIGHT> <WIDTH> \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "elapsed time:%g sec \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
je .L18
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L17:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 28(%rsp)
movl %r14d, %ebx
imull %eax, %ebx
movslq %ebx, %r13
movl $8, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, %r14
movslq %ebp, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, (%rsp)
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, 16(%rsp)
testl %ebx, %ebx
jle .L20
movq %r14, %rbx
leaq (%r14,%r13,8), %r15
.L21:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r15, %rbx
jne .L21
.L20:
testl %ebp, %ebp
jle .L26
movq (%rsp), %rsi
movq %rsi, %rbx
leal -1(%rbp), %eax
leaq 8(%rsi,%rax,8), %r15
.L23:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r15, %rbx
jne .L23
.L22:
salq $3, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
salq $3, %r12
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq 8(%rsp), %rbx
salq $3, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
subl $1, %ebp
shrl $9, %ebp
addl $1, %ebp
movl %ebp, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0x00000000, 36(%rsp)
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $0, %edx
call _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rcx
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $0, %edx
call _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf
movss 36(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
jmp .L17
.L26:
movl $0, %ebp
jmp .L22
.L31:
movl 8(%rsp), %r8d
movl 28(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
jmp .L24
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7vecMat1PdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vecMat1PdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include "cuda.h"
void StartKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream);
void StopKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream, float* ptimer);
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h );
int main(int argc , char *argv[])
{
if(argc != 3)
{
printf("\n Usage: %s <HEIGHT> <WIDTH> \n",argv[0]);
return 1;
}
int h=atoi(argv[1]);
int w=atoi(argv[2]);
int n;
const unsigned int THREADS_PER_BLOCK = 512;
double *hostMat = (double*) calloc(h*w, sizeof(double));
double *hostVec = (double*) calloc(w, sizeof(double));
double *hostResVec = (double*) calloc(w, sizeof(double));
for(n=0;n<h*w;++n){
hostMat[n]=rand() % 100;
}
for(n=0;n<w;++n)
{
hostVec[n] = rand() % 100;
}
// allocate memory
double *gpuMat, *gpuVec, *gpuResVec;
cudaMalloc( (void**)&gpuMat, w*h* sizeof(double) );
cudaMalloc( (void**)&gpuVec, w * sizeof(double) );
cudaMalloc( (void**)&gpuResVec, h * sizeof(double) );
// upload M and x
cudaMemcpy( gpuMat, (void*) hostMat, w*h * sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy( gpuVec, (void*) hostVec, w * sizeof(double),cudaMemcpyHostToDevice );
// compute the block and grid dimensions
dim3 threadBlock( THREADS_PER_BLOCK, 1 );
const unsigned int numBlocks = (n - 1)/THREADS_PER_BLOCK + 1;
dim3 blockGrid( numBlocks, 1, 1);
//xronometrhsh
cudaEvent_t tic, toc;
float elapsed_time = 0.f;
StartKernelTiming(tic, toc, 0);
vecMat1<<< blockGrid, threadBlock >>>( gpuResVec, gpuMat, gpuVec,w,h);
cudaThreadSynchronize() ;
// download result y
cudaMemcpy( hostResVec, gpuResVec, h * sizeof(double), cudaMemcpyDeviceToHost) ;
StopKernelTiming(tic,toc, 0, &elapsed_time); /*telos xronometrhshs*/
/*int k=0;
for(k=0; k<h; k++)
{
printf("gpu: %f\n", hostResVec[k]);
/*}
/* convert from miliseconds to seconds */
elapsed_time /= 1000.0;
/* output elapsed time */
printf("elapsed time:%g sec \n", elapsed_time);
cudaFree( gpuMat );
cudaFree( gpuVec );
cudaFree( gpuResVec );
free(hostMat);
free(hostVec);
free(hostResVec);
}
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h )
{
// row index the thread is operating on
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < _h) {
float res = 0.;
// dot product of one line
for (int j = 0; j < _w; ++j) {
res += _mat[i*_w + j] * _v[j];
}
// write result to global memory
_dst[i] = res;
}
}
void StartKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream)
{
cudaEventCreate(&tic);
cudaEventCreate(&toc);
cudaEventRecord(tic, iStream);
}
void StopKernelTiming(cudaEvent_t& tic, cudaEvent_t& toc, cudaStream_t iStream, float* ptimer)
{
float kt;
cudaEventRecord(toc, iStream);
cudaEventSynchronize(toc);
cudaEventElapsedTime(&kt, tic, toc);
cudaEventDestroy(tic); cudaEventDestroy(toc);
(*ptimer) += kt;
} | #include <stdio.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
void StartKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream);
void StopKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream, float* ptimer);
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h );
int main(int argc , char *argv[])
{
if(argc != 3)
{
printf("\n Usage: %s <HEIGHT> <WIDTH> \n",argv[0]);
return 1;
}
int h=atoi(argv[1]);
int w=atoi(argv[2]);
int n;
const unsigned int THREADS_PER_BLOCK = 512;
double *hostMat = (double*) calloc(h*w, sizeof(double));
double *hostVec = (double*) calloc(w, sizeof(double));
double *hostResVec = (double*) calloc(w, sizeof(double));
for(n=0;n<h*w;++n){
hostMat[n]=rand() % 100;
}
for(n=0;n<w;++n)
{
hostVec[n] = rand() % 100;
}
// allocate memory
double *gpuMat, *gpuVec, *gpuResVec;
hipMalloc( (void**)&gpuMat, w*h* sizeof(double) );
hipMalloc( (void**)&gpuVec, w * sizeof(double) );
hipMalloc( (void**)&gpuResVec, h * sizeof(double) );
// upload M and x
hipMemcpy( gpuMat, (void*) hostMat, w*h * sizeof(double),hipMemcpyHostToDevice);
hipMemcpy( gpuVec, (void*) hostVec, w * sizeof(double),hipMemcpyHostToDevice );
// compute the block and grid dimensions
dim3 threadBlock( THREADS_PER_BLOCK, 1 );
const unsigned int numBlocks = (n - 1)/THREADS_PER_BLOCK + 1;
dim3 blockGrid( numBlocks, 1, 1);
//xronometrhsh
hipEvent_t tic, toc;
float elapsed_time = 0.f;
StartKernelTiming(tic, toc, 0);
vecMat1<<< blockGrid, threadBlock >>>( gpuResVec, gpuMat, gpuVec,w,h);
hipDeviceSynchronize() ;
// download result y
hipMemcpy( hostResVec, gpuResVec, h * sizeof(double), hipMemcpyDeviceToHost) ;
StopKernelTiming(tic,toc, 0, &elapsed_time); /*telos xronometrhshs*/
/*int k=0;
for(k=0; k<h; k++)
{
printf("gpu: %f\n", hostResVec[k]);
/*}
/* convert from miliseconds to seconds */
elapsed_time /= 1000.0;
/* output elapsed time */
printf("elapsed time:%g sec \n", elapsed_time);
hipFree( gpuMat );
hipFree( gpuVec );
hipFree( gpuResVec );
free(hostMat);
free(hostVec);
free(hostResVec);
}
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h )
{
// row index the thread is operating on
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < _h) {
float res = 0.;
// dot product of one line
for (int j = 0; j < _w; ++j) {
res += _mat[i*_w + j] * _v[j];
}
// write result to global memory
_dst[i] = res;
}
}
void StartKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream)
{
hipEventCreate(&tic);
hipEventCreate(&toc);
hipEventRecord(tic, iStream);
}
void StopKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream, float* ptimer)
{
float kt;
hipEventRecord(toc, iStream);
hipEventSynchronize(toc);
hipEventElapsedTime(&kt, tic, toc);
hipEventDestroy(tic); hipEventDestroy(toc);
(*ptimer) += kt;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
void StartKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream);
void StopKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream, float* ptimer);
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h );
int main(int argc , char *argv[])
{
if(argc != 3)
{
printf("\n Usage: %s <HEIGHT> <WIDTH> \n",argv[0]);
return 1;
}
int h=atoi(argv[1]);
int w=atoi(argv[2]);
int n;
const unsigned int THREADS_PER_BLOCK = 512;
double *hostMat = (double*) calloc(h*w, sizeof(double));
double *hostVec = (double*) calloc(w, sizeof(double));
double *hostResVec = (double*) calloc(w, sizeof(double));
for(n=0;n<h*w;++n){
hostMat[n]=rand() % 100;
}
for(n=0;n<w;++n)
{
hostVec[n] = rand() % 100;
}
// allocate memory
double *gpuMat, *gpuVec, *gpuResVec;
hipMalloc( (void**)&gpuMat, w*h* sizeof(double) );
hipMalloc( (void**)&gpuVec, w * sizeof(double) );
hipMalloc( (void**)&gpuResVec, h * sizeof(double) );
// upload M and x
hipMemcpy( gpuMat, (void*) hostMat, w*h * sizeof(double),hipMemcpyHostToDevice);
hipMemcpy( gpuVec, (void*) hostVec, w * sizeof(double),hipMemcpyHostToDevice );
// compute the block and grid dimensions
dim3 threadBlock( THREADS_PER_BLOCK, 1 );
const unsigned int numBlocks = (n - 1)/THREADS_PER_BLOCK + 1;
dim3 blockGrid( numBlocks, 1, 1);
//xronometrhsh
hipEvent_t tic, toc;
float elapsed_time = 0.f;
StartKernelTiming(tic, toc, 0);
vecMat1<<< blockGrid, threadBlock >>>( gpuResVec, gpuMat, gpuVec,w,h);
hipDeviceSynchronize() ;
// download result y
hipMemcpy( hostResVec, gpuResVec, h * sizeof(double), hipMemcpyDeviceToHost) ;
StopKernelTiming(tic,toc, 0, &elapsed_time); /*telos xronometrhshs*/
/*int k=0;
for(k=0; k<h; k++)
{
printf("gpu: %f\n", hostResVec[k]);
/*}
/* convert from miliseconds to seconds */
elapsed_time /= 1000.0;
/* output elapsed time */
printf("elapsed time:%g sec \n", elapsed_time);
hipFree( gpuMat );
hipFree( gpuVec );
hipFree( gpuResVec );
free(hostMat);
free(hostVec);
free(hostResVec);
}
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h )
{
// row index the thread is operating on
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < _h) {
float res = 0.;
// dot product of one line
for (int j = 0; j < _w; ++j) {
res += _mat[i*_w + j] * _v[j];
}
// write result to global memory
_dst[i] = res;
}
}
void StartKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream)
{
hipEventCreate(&tic);
hipEventCreate(&toc);
hipEventRecord(tic, iStream);
}
void StopKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream, float* ptimer)
{
float kt;
hipEventRecord(toc, iStream);
hipEventSynchronize(toc);
hipEventElapsedTime(&kt, tic, toc);
hipEventDestroy(tic); hipEventDestroy(toc);
(*ptimer) += kt;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vecMat1PdS_S_ii
.globl _Z7vecMat1PdS_S_ii
.p2align 8
.type _Z7vecMat1PdS_S_ii,@function
_Z7vecMat1PdS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:
global_load_b64 v[4:5], v[2:3], off
v_cvt_f64_f32_e32 v[6:7], v0
s_load_b64 s[4:5], s[6:7], 0x0
v_add_co_u32 v2, vcc_lo, v2, 8
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
v_cvt_f32_f64_e32 v0, v[4:5]
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[3:4], v0
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vecMat1PdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vecMat1PdS_S_ii, .Lfunc_end0-_Z7vecMat1PdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vecMat1PdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vecMat1PdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
void StartKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream);
void StopKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream, float* ptimer);
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h );
int main(int argc , char *argv[])
{
if(argc != 3)
{
printf("\n Usage: %s <HEIGHT> <WIDTH> \n",argv[0]);
return 1;
}
int h=atoi(argv[1]);
int w=atoi(argv[2]);
int n;
const unsigned int THREADS_PER_BLOCK = 512;
double *hostMat = (double*) calloc(h*w, sizeof(double));
double *hostVec = (double*) calloc(w, sizeof(double));
double *hostResVec = (double*) calloc(w, sizeof(double));
for(n=0;n<h*w;++n){
hostMat[n]=rand() % 100;
}
for(n=0;n<w;++n)
{
hostVec[n] = rand() % 100;
}
// allocate memory
double *gpuMat, *gpuVec, *gpuResVec;
hipMalloc( (void**)&gpuMat, w*h* sizeof(double) );
hipMalloc( (void**)&gpuVec, w * sizeof(double) );
hipMalloc( (void**)&gpuResVec, h * sizeof(double) );
// upload M and x
hipMemcpy( gpuMat, (void*) hostMat, w*h * sizeof(double),hipMemcpyHostToDevice);
hipMemcpy( gpuVec, (void*) hostVec, w * sizeof(double),hipMemcpyHostToDevice );
// compute the block and grid dimensions
dim3 threadBlock( THREADS_PER_BLOCK, 1 );
const unsigned int numBlocks = (n - 1)/THREADS_PER_BLOCK + 1;
dim3 blockGrid( numBlocks, 1, 1);
//xronometrhsh
hipEvent_t tic, toc;
float elapsed_time = 0.f;
StartKernelTiming(tic, toc, 0);
vecMat1<<< blockGrid, threadBlock >>>( gpuResVec, gpuMat, gpuVec,w,h);
hipDeviceSynchronize() ;
// download result y
hipMemcpy( hostResVec, gpuResVec, h * sizeof(double), hipMemcpyDeviceToHost) ;
StopKernelTiming(tic,toc, 0, &elapsed_time); /*telos xronometrhshs*/
/*int k=0;
for(k=0; k<h; k++)
{
printf("gpu: %f\n", hostResVec[k]);
/*}
/* convert from miliseconds to seconds */
elapsed_time /= 1000.0;
/* output elapsed time */
printf("elapsed time:%g sec \n", elapsed_time);
hipFree( gpuMat );
hipFree( gpuVec );
hipFree( gpuResVec );
free(hostMat);
free(hostVec);
free(hostResVec);
}
__global__ void vecMat1(double *_dst, double* _mat, double* _v, int _w, int _h )
{
// row index the thread is operating on
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < _h) {
float res = 0.;
// dot product of one line
for (int j = 0; j < _w; ++j) {
res += _mat[i*_w + j] * _v[j];
}
// write result to global memory
_dst[i] = res;
}
}
void StartKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream)
{
hipEventCreate(&tic);
hipEventCreate(&toc);
hipEventRecord(tic, iStream);
}
void StopKernelTiming(hipEvent_t& tic, hipEvent_t& toc, hipStream_t iStream, float* ptimer)
{
float kt;
hipEventRecord(toc, iStream);
hipEventSynchronize(toc);
hipEventElapsedTime(&kt, tic, toc);
hipEventDestroy(tic); hipEventDestroy(toc);
(*ptimer) += kt;
} | .text
.file "er2.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB0_1
# %bb.2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl %r14d, %r12d
imull %r13d, %r12d
movslq %r12d, %rbp
movl $8, %esi
movq %rbp, %rdi
callq calloc
movq %rax, %rbx
movq %r14, 56(%rsp) # 8-byte Spill
movslq %r14d, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, 80(%rsp) # 8-byte Spill
testl %ebp, %ebp
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
movl %r12d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB0_4
.LBB0_5: # %.preheader
movq %r13, 64(%rsp) # 8-byte Spill
movq 56(%rsp), %rax # 8-byte Reload
movq %rax, %r15
shlq $32, %r15
movabsq $4294967296, %r12 # imm = 0x100000000
testl %eax, %eax
jle .LBB0_6
# %bb.7: # %.lr.ph52.preheader
movl %eax, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_8: # %.lr.ph52
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB0_8
# %bb.9: # %._crit_edge.loopexit
decl %r13d
shrl $9, %r13d
incl %r13d
movabsq $4294967296, %r12 # imm = 0x100000000
orq %r12, %r13
jmp .LBB0_10
.LBB0_1:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %ebp
jmp .LBB0_13
.LBB0_6:
leaq 8388608(%r12), %r13
.LBB0_10: # %._crit_edge
shlq $3, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
sarq $29, %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq 64(%rsp), %rsi # 4-byte Folded Reload
shlq $3, %rsi
leaq 24(%rsp), %rdi
movq %rsi, 72(%rsp) # 8-byte Spill
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
addq $512, %r12 # imm = 0x200
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_12
# %bb.11:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z7vecMat1PdS_S_ii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_12:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 72(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorpd %xmm0, %xmm0
addss 160(%rsp), %xmm0
divss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
.LBB0_13:
movl %ebp, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t # -- Begin function _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t
.p2align 4, 0x90
.type _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t,@function
_Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t: # @_Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
callq hipEventCreate
movq %r14, %rdi
callq hipEventCreate
movq (%r15), %rdi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipEventRecord # TAILCALL
.Lfunc_end1:
.size _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t, .Lfunc_end1-_Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t
.cfi_endproc
# -- End function
.globl _Z22__device_stub__vecMat1PdS_S_ii # -- Begin function _Z22__device_stub__vecMat1PdS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__vecMat1PdS_S_ii,@function
_Z22__device_stub__vecMat1PdS_S_ii: # @_Z22__device_stub__vecMat1PdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vecMat1PdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__vecMat1PdS_S_ii, .Lfunc_end2-_Z22__device_stub__vecMat1PdS_S_ii
.cfi_endproc
# -- End function
.globl _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf # -- Begin function _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf
.p2align 4, 0x90
.type _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf,@function
_Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf: # @_Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq (%rsi), %rdi
movq %rdx, %rsi
callq hipEventRecord
movq (%r14), %rdi
callq hipEventSynchronize
movq (%r15), %rsi
movq (%r14), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movq (%r15), %rdi
callq hipEventDestroy
movq (%r14), %rdi
callq hipEventDestroy
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rbx), %xmm0
movss %xmm0, (%rbx)
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf, .Lfunc_end3-_Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vecMat1PdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Usage: %s <HEIGHT> <WIDTH> \n"
.size .L.str, 31
.type _Z7vecMat1PdS_S_ii,@object # @_Z7vecMat1PdS_S_ii
.section .rodata,"a",@progbits
.globl _Z7vecMat1PdS_S_ii
.p2align 3, 0x0
_Z7vecMat1PdS_S_ii:
.quad _Z22__device_stub__vecMat1PdS_S_ii
.size _Z7vecMat1PdS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "elapsed time:%g sec \n"
.size .L.str.1, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7vecMat1PdS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vecMat1PdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vecMat1PdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7vecMat1PdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fc6000001ff00 */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xde0 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*00e0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0xc60 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R3, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002037a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0140*/ IMAD R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0205 */
/*01a0*/ @!P0 BRA 0xaa0 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x770 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E.64 R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000ea8000c1e1b00 */
/*0200*/ LDG.E.64 R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x000ea8000c1e1b00 */
/*0210*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ee8000c1e1b00 */
/*0220*/ LDG.E.64 R26, [R4.64+0x8] ; /* 0x00000804041a7981 */
/* 0x000ee8000c1e1b00 */
/*0230*/ LDG.E.64 R10, [R6.64+0x10] ; /* 0x00001004060a7981 */
/* 0x000f28000c1e1b00 */
/*0240*/ LDG.E.64 R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000f28000c1e1b00 */
/*0250*/ LDG.E.64 R8, [R6.64+0x18] ; /* 0x0000180406087981 */
/* 0x001f68000c1e1b00 */
/*0260*/ LDG.E.64 R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000f62000c1e1b00 */
/*0270*/ DFMA R24, R14, R24, R20 ; /* 0x000000180e18722b */
/* 0x0060460000000014 */
/*0280*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x001ea8000c1e1b00 */
/*0290*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ea2000c1e1b00 */
/*02a0*/ F2F.F32.F64 R28, R24 ; /* 0x00000018001c7310 */
/* 0x0020660000301000 */
/*02b0*/ LDG.E.64 R24, [R6.64+0x28] ; /* 0x0000280406187981 */
/* 0x001eaa000c1e1b00 */
/*02c0*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x002ee40000201800 */
/*02d0*/ DFMA R26, R12, R26, R16 ; /* 0x0000001a0c1a722b */
/* 0x0080440000000010 */
/*02e0*/ LDG.E.64 R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x001ef0000c1e1b00 */
/*02f0*/ F2F.F32.F64 R26, R26 ; /* 0x0000001a001a7310 */
/* 0x002e300000301000 */
/*0300*/ F2F.F64.F32 R16, R26 ; /* 0x0000001a00107310 */
/* 0x0011240000201800 */
/*0310*/ LDG.E.64 R26, [R6.64+0x30] ; /* 0x00003004061a7981 */
/* 0x001ee2000c1e1b00 */
/*0320*/ DFMA R22, R10, R22, R16 ; /* 0x000000160a16722b */
/* 0x0100460000000010 */
/*0330*/ LDG.E.64 R10, [R4.64+0x30] ; /* 0x00003004040a7981 */
/* 0x001f2e000c1e1b00 */
/*0340*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x002e300000301000 */
/*0350*/ F2F.F64.F32 R16, R22 ; /* 0x0000001600107310 */
/* 0x0011640000201800 */
/*0360*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001f22000c1e1b00 */
/*0370*/ DFMA R18, R8, R18, R16 ; /* 0x000000120812722b */
/* 0x0200460000000010 */
/*0380*/ LDG.E.64 R8, [R4.64+0x38] ; /* 0x0000380404087981 */
/* 0x001f66000c1e1b00 */
/*0390*/ F2F.F32.F64 R28, R18 ; /* 0x00000012001c7310 */
/* 0x0020680000301000 */
/*03a0*/ LDG.E.64 R18, [R6.64+0x40] ; /* 0x0000400406127981 */
/* 0x001f68000c1e1b00 */
/*03b0*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x002ea40000201800 */
/*03c0*/ DFMA R20, R20, R14, R16 ; /* 0x0000000e1414722b */
/* 0x0040440000000010 */
/*03d0*/ LDG.E.64 R16, [R4.64+0x40] ; /* 0x0000400404107981 */
/* 0x001ea8000c1e1b00 */
/*03e0*/ F2F.F32.F64 R14, R20 ; /* 0x00000014000e7310 */
/* 0x002e300000301000 */
/*03f0*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001ee40000201800 */
/*0400*/ DFMA R24, R24, R12, R14 ; /* 0x0000000c1818722b */
/* 0x008044000000000e */
/*0410*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001ee8000c1e1b00 */
/*0420*/ LDG.E.64 R12, [R4.64+0x48] ; /* 0x00004804040c7981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x002e300000301000 */
/*0440*/ F2F.F64.F32 R20, R24 ; /* 0x0000001800147310 */
/* 0x0011240000201800 */
/*0450*/ LDG.E.64 R24, [R6.64+0x50] ; /* 0x0000500406187981 */
/* 0x001ee2000c1e1b00 */
/*0460*/ DFMA R26, R26, R10, R20 ; /* 0x0000000a1a1a722b */
/* 0x0100460000000014 */
/*0470*/ LDG.E.64 R10, [R4.64+0x50] ; /* 0x00005004040a7981 */
/* 0x001f26000c1e1b00 */
/*0480*/ F2F.F32.F64 R28, R26 ; /* 0x0000001a001c7310 */
/* 0x0020680000301000 */
/*0490*/ LDG.E.64 R26, [R6.64+0x58] ; /* 0x00005804061a7981 */
/* 0x001f28000c1e1b00 */
/*04a0*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x002f640000201800 */
/*04b0*/ DFMA R22, R22, R8, R20 ; /* 0x000000081616722b */
/* 0x0200440000000014 */
/*04c0*/ LDG.E.64 R8, [R4.64+0x58] ; /* 0x0000580404087981 */
/* 0x001f68000c1e1b00 */
/*04d0*/ F2F.F32.F64 R20, R22 ; /* 0x0000001600147310 */
/* 0x0020680000301000 */
/*04e0*/ LDG.E.64 R22, [R4.64+0x60] ; /* 0x0000600404167981 */
/* 0x001f68000c1e1b00 */
/*04f0*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x002ea40000201800 */
/*0500*/ DFMA R18, R18, R16, R20 ; /* 0x000000101212722b */
/* 0x0040440000000014 */
/*0510*/ LDG.E.64 R20, [R6.64+0x60] ; /* 0x0000600406147981 */
/* 0x001ea8000c1e1b00 */
/*0520*/ F2F.F32.F64 R16, R18 ; /* 0x0000001200107310 */
/* 0x0020680000301000 */
/*0530*/ LDG.E.64 R18, [R4.64+0x68] ; /* 0x0000680404127981 */
/* 0x001ea8000c1e1b00 */
/*0540*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x002ee40000201800 */
/*0550*/ DFMA R14, R14, R12, R16 ; /* 0x0000000c0e0e722b */
/* 0x0080440000000010 */
/*0560*/ LDG.E.64 R16, [R6.64+0x68] ; /* 0x0000680406107981 */
/* 0x001ee8000c1e1b00 */
/*0570*/ F2F.F32.F64 R28, R14 ; /* 0x0000000e001c7310 */
/* 0x0020680000301000 */
/*0580*/ LDG.E.64 R14, [R4.64+0x70] ; /* 0x00007004040e7981 */
/* 0x001ee8000c1e1b00 */
/*0590*/ F2F.F64.F32 R12, R28 ; /* 0x0000001c000c7310 */
/* 0x002f240000201800 */
/*05a0*/ DFMA R24, R24, R10, R12 ; /* 0x0000000a1818722b */
/* 0x010044000000000c */
/*05b0*/ LDG.E.64 R12, [R6.64+0x70] ; /* 0x00007004060c7981 */
/* 0x001f28000c1e1b00 */
/*05c0*/ F2F.F32.F64 R10, R24 ; /* 0x00000018000a7310 */
/* 0x002e300000301000 */
/*05d0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001f640000201800 */
/*05e0*/ DFMA R26, R26, R8, R10 ; /* 0x000000081a1a722b */
/* 0x020044000000000a */
/*05f0*/ LDG.E.64 R8, [R6.64+0x78] ; /* 0x0000780406087981 */
/* 0x001f68000c1e1b00 */
/*0600*/ LDG.E.64 R10, [R4.64+0x78] ; /* 0x00007804040a7981 */
/* 0x000f68000c1e1b00 */
/*0610*/ F2F.F32.F64 R26, R26 ; /* 0x0000001a001a7310 */
/* 0x002e300000301000 */
/*0620*/ F2F.F64.F32 R24, R26 ; /* 0x0000001a00187310 */
/* 0x001ea20000201800 */
/*0630*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fc80007ffe0ff */
/*0640*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe20003f24270 */
/*0650*/ DFMA R20, R20, R22, R24 ; /* 0x000000161414722b */
/* 0x004e0c0000000018 */
/*0660*/ F2F.F32.F64 R22, R20 ; /* 0x0000001400167310 */
/* 0x001e300000301000 */
/*0670*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x001ee40000201800 */
/*0680*/ DFMA R16, R16, R18, R22 ; /* 0x000000121010722b */
/* 0x008e140000000016 */
/*0690*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*06a0*/ F2F.F64.F32 R18, R16 ; /* 0x0000001000127310 */
/* 0x001f240000201800 */
/*06b0*/ DFMA R12, R12, R14, R18 ; /* 0x0000000e0c0c722b */
/* 0x010e140000000012 */
/*06c0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*06d0*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001f640000201800 */
/*06e0*/ DFMA R8, R8, R10, R14 ; /* 0x0000000a0808722b */
/* 0x020e14000000000e */
/*06f0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e220000301000 */
/*0700*/ IADD3 R6, P3, R6, 0x80, RZ ; /* 0x0000008006067810 */
/* 0x000fe40007f7e0ff */
/*0710*/ IADD3 R4, P2, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x000fca0007f5e0ff */
/*0720*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x0010620000201800 */
/*0730*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0607 */
/*0740*/ IADD3 R29, R29, 0x10, RZ ; /* 0x000000101d1d7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0760*/ @P1 BRA 0x1f0 ; /* 0xfffffa8000001947 */
/* 0x000fea000383ffff */
/*0770*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*0780*/ @!P1 BRA 0xa80 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E.64 R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea8000c1e1b00 */
/*07a0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ee8000c1e1b00 */
/*07c0*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee8000c1e1b00 */
/*07d0*/ LDG.E.64 R26, [R6.64+0x10] ; /* 0x00001004061a7981 */
/* 0x000f28000c1e1b00 */
/*07e0*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000f28000c1e1b00 */
/*07f0*/ LDG.E.64 R24, [R6.64+0x18] ; /* 0x0000180406187981 */
/* 0x000ee8000c1e1b00 */
/*0800*/ LDG.E.64 R8, [R4.64+0x18] ; /* 0x0000180404087981 */
/* 0x001ee8000c1e1b00 */
/*0810*/ LDG.E.64 R22, [R4.64+0x20] ; /* 0x0000200404167981 */
/* 0x0000e2000c1e1b00 */
/*0820*/ DFMA R18, R18, R16, R20 ; /* 0x000000101212722b */
/* 0x0062860000000014 */
/*0830*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x002366000c1e1b00 */
/*0840*/ F2F.F32.F64 R28, R18 ; /* 0x00000012001c7310 */
/* 0x0044280000301000 */
/*0850*/ LDG.E.64 R18, [R4.64+0x28] ; /* 0x0000280404127981 */
/* 0x004568000c1e1b00 */
/*0860*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x001ee40000201800 */
/*0870*/ DFMA R14, R14, R12, R16 ; /* 0x0000000c0e0e722b */
/* 0x0080c40000000010 */
/*0880*/ LDG.E.64 R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x001368000c1e1b00 */
/*0890*/ F2F.F32.F64 R12, R14 ; /* 0x0000000e000c7310 */
/* 0x0080e80000301000 */
/*08a0*/ LDG.E.64 R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x001568000c1e1b00 */
/*08b0*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x008f240000201800 */
/*08c0*/ DFMA R26, R26, R10, R12 ; /* 0x0000000a1a1a722b */
/* 0x0100c4000000000c */
/*08d0*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x001328000c1e1b00 */
/*08e0*/ F2F.F32.F64 R10, R26 ; /* 0x0000001a000a7310 */
/* 0x008e300000301000 */
/*08f0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e240000201800 */
/*0900*/ DFMA R24, R24, R8, R10 ; /* 0x000000081818722b */
/* 0x0010c4000000000a */
/*0910*/ LDG.E.64 R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x001328000c1e1b00 */
/*0920*/ LDG.E.64 R10, [R4.64+0x38] ; /* 0x00003804040a7981 */
/* 0x000528000c1e1b00 */
/*0930*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x008e300000301000 */
/*0940*/ F2F.F64.F32 R26, R24 ; /* 0x00000018001a7310 */
/* 0x001f620000201800 */
/*0950*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x004fc40007f3e0ff */
/*0960*/ IADD3 R6, P2, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x002fe20007f5e0ff */
/*0970*/ DFMA R22, R20, R22, R26 ; /* 0x000000161416722b */
/* 0x020e14000000001a */
/*0980*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x001e300000301000 */
/*0990*/ F2F.F64.F32 R20, R22 ; /* 0x0000001600147310 */
/* 0x001e240000201800 */
/*09a0*/ DFMA R16, R16, R18, R20 ; /* 0x000000121010722b */
/* 0x001e140000000014 */
/*09b0*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x001e300000301000 */
/*09c0*/ F2F.F64.F32 R18, R16 ; /* 0x0000001000127310 */
/* 0x001f240000201800 */
/*09d0*/ DFMA R12, R12, R14, R18 ; /* 0x0000000e0c0c722b */
/* 0x010e140000000012 */
/*09e0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*09f0*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0a00*/ DFMA R8, R8, R10, R14 ; /* 0x0000000a0808722b */
/* 0x001e14000000000e */
/*0a10*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e220000301000 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0a40*/ IADD3 R29, R29, 0x8, RZ ; /* 0x000000081d1d7810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fc800010e0607 */
/*0a60*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x0010620000201800 */
/*0a70*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fce0007ffe0ff */
/*0a80*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0a90*/ @!P0 BRA 0xc60 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E.64 R24, [R6.64] ; /* 0x0000000406187981 */
/* 0x0004e8000c1e1b00 */
/*0ab0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0010e8000c1e1b00 */
/*0ac0*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000528000c1e1b00 */
/*0ad0*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000128000c1e1b00 */
/*0ae0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000568000c1e1b00 */
/*0af0*/ LDG.E.64 R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000168000c1e1b00 */
/*0b00*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x000528000c1e1b00 */
/*0b10*/ LDG.E.64 R22, [R4.64+0x18] ; /* 0x0000180404167981 */
/* 0x000122000c1e1b00 */
/*0b20*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fc40007ffe0ff */
/*0b30*/ IADD3 R29, R29, 0x4, RZ ; /* 0x000000041d1d7810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0b50*/ IADD3 R6, P2, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x004fe40007f5e0ff */
/*0b60*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fc60007f3e0ff */
/*0b70*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0b80*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0b90*/ DFMA R8, R24, R8, R20 ; /* 0x000000081808722b */
/* 0x00ae140000000014 */
/*0ba0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x001e300000301000 */
/*0bb0*/ F2F.F64.F32 R20, R8 ; /* 0x0000000800147310 */
/* 0x001f240000201800 */
/*0bc0*/ DFMA R10, R10, R12, R20 ; /* 0x0000000c0a0a722b */
/* 0x010e140000000014 */
/*0bd0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e300000301000 */
/*0be0*/ F2F.F64.F32 R12, R10 ; /* 0x0000000a000c7310 */
/* 0x001f640000201800 */
/*0bf0*/ DFMA R12, R14, R16, R12 ; /* 0x000000100e0c722b */
/* 0x020e14000000000c */
/*0c00*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x001e300000301000 */
/*0c10*/ F2F.F64.F32 R14, R12 ; /* 0x0000000c000e7310 */
/* 0x001e240000201800 */
/*0c20*/ DFMA R14, R18, R22, R14 ; /* 0x00000016120e722b */
/* 0x001e14000000000e */
/*0c30*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e300000301000 */
/*0c40*/ F2F.F64.F32 R20, R14 ; /* 0x0000000e00147310 */
/* 0x0010640000201800 */
/*0c50*/ @P0 BRA 0xaa0 ; /* 0xfffffe4000000947 */
/* 0x003fea000383ffff */
/*0c60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0c70*/ @!P0 BRA 0xde0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0c80*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*0c90*/ IMAD R6, R0, c[0x0][0x178], R29 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e021d */
/*0ca0*/ IMAD.WIDE R4, R29, R7, c[0x0][0x170] ; /* 0x00005c001d047625 */
/* 0x000fc800078e0207 */
/*0cb0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0207 */
/*0cc0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0004 */
/*0cd0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0ce0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0cf0*/ IMAD.MOV.U32 R10, RZ, RZ, R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0007 */
/*0d00*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0003 */
/*0d10*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0010a2000c1e1b00 */
/*0d20*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e000a */
/*0d30*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0d40*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0d60*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x001fe40007f3e0ff */
/*0d70*/ IADD3 R3, P2, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fc60007f5e0ff */
/*0d80*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*0d90*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200010e060a */
/*0da0*/ DFMA R4, R4, R6, R20 ; /* 0x000000060404722b */
/* 0x006e140000000014 */
/*0db0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x001e300000301000 */
/*0dc0*/ F2F.F64.F32 R20, R4 ; /* 0x0000000400147310 */
/* 0x0010620000201800 */
/*0dd0*/ @P0 BRA 0xd00 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0de0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0df0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0e00*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101b04 */
/*0e10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vecMat1PdS_S_ii
.globl _Z7vecMat1PdS_S_ii
.p2align 8
.type _Z7vecMat1PdS_S_ii,@function
_Z7vecMat1PdS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:
global_load_b64 v[4:5], v[2:3], off
v_cvt_f64_f32_e32 v[6:7], v0
s_load_b64 s[4:5], s[6:7], 0x0
v_add_co_u32 v2, vcc_lo, v2, 8
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
v_cvt_f32_f64_e32 v0, v[4:5]
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[3:4], v0
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vecMat1PdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vecMat1PdS_S_ii, .Lfunc_end0-_Z7vecMat1PdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vecMat1PdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vecMat1PdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aee51_00000000-6_er2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st
.type _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st, @function
_Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %rbp
call cudaEventCreate@PLT
movq %r12, %rdi
call cudaEventCreate@PLT
movq (%rbx), %rdi
movq %rbp, %rsi
call cudaEventRecord@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st, .-_Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st
.globl _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf
.type _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf, @function
_Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rsi
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq (%rbx), %rdi
call cudaEventRecord@PLT
movq (%rbx), %rdi
call cudaEventSynchronize@PLT
movq (%rbx), %rdx
movq (%r12), %rsi
leaq 4(%rsp), %rdi
call cudaEventElapsedTime@PLT
movq (%r12), %rdi
call cudaEventDestroy@PLT
movq (%rbx), %rdi
call cudaEventDestroy@PLT
movss 0(%rbp), %xmm0
addss 4(%rsp), %xmm0
movss %xmm0, 0(%rbp)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf, .-_Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf
.globl _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
.type _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii, @function
_Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7vecMat1PdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii, .-_Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
.globl _Z7vecMat1PdS_S_ii
.type _Z7vecMat1PdS_S_ii, @function
_Z7vecMat1PdS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7vecMat1PdS_S_ii, .-_Z7vecMat1PdS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n Usage: %s <HEIGHT> <WIDTH> \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "elapsed time:%g sec \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
je .L18
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L17:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 28(%rsp)
movl %r14d, %ebx
imull %eax, %ebx
movslq %ebx, %r13
movl $8, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, %r14
movslq %ebp, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, (%rsp)
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, 16(%rsp)
testl %ebx, %ebx
jle .L20
movq %r14, %rbx
leaq (%r14,%r13,8), %r15
.L21:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r15, %rbx
jne .L21
.L20:
testl %ebp, %ebp
jle .L26
movq (%rsp), %rsi
movq %rsi, %rbx
leal -1(%rbp), %eax
leaq 8(%rsi,%rax,8), %r15
.L23:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r15, %rbx
jne .L23
.L22:
salq $3, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
salq $3, %r12
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq 8(%rsp), %rbx
salq $3, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
subl $1, %ebp
shrl $9, %ebp
addl $1, %ebp
movl %ebp, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0x00000000, 36(%rsp)
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $0, %edx
call _Z17StartKernelTimingRP10CUevent_stS1_P11CUstream_st
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rcx
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $0, %edx
call _Z16StopKernelTimingRP10CUevent_stS1_P11CUstream_stPf
movss 36(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
jmp .L17
.L26:
movl $0, %ebp
jmp .L22
.L31:
movl 8(%rsp), %r8d
movl 28(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z32__device_stub__Z7vecMat1PdS_S_iiPdS_S_ii
jmp .L24
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7vecMat1PdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vecMat1PdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "er2.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB0_1
# %bb.2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl %r14d, %r12d
imull %r13d, %r12d
movslq %r12d, %rbp
movl $8, %esi
movq %rbp, %rdi
callq calloc
movq %rax, %rbx
movq %r14, 56(%rsp) # 8-byte Spill
movslq %r14d, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, 80(%rsp) # 8-byte Spill
testl %ebp, %ebp
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
movl %r12d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB0_4
.LBB0_5: # %.preheader
movq %r13, 64(%rsp) # 8-byte Spill
movq 56(%rsp), %rax # 8-byte Reload
movq %rax, %r15
shlq $32, %r15
movabsq $4294967296, %r12 # imm = 0x100000000
testl %eax, %eax
jle .LBB0_6
# %bb.7: # %.lr.ph52.preheader
movl %eax, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_8: # %.lr.ph52
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB0_8
# %bb.9: # %._crit_edge.loopexit
decl %r13d
shrl $9, %r13d
incl %r13d
movabsq $4294967296, %r12 # imm = 0x100000000
orq %r12, %r13
jmp .LBB0_10
.LBB0_1:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %ebp
jmp .LBB0_13
.LBB0_6:
leaq 8388608(%r12), %r13
.LBB0_10: # %._crit_edge
shlq $3, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
sarq $29, %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq 64(%rsp), %rsi # 4-byte Folded Reload
shlq $3, %rsi
leaq 24(%rsp), %rdi
movq %rsi, 72(%rsp) # 8-byte Spill
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
addq $512, %r12 # imm = 0x200
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_12
# %bb.11:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z7vecMat1PdS_S_ii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_12:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 72(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorpd %xmm0, %xmm0
addss 160(%rsp), %xmm0
divss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
.LBB0_13:
movl %ebp, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t # -- Begin function _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t
.p2align 4, 0x90
.type _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t,@function
_Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t: # @_Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
callq hipEventCreate
movq %r14, %rdi
callq hipEventCreate
movq (%r15), %rdi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipEventRecord # TAILCALL
.Lfunc_end1:
.size _Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t, .Lfunc_end1-_Z17StartKernelTimingRP11ihipEvent_tS1_P12ihipStream_t
.cfi_endproc
# -- End function
.globl _Z22__device_stub__vecMat1PdS_S_ii # -- Begin function _Z22__device_stub__vecMat1PdS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__vecMat1PdS_S_ii,@function
_Z22__device_stub__vecMat1PdS_S_ii: # @_Z22__device_stub__vecMat1PdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vecMat1PdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__vecMat1PdS_S_ii, .Lfunc_end2-_Z22__device_stub__vecMat1PdS_S_ii
.cfi_endproc
# -- End function
.globl _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf # -- Begin function _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf
.p2align 4, 0x90
.type _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf,@function
_Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf: # @_Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq (%rsi), %rdi
movq %rdx, %rsi
callq hipEventRecord
movq (%r14), %rdi
callq hipEventSynchronize
movq (%r15), %rsi
movq (%r14), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movq (%r15), %rdi
callq hipEventDestroy
movq (%r14), %rdi
callq hipEventDestroy
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rbx), %xmm0
movss %xmm0, (%rbx)
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf, .Lfunc_end3-_Z16StopKernelTimingRP11ihipEvent_tS1_P12ihipStream_tPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vecMat1PdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Usage: %s <HEIGHT> <WIDTH> \n"
.size .L.str, 31
.type _Z7vecMat1PdS_S_ii,@object # @_Z7vecMat1PdS_S_ii
.section .rodata,"a",@progbits
.globl _Z7vecMat1PdS_S_ii
.p2align 3, 0x0
_Z7vecMat1PdS_S_ii:
.quad _Z22__device_stub__vecMat1PdS_S_ii
.size _Z7vecMat1PdS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "elapsed time:%g sec \n"
.size .L.str.1, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7vecMat1PdS_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vecMat1PdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vecMat1PdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Elapsed Real Time for input-4.txt: 1.381 seconds
#include <stdio.h>
#include <stdbool.h>
#include <cuda_runtime.h>
// Size of the square we're looking for.
#define SQUARE_WIDTH 6
#define SQUARE_HEIGHT 6
// Maximum width of a row. Makes it easier to allocate the whole
// grid contiguously.
#define MAX_WIDTH 16384
// Type used for a row of the grid. Makes it easier to declare the
// grid as a pointer.
typedef char Row[ MAX_WIDTH ];
// Size of the grid of characters.
int rows, cols;
// Grid of letters.
Row *grid;
// Kernel, run by each thread to count complete squares in parallel.
__global__ void countSquares( int rows, int cols, bool report, int *gpuResults, Row *gridCpy ) {
// Unique index for this worker.
int r0 = blockDim.x * blockIdx.x + threadIdx.x;
int c = 0;
// Make sure I actually have something to work on.
if ( r0 + SQUARE_HEIGHT - 1 < rows ) {
for(int col = 0; col < cols; col++) {
if(col + 6 <= cols) {
bool check = false;//check if that grid actually makes a square or not.
char letters[26] = {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p','q','r','s','t','u','v','w','x','y','z'}; // array of alphabets.
for( int i = r0; i < r0 + 6; i++) {
for( int j = col; j < col + 6; j++) {
for( int k = 0; k < 26; k++) {
if(gridCpy[i][j] == letters[k]) { //if cell in grid has any aplhabet, change that alphabet bucket to 0.
letters[k] = '0';//if the letter is not yet, remove it.
}
}
}
}
for(int k = 0; k < 26; k++) {
if(letters[k] != '0') {
check = false;//if any letter in the array is not 0, the grid is not a square.
break;
} else {
check = true;//else it is true and continue to make sure all if true.
}
}
if(check == true) {
c += 1;//if it is a perfect square grid, increment the count for that index
if(report) {
printf("%d %d\n", r0, col);//if report is true, print the index
}
}
}
}
}
gpuResults[r0] = c;//put number of squares in the array
}
// Read the grid of characters.
void readGrid() {
// Read grid dimensions.
scanf( "%d%d", &rows, &cols );
if ( cols > MAX_WIDTH ) {
fprintf( stderr, "Input grid is too wide.\n" );
exit( EXIT_FAILURE );
}
// Make space to store the grid as a big, contiguous array.
grid = (Row *) malloc( rows * sizeof( Row ) );
// Read each row of the grid as a string, then copy everything
// but the null terminator into the grid array.
int rowCount = 0;
char buffer[ MAX_WIDTH + 1 ];
while ( rowCount < rows ) {
scanf( "%s", buffer );
memcpy( grid[ rowCount++ ], buffer, cols );
}
}
// General function to report a failure and exit.
static void fail( char const *message ) {
fprintf( stderr, "%s\n", message );
exit( 1 );
}
// Print out a usage message, then exit.
static void usage() {
printf( "usage: square [report]\n" );
exit( 1 );
}
//main
int main( int argc, char *argv[] ) {
// If there's an argument, it better be "report"
bool report = false;
if ( argc == 2 ) {
if ( strcmp( argv[ 1 ], "report" ) != 0 )
usage();
report = true;
}
readGrid();
// Need to add code to allocate memory on the device and copy the grid
// over.
Row *gridCpy = NULL;
cudaMalloc( (void **)&gridCpy, rows * sizeof( Row ) );
cudaMemcpy( gridCpy, grid, rows * sizeof( Row ), cudaMemcpyHostToDevice );
//allocate memory for results array
int *gpuResults = NULL;
cudaMalloc((void **)&gpuResults, rows * sizeof(int));
// Block and grid dimensions.
int threadsPerBlock = 250;
// Round up.
int blocksPerGrid = ( rows + threadsPerBlock - 1 ) / threadsPerBlock;
// Run our kernel on these block/grid dimensions
countSquares<<<blocksPerGrid, threadsPerBlock>>>( rows, cols, report, gpuResults, gridCpy );
if ( cudaGetLastError() != cudaSuccess )
fail( "Failure in CUDA kernel execution." );
int *results = (int *) malloc( rows * sizeof( int ) );
// Need to add code to copy the results list back to the host and
// add them up.
cudaMemcpy( results, gpuResults, rows * sizeof(int), cudaMemcpyDeviceToHost);
int total = 0;
for(int i = 0; i < rows; i++) {
total += results[i];//add all integers in results array to get total
}
printf( "Squares: %d\n", total );
// Free memory on the device and the host.
free(grid);
free(results);
cudaFree(gridCpy);
cudaFree(gpuResults);
cudaDeviceReset();
return 0;
} | .file "tmpxft_0002053d_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d%d"
.LC1:
.string "Input grid is too wide.\n"
.LC2:
.string "%s"
.text
.globl _Z8readGridv
.type _Z8readGridv, @function
_Z8readGridv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16416
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $16, %rsp
.cfi_def_cfa_offset 16432
movq %fs:40, %rax
movq %rax, 16392(%rsp)
xorl %eax, %eax
leaq cols(%rip), %rdx
leaq rows(%rip), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
cmpl $16384, cols(%rip)
jg .L10
movl rows(%rip), %ebx
movslq %ebx, %rdi
salq $14, %rdi
call malloc@PLT
movq %rax, grid(%rip)
testl %ebx, %ebx
jle .L3
movl $0, %ebx
leaq .LC2(%rip), %r12
.L6:
movq %rsp, %rbp
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbx, %rdi
salq $14, %rdi
addq grid(%rip), %rdi
movslq cols(%rip), %rdx
movq %rbp, %rsi
call memcpy@PLT
addq $1, %rbx
cmpl %ebx, rows(%rip)
jg .L6
.L3:
movq 16392(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $16400, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8readGridv, .-_Z8readGridv
.globl _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
.type _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c, @function
_Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movb %dl, 20(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12countSquaresiibPiPA16384_c(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c, .-_Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
.globl _Z12countSquaresiibPiPA16384_c
.type _Z12countSquaresiibPiPA16384_c, @function
_Z12countSquaresiibPiPA16384_c:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %dl, %edx
call _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12countSquaresiibPiPA16384_c, .-_Z12countSquaresiibPiPA16384_c
.section .rodata.str1.1
.LC3:
.string "report"
.LC4:
.string "usage: square [report]\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Failure in CUDA kernel execution."
.section .rodata.str1.1
.LC6:
.string "%s\n"
.LC7:
.string "Squares: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L27
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call strcmp@PLT
movl $1, %ebx
testl %eax, %eax
jne .L32
.L21:
call _Z8readGridv
movq $0, (%rsp)
movslq rows(%rip), %rsi
salq $14, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movslq rows(%rip), %rdx
salq $14, %rdx
movl $1, %ecx
movq grid(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 8(%rsp)
movslq rows(%rip), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl rows(%rip), %eax
leal 249(%rax), %edx
movslq %edx, %rax
imulq $274877907, %rax, %rax
sarq $36, %rax
sarl $31, %edx
subl %edx, %eax
movl $250, 28(%rsp)
movl $1, 32(%rsp)
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L22:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L34
movslq rows(%rip), %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl rows(%rip), %edx
testl %edx, %edx
jle .L29
movq %rbx, %rax
movslq %edx, %rdx
leaq (%rbx,%rdx,4), %rcx
movl $0, %edx
.L25:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L25
.L24:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq grid(%rip), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl $0, %ebx
jmp .L21
.L33:
movzbl %bl, %edx
movq (%rsp), %r8
movq 8(%rsp), %rcx
movl cols(%rip), %esi
movl rows(%rip), %edi
call _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
jmp .L22
.L34:
leaq .LC5(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl $0, %edx
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z12countSquaresiibPiPA16384_c"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12countSquaresiibPiPA16384_c(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl grid
.bss
.align 8
.type grid, @object
.size grid, 8
grid:
.zero 8
.globl cols
.align 4
.type cols, @object
.size cols, 4
cols:
.zero 4
.globl rows
.align 4
.type rows, @object
.size rows, 4
rows:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Elapsed Real Time for input-4.txt: 1.381 seconds
#include <stdio.h>
#include <stdbool.h>
#include <cuda_runtime.h>
// Size of the square we're looking for.
#define SQUARE_WIDTH 6
#define SQUARE_HEIGHT 6
// Maximum width of a row. Makes it easier to allocate the whole
// grid contiguously.
#define MAX_WIDTH 16384
// Type used for a row of the grid. Makes it easier to declare the
// grid as a pointer.
typedef char Row[ MAX_WIDTH ];
// Size of the grid of characters.
int rows, cols;
// Grid of letters.
Row *grid;
// Kernel, run by each thread to count complete squares in parallel.
__global__ void countSquares( int rows, int cols, bool report, int *gpuResults, Row *gridCpy ) {
// Unique index for this worker.
int r0 = blockDim.x * blockIdx.x + threadIdx.x;
int c = 0;
// Make sure I actually have something to work on.
if ( r0 + SQUARE_HEIGHT - 1 < rows ) {
for(int col = 0; col < cols; col++) {
if(col + 6 <= cols) {
bool check = false;//check if that grid actually makes a square or not.
char letters[26] = {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p','q','r','s','t','u','v','w','x','y','z'}; // array of alphabets.
for( int i = r0; i < r0 + 6; i++) {
for( int j = col; j < col + 6; j++) {
for( int k = 0; k < 26; k++) {
if(gridCpy[i][j] == letters[k]) { //if cell in grid has any aplhabet, change that alphabet bucket to 0.
letters[k] = '0';//if the letter is not yet, remove it.
}
}
}
}
for(int k = 0; k < 26; k++) {
if(letters[k] != '0') {
check = false;//if any letter in the array is not 0, the grid is not a square.
break;
} else {
check = true;//else it is true and continue to make sure all if true.
}
}
if(check == true) {
c += 1;//if it is a perfect square grid, increment the count for that index
if(report) {
printf("%d %d\n", r0, col);//if report is true, print the index
}
}
}
}
}
gpuResults[r0] = c;//put number of squares in the array
}
// Read the grid of characters.
void readGrid() {
// Read grid dimensions.
scanf( "%d%d", &rows, &cols );
if ( cols > MAX_WIDTH ) {
fprintf( stderr, "Input grid is too wide.\n" );
exit( EXIT_FAILURE );
}
// Make space to store the grid as a big, contiguous array.
grid = (Row *) malloc( rows * sizeof( Row ) );
// Read each row of the grid as a string, then copy everything
// but the null terminator into the grid array.
int rowCount = 0;
char buffer[ MAX_WIDTH + 1 ];
while ( rowCount < rows ) {
scanf( "%s", buffer );
memcpy( grid[ rowCount++ ], buffer, cols );
}
}
// General function to report a failure and exit.
static void fail( char const *message ) {
fprintf( stderr, "%s\n", message );
exit( 1 );
}
// Print out a usage message, then exit.
static void usage() {
printf( "usage: square [report]\n" );
exit( 1 );
}
//main
int main( int argc, char *argv[] ) {
// If there's an argument, it better be "report"
bool report = false;
if ( argc == 2 ) {
if ( strcmp( argv[ 1 ], "report" ) != 0 )
usage();
report = true;
}
readGrid();
// Need to add code to allocate memory on the device and copy the grid
// over.
Row *gridCpy = NULL;
cudaMalloc( (void **)&gridCpy, rows * sizeof( Row ) );
cudaMemcpy( gridCpy, grid, rows * sizeof( Row ), cudaMemcpyHostToDevice );
//allocate memory for results array
int *gpuResults = NULL;
cudaMalloc((void **)&gpuResults, rows * sizeof(int));
// Block and grid dimensions.
int threadsPerBlock = 250;
// Round up.
int blocksPerGrid = ( rows + threadsPerBlock - 1 ) / threadsPerBlock;
// Run our kernel on these block/grid dimensions
countSquares<<<blocksPerGrid, threadsPerBlock>>>( rows, cols, report, gpuResults, gridCpy );
if ( cudaGetLastError() != cudaSuccess )
fail( "Failure in CUDA kernel execution." );
int *results = (int *) malloc( rows * sizeof( int ) );
// Need to add code to copy the results list back to the host and
// add them up.
cudaMemcpy( results, gpuResults, rows * sizeof(int), cudaMemcpyDeviceToHost);
int total = 0;
for(int i = 0; i < rows; i++) {
total += results[i];//add all integers in results array to get total
}
printf( "Squares: %d\n", total );
// Free memory on the device and the host.
free(grid);
free(results);
cudaFree(gridCpy);
cudaFree(gpuResults);
cudaDeviceReset();
return 0;
} | // Elapsed Real Time for input-4.txt: 1.381 seconds
#include <stdio.h>
#include <stdbool.h>
#include <hip/hip_runtime.h>
// Size of the square we're looking for.
#define SQUARE_WIDTH 6
#define SQUARE_HEIGHT 6
// Maximum width of a row. Makes it easier to allocate the whole
// grid contiguously.
#define MAX_WIDTH 16384
// Type used for a row of the grid. Makes it easier to declare the
// grid as a pointer.
typedef char Row[ MAX_WIDTH ];
// Size of the grid of characters.
int rows, cols;
// Grid of letters.
Row *grid;
// Kernel, run by each thread to count complete squares in parallel.
__global__ void countSquares( int rows, int cols, bool report, int *gpuResults, Row *gridCpy ) {
// Unique index for this worker.
int r0 = blockDim.x * blockIdx.x + threadIdx.x;
int c = 0;
// Make sure I actually have something to work on.
if ( r0 + SQUARE_HEIGHT - 1 < rows ) {
for(int col = 0; col < cols; col++) {
if(col + 6 <= cols) {
bool check = false;//check if that grid actually makes a square or not.
char letters[26] = {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p','q','r','s','t','u','v','w','x','y','z'}; // array of alphabets.
for( int i = r0; i < r0 + 6; i++) {
for( int j = col; j < col + 6; j++) {
for( int k = 0; k < 26; k++) {
if(gridCpy[i][j] == letters[k]) { //if cell in grid has any aplhabet, change that alphabet bucket to 0.
letters[k] = '0';//if the letter is not yet, remove it.
}
}
}
}
for(int k = 0; k < 26; k++) {
if(letters[k] != '0') {
check = false;//if any letter in the array is not 0, the grid is not a square.
break;
} else {
check = true;//else it is true and continue to make sure all if true.
}
}
if(check == true) {
c += 1;//if it is a perfect square grid, increment the count for that index
if(report) {
printf("%d %d\n", r0, col);//if report is true, print the index
}
}
}
}
}
gpuResults[r0] = c;//put number of squares in the array
}
// Read the grid of characters.
void readGrid() {
// Read grid dimensions.
scanf( "%d%d", &rows, &cols );
if ( cols > MAX_WIDTH ) {
fprintf( stderr, "Input grid is too wide.\n" );
exit( EXIT_FAILURE );
}
// Make space to store the grid as a big, contiguous array.
grid = (Row *) malloc( rows * sizeof( Row ) );
// Read each row of the grid as a string, then copy everything
// but the null terminator into the grid array.
int rowCount = 0;
char buffer[ MAX_WIDTH + 1 ];
while ( rowCount < rows ) {
scanf( "%s", buffer );
memcpy( grid[ rowCount++ ], buffer, cols );
}
}
// General function to report a failure and exit.
static void fail( char const *message ) {
fprintf( stderr, "%s\n", message );
exit( 1 );
}
// Print out a usage message, then exit.
static void usage() {
printf( "usage: square [report]\n" );
exit( 1 );
}
//main
int main( int argc, char *argv[] ) {
// If there's an argument, it better be "report"
bool report = false;
if ( argc == 2 ) {
if ( strcmp( argv[ 1 ], "report" ) != 0 )
usage();
report = true;
}
readGrid();
// Need to add code to allocate memory on the device and copy the grid
// over.
Row *gridCpy = NULL;
hipMalloc( (void **)&gridCpy, rows * sizeof( Row ) );
hipMemcpy( gridCpy, grid, rows * sizeof( Row ), hipMemcpyHostToDevice );
//allocate memory for results array
int *gpuResults = NULL;
hipMalloc((void **)&gpuResults, rows * sizeof(int));
// Block and grid dimensions.
int threadsPerBlock = 250;
// Round up.
int blocksPerGrid = ( rows + threadsPerBlock - 1 ) / threadsPerBlock;
// Run our kernel on these block/grid dimensions
countSquares<<<blocksPerGrid, threadsPerBlock>>>( rows, cols, report, gpuResults, gridCpy );
if ( hipGetLastError() != hipSuccess )
fail( "Failure in CUDA kernel execution." );
int *results = (int *) malloc( rows * sizeof( int ) );
// Need to add code to copy the results list back to the host and
// add them up.
hipMemcpy( results, gpuResults, rows * sizeof(int), hipMemcpyDeviceToHost);
int total = 0;
for(int i = 0; i < rows; i++) {
total += results[i];//add all integers in results array to get total
}
printf( "Squares: %d\n", total );
// Free memory on the device and the host.
free(grid);
free(results);
hipFree(gridCpy);
hipFree(gpuResults);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Elapsed Real Time for input-4.txt: 1.381 seconds
#include <stdio.h>
#include <stdbool.h>
#include <hip/hip_runtime.h>
// Size of the square we're looking for.
#define SQUARE_WIDTH 6
#define SQUARE_HEIGHT 6
// Maximum width of a row. Makes it easier to allocate the whole
// grid contiguously.
#define MAX_WIDTH 16384
// Type used for a row of the grid. Makes it easier to declare the
// grid as a pointer.
typedef char Row[ MAX_WIDTH ];
// Size of the grid of characters.
int rows, cols;
// Grid of letters.
Row *grid;
// Kernel, run by each thread to count complete squares in parallel.
__global__ void countSquares( int rows, int cols, bool report, int *gpuResults, Row *gridCpy ) {
// Unique index for this worker.
int r0 = blockDim.x * blockIdx.x + threadIdx.x;
int c = 0;
// Make sure I actually have something to work on.
if ( r0 + SQUARE_HEIGHT - 1 < rows ) {
for(int col = 0; col < cols; col++) {
if(col + 6 <= cols) {
bool check = false;//check if that grid actually makes a square or not.
char letters[26] = {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p','q','r','s','t','u','v','w','x','y','z'}; // array of alphabets.
for( int i = r0; i < r0 + 6; i++) {
for( int j = col; j < col + 6; j++) {
for( int k = 0; k < 26; k++) {
if(gridCpy[i][j] == letters[k]) { //if cell in grid has any aplhabet, change that alphabet bucket to 0.
letters[k] = '0';//if the letter is not yet, remove it.
}
}
}
}
for(int k = 0; k < 26; k++) {
if(letters[k] != '0') {
check = false;//if any letter in the array is not 0, the grid is not a square.
break;
} else {
check = true;//else it is true and continue to make sure all if true.
}
}
if(check == true) {
c += 1;//if it is a perfect square grid, increment the count for that index
if(report) {
printf("%d %d\n", r0, col);//if report is true, print the index
}
}
}
}
}
gpuResults[r0] = c;//put number of squares in the array
}
// Read the grid of characters.
void readGrid() {
// Read grid dimensions.
scanf( "%d%d", &rows, &cols );
if ( cols > MAX_WIDTH ) {
fprintf( stderr, "Input grid is too wide.\n" );
exit( EXIT_FAILURE );
}
// Make space to store the grid as a big, contiguous array.
grid = (Row *) malloc( rows * sizeof( Row ) );
// Read each row of the grid as a string, then copy everything
// but the null terminator into the grid array.
int rowCount = 0;
char buffer[ MAX_WIDTH + 1 ];
while ( rowCount < rows ) {
scanf( "%s", buffer );
memcpy( grid[ rowCount++ ], buffer, cols );
}
}
// General function to report a failure and exit.
static void fail( char const *message ) {
fprintf( stderr, "%s\n", message );
exit( 1 );
}
// Print out a usage message, then exit.
static void usage() {
printf( "usage: square [report]\n" );
exit( 1 );
}
//main
int main( int argc, char *argv[] ) {
// If there's an argument, it better be "report"
bool report = false;
if ( argc == 2 ) {
if ( strcmp( argv[ 1 ], "report" ) != 0 )
usage();
report = true;
}
readGrid();
// Need to add code to allocate memory on the device and copy the grid
// over.
Row *gridCpy = NULL;
hipMalloc( (void **)&gridCpy, rows * sizeof( Row ) );
hipMemcpy( gridCpy, grid, rows * sizeof( Row ), hipMemcpyHostToDevice );
//allocate memory for results array
int *gpuResults = NULL;
hipMalloc((void **)&gpuResults, rows * sizeof(int));
// Block and grid dimensions.
int threadsPerBlock = 250;
// Round up.
int blocksPerGrid = ( rows + threadsPerBlock - 1 ) / threadsPerBlock;
// Run our kernel on these block/grid dimensions
countSquares<<<blocksPerGrid, threadsPerBlock>>>( rows, cols, report, gpuResults, gridCpy );
if ( hipGetLastError() != hipSuccess )
fail( "Failure in CUDA kernel execution." );
int *results = (int *) malloc( rows * sizeof( int ) );
// Need to add code to copy the results list back to the host and
// add them up.
hipMemcpy( results, gpuResults, rows * sizeof(int), hipMemcpyDeviceToHost);
int total = 0;
for(int i = 0; i < rows; i++) {
total += results[i];//add all integers in results array to get total
}
printf( "Squares: %d\n", total );
// Free memory on the device and the host.
free(grid);
free(results);
hipFree(gridCpy);
hipFree(gpuResults);
hipDeviceReset();
return 0;
} | .text
.file "square.hip"
.globl _Z27__device_stub__countSquaresiibPiPA16384_c # -- Begin function _Z27__device_stub__countSquaresiibPiPA16384_c
.p2align 4, 0x90
.type _Z27__device_stub__countSquaresiibPiPA16384_c,@function
_Z27__device_stub__countSquaresiibPiPA16384_c: # @_Z27__device_stub__countSquaresiibPiPA16384_c
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movb %dl, 7(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 7(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12countSquaresiibPiPA16384_c, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__countSquaresiibPiPA16384_c, .Lfunc_end0-_Z27__device_stub__countSquaresiibPiPA16384_c
.cfi_endproc
# -- End function
.globl _Z8readGridv # -- Begin function _Z8readGridv
.p2align 4, 0x90
.type _Z8readGridv,@function
_Z8readGridv: # @_Z8readGridv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16400, %rsp # imm = 0x4010
.cfi_def_cfa_offset 16432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $rows, %esi
movl $cols, %edx
xorl %eax, %eax
callq __isoc23_scanf
cmpl $16385, cols(%rip) # imm = 0x4001
jge .LBB1_5
# %bb.1:
movslq rows(%rip), %rbx
movq %rbx, %rdi
shlq $14, %rdi
callq malloc
movq %rax, grid(%rip)
testq %rbx, %rbx
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movq %rsp, %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r15
movq grid(%rip), %rdi
addq %r14, %rdi
movslq cols(%rip), %rdx
movq %rbx, %rsi
callq memcpy@PLT
movslq rows(%rip), %rax
addq $16384, %r14 # imm = 0x4000
cmpq %rax, %r15
jl .LBB1_3
.LBB1_4: # %._crit_edge
addq $16400, %rsp # imm = 0x4010
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 16432
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8readGridv, .Lfunc_end1-_Z8readGridv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
cmpl $2, %edi
jne .LBB2_2
# %bb.1:
movq 8(%rsi), %rdi
movl $.L.str.3, %esi
callq strcmp
testl %eax, %eax
jne .LBB2_10
.LBB2_2:
callq _Z8readGridv
movq $0, 16(%rsp)
movslq rows(%rip), %rsi
shlq $14, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movq grid(%rip), %rsi
movslq rows(%rip), %rdx
shlq $14, %rdx
movl $1, %ecx
callq hipMemcpy
movq $0, 8(%rsp)
movslq rows(%rip), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl $249, %eax
addl rows(%rip), %eax
cltq
imulq $274877907, %rax, %rdi # imm = 0x10624DD3
movq %rdi, %rax
shrq $63, %rax
sarq $36, %rdi
addl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $250, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
cmpl $2, %ebx
movl rows(%rip), %eax
movl cols(%rip), %ecx
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movl %eax, 28(%rsp)
movl %ecx, 24(%rsp)
sete 7(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12countSquaresiibPiPA16384_c, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.5:
movslq rows(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl rows(%rip), %eax
testl %eax, %eax
jle .LBB2_6
# %bb.8: # %.lr.ph.preheader
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %esi
incq %rcx
cmpq %rcx, %rax
jne .LBB2_9
jmp .LBB2_7
.LBB2_6:
xorl %esi, %esi
.LBB2_7: # %._crit_edge
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq grid(%rip), %rdi
callq free
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
movl $.L.str.4, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_10:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12countSquaresiibPiPA16384_c, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type rows,@object # @rows
.bss
.globl rows
.p2align 2, 0x0
rows:
.long 0 # 0x0
.size rows, 4
.type cols,@object # @cols
.globl cols
.p2align 2, 0x0
cols:
.long 0 # 0x0
.size cols, 4
.type grid,@object # @grid
.globl grid
.p2align 3, 0x0
grid:
.quad 0
.size grid, 8
.type _Z12countSquaresiibPiPA16384_c,@object # @_Z12countSquaresiibPiPA16384_c
.section .rodata,"a",@progbits
.globl _Z12countSquaresiibPiPA16384_c
.p2align 3, 0x0
_Z12countSquaresiibPiPA16384_c:
.quad _Z27__device_stub__countSquaresiibPiPA16384_c
.size _Z12countSquaresiibPiPA16384_c, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d%d"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Input grid is too wide.\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "report"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failure in CUDA kernel execution."
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Squares: %d\n"
.size .L.str.5, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s\n"
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12countSquaresiibPiPA16384_c"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: square [report]"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__countSquaresiibPiPA16384_c
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym rows
.addrsig_sym cols
.addrsig_sym _Z12countSquaresiibPiPA16384_c
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002053d_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d%d"
.LC1:
.string "Input grid is too wide.\n"
.LC2:
.string "%s"
.text
.globl _Z8readGridv
.type _Z8readGridv, @function
_Z8readGridv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16416
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $16, %rsp
.cfi_def_cfa_offset 16432
movq %fs:40, %rax
movq %rax, 16392(%rsp)
xorl %eax, %eax
leaq cols(%rip), %rdx
leaq rows(%rip), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
cmpl $16384, cols(%rip)
jg .L10
movl rows(%rip), %ebx
movslq %ebx, %rdi
salq $14, %rdi
call malloc@PLT
movq %rax, grid(%rip)
testl %ebx, %ebx
jle .L3
movl $0, %ebx
leaq .LC2(%rip), %r12
.L6:
movq %rsp, %rbp
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbx, %rdi
salq $14, %rdi
addq grid(%rip), %rdi
movslq cols(%rip), %rdx
movq %rbp, %rsi
call memcpy@PLT
addq $1, %rbx
cmpl %ebx, rows(%rip)
jg .L6
.L3:
movq 16392(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $16400, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8readGridv, .-_Z8readGridv
.globl _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
.type _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c, @function
_Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movb %dl, 20(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12countSquaresiibPiPA16384_c(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c, .-_Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
.globl _Z12countSquaresiibPiPA16384_c
.type _Z12countSquaresiibPiPA16384_c, @function
_Z12countSquaresiibPiPA16384_c:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %dl, %edx
call _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12countSquaresiibPiPA16384_c, .-_Z12countSquaresiibPiPA16384_c
.section .rodata.str1.1
.LC3:
.string "report"
.LC4:
.string "usage: square [report]\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Failure in CUDA kernel execution."
.section .rodata.str1.1
.LC6:
.string "%s\n"
.LC7:
.string "Squares: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L27
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call strcmp@PLT
movl $1, %ebx
testl %eax, %eax
jne .L32
.L21:
call _Z8readGridv
movq $0, (%rsp)
movslq rows(%rip), %rsi
salq $14, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movslq rows(%rip), %rdx
salq $14, %rdx
movl $1, %ecx
movq grid(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 8(%rsp)
movslq rows(%rip), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl rows(%rip), %eax
leal 249(%rax), %edx
movslq %edx, %rax
imulq $274877907, %rax, %rax
sarq $36, %rax
sarl $31, %edx
subl %edx, %eax
movl $250, 28(%rsp)
movl $1, 32(%rsp)
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L22:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L34
movslq rows(%rip), %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl rows(%rip), %edx
testl %edx, %edx
jle .L29
movq %rbx, %rax
movslq %edx, %rdx
leaq (%rbx,%rdx,4), %rcx
movl $0, %edx
.L25:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L25
.L24:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq grid(%rip), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl $0, %ebx
jmp .L21
.L33:
movzbl %bl, %edx
movq (%rsp), %r8
movq 8(%rsp), %rcx
movl cols(%rip), %esi
movl rows(%rip), %edi
call _Z44__device_stub__Z12countSquaresiibPiPA16384_ciibPiPA16384_c
jmp .L22
.L34:
leaq .LC5(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl $0, %edx
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z12countSquaresiibPiPA16384_c"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12countSquaresiibPiPA16384_c(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl grid
.bss
.align 8
.type grid, @object
.size grid, 8
grid:
.zero 8
.globl cols
.align 4
.type cols, @object
.size cols, 4
cols:
.zero 4
.globl rows
.align 4
.type rows, @object
.size rows, 4
rows:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square.hip"
.globl _Z27__device_stub__countSquaresiibPiPA16384_c # -- Begin function _Z27__device_stub__countSquaresiibPiPA16384_c
.p2align 4, 0x90
.type _Z27__device_stub__countSquaresiibPiPA16384_c,@function
_Z27__device_stub__countSquaresiibPiPA16384_c: # @_Z27__device_stub__countSquaresiibPiPA16384_c
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movb %dl, 7(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 7(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12countSquaresiibPiPA16384_c, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__countSquaresiibPiPA16384_c, .Lfunc_end0-_Z27__device_stub__countSquaresiibPiPA16384_c
.cfi_endproc
# -- End function
.globl _Z8readGridv # -- Begin function _Z8readGridv
.p2align 4, 0x90
.type _Z8readGridv,@function
_Z8readGridv: # @_Z8readGridv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16400, %rsp # imm = 0x4010
.cfi_def_cfa_offset 16432
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $rows, %esi
movl $cols, %edx
xorl %eax, %eax
callq __isoc23_scanf
cmpl $16385, cols(%rip) # imm = 0x4001
jge .LBB1_5
# %bb.1:
movslq rows(%rip), %rbx
movq %rbx, %rdi
shlq $14, %rdi
callq malloc
movq %rax, grid(%rip)
testq %rbx, %rbx
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movq %rsp, %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r15
movq grid(%rip), %rdi
addq %r14, %rdi
movslq cols(%rip), %rdx
movq %rbx, %rsi
callq memcpy@PLT
movslq rows(%rip), %rax
addq $16384, %r14 # imm = 0x4000
cmpq %rax, %r15
jl .LBB1_3
.LBB1_4: # %._crit_edge
addq $16400, %rsp # imm = 0x4010
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 16432
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8readGridv, .Lfunc_end1-_Z8readGridv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
cmpl $2, %edi
jne .LBB2_2
# %bb.1:
movq 8(%rsi), %rdi
movl $.L.str.3, %esi
callq strcmp
testl %eax, %eax
jne .LBB2_10
.LBB2_2:
callq _Z8readGridv
movq $0, 16(%rsp)
movslq rows(%rip), %rsi
shlq $14, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movq grid(%rip), %rsi
movslq rows(%rip), %rdx
shlq $14, %rdx
movl $1, %ecx
callq hipMemcpy
movq $0, 8(%rsp)
movslq rows(%rip), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl $249, %eax
addl rows(%rip), %eax
cltq
imulq $274877907, %rax, %rdi # imm = 0x10624DD3
movq %rdi, %rax
shrq $63, %rax
sarq $36, %rdi
addl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $250, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
cmpl $2, %ebx
movl rows(%rip), %eax
movl cols(%rip), %ecx
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movl %eax, 28(%rsp)
movl %ecx, 24(%rsp)
sete 7(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12countSquaresiibPiPA16384_c, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.5:
movslq rows(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl rows(%rip), %eax
testl %eax, %eax
jle .LBB2_6
# %bb.8: # %.lr.ph.preheader
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %esi
incq %rcx
cmpq %rcx, %rax
jne .LBB2_9
jmp .LBB2_7
.LBB2_6:
xorl %esi, %esi
.LBB2_7: # %._crit_edge
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq grid(%rip), %rdi
callq free
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
movl $.L.str.4, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_10:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12countSquaresiibPiPA16384_c, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type rows,@object # @rows
.bss
.globl rows
.p2align 2, 0x0
rows:
.long 0 # 0x0
.size rows, 4
.type cols,@object # @cols
.globl cols
.p2align 2, 0x0
cols:
.long 0 # 0x0
.size cols, 4
.type grid,@object # @grid
.globl grid
.p2align 3, 0x0
grid:
.quad 0
.size grid, 8
.type _Z12countSquaresiibPiPA16384_c,@object # @_Z12countSquaresiibPiPA16384_c
.section .rodata,"a",@progbits
.globl _Z12countSquaresiibPiPA16384_c
.p2align 3, 0x0
_Z12countSquaresiibPiPA16384_c:
.quad _Z27__device_stub__countSquaresiibPiPA16384_c
.size _Z12countSquaresiibPiPA16384_c, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d%d"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Input grid is too wide.\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "report"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failure in CUDA kernel execution."
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Squares: %d\n"
.size .L.str.5, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s\n"
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12countSquaresiibPiPA16384_c"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: square [report]"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__countSquaresiibPiPA16384_c
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym rows
.addrsig_sym cols
.addrsig_sym _Z12countSquaresiibPiPA16384_c
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //--blockDim=8 --gridDim=1
__global__ void a() {
unsigned tid = threadIdx.x;
if ((tid % 2) == 0)
__syncthreads();
else
__syncthreads();
} | code for sm_80
Function : _Z1av
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x001fc800078ec0ff */
/*0030*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*0040*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0050*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe40003800000 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //--blockDim=8 --gridDim=1
__global__ void a() {
unsigned tid = threadIdx.x;
if ((tid % 2) == 0)
__syncthreads();
else
__syncthreads();
} | .file "tmpxft_001b035a_00000000-6_a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1avv
.type _Z19__device_stub__Z1avv, @function
_Z19__device_stub__Z1avv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1av(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z19__device_stub__Z1avv, .-_Z19__device_stub__Z1avv
.globl _Z1av
.type _Z1av, @function
_Z1av:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1avv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z1av, .-_Z1av
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1av"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1av(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //--blockDim=8 --gridDim=1
__global__ void a() {
unsigned tid = threadIdx.x;
if ((tid % 2) == 0)
__syncthreads();
else
__syncthreads();
} | #include <hip/hip_runtime.h>
//--blockDim=8 --gridDim=1
__global__ void a() {
unsigned tid = threadIdx.x;
if ((tid % 2) == 0)
__syncthreads();
else
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//--blockDim=8 --gridDim=1
__global__ void a() {
unsigned tid = threadIdx.x;
if ((tid % 2) == 0)
__syncthreads();
else
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1av
.globl _Z1av
.p2align 8
.type _Z1av,@function
_Z1av:
v_and_b32_e32 v0, 1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v0
s_xor_b32 s0, exec_lo, s0
s_barrier
s_and_not1_saveexec_b32 s0, s0
s_barrier
s_or_b32 exec_lo, exec_lo, s0
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1av
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1av, .Lfunc_end0-_Z1av
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1av
.private_segment_fixed_size: 0
.sgpr_count: 1
.sgpr_spill_count: 0
.symbol: _Z1av.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//--blockDim=8 --gridDim=1
__global__ void a() {
unsigned tid = threadIdx.x;
if ((tid % 2) == 0)
__syncthreads();
else
__syncthreads();
} | .text
.file "a.hip"
.globl _Z16__device_stub__av # -- Begin function _Z16__device_stub__av
.p2align 4, 0x90
.type _Z16__device_stub__av,@function
_Z16__device_stub__av: # @_Z16__device_stub__av
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1av, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__av, .Lfunc_end0-_Z16__device_stub__av
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1av, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1av,@object # @_Z1av
.section .rodata,"a",@progbits
.globl _Z1av
.p2align 3, 0x0
_Z1av:
.quad _Z16__device_stub__av
.size _Z1av, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1av"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__av
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1av
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1av
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x001fc800078ec0ff */
/*0030*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*0040*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0050*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe40003800000 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1av
.globl _Z1av
.p2align 8
.type _Z1av,@function
_Z1av:
v_and_b32_e32 v0, 1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v0
s_xor_b32 s0, exec_lo, s0
s_barrier
s_and_not1_saveexec_b32 s0, s0
s_barrier
s_or_b32 exec_lo, exec_lo, s0
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1av
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1av, .Lfunc_end0-_Z1av
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1av
.private_segment_fixed_size: 0
.sgpr_count: 1
.sgpr_spill_count: 0
.symbol: _Z1av.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b035a_00000000-6_a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1avv
.type _Z19__device_stub__Z1avv, @function
_Z19__device_stub__Z1avv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1av(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z19__device_stub__Z1avv, .-_Z19__device_stub__Z1avv
.globl _Z1av
.type _Z1av, @function
_Z1av:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1avv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z1av, .-_Z1av
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1av"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1av(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "a.hip"
.globl _Z16__device_stub__av # -- Begin function _Z16__device_stub__av
.p2align 4, 0x90
.type _Z16__device_stub__av,@function
_Z16__device_stub__av: # @_Z16__device_stub__av
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1av, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__av, .Lfunc_end0-_Z16__device_stub__av
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1av, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1av,@object # @_Z1av
.section .rodata,"a",@progbits
.globl _Z1av
.p2align 3, 0x0
_Z1av:
.quad _Z16__device_stub__av
.size _Z1av, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1av"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__av
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1av
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
void initialInt(int *ip, int size){
for(int i = 0; i<size; i++){
ip[i] = i;
}
}
void printMatrix(int *C, const int nx, const int ny){
int *ic = C;
printf("\n Matrix: (%d, %d) \n", nx, ny);
for (int iy = 0; iy < ny; iy++){
for(int ix = 0; ix < nx; ix++){
printf("%3d", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void printfThreadIndex(int *A, const int nx, const int ny){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.x * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d,%d) block_id (%d, %d) coordinate (%d, %d) global index %2d\n", threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, A[idx]);
}
int main(int argc, char **argv){
printf("%s Starting...\n", argv[0]);
//get device information
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d:%s\n", dev, deviceProp.name);
cudaSetDevice(dev);
//set matrix dimention
int nx = 8;
int ny = 6;
int nxy = nx*ny;
int nBytes = nxy * sizeof(float);
//malloc host memory
int *h_A;
h_A = (int *)malloc(nBytes);
//initialize host matrix with integer
initialInt(h_A, nxy);
printMatrix(h_A, nx, ny);
//malloc device memory
int *d_MatA;
cudaMalloc((void **)&d_MatA, nBytes);
//transfer data from host to device
cudaMemcpy(d_MatA, h_A, nBytes, cudaMemcpyHostToDevice);
//setup execution configuration
dim3 block(4, 2);
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
//invoke the kernel
printfThreadIndex<<< grid, block >>>(d_MatA, nx, ny);
cudaDeviceSynchronize();
// free host and device memory
cudaFree(d_MatA);
free(h_A);
//reset device
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z17printfThreadIndexPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R16, SR_TID.X ; /* 0x0000000000107919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e280000002500 */
/*0060*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R8, R18.reuse, c[0x0][0x0], R16 ; /* 0x0000000012087a24 */
/* 0x041fe400078e0210 */
/*0080*/ IMAD R9, R18, c[0x0][0x4], R17 ; /* 0x0000010012097a24 */
/* 0x002fc800078e0211 */
/*0090*/ IMAD R10, R9, c[0x0][0x168], R8 ; /* 0x00005a00090a7a24 */
/* 0x000fc800078e0208 */
/*00a0*/ IMAD.WIDE.U32 R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0003 */
/*00b0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ S2R R19, SR_CTAID.Y ; /* 0x0000000000137919 */
/* 0x000e220000002600 */
/*0100*/ LDC.64 R12, c[0x4][R0] ; /* 0x01000000000c7b82 */
/* 0x0002e20000000a00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0130*/ STL.128 [R1], R16 ; /* 0x0000001001007387 */
/* 0x0013e80000100c00 */
/*0140*/ STL.128 [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0043e60000100c00 */
/*0150*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x008fe40000000000 */
/*0160*/ MOV R9, 0x1d0 ; /* 0x000001d000097802 */
/* 0x002fe40000000f00 */
/*0170*/ MOV R20, 0x150 ; /* 0x0000015000147802 */
/* 0x000fc40000000f00 */
/*0180*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01a0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*01b0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01c0*/ CALL.ABS.NOINC R12 ; /* 0x000000000c007343 */
/* 0x000fea0003c00000 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
void initialInt(int *ip, int size){
for(int i = 0; i<size; i++){
ip[i] = i;
}
}
void printMatrix(int *C, const int nx, const int ny){
int *ic = C;
printf("\n Matrix: (%d, %d) \n", nx, ny);
for (int iy = 0; iy < ny; iy++){
for(int ix = 0; ix < nx; ix++){
printf("%3d", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void printfThreadIndex(int *A, const int nx, const int ny){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.x * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d,%d) block_id (%d, %d) coordinate (%d, %d) global index %2d\n", threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, A[idx]);
}
int main(int argc, char **argv){
printf("%s Starting...\n", argv[0]);
//get device information
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d:%s\n", dev, deviceProp.name);
cudaSetDevice(dev);
//set matrix dimention
int nx = 8;
int ny = 6;
int nxy = nx*ny;
int nBytes = nxy * sizeof(float);
//malloc host memory
int *h_A;
h_A = (int *)malloc(nBytes);
//initialize host matrix with integer
initialInt(h_A, nxy);
printMatrix(h_A, nx, ny);
//malloc device memory
int *d_MatA;
cudaMalloc((void **)&d_MatA, nBytes);
//transfer data from host to device
cudaMemcpy(d_MatA, h_A, nBytes, cudaMemcpyHostToDevice);
//setup execution configuration
dim3 block(4, 2);
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
//invoke the kernel
printfThreadIndex<<< grid, block >>>(d_MatA, nx, ny);
cudaDeviceSynchronize();
// free host and device memory
cudaFree(d_MatA);
free(h_A);
//reset device
cudaDeviceReset();
return 0;
} | .file "tmpxft_000955a6_00000000-6_checkThreadIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initialIntPii
.type _Z10initialIntPii, @function
_Z10initialIntPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10initialIntPii, .-_Z10initialIntPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n Matrix: (%d, %d) \n"
.LC1:
.string "%3d"
.LC2:
.string "\n"
.text
.globl _Z11printMatrixPiii
.type _Z11printMatrixPiii, @function
_Z11printMatrixPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %r14d
movl %esi, 8(%rsp)
movl %edx, %ebx
movl %edx, 12(%rsp)
movl %edx, %ecx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L8
movslq %r14d, %r15
salq $2, %r15
leaq 0(%r13,%r15), %rbp
movl $0, %r14d
leaq .LC1(%rip), %r12
jmp .L9
.L10:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
.L12:
addq %r15, %r13
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 12(%rsp)
je .L8
.L9:
movq %r13, %rbx
cmpl $0, 8(%rsp)
jg .L10
jmp .L12
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11printMatrixPiii, .-_Z11printMatrixPiii
.globl _Z39__device_stub__Z17printfThreadIndexPiiiPiii
.type _Z39__device_stub__Z17printfThreadIndexPiiiPiii, @function
_Z39__device_stub__Z17printfThreadIndexPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17printfThreadIndexPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z17printfThreadIndexPiiiPiii, .-_Z39__device_stub__Z17printfThreadIndexPiiiPiii
.globl _Z17printfThreadIndexPiii
.type _Z17printfThreadIndexPiii, @function
_Z17printfThreadIndexPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17printfThreadIndexPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z17printfThreadIndexPiii, .-_Z17printfThreadIndexPiii
.section .rodata.str1.1
.LC3:
.string "%s Starting...\n"
.LC4:
.string "Using Device %d:%s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1072, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 32(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl $192, %edi
call malloc@PLT
movq %rax, %rbx
movl $48, %esi
movq %rax, %rdi
call _Z10initialIntPii
movl $6, %edx
movl $8, %esi
movq %rbx, %rdi
call _Z11printMatrixPiii
movq %rsp, %rdi
movl $192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $192, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $4, 8(%rsp)
movl $2, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $6, %edx
movl $8, %esi
movq (%rsp), %rdi
call _Z39__device_stub__Z17printfThreadIndexPiiiPiii
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z17printfThreadIndexPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17printfThreadIndexPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
void initialInt(int *ip, int size){
for(int i = 0; i<size; i++){
ip[i] = i;
}
}
void printMatrix(int *C, const int nx, const int ny){
int *ic = C;
printf("\n Matrix: (%d, %d) \n", nx, ny);
for (int iy = 0; iy < ny; iy++){
for(int ix = 0; ix < nx; ix++){
printf("%3d", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void printfThreadIndex(int *A, const int nx, const int ny){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.x * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d,%d) block_id (%d, %d) coordinate (%d, %d) global index %2d\n", threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, A[idx]);
}
int main(int argc, char **argv){
printf("%s Starting...\n", argv[0]);
//get device information
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d:%s\n", dev, deviceProp.name);
cudaSetDevice(dev);
//set matrix dimention
int nx = 8;
int ny = 6;
int nxy = nx*ny;
int nBytes = nxy * sizeof(float);
//malloc host memory
int *h_A;
h_A = (int *)malloc(nBytes);
//initialize host matrix with integer
initialInt(h_A, nxy);
printMatrix(h_A, nx, ny);
//malloc device memory
int *d_MatA;
cudaMalloc((void **)&d_MatA, nBytes);
//transfer data from host to device
cudaMemcpy(d_MatA, h_A, nBytes, cudaMemcpyHostToDevice);
//setup execution configuration
dim3 block(4, 2);
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
//invoke the kernel
printfThreadIndex<<< grid, block >>>(d_MatA, nx, ny);
cudaDeviceSynchronize();
// free host and device memory
cudaFree(d_MatA);
free(h_A);
//reset device
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
void initialInt(int *ip, int size){
for(int i = 0; i<size; i++){
ip[i] = i;
}
}
void printMatrix(int *C, const int nx, const int ny){
int *ic = C;
printf("\n Matrix: (%d, %d) \n", nx, ny);
for (int iy = 0; iy < ny; iy++){
for(int ix = 0; ix < nx; ix++){
printf("%3d", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void printfThreadIndex(int *A, const int nx, const int ny){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.x * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d,%d) block_id (%d, %d) coordinate (%d, %d) global index %2d\n", threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, A[idx]);
}
int main(int argc, char **argv){
printf("%s Starting...\n", argv[0]);
//get device information
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d:%s\n", dev, deviceProp.name);
hipSetDevice(dev);
//set matrix dimention
int nx = 8;
int ny = 6;
int nxy = nx*ny;
int nBytes = nxy * sizeof(float);
//malloc host memory
int *h_A;
h_A = (int *)malloc(nBytes);
//initialize host matrix with integer
initialInt(h_A, nxy);
printMatrix(h_A, nx, ny);
//malloc device memory
int *d_MatA;
hipMalloc((void **)&d_MatA, nBytes);
//transfer data from host to device
hipMemcpy(d_MatA, h_A, nBytes, hipMemcpyHostToDevice);
//setup execution configuration
dim3 block(4, 2);
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
//invoke the kernel
printfThreadIndex<<< grid, block >>>(d_MatA, nx, ny);
hipDeviceSynchronize();
// free host and device memory
hipFree(d_MatA);
free(h_A);
//reset device
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void initialInt(int *ip, int size){
for(int i = 0; i<size; i++){
ip[i] = i;
}
}
void printMatrix(int *C, const int nx, const int ny){
int *ic = C;
printf("\n Matrix: (%d, %d) \n", nx, ny);
for (int iy = 0; iy < ny; iy++){
for(int ix = 0; ix < nx; ix++){
printf("%3d", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void printfThreadIndex(int *A, const int nx, const int ny){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.x * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d,%d) block_id (%d, %d) coordinate (%d, %d) global index %2d\n", threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, A[idx]);
}
int main(int argc, char **argv){
printf("%s Starting...\n", argv[0]);
//get device information
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d:%s\n", dev, deviceProp.name);
hipSetDevice(dev);
//set matrix dimention
int nx = 8;
int ny = 6;
int nxy = nx*ny;
int nBytes = nxy * sizeof(float);
//malloc host memory
int *h_A;
h_A = (int *)malloc(nBytes);
//initialize host matrix with integer
initialInt(h_A, nxy);
printMatrix(h_A, nx, ny);
//malloc device memory
int *d_MatA;
hipMalloc((void **)&d_MatA, nBytes);
//transfer data from host to device
hipMemcpy(d_MatA, h_A, nBytes, hipMemcpyHostToDevice);
//setup execution configuration
dim3 block(4, 2);
dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
//invoke the kernel
printfThreadIndex<<< grid, block >>>(d_MatA, nx, ny);
hipDeviceSynchronize();
// free host and device memory
hipFree(d_MatA);
free(h_A);
//reset device
hipDeviceReset();
return 0;
} | .text
.file "checkThreadIndex.hip"
.globl _Z10initialIntPii # -- Begin function _Z10initialIntPii
.p2align 4, 0x90
.type _Z10initialIntPii,@function
_Z10initialIntPii: # @_Z10initialIntPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initialIntPii, .Lfunc_end0-_Z10initialIntPii
.cfi_endproc
# -- End function
.globl _Z11printMatrixPiii # -- Begin function _Z11printMatrixPiii
.p2align 4, 0x90
.type _Z11printMatrixPiii,@function
_Z11printMatrixPiii: # @_Z11printMatrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rdi, %r14
movl $.L.str, %edi
movl %esi, 4(%rsp) # 4-byte Spill
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ebp
movl 4(%rsp), %eax # 4-byte Reload
movslq %eax, %r15
movl %eax, %r12d
shlq $2, %r15
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r13d
addq %r15, %r14
cmpl %ebp, %r13d
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge19
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11printMatrixPiii, .Lfunc_end1-_Z11printMatrixPiii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__printfThreadIndexPiii # -- Begin function _Z32__device_stub__printfThreadIndexPiii
.p2align 4, 0x90
.type _Z32__device_stub__printfThreadIndexPiii,@function
_Z32__device_stub__printfThreadIndexPiii: # @_Z32__device_stub__printfThreadIndexPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17printfThreadIndexPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z32__device_stub__printfThreadIndexPiii, .Lfunc_end2-_Z32__device_stub__printfThreadIndexPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
xorl %r14d, %r14d
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 104(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.4, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movl $192, %edi
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r14d, (%rbx,%r14,4)
incq %r14
cmpq $48, %r14
jne .LBB3_1
# %bb.2: # %_Z10initialIntPii.exit
movl $.L.str, %edi
movl $8, %esi
movl $6, %edx
xorl %eax, %eax
callq printf
xorl %ebp, %ebp
movq %rbx, %r14
.p2align 4, 0x90
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i26
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $8, %r15
jne .LBB3_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB3_3 Depth=1
addq $32, %r14
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl $6, %ebp
jne .LBB3_3
# %bb.6: # %_Z11printMatrixPiii.exit
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $192, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $192, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $12884901890, %rdi # imm = 0x300000002
movabsq $8589934596, %rdx # imm = 0x200000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $8, 20(%rsp)
movl $6, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17printfThreadIndexPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17printfThreadIndexPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Matrix: (%d, %d) \n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%3d"
.size .L.str.1, 4
.type _Z17printfThreadIndexPiii,@object # @_Z17printfThreadIndexPiii
.section .rodata,"a",@progbits
.globl _Z17printfThreadIndexPiii
.p2align 3, 0x0
_Z17printfThreadIndexPiii:
.quad _Z32__device_stub__printfThreadIndexPiii
.size _Z17printfThreadIndexPiii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%s Starting...\n"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Using Device %d:%s\n"
.size .L.str.4, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17printfThreadIndexPiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__printfThreadIndexPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17printfThreadIndexPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000955a6_00000000-6_checkThreadIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initialIntPii
.type _Z10initialIntPii, @function
_Z10initialIntPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10initialIntPii, .-_Z10initialIntPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n Matrix: (%d, %d) \n"
.LC1:
.string "%3d"
.LC2:
.string "\n"
.text
.globl _Z11printMatrixPiii
.type _Z11printMatrixPiii, @function
_Z11printMatrixPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %r14d
movl %esi, 8(%rsp)
movl %edx, %ebx
movl %edx, 12(%rsp)
movl %edx, %ecx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L8
movslq %r14d, %r15
salq $2, %r15
leaq 0(%r13,%r15), %rbp
movl $0, %r14d
leaq .LC1(%rip), %r12
jmp .L9
.L10:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
.L12:
addq %r15, %r13
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 12(%rsp)
je .L8
.L9:
movq %r13, %rbx
cmpl $0, 8(%rsp)
jg .L10
jmp .L12
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11printMatrixPiii, .-_Z11printMatrixPiii
.globl _Z39__device_stub__Z17printfThreadIndexPiiiPiii
.type _Z39__device_stub__Z17printfThreadIndexPiiiPiii, @function
_Z39__device_stub__Z17printfThreadIndexPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17printfThreadIndexPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z17printfThreadIndexPiiiPiii, .-_Z39__device_stub__Z17printfThreadIndexPiiiPiii
.globl _Z17printfThreadIndexPiii
.type _Z17printfThreadIndexPiii, @function
_Z17printfThreadIndexPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17printfThreadIndexPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z17printfThreadIndexPiii, .-_Z17printfThreadIndexPiii
.section .rodata.str1.1
.LC3:
.string "%s Starting...\n"
.LC4:
.string "Using Device %d:%s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1072, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 32(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl $192, %edi
call malloc@PLT
movq %rax, %rbx
movl $48, %esi
movq %rax, %rdi
call _Z10initialIntPii
movl $6, %edx
movl $8, %esi
movq %rbx, %rdi
call _Z11printMatrixPiii
movq %rsp, %rdi
movl $192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $192, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $4, 8(%rsp)
movl $2, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $6, %edx
movl $8, %esi
movq (%rsp), %rdi
call _Z39__device_stub__Z17printfThreadIndexPiiiPiii
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z17printfThreadIndexPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17printfThreadIndexPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "checkThreadIndex.hip"
.globl _Z10initialIntPii # -- Begin function _Z10initialIntPii
.p2align 4, 0x90
.type _Z10initialIntPii,@function
_Z10initialIntPii: # @_Z10initialIntPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initialIntPii, .Lfunc_end0-_Z10initialIntPii
.cfi_endproc
# -- End function
.globl _Z11printMatrixPiii # -- Begin function _Z11printMatrixPiii
.p2align 4, 0x90
.type _Z11printMatrixPiii,@function
_Z11printMatrixPiii: # @_Z11printMatrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rdi, %r14
movl $.L.str, %edi
movl %esi, 4(%rsp) # 4-byte Spill
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ebp
movl 4(%rsp), %eax # 4-byte Reload
movslq %eax, %r15
movl %eax, %r12d
shlq $2, %r15
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r13d
addq %r15, %r14
cmpl %ebp, %r13d
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge19
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11printMatrixPiii, .Lfunc_end1-_Z11printMatrixPiii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__printfThreadIndexPiii # -- Begin function _Z32__device_stub__printfThreadIndexPiii
.p2align 4, 0x90
.type _Z32__device_stub__printfThreadIndexPiii,@function
_Z32__device_stub__printfThreadIndexPiii: # @_Z32__device_stub__printfThreadIndexPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17printfThreadIndexPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z32__device_stub__printfThreadIndexPiii, .Lfunc_end2-_Z32__device_stub__printfThreadIndexPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
xorl %r14d, %r14d
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 104(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.4, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movl $192, %edi
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r14d, (%rbx,%r14,4)
incq %r14
cmpq $48, %r14
jne .LBB3_1
# %bb.2: # %_Z10initialIntPii.exit
movl $.L.str, %edi
movl $8, %esi
movl $6, %edx
xorl %eax, %eax
callq printf
xorl %ebp, %ebp
movq %rbx, %r14
.p2align 4, 0x90
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i26
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $8, %r15
jne .LBB3_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB3_3 Depth=1
addq $32, %r14
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl $6, %ebp
jne .LBB3_3
# %bb.6: # %_Z11printMatrixPiii.exit
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $192, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $192, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $12884901890, %rdi # imm = 0x300000002
movabsq $8589934596, %rdx # imm = 0x200000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $8, 20(%rsp)
movl $6, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17printfThreadIndexPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17printfThreadIndexPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Matrix: (%d, %d) \n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%3d"
.size .L.str.1, 4
.type _Z17printfThreadIndexPiii,@object # @_Z17printfThreadIndexPiii
.section .rodata,"a",@progbits
.globl _Z17printfThreadIndexPiii
.p2align 3, 0x0
_Z17printfThreadIndexPiii:
.quad _Z32__device_stub__printfThreadIndexPiii
.size _Z17printfThreadIndexPiii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%s Starting...\n"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Using Device %d:%s\n"
.size .L.str.4, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17printfThreadIndexPiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__printfThreadIndexPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17printfThreadIndexPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
//Since this is matrix multiplication, A.width must be equal to B.height and the final matrix has height A.height and width B.width
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 32 //32 is the max since it means there are 32*32=1024 threads operating for each block
#define ARR_DIM (2048*2048)
#define WIDTH 2048
#define HEIGHT 2048
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(float *A, float *B, float *C);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(Matrix *A, Matrix *B, Matrix *C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A->width; d_A.height = A->height;
size_t size = A->width * A->height * sizeof(float);
cudaMalloc((void **)&d_A.elements, size);
cudaMemcpy(d_A.elements, A->elements, size,
cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B->width; d_B.height = B->height;
size = B->width * B->height * sizeof(float);
cudaMalloc((void **)&d_B.elements, size);
cudaMemcpy(d_B.elements, B->elements, size,
cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C->width; d_C.height = C->height;
size = C->width * C->height * sizeof(float);
cudaMalloc((void **)&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B->width / dimBlock.x, A->height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A.elements, d_B.elements, d_C.elements);
//This is causing a segmentation fault
// Read C from device memory
cudaMemcpy(C->elements, d_C.elements, size,
cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(float *A, float *B, float *C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < WIDTH; ++e)
Cvalue += A[row * WIDTH + e]
* B[e * WIDTH + col];
C[row * WIDTH + col] = Cvalue;
//printf("VAL=%f row=%d col=%d\n", Cvalue, row, col);
}
__global__ void cudaRandomize(float *arr){
float val;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
arr[row*WIDTH + col] = 1.654981;
}
float* generateRandArray(){
float* a = (float *)malloc(ARR_DIM*sizeof(float));
int i = 0;
for(i; i < ARR_DIM; i++){
a[i] = rand()%100 + 1;
}
return a;
}
int main(){
Matrix *A,*B,*C;
A = (Matrix *)malloc(sizeof(Matrix));
B = (Matrix *)malloc(sizeof(Matrix));
C = (Matrix *)malloc(sizeof(Matrix));
A->width = WIDTH;
A->height = HEIGHT;
B->width=WIDTH;
B->height = HEIGHT;
C->width = WIDTH;
C->height = HEIGHT;
A->elements = (float *)malloc(ARR_DIM*sizeof(float));
B->elements = (float *)malloc(ARR_DIM*sizeof(float));
float * d_A, *d_B;
size_t size = A->width * A->height * sizeof(float);
cudaMalloc((void**)&d_A, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(A->width / dimBlock.x, A->height / dimBlock.y);
cudaRandomize<<<dimGrid, dimBlock>>>(d_A);
cudaMemcpy(A->elements, d_A, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
size = B->width * B->height * sizeof(float);
cudaMalloc((void**)&d_B, size);
dim3 dimBlock2(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid2(B->width / dimBlock.x, B->height / dimBlock.y);
cudaRandomize<<<dimGrid2, dimBlock2>>>(d_B);
cudaMemcpy(B->elements, d_B, size, cudaMemcpyDeviceToHost);
cudaFree(d_B);
C->elements = (float *)malloc(ARR_DIM*sizeof(float));
for(int i = 0; i < 500; i++){
printf("i=%d\n",i);
MatMul(A,B,C);
}
free(A->elements);
free(B->elements);
free(C->elements);
return 0;
} | code for sm_80
Function : _Z13cudaRandomizePf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R5, 0x3fd3d66b ; /* 0x3fd3d66b00057802 */
/* 0x000fc60000000f00 */
/*00a0*/ LEA R3, R0, R3, 0xb ; /* 0x0000000300037211 */
/* 0x000fcc00078e58ff */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12MatMulKernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*00a0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00b0*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0200 */
/*00c0*/ SHF.L.U32 R9, R9, 0xb, RZ ; /* 0x0000000b09097819 */
/* 0x000fe200000006ff */
/*00d0*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fc600078e0203 */
/*00e0*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0100*/ IMAD.WIDE R14, R9, 0x4, R4 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0204 */
/*0110*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0120*/ IMAD.WIDE R2, R11, 0x4, R4 ; /* 0x000000040b027825 */
/* 0x000fe400078e0204 */
/*0130*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*0140*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe400078e0206 */
/*0150*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R27, [R6.64+0x2000] ; /* 0x00200004061b7981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R19, [R6.64+0x4000] ; /* 0x0040000406137981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R20, [R6.64+0x6000] ; /* 0x0060000406147981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R25, [R6.64+0x8000] ; /* 0x0080000406197981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100402127981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R21, [R6.64+0xa000] ; /* 0x00a0000406157981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0xc000] ; /* 0x00c00004060d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R15, [R6.64+0xe000] ; /* 0x00e00004060f7981 */
/* 0x001f68000c1e1900 */
/*0230*/ LDG.E R26, [R6.64+0x1e000] ; /* 0x01e00004061a7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x38] ; /* 0x00003804021d7981 */
/* 0x000f62000c1e1900 */
/*0250*/ FFMA R14, R17, R14, R12 ; /* 0x0000000e110e7223 */
/* 0x004fc6000000000c */
/*0260*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ FFMA R24, R27, R24, R14 ; /* 0x000000181b187223 */
/* 0x008fc6000000000e */
/*0280*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R17, [R6.64+0x10000] ; /* 0x0100000406117981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x010fc60000000018 */
/*02b0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R19, [R6.64+0x12000] ; /* 0x0120000406137981 */
/* 0x000f22000c1e1900 */
/*02d0*/ FFMA R24, R20, R23, R24 ; /* 0x0000001714187223 */
/* 0x020fc60000000018 */
/*02e0*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R20, [R6.64+0x14000] ; /* 0x0140000406147981 */
/* 0x000f62000c1e1900 */
/*0300*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x000fc60000000018 */
/*0310*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R22, [R6.64+0x16000] ; /* 0x0160000406167981 */
/* 0x000f62000c1e1900 */
/*0330*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x000fc60000000018 */
/*0340*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R18, [R6.64+0x18000] ; /* 0x0180000406127981 */
/* 0x000f62000c1e1900 */
/*0360*/ FFMA R28, R13, R10, R24 ; /* 0x0000000a0d1c7223 */
/* 0x000fc60000000018 */
/*0370*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R13, [R6.64+0x1a000] ; /* 0x01a00004060d7981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x1c000] ; /* 0x01c00004060a7981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003404021b7981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R8, 0x800, PT ; /* 0x000008000800780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x20000, URZ ; /* 0x0002000006067890 */
/* 0x000fe2000ff1e03f */
/*03e0*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*03f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0400*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0410*/ FFMA R12, R15, R12, R28 ; /* 0x0000000c0f0c7223 */
/* 0x004fc8000000001c */
/*0420*/ FFMA R12, R17, R14, R12 ; /* 0x0000000e110c7223 */
/* 0x008fc8000000000c */
/*0430*/ FFMA R12, R19, R16, R12 ; /* 0x00000010130c7223 */
/* 0x010fc8000000000c */
/*0440*/ FFMA R12, R20, R23, R12 ; /* 0x00000017140c7223 */
/* 0x020fc8000000000c */
/*0450*/ FFMA R12, R22, R25, R12 ; /* 0x00000019160c7223 */
/* 0x000fc8000000000c */
/*0460*/ FFMA R12, R18, R21, R12 ; /* 0x00000015120c7223 */
/* 0x000fc8000000000c */
/*0470*/ FFMA R12, R13, R24, R12 ; /* 0x000000180d0c7223 */
/* 0x000fc8000000000c */
/*0480*/ FFMA R12, R10, R27, R12 ; /* 0x0000001b0a0c7223 */
/* 0x000fc8000000000c */
/*0490*/ FFMA R12, R26, R29, R12 ; /* 0x0000001d1a0c7223 */
/* 0x000fe2000000000c */
/*04a0*/ @P0 BRA 0xf0 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04c0*/ IADD3 R2, R0, R9, RZ ; /* 0x0000000900027210 */
/* 0x000fd20007ffe0ff */
/*04d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04e0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
//Since this is matrix multiplication, A.width must be equal to B.height and the final matrix has height A.height and width B.width
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 32 //32 is the max since it means there are 32*32=1024 threads operating for each block
#define ARR_DIM (2048*2048)
#define WIDTH 2048
#define HEIGHT 2048
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(float *A, float *B, float *C);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(Matrix *A, Matrix *B, Matrix *C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A->width; d_A.height = A->height;
size_t size = A->width * A->height * sizeof(float);
cudaMalloc((void **)&d_A.elements, size);
cudaMemcpy(d_A.elements, A->elements, size,
cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B->width; d_B.height = B->height;
size = B->width * B->height * sizeof(float);
cudaMalloc((void **)&d_B.elements, size);
cudaMemcpy(d_B.elements, B->elements, size,
cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C->width; d_C.height = C->height;
size = C->width * C->height * sizeof(float);
cudaMalloc((void **)&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B->width / dimBlock.x, A->height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A.elements, d_B.elements, d_C.elements);
//This is causing a segmentation fault
// Read C from device memory
cudaMemcpy(C->elements, d_C.elements, size,
cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(float *A, float *B, float *C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < WIDTH; ++e)
Cvalue += A[row * WIDTH + e]
* B[e * WIDTH + col];
C[row * WIDTH + col] = Cvalue;
//printf("VAL=%f row=%d col=%d\n", Cvalue, row, col);
}
__global__ void cudaRandomize(float *arr){
float val;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
arr[row*WIDTH + col] = 1.654981;
}
float* generateRandArray(){
float* a = (float *)malloc(ARR_DIM*sizeof(float));
int i = 0;
for(i; i < ARR_DIM; i++){
a[i] = rand()%100 + 1;
}
return a;
}
int main(){
Matrix *A,*B,*C;
A = (Matrix *)malloc(sizeof(Matrix));
B = (Matrix *)malloc(sizeof(Matrix));
C = (Matrix *)malloc(sizeof(Matrix));
A->width = WIDTH;
A->height = HEIGHT;
B->width=WIDTH;
B->height = HEIGHT;
C->width = WIDTH;
C->height = HEIGHT;
A->elements = (float *)malloc(ARR_DIM*sizeof(float));
B->elements = (float *)malloc(ARR_DIM*sizeof(float));
float * d_A, *d_B;
size_t size = A->width * A->height * sizeof(float);
cudaMalloc((void**)&d_A, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(A->width / dimBlock.x, A->height / dimBlock.y);
cudaRandomize<<<dimGrid, dimBlock>>>(d_A);
cudaMemcpy(A->elements, d_A, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
size = B->width * B->height * sizeof(float);
cudaMalloc((void**)&d_B, size);
dim3 dimBlock2(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid2(B->width / dimBlock.x, B->height / dimBlock.y);
cudaRandomize<<<dimGrid2, dimBlock2>>>(d_B);
cudaMemcpy(B->elements, d_B, size, cudaMemcpyDeviceToHost);
cudaFree(d_B);
C->elements = (float *)malloc(ARR_DIM*sizeof(float));
for(int i = 0; i < 500; i++){
printf("i=%d\n",i);
MatMul(A,B,C);
}
free(A->elements);
free(B->elements);
free(C->elements);
return 0;
} | .file "tmpxft_0010ffa2_00000000-6_cudaMatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17generateRandArrayv
.type _Z17generateRandArrayv, @function
_Z17generateRandArrayv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 16777216(%rax), %rbp
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L4
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z17generateRandArrayv, .-_Z17generateRandArrayv
.globl _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
.type _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_, @function
_Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12MatMulKernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_, .-_Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
.globl _Z12MatMulKernelPfS_S_
.type _Z12MatMulKernelPfS_S_, @function
_Z12MatMulKernelPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12MatMulKernelPfS_S_, .-_Z12MatMulKernelPfS_S_
.globl _Z6MatMulP6MatrixS0_S0_
.type _Z6MatMulP6MatrixS0_S0_, @function
_Z6MatMulP6MatrixS0_S0_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl (%rdi), %ebx
movl %ebx, 32(%rsp)
movl 4(%rdi), %eax
movl %eax, 36(%rsp)
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 8(%r12), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %ebx
movl %ebx, 48(%rsp)
movl 4(%rbp), %eax
movl %eax, 52(%rsp)
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 8(%rbp), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%r13), %ebx
movl %ebx, 64(%rsp)
movl 4(%r13), %eax
movl %eax, 68(%rsp)
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 4(%r12), %eax
shrl $5, %eax
movl 0(%rbp), %edx
shrl $5, %edx
movl %edx, 20(%rsp)
movl %eax, 24(%rsp)
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%r13), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 72(%rsp), %rdx
movq 56(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatMulP6MatrixS0_S0_, .-_Z6MatMulP6MatrixS0_S0_
.globl _Z33__device_stub__Z13cudaRandomizePfPf
.type _Z33__device_stub__Z13cudaRandomizePfPf, @function
_Z33__device_stub__Z13cudaRandomizePfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cudaRandomizePf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z13cudaRandomizePfPf, .-_Z33__device_stub__Z13cudaRandomizePfPf
.globl _Z13cudaRandomizePf
.type _Z13cudaRandomizePf, @function
_Z13cudaRandomizePf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13cudaRandomizePfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13cudaRandomizePf, .-_Z13cudaRandomizePf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, (%r12)
movl $2048, 4(%r12)
movl $2048, 0(%r13)
movl $2048, 4(%r13)
movl $2048, (%rax)
movl $2048, 4(%rax)
movl $16777216, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, 8(%r12)
movl $16777216, %edi
call malloc@PLT
movq %rax, (%rsp)
movq %rax, 8(%r13)
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $64, 52(%rsp)
movl $64, 56(%rsp)
movl $32, 40(%rsp)
movl $32, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $32, 64(%rsp)
movl $32, 68(%rsp)
movl $64, 76(%rsp)
movl $64, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
movl $2, %ecx
movl $16777216, %edx
movq 32(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, 8(%rbp)
movl $0, %ebx
leaq .LC0(%rip), %r14
.L32:
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z6MatMulP6MatrixS0_S0_
addl $1, %ebx
cmpl $500, %ebx
jne .L32
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 24(%rsp), %rdi
call _Z33__device_stub__Z13cudaRandomizePfPf
jmp .L30
.L37:
movq 32(%rsp), %rdi
call _Z33__device_stub__Z13cudaRandomizePfPf
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13cudaRandomizePf"
.LC2:
.string "_Z12MatMulKernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaRandomizePf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernelPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
//Since this is matrix multiplication, A.width must be equal to B.height and the final matrix has height A.height and width B.width
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 32 //32 is the max since it means there are 32*32=1024 threads operating for each block
#define ARR_DIM (2048*2048)
#define WIDTH 2048
#define HEIGHT 2048
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(float *A, float *B, float *C);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(Matrix *A, Matrix *B, Matrix *C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A->width; d_A.height = A->height;
size_t size = A->width * A->height * sizeof(float);
cudaMalloc((void **)&d_A.elements, size);
cudaMemcpy(d_A.elements, A->elements, size,
cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B->width; d_B.height = B->height;
size = B->width * B->height * sizeof(float);
cudaMalloc((void **)&d_B.elements, size);
cudaMemcpy(d_B.elements, B->elements, size,
cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C->width; d_C.height = C->height;
size = C->width * C->height * sizeof(float);
cudaMalloc((void **)&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B->width / dimBlock.x, A->height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A.elements, d_B.elements, d_C.elements);
//This is causing a segmentation fault
// Read C from device memory
cudaMemcpy(C->elements, d_C.elements, size,
cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(float *A, float *B, float *C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < WIDTH; ++e)
Cvalue += A[row * WIDTH + e]
* B[e * WIDTH + col];
C[row * WIDTH + col] = Cvalue;
//printf("VAL=%f row=%d col=%d\n", Cvalue, row, col);
}
__global__ void cudaRandomize(float *arr){
float val;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
arr[row*WIDTH + col] = 1.654981;
}
float* generateRandArray(){
float* a = (float *)malloc(ARR_DIM*sizeof(float));
int i = 0;
for(i; i < ARR_DIM; i++){
a[i] = rand()%100 + 1;
}
return a;
}
int main(){
Matrix *A,*B,*C;
A = (Matrix *)malloc(sizeof(Matrix));
B = (Matrix *)malloc(sizeof(Matrix));
C = (Matrix *)malloc(sizeof(Matrix));
A->width = WIDTH;
A->height = HEIGHT;
B->width=WIDTH;
B->height = HEIGHT;
C->width = WIDTH;
C->height = HEIGHT;
A->elements = (float *)malloc(ARR_DIM*sizeof(float));
B->elements = (float *)malloc(ARR_DIM*sizeof(float));
float * d_A, *d_B;
size_t size = A->width * A->height * sizeof(float);
cudaMalloc((void**)&d_A, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(A->width / dimBlock.x, A->height / dimBlock.y);
cudaRandomize<<<dimGrid, dimBlock>>>(d_A);
cudaMemcpy(A->elements, d_A, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
size = B->width * B->height * sizeof(float);
cudaMalloc((void**)&d_B, size);
dim3 dimBlock2(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid2(B->width / dimBlock.x, B->height / dimBlock.y);
cudaRandomize<<<dimGrid2, dimBlock2>>>(d_B);
cudaMemcpy(B->elements, d_B, size, cudaMemcpyDeviceToHost);
cudaFree(d_B);
C->elements = (float *)malloc(ARR_DIM*sizeof(float));
for(int i = 0; i < 500; i++){
printf("i=%d\n",i);
MatMul(A,B,C);
}
free(A->elements);
free(B->elements);
free(C->elements);
return 0;
} | // Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
//Since this is matrix multiplication, A.width must be equal to B.height and the final matrix has height A.height and width B.width
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 32 //32 is the max since it means there are 32*32=1024 threads operating for each block
#define ARR_DIM (2048*2048)
#define WIDTH 2048
#define HEIGHT 2048
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(float *A, float *B, float *C);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(Matrix *A, Matrix *B, Matrix *C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A->width; d_A.height = A->height;
size_t size = A->width * A->height * sizeof(float);
hipMalloc((void **)&d_A.elements, size);
hipMemcpy(d_A.elements, A->elements, size,
hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B->width; d_B.height = B->height;
size = B->width * B->height * sizeof(float);
hipMalloc((void **)&d_B.elements, size);
hipMemcpy(d_B.elements, B->elements, size,
hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C->width; d_C.height = C->height;
size = C->width * C->height * sizeof(float);
hipMalloc((void **)&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B->width / dimBlock.x, A->height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A.elements, d_B.elements, d_C.elements);
//This is causing a segmentation fault
// Read C from device memory
hipMemcpy(C->elements, d_C.elements, size,
hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(float *A, float *B, float *C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < WIDTH; ++e)
Cvalue += A[row * WIDTH + e]
* B[e * WIDTH + col];
C[row * WIDTH + col] = Cvalue;
//printf("VAL=%f row=%d col=%d\n", Cvalue, row, col);
}
__global__ void cudaRandomize(float *arr){
float val;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
arr[row*WIDTH + col] = 1.654981;
}
float* generateRandArray(){
float* a = (float *)malloc(ARR_DIM*sizeof(float));
int i = 0;
for(i; i < ARR_DIM; i++){
a[i] = rand()%100 + 1;
}
return a;
}
int main(){
Matrix *A,*B,*C;
A = (Matrix *)malloc(sizeof(Matrix));
B = (Matrix *)malloc(sizeof(Matrix));
C = (Matrix *)malloc(sizeof(Matrix));
A->width = WIDTH;
A->height = HEIGHT;
B->width=WIDTH;
B->height = HEIGHT;
C->width = WIDTH;
C->height = HEIGHT;
A->elements = (float *)malloc(ARR_DIM*sizeof(float));
B->elements = (float *)malloc(ARR_DIM*sizeof(float));
float * d_A, *d_B;
size_t size = A->width * A->height * sizeof(float);
hipMalloc((void**)&d_A, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(A->width / dimBlock.x, A->height / dimBlock.y);
cudaRandomize<<<dimGrid, dimBlock>>>(d_A);
hipMemcpy(A->elements, d_A, size, hipMemcpyDeviceToHost);
hipFree(d_A);
size = B->width * B->height * sizeof(float);
hipMalloc((void**)&d_B, size);
dim3 dimBlock2(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid2(B->width / dimBlock.x, B->height / dimBlock.y);
cudaRandomize<<<dimGrid2, dimBlock2>>>(d_B);
hipMemcpy(B->elements, d_B, size, hipMemcpyDeviceToHost);
hipFree(d_B);
C->elements = (float *)malloc(ARR_DIM*sizeof(float));
for(int i = 0; i < 500; i++){
printf("i=%d\n",i);
MatMul(A,B,C);
}
free(A->elements);
free(B->elements);
free(C->elements);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
//Since this is matrix multiplication, A.width must be equal to B.height and the final matrix has height A.height and width B.width
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 32 //32 is the max since it means there are 32*32=1024 threads operating for each block
#define ARR_DIM (2048*2048)
#define WIDTH 2048
#define HEIGHT 2048
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(float *A, float *B, float *C);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(Matrix *A, Matrix *B, Matrix *C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A->width; d_A.height = A->height;
size_t size = A->width * A->height * sizeof(float);
hipMalloc((void **)&d_A.elements, size);
hipMemcpy(d_A.elements, A->elements, size,
hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B->width; d_B.height = B->height;
size = B->width * B->height * sizeof(float);
hipMalloc((void **)&d_B.elements, size);
hipMemcpy(d_B.elements, B->elements, size,
hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C->width; d_C.height = C->height;
size = C->width * C->height * sizeof(float);
hipMalloc((void **)&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B->width / dimBlock.x, A->height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A.elements, d_B.elements, d_C.elements);
//This is causing a segmentation fault
// Read C from device memory
hipMemcpy(C->elements, d_C.elements, size,
hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(float *A, float *B, float *C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < WIDTH; ++e)
Cvalue += A[row * WIDTH + e]
* B[e * WIDTH + col];
C[row * WIDTH + col] = Cvalue;
//printf("VAL=%f row=%d col=%d\n", Cvalue, row, col);
}
__global__ void cudaRandomize(float *arr){
float val;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
arr[row*WIDTH + col] = 1.654981;
}
float* generateRandArray(){
float* a = (float *)malloc(ARR_DIM*sizeof(float));
int i = 0;
for(i; i < ARR_DIM; i++){
a[i] = rand()%100 + 1;
}
return a;
}
int main(){
Matrix *A,*B,*C;
A = (Matrix *)malloc(sizeof(Matrix));
B = (Matrix *)malloc(sizeof(Matrix));
C = (Matrix *)malloc(sizeof(Matrix));
A->width = WIDTH;
A->height = HEIGHT;
B->width=WIDTH;
B->height = HEIGHT;
C->width = WIDTH;
C->height = HEIGHT;
A->elements = (float *)malloc(ARR_DIM*sizeof(float));
B->elements = (float *)malloc(ARR_DIM*sizeof(float));
float * d_A, *d_B;
size_t size = A->width * A->height * sizeof(float);
hipMalloc((void**)&d_A, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(A->width / dimBlock.x, A->height / dimBlock.y);
cudaRandomize<<<dimGrid, dimBlock>>>(d_A);
hipMemcpy(A->elements, d_A, size, hipMemcpyDeviceToHost);
hipFree(d_A);
size = B->width * B->height * sizeof(float);
hipMalloc((void**)&d_B, size);
dim3 dimBlock2(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid2(B->width / dimBlock.x, B->height / dimBlock.y);
cudaRandomize<<<dimGrid2, dimBlock2>>>(d_B);
hipMemcpy(B->elements, d_B, size, hipMemcpyDeviceToHost);
hipFree(d_B);
C->elements = (float *)malloc(ARR_DIM*sizeof(float));
for(int i = 0; i < 500; i++){
printf("i=%d\n",i);
MatMul(A,B,C);
}
free(A->elements);
free(B->elements);
free(C->elements);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernelPfS_S_
.globl _Z12MatMulKernelPfS_S_
.p2align 8
.type _Z12MatMulKernelPfS_S_,@function
_Z12MatMulKernelPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 11, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v3, v2
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_add_nc_u32_e32 v3, 0x800, v3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x2000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v4, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v4, v7
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v1, v1, 11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernelPfS_S_, .Lfunc_end0-_Z12MatMulKernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13cudaRandomizePf
.globl _Z13cudaRandomizePf
.p2align 8
.type _Z13cudaRandomizePf,@function
_Z13cudaRandomizePf:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0x3fd3d66b
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cudaRandomizePf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13cudaRandomizePf, .Lfunc_end1-_Z13cudaRandomizePf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cudaRandomizePf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13cudaRandomizePf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
//Since this is matrix multiplication, A.width must be equal to B.height and the final matrix has height A.height and width B.width
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 32 //32 is the max since it means there are 32*32=1024 threads operating for each block
#define ARR_DIM (2048*2048)
#define WIDTH 2048
#define HEIGHT 2048
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(float *A, float *B, float *C);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(Matrix *A, Matrix *B, Matrix *C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A->width; d_A.height = A->height;
size_t size = A->width * A->height * sizeof(float);
hipMalloc((void **)&d_A.elements, size);
hipMemcpy(d_A.elements, A->elements, size,
hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B->width; d_B.height = B->height;
size = B->width * B->height * sizeof(float);
hipMalloc((void **)&d_B.elements, size);
hipMemcpy(d_B.elements, B->elements, size,
hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C->width; d_C.height = C->height;
size = C->width * C->height * sizeof(float);
hipMalloc((void **)&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B->width / dimBlock.x, A->height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A.elements, d_B.elements, d_C.elements);
//This is causing a segmentation fault
// Read C from device memory
hipMemcpy(C->elements, d_C.elements, size,
hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(float *A, float *B, float *C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < WIDTH; ++e)
Cvalue += A[row * WIDTH + e]
* B[e * WIDTH + col];
C[row * WIDTH + col] = Cvalue;
//printf("VAL=%f row=%d col=%d\n", Cvalue, row, col);
}
__global__ void cudaRandomize(float *arr){
float val;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
arr[row*WIDTH + col] = 1.654981;
}
float* generateRandArray(){
float* a = (float *)malloc(ARR_DIM*sizeof(float));
int i = 0;
for(i; i < ARR_DIM; i++){
a[i] = rand()%100 + 1;
}
return a;
}
int main(){
Matrix *A,*B,*C;
A = (Matrix *)malloc(sizeof(Matrix));
B = (Matrix *)malloc(sizeof(Matrix));
C = (Matrix *)malloc(sizeof(Matrix));
A->width = WIDTH;
A->height = HEIGHT;
B->width=WIDTH;
B->height = HEIGHT;
C->width = WIDTH;
C->height = HEIGHT;
A->elements = (float *)malloc(ARR_DIM*sizeof(float));
B->elements = (float *)malloc(ARR_DIM*sizeof(float));
float * d_A, *d_B;
size_t size = A->width * A->height * sizeof(float);
hipMalloc((void**)&d_A, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(A->width / dimBlock.x, A->height / dimBlock.y);
cudaRandomize<<<dimGrid, dimBlock>>>(d_A);
hipMemcpy(A->elements, d_A, size, hipMemcpyDeviceToHost);
hipFree(d_A);
size = B->width * B->height * sizeof(float);
hipMalloc((void**)&d_B, size);
dim3 dimBlock2(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid2(B->width / dimBlock.x, B->height / dimBlock.y);
cudaRandomize<<<dimGrid2, dimBlock2>>>(d_B);
hipMemcpy(B->elements, d_B, size, hipMemcpyDeviceToHost);
hipFree(d_B);
C->elements = (float *)malloc(ARR_DIM*sizeof(float));
for(int i = 0; i < 500; i++){
printf("i=%d\n",i);
MatMul(A,B,C);
}
free(A->elements);
free(B->elements);
free(C->elements);
return 0;
} | .text
.file "cudaMatMul.hip"
.globl _Z6MatMulP6MatrixS0_S0_ # -- Begin function _Z6MatMulP6MatrixS0_S0_
.p2align 4, 0x90
.type _Z6MatMulP6MatrixS0_S0_,@function
_Z6MatMulP6MatrixS0_S0_: # @_Z6MatMulP6MatrixS0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r15
movl (%rdi), %eax
movl %eax, 40(%rsp)
movl 4(%rdi), %ecx
movl %ecx, 44(%rsp)
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 8(%r15), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl (%r12), %eax
movl %eax, 24(%rsp)
movl 4(%r12), %ecx
movl %ecx, 28(%rsp)
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 8(%r12), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl (%rbx), %eax
movl %eax, 8(%rsp)
movl 4(%rbx), %ecx
movl %ecx, 12(%rsp)
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl (%r12), %eax
shrl $5, %eax
movl 4(%r15), %edi
shrl $5, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 48(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernelPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rbx), %rdi
movq 16(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6MatMulP6MatrixS0_S0_, .Lfunc_end0-_Z6MatMulP6MatrixS0_S0_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernelPfS_S_ # -- Begin function _Z27__device_stub__MatMulKernelPfS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernelPfS_S_,@function
_Z27__device_stub__MatMulKernelPfS_S_: # @_Z27__device_stub__MatMulKernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12MatMulKernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernelPfS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernelPfS_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__cudaRandomizePf # -- Begin function _Z28__device_stub__cudaRandomizePf
.p2align 4, 0x90
.type _Z28__device_stub__cudaRandomizePf,@function
_Z28__device_stub__cudaRandomizePf: # @_Z28__device_stub__cudaRandomizePf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13cudaRandomizePf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z28__device_stub__cudaRandomizePf, .Lfunc_end2-_Z28__device_stub__cudaRandomizePf
.cfi_endproc
# -- End function
.globl _Z17generateRandArrayv # -- Begin function _Z17generateRandArrayv
.p2align 4, 0x90
.type _Z17generateRandArrayv,@function
_Z17generateRandArrayv: # @_Z17generateRandArrayv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB3_1
# %bb.2:
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17generateRandArrayv, .Lfunc_end3-_Z17generateRandArrayv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $274877907008, %r13 # imm = 0x4000000040
movabsq $137438953504, %rbp # imm = 0x2000000020
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
movl $16, %edi
callq malloc
movq %rax, %r15
movabsq $8796093024256, %rax # imm = 0x80000000800
movq %rax, (%rbx)
movq %rax, (%r14)
movq %rax, (%r15)
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r12
movq %rax, 8(%rbx)
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movq %rax, 8(%r14)
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z13cudaRandomizePf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 24(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r12, 96(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movabsq $274877907008, %rdi # imm = 0x4000000040
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z13cudaRandomizePf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 16(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq 88(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbp
movq %rax, 8(%r15)
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z6MatMulP6MatrixS0_S0_
incl %r12d
cmpl $500, %r12d # imm = 0x1F4
jne .LBB4_5
# %bb.6:
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cudaRandomizePf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernelPfS_S_,@object # @_Z12MatMulKernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernelPfS_S_
.p2align 3, 0x0
_Z12MatMulKernelPfS_S_:
.quad _Z27__device_stub__MatMulKernelPfS_S_
.size _Z12MatMulKernelPfS_S_, 8
.type _Z13cudaRandomizePf,@object # @_Z13cudaRandomizePf
.globl _Z13cudaRandomizePf
.p2align 3, 0x0
_Z13cudaRandomizePf:
.quad _Z28__device_stub__cudaRandomizePf
.size _Z13cudaRandomizePf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i=%d\n"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernelPfS_S_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13cudaRandomizePf"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernelPfS_S_
.addrsig_sym _Z28__device_stub__cudaRandomizePf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernelPfS_S_
.addrsig_sym _Z13cudaRandomizePf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13cudaRandomizePf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R5, 0x3fd3d66b ; /* 0x3fd3d66b00057802 */
/* 0x000fc60000000f00 */
/*00a0*/ LEA R3, R0, R3, 0xb ; /* 0x0000000300037211 */
/* 0x000fcc00078e58ff */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12MatMulKernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*00a0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00b0*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0200 */
/*00c0*/ SHF.L.U32 R9, R9, 0xb, RZ ; /* 0x0000000b09097819 */
/* 0x000fe200000006ff */
/*00d0*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fc600078e0203 */
/*00e0*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0100*/ IMAD.WIDE R14, R9, 0x4, R4 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0204 */
/*0110*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0120*/ IMAD.WIDE R2, R11, 0x4, R4 ; /* 0x000000040b027825 */
/* 0x000fe400078e0204 */
/*0130*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*0140*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe400078e0206 */
/*0150*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R27, [R6.64+0x2000] ; /* 0x00200004061b7981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R19, [R6.64+0x4000] ; /* 0x0040000406137981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R20, [R6.64+0x6000] ; /* 0x0060000406147981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R25, [R6.64+0x8000] ; /* 0x0080000406197981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100402127981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R21, [R6.64+0xa000] ; /* 0x00a0000406157981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0xc000] ; /* 0x00c00004060d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R15, [R6.64+0xe000] ; /* 0x00e00004060f7981 */
/* 0x001f68000c1e1900 */
/*0230*/ LDG.E R26, [R6.64+0x1e000] ; /* 0x01e00004061a7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x38] ; /* 0x00003804021d7981 */
/* 0x000f62000c1e1900 */
/*0250*/ FFMA R14, R17, R14, R12 ; /* 0x0000000e110e7223 */
/* 0x004fc6000000000c */
/*0260*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ FFMA R24, R27, R24, R14 ; /* 0x000000181b187223 */
/* 0x008fc6000000000e */
/*0280*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R17, [R6.64+0x10000] ; /* 0x0100000406117981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x010fc60000000018 */
/*02b0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R19, [R6.64+0x12000] ; /* 0x0120000406137981 */
/* 0x000f22000c1e1900 */
/*02d0*/ FFMA R24, R20, R23, R24 ; /* 0x0000001714187223 */
/* 0x020fc60000000018 */
/*02e0*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R20, [R6.64+0x14000] ; /* 0x0140000406147981 */
/* 0x000f62000c1e1900 */
/*0300*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x000fc60000000018 */
/*0310*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R22, [R6.64+0x16000] ; /* 0x0160000406167981 */
/* 0x000f62000c1e1900 */
/*0330*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x000fc60000000018 */
/*0340*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R18, [R6.64+0x18000] ; /* 0x0180000406127981 */
/* 0x000f62000c1e1900 */
/*0360*/ FFMA R28, R13, R10, R24 ; /* 0x0000000a0d1c7223 */
/* 0x000fc60000000018 */
/*0370*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R13, [R6.64+0x1a000] ; /* 0x01a00004060d7981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x1c000] ; /* 0x01c00004060a7981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003404021b7981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R8, 0x800, PT ; /* 0x000008000800780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x20000, URZ ; /* 0x0002000006067890 */
/* 0x000fe2000ff1e03f */
/*03e0*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*03f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0400*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0410*/ FFMA R12, R15, R12, R28 ; /* 0x0000000c0f0c7223 */
/* 0x004fc8000000001c */
/*0420*/ FFMA R12, R17, R14, R12 ; /* 0x0000000e110c7223 */
/* 0x008fc8000000000c */
/*0430*/ FFMA R12, R19, R16, R12 ; /* 0x00000010130c7223 */
/* 0x010fc8000000000c */
/*0440*/ FFMA R12, R20, R23, R12 ; /* 0x00000017140c7223 */
/* 0x020fc8000000000c */
/*0450*/ FFMA R12, R22, R25, R12 ; /* 0x00000019160c7223 */
/* 0x000fc8000000000c */
/*0460*/ FFMA R12, R18, R21, R12 ; /* 0x00000015120c7223 */
/* 0x000fc8000000000c */
/*0470*/ FFMA R12, R13, R24, R12 ; /* 0x000000180d0c7223 */
/* 0x000fc8000000000c */
/*0480*/ FFMA R12, R10, R27, R12 ; /* 0x0000001b0a0c7223 */
/* 0x000fc8000000000c */
/*0490*/ FFMA R12, R26, R29, R12 ; /* 0x0000001d1a0c7223 */
/* 0x000fe2000000000c */
/*04a0*/ @P0 BRA 0xf0 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04c0*/ IADD3 R2, R0, R9, RZ ; /* 0x0000000900027210 */
/* 0x000fd20007ffe0ff */
/*04d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04e0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernelPfS_S_
.globl _Z12MatMulKernelPfS_S_
.p2align 8
.type _Z12MatMulKernelPfS_S_,@function
_Z12MatMulKernelPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 11, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v3, v2
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_add_nc_u32_e32 v3, 0x800, v3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x2000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v4, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v4, v7
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v1, v1, 11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernelPfS_S_, .Lfunc_end0-_Z12MatMulKernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13cudaRandomizePf
.globl _Z13cudaRandomizePf
.p2align 8
.type _Z13cudaRandomizePf,@function
_Z13cudaRandomizePf:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0x3fd3d66b
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cudaRandomizePf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13cudaRandomizePf, .Lfunc_end1-_Z13cudaRandomizePf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cudaRandomizePf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13cudaRandomizePf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010ffa2_00000000-6_cudaMatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17generateRandArrayv
.type _Z17generateRandArrayv, @function
_Z17generateRandArrayv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 16777216(%rax), %rbp
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L4
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z17generateRandArrayv, .-_Z17generateRandArrayv
.globl _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
.type _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_, @function
_Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12MatMulKernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_, .-_Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
.globl _Z12MatMulKernelPfS_S_
.type _Z12MatMulKernelPfS_S_, @function
_Z12MatMulKernelPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12MatMulKernelPfS_S_, .-_Z12MatMulKernelPfS_S_
.globl _Z6MatMulP6MatrixS0_S0_
.type _Z6MatMulP6MatrixS0_S0_, @function
_Z6MatMulP6MatrixS0_S0_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl (%rdi), %ebx
movl %ebx, 32(%rsp)
movl 4(%rdi), %eax
movl %eax, 36(%rsp)
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 8(%r12), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %ebx
movl %ebx, 48(%rsp)
movl 4(%rbp), %eax
movl %eax, 52(%rsp)
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq 8(%rbp), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%r13), %ebx
movl %ebx, 64(%rsp)
movl 4(%r13), %eax
movl %eax, 68(%rsp)
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 4(%r12), %eax
shrl $5, %eax
movl 0(%rbp), %edx
shrl $5, %edx
movl %edx, 20(%rsp)
movl %eax, 24(%rsp)
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%r13), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 72(%rsp), %rdx
movq 56(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z12MatMulKernelPfS_S_PfS_S_
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatMulP6MatrixS0_S0_, .-_Z6MatMulP6MatrixS0_S0_
.globl _Z33__device_stub__Z13cudaRandomizePfPf
.type _Z33__device_stub__Z13cudaRandomizePfPf, @function
_Z33__device_stub__Z13cudaRandomizePfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13cudaRandomizePf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z13cudaRandomizePfPf, .-_Z33__device_stub__Z13cudaRandomizePfPf
.globl _Z13cudaRandomizePf
.type _Z13cudaRandomizePf, @function
_Z13cudaRandomizePf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13cudaRandomizePfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13cudaRandomizePf, .-_Z13cudaRandomizePf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, (%r12)
movl $2048, 4(%r12)
movl $2048, 0(%r13)
movl $2048, 4(%r13)
movl $2048, (%rax)
movl $2048, 4(%rax)
movl $16777216, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, 8(%r12)
movl $16777216, %edi
call malloc@PLT
movq %rax, (%rsp)
movq %rax, 8(%r13)
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $64, 52(%rsp)
movl $64, 56(%rsp)
movl $32, 40(%rsp)
movl $32, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $32, 64(%rsp)
movl $32, 68(%rsp)
movl $64, 76(%rsp)
movl $64, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
movl $2, %ecx
movl $16777216, %edx
movq 32(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, 8(%rbp)
movl $0, %ebx
leaq .LC0(%rip), %r14
.L32:
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z6MatMulP6MatrixS0_S0_
addl $1, %ebx
cmpl $500, %ebx
jne .L32
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 24(%rsp), %rdi
call _Z33__device_stub__Z13cudaRandomizePfPf
jmp .L30
.L37:
movq 32(%rsp), %rdi
call _Z33__device_stub__Z13cudaRandomizePfPf
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13cudaRandomizePf"
.LC2:
.string "_Z12MatMulKernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaRandomizePf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernelPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaMatMul.hip"
.globl _Z6MatMulP6MatrixS0_S0_ # -- Begin function _Z6MatMulP6MatrixS0_S0_
.p2align 4, 0x90
.type _Z6MatMulP6MatrixS0_S0_,@function
_Z6MatMulP6MatrixS0_S0_: # @_Z6MatMulP6MatrixS0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r15
movl (%rdi), %eax
movl %eax, 40(%rsp)
movl 4(%rdi), %ecx
movl %ecx, 44(%rsp)
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 8(%r15), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl (%r12), %eax
movl %eax, 24(%rsp)
movl 4(%r12), %ecx
movl %ecx, 28(%rsp)
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 8(%r12), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl (%rbx), %eax
movl %eax, 8(%rsp)
movl 4(%rbx), %ecx
movl %ecx, 12(%rsp)
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl (%r12), %eax
shrl $5, %eax
movl 4(%r15), %edi
shrl $5, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 48(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernelPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rbx), %rdi
movq 16(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6MatMulP6MatrixS0_S0_, .Lfunc_end0-_Z6MatMulP6MatrixS0_S0_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernelPfS_S_ # -- Begin function _Z27__device_stub__MatMulKernelPfS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernelPfS_S_,@function
_Z27__device_stub__MatMulKernelPfS_S_: # @_Z27__device_stub__MatMulKernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12MatMulKernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernelPfS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernelPfS_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__cudaRandomizePf # -- Begin function _Z28__device_stub__cudaRandomizePf
.p2align 4, 0x90
.type _Z28__device_stub__cudaRandomizePf,@function
_Z28__device_stub__cudaRandomizePf: # @_Z28__device_stub__cudaRandomizePf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13cudaRandomizePf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z28__device_stub__cudaRandomizePf, .Lfunc_end2-_Z28__device_stub__cudaRandomizePf
.cfi_endproc
# -- End function
.globl _Z17generateRandArrayv # -- Begin function _Z17generateRandArrayv
.p2align 4, 0x90
.type _Z17generateRandArrayv,@function
_Z17generateRandArrayv: # @_Z17generateRandArrayv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB3_1
# %bb.2:
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17generateRandArrayv, .Lfunc_end3-_Z17generateRandArrayv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $274877907008, %r13 # imm = 0x4000000040
movabsq $137438953504, %rbp # imm = 0x2000000020
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
movl $16, %edi
callq malloc
movq %rax, %r15
movabsq $8796093024256, %rax # imm = 0x80000000800
movq %rax, (%rbx)
movq %rax, (%r14)
movq %rax, (%r15)
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r12
movq %rax, 8(%rbx)
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movq %rax, 8(%r14)
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z13cudaRandomizePf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq 24(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r12, 96(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movabsq $274877907008, %rdi # imm = 0x4000000040
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z13cudaRandomizePf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 16(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq 88(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbp
movq %rax, 8(%r15)
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z6MatMulP6MatrixS0_S0_
incl %r12d
cmpl $500, %r12d # imm = 0x1F4
jne .LBB4_5
# %bb.6:
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cudaRandomizePf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernelPfS_S_,@object # @_Z12MatMulKernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernelPfS_S_
.p2align 3, 0x0
_Z12MatMulKernelPfS_S_:
.quad _Z27__device_stub__MatMulKernelPfS_S_
.size _Z12MatMulKernelPfS_S_, 8
.type _Z13cudaRandomizePf,@object # @_Z13cudaRandomizePf
.globl _Z13cudaRandomizePf
.p2align 3, 0x0
_Z13cudaRandomizePf:
.quad _Z28__device_stub__cudaRandomizePf
.size _Z13cudaRandomizePf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i=%d\n"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernelPfS_S_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13cudaRandomizePf"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernelPfS_S_
.addrsig_sym _Z28__device_stub__cudaRandomizePf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernelPfS_S_
.addrsig_sym _Z13cudaRandomizePf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//#define DEBUGPRINT 0
__global__ void compute_entropy_gpu_kernel(double *tlag, double *pr, double *vtrans,int ntot, int irho, double ntol , double rgam, double gmaref,int ltot ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
double rho= fmax(vtrans[ltot*(irho-1)+id],ntol);
tlag[id]=rgam*rho*log(pr[id]/(pow(rho,gmaref) ));
}
}
extern "C" void compute_entropy_gpu_wrapper_(int *glbblockSize1,double *d_tlag, double *d_pr, double *d_vtrans,int *ntot, int *irho, double *ntol , double *rgam, double *gmaref, int *ltot){
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start compute_entropy_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values ntot = %d, irho = %d, ntol = %lf, rgam = %lf, gmaref = %lf \n",ntot[0],irho[0],ntol[0],rgam[0],gmaref[0] );
#endif
//}
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot[0]/blockSize);
compute_entropy_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_pr,d_vtrans,ntot[0],irho[0],ntol[0],rgam[0],gmaref[0],ltot[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
//if (code2 != cudaSuccess){
printf("CUDA: End compute_engropy_wrapper cuda status: %s\n",cudaGetErrorString(code1));
#endif
//}
}
__global__ void entropy_residual_flux_gpu_kernel(double *tlag, double *res2,int ntot, double rdt, int stage, int lorder, int ltot, double *totalh, int lxyzdlelt, double *vx, double *vy, double *vz, int if3d ){//lxyzd -> lxyzdlelt by Kk 03/16
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
if(stage==1){
res2[id]=tlag[id]-tlag[ltot*lorder+id] ;
}
else{
res2[id]=tlag[id]-tlag[ltot+id] ;
}
res2[id] = res2[id]*rdt;
// evaluate_entropy_flux(e)
totalh[id]= vx[id]*tlag[id];
//totalh[lxyzd+id] = vy[id]*tlag[id];
//if(if3d){totalh[lxyzd*2+id] = vz[id]*tlag[id];}
totalh[lxyzdlelt+id] = vy[id]*tlag[id]; //lxyzd -> lxyzdlelt by Kk 03/16
if(if3d){totalh[lxyzdlelt*2+id] = vz[id]*tlag[id];}
//flux_div_mini(e)
}
}
__global__ void flux_div_mini_gpu_kernel(double *tlag, double *res2,int ntot, double rdt, int stage, int lorder, int ltot, double *totalh, int lxyzd, double *ur1,double *us1, double *ut1, double *ur2, double *us2, double *ut2, double *ur3, double *us3, double *ut3,double *ud, int ldd, double *jacmi, double *rxm1, double *sxm1, double *txm1, double *rym1, double *sym1, double *tym1,double *rzm1, double *szm1, double *tzm1, int if3d ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
int i= id % ldd;
if(id<ntot){
//something is wrong because ur us ut has only [i]. I think it should be [id] because I added *lelt later. Check again. adeesha
if(if3d){
ud[id] = jacmi[id] *( rxm1[id]*ur1[i]+ sxm1[id]*us1[i]+txm1[id]*ut1[i]);
ud[id] = ud[id]+ jacmi[id] *( rym1[id]*ur2[i]+ sym1[id]*us2[i]+txm1[id]*ut2[i]);
ud[id] = ud[id] + jacmi[id] *( rzm1[id]*ur3[i]+ szm1[id]*us3[i]+tzm1[id]*ut3[i]);
}
else{
ud[id] = jacmi[id] *( rxm1[id]*ur1[i]+ sxm1[id]*us1[i]);
ud[id] = ud[id]+ jacmi[id] *( rym1[id]*ur2[i]+ sym1[id]*us2[i]);
}
//add 2
res2[id] = res2[id] + ud[id];
}
}
//mxm multiplication
__global__ void mxm1(double *a, int n1, double *b, int n2, double *c, int n3, int nelt, int aSize, int bSize, int cSize, int extraEq){
//calculate c(n1,n3) = a(n1,n2) X b(n2,n3) in c
//in fortran the original calculation was
// c(n3,n1) = b(n3,n2) X a(n2,n1)
// a,b,cSize are single element size
//extraEq, in case of a matrix has equation as an index
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<nelt*n1*n3){
int e = id/(n1*n3);
int rc = id%(n1*n3);
int i = rc/n3;
int j = rc%n3;
int cid = e*cSize + rc;
int aid = e*aSize + extraEq + i*n2;
int bid = e*bSize + j;
c[cid] = 0;
for(int k = 0; k<n2; k++)
c[cid]+=a[aid+k]*b[bid+k*n3];
}
}
extern "C" void entropy_residual_gpu_wrapper_(int *glbblockSize1,double *d_tlag, double *d_res2,int *ntot, double *rdt, int *stage, int *lorder,int *ltot, int *lxd, int *lyd, int *lzd, double *d_vx, double *d_vy, double *d_vz, int *lx1, int *ly1, int *lz1, double *d_jacmi, double *d_rxm1, double *d_sxm1, double *d_txm1, double *d_rym1, double *d_sym1, double *d_tym1,double *d_rzm1, double *d_szm1, double *d_tzm1,int *if3d,int *nelt, double *d_dxm1, double *d_dxtm1, int *lelt){//added parameter lelt by Kk 03/16
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start entropy_residual_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start entropy_residual_gpu_wrapper values rdt = %lf, stage = %d, lorder= %d,ltot = %d,lxd = %d, lyd = %d, lzd = %d, lx1 = %d,ly1 = %d,lz1 = %d,if3d = %d,nelt = %d \n",rdt[0], stage[0],lorder[0],ltot[0],lxd[0], lyd[0],lzd[0],lx1[0],ly1[0],lz1[0],if3d[0],nelt[0]);
#endif
//}
double *d_totalh_temp; // Anyway d_totalh seems not needed. check with Dr.Tania. adeesha
double *d_ur1;
double *d_us1;
double *d_ut1;
double *d_ur2;
double *d_us2;
double *d_ut2;
double *d_ur3;
double *d_us3;
double *d_ut3;
double *d_ud;
int lxyzd = lxd[0]*lyd[0]*lzd[0];
int lxyzdlelt = lxd[0]*lyd[0]*lzd[0]*lelt[0];
int ldd = lx1[0]*ly1[0]*lz1[0];
//cudaMalloc((void**)&d_totalh_temp,3*lxyzd *nelt[0]* sizeof(double));
cudaMalloc((void**)&d_totalh_temp,3*lxyzd *lelt[0]* sizeof(double));//note here changed to lelt by Kk, check if correct
cudaMalloc((void**)&d_ur1,ldd * nelt[0]*sizeof(double)); //nelt[0] added later. need to double check.
cudaMalloc((void**)&d_us1,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_ut1,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_ur2,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_us2,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_ut2,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_ur3,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_us3,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_ut3,ldd * nelt[0]*sizeof(double));
cudaMalloc((void**)&d_ud,nelt[0]*ldd * sizeof(double));
cudaMemset(d_totalh_temp, 0.0, 3*lxyzd*nelt[0]*sizeof(double));
cudaMemset(d_ur1, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_us1, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_ut1, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_ur2, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_us2, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_ut2, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_ur3, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_us3, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_ut3, 0.0, ldd*nelt[0]*sizeof(double));
cudaMemset(d_ud, 0.0, ldd*nelt[0]*sizeof(double));
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot[0]/blockSize);
//lxyzd -> lxyzdlelt by Kk 03/16
//entropy_residual_flux_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_res2,ntot[0],rdt[0],stage[0],lorder[0], ltot[0], d_totalh_temp, lxyzd, d_vx, d_vy, d_vz, if3d[0]);
entropy_residual_flux_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_res2,ntot[0],rdt[0],stage[0],lorder[0], ltot[0], d_totalh_temp, lxyzdlelt, d_vx, d_vy, d_vz, if3d[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after kernel 1cuda status: %s\n",cudaGetErrorString(code1));
#endif
int mdm1 = lx1[0]-1;
// Following is the local_grad3 function
int nx_2 = lx1[0]*lx1[0];
int nx_3 = nx_2*lx1[0];
int nxd_2 = nx_2;
int nxd_3 = nx_3;
//ur(nx,nx*nx) = D(nx,nx) * u(nx,nx*nx) fortran
//ur(nx*nx,nx) = u(nx*nx,nx) * D(nx,nx) C
if(if3d[0]){
blockSize=glbblockSize1[0], gridSize;
// for ur1 us1 and ut1
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp,nx_2, d_dxm1, lx1[0], d_ur1, lx1[0], nelt[0], nx_3, 0, nxd_3, 0);//ur,us, ut should be indexed by nxd
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after 1st mxm 1cuda status: %s\n",cudaGetErrorString(code1));
#endif
for(int k = 0; k<lx1[0]; k++){
//usk(nx,nx) = uk(nx,nx) * dt(nx,nx) fortran
//usk(nx,nx) = dt(nx,nx) * uk(nx,nx) C
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+k*nx_2, lx1[0],d_us1+k*nx_2, lx1[0], nelt[0], 0, nx_3, nxd_3, 0);
}
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after for loop mxm 1cuda status: %s\n",cudaGetErrorString(code1));
#endif
//ut(nx_2,nx) = u(nx_2,nx) * dt(nx,nx) fortran
//ut(nx,nx_2) = dt(nx,nx) * u(nx,nx_2) C
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp, lx1[0], d_ut1, nx_2, nelt[0], 0, nx_3, nxd_3, 0);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after 3rd mxm 1cuda status: %s\n",cudaGetErrorString(code1));
#endif
// for ur2 us2 and ut2
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp+lxyzd*nelt[0],nx_2, d_dxm1, lx1[0], d_ur2, lx1[0], nelt[0], nx_3, 0, nxd_3, 0);//ur,us, ut should be indexed by nxd
for(int k = 0; k<lx1[0]; k++){
//usk(nx,nx) = uk(nx,nx) * dt(nx,nx) fortran
//usk(nx,nx) = dt(nx,nx) * uk(nx,nx) C
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+lxyzd*nelt[0]+k*nx_2, lx1[0],d_us2+k*nx_2, lx1[0], nelt[0], 0, nx_3, nxd_3, 0);
}
//ut(nx_2,nx) = u(nx_2,nx) * dt(nx,nx) fortran
//ut(nx,nx_2) = dt(nx,nx) * u(nx,nx_2) C
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+lxyzd*nelt[0], lx1[0], d_ut2, nx_2, nelt[0], 0, nx_3, nxd_3, 0);
// for ur3 us3 and ut3
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp+2*lxyzd*nelt[0],nx_2, d_dxm1, lx1[0], d_ur3, lx1[0], nelt[0], nx_3, 0, nxd_3, 0);//ur,us, ut should be indexed by nxd
for(int k = 0; k<lx1[0]; k++){
//usk(nx,nx) = uk(nx,nx) * dt(nx,nx) fortran
//usk(nx,nx) = dt(nx,nx) * uk(nx,nx) C
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+2*lxyzd*nelt[0]+k*nx_2, lx1[0],d_us3+k*nx_2, lx1[0], nelt[0], 0, nx_3, nxd_3, 0);
}
//ut(nx_2,nx) = u(nx_2,nx) * dt(nx,nx) fortran
//ut(nx,nx_2) = dt(nx,nx) * u(nx,nx_2) C
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+2*lxyzd*nelt[0], lx1[0], d_ut3, nx_2, nelt[0], 0, nx_3, nxd_3, 0);
}else{
// for ur1 us1 and ut1
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp,lx1[0], d_dxm1, lx1[0], d_ur1, lx1[0], nelt[0], nx_2, 0, nxd_2, 0);//ur,us, ut should be indexed by nxd
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp, lx1[0],d_us1, lx1[0], nelt[0], 0, nx_2, nxd_2, 0);
// for ur2 us2 and ut1
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp+lxyzd*nelt[0],lx1[0], d_dxm1, lx1[0], d_ur2, lx1[0], nelt[0], nx_2, 0, nxd_2, 0);//ur,us, ut should be indexed by nxd
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+lxyzd*nelt[0], lx1[0],d_us2, lx1[0], nelt[0], 0, nx_2, nxd_2, 0);
}
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper before flux_div_mini_gpu_kernel cuda status: %s\n",cudaGetErrorString(code1));
#endif
flux_div_mini_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_res2,ntot[0],rdt[0],stage[0],lorder[0], ltot[0], d_totalh_temp, lxyzd, d_ur1,d_us1, d_ut1, d_ur2,d_us2, d_ut2, d_ur3, d_us3, d_ut3,d_ud, ldd, d_jacmi, d_rxm1, d_sxm1, d_txm1, d_rym1, d_sym1, d_tym1, d_rzm1, d_szm1, d_tzm1,if3d[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after flux_div_mini_gpu_kernel cuda status: %s\n",cudaGetErrorString(code1));
#endif
cudaFree(d_totalh_temp);
cudaFree(d_ur1);
cudaFree(d_ur2);
cudaFree(d_ur3);
cudaFree(d_us1);
cudaFree(d_us2);
cudaFree(d_us3);
cudaFree(d_ut1);
cudaFree(d_ut2);
cudaFree(d_ut3);
cudaFree(d_ud);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End entropy residual_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));
#endif
//}
}
__global__ void wavevisc_gpu_kernel(double *t,double *csound, double *vx, double *vy, double *vz, int ntot, double *wavespeed,int lxyz, int lx1, int ly1, int lz1, double *vtranstmp, double c_max,int ltot, double *meshh ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
wavespeed[id]= csound [id] +sqrt(vx[id]*vx[id]+vy[id]*vy[id]+vz[id]*vz[id] ) ;
// find max of wavespeed using reduction
__syncthreads();
unsigned int i = lxyz/2;
int len = lxyz;
int e= id/(lxyz);
int startofcurrentelement = e*lxyz;
while(i != 0){
if(id-startofcurrentelement <= i){
wavespeed[id] = fmax(fabs(wavespeed[id]),fabs(wavespeed[startofcurrentelement + (id+i)%len]));
}
__syncthreads();
//added by Kk 02/05/2019 since the latter one may not correct when len is odd
len = (len+1)/2;
i = len/2;
/* commented by Kk 02/05/2019
len = i;
i /= 2;*/
}
double maxeig = wavespeed[e*lxyz];
/*if(id%lxyz == 0){
printf("maxeig in wavevisc %d %.15lf %.15lf \n", id/lxyz, maxeig, c_max);
}*/
// find max of vtrans using reduction. But never used? check with Dr.Tania
//i = lxyz/2;
//int e= id/(lx1*ly1*lz1);
//int startofcurrentelement = id-e;
//while(i != 0){
// if(id-startofcurrentelement < i){
// vtranstmp[id] = fmaxf(vtranstmp[id], vtranstmp[id + i]);
// }
// __syncthreads();
// i /= 2;
//}
//int rhomax = vtranstmp[id-e];
t[2*ltot+id] = c_max*maxeig*meshh[e];
// if(id<10){
// printf("$$$ print from cuda maxeig = %lf t[2*ltot+id]= %lf meshh[e]=%lf \n",maxeig,t[2*ltot+id],meshh[e]);
// }
}
}
extern "C" void wavevisc_gpu_wrapper_(int *glbblockSize1,double *d_t, double *d_csound,double *d_vx, double *d_vy, double *d_vz, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *d_vtrans, double *c_max, double *d_meshh, int *irho ){
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start wavevisc_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d, lz1= %d,c_max= %lf,irho= %d \n",nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],c_max[0],irho[0]);
#endif
// }
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
double *d_wavespeed;
cudaMalloc((void**)&d_wavespeed,nelt[0]*lxyz* sizeof(double));
// cudaMemset(d_totalh_temp, 0.0, 3*lxyzd*nelt*sizeof(double));
double *d_vtranstemp;
cudaMalloc((void**)&d_vtranstemp,nelt[0]*lxyz* sizeof(double));
cudaMemcpy(d_vtranstemp, &d_vtrans[(irho[0]-1)*lelt[0]*lxyz], nelt[0]*lxyz* sizeof(double), cudaMemcpyDeviceToDevice);
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
wavevisc_gpu_kernel<<<gridSize, blockSize>>>(d_t,d_csound, d_vx, d_vy, d_vz,ntot,d_wavespeed, lxyz,lx1[0],ly1[0],lz1[0],d_vtranstemp,c_max[0], ltot, d_meshh);
cudaFree(d_wavespeed);
cudaFree(d_vtranstemp);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End Wavevisc_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));
#endif
// }
}
__global__ void max_to_trilin_gpu_kernel(double *t,int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy, double *xm1, double *ym1, double *zm1, int if3d ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lxyz);
double p000 = t[2*ltot+e*lxyz];
double p100 = t[2*ltot+e*lxyz+(lx1-1)];
double p010 = t[2*ltot+e*lxyz+(ly1-1)*lx1];
double p110 = t[2*ltot+e*lxyz+(ly1-1)*lx1+(lx1-1)];
double p001 = t[2*ltot+e*lxyz+(lz1-1)*lxy];
double p101 = t[2*ltot+e*lxyz+(lz1-1)*lxy+(lx1-1)];
double p011 = t[2*ltot+e*lxyz+(lz1-1)*lxy+(ly1-1)*lx1];
double p111 = t[2*ltot+e*lxyz+(lz1-1)*lxy+(ly1-1)*lx1+(lx1-1)];
double c1=p100-p000;
double c2=p010-p000;
double c3=p001-p000;
double c4=p110-p010-p100+p000;
double c5=p011-p001-p010+p000;
double c6=p101-p001-p100+p000;
double c7=p111-p011-p101-p110+p100+p001+p010-p000;
double rdx=1.0/(xm1[e*lxyz+(lx1-1)]-xm1[e*lxyz]); // cubes only!!!
double rdy=1.0/(ym1[e*lxyz+(ly1-1)*lx1]-ym1[e*lxyz]);
double rdz=0.0;
if(if3d){ rdz=1.0/(zm1[e*lxyz+(lz1-1)*lxy]-zm1[e*lxyz]); }
int firstlx = id%lxyz;
double deltax=rdx*(xm1[id]-xm1[e*lxyz]) ;//! cubes only!!!
double deltay=rdy*(ym1[id]-ym1[e*lxyz]);
double deltaz=0.0;
if (if3d){ deltaz=rdz*(zm1[id]-zm1[e*lxyz]);}
t[2*ltot+id] =p000+c1*deltax+c2*deltay+c3*deltaz+ c4*deltax*deltay+c5*deltay*deltaz+ c6*deltaz*deltax+c7*deltay*deltaz*deltax;
/*if(id ==ntot-1){
printf("debug max_to_trilin: %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %d\n", p000, c1, c2, c3, c4, c5, c6, c7, rdx, rdy, deltax, deltay, deltaz, t[2*ltot+id], if3d);
}*/
}
}
extern "C" void max_to_trilin_gpu_wrapper_(int *glbblockSize1,double *d_t, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *d_xm1, double *d_ym1, double *d_zm1, int *if3d ){
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start max_to_trilin_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,if3d=%d \n",nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],if3d[0]);
#endif
//}
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
max_to_trilin_gpu_kernel<<<gridSize, blockSize>>>(d_t,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0], d_xm1, d_ym1, d_zm1, if3d[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
//if (code2 != cudaSuccess){
printf("CUDA: End max_to_trilin_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));
#endif
//}
}
__global__ void resvisc_gpu_kernel1(double *res2,int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy,double *meshh ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lx1*ly1*lz1);
res2[id] = res2[id]*meshh[e]*meshh[e];
}
}
extern "C" void resvisc_gpu_wrapper1_(int *glbblockSize1,double *d_res2, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *d_meshh){
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
//if (code1 != cudaSuccess){
printf("CUDA: Start resvisc_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d,lz1 = %d,\n", nelt[0],lelt[0],lx1[0],ly1[0],lz1[0]);
#endif
//}
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
resvisc_gpu_kernel1<<<gridSize, blockSize>>>(d_res2,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0], d_meshh);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
//if (code2 != cudaSuccess){
printf("CUDA: End resvisc_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));
#endif
//}
}
__global__ void resvisc_gpu_kernel2(double *res2,int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy,double c_sub_e, double maxdiff ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lx1*ly1*lz1);
res2[id] = fabs(res2[id]);
res2[id] = res2[id]*c_sub_e; // cmult
if(maxdiff !=0){
double consta = 1/maxdiff;
res2[id] = res2[id]*consta;
}
}
}
extern "C" void resvisc_gpu_wrapper2_(int *glbblockSize1,double *d_res2, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *c_sub_e, double *maxdiff){
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start resvisc_gpu_wrapper2 cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,c_sub_e=%lf,maxdiff= %.20lf, \n",nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],c_sub_e[0],maxdiff[0]);
#endif
// }
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
int blockSize =glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
resvisc_gpu_kernel2<<<gridSize, blockSize>>>(d_res2,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0], c_sub_e[0], maxdiff[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End resvisc_gpu_wrapper2 cuda status: %s\n",cudaGetErrorString(code2));
#endif
// }
}
__global__ void evnsmooth_gpu_kernel(double *res2, double *t, int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy, int kstart, int kend, int jstart, int jend, int istart, int iend,int ldim , double rldim, double *rtmp, int if3d ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lx1*ly1*lz1);
if(t[2*ltot+id] <= res2[id]){
res2[id] = t[2*ltot+id];// wavevisc and resvisc are really res2 and t. but the dimensions are different. As I understand this will start from 0 and works well. Need to check with Dr.Tania . adeesha
}
//global syncthread is needed here. check with Dr.Tania. adeesha.
rtmp[id] = res2[id];
int ix= id % lx1;
int iy= (id/lx1)%ly1;
int iz = (id / (lx1*ly1))%lz1;
if((kstart<=iz && iz<=kend)&& (jstart<= iy && iy<= jend) && (istart<=ix && ix<=iend)){
int izm,izp;
if(if3d){
int km1=iz-1;
int kp1=iz+1;
int izm=km1;
if (km1 < 0){ izm=kp1;} // Guermond symmetry
izp=kp1;
if (kp1 > (lz1-1)){ izp=km1;} // Guermond symmetry
}
else{
izm=iz;
izp=iz;
}
int jm1=iy-1;
int jp1=iy+1;
int iym=jm1;
if (jm1 < 0){ iym=jp1;}// Guermond symmetry
int iyp=jp1;
if (jp1 > (ly1-1)){ iyp=jm1;} // Guermond symmetry
int im1=ix-1;
int ip1=ix+1;
int ixm=im1;
if (im1 < 0){ ixm=ip1;} // Guermond symmetry
int ixp=ip1;
if (ip1 > (lx1-1)) {ixp=im1 ;} // Guermond symmetry
double x0 = res2[e*lxyz+iz*lxy+iy*lx1+ix];
double x1 = res2[e*lxyz+iz*lxy+iy*lx1+ixm];
double x2 = res2[e*lxyz+iz*lxy+iy*lx1+ixp];
double x3 = res2[e*lxyz+iz*lxy+iym*lx1+ix];
double x4 = res2[e*lxyz+iz*lxy+iyp*lx1+ix];
double x5,x6;
if (if3d){
x5 = res2[e*lxyz+izm*lxy+iy*lx1+ixp];
x6 = res2[e*lxyz+izp*lxy+iy*lx1+ixp];
}
else {
x5=0.0;
x6=0.0;
}
rtmp[id]=0.25*(2.0*ldim*x0+x1+x2+x3+x4+x5+x6)*rldim;// check whether this is same as rtmp [id]. adeesha
}
res2[id]=rtmp[id];
}
}
extern "C" void evnsmooth_gpu_wrapper_(int *glbblockSize1,double *d_res2, double *d_t, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1,int *kstart, int *kend, int *jstart, int *jend, int *istart, int *iend, int *ldim , double *rldim, int *if3d ){
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start evnsmooth_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt =%d ,lelt=%d,lx1=%d,ly1=%d,lz1=%d,kstart=%d,kend=%d,jstart=%d,jend=%d,istart=%d,iend=%d,ldim=%d ,rldim=%lf,if3d=%d,\n", nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],kstart[0],kend[0],jstart[0],jend[0],istart[0],iend[0],ldim[0] ,rldim[0],if3d[0]);
#endif
// }
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
double *d_rtmp;
cudaMalloc((void**)&d_rtmp,nelt[0]*lxyz* sizeof(double));
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
evnsmooth_gpu_kernel<<<gridSize, blockSize>>>(d_res2,d_t,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0],(kstart[0]-1),(kend[0]-1),(jstart[0]-1),(jend[0]-1),(istart[0]-1),(iend[0]-1),ldim[0] ,rldim[0], d_rtmp, if3d[0] );
cudaFree(d_rtmp);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End evnsmooth_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));
#endif
// }
} | #include <hip/hip_runtime.h>
#include <stdio.h>
//#define DEBUGPRINT 0
__global__ void compute_entropy_gpu_kernel(double *tlag, double *pr, double *vtrans,int ntot, int irho, double ntol , double rgam, double gmaref,int ltot ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
double rho= fmax(vtrans[ltot*(irho-1)+id],ntol);
tlag[id]=rgam*rho*log(pr[id]/(pow(rho,gmaref) ));
}
}
extern "C" void compute_entropy_gpu_wrapper_(int *glbblockSize1,double *d_tlag, double *d_pr, double *d_vtrans,int *ntot, int *irho, double *ntol , double *rgam, double *gmaref, int *ltot){
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start compute_entropy_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values ntot = %d, irho = %d, ntol = %lf, rgam = %lf, gmaref = %lf \n",ntot[0],irho[0],ntol[0],rgam[0],gmaref[0] );
#endif
//}
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot[0]/blockSize);
compute_entropy_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_pr,d_vtrans,ntot[0],irho[0],ntol[0],rgam[0],gmaref[0],ltot[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
//if (code2 != cudaSuccess){
printf("CUDA: End compute_engropy_wrapper cuda status: %s\n",hipGetErrorString(code1));
#endif
//}
}
__global__ void entropy_residual_flux_gpu_kernel(double *tlag, double *res2,int ntot, double rdt, int stage, int lorder, int ltot, double *totalh, int lxyzdlelt, double *vx, double *vy, double *vz, int if3d ){//lxyzd -> lxyzdlelt by Kk 03/16
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
if(stage==1){
res2[id]=tlag[id]-tlag[ltot*lorder+id] ;
}
else{
res2[id]=tlag[id]-tlag[ltot+id] ;
}
res2[id] = res2[id]*rdt;
// evaluate_entropy_flux(e)
totalh[id]= vx[id]*tlag[id];
//totalh[lxyzd+id] = vy[id]*tlag[id];
//if(if3d){totalh[lxyzd*2+id] = vz[id]*tlag[id];}
totalh[lxyzdlelt+id] = vy[id]*tlag[id]; //lxyzd -> lxyzdlelt by Kk 03/16
if(if3d){totalh[lxyzdlelt*2+id] = vz[id]*tlag[id];}
//flux_div_mini(e)
}
}
__global__ void flux_div_mini_gpu_kernel(double *tlag, double *res2,int ntot, double rdt, int stage, int lorder, int ltot, double *totalh, int lxyzd, double *ur1,double *us1, double *ut1, double *ur2, double *us2, double *ut2, double *ur3, double *us3, double *ut3,double *ud, int ldd, double *jacmi, double *rxm1, double *sxm1, double *txm1, double *rym1, double *sym1, double *tym1,double *rzm1, double *szm1, double *tzm1, int if3d ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
int i= id % ldd;
if(id<ntot){
//something is wrong because ur us ut has only [i]. I think it should be [id] because I added *lelt later. Check again. adeesha
if(if3d){
ud[id] = jacmi[id] *( rxm1[id]*ur1[i]+ sxm1[id]*us1[i]+txm1[id]*ut1[i]);
ud[id] = ud[id]+ jacmi[id] *( rym1[id]*ur2[i]+ sym1[id]*us2[i]+txm1[id]*ut2[i]);
ud[id] = ud[id] + jacmi[id] *( rzm1[id]*ur3[i]+ szm1[id]*us3[i]+tzm1[id]*ut3[i]);
}
else{
ud[id] = jacmi[id] *( rxm1[id]*ur1[i]+ sxm1[id]*us1[i]);
ud[id] = ud[id]+ jacmi[id] *( rym1[id]*ur2[i]+ sym1[id]*us2[i]);
}
//add 2
res2[id] = res2[id] + ud[id];
}
}
//mxm multiplication
__global__ void mxm1(double *a, int n1, double *b, int n2, double *c, int n3, int nelt, int aSize, int bSize, int cSize, int extraEq){
//calculate c(n1,n3) = a(n1,n2) X b(n2,n3) in c
//in fortran the original calculation was
// c(n3,n1) = b(n3,n2) X a(n2,n1)
// a,b,cSize are single element size
//extraEq, in case of a matrix has equation as an index
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<nelt*n1*n3){
int e = id/(n1*n3);
int rc = id%(n1*n3);
int i = rc/n3;
int j = rc%n3;
int cid = e*cSize + rc;
int aid = e*aSize + extraEq + i*n2;
int bid = e*bSize + j;
c[cid] = 0;
for(int k = 0; k<n2; k++)
c[cid]+=a[aid+k]*b[bid+k*n3];
}
}
extern "C" void entropy_residual_gpu_wrapper_(int *glbblockSize1,double *d_tlag, double *d_res2,int *ntot, double *rdt, int *stage, int *lorder,int *ltot, int *lxd, int *lyd, int *lzd, double *d_vx, double *d_vy, double *d_vz, int *lx1, int *ly1, int *lz1, double *d_jacmi, double *d_rxm1, double *d_sxm1, double *d_txm1, double *d_rym1, double *d_sym1, double *d_tym1,double *d_rzm1, double *d_szm1, double *d_tzm1,int *if3d,int *nelt, double *d_dxm1, double *d_dxtm1, int *lelt){//added parameter lelt by Kk 03/16
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start entropy_residual_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start entropy_residual_gpu_wrapper values rdt = %lf, stage = %d, lorder= %d,ltot = %d,lxd = %d, lyd = %d, lzd = %d, lx1 = %d,ly1 = %d,lz1 = %d,if3d = %d,nelt = %d \n",rdt[0], stage[0],lorder[0],ltot[0],lxd[0], lyd[0],lzd[0],lx1[0],ly1[0],lz1[0],if3d[0],nelt[0]);
#endif
//}
double *d_totalh_temp; // Anyway d_totalh seems not needed. check with Dr.Tania. adeesha
double *d_ur1;
double *d_us1;
double *d_ut1;
double *d_ur2;
double *d_us2;
double *d_ut2;
double *d_ur3;
double *d_us3;
double *d_ut3;
double *d_ud;
int lxyzd = lxd[0]*lyd[0]*lzd[0];
int lxyzdlelt = lxd[0]*lyd[0]*lzd[0]*lelt[0];
int ldd = lx1[0]*ly1[0]*lz1[0];
//cudaMalloc((void**)&d_totalh_temp,3*lxyzd *nelt[0]* sizeof(double));
hipMalloc((void**)&d_totalh_temp,3*lxyzd *lelt[0]* sizeof(double));//note here changed to lelt by Kk, check if correct
hipMalloc((void**)&d_ur1,ldd * nelt[0]*sizeof(double)); //nelt[0] added later. need to double check.
hipMalloc((void**)&d_us1,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_ut1,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_ur2,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_us2,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_ut2,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_ur3,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_us3,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_ut3,ldd * nelt[0]*sizeof(double));
hipMalloc((void**)&d_ud,nelt[0]*ldd * sizeof(double));
hipMemset(d_totalh_temp, 0.0, 3*lxyzd*nelt[0]*sizeof(double));
hipMemset(d_ur1, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_us1, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_ut1, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_ur2, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_us2, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_ut2, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_ur3, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_us3, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_ut3, 0.0, ldd*nelt[0]*sizeof(double));
hipMemset(d_ud, 0.0, ldd*nelt[0]*sizeof(double));
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot[0]/blockSize);
//lxyzd -> lxyzdlelt by Kk 03/16
//entropy_residual_flux_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_res2,ntot[0],rdt[0],stage[0],lorder[0], ltot[0], d_totalh_temp, lxyzd, d_vx, d_vy, d_vz, if3d[0]);
entropy_residual_flux_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_res2,ntot[0],rdt[0],stage[0],lorder[0], ltot[0], d_totalh_temp, lxyzdlelt, d_vx, d_vy, d_vz, if3d[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after kernel 1cuda status: %s\n",hipGetErrorString(code1));
#endif
int mdm1 = lx1[0]-1;
// Following is the local_grad3 function
int nx_2 = lx1[0]*lx1[0];
int nx_3 = nx_2*lx1[0];
int nxd_2 = nx_2;
int nxd_3 = nx_3;
//ur(nx,nx*nx) = D(nx,nx) * u(nx,nx*nx) fortran
//ur(nx*nx,nx) = u(nx*nx,nx) * D(nx,nx) C
if(if3d[0]){
blockSize=glbblockSize1[0], gridSize;
// for ur1 us1 and ut1
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp,nx_2, d_dxm1, lx1[0], d_ur1, lx1[0], nelt[0], nx_3, 0, nxd_3, 0);//ur,us, ut should be indexed by nxd
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after 1st mxm 1cuda status: %s\n",hipGetErrorString(code1));
#endif
for(int k = 0; k<lx1[0]; k++){
//usk(nx,nx) = uk(nx,nx) * dt(nx,nx) fortran
//usk(nx,nx) = dt(nx,nx) * uk(nx,nx) C
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+k*nx_2, lx1[0],d_us1+k*nx_2, lx1[0], nelt[0], 0, nx_3, nxd_3, 0);
}
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after for loop mxm 1cuda status: %s\n",hipGetErrorString(code1));
#endif
//ut(nx_2,nx) = u(nx_2,nx) * dt(nx,nx) fortran
//ut(nx,nx_2) = dt(nx,nx) * u(nx,nx_2) C
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp, lx1[0], d_ut1, nx_2, nelt[0], 0, nx_3, nxd_3, 0);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after 3rd mxm 1cuda status: %s\n",hipGetErrorString(code1));
#endif
// for ur2 us2 and ut2
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp+lxyzd*nelt[0],nx_2, d_dxm1, lx1[0], d_ur2, lx1[0], nelt[0], nx_3, 0, nxd_3, 0);//ur,us, ut should be indexed by nxd
for(int k = 0; k<lx1[0]; k++){
//usk(nx,nx) = uk(nx,nx) * dt(nx,nx) fortran
//usk(nx,nx) = dt(nx,nx) * uk(nx,nx) C
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+lxyzd*nelt[0]+k*nx_2, lx1[0],d_us2+k*nx_2, lx1[0], nelt[0], 0, nx_3, nxd_3, 0);
}
//ut(nx_2,nx) = u(nx_2,nx) * dt(nx,nx) fortran
//ut(nx,nx_2) = dt(nx,nx) * u(nx,nx_2) C
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+lxyzd*nelt[0], lx1[0], d_ut2, nx_2, nelt[0], 0, nx_3, nxd_3, 0);
// for ur3 us3 and ut3
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp+2*lxyzd*nelt[0],nx_2, d_dxm1, lx1[0], d_ur3, lx1[0], nelt[0], nx_3, 0, nxd_3, 0);//ur,us, ut should be indexed by nxd
for(int k = 0; k<lx1[0]; k++){
//usk(nx,nx) = uk(nx,nx) * dt(nx,nx) fortran
//usk(nx,nx) = dt(nx,nx) * uk(nx,nx) C
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+2*lxyzd*nelt[0]+k*nx_2, lx1[0],d_us3+k*nx_2, lx1[0], nelt[0], 0, nx_3, nxd_3, 0);
}
//ut(nx_2,nx) = u(nx_2,nx) * dt(nx,nx) fortran
//ut(nx,nx_2) = dt(nx,nx) * u(nx,nx_2) C
gridSize = (int)ceil((float)nelt[0]*nx_3/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+2*lxyzd*nelt[0], lx1[0], d_ut3, nx_2, nelt[0], 0, nx_3, nxd_3, 0);
}else{
// for ur1 us1 and ut1
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp,lx1[0], d_dxm1, lx1[0], d_ur1, lx1[0], nelt[0], nx_2, 0, nxd_2, 0);//ur,us, ut should be indexed by nxd
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp, lx1[0],d_us1, lx1[0], nelt[0], 0, nx_2, nxd_2, 0);
// for ur2 us2 and ut1
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_totalh_temp+lxyzd*nelt[0],lx1[0], d_dxm1, lx1[0], d_ur2, lx1[0], nelt[0], nx_2, 0, nxd_2, 0);//ur,us, ut should be indexed by nxd
gridSize = (int)ceil((float)nelt[0]*nx_2/blockSize);
mxm1<<<gridSize, blockSize>>>(d_dxtm1,lx1[0], d_totalh_temp+lxyzd*nelt[0], lx1[0],d_us2, lx1[0], nelt[0], 0, nx_2, nxd_2, 0);
}
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper before flux_div_mini_gpu_kernel cuda status: %s\n",hipGetErrorString(code1));
#endif
flux_div_mini_gpu_kernel<<<gridSize, blockSize>>>(d_tlag,d_res2,ntot[0],rdt[0],stage[0],lorder[0], ltot[0], d_totalh_temp, lxyzd, d_ur1,d_us1, d_ut1, d_ur2,d_us2, d_ut2, d_ur3, d_us3, d_ut3,d_ud, ldd, d_jacmi, d_rxm1, d_sxm1, d_txm1, d_rym1, d_sym1, d_tym1, d_rzm1, d_szm1, d_tzm1,if3d[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA: entropy_residual_gpu_wrapper after flux_div_mini_gpu_kernel cuda status: %s\n",hipGetErrorString(code1));
#endif
hipFree(d_totalh_temp);
hipFree(d_ur1);
hipFree(d_ur2);
hipFree(d_ur3);
hipFree(d_us1);
hipFree(d_us2);
hipFree(d_us3);
hipFree(d_ut1);
hipFree(d_ut2);
hipFree(d_ut3);
hipFree(d_ud);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End entropy residual_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));
#endif
//}
}
__global__ void wavevisc_gpu_kernel(double *t,double *csound, double *vx, double *vy, double *vz, int ntot, double *wavespeed,int lxyz, int lx1, int ly1, int lz1, double *vtranstmp, double c_max,int ltot, double *meshh ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
wavespeed[id]= csound [id] +sqrt(vx[id]*vx[id]+vy[id]*vy[id]+vz[id]*vz[id] ) ;
// find max of wavespeed using reduction
__syncthreads();
unsigned int i = lxyz/2;
int len = lxyz;
int e= id/(lxyz);
int startofcurrentelement = e*lxyz;
while(i != 0){
if(id-startofcurrentelement <= i){
wavespeed[id] = fmax(fabs(wavespeed[id]),fabs(wavespeed[startofcurrentelement + (id+i)%len]));
}
__syncthreads();
//added by Kk 02/05/2019 since the latter one may not correct when len is odd
len = (len+1)/2;
i = len/2;
/* commented by Kk 02/05/2019
len = i;
i /= 2;*/
}
double maxeig = wavespeed[e*lxyz];
/*if(id%lxyz == 0){
printf("maxeig in wavevisc %d %.15lf %.15lf \n", id/lxyz, maxeig, c_max);
}*/
// find max of vtrans using reduction. But never used? check with Dr.Tania
//i = lxyz/2;
//int e= id/(lx1*ly1*lz1);
//int startofcurrentelement = id-e;
//while(i != 0){
// if(id-startofcurrentelement < i){
// vtranstmp[id] = fmaxf(vtranstmp[id], vtranstmp[id + i]);
// }
// __syncthreads();
// i /= 2;
//}
//int rhomax = vtranstmp[id-e];
t[2*ltot+id] = c_max*maxeig*meshh[e];
// if(id<10){
// printf("$$$ print from cuda maxeig = %lf t[2*ltot+id]= %lf meshh[e]=%lf \n",maxeig,t[2*ltot+id],meshh[e]);
// }
}
}
extern "C" void wavevisc_gpu_wrapper_(int *glbblockSize1,double *d_t, double *d_csound,double *d_vx, double *d_vy, double *d_vz, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *d_vtrans, double *c_max, double *d_meshh, int *irho ){
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start wavevisc_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d, lz1= %d,c_max= %lf,irho= %d \n",nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],c_max[0],irho[0]);
#endif
// }
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
double *d_wavespeed;
hipMalloc((void**)&d_wavespeed,nelt[0]*lxyz* sizeof(double));
// cudaMemset(d_totalh_temp, 0.0, 3*lxyzd*nelt*sizeof(double));
double *d_vtranstemp;
hipMalloc((void**)&d_vtranstemp,nelt[0]*lxyz* sizeof(double));
hipMemcpy(d_vtranstemp, &d_vtrans[(irho[0]-1)*lelt[0]*lxyz], nelt[0]*lxyz* sizeof(double), hipMemcpyDeviceToDevice);
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
wavevisc_gpu_kernel<<<gridSize, blockSize>>>(d_t,d_csound, d_vx, d_vy, d_vz,ntot,d_wavespeed, lxyz,lx1[0],ly1[0],lz1[0],d_vtranstemp,c_max[0], ltot, d_meshh);
hipFree(d_wavespeed);
hipFree(d_vtranstemp);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End Wavevisc_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));
#endif
// }
}
__global__ void max_to_trilin_gpu_kernel(double *t,int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy, double *xm1, double *ym1, double *zm1, int if3d ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lxyz);
double p000 = t[2*ltot+e*lxyz];
double p100 = t[2*ltot+e*lxyz+(lx1-1)];
double p010 = t[2*ltot+e*lxyz+(ly1-1)*lx1];
double p110 = t[2*ltot+e*lxyz+(ly1-1)*lx1+(lx1-1)];
double p001 = t[2*ltot+e*lxyz+(lz1-1)*lxy];
double p101 = t[2*ltot+e*lxyz+(lz1-1)*lxy+(lx1-1)];
double p011 = t[2*ltot+e*lxyz+(lz1-1)*lxy+(ly1-1)*lx1];
double p111 = t[2*ltot+e*lxyz+(lz1-1)*lxy+(ly1-1)*lx1+(lx1-1)];
double c1=p100-p000;
double c2=p010-p000;
double c3=p001-p000;
double c4=p110-p010-p100+p000;
double c5=p011-p001-p010+p000;
double c6=p101-p001-p100+p000;
double c7=p111-p011-p101-p110+p100+p001+p010-p000;
double rdx=1.0/(xm1[e*lxyz+(lx1-1)]-xm1[e*lxyz]); // cubes only!!!
double rdy=1.0/(ym1[e*lxyz+(ly1-1)*lx1]-ym1[e*lxyz]);
double rdz=0.0;
if(if3d){ rdz=1.0/(zm1[e*lxyz+(lz1-1)*lxy]-zm1[e*lxyz]); }
int firstlx = id%lxyz;
double deltax=rdx*(xm1[id]-xm1[e*lxyz]) ;//! cubes only!!!
double deltay=rdy*(ym1[id]-ym1[e*lxyz]);
double deltaz=0.0;
if (if3d){ deltaz=rdz*(zm1[id]-zm1[e*lxyz]);}
t[2*ltot+id] =p000+c1*deltax+c2*deltay+c3*deltaz+ c4*deltax*deltay+c5*deltay*deltaz+ c6*deltaz*deltax+c7*deltay*deltaz*deltax;
/*if(id ==ntot-1){
printf("debug max_to_trilin: %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %.30lf, %d\n", p000, c1, c2, c3, c4, c5, c6, c7, rdx, rdy, deltax, deltay, deltaz, t[2*ltot+id], if3d);
}*/
}
}
extern "C" void max_to_trilin_gpu_wrapper_(int *glbblockSize1,double *d_t, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *d_xm1, double *d_ym1, double *d_zm1, int *if3d ){
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start max_to_trilin_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,if3d=%d \n",nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],if3d[0]);
#endif
//}
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
max_to_trilin_gpu_kernel<<<gridSize, blockSize>>>(d_t,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0], d_xm1, d_ym1, d_zm1, if3d[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
//if (code2 != cudaSuccess){
printf("CUDA: End max_to_trilin_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));
#endif
//}
}
__global__ void resvisc_gpu_kernel1(double *res2,int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy,double *meshh ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lx1*ly1*lz1);
res2[id] = res2[id]*meshh[e]*meshh[e];
}
}
extern "C" void resvisc_gpu_wrapper1_(int *glbblockSize1,double *d_res2, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *d_meshh){
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
//if (code1 != cudaSuccess){
printf("CUDA: Start resvisc_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt= %d,lelt= %d,lx1= %d,ly1= %d,lz1 = %d,\n", nelt[0],lelt[0],lx1[0],ly1[0],lz1[0]);
#endif
//}
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
resvisc_gpu_kernel1<<<gridSize, blockSize>>>(d_res2,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0], d_meshh);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
//if (code2 != cudaSuccess){
printf("CUDA: End resvisc_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));
#endif
//}
}
__global__ void resvisc_gpu_kernel2(double *res2,int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy,double c_sub_e, double maxdiff ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lx1*ly1*lz1);
res2[id] = fabs(res2[id]);
res2[id] = res2[id]*c_sub_e; // cmult
if(maxdiff !=0){
double consta = 1/maxdiff;
res2[id] = res2[id]*consta;
}
}
}
extern "C" void resvisc_gpu_wrapper2_(int *glbblockSize1,double *d_res2, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1, double *c_sub_e, double *maxdiff){
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start resvisc_gpu_wrapper2 cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt=%d,lelt=%d,lx1=%d,ly1=%d,lz1=%d,c_sub_e=%lf,maxdiff= %.20lf, \n",nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],c_sub_e[0],maxdiff[0]);
#endif
// }
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
int blockSize =glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
resvisc_gpu_kernel2<<<gridSize, blockSize>>>(d_res2,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0], c_sub_e[0], maxdiff[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End resvisc_gpu_wrapper2 cuda status: %s\n",hipGetErrorString(code2));
#endif
// }
}
__global__ void evnsmooth_gpu_kernel(double *res2, double *t, int ntot,int lxyz, int lx1, int ly1, int lz1,int ltot, int lxy, int kstart, int kend, int jstart, int jend, int istart, int iend,int ldim , double rldim, double *rtmp, int if3d ){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int e= id/(lx1*ly1*lz1);
if(t[2*ltot+id] <= res2[id]){
res2[id] = t[2*ltot+id];// wavevisc and resvisc are really res2 and t. but the dimensions are different. As I understand this will start from 0 and works well. Need to check with Dr.Tania . adeesha
}
//global syncthread is needed here. check with Dr.Tania. adeesha.
rtmp[id] = res2[id];
int ix= id % lx1;
int iy= (id/lx1)%ly1;
int iz = (id / (lx1*ly1))%lz1;
if((kstart<=iz && iz<=kend)&& (jstart<= iy && iy<= jend) && (istart<=ix && ix<=iend)){
int izm,izp;
if(if3d){
int km1=iz-1;
int kp1=iz+1;
int izm=km1;
if (km1 < 0){ izm=kp1;} // Guermond symmetry
izp=kp1;
if (kp1 > (lz1-1)){ izp=km1;} // Guermond symmetry
}
else{
izm=iz;
izp=iz;
}
int jm1=iy-1;
int jp1=iy+1;
int iym=jm1;
if (jm1 < 0){ iym=jp1;}// Guermond symmetry
int iyp=jp1;
if (jp1 > (ly1-1)){ iyp=jm1;} // Guermond symmetry
int im1=ix-1;
int ip1=ix+1;
int ixm=im1;
if (im1 < 0){ ixm=ip1;} // Guermond symmetry
int ixp=ip1;
if (ip1 > (lx1-1)) {ixp=im1 ;} // Guermond symmetry
double x0 = res2[e*lxyz+iz*lxy+iy*lx1+ix];
double x1 = res2[e*lxyz+iz*lxy+iy*lx1+ixm];
double x2 = res2[e*lxyz+iz*lxy+iy*lx1+ixp];
double x3 = res2[e*lxyz+iz*lxy+iym*lx1+ix];
double x4 = res2[e*lxyz+iz*lxy+iyp*lx1+ix];
double x5,x6;
if (if3d){
x5 = res2[e*lxyz+izm*lxy+iy*lx1+ixp];
x6 = res2[e*lxyz+izp*lxy+iy*lx1+ixp];
}
else {
x5=0.0;
x6=0.0;
}
rtmp[id]=0.25*(2.0*ldim*x0+x1+x2+x3+x4+x5+x6)*rldim;// check whether this is same as rtmp [id]. adeesha
}
res2[id]=rtmp[id];
}
}
extern "C" void evnsmooth_gpu_wrapper_(int *glbblockSize1,double *d_res2, double *d_t, int *nelt, int *lelt, int *lx1, int *ly1, int *lz1,int *kstart, int *kend, int *jstart, int *jend, int *istart, int *iend, int *ldim , double *rldim, int *if3d ){
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
// if (code1 != cudaSuccess){
printf("CUDA: Start evnsmooth_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start compute_entropy_gpu_wrapper values nelt =%d ,lelt=%d,lx1=%d,ly1=%d,lz1=%d,kstart=%d,kend=%d,jstart=%d,jend=%d,istart=%d,iend=%d,ldim=%d ,rldim=%lf,if3d=%d,\n", nelt[0],lelt[0],lx1[0],ly1[0],lz1[0],kstart[0],kend[0],jstart[0],jend[0],istart[0],iend[0],ldim[0] ,rldim[0],if3d[0]);
#endif
// }
int ntot = nelt[0]*lx1[0]*ly1[0]*lz1[0];
int lxyz = lx1[0]*ly1[0]*lz1[0];
int ltot = lelt[0]*lxyz;
double *d_rtmp;
hipMalloc((void**)&d_rtmp,nelt[0]*lxyz* sizeof(double));
int blockSize = glbblockSize1[0], gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
evnsmooth_gpu_kernel<<<gridSize, blockSize>>>(d_res2,d_t,ntot,lxyz,lx1[0],ly1[0],lz1[0], ltot,lx1[0]*ly1[0],(kstart[0]-1),(kend[0]-1),(jstart[0]-1),(jend[0]-1),(istart[0]-1),(iend[0]-1),ldim[0] ,rldim[0], d_rtmp, if3d[0] );
hipFree(d_rtmp);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
// if (code2 != cudaSuccess){
printf("CUDA: End evnsmooth_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));
#endif
// }
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void resetParticlesKernel(float3* pos, float3* vel, float* age, float* life, int nParts)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
int n = x;
if (n<nParts) {
pos[n] = make_float3(0.0,0.0,0.0);
vel[n] = make_float3(0.0,0.0,0.0);
age[n] = 1.0;
life[n] = 1.0;
}
} | code for sm_80
Function : _Z20resetParticlesKernelP6float3S0_PfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R11, 0x3f800000 ; /* 0x3f800000000b7802 */
/* 0x000fe20000000f00 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00a0*/ IMAD.WIDE R2, R8, R5, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R8.reuse, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x040fe200078e0205 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe6000c101904 */
/*00d0*/ IMAD.WIDE R6, R8.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x0c0fe200078e0209 */
/*00e0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe6000c101904 */
/*00f0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e0209 */
/*0100*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0150*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void resetParticlesKernel(float3* pos, float3* vel, float* age, float* life, int nParts)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
int n = x;
if (n<nParts) {
pos[n] = make_float3(0.0,0.0,0.0);
vel[n] = make_float3(0.0,0.0,0.0);
age[n] = 1.0;
life[n] = 1.0;
}
} | .file "tmpxft_00180561_00000000-6_resetParticlesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i
.type _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i, @function
_Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20resetParticlesKernelP6float3S0_PfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i, .-_Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i
.globl _Z20resetParticlesKernelP6float3S0_PfS1_i
.type _Z20resetParticlesKernelP6float3S0_PfS1_i, @function
_Z20resetParticlesKernelP6float3S0_PfS1_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20resetParticlesKernelP6float3S0_PfS1_i, .-_Z20resetParticlesKernelP6float3S0_PfS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20resetParticlesKernelP6float3S0_PfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20resetParticlesKernelP6float3S0_PfS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void resetParticlesKernel(float3* pos, float3* vel, float* age, float* life, int nParts)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
int n = x;
if (n<nParts) {
pos[n] = make_float3(0.0,0.0,0.0);
vel[n] = make_float3(0.0,0.0,0.0);
age[n] = 1.0;
life[n] = 1.0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void resetParticlesKernel(float3* pos, float3* vel, float* age, float* life, int nParts)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
int n = x;
if (n<nParts) {
pos[n] = make_float3(0.0,0.0,0.0);
vel[n] = make_float3(0.0,0.0,0.0);
age[n] = 1.0;
life[n] = 1.0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void resetParticlesKernel(float3* pos, float3* vel, float* age, float* life, int nParts)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
int n = x;
if (n<nParts) {
pos[n] = make_float3(0.0,0.0,0.0);
vel[n] = make_float3(0.0,0.0,0.0);
age[n] = 1.0;
life[n] = 1.0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.globl _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.p2align 8
.type _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i,@function
_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_dual_mov_b32 v12, 1.0 :: v_dual_mov_b32 v3, s8
v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[8:9], null, v1, 12, s[0:1]
v_mad_i64_i32 v[10:11], null, v1, 12, s[2:3]
v_add_co_u32 v0, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_store_b96 v[8:9], v[3:5], off
global_store_b96 v[10:11], v[3:5], off
global_store_b32 v[0:1], v12, off
global_store_b32 v[6:7], v12, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, .Lfunc_end0-_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void resetParticlesKernel(float3* pos, float3* vel, float* age, float* life, int nParts)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
int n = x;
if (n<nParts) {
pos[n] = make_float3(0.0,0.0,0.0);
vel[n] = make_float3(0.0,0.0,0.0);
age[n] = 1.0;
life[n] = 1.0;
}
} | .text
.file "resetParticlesKernel.hip"
.globl _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i # -- Begin function _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.p2align 4, 0x90
.type _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i,@function
_Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i: # @_Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, .Lfunc_end0-_Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i,@object # @_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.section .rodata,"a",@progbits
.globl _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.p2align 3, 0x0
_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i:
.quad _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.size _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i"
.size .L__unnamed_1, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20resetParticlesKernelP6float3S0_PfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R11, 0x3f800000 ; /* 0x3f800000000b7802 */
/* 0x000fe20000000f00 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00a0*/ IMAD.WIDE R2, R8, R5, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R8.reuse, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x040fe200078e0205 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe6000c101904 */
/*00d0*/ IMAD.WIDE R6, R8.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x0c0fe200078e0209 */
/*00e0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe6000c101904 */
/*00f0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e0209 */
/*0100*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0150*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.globl _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.p2align 8
.type _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i,@function
_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_dual_mov_b32 v12, 1.0 :: v_dual_mov_b32 v3, s8
v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[8:9], null, v1, 12, s[0:1]
v_mad_i64_i32 v[10:11], null, v1, 12, s[2:3]
v_add_co_u32 v0, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_store_b96 v[8:9], v[3:5], off
global_store_b96 v[10:11], v[3:5], off
global_store_b32 v[0:1], v12, off
global_store_b32 v[6:7], v12, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, .Lfunc_end0-_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00180561_00000000-6_resetParticlesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i
.type _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i, @function
_Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20resetParticlesKernelP6float3S0_PfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i, .-_Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i
.globl _Z20resetParticlesKernelP6float3S0_PfS1_i
.type _Z20resetParticlesKernelP6float3S0_PfS1_i, @function
_Z20resetParticlesKernelP6float3S0_PfS1_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z20resetParticlesKernelP6float3S0_PfS1_iP6float3S0_PfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20resetParticlesKernelP6float3S0_PfS1_i, .-_Z20resetParticlesKernelP6float3S0_PfS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20resetParticlesKernelP6float3S0_PfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20resetParticlesKernelP6float3S0_PfS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "resetParticlesKernel.hip"
.globl _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i # -- Begin function _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.p2align 4, 0x90
.type _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i,@function
_Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i: # @_Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, .Lfunc_end0-_Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i,@object # @_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.section .rodata,"a",@progbits
.globl _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.p2align 3, 0x0
_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i:
.quad _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.size _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i"
.size .L__unnamed_1, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20resetParticlesKernelP15HIP_vector_typeIfLj3EES1_PfS2_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void boxFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height, int channel)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
for(int c=0 ; c<channel ; c++)
{
// Sum of pixel values
float sum = 0;
// Number of filter pixels
float kS = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))*channel+c];
sum += fl;
kS += 1;
}
}
dstImage[(y*width+x)*channel+c] = sum / kS;
}
}
} | .file "tmpxft_0019aeaa_00000000-6_boxFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji
.type _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji, @function
_Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9boxFilterPhS_jji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji, .-_Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji
.globl _Z9boxFilterPhS_jji
.type _Z9boxFilterPhS_jji, @function
_Z9boxFilterPhS_jji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9boxFilterPhS_jji, .-_Z9boxFilterPhS_jji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9boxFilterPhS_jji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9boxFilterPhS_jji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void boxFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height, int channel)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
for(int c=0 ; c<channel ; c++)
{
// Sum of pixel values
float sum = 0;
// Number of filter pixels
float kS = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))*channel+c];
sum += fl;
kS += 1;
}
}
dstImage[(y*width+x)*channel+c] = sum / kS;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void boxFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height, int channel)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
for(int c=0 ; c<channel ; c++)
{
// Sum of pixel values
float sum = 0;
// Number of filter pixels
float kS = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))*channel+c];
sum += fl;
kS += 1;
}
}
dstImage[(y*width+x)*channel+c] = sum / kS;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void boxFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height, int channel)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
for(int c=0 ; c<channel ; c++)
{
// Sum of pixel values
float sum = 0;
// Number of filter pixels
float kS = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))*channel+c];
sum += fl;
kS += 1;
}
}
dstImage[(y*width+x)*channel+c] = sum / kS;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9boxFilterPhS_jji
.globl _Z9boxFilterPhS_jji
.p2align 8
.type _Z9boxFilterPhS_jji,@function
_Z9boxFilterPhS_jji:
s_load_b32 s4, s[0:1], 0x2c
s_add_u32 s2, s0, 32
v_and_b32_e32 v1, 0x3ff, v0
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s4
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v2, s14, v1
v_cmpx_lt_i32_e32 0, v2
s_cbranch_execz .LBB0_8
s_load_b32 s2, s[2:3], 0xc
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_add_i32 s3, s5, -1
s_mul_i32 s15, s15, s2
s_add_i32 s2, s4, -1
v_add_nc_u32_e32 v0, s15, v3
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s2, s3, v0
v_cmp_lt_i32_e64 s3, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_cmp_gt_i32 s6, 0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_8
v_add3_u32 v5, v3, s15, -1
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s4, v5, v[1:2]
v_mad_u64_u32 v[4:5], null, v0, s4, v[2:3]
v_add3_u32 v1, v3, s14, -1
s_mul_i32 s4, s6, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v1, s6, v1
v_mul_lo_u32 v0, v4, s6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v4, v1
s_mov_b32 s7, -1
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v4
s_mov_b32 s8, 3
.LBB0_5:
s_waitcnt lgkmcnt(0)
global_load_u8 v6, v5, s[0:1]
v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_nc_u32 v5, s6, v5
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s8, 0
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
v_add_f32_e32 v3, v3, v6
s_cbranch_scc0 .LBB0_5
v_add_nc_u32_e32 v4, s4, v4
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 2
s_cbranch_scc0 .LBB0_4
v_div_scale_f32 v4, null, v2, v2, v3
v_div_scale_f32 v7, vcc_lo, v3, v2, v3
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v6
v_div_fixup_f32 v2, v4, v2, v3
v_add_nc_u32_e32 v3, s5, v0
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s5, s6
v_cvt_i32_f32_e32 v2, v2
global_store_b8 v3, v2, s[2:3]
s_cbranch_scc0 .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9boxFilterPhS_jji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9boxFilterPhS_jji, .Lfunc_end0-_Z9boxFilterPhS_jji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9boxFilterPhS_jji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9boxFilterPhS_jji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void boxFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height, int channel)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
for(int c=0 ; c<channel ; c++)
{
// Sum of pixel values
float sum = 0;
// Number of filter pixels
float kS = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))*channel+c];
sum += fl;
kS += 1;
}
}
dstImage[(y*width+x)*channel+c] = sum / kS;
}
}
} | .text
.file "boxFilter.hip"
.globl _Z24__device_stub__boxFilterPhS_jji # -- Begin function _Z24__device_stub__boxFilterPhS_jji
.p2align 4, 0x90
.type _Z24__device_stub__boxFilterPhS_jji,@function
_Z24__device_stub__boxFilterPhS_jji: # @_Z24__device_stub__boxFilterPhS_jji
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9boxFilterPhS_jji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__boxFilterPhS_jji, .Lfunc_end0-_Z24__device_stub__boxFilterPhS_jji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9boxFilterPhS_jji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9boxFilterPhS_jji,@object # @_Z9boxFilterPhS_jji
.section .rodata,"a",@progbits
.globl _Z9boxFilterPhS_jji
.p2align 3, 0x0
_Z9boxFilterPhS_jji:
.quad _Z24__device_stub__boxFilterPhS_jji
.size _Z9boxFilterPhS_jji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9boxFilterPhS_jji"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__boxFilterPhS_jji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9boxFilterPhS_jji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019aeaa_00000000-6_boxFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji
.type _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji, @function
_Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9boxFilterPhS_jji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji, .-_Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji
.globl _Z9boxFilterPhS_jji
.type _Z9boxFilterPhS_jji, @function
_Z9boxFilterPhS_jji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9boxFilterPhS_jjiPhS_jji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9boxFilterPhS_jji, .-_Z9boxFilterPhS_jji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9boxFilterPhS_jji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9boxFilterPhS_jji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "boxFilter.hip"
.globl _Z24__device_stub__boxFilterPhS_jji # -- Begin function _Z24__device_stub__boxFilterPhS_jji
.p2align 4, 0x90
.type _Z24__device_stub__boxFilterPhS_jji,@function
_Z24__device_stub__boxFilterPhS_jji: # @_Z24__device_stub__boxFilterPhS_jji
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9boxFilterPhS_jji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__boxFilterPhS_jji, .Lfunc_end0-_Z24__device_stub__boxFilterPhS_jji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9boxFilterPhS_jji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9boxFilterPhS_jji,@object # @_Z9boxFilterPhS_jji
.section .rodata,"a",@progbits
.globl _Z9boxFilterPhS_jji
.p2align 3, 0x0
_Z9boxFilterPhS_jji:
.quad _Z24__device_stub__boxFilterPhS_jji
.size _Z9boxFilterPhS_jji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9boxFilterPhS_jji"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__boxFilterPhS_jji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9boxFilterPhS_jji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
void cVecAdd(float *A, float *B, float *C)
{
for(long long i=0; i < (4096 * 16); ++i)
{
C[i] = A[i] + B[i];
}
}
__global__ void VecAdd(float *A, float *B, float *C)
{
long long i = threadIdx.x + blockIdx.x * blockDim.x;
C[i] = A[i] + B[i];
}
int main()
{
const long long N = 4096 * 16;
dim3 NumberOfThreadsPerBlock (256, 8, 1);
dim3 NumberOfBlocks ((N / NumberOfThreadsPerBlock.x),
(N / NumberOfThreadsPerBlock.y),
1);
//printf("Number of blocks %d ", NumberOfBlocks);
float A[N];
float B[N];
float C[N];
float *D_A, *D_B, *D_C;
clock_t start, end, cstart, cend;
double elapsed, celapsed;
size_t memSize = N * sizeof(float);
cudaMalloc( (void**) &D_A, memSize);
cudaMalloc( (void**) &D_B, memSize);
cudaMalloc( (void**) &D_C, memSize);
for(long long i=0; i < N; ++i)
{
A[i] = i;
B[i] = i * 2.0;
C[i] = 0;
}
cudaMemcpy(D_A, A, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(D_B, B, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(D_C, C, memSize, cudaMemcpyHostToDevice);
cudaThreadSynchronize();
start = clock();
VecAdd<<<NumberOfBlocks, NumberOfThreadsPerBlock>>>(D_A, D_B, D_C);
cudaThreadSynchronize();
cudaMemcpy(C, D_C, memSize, cudaMemcpyDeviceToHost);
end = clock();
elapsed = ((double)(end-start)) / CLOCKS_PER_SEC;
cstart = clock();
cVecAdd(A, B, C);
cend = clock();
celapsed = ((double)(cend - cstart)) / CLOCKS_PER_SEC;
printf("Time elapsed %f \n", elapsed);
printf("Time celapsed %f \n", celapsed);
cudaFree(D_A);
cudaFree(D_B);
cudaFree(D_C);
} | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
void cVecAdd(float *A, float *B, float *C)
{
for(long long i=0; i < (4096 * 16); ++i)
{
C[i] = A[i] + B[i];
}
}
__global__ void VecAdd(float *A, float *B, float *C)
{
long long i = threadIdx.x + blockIdx.x * blockDim.x;
C[i] = A[i] + B[i];
}
int main()
{
const long long N = 4096 * 16;
dim3 NumberOfThreadsPerBlock (256, 8, 1);
dim3 NumberOfBlocks ((N / NumberOfThreadsPerBlock.x),
(N / NumberOfThreadsPerBlock.y),
1);
//printf("Number of blocks %d ", NumberOfBlocks);
float A[N];
float B[N];
float C[N];
float *D_A, *D_B, *D_C;
clock_t start, end, cstart, cend;
double elapsed, celapsed;
size_t memSize = N * sizeof(float);
cudaMalloc( (void**) &D_A, memSize);
cudaMalloc( (void**) &D_B, memSize);
cudaMalloc( (void**) &D_C, memSize);
for(long long i=0; i < N; ++i)
{
A[i] = i;
B[i] = i * 2.0;
C[i] = 0;
}
cudaMemcpy(D_A, A, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(D_B, B, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(D_C, C, memSize, cudaMemcpyHostToDevice);
cudaThreadSynchronize();
start = clock();
VecAdd<<<NumberOfBlocks, NumberOfThreadsPerBlock>>>(D_A, D_B, D_C);
cudaThreadSynchronize();
cudaMemcpy(C, D_C, memSize, cudaMemcpyDeviceToHost);
end = clock();
elapsed = ((double)(end-start)) / CLOCKS_PER_SEC;
cstart = clock();
cVecAdd(A, B, C);
cend = clock();
celapsed = ((double)(cend - cstart)) / CLOCKS_PER_SEC;
printf("Time elapsed %f \n", elapsed);
printf("Time celapsed %f \n", celapsed);
cudaFree(D_A);
cudaFree(D_B);
cudaFree(D_C);
} | .file "tmpxft_00173fd1_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7cVecAddPfS_S_
.type _Z7cVecAddPfS_S_, @function
_Z7cVecAddPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z7cVecAddPfS_S_, .-_Z7cVecAddPfS_S_
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time elapsed %f \n"
.LC3:
.string "Time celapsed %f \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -786432(%rsp), %r11
.cfi_def_cfa 11, 786456
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 786544
movq %fs:40, %rax
movq %rax, 786504(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $256, 52(%rsp)
movl $8192, 56(%rsp)
movl $1, 60(%rsp)
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $0, %eax
.L15:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movss %xmm0, 64(%rsp,%rax,4)
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 262208(%rsp,%rax,4)
movl $0x00000000, 524352(%rsp,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L15
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 262208(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 524352(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
call clock@PLT
movq %rax, %rbx
movl $256, 40(%rsp)
movl $8, 44(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
call cudaThreadSynchronize@PLT
leaq 524352(%rsp), %rbp
movl $2, %ecx
movl $262144, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rsp)
call clock@PLT
movq %rax, %rbx
leaq 262208(%rsp), %rsi
leaq 64(%rsp), %rdi
movq %rbp, %rdx
call _Z7cVecAddPfS_S_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movapd %xmm0, %xmm1
divsd .LC1(%rip), %xmm1
movsd %xmm1, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 786504(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $786520, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
void cVecAdd(float *A, float *B, float *C)
{
for(long long i=0; i < (4096 * 16); ++i)
{
C[i] = A[i] + B[i];
}
}
__global__ void VecAdd(float *A, float *B, float *C)
{
long long i = threadIdx.x + blockIdx.x * blockDim.x;
C[i] = A[i] + B[i];
}
int main()
{
const long long N = 4096 * 16;
dim3 NumberOfThreadsPerBlock (256, 8, 1);
dim3 NumberOfBlocks ((N / NumberOfThreadsPerBlock.x),
(N / NumberOfThreadsPerBlock.y),
1);
//printf("Number of blocks %d ", NumberOfBlocks);
float A[N];
float B[N];
float C[N];
float *D_A, *D_B, *D_C;
clock_t start, end, cstart, cend;
double elapsed, celapsed;
size_t memSize = N * sizeof(float);
cudaMalloc( (void**) &D_A, memSize);
cudaMalloc( (void**) &D_B, memSize);
cudaMalloc( (void**) &D_C, memSize);
for(long long i=0; i < N; ++i)
{
A[i] = i;
B[i] = i * 2.0;
C[i] = 0;
}
cudaMemcpy(D_A, A, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(D_B, B, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(D_C, C, memSize, cudaMemcpyHostToDevice);
cudaThreadSynchronize();
start = clock();
VecAdd<<<NumberOfBlocks, NumberOfThreadsPerBlock>>>(D_A, D_B, D_C);
cudaThreadSynchronize();
cudaMemcpy(C, D_C, memSize, cudaMemcpyDeviceToHost);
end = clock();
elapsed = ((double)(end-start)) / CLOCKS_PER_SEC;
cstart = clock();
cVecAdd(A, B, C);
cend = clock();
celapsed = ((double)(cend - cstart)) / CLOCKS_PER_SEC;
printf("Time elapsed %f \n", elapsed);
printf("Time celapsed %f \n", celapsed);
cudaFree(D_A);
cudaFree(D_B);
cudaFree(D_C);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
void cVecAdd(float *A, float *B, float *C)
{
for(long long i=0; i < (4096 * 16); ++i)
{
C[i] = A[i] + B[i];
}
}
__global__ void VecAdd(float *A, float *B, float *C)
{
long long i = threadIdx.x + blockIdx.x * blockDim.x;
C[i] = A[i] + B[i];
}
int main()
{
const long long N = 4096 * 16;
dim3 NumberOfThreadsPerBlock (256, 8, 1);
dim3 NumberOfBlocks ((N / NumberOfThreadsPerBlock.x),
(N / NumberOfThreadsPerBlock.y),
1);
//printf("Number of blocks %d ", NumberOfBlocks);
float A[N];
float B[N];
float C[N];
float *D_A, *D_B, *D_C;
clock_t start, end, cstart, cend;
double elapsed, celapsed;
size_t memSize = N * sizeof(float);
hipMalloc( (void**) &D_A, memSize);
hipMalloc( (void**) &D_B, memSize);
hipMalloc( (void**) &D_C, memSize);
for(long long i=0; i < N; ++i)
{
A[i] = i;
B[i] = i * 2.0;
C[i] = 0;
}
hipMemcpy(D_A, A, memSize, hipMemcpyHostToDevice);
hipMemcpy(D_B, B, memSize, hipMemcpyHostToDevice);
hipMemcpy(D_C, C, memSize, hipMemcpyHostToDevice);
hipDeviceSynchronize();
start = clock();
VecAdd<<<NumberOfBlocks, NumberOfThreadsPerBlock>>>(D_A, D_B, D_C);
hipDeviceSynchronize();
hipMemcpy(C, D_C, memSize, hipMemcpyDeviceToHost);
end = clock();
elapsed = ((double)(end-start)) / CLOCKS_PER_SEC;
cstart = clock();
cVecAdd(A, B, C);
cend = clock();
celapsed = ((double)(cend - cstart)) / CLOCKS_PER_SEC;
printf("Time elapsed %f \n", elapsed);
printf("Time celapsed %f \n", celapsed);
hipFree(D_A);
hipFree(D_B);
hipFree(D_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
void cVecAdd(float *A, float *B, float *C)
{
for(long long i=0; i < (4096 * 16); ++i)
{
C[i] = A[i] + B[i];
}
}
__global__ void VecAdd(float *A, float *B, float *C)
{
long long i = threadIdx.x + blockIdx.x * blockDim.x;
C[i] = A[i] + B[i];
}
int main()
{
const long long N = 4096 * 16;
dim3 NumberOfThreadsPerBlock (256, 8, 1);
dim3 NumberOfBlocks ((N / NumberOfThreadsPerBlock.x),
(N / NumberOfThreadsPerBlock.y),
1);
//printf("Number of blocks %d ", NumberOfBlocks);
float A[N];
float B[N];
float C[N];
float *D_A, *D_B, *D_C;
clock_t start, end, cstart, cend;
double elapsed, celapsed;
size_t memSize = N * sizeof(float);
hipMalloc( (void**) &D_A, memSize);
hipMalloc( (void**) &D_B, memSize);
hipMalloc( (void**) &D_C, memSize);
for(long long i=0; i < N; ++i)
{
A[i] = i;
B[i] = i * 2.0;
C[i] = 0;
}
hipMemcpy(D_A, A, memSize, hipMemcpyHostToDevice);
hipMemcpy(D_B, B, memSize, hipMemcpyHostToDevice);
hipMemcpy(D_C, C, memSize, hipMemcpyHostToDevice);
hipDeviceSynchronize();
start = clock();
VecAdd<<<NumberOfBlocks, NumberOfThreadsPerBlock>>>(D_A, D_B, D_C);
hipDeviceSynchronize();
hipMemcpy(C, D_C, memSize, hipMemcpyDeviceToHost);
end = clock();
elapsed = ((double)(end-start)) / CLOCKS_PER_SEC;
cstart = clock();
cVecAdd(A, B, C);
cend = clock();
celapsed = ((double)(cend - cstart)) / CLOCKS_PER_SEC;
printf("Time elapsed %f \n", elapsed);
printf("Time celapsed %f \n", celapsed);
hipFree(D_A);
hipFree(D_B);
hipFree(D_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
void cVecAdd(float *A, float *B, float *C)
{
for(long long i=0; i < (4096 * 16); ++i)
{
C[i] = A[i] + B[i];
}
}
__global__ void VecAdd(float *A, float *B, float *C)
{
long long i = threadIdx.x + blockIdx.x * blockDim.x;
C[i] = A[i] + B[i];
}
int main()
{
const long long N = 4096 * 16;
dim3 NumberOfThreadsPerBlock (256, 8, 1);
dim3 NumberOfBlocks ((N / NumberOfThreadsPerBlock.x),
(N / NumberOfThreadsPerBlock.y),
1);
//printf("Number of blocks %d ", NumberOfBlocks);
float A[N];
float B[N];
float C[N];
float *D_A, *D_B, *D_C;
clock_t start, end, cstart, cend;
double elapsed, celapsed;
size_t memSize = N * sizeof(float);
hipMalloc( (void**) &D_A, memSize);
hipMalloc( (void**) &D_B, memSize);
hipMalloc( (void**) &D_C, memSize);
for(long long i=0; i < N; ++i)
{
A[i] = i;
B[i] = i * 2.0;
C[i] = 0;
}
hipMemcpy(D_A, A, memSize, hipMemcpyHostToDevice);
hipMemcpy(D_B, B, memSize, hipMemcpyHostToDevice);
hipMemcpy(D_C, C, memSize, hipMemcpyHostToDevice);
hipDeviceSynchronize();
start = clock();
VecAdd<<<NumberOfBlocks, NumberOfThreadsPerBlock>>>(D_A, D_B, D_C);
hipDeviceSynchronize();
hipMemcpy(C, D_C, memSize, hipMemcpyDeviceToHost);
end = clock();
elapsed = ((double)(end-start)) / CLOCKS_PER_SEC;
cstart = clock();
cVecAdd(A, B, C);
cend = clock();
celapsed = ((double)(cend - cstart)) / CLOCKS_PER_SEC;
printf("Time elapsed %f \n", elapsed);
printf("Time celapsed %f \n", celapsed);
hipFree(D_A);
hipFree(D_B);
hipFree(D_C);
} | .text
.file "vector_add.hip"
.globl _Z7cVecAddPfS_S_ # -- Begin function _Z7cVecAddPfS_S_
.p2align 4, 0x90
.type _Z7cVecAddPfS_S_,@function
_Z7cVecAddPfS_S_: # @_Z7cVecAddPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z7cVecAddPfS_S_, .Lfunc_end0-_Z7cVecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end1-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $786584, %rsp # imm = 0xC0098
.cfi_def_cfa_offset 786624
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq %rsp, %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 144(%rsp), %rdi
xorl %ebx, %ebx
movl $262144, %edx # imm = 0x40000
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rbx, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %rbx, %xmm1
addsd %xmm1, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm0, 524432(%rsp,%rbx,4)
movss %xmm1, 262288(%rsp,%rbx,4)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB2_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 524432(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 262288(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 144(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq clock
movq %rax, %rbx
movabsq $35184372089088, %rdi # imm = 0x200000000100
movabsq $34359738624, %rdx # imm = 0x800000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 144(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movl $2, %ecx
callq hipMemcpy
callq clock
movq %rax, %r15
xorl %r12d, %r12d
callq clock
movq %rax, %r14
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss 524432(%rsp,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 262288(%rsp,%r12,4), %xmm0
movss %xmm0, 144(%rsp,%r12,4)
incq %r12
cmpq $65536, %r12 # imm = 0x10000
jne .LBB2_5
# %bb.6: # %_Z7cVecAddPfS_S_.exit
subq %rbx, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $.L.str, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $786584, %rsp # imm = 0xC0098
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed %f \n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time celapsed %f \n"
.size .L.str.1, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00173fd1_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7cVecAddPfS_S_
.type _Z7cVecAddPfS_S_, @function
_Z7cVecAddPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z7cVecAddPfS_S_, .-_Z7cVecAddPfS_S_
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time elapsed %f \n"
.LC3:
.string "Time celapsed %f \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -786432(%rsp), %r11
.cfi_def_cfa 11, 786456
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 786544
movq %fs:40, %rax
movq %rax, 786504(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $256, 52(%rsp)
movl $8192, 56(%rsp)
movl $1, 60(%rsp)
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $0, %eax
.L15:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movss %xmm0, 64(%rsp,%rax,4)
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 262208(%rsp,%rax,4)
movl $0x00000000, 524352(%rsp,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L15
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 262208(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 524352(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
call clock@PLT
movq %rax, %rbx
movl $256, 40(%rsp)
movl $8, 44(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
call cudaThreadSynchronize@PLT
leaq 524352(%rsp), %rbp
movl $2, %ecx
movl $262144, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rsp)
call clock@PLT
movq %rax, %rbx
leaq 262208(%rsp), %rsi
leaq 64(%rsp), %rdi
movq %rbp, %rdx
call _Z7cVecAddPfS_S_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movapd %xmm0, %xmm1
divsd .LC1(%rip), %xmm1
movsd %xmm1, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 786504(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $786520, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add.hip"
.globl _Z7cVecAddPfS_S_ # -- Begin function _Z7cVecAddPfS_S_
.p2align 4, 0x90
.type _Z7cVecAddPfS_S_,@function
_Z7cVecAddPfS_S_: # @_Z7cVecAddPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z7cVecAddPfS_S_, .Lfunc_end0-_Z7cVecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end1-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $786584, %rsp # imm = 0xC0098
.cfi_def_cfa_offset 786624
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq %rsp, %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 144(%rsp), %rdi
xorl %ebx, %ebx
movl $262144, %edx # imm = 0x40000
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rbx, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %rbx, %xmm1
addsd %xmm1, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm0, 524432(%rsp,%rbx,4)
movss %xmm1, 262288(%rsp,%rbx,4)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB2_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 524432(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 262288(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 144(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq clock
movq %rax, %rbx
movabsq $35184372089088, %rdi # imm = 0x200000000100
movabsq $34359738624, %rdx # imm = 0x800000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 144(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movl $2, %ecx
callq hipMemcpy
callq clock
movq %rax, %r15
xorl %r12d, %r12d
callq clock
movq %rax, %r14
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss 524432(%rsp,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 262288(%rsp,%r12,4), %xmm0
movss %xmm0, 144(%rsp,%r12,4)
incq %r12
cmpq $65536, %r12 # imm = 0x10000
jne .LBB2_5
# %bb.6: # %_Z7cVecAddPfS_S_.exit
subq %rbx, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $.L.str, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $786584, %rsp # imm = 0xC0098
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed %f \n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time celapsed %f \n"
.size .L.str.1, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void kernel_deformation(float *img1, cudaTextureObject_t tex_img, float *mx2, float *my2, float *mz2, int nx, int ny, int nz){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = iy + ix * ny + iz * nx * ny;
float xi = iy + 1.0f + my2[id];
float yi = ix + 1.0f + mx2[id];
float zi = iz + 1.0f + mz2[id];
img1[id] = tex3D<float>(tex_img, xi - 0.5f, yi - 0.5f, zi - 0.5f);
// int id = ix + iy * nx + iz * nx * ny; // index for image
// int id2 = iy + ix * ny + iz * nx * ny; // index for DVFs
// float xi = iy + 0.5f + my2[id2];
// float yi = ix + 0.5f + mx2[id2];
// float zi = iz + 0.5f + mz2[id2];
// img1[id2] = tex3D<float>(tex_img, xi, yi, zi);
// img1[id] = 0.0f;
// if (xi < 0.5f || xi >= nx - 0.5f || yi < 0.5f || yi >= ny - 0.5f || zi < 0.5f || zi >= nz - 0.5f)
// return;
// if (xi < 0.5f) {xi = 0.5f;}
// if (xi > nx - 0.5f) {xi = nx - 0.5f;}
// int ix1, ix2, iy1, iy2, iz1, iz2;
// float wx1, wx2, wy1, wy2, wz1, wz2;
// if (xi < 0.5f)
// {ix1 = 0; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else{
// if (xi >= nx - 0.5f)
// {ix1 = nx - 1; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else
// {ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;}
// }
// if (yi < 0.5f)
// {iy1 = 0; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else{
// if (yi >= ny - 0.5f)
// {iy1 = ny - 1; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else
// {iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;}
// }
// if (zi < 0.5f)
// {iz1 = 0; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else{
// if (zi >= nz - 0.5f)
// {iz1 = nz - 1; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else
// {iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2; }
// }
// ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;
// iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;
// iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2;
// img1[id] += img[ix1 + iy1 * nx + iz1 * nx * ny] * wx1 * wy1 * wz1;
// img1[id] += img[ix1 + iy1 * nx + iz2 * nx * ny] * wx1 * wy1 * wz2;
// img1[id] += img[ix1 + iy2 * nx + iz1 * nx * ny] * wx1 * wy2 * wz1;
// img1[id] += img[ix1 + iy2 * nx + iz2 * nx * ny] * wx1 * wy2 * wz2;
// img1[id] += img[ix2 + iy1 * nx + iz1 * nx * ny] * wx2 * wy1 * wz1;
// img1[id] += img[ix2 + iy1 * nx + iz2 * nx * ny] * wx2 * wy1 * wz2;
// img1[id] += img[ix2 + iy2 * nx + iz1 * nx * ny] * wx2 * wy2 * wz1;
// img1[id] += img[ix2 + iy2 * nx + iz2 * nx * ny] * wx2 * wy2 * wz2;
}
// int x = blockSize.x * blockIdx.x + threadIdx.x;
// int y = blockSize.y * blockIdx.y + threadIdx.y;
// int z = blockSize.z * blockIdx.z + threadIdx.z;
// if (x >= nx || y >= ny || z >= nz)
// return;
// int xi = mx2[x][y][z];
// int yi = my2[x][y][z];
// int zi = mz2[x][y][z];
// singleViewImg1[x][y][z] = tex3D<float>(tex_img, xi-0.5f, yi-0.5f, zi-0.5f);
// } | code for sm_80
Function : _Z18kernel_deformationPfyS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R9, SR_CTAID.Z ; /* 0x0000000000097919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000ea20000002300 */
/*0070*/ LEA R8, R8, R5, 0x4 ; /* 0x0000000508087211 */
/* 0x001fc800078e20ff */
/*0080*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x18c], PT ; /* 0x0000630008007a0c */
/* 0x000fe40003f06270 */
/*0090*/ LEA R0, R0, R3, 0x4 ; /* 0x0000000300007211 */
/* 0x002fc800078e20ff */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x188], P0 ; /* 0x0000620000007a0c */
/* 0x000fe40000706670 */
/*00b0*/ LEA R9, R9, R2, 0x2 ; /* 0x0000000209097211 */
/* 0x004fc800078e10ff */
/*00c0*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x190], P0 ; /* 0x0000640009007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R3, R9, c[0x0][0x188], R0 ; /* 0x0000620009037a24 */
/* 0x000fe200078e0200 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0110*/ IMAD R10, R3, c[0x0][0x18c], R8 ; /* 0x00006300030a7a24 */
/* 0x000fca00078e0208 */
/*0120*/ IMAD.WIDE R4, R10, R17, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fc800078e0211 */
/*0130*/ IMAD.WIDE R2, R10.reuse, R17.reuse, c[0x0][0x178] ; /* 0x00005e000a027625 */
/* 0x0c0fe400078e0211 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.WIDE R6, R10, R17, c[0x0][0x180] ; /* 0x000060000a067625 */
/* 0x000fe400078e0211 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0180*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e300000201400 */
/*0190*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e700000201400 */
/*01a0*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e620000201400 */
/*01b0*/ FADD R12, R0, 1 ; /* 0x3f800000000c7421 */
/* 0x001fe20000000000 */
/*01c0*/ HFMA2.MMA R15, -RZ, RZ, -3, 0 ; /* 0xc2000000ff0f7435 */
/* 0x000fe200000001ff */
/*01d0*/ FADD R11, R8, 1 ; /* 0x3f800000080b7421 */
/* 0x002fc40000000000 */
/*01e0*/ FADD R13, R9, 1 ; /* 0x3f800000090d7421 */
/* 0x000fe40000000000 */
/*01f0*/ FADD R12, R12, R5 ; /* 0x000000050c0c7221 */
/* 0x004fe40000000000 */
/*0200*/ FADD R11, R11, R2 ; /* 0x000000020b0b7221 */
/* 0x008fe40000000000 */
/*0210*/ FADD R5, R12, -0.5 ; /* 0xbf0000000c057421 */
/* 0x000fe40000000000 */
/*0220*/ FADD R13, R13, R6 ; /* 0x000000060d0d7221 */
/* 0x010fe40000000000 */
/*0230*/ FADD R4, R11, -0.5 ; /* 0xbf0000000b047421 */
/* 0x000fc40000000000 */
/*0240*/ FADD R14, R13, -0.5 ; /* 0xbf0000000d0e7421 */
/* 0x000fc80000000000 */
/*0250*/ TEX.SCR.LL RZ, R5, R4, R14, 0x0, 0x5a, 3D, 0x1 ; /* 0x50005a0e04057b60 */
/* 0x000f4200019e01ff */
/*0260*/ IMAD.WIDE R2, R10, R17, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0211 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void kernel_deformation(float *img1, cudaTextureObject_t tex_img, float *mx2, float *my2, float *mz2, int nx, int ny, int nz){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = iy + ix * ny + iz * nx * ny;
float xi = iy + 1.0f + my2[id];
float yi = ix + 1.0f + mx2[id];
float zi = iz + 1.0f + mz2[id];
img1[id] = tex3D<float>(tex_img, xi - 0.5f, yi - 0.5f, zi - 0.5f);
// int id = ix + iy * nx + iz * nx * ny; // index for image
// int id2 = iy + ix * ny + iz * nx * ny; // index for DVFs
// float xi = iy + 0.5f + my2[id2];
// float yi = ix + 0.5f + mx2[id2];
// float zi = iz + 0.5f + mz2[id2];
// img1[id2] = tex3D<float>(tex_img, xi, yi, zi);
// img1[id] = 0.0f;
// if (xi < 0.5f || xi >= nx - 0.5f || yi < 0.5f || yi >= ny - 0.5f || zi < 0.5f || zi >= nz - 0.5f)
// return;
// if (xi < 0.5f) {xi = 0.5f;}
// if (xi > nx - 0.5f) {xi = nx - 0.5f;}
// int ix1, ix2, iy1, iy2, iz1, iz2;
// float wx1, wx2, wy1, wy2, wz1, wz2;
// if (xi < 0.5f)
// {ix1 = 0; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else{
// if (xi >= nx - 0.5f)
// {ix1 = nx - 1; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else
// {ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;}
// }
// if (yi < 0.5f)
// {iy1 = 0; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else{
// if (yi >= ny - 0.5f)
// {iy1 = ny - 1; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else
// {iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;}
// }
// if (zi < 0.5f)
// {iz1 = 0; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else{
// if (zi >= nz - 0.5f)
// {iz1 = nz - 1; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else
// {iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2; }
// }
// ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;
// iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;
// iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2;
// img1[id] += img[ix1 + iy1 * nx + iz1 * nx * ny] * wx1 * wy1 * wz1;
// img1[id] += img[ix1 + iy1 * nx + iz2 * nx * ny] * wx1 * wy1 * wz2;
// img1[id] += img[ix1 + iy2 * nx + iz1 * nx * ny] * wx1 * wy2 * wz1;
// img1[id] += img[ix1 + iy2 * nx + iz2 * nx * ny] * wx1 * wy2 * wz2;
// img1[id] += img[ix2 + iy1 * nx + iz1 * nx * ny] * wx2 * wy1 * wz1;
// img1[id] += img[ix2 + iy1 * nx + iz2 * nx * ny] * wx2 * wy1 * wz2;
// img1[id] += img[ix2 + iy2 * nx + iz1 * nx * ny] * wx2 * wy2 * wz1;
// img1[id] += img[ix2 + iy2 * nx + iz2 * nx * ny] * wx2 * wy2 * wz2;
}
// int x = blockSize.x * blockIdx.x + threadIdx.x;
// int y = blockSize.y * blockIdx.y + threadIdx.y;
// int z = blockSize.z * blockIdx.z + threadIdx.z;
// if (x >= nx || y >= ny || z >= nz)
// return;
// int xi = mx2[x][y][z];
// int yi = my2[x][y][z];
// int zi = mz2[x][y][z];
// singleViewImg1[x][y][z] = tex3D<float>(tex_img, xi-0.5f, yi-0.5f, zi-0.5f);
// } | .file "tmpxft_00125ba2_00000000-6_kernel_deformation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii
.type _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii, @function
_Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kernel_deformationPfyS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii, .-_Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii
.globl _Z18kernel_deformationPfyS_S_S_iii
.type _Z18kernel_deformationPfyS_S_S_iii, @function
_Z18kernel_deformationPfyS_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_deformationPfyS_S_S_iii, .-_Z18kernel_deformationPfyS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kernel_deformationPfyS_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_deformationPfyS_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void kernel_deformation(float *img1, cudaTextureObject_t tex_img, float *mx2, float *my2, float *mz2, int nx, int ny, int nz){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = iy + ix * ny + iz * nx * ny;
float xi = iy + 1.0f + my2[id];
float yi = ix + 1.0f + mx2[id];
float zi = iz + 1.0f + mz2[id];
img1[id] = tex3D<float>(tex_img, xi - 0.5f, yi - 0.5f, zi - 0.5f);
// int id = ix + iy * nx + iz * nx * ny; // index for image
// int id2 = iy + ix * ny + iz * nx * ny; // index for DVFs
// float xi = iy + 0.5f + my2[id2];
// float yi = ix + 0.5f + mx2[id2];
// float zi = iz + 0.5f + mz2[id2];
// img1[id2] = tex3D<float>(tex_img, xi, yi, zi);
// img1[id] = 0.0f;
// if (xi < 0.5f || xi >= nx - 0.5f || yi < 0.5f || yi >= ny - 0.5f || zi < 0.5f || zi >= nz - 0.5f)
// return;
// if (xi < 0.5f) {xi = 0.5f;}
// if (xi > nx - 0.5f) {xi = nx - 0.5f;}
// int ix1, ix2, iy1, iy2, iz1, iz2;
// float wx1, wx2, wy1, wy2, wz1, wz2;
// if (xi < 0.5f)
// {ix1 = 0; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else{
// if (xi >= nx - 0.5f)
// {ix1 = nx - 1; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else
// {ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;}
// }
// if (yi < 0.5f)
// {iy1 = 0; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else{
// if (yi >= ny - 0.5f)
// {iy1 = ny - 1; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else
// {iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;}
// }
// if (zi < 0.5f)
// {iz1 = 0; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else{
// if (zi >= nz - 0.5f)
// {iz1 = nz - 1; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else
// {iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2; }
// }
// ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;
// iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;
// iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2;
// img1[id] += img[ix1 + iy1 * nx + iz1 * nx * ny] * wx1 * wy1 * wz1;
// img1[id] += img[ix1 + iy1 * nx + iz2 * nx * ny] * wx1 * wy1 * wz2;
// img1[id] += img[ix1 + iy2 * nx + iz1 * nx * ny] * wx1 * wy2 * wz1;
// img1[id] += img[ix1 + iy2 * nx + iz2 * nx * ny] * wx1 * wy2 * wz2;
// img1[id] += img[ix2 + iy1 * nx + iz1 * nx * ny] * wx2 * wy1 * wz1;
// img1[id] += img[ix2 + iy1 * nx + iz2 * nx * ny] * wx2 * wy1 * wz2;
// img1[id] += img[ix2 + iy2 * nx + iz1 * nx * ny] * wx2 * wy2 * wz1;
// img1[id] += img[ix2 + iy2 * nx + iz2 * nx * ny] * wx2 * wy2 * wz2;
}
// int x = blockSize.x * blockIdx.x + threadIdx.x;
// int y = blockSize.y * blockIdx.y + threadIdx.y;
// int z = blockSize.z * blockIdx.z + threadIdx.z;
// if (x >= nx || y >= ny || z >= nz)
// return;
// int xi = mx2[x][y][z];
// int yi = my2[x][y][z];
// int zi = mz2[x][y][z];
// singleViewImg1[x][y][z] = tex3D<float>(tex_img, xi-0.5f, yi-0.5f, zi-0.5f);
// } | #include <hip/hip_runtime.h>
__global__ void kernel_deformation(float *img1, hipTextureObject_t tex_img, float *mx2, float *my2, float *mz2, int nx, int ny, int nz){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = iy + ix * ny + iz * nx * ny;
float xi = iy + 1.0f + my2[id];
float yi = ix + 1.0f + mx2[id];
float zi = iz + 1.0f + mz2[id];
img1[id] = tex3D<float>(tex_img, xi - 0.5f, yi - 0.5f, zi - 0.5f);
// int id = ix + iy * nx + iz * nx * ny; // index for image
// int id2 = iy + ix * ny + iz * nx * ny; // index for DVFs
// float xi = iy + 0.5f + my2[id2];
// float yi = ix + 0.5f + mx2[id2];
// float zi = iz + 0.5f + mz2[id2];
// img1[id2] = tex3D<float>(tex_img, xi, yi, zi);
// img1[id] = 0.0f;
// if (xi < 0.5f || xi >= nx - 0.5f || yi < 0.5f || yi >= ny - 0.5f || zi < 0.5f || zi >= nz - 0.5f)
// return;
// if (xi < 0.5f) {xi = 0.5f;}
// if (xi > nx - 0.5f) {xi = nx - 0.5f;}
// int ix1, ix2, iy1, iy2, iz1, iz2;
// float wx1, wx2, wy1, wy2, wz1, wz2;
// if (xi < 0.5f)
// {ix1 = 0; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else{
// if (xi >= nx - 0.5f)
// {ix1 = nx - 1; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else
// {ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;}
// }
// if (yi < 0.5f)
// {iy1 = 0; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else{
// if (yi >= ny - 0.5f)
// {iy1 = ny - 1; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else
// {iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;}
// }
// if (zi < 0.5f)
// {iz1 = 0; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else{
// if (zi >= nz - 0.5f)
// {iz1 = nz - 1; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else
// {iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2; }
// }
// ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;
// iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;
// iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2;
// img1[id] += img[ix1 + iy1 * nx + iz1 * nx * ny] * wx1 * wy1 * wz1;
// img1[id] += img[ix1 + iy1 * nx + iz2 * nx * ny] * wx1 * wy1 * wz2;
// img1[id] += img[ix1 + iy2 * nx + iz1 * nx * ny] * wx1 * wy2 * wz1;
// img1[id] += img[ix1 + iy2 * nx + iz2 * nx * ny] * wx1 * wy2 * wz2;
// img1[id] += img[ix2 + iy1 * nx + iz1 * nx * ny] * wx2 * wy1 * wz1;
// img1[id] += img[ix2 + iy1 * nx + iz2 * nx * ny] * wx2 * wy1 * wz2;
// img1[id] += img[ix2 + iy2 * nx + iz1 * nx * ny] * wx2 * wy2 * wz1;
// img1[id] += img[ix2 + iy2 * nx + iz2 * nx * ny] * wx2 * wy2 * wz2;
}
// int x = blockSize.x * blockIdx.x + threadIdx.x;
// int y = blockSize.y * blockIdx.y + threadIdx.y;
// int z = blockSize.z * blockIdx.z + threadIdx.z;
// if (x >= nx || y >= ny || z >= nz)
// return;
// int xi = mx2[x][y][z];
// int yi = my2[x][y][z];
// int zi = mz2[x][y][z];
// singleViewImg1[x][y][z] = tex3D<float>(tex_img, xi-0.5f, yi-0.5f, zi-0.5f);
// } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void kernel_deformation(float *img1, hipTextureObject_t tex_img, float *mx2, float *my2, float *mz2, int nx, int ny, int nz){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = iy + ix * ny + iz * nx * ny;
float xi = iy + 1.0f + my2[id];
float yi = ix + 1.0f + mx2[id];
float zi = iz + 1.0f + mz2[id];
img1[id] = tex3D<float>(tex_img, xi - 0.5f, yi - 0.5f, zi - 0.5f);
// int id = ix + iy * nx + iz * nx * ny; // index for image
// int id2 = iy + ix * ny + iz * nx * ny; // index for DVFs
// float xi = iy + 0.5f + my2[id2];
// float yi = ix + 0.5f + mx2[id2];
// float zi = iz + 0.5f + mz2[id2];
// img1[id2] = tex3D<float>(tex_img, xi, yi, zi);
// img1[id] = 0.0f;
// if (xi < 0.5f || xi >= nx - 0.5f || yi < 0.5f || yi >= ny - 0.5f || zi < 0.5f || zi >= nz - 0.5f)
// return;
// if (xi < 0.5f) {xi = 0.5f;}
// if (xi > nx - 0.5f) {xi = nx - 0.5f;}
// int ix1, ix2, iy1, iy2, iz1, iz2;
// float wx1, wx2, wy1, wy2, wz1, wz2;
// if (xi < 0.5f)
// {ix1 = 0; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else{
// if (xi >= nx - 0.5f)
// {ix1 = nx - 1; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else
// {ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;}
// }
// if (yi < 0.5f)
// {iy1 = 0; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else{
// if (yi >= ny - 0.5f)
// {iy1 = ny - 1; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else
// {iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;}
// }
// if (zi < 0.5f)
// {iz1 = 0; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else{
// if (zi >= nz - 0.5f)
// {iz1 = nz - 1; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else
// {iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2; }
// }
// ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;
// iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;
// iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2;
// img1[id] += img[ix1 + iy1 * nx + iz1 * nx * ny] * wx1 * wy1 * wz1;
// img1[id] += img[ix1 + iy1 * nx + iz2 * nx * ny] * wx1 * wy1 * wz2;
// img1[id] += img[ix1 + iy2 * nx + iz1 * nx * ny] * wx1 * wy2 * wz1;
// img1[id] += img[ix1 + iy2 * nx + iz2 * nx * ny] * wx1 * wy2 * wz2;
// img1[id] += img[ix2 + iy1 * nx + iz1 * nx * ny] * wx2 * wy1 * wz1;
// img1[id] += img[ix2 + iy1 * nx + iz2 * nx * ny] * wx2 * wy1 * wz2;
// img1[id] += img[ix2 + iy2 * nx + iz1 * nx * ny] * wx2 * wy2 * wz1;
// img1[id] += img[ix2 + iy2 * nx + iz2 * nx * ny] * wx2 * wy2 * wz2;
}
// int x = blockSize.x * blockIdx.x + threadIdx.x;
// int y = blockSize.y * blockIdx.y + threadIdx.y;
// int z = blockSize.z * blockIdx.z + threadIdx.z;
// if (x >= nx || y >= ny || z >= nz)
// return;
// int xi = mx2[x][y][z];
// int yi = my2[x][y][z];
// int zi = mz2[x][y][z];
// singleViewImg1[x][y][z] = tex3D<float>(tex_img, xi-0.5f, yi-0.5f, zi-0.5f);
// } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.globl _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.p2align 8
.type _Z18kernel_deformationPfP13__hip_textureS_S_S_iii,@function
_Z18kernel_deformationPfP13__hip_textureS_S_S_iii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x30
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v3, v0, 20, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s13, 4, v1
v_lshl_add_u32 v1, s14, 4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v2, s15, 2, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s5, v1
v_cmp_gt_i32_e64 s3, s3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x20
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s5, v[1:2]
s_load_b256 s[4:11], s[0:1], 0x0
v_cvt_f32_i32_e32 v2, v2
v_cvt_f32_i32_e32 v1, v1
v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
global_load_b32 v9, v[5:6], off
v_add_co_u32 v5, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_clause 0x5
s_load_b32 s0, s[6:7], 0x38
s_load_b32 s1, s[6:7], 0x30
s_load_b32 s2, s[6:7], 0x10
s_load_b32 s3, s[6:7], 0x8
s_load_b32 s20, s[6:7], 0x28
s_load_b128 s[8:11], s[6:7], 0x30
v_add_f32_e32 v0, 1.0, v0
s_load_b256 s[12:19], s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s1, 15
s_cselect_b32 s0, -1, 0
s_and_b32 s1, s2, 0x1fff
s_bfe_u32 s2, s3, 0xe000e
s_add_i32 s1, s1, 1
s_add_i32 s2, s2, 1
v_cvt_f32_u32_e32 v7, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 1.0, v7, s0
v_rcp_f32_e32 v8, v7
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, v2, v9
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v5
v_cvt_f32_u32_e32 v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, -0.5, v2 :: v_dual_add_f32 v1, -0.5, v1
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v6 :: v_dual_mul_f32 v7, v2, v7
v_cvt_f32_u32_e32 v6, s20
v_cndmask_b32_e64 v5, 1.0, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f32_e32 v7, v7
v_cndmask_b32_e64 v6, 1.0, v6, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v9, v5
v_dual_add_f32 v0, -0.5, v0 :: v_dual_mul_f32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v6
v_dual_mul_f32 v6, v1, v6 :: v_dual_mul_f32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, v2, v7, vcc_lo
v_floor_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_floor_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v5, v9, v5 :: v_dual_mul_f32 v6, v10, v6
v_dual_cndmask_b32 v7, v0, v5 :: v_dual_cndmask_b32 v6, v1, v6
v_add_co_u32 v0, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
image_sample_lz v2, v[6:8], s[12:19], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_3D
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_deformationPfP13__hip_textureS_S_S_iii, .Lfunc_end0-_Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z18kernel_deformationPfP13__hip_textureS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void kernel_deformation(float *img1, hipTextureObject_t tex_img, float *mx2, float *my2, float *mz2, int nx, int ny, int nz){
int ix = 16 * blockIdx.x + threadIdx.x;
int iy = 16 * blockIdx.y + threadIdx.y;
int iz = 4 * blockIdx.z + threadIdx.z;
if (ix >= nx || iy >= ny || iz >= nz)
return;
int id = iy + ix * ny + iz * nx * ny;
float xi = iy + 1.0f + my2[id];
float yi = ix + 1.0f + mx2[id];
float zi = iz + 1.0f + mz2[id];
img1[id] = tex3D<float>(tex_img, xi - 0.5f, yi - 0.5f, zi - 0.5f);
// int id = ix + iy * nx + iz * nx * ny; // index for image
// int id2 = iy + ix * ny + iz * nx * ny; // index for DVFs
// float xi = iy + 0.5f + my2[id2];
// float yi = ix + 0.5f + mx2[id2];
// float zi = iz + 0.5f + mz2[id2];
// img1[id2] = tex3D<float>(tex_img, xi, yi, zi);
// img1[id] = 0.0f;
// if (xi < 0.5f || xi >= nx - 0.5f || yi < 0.5f || yi >= ny - 0.5f || zi < 0.5f || zi >= nz - 0.5f)
// return;
// if (xi < 0.5f) {xi = 0.5f;}
// if (xi > nx - 0.5f) {xi = nx - 0.5f;}
// int ix1, ix2, iy1, iy2, iz1, iz2;
// float wx1, wx2, wy1, wy2, wz1, wz2;
// if (xi < 0.5f)
// {ix1 = 0; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else{
// if (xi >= nx - 0.5f)
// {ix1 = nx - 1; ix2 = 1; wx2 = 0.0f; wx1 = 1.0f;}
// else
// {ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;}
// }
// if (yi < 0.5f)
// {iy1 = 0; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else{
// if (yi >= ny - 0.5f)
// {iy1 = ny - 1; iy2 = 1; wy2 = 0.0f; wy1 = 1.0f;}
// else
// {iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;}
// }
// if (zi < 0.5f)
// {iz1 = 0; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else{
// if (zi >= nz - 0.5f)
// {iz1 = nz - 1; iz2 = 1; wz2 = 0.0f; wz1 = 1.0f;}
// else
// {iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2; }
// }
// ix1 = (int)floor(xi - 0.5f); ix2 = ix1 + 1; wx2 = xi - 0.5f - (float)ix1; wx1 = 1.0f - wx2;
// iy1 = (int)floor(yi - 0.5f); iy2 = iy1 + 1; wy2 = yi - 0.5f - (float)iy1; wy1 = 1.0f - wy2;
// iz1 = (int)floor(zi - 0.5f); iz2 = iz1 + 1; wz2 = zi - 0.5f - (float)iz1; wz1 = 1.0f - wz2;
// img1[id] += img[ix1 + iy1 * nx + iz1 * nx * ny] * wx1 * wy1 * wz1;
// img1[id] += img[ix1 + iy1 * nx + iz2 * nx * ny] * wx1 * wy1 * wz2;
// img1[id] += img[ix1 + iy2 * nx + iz1 * nx * ny] * wx1 * wy2 * wz1;
// img1[id] += img[ix1 + iy2 * nx + iz2 * nx * ny] * wx1 * wy2 * wz2;
// img1[id] += img[ix2 + iy1 * nx + iz1 * nx * ny] * wx2 * wy1 * wz1;
// img1[id] += img[ix2 + iy1 * nx + iz2 * nx * ny] * wx2 * wy1 * wz2;
// img1[id] += img[ix2 + iy2 * nx + iz1 * nx * ny] * wx2 * wy2 * wz1;
// img1[id] += img[ix2 + iy2 * nx + iz2 * nx * ny] * wx2 * wy2 * wz2;
}
// int x = blockSize.x * blockIdx.x + threadIdx.x;
// int y = blockSize.y * blockIdx.y + threadIdx.y;
// int z = blockSize.z * blockIdx.z + threadIdx.z;
// if (x >= nx || y >= ny || z >= nz)
// return;
// int xi = mx2[x][y][z];
// int yi = my2[x][y][z];
// int zi = mz2[x][y][z];
// singleViewImg1[x][y][z] = tex3D<float>(tex_img, xi-0.5f, yi-0.5f, zi-0.5f);
// } | .text
.file "kernel_deformation.hip"
.globl _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii # -- Begin function _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.p2align 4, 0x90
.type _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii,@function
_Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii: # @_Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kernel_deformationPfP13__hip_textureS_S_S_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii, .Lfunc_end0-_Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_deformationPfP13__hip_textureS_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_deformationPfP13__hip_textureS_S_S_iii,@object # @_Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.section .rodata,"a",@progbits
.globl _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.p2align 3, 0x0
_Z18kernel_deformationPfP13__hip_textureS_S_S_iii:
.quad _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.size _Z18kernel_deformationPfP13__hip_textureS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_deformationPfP13__hip_textureS_S_S_iii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kernel_deformationPfyS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R9, SR_CTAID.Z ; /* 0x0000000000097919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000ea20000002300 */
/*0070*/ LEA R8, R8, R5, 0x4 ; /* 0x0000000508087211 */
/* 0x001fc800078e20ff */
/*0080*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x18c], PT ; /* 0x0000630008007a0c */
/* 0x000fe40003f06270 */
/*0090*/ LEA R0, R0, R3, 0x4 ; /* 0x0000000300007211 */
/* 0x002fc800078e20ff */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x188], P0 ; /* 0x0000620000007a0c */
/* 0x000fe40000706670 */
/*00b0*/ LEA R9, R9, R2, 0x2 ; /* 0x0000000209097211 */
/* 0x004fc800078e10ff */
/*00c0*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x190], P0 ; /* 0x0000640009007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R3, R9, c[0x0][0x188], R0 ; /* 0x0000620009037a24 */
/* 0x000fe200078e0200 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0110*/ IMAD R10, R3, c[0x0][0x18c], R8 ; /* 0x00006300030a7a24 */
/* 0x000fca00078e0208 */
/*0120*/ IMAD.WIDE R4, R10, R17, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fc800078e0211 */
/*0130*/ IMAD.WIDE R2, R10.reuse, R17.reuse, c[0x0][0x178] ; /* 0x00005e000a027625 */
/* 0x0c0fe400078e0211 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.WIDE R6, R10, R17, c[0x0][0x180] ; /* 0x000060000a067625 */
/* 0x000fe400078e0211 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0180*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e300000201400 */
/*0190*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e700000201400 */
/*01a0*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e620000201400 */
/*01b0*/ FADD R12, R0, 1 ; /* 0x3f800000000c7421 */
/* 0x001fe20000000000 */
/*01c0*/ HFMA2.MMA R15, -RZ, RZ, -3, 0 ; /* 0xc2000000ff0f7435 */
/* 0x000fe200000001ff */
/*01d0*/ FADD R11, R8, 1 ; /* 0x3f800000080b7421 */
/* 0x002fc40000000000 */
/*01e0*/ FADD R13, R9, 1 ; /* 0x3f800000090d7421 */
/* 0x000fe40000000000 */
/*01f0*/ FADD R12, R12, R5 ; /* 0x000000050c0c7221 */
/* 0x004fe40000000000 */
/*0200*/ FADD R11, R11, R2 ; /* 0x000000020b0b7221 */
/* 0x008fe40000000000 */
/*0210*/ FADD R5, R12, -0.5 ; /* 0xbf0000000c057421 */
/* 0x000fe40000000000 */
/*0220*/ FADD R13, R13, R6 ; /* 0x000000060d0d7221 */
/* 0x010fe40000000000 */
/*0230*/ FADD R4, R11, -0.5 ; /* 0xbf0000000b047421 */
/* 0x000fc40000000000 */
/*0240*/ FADD R14, R13, -0.5 ; /* 0xbf0000000d0e7421 */
/* 0x000fc80000000000 */
/*0250*/ TEX.SCR.LL RZ, R5, R4, R14, 0x0, 0x5a, 3D, 0x1 ; /* 0x50005a0e04057b60 */
/* 0x000f4200019e01ff */
/*0260*/ IMAD.WIDE R2, R10, R17, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0211 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.globl _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.p2align 8
.type _Z18kernel_deformationPfP13__hip_textureS_S_S_iii,@function
_Z18kernel_deformationPfP13__hip_textureS_S_S_iii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x30
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v3, v0, 20, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s13, 4, v1
v_lshl_add_u32 v1, s14, 4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v2, s15, 2, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s5, v1
v_cmp_gt_i32_e64 s3, s3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x20
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s5, v[1:2]
s_load_b256 s[4:11], s[0:1], 0x0
v_cvt_f32_i32_e32 v2, v2
v_cvt_f32_i32_e32 v1, v1
v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
global_load_b32 v9, v[5:6], off
v_add_co_u32 v5, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_clause 0x5
s_load_b32 s0, s[6:7], 0x38
s_load_b32 s1, s[6:7], 0x30
s_load_b32 s2, s[6:7], 0x10
s_load_b32 s3, s[6:7], 0x8
s_load_b32 s20, s[6:7], 0x28
s_load_b128 s[8:11], s[6:7], 0x30
v_add_f32_e32 v0, 1.0, v0
s_load_b256 s[12:19], s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s1, 15
s_cselect_b32 s0, -1, 0
s_and_b32 s1, s2, 0x1fff
s_bfe_u32 s2, s3, 0xe000e
s_add_i32 s1, s1, 1
s_add_i32 s2, s2, 1
v_cvt_f32_u32_e32 v7, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 1.0, v7, s0
v_rcp_f32_e32 v8, v7
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, v2, v9
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v5
v_cvt_f32_u32_e32 v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, -0.5, v2 :: v_dual_add_f32 v1, -0.5, v1
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v6 :: v_dual_mul_f32 v7, v2, v7
v_cvt_f32_u32_e32 v6, s20
v_cndmask_b32_e64 v5, 1.0, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_floor_f32_e32 v7, v7
v_cndmask_b32_e64 v6, 1.0, v6, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v9, v5
v_dual_add_f32 v0, -0.5, v0 :: v_dual_mul_f32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v6
v_dual_mul_f32 v6, v1, v6 :: v_dual_mul_f32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, v2, v7, vcc_lo
v_floor_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_floor_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v5, v9, v5 :: v_dual_mul_f32 v6, v10, v6
v_dual_cndmask_b32 v7, v0, v5 :: v_dual_cndmask_b32 v6, v1, v6
v_add_co_u32 v0, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
image_sample_lz v2, v[6:8], s[12:19], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_3D
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_deformationPfP13__hip_textureS_S_S_iii, .Lfunc_end0-_Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z18kernel_deformationPfP13__hip_textureS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00125ba2_00000000-6_kernel_deformation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii
.type _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii, @function
_Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kernel_deformationPfyS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii, .-_Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii
.globl _Z18kernel_deformationPfyS_S_S_iii
.type _Z18kernel_deformationPfyS_S_S_iii, @function
_Z18kernel_deformationPfyS_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z18kernel_deformationPfyS_S_S_iiiPfyS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_deformationPfyS_S_S_iii, .-_Z18kernel_deformationPfyS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kernel_deformationPfyS_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_deformationPfyS_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_deformation.hip"
.globl _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii # -- Begin function _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.p2align 4, 0x90
.type _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii,@function
_Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii: # @_Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kernel_deformationPfP13__hip_textureS_S_S_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii, .Lfunc_end0-_Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_deformationPfP13__hip_textureS_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_deformationPfP13__hip_textureS_S_S_iii,@object # @_Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.section .rodata,"a",@progbits
.globl _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.p2align 3, 0x0
_Z18kernel_deformationPfP13__hip_textureS_S_S_iii:
.quad _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.size _Z18kernel_deformationPfP13__hip_textureS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_deformationPfP13__hip_textureS_S_S_iii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_deformationPfP13__hip_textureS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_deformationPfP13__hip_textureS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
__global__
void bw(int n, float c, float *x, float *y){
int j = blockIdx.x;
if (j < n) y[j] = x[j] + c*y[j];
}
int main(void){
float *x, *y, *dev_x, *dev_y;
int N = 1<<10;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
cudaMalloc(&dev_x, N*sizeof(float));
cudaMalloc(&dev_y, N*sizeof(float));
for (int j = 0; j < N; j++) {
x[j] = 4.0f;
y[j] = 1.0f;
}
cudaMemcpy(dev_x, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_y, y, N*sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start1, stop1;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventRecord(start1);
bw<<<(N+447)/448,448>>>(N, 2.0f, dev_x, dev_y);
cudaEventRecord(stop1);
cudaEventSynchronize(stop1);
float time = 0;
cudaEventElapsedTime(&time, start1, stop1);
// N*4 number of bytes transferred r/w
// 3 = rx + ry + wy
printf("Bandwidth(GB/s): %f \n", N*4*3/time/1e6);
cudaFree(dev_x);
cudaFree(dev_y);
} | code for sm_80
Function : _Z2bwifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FFMA R7, R0, c[0x0][0x164], R3 ; /* 0x0000590000077a23 */
/* 0x004fca0000000003 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
__global__
void bw(int n, float c, float *x, float *y){
int j = blockIdx.x;
if (j < n) y[j] = x[j] + c*y[j];
}
int main(void){
float *x, *y, *dev_x, *dev_y;
int N = 1<<10;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
cudaMalloc(&dev_x, N*sizeof(float));
cudaMalloc(&dev_y, N*sizeof(float));
for (int j = 0; j < N; j++) {
x[j] = 4.0f;
y[j] = 1.0f;
}
cudaMemcpy(dev_x, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_y, y, N*sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start1, stop1;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventRecord(start1);
bw<<<(N+447)/448,448>>>(N, 2.0f, dev_x, dev_y);
cudaEventRecord(stop1);
cudaEventSynchronize(stop1);
float time = 0;
cudaEventElapsedTime(&time, start1, stop1);
// N*4 number of bytes transferred r/w
// 3 = rx + ry + wy
printf("Bandwidth(GB/s): %f \n", N*4*3/time/1e6);
cudaFree(dev_x);
cudaFree(dev_y);
} | .file "tmpxft_0002e9ab_00000000-6_gpuKB.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2bwifPfS_ifPfS_
.type _Z25__device_stub__Z2bwifPfS_ifPfS_, @function
_Z25__device_stub__Z2bwifPfS_ifPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2bwifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z2bwifPfS_ifPfS_, .-_Z25__device_stub__Z2bwifPfS_ifPfS_
.globl _Z2bwifPfS_
.type _Z2bwifPfS_, @function
_Z2bwifPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2bwifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2bwifPfS_, .-_Z2bwifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Bandwidth(GB/s): %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L12
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $448, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss .LC4(%rip), %xmm0
divss 44(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC2(%rip), %xmm0
movl $1024, %edi
call _Z25__device_stub__Z2bwifPfS_ifPfS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z2bwifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z2bwifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1082130432
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC4:
.long 1178599424
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
__global__
void bw(int n, float c, float *x, float *y){
int j = blockIdx.x;
if (j < n) y[j] = x[j] + c*y[j];
}
int main(void){
float *x, *y, *dev_x, *dev_y;
int N = 1<<10;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
cudaMalloc(&dev_x, N*sizeof(float));
cudaMalloc(&dev_y, N*sizeof(float));
for (int j = 0; j < N; j++) {
x[j] = 4.0f;
y[j] = 1.0f;
}
cudaMemcpy(dev_x, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_y, y, N*sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start1, stop1;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventRecord(start1);
bw<<<(N+447)/448,448>>>(N, 2.0f, dev_x, dev_y);
cudaEventRecord(stop1);
cudaEventSynchronize(stop1);
float time = 0;
cudaEventElapsedTime(&time, start1, stop1);
// N*4 number of bytes transferred r/w
// 3 = rx + ry + wy
printf("Bandwidth(GB/s): %f \n", N*4*3/time/1e6);
cudaFree(dev_x);
cudaFree(dev_y);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
__global__
void bw(int n, float c, float *x, float *y){
int j = blockIdx.x;
if (j < n) y[j] = x[j] + c*y[j];
}
int main(void){
float *x, *y, *dev_x, *dev_y;
int N = 1<<10;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
hipMalloc(&dev_x, N*sizeof(float));
hipMalloc(&dev_y, N*sizeof(float));
for (int j = 0; j < N; j++) {
x[j] = 4.0f;
y[j] = 1.0f;
}
hipMemcpy(dev_x, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_y, y, N*sizeof(float), hipMemcpyHostToDevice);
hipEvent_t start1, stop1;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventRecord(start1);
bw<<<(N+447)/448,448>>>(N, 2.0f, dev_x, dev_y);
hipEventRecord(stop1);
hipEventSynchronize(stop1);
float time = 0;
hipEventElapsedTime(&time, start1, stop1);
// N*4 number of bytes transferred r/w
// 3 = rx + ry + wy
printf("Bandwidth(GB/s): %f \n", N*4*3/time/1e6);
hipFree(dev_x);
hipFree(dev_y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
__global__
void bw(int n, float c, float *x, float *y){
int j = blockIdx.x;
if (j < n) y[j] = x[j] + c*y[j];
}
int main(void){
float *x, *y, *dev_x, *dev_y;
int N = 1<<10;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
hipMalloc(&dev_x, N*sizeof(float));
hipMalloc(&dev_y, N*sizeof(float));
for (int j = 0; j < N; j++) {
x[j] = 4.0f;
y[j] = 1.0f;
}
hipMemcpy(dev_x, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_y, y, N*sizeof(float), hipMemcpyHostToDevice);
hipEvent_t start1, stop1;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventRecord(start1);
bw<<<(N+447)/448,448>>>(N, 2.0f, dev_x, dev_y);
hipEventRecord(stop1);
hipEventSynchronize(stop1);
float time = 0;
hipEventElapsedTime(&time, start1, stop1);
// N*4 number of bytes transferred r/w
// 3 = rx + ry + wy
printf("Bandwidth(GB/s): %f \n", N*4*3/time/1e6);
hipFree(dev_x);
hipFree(dev_y);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2bwifPfS_
.globl _Z2bwifPfS_
.p2align 8
.type _Z2bwifPfS_,@function
_Z2bwifPfS_:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s2, s6, s2
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s7, s3
s_load_b32 s0, s[0:1], 0x4
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e64 v0, s1, s0
global_store_b32 v1, v0, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2bwifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2bwifPfS_, .Lfunc_end0-_Z2bwifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2bwifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z2bwifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
__global__
void bw(int n, float c, float *x, float *y){
int j = blockIdx.x;
if (j < n) y[j] = x[j] + c*y[j];
}
int main(void){
float *x, *y, *dev_x, *dev_y;
int N = 1<<10;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
hipMalloc(&dev_x, N*sizeof(float));
hipMalloc(&dev_y, N*sizeof(float));
for (int j = 0; j < N; j++) {
x[j] = 4.0f;
y[j] = 1.0f;
}
hipMemcpy(dev_x, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_y, y, N*sizeof(float), hipMemcpyHostToDevice);
hipEvent_t start1, stop1;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventRecord(start1);
bw<<<(N+447)/448,448>>>(N, 2.0f, dev_x, dev_y);
hipEventRecord(stop1);
hipEventSynchronize(stop1);
float time = 0;
hipEventElapsedTime(&time, start1, stop1);
// N*4 number of bytes transferred r/w
// 3 = rx + ry + wy
printf("Bandwidth(GB/s): %f \n", N*4*3/time/1e6);
hipFree(dev_x);
hipFree(dev_y);
} | .text
.file "gpuKB.hip"
.globl _Z17__device_stub__bwifPfS_ # -- Begin function _Z17__device_stub__bwifPfS_
.p2align 4, 0x90
.type _Z17__device_stub__bwifPfS_,@function
_Z17__device_stub__bwifPfS_: # @_Z17__device_stub__bwifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2bwifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z17__device_stub__bwifPfS_, .Lfunc_end0-_Z17__device_stub__bwifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x46400000 # float 12288
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1082130432, (%r14,%rax,4) # imm = 0x40800000
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 445(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl $1024, 36(%rsp) # imm = 0x400
movl $1073741824, 32(%rsp) # imm = 0x40000000
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 48(%rsp)
leaq 32(%rsp), %rax
movq %rax, 56(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2bwifPfS_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 48(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2bwifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2bwifPfS_,@object # @_Z2bwifPfS_
.section .rodata,"a",@progbits
.globl _Z2bwifPfS_
.p2align 3, 0x0
_Z2bwifPfS_:
.quad _Z17__device_stub__bwifPfS_
.size _Z2bwifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Bandwidth(GB/s): %f \n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2bwifPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__bwifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2bwifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2bwifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FFMA R7, R0, c[0x0][0x164], R3 ; /* 0x0000590000077a23 */
/* 0x004fca0000000003 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2bwifPfS_
.globl _Z2bwifPfS_
.p2align 8
.type _Z2bwifPfS_,@function
_Z2bwifPfS_:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s2, s6, s2
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s7, s3
s_load_b32 s0, s[0:1], 0x4
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e64 v0, s1, s0
global_store_b32 v1, v0, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2bwifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2bwifPfS_, .Lfunc_end0-_Z2bwifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2bwifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z2bwifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002e9ab_00000000-6_gpuKB.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2bwifPfS_ifPfS_
.type _Z25__device_stub__Z2bwifPfS_ifPfS_, @function
_Z25__device_stub__Z2bwifPfS_ifPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2bwifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z2bwifPfS_ifPfS_, .-_Z25__device_stub__Z2bwifPfS_ifPfS_
.globl _Z2bwifPfS_
.type _Z2bwifPfS_, @function
_Z2bwifPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2bwifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2bwifPfS_, .-_Z2bwifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Bandwidth(GB/s): %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L12
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $448, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss .LC4(%rip), %xmm0
divss 44(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC2(%rip), %xmm0
movl $1024, %edi
call _Z25__device_stub__Z2bwifPfS_ifPfS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z2bwifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z2bwifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1082130432
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC4:
.long 1178599424
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpuKB.hip"
.globl _Z17__device_stub__bwifPfS_ # -- Begin function _Z17__device_stub__bwifPfS_
.p2align 4, 0x90
.type _Z17__device_stub__bwifPfS_,@function
_Z17__device_stub__bwifPfS_: # @_Z17__device_stub__bwifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2bwifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z17__device_stub__bwifPfS_, .Lfunc_end0-_Z17__device_stub__bwifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x46400000 # float 12288
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1082130432, (%r14,%rax,4) # imm = 0x40800000
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 445(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl $1024, 36(%rsp) # imm = 0x400
movl $1073741824, 32(%rsp) # imm = 0x40000000
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 48(%rsp)
leaq 32(%rsp), %rax
movq %rax, 56(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2bwifPfS_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 48(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2bwifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2bwifPfS_,@object # @_Z2bwifPfS_
.section .rodata,"a",@progbits
.globl _Z2bwifPfS_
.p2align 3, 0x0
_Z2bwifPfS_:
.quad _Z17__device_stub__bwifPfS_
.size _Z2bwifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Bandwidth(GB/s): %f \n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2bwifPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__bwifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2bwifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include "stdlib.h"
#include "stdio.h"
#include <iostream>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <ctime>
using namespace std;
__global__ void sum_cuda(int *res, int *mas1, int *mas2, int N, int M)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
int tx = i * N + j;
res[tx] = mas1[tx] + mas2[tx];
}
void init(int *mas, int size);
void sum(int *res, int *mas1, int *mas2, int N, int M);
void print(int *mas, int N, int M);
int main()
{
int N = 4, M = 4, dimN = 2, dimM = 2;
int mas1[N * M];
init(mas1, N * M);
int mas2[N * M];
init(mas2, N*M);
int *res = new int[N * M];
int *cudaMas1;
int *cudaMas2;
int *cudaRes;
float time = 0;
cudaMalloc((void**)&cudaMas1, sizeof(int) * N * M);
cudaMalloc((void**)&cudaMas2, sizeof(int) * N * M);
cudaMalloc((void**)&cudaRes, sizeof(int) * N * M);
cudaMemcpy(cudaMas1, mas1, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(cudaMas2, mas2, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(cudaRes, res, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
print(mas1, N, M);
print(mas2, N, M);
cudaEventRecord(start);
sum(res, mas1, mas2, N, M);
cudaEventRecord(end);
cudaEventSynchronize(end);
print(res, N, M);
cudaEventElapsedTime(&time, start, end);
cout << "Последовательно " << time << endl;
dim3 blocks(N / dimN, M / dimM);
dim3 threads(dimN, dimM);
cudaEventRecord(start);
sum_cuda<<< blocks, threads >>>(cudaRes, cudaMas1, cudaMas2, N, M);
cudaDeviceSynchronize();
cudaEventRecord(end);
cudaMemcpy(res, cudaRes, sizeof(int) * N * M, cudaMemcpyDeviceToHost);
print(res, N, M);
cudaEventElapsedTime(&time, start, end);
cout << "Параллельно " << time << endl;
cudaFree(cudaMas1);
cudaFree(cudaMas2);
cudaFree(cudaRes);
return 0;
}
void sum(int *res, int *mas1, int *mas2, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
res[i*N + j] = mas1[i*N + j] + mas2[i*N + j];
}
}
void print(int *mas, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
cout << mas[i*N + j] << " ";
cout << endl;
}
cout << endl;
}
void init(int *mas, int size)
{
srand( time(0));
for (int i = 0; i < size; i++)
{
mas[i] = rand() % 1000;
}
} | code for sm_80
Function : _Z8sum_cudaPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "stdlib.h"
#include "stdio.h"
#include <iostream>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <ctime>
using namespace std;
__global__ void sum_cuda(int *res, int *mas1, int *mas2, int N, int M)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
int tx = i * N + j;
res[tx] = mas1[tx] + mas2[tx];
}
void init(int *mas, int size);
void sum(int *res, int *mas1, int *mas2, int N, int M);
void print(int *mas, int N, int M);
int main()
{
int N = 4, M = 4, dimN = 2, dimM = 2;
int mas1[N * M];
init(mas1, N * M);
int mas2[N * M];
init(mas2, N*M);
int *res = new int[N * M];
int *cudaMas1;
int *cudaMas2;
int *cudaRes;
float time = 0;
cudaMalloc((void**)&cudaMas1, sizeof(int) * N * M);
cudaMalloc((void**)&cudaMas2, sizeof(int) * N * M);
cudaMalloc((void**)&cudaRes, sizeof(int) * N * M);
cudaMemcpy(cudaMas1, mas1, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(cudaMas2, mas2, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(cudaRes, res, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
print(mas1, N, M);
print(mas2, N, M);
cudaEventRecord(start);
sum(res, mas1, mas2, N, M);
cudaEventRecord(end);
cudaEventSynchronize(end);
print(res, N, M);
cudaEventElapsedTime(&time, start, end);
cout << "Последовательно " << time << endl;
dim3 blocks(N / dimN, M / dimM);
dim3 threads(dimN, dimM);
cudaEventRecord(start);
sum_cuda<<< blocks, threads >>>(cudaRes, cudaMas1, cudaMas2, N, M);
cudaDeviceSynchronize();
cudaEventRecord(end);
cudaMemcpy(res, cudaRes, sizeof(int) * N * M, cudaMemcpyDeviceToHost);
print(res, N, M);
cudaEventElapsedTime(&time, start, end);
cout << "Параллельно " << time << endl;
cudaFree(cudaMas1);
cudaFree(cudaMas2);
cudaFree(cudaRes);
return 0;
}
void sum(int *res, int *mas1, int *mas2, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
res[i*N + j] = mas1[i*N + j] + mas2[i*N + j];
}
}
void print(int *mas, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
cout << mas[i*N + j] << " ";
cout << endl;
}
cout << endl;
}
void init(int *mas, int size)
{
srand( time(0));
for (int i = 0; i < size; i++)
{
mas[i] = rand() % 1000;
}
} | .file "tmpxft_0012e777_00000000-6_matrix-sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3sumPiS_S_ii
.type _Z3sumPiS_S_ii, @function
_Z3sumPiS_S_ii:
.LFB3670:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdx, %r9
movl %ecx, %ebx
movl $0, %r11d
movl $0, %r10d
movslq %r8d, %rbp
jmp .L5
.L7:
movslq %r11d, %rcx
leaq 0(,%rcx,4), %rax
addq %rbp, %rcx
salq $2, %rcx
.L6:
movl (%r9,%rax), %edx
addl (%rsi,%rax), %edx
movl %edx, (%rdi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r10d
addl %ebx, %r11d
cmpl %r10d, %ebx
je .L3
.L5:
testl %r8d, %r8d
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3670:
.size _Z3sumPiS_S_ii, .-_Z3sumPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z5printPiii
.type _Z5printPiii, @function
_Z5printPiii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
testl %esi, %esi
jle .L15
movl $0, %r15d
movl $0, %r14d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L16
.L28:
call _ZSt16__throw_bad_castv@PLT
.L19:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, %eax
je .L15
.L16:
cmpl $0, 12(%rsp)
jle .L22
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %r12
.L17:
movl (%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
.L22:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L28
cmpb $0, 56(%rbx)
je .L19
movzbl 67(%rbx), %esi
jmp .L20
.L15:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L29
cmpb $0, 56(%rbx)
je .L24
movzbl 67(%rbx), %eax
.L25:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L24:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L25
.cfi_endproc
.LFE3671:
.size _Z5printPiii, .-_Z5printPiii
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB3672:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L30
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %rbp
.L32:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
.L30:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z4initPii, .-_Z4initPii
.globl _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
.type _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii, @function
_Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8sum_cudaPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii, .-_Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
.globl _Z8sum_cudaPiS_S_ii
.type _Z8sum_cudaPiS_S_ii, @function
_Z8sum_cudaPiS_S_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z8sum_cudaPiS_S_ii, .-_Z8sum_cudaPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\320\237\320\276\321\201\320\273\320\265\320\264\320\276\320\262\320\260\321\202\320\265\320\273\321\214\320\275\320\276 "
.section .rodata.str1.1
.LC3:
.string "\320\237\320\260\321\200\320\260\320\273\320\273\320\265\320\273\321\214\320\275\320\276 "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $224, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbp
movl $16, %esi
movq %rbp, %rdi
call _Z4initPii
leaq 144(%rsp), %r12
movl $16, %esi
movq %r12, %rdi
call _Z4initPii
movl $64, %edi
call _Znam@PLT
movq %rax, %rbx
movl $0x00000000, 12(%rsp)
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $4, %edx
movl $4, %esi
movq %rbp, %rdi
call _Z5printPiii
movl $4, %edx
movl $4, %esi
movq %r12, %rdi
call _Z5printPiii
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, %r8d
movl $4, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z3sumPiS_S_ii
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z5printPiii
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, 56(%rsp)
movl $2, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 68(%rsp)
movl $2, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L44:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $64, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z5printPiii
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl $4, %r8d
movl $4, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
jmp .L44
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z8sum_cudaPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sum_cudaPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "stdlib.h"
#include "stdio.h"
#include <iostream>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <ctime>
using namespace std;
__global__ void sum_cuda(int *res, int *mas1, int *mas2, int N, int M)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
int tx = i * N + j;
res[tx] = mas1[tx] + mas2[tx];
}
void init(int *mas, int size);
void sum(int *res, int *mas1, int *mas2, int N, int M);
void print(int *mas, int N, int M);
int main()
{
int N = 4, M = 4, dimN = 2, dimM = 2;
int mas1[N * M];
init(mas1, N * M);
int mas2[N * M];
init(mas2, N*M);
int *res = new int[N * M];
int *cudaMas1;
int *cudaMas2;
int *cudaRes;
float time = 0;
cudaMalloc((void**)&cudaMas1, sizeof(int) * N * M);
cudaMalloc((void**)&cudaMas2, sizeof(int) * N * M);
cudaMalloc((void**)&cudaRes, sizeof(int) * N * M);
cudaMemcpy(cudaMas1, mas1, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(cudaMas2, mas2, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaMemcpy(cudaRes, res, sizeof(int) * N * M, cudaMemcpyHostToDevice);
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
print(mas1, N, M);
print(mas2, N, M);
cudaEventRecord(start);
sum(res, mas1, mas2, N, M);
cudaEventRecord(end);
cudaEventSynchronize(end);
print(res, N, M);
cudaEventElapsedTime(&time, start, end);
cout << "Последовательно " << time << endl;
dim3 blocks(N / dimN, M / dimM);
dim3 threads(dimN, dimM);
cudaEventRecord(start);
sum_cuda<<< blocks, threads >>>(cudaRes, cudaMas1, cudaMas2, N, M);
cudaDeviceSynchronize();
cudaEventRecord(end);
cudaMemcpy(res, cudaRes, sizeof(int) * N * M, cudaMemcpyDeviceToHost);
print(res, N, M);
cudaEventElapsedTime(&time, start, end);
cout << "Параллельно " << time << endl;
cudaFree(cudaMas1);
cudaFree(cudaMas2);
cudaFree(cudaRes);
return 0;
}
void sum(int *res, int *mas1, int *mas2, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
res[i*N + j] = mas1[i*N + j] + mas2[i*N + j];
}
}
void print(int *mas, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
cout << mas[i*N + j] << " ";
cout << endl;
}
cout << endl;
}
void init(int *mas, int size)
{
srand( time(0));
for (int i = 0; i < size; i++)
{
mas[i] = rand() % 1000;
}
} | #include "hip/hip_runtime.h"
#include "stdlib.h"
#include "stdio.h"
#include <iostream>
#include <ctime>
using namespace std;
__global__ void sum_cuda(int *res, int *mas1, int *mas2, int N, int M)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
int tx = i * N + j;
res[tx] = mas1[tx] + mas2[tx];
}
void init(int *mas, int size);
void sum(int *res, int *mas1, int *mas2, int N, int M);
void print(int *mas, int N, int M);
int main()
{
int N = 4, M = 4, dimN = 2, dimM = 2;
int mas1[N * M];
init(mas1, N * M);
int mas2[N * M];
init(mas2, N*M);
int *res = new int[N * M];
int *cudaMas1;
int *cudaMas2;
int *cudaRes;
float time = 0;
hipMalloc((void**)&cudaMas1, sizeof(int) * N * M);
hipMalloc((void**)&cudaMas2, sizeof(int) * N * M);
hipMalloc((void**)&cudaRes, sizeof(int) * N * M);
hipMemcpy(cudaMas1, mas1, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipMemcpy(cudaMas2, mas2, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipMemcpy(cudaRes, res, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
print(mas1, N, M);
print(mas2, N, M);
hipEventRecord(start);
sum(res, mas1, mas2, N, M);
hipEventRecord(end);
hipEventSynchronize(end);
print(res, N, M);
hipEventElapsedTime(&time, start, end);
cout << "Последовательно " << time << endl;
dim3 blocks(N / dimN, M / dimM);
dim3 threads(dimN, dimM);
hipEventRecord(start);
sum_cuda<<< blocks, threads >>>(cudaRes, cudaMas1, cudaMas2, N, M);
hipDeviceSynchronize();
hipEventRecord(end);
hipMemcpy(res, cudaRes, sizeof(int) * N * M, hipMemcpyDeviceToHost);
print(res, N, M);
hipEventElapsedTime(&time, start, end);
cout << "Параллельно " << time << endl;
hipFree(cudaMas1);
hipFree(cudaMas2);
hipFree(cudaRes);
return 0;
}
void sum(int *res, int *mas1, int *mas2, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
res[i*N + j] = mas1[i*N + j] + mas2[i*N + j];
}
}
void print(int *mas, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
cout << mas[i*N + j] << " ";
cout << endl;
}
cout << endl;
}
void init(int *mas, int size)
{
srand( time(0));
for (int i = 0; i < size; i++)
{
mas[i] = rand() % 1000;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "stdlib.h"
#include "stdio.h"
#include <iostream>
#include <ctime>
using namespace std;
__global__ void sum_cuda(int *res, int *mas1, int *mas2, int N, int M)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
int tx = i * N + j;
res[tx] = mas1[tx] + mas2[tx];
}
void init(int *mas, int size);
void sum(int *res, int *mas1, int *mas2, int N, int M);
void print(int *mas, int N, int M);
int main()
{
int N = 4, M = 4, dimN = 2, dimM = 2;
int mas1[N * M];
init(mas1, N * M);
int mas2[N * M];
init(mas2, N*M);
int *res = new int[N * M];
int *cudaMas1;
int *cudaMas2;
int *cudaRes;
float time = 0;
hipMalloc((void**)&cudaMas1, sizeof(int) * N * M);
hipMalloc((void**)&cudaMas2, sizeof(int) * N * M);
hipMalloc((void**)&cudaRes, sizeof(int) * N * M);
hipMemcpy(cudaMas1, mas1, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipMemcpy(cudaMas2, mas2, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipMemcpy(cudaRes, res, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
print(mas1, N, M);
print(mas2, N, M);
hipEventRecord(start);
sum(res, mas1, mas2, N, M);
hipEventRecord(end);
hipEventSynchronize(end);
print(res, N, M);
hipEventElapsedTime(&time, start, end);
cout << "Последовательно " << time << endl;
dim3 blocks(N / dimN, M / dimM);
dim3 threads(dimN, dimM);
hipEventRecord(start);
sum_cuda<<< blocks, threads >>>(cudaRes, cudaMas1, cudaMas2, N, M);
hipDeviceSynchronize();
hipEventRecord(end);
hipMemcpy(res, cudaRes, sizeof(int) * N * M, hipMemcpyDeviceToHost);
print(res, N, M);
hipEventElapsedTime(&time, start, end);
cout << "Параллельно " << time << endl;
hipFree(cudaMas1);
hipFree(cudaMas2);
hipFree(cudaRes);
return 0;
}
void sum(int *res, int *mas1, int *mas2, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
res[i*N + j] = mas1[i*N + j] + mas2[i*N + j];
}
}
void print(int *mas, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
cout << mas[i*N + j] << " ";
cout << endl;
}
cout << endl;
}
void init(int *mas, int size)
{
srand( time(0));
for (int i = 0; i < size; i++)
{
mas[i] = rand() % 1000;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8sum_cudaPiS_S_ii
.globl _Z8sum_cudaPiS_S_ii
.p2align 8
.type _Z8sum_cudaPiS_S_ii,@function
_Z8sum_cudaPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s15, s15, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s15, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8sum_cudaPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8sum_cudaPiS_S_ii, .Lfunc_end0-_Z8sum_cudaPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8sum_cudaPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8sum_cudaPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "stdlib.h"
#include "stdio.h"
#include <iostream>
#include <ctime>
using namespace std;
__global__ void sum_cuda(int *res, int *mas1, int *mas2, int N, int M)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
int tx = i * N + j;
res[tx] = mas1[tx] + mas2[tx];
}
void init(int *mas, int size);
void sum(int *res, int *mas1, int *mas2, int N, int M);
void print(int *mas, int N, int M);
int main()
{
int N = 4, M = 4, dimN = 2, dimM = 2;
int mas1[N * M];
init(mas1, N * M);
int mas2[N * M];
init(mas2, N*M);
int *res = new int[N * M];
int *cudaMas1;
int *cudaMas2;
int *cudaRes;
float time = 0;
hipMalloc((void**)&cudaMas1, sizeof(int) * N * M);
hipMalloc((void**)&cudaMas2, sizeof(int) * N * M);
hipMalloc((void**)&cudaRes, sizeof(int) * N * M);
hipMemcpy(cudaMas1, mas1, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipMemcpy(cudaMas2, mas2, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipMemcpy(cudaRes, res, sizeof(int) * N * M, hipMemcpyHostToDevice);
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
print(mas1, N, M);
print(mas2, N, M);
hipEventRecord(start);
sum(res, mas1, mas2, N, M);
hipEventRecord(end);
hipEventSynchronize(end);
print(res, N, M);
hipEventElapsedTime(&time, start, end);
cout << "Последовательно " << time << endl;
dim3 blocks(N / dimN, M / dimM);
dim3 threads(dimN, dimM);
hipEventRecord(start);
sum_cuda<<< blocks, threads >>>(cudaRes, cudaMas1, cudaMas2, N, M);
hipDeviceSynchronize();
hipEventRecord(end);
hipMemcpy(res, cudaRes, sizeof(int) * N * M, hipMemcpyDeviceToHost);
print(res, N, M);
hipEventElapsedTime(&time, start, end);
cout << "Параллельно " << time << endl;
hipFree(cudaMas1);
hipFree(cudaMas2);
hipFree(cudaRes);
return 0;
}
void sum(int *res, int *mas1, int *mas2, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
res[i*N + j] = mas1[i*N + j] + mas2[i*N + j];
}
}
void print(int *mas, int N, int M)
{
for (int i = 0; i < N; i++){
for (int j = 0; j < M; j++)
cout << mas[i*N + j] << " ";
cout << endl;
}
cout << endl;
}
void init(int *mas, int size)
{
srand( time(0));
for (int i = 0; i < size; i++)
{
mas[i] = rand() % 1000;
}
} | .text
.file "matrix-sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__sum_cudaPiS_S_ii # -- Begin function _Z23__device_stub__sum_cudaPiS_S_ii
.p2align 4, 0x90
.type _Z23__device_stub__sum_cudaPiS_S_ii,@function
_Z23__device_stub__sum_cudaPiS_S_ii: # @_Z23__device_stub__sum_cudaPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8sum_cudaPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__sum_cudaPiS_S_ii, .Lfunc_end0-_Z23__device_stub__sum_cudaPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $240, %rsp
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, -272(%rbp,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2: # %_Z4initPii.exit
movq %rsp, %r14
addq $-64, %r14
movq %r14, %rsp
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i54
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB1_3
# %bb.4: # %_Z4initPii.exit58
movl $64, %edi
callq _Znam
movq %rax, %rbx
movl $0, -36(%rbp)
leaq -80(%rbp), %rdi
movl $64, %esi
callq hipMalloc
leaq -72(%rbp), %rdi
movl $64, %esi
callq hipMalloc
leaq -64(%rbp), %rdi
movl $64, %esi
callq hipMalloc
movq -80(%rbp), %rdi
leaq -272(%rbp), %r15
movl $64, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq -72(%rbp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq -56(%rbp), %rdi
callq hipEventCreate
leaq -48(%rbp), %rdi
callq hipEventCreate
movq %r15, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq %r14, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq -56(%rbp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rax
.p2align 4, 0x90
.LBB1_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rcx,4), %edx
addl (%r15,%rcx,4), %edx
movl %edx, (%rax,%rcx,4)
incq %rcx
cmpq $4, %rcx
jne .LBB1_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB1_5 Depth=1
incq %r12
addq $16, %rax
addq $16, %r14
addq $16, %r15
cmpq $4, %r12
jne .LBB1_5
# %bb.8: # %_Z3sumPiS_S_ii.exit
movq -48(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -48(%rbp), %rdi
callq hipEventSynchronize
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq -56(%rbp), %rsi
movq -48(%rbp), %rdx
leaq -36(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -36(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_19
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -56(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq -64(%rbp), %rax
movq -80(%rbp), %rcx
movq -72(%rbp), %rdx
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
movq %rdx, -144(%rbp)
movl $4, -88(%rbp)
movl $4, -84(%rbp)
leaq -160(%rbp), %rax
movq %rax, -208(%rbp)
leaq -152(%rbp), %rax
movq %rax, -200(%rbp)
leaq -144(%rbp), %rax
movq %rax, -192(%rbp)
leaq -88(%rbp), %rax
movq %rax, -184(%rbp)
leaq -84(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rdi
leaq -120(%rbp), %rsi
leaq -104(%rbp), %rdx
leaq -96(%rbp), %rcx
callq __hipPopCallConfiguration
movq -136(%rbp), %rsi
movl -128(%rbp), %edx
movq -120(%rbp), %rcx
movl -112(%rbp), %r8d
leaq -208(%rbp), %r9
movl $_Z8sum_cudaPiS_S_ii, %edi
pushq -96(%rbp)
pushq -104(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_14:
callq hipDeviceSynchronize
movq -48(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq -56(%rbp), %rsi
movq -48(%rbp), %rdx
leaq -36(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -36(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i64
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit67
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -80(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_19:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z4initPii # -- Begin function _Z4initPii
.p2align 4, 0x90
.type _Z4initPii,@function
_Z4initPii: # @_Z4initPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4initPii, .Lfunc_end2-_Z4initPii
.cfi_endproc
# -- End function
.globl _Z5printPiii # -- Begin function _Z5printPiii
.p2align 4, 0x90
.type _Z5printPiii,@function
_Z5printPiii: # @_Z5printPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_8
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r13d # 4-byte Reload
xorl %r14d, %r14d
xorl %r12d, %r12d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB3_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addl %ebp, %r14d
cmpq 16(%rsp), %r12 # 8-byte Folded Reload
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq %rbx, %r13
jne .LBB3_4
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_15
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
# in Loop: Header=BB3_2 Depth=1
cmpb $0, 56(%r15)
je .LBB3_13
# %bb.7: # in Loop: Header=BB3_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB3_14
.LBB3_8: # %._crit_edge18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_15
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB3_12
.LBB3_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB3_15:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z5printPiii, .Lfunc_end3-_Z5printPiii
.cfi_endproc
# -- End function
.globl _Z3sumPiS_S_ii # -- Begin function _Z3sumPiS_S_ii
.p2align 4, 0x90
.type _Z3sumPiS_S_ii,@function
_Z3sumPiS_S_ii: # @_Z3sumPiS_S_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %r8d, %r9d
xorl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r11
addl %ecx, %r10d
cmpq %rax, %r11
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %r8d, %r8d
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %r10d, %r15d
leaq (%rdi,%r15,4), %rbx
leaq (%rdx,%r15,4), %r14
leaq (%rsi,%r15,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %ebp
addl (%r15,%r12,4), %ebp
movl %ebp, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r9
jne .LBB4_4
jmp .LBB4_5
.LBB4_6:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_7: # %._crit_edge21
retq
.Lfunc_end4:
.size _Z3sumPiS_S_ii, .Lfunc_end4-_Z3sumPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sum_cudaPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8sum_cudaPiS_S_ii,@object # @_Z8sum_cudaPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z8sum_cudaPiS_S_ii
.p2align 3, 0x0
_Z8sum_cudaPiS_S_ii:
.quad _Z23__device_stub__sum_cudaPiS_S_ii
.size _Z8sum_cudaPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\320\237\320\276\321\201\320\273\320\265\320\264\320\276\320\262\320\260\321\202\320\265\320\273\321\214\320\275\320\276 "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\320\237\320\260\321\200\320\260\320\273\320\273\320\265\320\273\321\214\320\275\320\276 "
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8sum_cudaPiS_S_ii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sum_cudaPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sum_cudaPiS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8sum_cudaPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8sum_cudaPiS_S_ii
.globl _Z8sum_cudaPiS_S_ii
.p2align 8
.type _Z8sum_cudaPiS_S_ii,@function
_Z8sum_cudaPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s15, s15, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s15, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8sum_cudaPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8sum_cudaPiS_S_ii, .Lfunc_end0-_Z8sum_cudaPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8sum_cudaPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8sum_cudaPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012e777_00000000-6_matrix-sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3sumPiS_S_ii
.type _Z3sumPiS_S_ii, @function
_Z3sumPiS_S_ii:
.LFB3670:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdx, %r9
movl %ecx, %ebx
movl $0, %r11d
movl $0, %r10d
movslq %r8d, %rbp
jmp .L5
.L7:
movslq %r11d, %rcx
leaq 0(,%rcx,4), %rax
addq %rbp, %rcx
salq $2, %rcx
.L6:
movl (%r9,%rax), %edx
addl (%rsi,%rax), %edx
movl %edx, (%rdi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r10d
addl %ebx, %r11d
cmpl %r10d, %ebx
je .L3
.L5:
testl %r8d, %r8d
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3670:
.size _Z3sumPiS_S_ii, .-_Z3sumPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z5printPiii
.type _Z5printPiii, @function
_Z5printPiii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
testl %esi, %esi
jle .L15
movl $0, %r15d
movl $0, %r14d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L16
.L28:
call _ZSt16__throw_bad_castv@PLT
.L19:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, %eax
je .L15
.L16:
cmpl $0, 12(%rsp)
jle .L22
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %r12
.L17:
movl (%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
.L22:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L28
cmpb $0, 56(%rbx)
je .L19
movzbl 67(%rbx), %esi
jmp .L20
.L15:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L29
cmpb $0, 56(%rbx)
je .L24
movzbl 67(%rbx), %eax
.L25:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L24:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L25
.cfi_endproc
.LFE3671:
.size _Z5printPiii, .-_Z5printPiii
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB3672:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L30
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %rbp
.L32:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
.L30:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z4initPii, .-_Z4initPii
.globl _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
.type _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii, @function
_Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8sum_cudaPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii, .-_Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
.globl _Z8sum_cudaPiS_S_ii
.type _Z8sum_cudaPiS_S_ii, @function
_Z8sum_cudaPiS_S_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z8sum_cudaPiS_S_ii, .-_Z8sum_cudaPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\320\237\320\276\321\201\320\273\320\265\320\264\320\276\320\262\320\260\321\202\320\265\320\273\321\214\320\275\320\276 "
.section .rodata.str1.1
.LC3:
.string "\320\237\320\260\321\200\320\260\320\273\320\273\320\265\320\273\321\214\320\275\320\276 "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $224, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbp
movl $16, %esi
movq %rbp, %rdi
call _Z4initPii
leaq 144(%rsp), %r12
movl $16, %esi
movq %r12, %rdi
call _Z4initPii
movl $64, %edi
call _Znam@PLT
movq %rax, %rbx
movl $0x00000000, 12(%rsp)
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $4, %edx
movl $4, %esi
movq %rbp, %rdi
call _Z5printPiii
movl $4, %edx
movl $4, %esi
movq %r12, %rdi
call _Z5printPiii
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, %r8d
movl $4, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z3sumPiS_S_ii
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z5printPiii
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, 56(%rsp)
movl $2, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 68(%rsp)
movl $2, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L44:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $64, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z5printPiii
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl $4, %r8d
movl $4, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z33__device_stub__Z8sum_cudaPiS_S_iiPiS_S_ii
jmp .L44
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z8sum_cudaPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sum_cudaPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix-sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__sum_cudaPiS_S_ii # -- Begin function _Z23__device_stub__sum_cudaPiS_S_ii
.p2align 4, 0x90
.type _Z23__device_stub__sum_cudaPiS_S_ii,@function
_Z23__device_stub__sum_cudaPiS_S_ii: # @_Z23__device_stub__sum_cudaPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8sum_cudaPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__sum_cudaPiS_S_ii, .Lfunc_end0-_Z23__device_stub__sum_cudaPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $240, %rsp
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, -272(%rbp,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2: # %_Z4initPii.exit
movq %rsp, %r14
addq $-64, %r14
movq %r14, %rsp
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i54
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB1_3
# %bb.4: # %_Z4initPii.exit58
movl $64, %edi
callq _Znam
movq %rax, %rbx
movl $0, -36(%rbp)
leaq -80(%rbp), %rdi
movl $64, %esi
callq hipMalloc
leaq -72(%rbp), %rdi
movl $64, %esi
callq hipMalloc
leaq -64(%rbp), %rdi
movl $64, %esi
callq hipMalloc
movq -80(%rbp), %rdi
leaq -272(%rbp), %r15
movl $64, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq -72(%rbp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq -56(%rbp), %rdi
callq hipEventCreate
leaq -48(%rbp), %rdi
callq hipEventCreate
movq %r15, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq %r14, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq -56(%rbp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rax
.p2align 4, 0x90
.LBB1_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rcx,4), %edx
addl (%r15,%rcx,4), %edx
movl %edx, (%rax,%rcx,4)
incq %rcx
cmpq $4, %rcx
jne .LBB1_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB1_5 Depth=1
incq %r12
addq $16, %rax
addq $16, %r14
addq $16, %r15
cmpq $4, %r12
jne .LBB1_5
# %bb.8: # %_Z3sumPiS_S_ii.exit
movq -48(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -48(%rbp), %rdi
callq hipEventSynchronize
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq -56(%rbp), %rsi
movq -48(%rbp), %rdx
leaq -36(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -36(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_19
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -56(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq -64(%rbp), %rax
movq -80(%rbp), %rcx
movq -72(%rbp), %rdx
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
movq %rdx, -144(%rbp)
movl $4, -88(%rbp)
movl $4, -84(%rbp)
leaq -160(%rbp), %rax
movq %rax, -208(%rbp)
leaq -152(%rbp), %rax
movq %rax, -200(%rbp)
leaq -144(%rbp), %rax
movq %rax, -192(%rbp)
leaq -88(%rbp), %rax
movq %rax, -184(%rbp)
leaq -84(%rbp), %rax
movq %rax, -176(%rbp)
leaq -136(%rbp), %rdi
leaq -120(%rbp), %rsi
leaq -104(%rbp), %rdx
leaq -96(%rbp), %rcx
callq __hipPopCallConfiguration
movq -136(%rbp), %rsi
movl -128(%rbp), %edx
movq -120(%rbp), %rcx
movl -112(%rbp), %r8d
leaq -208(%rbp), %r9
movl $_Z8sum_cudaPiS_S_ii, %edi
pushq -96(%rbp)
pushq -104(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_14:
callq hipDeviceSynchronize
movq -48(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
callq _Z5printPiii
movq -56(%rbp), %rsi
movq -48(%rbp), %rdx
leaq -36(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -36(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i64
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit67
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -80(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_19:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z4initPii # -- Begin function _Z4initPii
.p2align 4, 0x90
.type _Z4initPii,@function
_Z4initPii: # @_Z4initPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4initPii, .Lfunc_end2-_Z4initPii
.cfi_endproc
# -- End function
.globl _Z5printPiii # -- Begin function _Z5printPiii
.p2align 4, 0x90
.type _Z5printPiii,@function
_Z5printPiii: # @_Z5printPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_8
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r13d # 4-byte Reload
xorl %r14d, %r14d
xorl %r12d, %r12d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB3_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addl %ebp, %r14d
cmpq 16(%rsp), %r12 # 8-byte Folded Reload
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq %rbx, %r13
jne .LBB3_4
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_15
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
# in Loop: Header=BB3_2 Depth=1
cmpb $0, 56(%r15)
je .LBB3_13
# %bb.7: # in Loop: Header=BB3_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB3_14
.LBB3_8: # %._crit_edge18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_15
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB3_12
.LBB3_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB3_15:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z5printPiii, .Lfunc_end3-_Z5printPiii
.cfi_endproc
# -- End function
.globl _Z3sumPiS_S_ii # -- Begin function _Z3sumPiS_S_ii
.p2align 4, 0x90
.type _Z3sumPiS_S_ii,@function
_Z3sumPiS_S_ii: # @_Z3sumPiS_S_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %r8d, %r9d
xorl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r11
addl %ecx, %r10d
cmpq %rax, %r11
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %r8d, %r8d
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %r10d, %r15d
leaq (%rdi,%r15,4), %rbx
leaq (%rdx,%r15,4), %r14
leaq (%rsi,%r15,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %ebp
addl (%r15,%r12,4), %ebp
movl %ebp, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r9
jne .LBB4_4
jmp .LBB4_5
.LBB4_6:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_7: # %._crit_edge21
retq
.Lfunc_end4:
.size _Z3sumPiS_S_ii, .Lfunc_end4-_Z3sumPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sum_cudaPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8sum_cudaPiS_S_ii,@object # @_Z8sum_cudaPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z8sum_cudaPiS_S_ii
.p2align 3, 0x0
_Z8sum_cudaPiS_S_ii:
.quad _Z23__device_stub__sum_cudaPiS_S_ii
.size _Z8sum_cudaPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\320\237\320\276\321\201\320\273\320\265\320\264\320\276\320\262\320\260\321\202\320\265\320\273\321\214\320\275\320\276 "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\320\237\320\260\321\200\320\260\320\273\320\273\320\265\320\273\321\214\320\275\320\276 "
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8sum_cudaPiS_S_ii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sum_cudaPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sum_cudaPiS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | typedef struct {
int width;
int height;
int stride;
int* elements;
} matrix;
typedef struct {
int width;
int height;
int stride;
float* elements;
} matrixf;
__device__ matrix GetSubmatrix(matrix A, int row, int col, int block_size)
{
matrix Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__device__ matrixf GetSubmatrixf(matrixf A, int row, int col, int block_size)
{
matrixf Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__global__ void create_accum(matrix *accum, matrix *r_table, matrixf *gradient_image)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;;//height of image
int idy = threadIdx.y + blockDim.y * blockIdx.y;//width of image
int idz = threadIdx.z + blockDim.z * blockIdx.z;;//width of r_table
//float phi =0;
//if(idx<gradient_image->height && idy<gradient_image->width){
float phi = gradient_image->elements[idx * gradient_image->width + idy];
//}
int slice =0;
float pi = 3.14159265359;
if(phi > 0.001||phi< -0.001){
slice = __float2int_rd(8*(phi+pi)/(2*pi));//rotate here?
if(r_table->elements[(slice*r_table->width + idz)*2] != 0 && r_table->elements[(slice*r_table->width + idz)*2+1] != 0){
int ix = idx+r_table->elements[(slice*r_table->width + idz)*2];
int iy = idy+r_table->elements[(slice*r_table->width + idz)*2 + 1];
if ( ix >= 0 && ix < accum->width && iy >= 0 && iy < accum->height){
atomicAdd(&accum->elements[(ix*accum->width + iy)],1);
__syncthreads();
}
}
}
} | code for sm_80
Function : _Z12create_accumP6matrixS0_P7matrixf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E.64 R6, [R4.64+0x10] ; /* 0x0000100604067981 */
/* 0x000ee8000c1e1b00 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0080*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*00b0*/ IMAD R3, R8, c[0x0][0x4], R9 ; /* 0x0000010008037a24 */
/* 0x002fc800078e0209 */
/*00c0*/ IMAD R9, R0, R2, R3 ; /* 0x0000000200097224 */
/* 0x004fc800078e0203 */
/*00d0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x008fcc00078e0206 */
/*00e0*/ LD.E R6, [R6.64] ; /* 0x0000000606067980 */
/* 0x000ea4000c101900 */
/*00f0*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */
/* 0x004e240000201800 */
/*0100*/ DSETP.GEU.AND P0, PT, R8, c[0x2][0x0], PT ; /* 0x008000000800762a */
/* 0x001fc80003f0e000 */
/*0110*/ DSETP.LEU.AND P1, PT, R8, c[0x2][0x8], PT ; /* 0x008002000800762a */
/* 0x000e1c0003f2b000 */
/*0120*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x001fea0000800000 */
/*0130*/ FADD R6, R6, 3.1415927410125732422 ; /* 0x40490fdb06067421 */
/* 0x000fe20000000000 */
/*0140*/ BSSY B1, 0x230 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3e22f983 ; /* 0x3e22f983ff057424 */
/* 0x000fe400078e00ff */
/*0160*/ FMUL R6, R6, 8 ; /* 0x4100000006067820 */
/* 0x000fe40000400000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x40c90fdb ; /* 0x40c90fdbff027424 */
/* 0x000fe400078e00ff */
/*0180*/ FCHK P0, R6, 6.2831854820251464844 ; /* 0x40c90fdb06007902 */
/* 0x000e240000000000 */
/*0190*/ FFMA R2, R5, -R2, 1 ; /* 0x3f80000005027423 */
/* 0x000fc80000000802 */
/*01a0*/ FFMA R5, R2, R5, 0.15915493667125701904 ; /* 0x3e22f98302057423 */
/* 0x000fc80000000005 */
/*01b0*/ FFMA R2, R6, R5, RZ ; /* 0x0000000506027223 */
/* 0x000fc800000000ff */
/*01c0*/ FFMA R4, R2, -6.2831854820251464844, R6 ; /* 0xc0c90fdb02047823 */
/* 0x000fc80000000006 */
/*01d0*/ FFMA R2, R5, R4, R2 ; /* 0x0000000405027223 */
/* 0x000fe20000000002 */
/*01e0*/ @!P0 BRA 0x220 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*01f0*/ MOV R2, 0x210 ; /* 0x0000021000027802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0x4c0 ; /* 0x000002b000007944 */
/* 0x000fea0003c00000 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0008 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0250*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E.64 R6, [R4.64+0x10] ; /* 0x0000100604067981 */
/* 0x000ee2000c1e1b00 */
/*0270*/ F2I.FLOOR.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000ea60000207100 */
/*0280*/ S2R R8, SR_TID.Z ; /* 0x0000000000087919 */
/* 0x000e280000002300 */
/*0290*/ S2R R11, SR_CTAID.Z ; /* 0x00000000000b7919 */
/* 0x000e240000002700 */
/*02a0*/ IMAD R8, R11, c[0x0][0x8], R8 ; /* 0x000002000b087a24 */
/* 0x001fc800078e0208 */
/*02b0*/ IMAD R8, R2, R9, R8 ; /* 0x0000000902087224 */
/* 0x004fc800078e0208 */
/*02c0*/ IMAD.SHL.U32 R9, R8, 0x2, RZ ; /* 0x0000000208097824 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x008fca00078e0206 */
/*02e0*/ LD.E R9, [R6.64] ; /* 0x0000000606097980 */
/* 0x000ea4000c101900 */
/*02f0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x004fda0003f05270 */
/*0300*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0310*/ LD.E R6, [R6.64+0x4] ; /* 0x0000040606067980 */
/* 0x000ea4000c101900 */
/*0320*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IMAD.IADD R7, R0, 0x1, R9 ; /* 0x0000000100077824 */
/* 0x000fe200078e0209 */
/*0350*/ BSSY B0, 0x3f0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.IADD R6, R3, 0x1, R6 ; /* 0x0000000103067824 */
/* 0x000fe200078e0206 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0390*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f26270 */
/*03a0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fd60000000f00 */
/*03b0*/ @!P1 BRA 0x3e0 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ ISETP.LT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x004fd00003f01270 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.LT.OR P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720c */
/* 0x000fda0004701670 */
/*0400*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*0420*/ ISETP.GE.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x004fda0003f06270 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E.64 R4, [R2.64+0x10] ; /* 0x0000100602047981 */
/* 0x000ee2000c1e1b00 */
/*0460*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD R7, R7, R0, R6 ; /* 0x0000000007077224 */
/* 0x004fc800078e0206 */
/*0480*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x008fca00078e0204 */
/*0490*/ ATOM.E.ADD.STRONG.GPU PT, RZ, [R4.64], R9 ; /* 0x0000000904ff798a */
/* 0x000fe800081ee1c6 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ SHF.R.U32.HI R4, RZ, 0x17, R6.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011606 */
/*04d0*/ BSSY B0, 0xaa0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*04e0*/ BSSY B2, 0x690 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*04f0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0500*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fc800078ec0ff */
/*0510*/ IADD3 R9, R4, -0x1, RZ ; /* 0xffffffff04097810 */
/* 0x000fc80007ffe0ff */
/*0520*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, !PT ; /* 0x000000fd0900780c */
/* 0x000fda0007f04470 */
/*0530*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0540*/ @!P0 BRA 0x680 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0550*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1c200 */
/*0560*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0570*/ @P0 BRA 0xa80 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0580*/ HFMA2.MMA R8, -RZ, RZ, 2.392578125, 0.0004794597625732421875 ; /* 0x40c90fdbff087435 */
/* 0x000fd400000001ff */
/*0590*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*05a0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*05b0*/ @!P0 BRA 0xa60 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*05c0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*05d0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*05e0*/ @!P0 BRA 0xa40 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1d200 */
/*0600*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0610*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0620*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0630*/ @P0 BRA 0xa10 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f06270 */
/*0650*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0660*/ @!P0 FFMA R5, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006058823 */
/* 0x000fe400000000ff */
/*0670*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0680*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0690*/ UMOV UR4, 0x40c90fdb ; /* 0x40c90fdb00047882 */
/* 0x000fe20000000000 */
/*06a0*/ IADD3 R4, R4, -0x7f, RZ ; /* 0xffffff8104047810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ UIADD3 UR4, UR4, -0x1000000, URZ ; /* 0xff00000004047890 */
/* 0x000fe2000fffe03f */
/*06c0*/ BSSY B2, 0xa00 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*06d0*/ IADD3 R7, R7, -0x2, R4 ; /* 0xfffffffe07077810 */
/* 0x000fe20007ffe004 */
/*06e0*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fc400078e0205 */
/*06f0*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*0700*/ MUFU.RCP R6, UR4 ; /* 0x0000000400067d08 */
/* 0x000e240008001000 */
/*0710*/ FFMA R9, R6, R8, 1 ; /* 0x3f80000006097423 */
/* 0x001fc80000000008 */
/*0720*/ FFMA R6, R6, R9, R6 ; /* 0x0000000906067223 */
/* 0x000fc80000000006 */
/*0730*/ FFMA R9, R5, R6, RZ ; /* 0x0000000605097223 */
/* 0x000fc800000000ff */
/*0740*/ FFMA R10, R8, R9, R5 ; /* 0x00000009080a7223 */
/* 0x000fc80000000005 */
/*0750*/ FFMA R9, R6, R10, R9 ; /* 0x0000000a06097223 */
/* 0x000fc80000000009 */
/*0760*/ FFMA R10, R8, R9, R5 ; /* 0x00000009080a7223 */
/* 0x000fc80000000005 */
/*0770*/ FFMA R8, R6, R10, R9 ; /* 0x0000000a06087223 */
/* 0x000fca0000000009 */
/*0780*/ SHF.R.U32.HI R5, RZ, 0x17, R8 ; /* 0x00000017ff057819 */
/* 0x000fc80000011608 */
/*0790*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*07a0*/ IMAD.IADD R11, R5, 0x1, R7 ; /* 0x00000001050b7824 */
/* 0x000fca00078e0207 */
/*07b0*/ IADD3 R4, R11, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x000fc80007ffe0ff */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*07d0*/ @!P0 BRA 0x9e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*07f0*/ @P0 BRA 0x9b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0810*/ @P0 BRA 0x9f0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0820*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0830*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008087812 */
/* 0x000fd600078ec0ff */
/*0840*/ @!P0 BRA 0x9f0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0850*/ FFMA.RZ R4, R6.reuse, R10.reuse, R9.reuse ; /* 0x0000000a06047223 */
/* 0x1c0fe2000000c009 */
/*0860*/ ISETP.NE.AND P2, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x040fe20003f45270 */
/*0870*/ FFMA.RM R5, R6, R10.reuse, R9.reuse ; /* 0x0000000a06057223 */
/* 0x180fe20000004009 */
/*0880*/ ISETP.NE.AND P1, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x040fe40003f25270 */
/*0890*/ LOP3.LUT R7, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04077812 */
/* 0x000fe200078ec0ff */
/*08a0*/ FFMA.RP R4, R6, R10, R9 ; /* 0x0000000a06047223 */
/* 0x000fe20000008009 */
/*08b0*/ IADD3 R6, R11, 0x20, RZ ; /* 0x000000200b067810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0b */
/*08d0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*08e0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*08f0*/ SHF.L.U32 R6, R7, R6, RZ ; /* 0x0000000607067219 */
/* 0x000fe400000006ff */
/*0900*/ SEL R4, R9, RZ, P2 ; /* 0x000000ff09047207 */
/* 0x000fe40001000000 */
/*0910*/ ISETP.NE.AND P1, PT, R6, RZ, P1 ; /* 0x000000ff0600720c */
/* 0x000fe40000f25270 */
/*0920*/ SHF.R.U32.HI R4, RZ, R4, R7 ; /* 0x00000004ff047219 */
/* 0x000fe40000011607 */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0940*/ SHF.R.U32.HI R6, RZ, 0x1, R4 ; /* 0x00000001ff067819 */
/* 0x000fc40000011604 */
/*0950*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0960*/ LOP3.LUT R5, R5, 0x1, R6, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef806 */
/*0970*/ LOP3.LUT R5, R5, R4, RZ, 0xc0, !PT ; /* 0x0000000405057212 */
/* 0x000fc800078ec0ff */
/*0980*/ IADD3 R5, R6, R5, RZ ; /* 0x0000000506057210 */
/* 0x000fc80007ffe0ff */
/*0990*/ LOP3.LUT R8, R5, R8, RZ, 0xfc, !PT ; /* 0x0000000805087212 */
/* 0x000fe200078efcff */
/*09a0*/ BRA 0x9f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09b0*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008087812 */
/* 0x000fc800078ec0ff */
/*09c0*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000008087812 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0x9f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09e0*/ IMAD R8, R7, 0x800000, R8 ; /* 0x0080000007087824 */
/* 0x000fe400078e0208 */
/*09f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0a10*/ LOP3.LUT R8, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008087812 */
/* 0x000fc800078e4805 */
/*0a20*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000008087812 */
/* 0x000fe200078efcff */
/*0a30*/ BRA 0xa90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R8, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008087812 */
/* 0x000fe200078e4805 */
/*0a50*/ BRA 0xa90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a60*/ MUFU.RSQ R8, -QNAN ; /* 0xffc0000000087908 */
/* 0x000e220000001400 */
/*0a70*/ BRA 0xa90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a80*/ FADD.FTZ R8, R6, 6.2831854820251464844 ; /* 0x40c90fdb06087421 */
/* 0x000fe40000010000 */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0ab0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0ac0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff53004007950 */
/* 0x000fea0003c3ffff */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | typedef struct {
int width;
int height;
int stride;
int* elements;
} matrix;
typedef struct {
int width;
int height;
int stride;
float* elements;
} matrixf;
__device__ matrix GetSubmatrix(matrix A, int row, int col, int block_size)
{
matrix Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__device__ matrixf GetSubmatrixf(matrixf A, int row, int col, int block_size)
{
matrixf Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__global__ void create_accum(matrix *accum, matrix *r_table, matrixf *gradient_image)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;;//height of image
int idy = threadIdx.y + blockDim.y * blockIdx.y;//width of image
int idz = threadIdx.z + blockDim.z * blockIdx.z;;//width of r_table
//float phi =0;
//if(idx<gradient_image->height && idy<gradient_image->width){
float phi = gradient_image->elements[idx * gradient_image->width + idy];
//}
int slice =0;
float pi = 3.14159265359;
if(phi > 0.001||phi< -0.001){
slice = __float2int_rd(8*(phi+pi)/(2*pi));//rotate here?
if(r_table->elements[(slice*r_table->width + idz)*2] != 0 && r_table->elements[(slice*r_table->width + idz)*2+1] != 0){
int ix = idx+r_table->elements[(slice*r_table->width + idz)*2];
int iy = idy+r_table->elements[(slice*r_table->width + idz)*2 + 1];
if ( ix >= 0 && ix < accum->width && iy >= 0 && iy < accum->height){
atomicAdd(&accum->elements[(ix*accum->width + iy)],1);
__syncthreads();
}
}
}
} | .file "tmpxft_00001291_00000000-6_hough_transform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12GetSubmatrix6matrixiii
.type _Z12GetSubmatrix6matrixiii, @function
_Z12GetSubmatrix6matrixiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12GetSubmatrix6matrixiii, .-_Z12GetSubmatrix6matrixiii
.globl _Z13GetSubmatrixf7matrixfiii
.type _Z13GetSubmatrixf7matrixfiii, @function
_Z13GetSubmatrixf7matrixfiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z13GetSubmatrixf7matrixfiii, .-_Z13GetSubmatrixf7matrixfiii
.globl _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf
.type _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf, @function
_Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12create_accumP6matrixS0_P7matrixf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf, .-_Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf
.globl _Z12create_accumP6matrixS0_P7matrixf
.type _Z12create_accumP6matrixS0_P7matrixf, @function
_Z12create_accumP6matrixS0_P7matrixf:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z12create_accumP6matrixS0_P7matrixf, .-_Z12create_accumP6matrixS0_P7matrixf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12create_accumP6matrixS0_P7matrixf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12create_accumP6matrixS0_P7matrixf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | typedef struct {
int width;
int height;
int stride;
int* elements;
} matrix;
typedef struct {
int width;
int height;
int stride;
float* elements;
} matrixf;
__device__ matrix GetSubmatrix(matrix A, int row, int col, int block_size)
{
matrix Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__device__ matrixf GetSubmatrixf(matrixf A, int row, int col, int block_size)
{
matrixf Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__global__ void create_accum(matrix *accum, matrix *r_table, matrixf *gradient_image)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;;//height of image
int idy = threadIdx.y + blockDim.y * blockIdx.y;//width of image
int idz = threadIdx.z + blockDim.z * blockIdx.z;;//width of r_table
//float phi =0;
//if(idx<gradient_image->height && idy<gradient_image->width){
float phi = gradient_image->elements[idx * gradient_image->width + idy];
//}
int slice =0;
float pi = 3.14159265359;
if(phi > 0.001||phi< -0.001){
slice = __float2int_rd(8*(phi+pi)/(2*pi));//rotate here?
if(r_table->elements[(slice*r_table->width + idz)*2] != 0 && r_table->elements[(slice*r_table->width + idz)*2+1] != 0){
int ix = idx+r_table->elements[(slice*r_table->width + idz)*2];
int iy = idy+r_table->elements[(slice*r_table->width + idz)*2 + 1];
if ( ix >= 0 && ix < accum->width && iy >= 0 && iy < accum->height){
atomicAdd(&accum->elements[(ix*accum->width + iy)],1);
__syncthreads();
}
}
}
} | #include <hip/hip_runtime.h>
typedef struct {
int width;
int height;
int stride;
int* elements;
} matrix;
typedef struct {
int width;
int height;
int stride;
float* elements;
} matrixf;
__device__ matrix GetSubmatrix(matrix A, int row, int col, int block_size)
{
matrix Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__device__ matrixf GetSubmatrixf(matrixf A, int row, int col, int block_size)
{
matrixf Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__global__ void create_accum(matrix *accum, matrix *r_table, matrixf *gradient_image)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;;//height of image
int idy = threadIdx.y + blockDim.y * blockIdx.y;//width of image
int idz = threadIdx.z + blockDim.z * blockIdx.z;;//width of r_table
//float phi =0;
//if(idx<gradient_image->height && idy<gradient_image->width){
float phi = gradient_image->elements[idx * gradient_image->width + idy];
//}
int slice =0;
float pi = 3.14159265359;
if(phi > 0.001||phi< -0.001){
slice = __float2int_rd(8*(phi+pi)/(2*pi));//rotate here?
if(r_table->elements[(slice*r_table->width + idz)*2] != 0 && r_table->elements[(slice*r_table->width + idz)*2+1] != 0){
int ix = idx+r_table->elements[(slice*r_table->width + idz)*2];
int iy = idy+r_table->elements[(slice*r_table->width + idz)*2 + 1];
if ( ix >= 0 && ix < accum->width && iy >= 0 && iy < accum->height){
atomicAdd(&accum->elements[(ix*accum->width + iy)],1);
__syncthreads();
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
typedef struct {
int width;
int height;
int stride;
int* elements;
} matrix;
typedef struct {
int width;
int height;
int stride;
float* elements;
} matrixf;
__device__ matrix GetSubmatrix(matrix A, int row, int col, int block_size)
{
matrix Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__device__ matrixf GetSubmatrixf(matrixf A, int row, int col, int block_size)
{
matrixf Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__global__ void create_accum(matrix *accum, matrix *r_table, matrixf *gradient_image)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;;//height of image
int idy = threadIdx.y + blockDim.y * blockIdx.y;//width of image
int idz = threadIdx.z + blockDim.z * blockIdx.z;;//width of r_table
//float phi =0;
//if(idx<gradient_image->height && idy<gradient_image->width){
float phi = gradient_image->elements[idx * gradient_image->width + idy];
//}
int slice =0;
float pi = 3.14159265359;
if(phi > 0.001||phi< -0.001){
slice = __float2int_rd(8*(phi+pi)/(2*pi));//rotate here?
if(r_table->elements[(slice*r_table->width + idz)*2] != 0 && r_table->elements[(slice*r_table->width + idz)*2+1] != 0){
int ix = idx+r_table->elements[(slice*r_table->width + idz)*2];
int iy = idy+r_table->elements[(slice*r_table->width + idz)*2 + 1];
if ( ix >= 0 && ix < accum->width && iy >= 0 && iy < accum->height){
atomicAdd(&accum->elements[(ix*accum->width + iy)],1);
__syncthreads();
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12create_accumP6matrixS0_P7matrixf
.globl _Z12create_accumP6matrixS0_P7matrixf
.p2align 8
.type _Z12create_accumP6matrixS0_P7matrixf,@function
_Z12create_accumP6matrixS0_P7matrixf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s7, s[2:3], 0x0
s_and_b32 s8, s6, 0xffff
s_lshr_b32 s6, s6, 16
v_mad_u64_u32 v[3:4], null, s13, s8, v[1:2]
v_mad_u64_u32 v[1:2], null, s14, s6, v[5:6]
s_load_b64 s[2:3], s[2:3], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s7, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_mov_b32 s3, 0x3f50624d
s_mov_b32 s2, 0xd2f1a9fc
flat_load_b32 v2, v[4:5]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_mov_b32 s3, 0xbf50624d
v_cmp_gt_f64_e64 s2, s[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
v_add_f32_e32 v2, 0x40490fdb, v2
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[4:5], 0x10
v_bfe_u32 v0, v0, 20, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x41000000, v2
v_div_scale_f32 v4, null, 0x40c90fdb, 0x40c90fdb, v2
v_div_scale_f32 v7, vcc_lo, v2, 0x40c90fdb, v2
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v5, v4
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_load_b64 s[2:3], s[2:3], 0x10
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, 0x40c90fdb, v2
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
v_floor_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v4, v4, v0, 1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
flat_load_b32 v0, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_or_b32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
flat_load_b32 v4, v[4:5]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v2, v0, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v0, v4, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e64 s0, -1, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s1, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_load_b32 s0, s[2:3], 0x4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[2:3], 0x10
v_mad_u64_u32 v[3:4], null, s1, v2, v[0:1]
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
flat_atomic_add_u32 v[0:1], v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12create_accumP6matrixS0_P7matrixf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12create_accumP6matrixS0_P7matrixf, .Lfunc_end0-_Z12create_accumP6matrixS0_P7matrixf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12create_accumP6matrixS0_P7matrixf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12create_accumP6matrixS0_P7matrixf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
typedef struct {
int width;
int height;
int stride;
int* elements;
} matrix;
typedef struct {
int width;
int height;
int stride;
float* elements;
} matrixf;
__device__ matrix GetSubmatrix(matrix A, int row, int col, int block_size)
{
matrix Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__device__ matrixf GetSubmatrixf(matrixf A, int row, int col, int block_size)
{
matrixf Asub;
Asub.width = block_size;
Asub.height = block_size;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * block_size * row
+ block_size * col];
return Asub;
}
__global__ void create_accum(matrix *accum, matrix *r_table, matrixf *gradient_image)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;;//height of image
int idy = threadIdx.y + blockDim.y * blockIdx.y;//width of image
int idz = threadIdx.z + blockDim.z * blockIdx.z;;//width of r_table
//float phi =0;
//if(idx<gradient_image->height && idy<gradient_image->width){
float phi = gradient_image->elements[idx * gradient_image->width + idy];
//}
int slice =0;
float pi = 3.14159265359;
if(phi > 0.001||phi< -0.001){
slice = __float2int_rd(8*(phi+pi)/(2*pi));//rotate here?
if(r_table->elements[(slice*r_table->width + idz)*2] != 0 && r_table->elements[(slice*r_table->width + idz)*2+1] != 0){
int ix = idx+r_table->elements[(slice*r_table->width + idz)*2];
int iy = idy+r_table->elements[(slice*r_table->width + idz)*2 + 1];
if ( ix >= 0 && ix < accum->width && iy >= 0 && iy < accum->height){
atomicAdd(&accum->elements[(ix*accum->width + iy)],1);
__syncthreads();
}
}
}
} | .text
.file "hough_transform.hip"
.globl _Z27__device_stub__create_accumP6matrixS0_P7matrixf # -- Begin function _Z27__device_stub__create_accumP6matrixS0_P7matrixf
.p2align 4, 0x90
.type _Z27__device_stub__create_accumP6matrixS0_P7matrixf,@function
_Z27__device_stub__create_accumP6matrixS0_P7matrixf: # @_Z27__device_stub__create_accumP6matrixS0_P7matrixf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12create_accumP6matrixS0_P7matrixf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__create_accumP6matrixS0_P7matrixf, .Lfunc_end0-_Z27__device_stub__create_accumP6matrixS0_P7matrixf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12create_accumP6matrixS0_P7matrixf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12create_accumP6matrixS0_P7matrixf,@object # @_Z12create_accumP6matrixS0_P7matrixf
.section .rodata,"a",@progbits
.globl _Z12create_accumP6matrixS0_P7matrixf
.p2align 3, 0x0
_Z12create_accumP6matrixS0_P7matrixf:
.quad _Z27__device_stub__create_accumP6matrixS0_P7matrixf
.size _Z12create_accumP6matrixS0_P7matrixf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12create_accumP6matrixS0_P7matrixf"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__create_accumP6matrixS0_P7matrixf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12create_accumP6matrixS0_P7matrixf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12create_accumP6matrixS0_P7matrixf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E.64 R6, [R4.64+0x10] ; /* 0x0000100604067981 */
/* 0x000ee8000c1e1b00 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0080*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*00b0*/ IMAD R3, R8, c[0x0][0x4], R9 ; /* 0x0000010008037a24 */
/* 0x002fc800078e0209 */
/*00c0*/ IMAD R9, R0, R2, R3 ; /* 0x0000000200097224 */
/* 0x004fc800078e0203 */
/*00d0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x008fcc00078e0206 */
/*00e0*/ LD.E R6, [R6.64] ; /* 0x0000000606067980 */
/* 0x000ea4000c101900 */
/*00f0*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */
/* 0x004e240000201800 */
/*0100*/ DSETP.GEU.AND P0, PT, R8, c[0x2][0x0], PT ; /* 0x008000000800762a */
/* 0x001fc80003f0e000 */
/*0110*/ DSETP.LEU.AND P1, PT, R8, c[0x2][0x8], PT ; /* 0x008002000800762a */
/* 0x000e1c0003f2b000 */
/*0120*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x001fea0000800000 */
/*0130*/ FADD R6, R6, 3.1415927410125732422 ; /* 0x40490fdb06067421 */
/* 0x000fe20000000000 */
/*0140*/ BSSY B1, 0x230 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3e22f983 ; /* 0x3e22f983ff057424 */
/* 0x000fe400078e00ff */
/*0160*/ FMUL R6, R6, 8 ; /* 0x4100000006067820 */
/* 0x000fe40000400000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x40c90fdb ; /* 0x40c90fdbff027424 */
/* 0x000fe400078e00ff */
/*0180*/ FCHK P0, R6, 6.2831854820251464844 ; /* 0x40c90fdb06007902 */
/* 0x000e240000000000 */
/*0190*/ FFMA R2, R5, -R2, 1 ; /* 0x3f80000005027423 */
/* 0x000fc80000000802 */
/*01a0*/ FFMA R5, R2, R5, 0.15915493667125701904 ; /* 0x3e22f98302057423 */
/* 0x000fc80000000005 */
/*01b0*/ FFMA R2, R6, R5, RZ ; /* 0x0000000506027223 */
/* 0x000fc800000000ff */
/*01c0*/ FFMA R4, R2, -6.2831854820251464844, R6 ; /* 0xc0c90fdb02047823 */
/* 0x000fc80000000006 */
/*01d0*/ FFMA R2, R5, R4, R2 ; /* 0x0000000405027223 */
/* 0x000fe20000000002 */
/*01e0*/ @!P0 BRA 0x220 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*01f0*/ MOV R2, 0x210 ; /* 0x0000021000027802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0x4c0 ; /* 0x000002b000007944 */
/* 0x000fea0003c00000 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0008 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0250*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E.64 R6, [R4.64+0x10] ; /* 0x0000100604067981 */
/* 0x000ee2000c1e1b00 */
/*0270*/ F2I.FLOOR.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000ea60000207100 */
/*0280*/ S2R R8, SR_TID.Z ; /* 0x0000000000087919 */
/* 0x000e280000002300 */
/*0290*/ S2R R11, SR_CTAID.Z ; /* 0x00000000000b7919 */
/* 0x000e240000002700 */
/*02a0*/ IMAD R8, R11, c[0x0][0x8], R8 ; /* 0x000002000b087a24 */
/* 0x001fc800078e0208 */
/*02b0*/ IMAD R8, R2, R9, R8 ; /* 0x0000000902087224 */
/* 0x004fc800078e0208 */
/*02c0*/ IMAD.SHL.U32 R9, R8, 0x2, RZ ; /* 0x0000000208097824 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x008fca00078e0206 */
/*02e0*/ LD.E R9, [R6.64] ; /* 0x0000000606097980 */
/* 0x000ea4000c101900 */
/*02f0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x004fda0003f05270 */
/*0300*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0310*/ LD.E R6, [R6.64+0x4] ; /* 0x0000040606067980 */
/* 0x000ea4000c101900 */
/*0320*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IMAD.IADD R7, R0, 0x1, R9 ; /* 0x0000000100077824 */
/* 0x000fe200078e0209 */
/*0350*/ BSSY B0, 0x3f0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.IADD R6, R3, 0x1, R6 ; /* 0x0000000103067824 */
/* 0x000fe200078e0206 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0390*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f26270 */
/*03a0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fd60000000f00 */
/*03b0*/ @!P1 BRA 0x3e0 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ ISETP.LT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x004fd00003f01270 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.LT.OR P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720c */
/* 0x000fda0004701670 */
/*0400*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*0420*/ ISETP.GE.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x004fda0003f06270 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E.64 R4, [R2.64+0x10] ; /* 0x0000100602047981 */
/* 0x000ee2000c1e1b00 */
/*0460*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD R7, R7, R0, R6 ; /* 0x0000000007077224 */
/* 0x004fc800078e0206 */
/*0480*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x008fca00078e0204 */
/*0490*/ ATOM.E.ADD.STRONG.GPU PT, RZ, [R4.64], R9 ; /* 0x0000000904ff798a */
/* 0x000fe800081ee1c6 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ SHF.R.U32.HI R4, RZ, 0x17, R6.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011606 */
/*04d0*/ BSSY B0, 0xaa0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*04e0*/ BSSY B2, 0x690 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*04f0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0500*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fc800078ec0ff */
/*0510*/ IADD3 R9, R4, -0x1, RZ ; /* 0xffffffff04097810 */
/* 0x000fc80007ffe0ff */
/*0520*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, !PT ; /* 0x000000fd0900780c */
/* 0x000fda0007f04470 */
/*0530*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0540*/ @!P0 BRA 0x680 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0550*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1c200 */
/*0560*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0570*/ @P0 BRA 0xa80 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0580*/ HFMA2.MMA R8, -RZ, RZ, 2.392578125, 0.0004794597625732421875 ; /* 0x40c90fdbff087435 */
/* 0x000fd400000001ff */
/*0590*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*05a0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*05b0*/ @!P0 BRA 0xa60 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*05c0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*05d0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*05e0*/ @!P0 BRA 0xa40 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1d200 */
/*0600*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0610*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0620*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0630*/ @P0 BRA 0xa10 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f06270 */
/*0650*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0660*/ @!P0 FFMA R5, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006058823 */
/* 0x000fe400000000ff */
/*0670*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0680*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0690*/ UMOV UR4, 0x40c90fdb ; /* 0x40c90fdb00047882 */
/* 0x000fe20000000000 */
/*06a0*/ IADD3 R4, R4, -0x7f, RZ ; /* 0xffffff8104047810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ UIADD3 UR4, UR4, -0x1000000, URZ ; /* 0xff00000004047890 */
/* 0x000fe2000fffe03f */
/*06c0*/ BSSY B2, 0xa00 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*06d0*/ IADD3 R7, R7, -0x2, R4 ; /* 0xfffffffe07077810 */
/* 0x000fe20007ffe004 */
/*06e0*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fc400078e0205 */
/*06f0*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*0700*/ MUFU.RCP R6, UR4 ; /* 0x0000000400067d08 */
/* 0x000e240008001000 */
/*0710*/ FFMA R9, R6, R8, 1 ; /* 0x3f80000006097423 */
/* 0x001fc80000000008 */
/*0720*/ FFMA R6, R6, R9, R6 ; /* 0x0000000906067223 */
/* 0x000fc80000000006 */
/*0730*/ FFMA R9, R5, R6, RZ ; /* 0x0000000605097223 */
/* 0x000fc800000000ff */
/*0740*/ FFMA R10, R8, R9, R5 ; /* 0x00000009080a7223 */
/* 0x000fc80000000005 */
/*0750*/ FFMA R9, R6, R10, R9 ; /* 0x0000000a06097223 */
/* 0x000fc80000000009 */
/*0760*/ FFMA R10, R8, R9, R5 ; /* 0x00000009080a7223 */
/* 0x000fc80000000005 */
/*0770*/ FFMA R8, R6, R10, R9 ; /* 0x0000000a06087223 */
/* 0x000fca0000000009 */
/*0780*/ SHF.R.U32.HI R5, RZ, 0x17, R8 ; /* 0x00000017ff057819 */
/* 0x000fc80000011608 */
/*0790*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*07a0*/ IMAD.IADD R11, R5, 0x1, R7 ; /* 0x00000001050b7824 */
/* 0x000fca00078e0207 */
/*07b0*/ IADD3 R4, R11, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x000fc80007ffe0ff */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*07d0*/ @!P0 BRA 0x9e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*07f0*/ @P0 BRA 0x9b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0810*/ @P0 BRA 0x9f0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0820*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0830*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008087812 */
/* 0x000fd600078ec0ff */
/*0840*/ @!P0 BRA 0x9f0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0850*/ FFMA.RZ R4, R6.reuse, R10.reuse, R9.reuse ; /* 0x0000000a06047223 */
/* 0x1c0fe2000000c009 */
/*0860*/ ISETP.NE.AND P2, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x040fe20003f45270 */
/*0870*/ FFMA.RM R5, R6, R10.reuse, R9.reuse ; /* 0x0000000a06057223 */
/* 0x180fe20000004009 */
/*0880*/ ISETP.NE.AND P1, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x040fe40003f25270 */
/*0890*/ LOP3.LUT R7, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04077812 */
/* 0x000fe200078ec0ff */
/*08a0*/ FFMA.RP R4, R6, R10, R9 ; /* 0x0000000a06047223 */
/* 0x000fe20000008009 */
/*08b0*/ IADD3 R6, R11, 0x20, RZ ; /* 0x000000200b067810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0b */
/*08d0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*08e0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*08f0*/ SHF.L.U32 R6, R7, R6, RZ ; /* 0x0000000607067219 */
/* 0x000fe400000006ff */
/*0900*/ SEL R4, R9, RZ, P2 ; /* 0x000000ff09047207 */
/* 0x000fe40001000000 */
/*0910*/ ISETP.NE.AND P1, PT, R6, RZ, P1 ; /* 0x000000ff0600720c */
/* 0x000fe40000f25270 */
/*0920*/ SHF.R.U32.HI R4, RZ, R4, R7 ; /* 0x00000004ff047219 */
/* 0x000fe40000011607 */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0940*/ SHF.R.U32.HI R6, RZ, 0x1, R4 ; /* 0x00000001ff067819 */
/* 0x000fc40000011604 */
/*0950*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0960*/ LOP3.LUT R5, R5, 0x1, R6, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef806 */
/*0970*/ LOP3.LUT R5, R5, R4, RZ, 0xc0, !PT ; /* 0x0000000405057212 */
/* 0x000fc800078ec0ff */
/*0980*/ IADD3 R5, R6, R5, RZ ; /* 0x0000000506057210 */
/* 0x000fc80007ffe0ff */
/*0990*/ LOP3.LUT R8, R5, R8, RZ, 0xfc, !PT ; /* 0x0000000805087212 */
/* 0x000fe200078efcff */
/*09a0*/ BRA 0x9f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09b0*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008087812 */
/* 0x000fc800078ec0ff */
/*09c0*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000008087812 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0x9f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09e0*/ IMAD R8, R7, 0x800000, R8 ; /* 0x0080000007087824 */
/* 0x000fe400078e0208 */
/*09f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0a10*/ LOP3.LUT R8, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008087812 */
/* 0x000fc800078e4805 */
/*0a20*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000008087812 */
/* 0x000fe200078efcff */
/*0a30*/ BRA 0xa90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R8, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008087812 */
/* 0x000fe200078e4805 */
/*0a50*/ BRA 0xa90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a60*/ MUFU.RSQ R8, -QNAN ; /* 0xffc0000000087908 */
/* 0x000e220000001400 */
/*0a70*/ BRA 0xa90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a80*/ FADD.FTZ R8, R6, 6.2831854820251464844 ; /* 0x40c90fdb06087421 */
/* 0x000fe40000010000 */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0ab0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0ac0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff53004007950 */
/* 0x000fea0003c3ffff */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12create_accumP6matrixS0_P7matrixf
.globl _Z12create_accumP6matrixS0_P7matrixf
.p2align 8
.type _Z12create_accumP6matrixS0_P7matrixf,@function
_Z12create_accumP6matrixS0_P7matrixf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s7, s[2:3], 0x0
s_and_b32 s8, s6, 0xffff
s_lshr_b32 s6, s6, 16
v_mad_u64_u32 v[3:4], null, s13, s8, v[1:2]
v_mad_u64_u32 v[1:2], null, s14, s6, v[5:6]
s_load_b64 s[2:3], s[2:3], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s7, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_mov_b32 s3, 0x3f50624d
s_mov_b32 s2, 0xd2f1a9fc
flat_load_b32 v2, v[4:5]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_mov_b32 s3, 0xbf50624d
v_cmp_gt_f64_e64 s2, s[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
v_add_f32_e32 v2, 0x40490fdb, v2
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[4:5], 0x10
v_bfe_u32 v0, v0, 20, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x41000000, v2
v_div_scale_f32 v4, null, 0x40c90fdb, 0x40c90fdb, v2
v_div_scale_f32 v7, vcc_lo, v2, 0x40c90fdb, v2
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v5, v4
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_load_b64 s[2:3], s[2:3], 0x10
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, 0x40c90fdb, v2
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
v_floor_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v4, v4, v0, 1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
flat_load_b32 v0, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_or_b32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
flat_load_b32 v4, v[4:5]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v2, v0, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v0, v4, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e64 s0, -1, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s1, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_load_b32 s0, s[2:3], 0x4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[2:3], 0x10
v_mad_u64_u32 v[3:4], null, s1, v2, v[0:1]
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
flat_atomic_add_u32 v[0:1], v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12create_accumP6matrixS0_P7matrixf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12create_accumP6matrixS0_P7matrixf, .Lfunc_end0-_Z12create_accumP6matrixS0_P7matrixf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12create_accumP6matrixS0_P7matrixf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12create_accumP6matrixS0_P7matrixf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00001291_00000000-6_hough_transform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12GetSubmatrix6matrixiii
.type _Z12GetSubmatrix6matrixiii, @function
_Z12GetSubmatrix6matrixiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12GetSubmatrix6matrixiii, .-_Z12GetSubmatrix6matrixiii
.globl _Z13GetSubmatrixf7matrixfiii
.type _Z13GetSubmatrixf7matrixfiii, @function
_Z13GetSubmatrixf7matrixfiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z13GetSubmatrixf7matrixfiii, .-_Z13GetSubmatrixf7matrixfiii
.globl _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf
.type _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf, @function
_Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12create_accumP6matrixS0_P7matrixf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf, .-_Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf
.globl _Z12create_accumP6matrixS0_P7matrixf
.type _Z12create_accumP6matrixS0_P7matrixf, @function
_Z12create_accumP6matrixS0_P7matrixf:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z12create_accumP6matrixS0_P7matrixfP6matrixS0_P7matrixf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z12create_accumP6matrixS0_P7matrixf, .-_Z12create_accumP6matrixS0_P7matrixf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12create_accumP6matrixS0_P7matrixf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12create_accumP6matrixS0_P7matrixf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hough_transform.hip"
.globl _Z27__device_stub__create_accumP6matrixS0_P7matrixf # -- Begin function _Z27__device_stub__create_accumP6matrixS0_P7matrixf
.p2align 4, 0x90
.type _Z27__device_stub__create_accumP6matrixS0_P7matrixf,@function
_Z27__device_stub__create_accumP6matrixS0_P7matrixf: # @_Z27__device_stub__create_accumP6matrixS0_P7matrixf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12create_accumP6matrixS0_P7matrixf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__create_accumP6matrixS0_P7matrixf, .Lfunc_end0-_Z27__device_stub__create_accumP6matrixS0_P7matrixf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12create_accumP6matrixS0_P7matrixf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12create_accumP6matrixS0_P7matrixf,@object # @_Z12create_accumP6matrixS0_P7matrixf
.section .rodata,"a",@progbits
.globl _Z12create_accumP6matrixS0_P7matrixf
.p2align 3, 0x0
_Z12create_accumP6matrixS0_P7matrixf:
.quad _Z27__device_stub__create_accumP6matrixS0_P7matrixf
.size _Z12create_accumP6matrixS0_P7matrixf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12create_accumP6matrixS0_P7matrixf"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__create_accumP6matrixS0_P7matrixf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12create_accumP6matrixS0_P7matrixf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 2 of 4: implement the kernel
__global__ void kernel( int *a, int dimx, int dimy ) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
a[i] = blockIdx.x * dimx + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[]) {
cudaSetDevice(MYDEVICE);
// Part 1 and 4 of 4: set the dimensions of the matrix
int dimx = 4;
int dimy = 4;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers
h_a = (int*)malloc(num_bytes);
//allocate memory on the device
cudaMalloc((void**) &d_a, dimx*dimy*num_bytes);
if( NULL==h_a || NULL==d_a ) {
fprintf(stderr,"couldn't allocate memory\n");
return 1;
}
// Part 2 of 4: define grid and block size and launch the kernel
dim3 grid, block;
block.x = dimx;
block.y = dimy;
grid.x = dimx;
grid.y = dimy;
kernel<<<grid, block>>>( d_a, dimx, dimy );
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// device to host copy
cudaMemcpy(h_a ,d_a, num_bytes ,cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// verify the data returned to the host is correct
for(int row=0; row<dimy; row++)
{
for(int col=0; col<dimx; col++)
assert(h_a[row * dimx + col] == row * dimx + col);
}
// free host memory
free( h_a );
// free device memory
cudaFree( d_a );
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(-1);
}
} | code for sm_80
Function : _Z6kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R5.reuse, c[0x0][0x0], R0.reuse ; /* 0x0000000005027a24 */
/* 0x141fe400078e0200 */
/*0060*/ IMAD R5, R5, c[0x0][0x168], R0 ; /* 0x00005a0005057a24 */
/* 0x000fc600078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 2 of 4: implement the kernel
__global__ void kernel( int *a, int dimx, int dimy ) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
a[i] = blockIdx.x * dimx + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[]) {
cudaSetDevice(MYDEVICE);
// Part 1 and 4 of 4: set the dimensions of the matrix
int dimx = 4;
int dimy = 4;
int num_bytes = dimx*dimy*sizeof(int);
int *d_a=0, *h_a=0; // device and host pointers
h_a = (int*)malloc(num_bytes);
//allocate memory on the device
cudaMalloc((void**) &d_a, dimx*dimy*num_bytes);
if( NULL==h_a || NULL==d_a ) {
fprintf(stderr,"couldn't allocate memory\n");
return 1;
}
// Part 2 of 4: define grid and block size and launch the kernel
dim3 grid, block;
block.x = dimx;
block.y = dimy;
grid.x = dimx;
grid.y = dimy;
kernel<<<grid, block>>>( d_a, dimx, dimy );
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// device to host copy
cudaMemcpy(h_a ,d_a, num_bytes ,cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// verify the data returned to the host is correct
for(int row=0; row<dimy; row++)
{
for(int col=0; col<dimx; col++)
assert(h_a[row * dimx + col] == row * dimx + col);
}
// free host memory
free( h_a );
// free device memory
cudaFree( d_a );
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(-1);
}
} | .file "tmpxft_0018e0b8_00000000-6_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z27__device_stub__Z6kernelPiiiPiii
.type _Z27__device_stub__Z6kernelPiiiPiii, @function
_Z27__device_stub__Z6kernelPiiiPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z6kernelPiiiPiii, .-_Z27__device_stub__Z6kernelPiiiPiii
.globl _Z6kernelPiii
.type _Z6kernelPiii, @function
_Z6kernelPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernelPiii, .-_Z6kernelPiii
.section .rodata.str1.1
.LC1:
.string "couldn't allocate memory\n"
.LC2:
.string "kernel execution"
.LC3:
.string "cudaMemcpy"
.LC4:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movq $0, 8(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testq %rbx, %rbx
je .L16
cmpq $0, 8(%rsp)
je .L16
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
call cudaThreadSynchronize@PLT
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L15:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L23
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L22:
movl $4, %edx
movl $4, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6kernelPiiiPiii
jmp .L19
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6kernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.