system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#ifndef USE_MALLOC_HOST
#define USE_MALLOC_HOST
#endif
#undef USE_MALLOC_HOST
#define CUDA_SAFE_CALL(err) __cudaSafeCall(err,__FILE__,__LINE__)
inline void __cudaSafeCall(cudaError_t err,const char *file, const int line) {
if(cudaSuccess != err) {
printf("%s(%i) : cudaSafeCall() Runtime API error : %s.\n",
file, line, cudaGetErrorString(err) );
exit(-1);
}
}
int main(int argc, char * argv[]) {
int numDevs=0, i, j, N, nBytes;
cudaError_t err;
cudaDeviceProp prop;
cudaEvent_t start, stop;
float *x_cpu, *y_cpu, *x_gpu;
float dt,totalDtTo=0.0,totalDtFrom=0.0;
/* create events */
CUDA_SAFE_CALL(cudaEventCreate(&start));
CUDA_SAFE_CALL(cudaEventCreate(&stop));
N = atoi(argv[1]);
nBytes = N*sizeof(float);
#ifdef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaMallocHost((void**)&x_cpu,nBytes));
CUDA_SAFE_CALL(cudaMallocHost((void**)&y_cpu,nBytes));
#else
x_cpu = (float *) malloc(nBytes);
y_cpu = (float *) malloc(nBytes);
#endif
for (i=0; i<N; ++i) {
x_cpu[i] = 1.0*i;
}
CUDA_SAFE_CALL(cudaGetDeviceCount(&numDevs));
printf("Number of CUDA Devices = %d\n",numDevs);
printf("===========================\n");
for (i=0; i<numDevs; ++i) {
CUDA_SAFE_CALL(cudaSetDevice(i));
CUDA_SAFE_CALL(cudaMalloc((void**)&x_gpu,nBytes));
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaHostRegister(x_cpu, nBytes, cudaHostRegisterMapped));
CUDA_SAFE_CALL(cudaHostRegister(y_cpu, nBytes, cudaHostRegisterMapped));
#endif
CUDA_SAFE_CALL(cudaGetDeviceProperties(&prop,i));
printf("Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n",i,prop.name,prop.major,prop.minor,prop.canMapHostMemory);
printf(" global memory = %1.5g\n",1.0*prop.totalGlobalMem/(1024*1024*1024));
dt=0.0;
CUDA_SAFE_CALL(cudaEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(cudaMemcpy(x_gpu, x_cpu, nBytes, cudaMemcpyHostToDevice));
}
CUDA_SAFE_CALL(cudaEventRecord(stop, 0));
CUDA_SAFE_CALL(cudaEventSynchronize(stop));
CUDA_SAFE_CALL(cudaEventElapsedTime(&dt,start,stop));
totalDtTo+=dt;
dt=0.0;
CUDA_SAFE_CALL(cudaEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(cudaMemcpy(y_cpu, x_gpu, nBytes, cudaMemcpyDeviceToHost));
}
CUDA_SAFE_CALL(cudaEventRecord(stop, 0));
CUDA_SAFE_CALL(cudaEventSynchronize(stop));
CUDA_SAFE_CALL(cudaEventElapsedTime(&dt,start,stop));
totalDtFrom+=dt;
totalDtTo*=.001;
totalDtFrom*=.001;
printf("HostToDevice PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtTo);
printf("DeviceToHost PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtFrom);
totalDtTo=0.0;
totalDtFrom=0.0;
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaHostUnregister(x_cpu));
CUDA_SAFE_CALL(cudaHostUnregister(y_cpu));
#endif
CUDA_SAFE_CALL(cudaFree(x_gpu));
}
#ifndef USE_MALLOC_HOST
free(x_cpu);
free(y_cpu);
#else
CUDA_SAFE_CALL(cudaFreeHost(x_cpu));
CUDA_SAFE_CALL(cudaFreeHost(y_cpu));
#endif
/* destroy events */
CUDA_SAFE_CALL(cudaEventDestroy(start));
CUDA_SAFE_CALL(cudaEventDestroy(stop));
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#ifndef USE_MALLOC_HOST
#define USE_MALLOC_HOST
#endif
#undef USE_MALLOC_HOST
#define CUDA_SAFE_CALL(err) __cudaSafeCall(err,__FILE__,__LINE__)
inline void __cudaSafeCall(cudaError_t err,const char *file, const int line) {
if(cudaSuccess != err) {
printf("%s(%i) : cudaSafeCall() Runtime API error : %s.\n",
file, line, cudaGetErrorString(err) );
exit(-1);
}
}
int main(int argc, char * argv[]) {
int numDevs=0, i, j, N, nBytes;
cudaError_t err;
cudaDeviceProp prop;
cudaEvent_t start, stop;
float *x_cpu, *y_cpu, *x_gpu;
float dt,totalDtTo=0.0,totalDtFrom=0.0;
/* create events */
CUDA_SAFE_CALL(cudaEventCreate(&start));
CUDA_SAFE_CALL(cudaEventCreate(&stop));
N = atoi(argv[1]);
nBytes = N*sizeof(float);
#ifdef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaMallocHost((void**)&x_cpu,nBytes));
CUDA_SAFE_CALL(cudaMallocHost((void**)&y_cpu,nBytes));
#else
x_cpu = (float *) malloc(nBytes);
y_cpu = (float *) malloc(nBytes);
#endif
for (i=0; i<N; ++i) {
x_cpu[i] = 1.0*i;
}
CUDA_SAFE_CALL(cudaGetDeviceCount(&numDevs));
printf("Number of CUDA Devices = %d\n",numDevs);
printf("===========================\n");
for (i=0; i<numDevs; ++i) {
CUDA_SAFE_CALL(cudaSetDevice(i));
CUDA_SAFE_CALL(cudaMalloc((void**)&x_gpu,nBytes));
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaHostRegister(x_cpu, nBytes, cudaHostRegisterMapped));
CUDA_SAFE_CALL(cudaHostRegister(y_cpu, nBytes, cudaHostRegisterMapped));
#endif
CUDA_SAFE_CALL(cudaGetDeviceProperties(&prop,i));
printf("Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n",i,prop.name,prop.major,prop.minor,prop.canMapHostMemory);
printf(" global memory = %1.5g\n",1.0*prop.totalGlobalMem/(1024*1024*1024));
dt=0.0;
CUDA_SAFE_CALL(cudaEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(cudaMemcpy(x_gpu, x_cpu, nBytes, cudaMemcpyHostToDevice));
}
CUDA_SAFE_CALL(cudaEventRecord(stop, 0));
CUDA_SAFE_CALL(cudaEventSynchronize(stop));
CUDA_SAFE_CALL(cudaEventElapsedTime(&dt,start,stop));
totalDtTo+=dt;
dt=0.0;
CUDA_SAFE_CALL(cudaEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(cudaMemcpy(y_cpu, x_gpu, nBytes, cudaMemcpyDeviceToHost));
}
CUDA_SAFE_CALL(cudaEventRecord(stop, 0));
CUDA_SAFE_CALL(cudaEventSynchronize(stop));
CUDA_SAFE_CALL(cudaEventElapsedTime(&dt,start,stop));
totalDtFrom+=dt;
totalDtTo*=.001;
totalDtFrom*=.001;
printf("HostToDevice PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtTo);
printf("DeviceToHost PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtFrom);
totalDtTo=0.0;
totalDtFrom=0.0;
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaHostUnregister(x_cpu));
CUDA_SAFE_CALL(cudaHostUnregister(y_cpu));
#endif
CUDA_SAFE_CALL(cudaFree(x_gpu));
}
#ifndef USE_MALLOC_HOST
free(x_cpu);
free(y_cpu);
#else
CUDA_SAFE_CALL(cudaFreeHost(x_cpu));
CUDA_SAFE_CALL(cudaFreeHost(y_cpu));
#endif
/* destroy events */
CUDA_SAFE_CALL(cudaEventDestroy(start));
CUDA_SAFE_CALL(cudaEventDestroy(stop));
return 0;
} | .file "tmpxft_000b93ac_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z14__cudaSafeCall9cudaErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "%s(%i) : cudaSafeCall() Runtime API error : %s.\n"
.section .text._Z14__cudaSafeCall9cudaErrorPKci,"axG",@progbits,_Z14__cudaSafeCall9cudaErrorPKci,comdat
.weak _Z14__cudaSafeCall9cudaErrorPKci
.type _Z14__cudaSafeCall9cudaErrorPKci, @function
_Z14__cudaSafeCall9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14__cudaSafeCall9cudaErrorPKci, .-_Z14__cudaSafeCall9cudaErrorPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/nricklin/ubuntu-gpu-test/master/test.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Number of CUDA Devices = %d\n"
.LC3:
.string "===========================\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n"
.align 8
.LC6:
.string " global memory = %1.5g\n"
.align 8
.LC10:
.string "HostToDevice PCI Express BW=%g GB/s\n"
.align 8
.LC11:
.string "DeviceToHost PCI Express BW=%g GB/s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movl $0, 16(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $29, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $30, %edx
movq %rbp, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
leal 0(,%rax,4), %r15d
movslq %r15d, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L10
leal -1(%rbx), %ecx
movl $0, %eax
.L11:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L11
.L10:
leaq 16(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, %edi
movl $46, %edx
leaq .LC1(%rip), %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl 16(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 16(%rsp)
jle .L12
movl $0, %r14d
jmp .L33
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $51, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $52, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $54, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $55, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $58, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L19:
mulsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0x00000000, 20(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L42
movl $100, %ebx
.L20:
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L43
subl $1, %ebx
jne .L20
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L44
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L45
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L46
pxor %xmm0, %xmm0
addss 20(%rsp), %xmm0
movss %xmm0, 12(%rsp)
movl $0x00000000, 20(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L47
movl $100, %ebx
.L25:
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
subl $1, %ebx
jne .L25
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L49
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L50
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L51
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
mulsd .LC8(%rip), %xmm0
pxor %xmm1, %xmm1
addss 20(%rsp), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC8(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movss %xmm2, 12(%rsp)
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
mulsd .LC9(%rip), %xmm1
mulsd .LC5(%rip), %xmm1
movq %xmm1, %rbx
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call cudaHostUnregister@PLT
testl %eax, %eax
jne .L52
movq %r13, %rdi
call cudaHostUnregister@PLT
testl %eax, %eax
jne .L53
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
addl $1, %r14d
cmpl %r14d, 16(%rsp)
jle .L12
.L33:
movl %r14d, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L55
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L56
movl $2, %edx
movq %rbp, %rsi
movq %r12, %rdi
call cudaHostRegister@PLT
testl %eax, %eax
jne .L57
movl $2, %edx
movq %rbp, %rsi
movq %r13, %rdi
call cudaHostRegister@PLT
testl %eax, %eax
jne .L58
leaq 48(%rsp), %rdi
movl %r14d, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L59
leaq 48(%rsp), %rcx
subq $8, %rsp
.cfi_def_cfa_offset 1160
movl 456(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1168
movl 428(%rsp), %r9d
movl 424(%rsp), %r8d
movl %r14d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1152
movq 336(%rsp), %rax
testq %rax, %rax
js .L18
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L19
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $63, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $65, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $67, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $68, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $69, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $73, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $75, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $77, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $78, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $79, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $91, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $92, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $94, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L12:
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
movl $106, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
movl $107, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1041235968
.align 8
.LC8:
.long -755914244
.long 1062232653
.align 8
.LC9:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#ifndef USE_MALLOC_HOST
#define USE_MALLOC_HOST
#endif
#undef USE_MALLOC_HOST
#define CUDA_SAFE_CALL(err) __cudaSafeCall(err,__FILE__,__LINE__)
inline void __cudaSafeCall(cudaError_t err,const char *file, const int line) {
if(cudaSuccess != err) {
printf("%s(%i) : cudaSafeCall() Runtime API error : %s.\n",
file, line, cudaGetErrorString(err) );
exit(-1);
}
}
int main(int argc, char * argv[]) {
int numDevs=0, i, j, N, nBytes;
cudaError_t err;
cudaDeviceProp prop;
cudaEvent_t start, stop;
float *x_cpu, *y_cpu, *x_gpu;
float dt,totalDtTo=0.0,totalDtFrom=0.0;
/* create events */
CUDA_SAFE_CALL(cudaEventCreate(&start));
CUDA_SAFE_CALL(cudaEventCreate(&stop));
N = atoi(argv[1]);
nBytes = N*sizeof(float);
#ifdef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaMallocHost((void**)&x_cpu,nBytes));
CUDA_SAFE_CALL(cudaMallocHost((void**)&y_cpu,nBytes));
#else
x_cpu = (float *) malloc(nBytes);
y_cpu = (float *) malloc(nBytes);
#endif
for (i=0; i<N; ++i) {
x_cpu[i] = 1.0*i;
}
CUDA_SAFE_CALL(cudaGetDeviceCount(&numDevs));
printf("Number of CUDA Devices = %d\n",numDevs);
printf("===========================\n");
for (i=0; i<numDevs; ++i) {
CUDA_SAFE_CALL(cudaSetDevice(i));
CUDA_SAFE_CALL(cudaMalloc((void**)&x_gpu,nBytes));
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaHostRegister(x_cpu, nBytes, cudaHostRegisterMapped));
CUDA_SAFE_CALL(cudaHostRegister(y_cpu, nBytes, cudaHostRegisterMapped));
#endif
CUDA_SAFE_CALL(cudaGetDeviceProperties(&prop,i));
printf("Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n",i,prop.name,prop.major,prop.minor,prop.canMapHostMemory);
printf(" global memory = %1.5g\n",1.0*prop.totalGlobalMem/(1024*1024*1024));
dt=0.0;
CUDA_SAFE_CALL(cudaEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(cudaMemcpy(x_gpu, x_cpu, nBytes, cudaMemcpyHostToDevice));
}
CUDA_SAFE_CALL(cudaEventRecord(stop, 0));
CUDA_SAFE_CALL(cudaEventSynchronize(stop));
CUDA_SAFE_CALL(cudaEventElapsedTime(&dt,start,stop));
totalDtTo+=dt;
dt=0.0;
CUDA_SAFE_CALL(cudaEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(cudaMemcpy(y_cpu, x_gpu, nBytes, cudaMemcpyDeviceToHost));
}
CUDA_SAFE_CALL(cudaEventRecord(stop, 0));
CUDA_SAFE_CALL(cudaEventSynchronize(stop));
CUDA_SAFE_CALL(cudaEventElapsedTime(&dt,start,stop));
totalDtFrom+=dt;
totalDtTo*=.001;
totalDtFrom*=.001;
printf("HostToDevice PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtTo);
printf("DeviceToHost PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtFrom);
totalDtTo=0.0;
totalDtFrom=0.0;
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(cudaHostUnregister(x_cpu));
CUDA_SAFE_CALL(cudaHostUnregister(y_cpu));
#endif
CUDA_SAFE_CALL(cudaFree(x_gpu));
}
#ifndef USE_MALLOC_HOST
free(x_cpu);
free(y_cpu);
#else
CUDA_SAFE_CALL(cudaFreeHost(x_cpu));
CUDA_SAFE_CALL(cudaFreeHost(y_cpu));
#endif
/* destroy events */
CUDA_SAFE_CALL(cudaEventDestroy(start));
CUDA_SAFE_CALL(cudaEventDestroy(stop));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#ifndef USE_MALLOC_HOST
#define USE_MALLOC_HOST
#endif
#undef USE_MALLOC_HOST
#define CUDA_SAFE_CALL(err) __cudaSafeCall(err,__FILE__,__LINE__)
inline void __cudaSafeCall(hipError_t err,const char *file, const int line) {
if(hipSuccess != err) {
printf("%s(%i) : cudaSafeCall() Runtime API error : %s.\n",
file, line, hipGetErrorString(err) );
exit(-1);
}
}
int main(int argc, char * argv[]) {
int numDevs=0, i, j, N, nBytes;
hipError_t err;
hipDeviceProp_t prop;
hipEvent_t start, stop;
float *x_cpu, *y_cpu, *x_gpu;
float dt,totalDtTo=0.0,totalDtFrom=0.0;
/* create events */
CUDA_SAFE_CALL(hipEventCreate(&start));
CUDA_SAFE_CALL(hipEventCreate(&stop));
N = atoi(argv[1]);
nBytes = N*sizeof(float);
#ifdef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostMalloc((void**)&x_cpu,nBytes, hipHostMallocDefault));
CUDA_SAFE_CALL(hipHostMalloc((void**)&y_cpu,nBytes, hipHostMallocDefault));
#else
x_cpu = (float *) malloc(nBytes);
y_cpu = (float *) malloc(nBytes);
#endif
for (i=0; i<N; ++i) {
x_cpu[i] = 1.0*i;
}
CUDA_SAFE_CALL(hipGetDeviceCount(&numDevs));
printf("Number of CUDA Devices = %d\n",numDevs);
printf("===========================\n");
for (i=0; i<numDevs; ++i) {
CUDA_SAFE_CALL(hipSetDevice(i));
CUDA_SAFE_CALL(hipMalloc((void**)&x_gpu,nBytes));
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostRegister(x_cpu, nBytes, hipHostRegisterMapped));
CUDA_SAFE_CALL(hipHostRegister(y_cpu, nBytes, hipHostRegisterMapped));
#endif
CUDA_SAFE_CALL(hipGetDeviceProperties(&prop,i));
printf("Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n",i,prop.name,prop.major,prop.minor,prop.canMapHostMemory);
printf(" global memory = %1.5g\n",1.0*prop.totalGlobalMem/(1024*1024*1024));
dt=0.0;
CUDA_SAFE_CALL(hipEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(hipMemcpy(x_gpu, x_cpu, nBytes, hipMemcpyHostToDevice));
}
CUDA_SAFE_CALL(hipEventRecord(stop, 0));
CUDA_SAFE_CALL(hipEventSynchronize(stop));
CUDA_SAFE_CALL(hipEventElapsedTime(&dt,start,stop));
totalDtTo+=dt;
dt=0.0;
CUDA_SAFE_CALL(hipEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(hipMemcpy(y_cpu, x_gpu, nBytes, hipMemcpyDeviceToHost));
}
CUDA_SAFE_CALL(hipEventRecord(stop, 0));
CUDA_SAFE_CALL(hipEventSynchronize(stop));
CUDA_SAFE_CALL(hipEventElapsedTime(&dt,start,stop));
totalDtFrom+=dt;
totalDtTo*=.001;
totalDtFrom*=.001;
printf("HostToDevice PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtTo);
printf("DeviceToHost PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtFrom);
totalDtTo=0.0;
totalDtFrom=0.0;
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostUnregister(x_cpu));
CUDA_SAFE_CALL(hipHostUnregister(y_cpu));
#endif
CUDA_SAFE_CALL(hipFree(x_gpu));
}
#ifndef USE_MALLOC_HOST
free(x_cpu);
free(y_cpu);
#else
CUDA_SAFE_CALL(hipHostFree(x_cpu));
CUDA_SAFE_CALL(hipHostFree(y_cpu));
#endif
/* destroy events */
CUDA_SAFE_CALL(hipEventDestroy(start));
CUDA_SAFE_CALL(hipEventDestroy(stop));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#ifndef USE_MALLOC_HOST
#define USE_MALLOC_HOST
#endif
#undef USE_MALLOC_HOST
#define CUDA_SAFE_CALL(err) __cudaSafeCall(err,__FILE__,__LINE__)
inline void __cudaSafeCall(hipError_t err,const char *file, const int line) {
if(hipSuccess != err) {
printf("%s(%i) : cudaSafeCall() Runtime API error : %s.\n",
file, line, hipGetErrorString(err) );
exit(-1);
}
}
int main(int argc, char * argv[]) {
int numDevs=0, i, j, N, nBytes;
hipError_t err;
hipDeviceProp_t prop;
hipEvent_t start, stop;
float *x_cpu, *y_cpu, *x_gpu;
float dt,totalDtTo=0.0,totalDtFrom=0.0;
/* create events */
CUDA_SAFE_CALL(hipEventCreate(&start));
CUDA_SAFE_CALL(hipEventCreate(&stop));
N = atoi(argv[1]);
nBytes = N*sizeof(float);
#ifdef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostMalloc((void**)&x_cpu,nBytes, hipHostMallocDefault));
CUDA_SAFE_CALL(hipHostMalloc((void**)&y_cpu,nBytes, hipHostMallocDefault));
#else
x_cpu = (float *) malloc(nBytes);
y_cpu = (float *) malloc(nBytes);
#endif
for (i=0; i<N; ++i) {
x_cpu[i] = 1.0*i;
}
CUDA_SAFE_CALL(hipGetDeviceCount(&numDevs));
printf("Number of CUDA Devices = %d\n",numDevs);
printf("===========================\n");
for (i=0; i<numDevs; ++i) {
CUDA_SAFE_CALL(hipSetDevice(i));
CUDA_SAFE_CALL(hipMalloc((void**)&x_gpu,nBytes));
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostRegister(x_cpu, nBytes, hipHostRegisterMapped));
CUDA_SAFE_CALL(hipHostRegister(y_cpu, nBytes, hipHostRegisterMapped));
#endif
CUDA_SAFE_CALL(hipGetDeviceProperties(&prop,i));
printf("Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n",i,prop.name,prop.major,prop.minor,prop.canMapHostMemory);
printf(" global memory = %1.5g\n",1.0*prop.totalGlobalMem/(1024*1024*1024));
dt=0.0;
CUDA_SAFE_CALL(hipEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(hipMemcpy(x_gpu, x_cpu, nBytes, hipMemcpyHostToDevice));
}
CUDA_SAFE_CALL(hipEventRecord(stop, 0));
CUDA_SAFE_CALL(hipEventSynchronize(stop));
CUDA_SAFE_CALL(hipEventElapsedTime(&dt,start,stop));
totalDtTo+=dt;
dt=0.0;
CUDA_SAFE_CALL(hipEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(hipMemcpy(y_cpu, x_gpu, nBytes, hipMemcpyDeviceToHost));
}
CUDA_SAFE_CALL(hipEventRecord(stop, 0));
CUDA_SAFE_CALL(hipEventSynchronize(stop));
CUDA_SAFE_CALL(hipEventElapsedTime(&dt,start,stop));
totalDtFrom+=dt;
totalDtTo*=.001;
totalDtFrom*=.001;
printf("HostToDevice PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtTo);
printf("DeviceToHost PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtFrom);
totalDtTo=0.0;
totalDtFrom=0.0;
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostUnregister(x_cpu));
CUDA_SAFE_CALL(hipHostUnregister(y_cpu));
#endif
CUDA_SAFE_CALL(hipFree(x_gpu));
}
#ifndef USE_MALLOC_HOST
free(x_cpu);
free(y_cpu);
#else
CUDA_SAFE_CALL(hipHostFree(x_cpu));
CUDA_SAFE_CALL(hipHostFree(y_cpu));
#endif
/* destroy events */
CUDA_SAFE_CALL(hipEventDestroy(start));
CUDA_SAFE_CALL(hipEventDestroy(stop));
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#ifndef USE_MALLOC_HOST
#define USE_MALLOC_HOST
#endif
#undef USE_MALLOC_HOST
#define CUDA_SAFE_CALL(err) __cudaSafeCall(err,__FILE__,__LINE__)
inline void __cudaSafeCall(hipError_t err,const char *file, const int line) {
if(hipSuccess != err) {
printf("%s(%i) : cudaSafeCall() Runtime API error : %s.\n",
file, line, hipGetErrorString(err) );
exit(-1);
}
}
int main(int argc, char * argv[]) {
int numDevs=0, i, j, N, nBytes;
hipError_t err;
hipDeviceProp_t prop;
hipEvent_t start, stop;
float *x_cpu, *y_cpu, *x_gpu;
float dt,totalDtTo=0.0,totalDtFrom=0.0;
/* create events */
CUDA_SAFE_CALL(hipEventCreate(&start));
CUDA_SAFE_CALL(hipEventCreate(&stop));
N = atoi(argv[1]);
nBytes = N*sizeof(float);
#ifdef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostMalloc((void**)&x_cpu,nBytes, hipHostMallocDefault));
CUDA_SAFE_CALL(hipHostMalloc((void**)&y_cpu,nBytes, hipHostMallocDefault));
#else
x_cpu = (float *) malloc(nBytes);
y_cpu = (float *) malloc(nBytes);
#endif
for (i=0; i<N; ++i) {
x_cpu[i] = 1.0*i;
}
CUDA_SAFE_CALL(hipGetDeviceCount(&numDevs));
printf("Number of CUDA Devices = %d\n",numDevs);
printf("===========================\n");
for (i=0; i<numDevs; ++i) {
CUDA_SAFE_CALL(hipSetDevice(i));
CUDA_SAFE_CALL(hipMalloc((void**)&x_gpu,nBytes));
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostRegister(x_cpu, nBytes, hipHostRegisterMapped));
CUDA_SAFE_CALL(hipHostRegister(y_cpu, nBytes, hipHostRegisterMapped));
#endif
CUDA_SAFE_CALL(hipGetDeviceProperties(&prop,i));
printf("Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n",i,prop.name,prop.major,prop.minor,prop.canMapHostMemory);
printf(" global memory = %1.5g\n",1.0*prop.totalGlobalMem/(1024*1024*1024));
dt=0.0;
CUDA_SAFE_CALL(hipEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(hipMemcpy(x_gpu, x_cpu, nBytes, hipMemcpyHostToDevice));
}
CUDA_SAFE_CALL(hipEventRecord(stop, 0));
CUDA_SAFE_CALL(hipEventSynchronize(stop));
CUDA_SAFE_CALL(hipEventElapsedTime(&dt,start,stop));
totalDtTo+=dt;
dt=0.0;
CUDA_SAFE_CALL(hipEventRecord(start, 0));
for (j=0; j<100; ++j) {
CUDA_SAFE_CALL(hipMemcpy(y_cpu, x_gpu, nBytes, hipMemcpyDeviceToHost));
}
CUDA_SAFE_CALL(hipEventRecord(stop, 0));
CUDA_SAFE_CALL(hipEventSynchronize(stop));
CUDA_SAFE_CALL(hipEventElapsedTime(&dt,start,stop));
totalDtFrom+=dt;
totalDtTo*=.001;
totalDtFrom*=.001;
printf("HostToDevice PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtTo);
printf("DeviceToHost PCI Express BW=%g GB/s\n",100.0*nBytes/(1024*1024*1024)/totalDtFrom);
totalDtTo=0.0;
totalDtFrom=0.0;
#ifndef USE_MALLOC_HOST
CUDA_SAFE_CALL(hipHostUnregister(x_cpu));
CUDA_SAFE_CALL(hipHostUnregister(y_cpu));
#endif
CUDA_SAFE_CALL(hipFree(x_gpu));
}
#ifndef USE_MALLOC_HOST
free(x_cpu);
free(y_cpu);
#else
CUDA_SAFE_CALL(hipHostFree(x_cpu));
CUDA_SAFE_CALL(hipHostFree(y_cpu));
#endif
/* destroy events */
CUDA_SAFE_CALL(hipEventDestroy(start));
CUDA_SAFE_CALL(hipEventDestroy(stop));
return 0;
} | .text
.file "test.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4059000000000000 # double 100
.LCPI0_1:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.LCPI0_4:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_2:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_3:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_5:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $0, 12(%rsp)
leaq 32(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit44
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
leal (,%rax,4), %ebp
movslq %ebp, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
testl %r12d, %r12d
jle .LBB0_8
# %bb.6: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_7
.LBB0_8: # %._crit_edge
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_9
# %bb.10: # %_Z14__cudaSafeCall10hipError_tPKci.exit46
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB0_53
# %bb.11: # %.lr.ph244
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
leaq 56(%rsp), %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_13: # =>This Loop Header: Depth=1
# Child Loop BB0_27 Depth 2
# Child Loop BB0_39 Depth 2
movl %r12d, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z14__cudaSafeCall10hipError_tPKci.exit48
# in Loop: Header=BB0_13 Depth=1
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit50
# in Loop: Header=BB0_13 Depth=1
movq %r14, %rdi
movq %rbx, %rsi
movl $2, %edx
callq hipHostRegister
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit52
# in Loop: Header=BB0_13 Depth=1
movq %r15, %rdi
movq %rbx, %rsi
movl $2, %edx
callq hipHostRegister
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z14__cudaSafeCall10hipError_tPKci.exit54
# in Loop: Header=BB0_13 Depth=1
movq %r13, %rdi
movl %r12d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_22
# %bb.23: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
# in Loop: Header=BB0_13 Depth=1
movl 416(%rsp), %ecx
movl 420(%rsp), %r8d
movl 456(%rsp), %r9d
movl $.L.str.3, %edi
movl %r12d, %esi
movq %r13, %rbp
movq %r13, %rdx
xorl %eax, %eax
callq printf
movsd 344(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_2(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_3(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $0, 8(%rsp)
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_25
# %bb.24: # %_Z14__cudaSafeCall10hipError_tPKci.exit60.preheader
# in Loop: Header=BB0_13 Depth=1
movl $100, %r13d
.p2align 4, 0x90
.LBB0_27: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
# Parent Loop BB0_13 Depth=1
# => This Inner Loop Header: Depth=2
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_28
# %bb.26: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
# in Loop: Header=BB0_27 Depth=2
decl %r13d
jne .LBB0_27
# %bb.29: # in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_30
# %bb.31: # %_Z14__cudaSafeCall10hipError_tPKci.exit62
# in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_32
# %bb.33: # %_Z14__cudaSafeCall10hipError_tPKci.exit64
# in Loop: Header=BB0_13 Depth=1
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_34
# %bb.35: # %_Z14__cudaSafeCall10hipError_tPKci.exit66
# in Loop: Header=BB0_13 Depth=1
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI0_5(%rip), %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
movl $0, 8(%rsp)
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_37
# %bb.36: # %_Z14__cudaSafeCall10hipError_tPKci.exit70.preheader
# in Loop: Header=BB0_13 Depth=1
movl $100, %r13d
.p2align 4, 0x90
.LBB0_39: # %_Z14__cudaSafeCall10hipError_tPKci.exit70
# Parent Loop BB0_13 Depth=1
# => This Inner Loop Header: Depth=2
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_40
# %bb.38: # %_Z14__cudaSafeCall10hipError_tPKci.exit68
# in Loop: Header=BB0_39 Depth=2
decl %r13d
jne .LBB0_39
# %bb.41: # in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_42
# %bb.43: # %_Z14__cudaSafeCall10hipError_tPKci.exit72
# in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_44
# %bb.45: # %_Z14__cudaSafeCall10hipError_tPKci.exit74
# in Loop: Header=BB0_13 Depth=1
movq %rbp, %r13
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_46
# %bb.47: # %_Z14__cudaSafeCall10hipError_tPKci.exit76
# in Loop: Header=BB0_13 Depth=1
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI0_5(%rip), %xmm0
movss 28(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movsd .LCPI0_4(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
mulsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
cvtss2sd %xmm1, %xmm1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %r14, %rdi
callq hipHostUnregister
testl %eax, %eax
jne .LBB0_48
# %bb.49: # %_Z14__cudaSafeCall10hipError_tPKci.exit78
# in Loop: Header=BB0_13 Depth=1
movq %r15, %rdi
callq hipHostUnregister
testl %eax, %eax
jne .LBB0_50
# %bb.51: # %_Z14__cudaSafeCall10hipError_tPKci.exit80
# in Loop: Header=BB0_13 Depth=1
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_52
# %bb.12: # in Loop: Header=BB0_13 Depth=1
incl %r12d
cmpl 12(%rsp), %r12d
jl .LBB0_13
.LBB0_53: # %._crit_edge245
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_54
# %bb.55: # %_Z14__cudaSafeCall10hipError_tPKci.exit84
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_56
# %bb.57: # %_Z14__cudaSafeCall10hipError_tPKci.exit86
xorl %eax, %eax
addq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_28:
.cfi_def_cfa_offset 1584
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $65, %edx
jmp .LBB0_2
.LBB0_40:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $75, %edx
.LBB0_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB0_25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $63, %edx
jmp .LBB0_2
.LBB0_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $58, %edx
jmp .LBB0_2
.LBB0_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $55, %edx
jmp .LBB0_2
.LBB0_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $54, %edx
jmp .LBB0_2
.LBB0_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $52, %edx
jmp .LBB0_2
.LBB0_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $51, %edx
jmp .LBB0_2
.LBB0_37:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $73, %edx
jmp .LBB0_2
.LBB0_34:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $69, %edx
jmp .LBB0_2
.LBB0_32:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $68, %edx
jmp .LBB0_2
.LBB0_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $67, %edx
jmp .LBB0_2
.LBB0_52:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $94, %edx
jmp .LBB0_2
.LBB0_50:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $92, %edx
jmp .LBB0_2
.LBB0_48:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $91, %edx
jmp .LBB0_2
.LBB0_46:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $79, %edx
jmp .LBB0_2
.LBB0_44:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $78, %edx
jmp .LBB0_2
.LBB0_42:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $77, %edx
jmp .LBB0_2
.LBB0_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $29, %edx
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $30, %edx
jmp .LBB0_2
.LBB0_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $46, %edx
jmp .LBB0_2
.LBB0_54:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $106, %edx
jmp .LBB0_2
.LBB0_56:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $107, %edx
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/nricklin/ubuntu-gpu-test/master/test.hip"
.size .L.str, 98
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of CUDA Devices = %d\n"
.size .L.str.1, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n"
.size .L.str.3, 73
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " global memory = %1.5g\n"
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "HostToDevice PCI Express BW=%g GB/s\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "DeviceToHost PCI Express BW=%g GB/s\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s(%i) : cudaSafeCall() Runtime API error : %s.\n"
.size .L.str.7, 49
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "==========================="
.size .Lstr, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b93ac_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z14__cudaSafeCall9cudaErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "%s(%i) : cudaSafeCall() Runtime API error : %s.\n"
.section .text._Z14__cudaSafeCall9cudaErrorPKci,"axG",@progbits,_Z14__cudaSafeCall9cudaErrorPKci,comdat
.weak _Z14__cudaSafeCall9cudaErrorPKci
.type _Z14__cudaSafeCall9cudaErrorPKci, @function
_Z14__cudaSafeCall9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14__cudaSafeCall9cudaErrorPKci, .-_Z14__cudaSafeCall9cudaErrorPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/nricklin/ubuntu-gpu-test/master/test.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Number of CUDA Devices = %d\n"
.LC3:
.string "===========================\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n"
.align 8
.LC6:
.string " global memory = %1.5g\n"
.align 8
.LC10:
.string "HostToDevice PCI Express BW=%g GB/s\n"
.align 8
.LC11:
.string "DeviceToHost PCI Express BW=%g GB/s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movl $0, 16(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $29, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $30, %edx
movq %rbp, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
leal 0(,%rax,4), %r15d
movslq %r15d, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L10
leal -1(%rbx), %ecx
movl $0, %eax
.L11:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L11
.L10:
leaq 16(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, %edi
movl $46, %edx
leaq .LC1(%rip), %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movl 16(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 16(%rsp)
jle .L12
movl $0, %r14d
jmp .L33
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $51, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $52, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $54, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $55, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $58, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L19:
mulsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0x00000000, 20(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L42
movl $100, %ebx
.L20:
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L43
subl $1, %ebx
jne .L20
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L44
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L45
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L46
pxor %xmm0, %xmm0
addss 20(%rsp), %xmm0
movss %xmm0, 12(%rsp)
movl $0x00000000, 20(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L47
movl $100, %ebx
.L25:
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
subl $1, %ebx
jne .L25
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L49
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L50
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L51
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
mulsd .LC8(%rip), %xmm0
pxor %xmm1, %xmm1
addss 20(%rsp), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC8(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movss %xmm2, 12(%rsp)
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
mulsd .LC9(%rip), %xmm1
mulsd .LC5(%rip), %xmm1
movq %xmm1, %rbx
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call cudaHostUnregister@PLT
testl %eax, %eax
jne .L52
movq %r13, %rdi
call cudaHostUnregister@PLT
testl %eax, %eax
jne .L53
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
addl $1, %r14d
cmpl %r14d, 16(%rsp)
jle .L12
.L33:
movl %r14d, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L55
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L56
movl $2, %edx
movq %rbp, %rsi
movq %r12, %rdi
call cudaHostRegister@PLT
testl %eax, %eax
jne .L57
movl $2, %edx
movq %rbp, %rsi
movq %r13, %rdi
call cudaHostRegister@PLT
testl %eax, %eax
jne .L58
leaq 48(%rsp), %rdi
movl %r14d, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L59
leaq 48(%rsp), %rcx
subq $8, %rsp
.cfi_def_cfa_offset 1160
movl 456(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1168
movl 428(%rsp), %r9d
movl 424(%rsp), %r8d
movl %r14d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1152
movq 336(%rsp), %rax
testq %rax, %rax
js .L18
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L19
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $63, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $65, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $67, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $68, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $69, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $73, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $75, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $77, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $78, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $79, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $91, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $92, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $94, %ecx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L12:
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
movl $106, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
movl $107, %edx
movq %rbx, %rsi
call _Z14__cudaSafeCall9cudaErrorPKci
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1041235968
.align 8
.LC8:
.long -755914244
.long 1062232653
.align 8
.LC9:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4059000000000000 # double 100
.LCPI0_1:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.LCPI0_4:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_2:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_3:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_5:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $0, 12(%rsp)
leaq 32(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit44
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
leal (,%rax,4), %ebp
movslq %ebp, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
testl %r12d, %r12d
jle .LBB0_8
# %bb.6: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_7
.LBB0_8: # %._crit_edge
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_9
# %bb.10: # %_Z14__cudaSafeCall10hipError_tPKci.exit46
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB0_53
# %bb.11: # %.lr.ph244
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
leaq 56(%rsp), %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_13: # =>This Loop Header: Depth=1
# Child Loop BB0_27 Depth 2
# Child Loop BB0_39 Depth 2
movl %r12d, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z14__cudaSafeCall10hipError_tPKci.exit48
# in Loop: Header=BB0_13 Depth=1
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit50
# in Loop: Header=BB0_13 Depth=1
movq %r14, %rdi
movq %rbx, %rsi
movl $2, %edx
callq hipHostRegister
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit52
# in Loop: Header=BB0_13 Depth=1
movq %r15, %rdi
movq %rbx, %rsi
movl $2, %edx
callq hipHostRegister
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z14__cudaSafeCall10hipError_tPKci.exit54
# in Loop: Header=BB0_13 Depth=1
movq %r13, %rdi
movl %r12d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_22
# %bb.23: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
# in Loop: Header=BB0_13 Depth=1
movl 416(%rsp), %ecx
movl 420(%rsp), %r8d
movl 456(%rsp), %r9d
movl $.L.str.3, %edi
movl %r12d, %esi
movq %r13, %rbp
movq %r13, %rdx
xorl %eax, %eax
callq printf
movsd 344(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_2(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_3(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $0, 8(%rsp)
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_25
# %bb.24: # %_Z14__cudaSafeCall10hipError_tPKci.exit60.preheader
# in Loop: Header=BB0_13 Depth=1
movl $100, %r13d
.p2align 4, 0x90
.LBB0_27: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
# Parent Loop BB0_13 Depth=1
# => This Inner Loop Header: Depth=2
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_28
# %bb.26: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
# in Loop: Header=BB0_27 Depth=2
decl %r13d
jne .LBB0_27
# %bb.29: # in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_30
# %bb.31: # %_Z14__cudaSafeCall10hipError_tPKci.exit62
# in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_32
# %bb.33: # %_Z14__cudaSafeCall10hipError_tPKci.exit64
# in Loop: Header=BB0_13 Depth=1
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_34
# %bb.35: # %_Z14__cudaSafeCall10hipError_tPKci.exit66
# in Loop: Header=BB0_13 Depth=1
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI0_5(%rip), %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
movl $0, 8(%rsp)
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_37
# %bb.36: # %_Z14__cudaSafeCall10hipError_tPKci.exit70.preheader
# in Loop: Header=BB0_13 Depth=1
movl $100, %r13d
.p2align 4, 0x90
.LBB0_39: # %_Z14__cudaSafeCall10hipError_tPKci.exit70
# Parent Loop BB0_13 Depth=1
# => This Inner Loop Header: Depth=2
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_40
# %bb.38: # %_Z14__cudaSafeCall10hipError_tPKci.exit68
# in Loop: Header=BB0_39 Depth=2
decl %r13d
jne .LBB0_39
# %bb.41: # in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_42
# %bb.43: # %_Z14__cudaSafeCall10hipError_tPKci.exit72
# in Loop: Header=BB0_13 Depth=1
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_44
# %bb.45: # %_Z14__cudaSafeCall10hipError_tPKci.exit74
# in Loop: Header=BB0_13 Depth=1
movq %rbp, %r13
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_46
# %bb.47: # %_Z14__cudaSafeCall10hipError_tPKci.exit76
# in Loop: Header=BB0_13 Depth=1
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI0_5(%rip), %xmm0
movss 28(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movsd .LCPI0_4(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
mulsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
cvtss2sd %xmm1, %xmm1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %r14, %rdi
callq hipHostUnregister
testl %eax, %eax
jne .LBB0_48
# %bb.49: # %_Z14__cudaSafeCall10hipError_tPKci.exit78
# in Loop: Header=BB0_13 Depth=1
movq %r15, %rdi
callq hipHostUnregister
testl %eax, %eax
jne .LBB0_50
# %bb.51: # %_Z14__cudaSafeCall10hipError_tPKci.exit80
# in Loop: Header=BB0_13 Depth=1
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_52
# %bb.12: # in Loop: Header=BB0_13 Depth=1
incl %r12d
cmpl 12(%rsp), %r12d
jl .LBB0_13
.LBB0_53: # %._crit_edge245
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_54
# %bb.55: # %_Z14__cudaSafeCall10hipError_tPKci.exit84
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_56
# %bb.57: # %_Z14__cudaSafeCall10hipError_tPKci.exit86
xorl %eax, %eax
addq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_28:
.cfi_def_cfa_offset 1584
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $65, %edx
jmp .LBB0_2
.LBB0_40:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $75, %edx
.LBB0_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB0_25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $63, %edx
jmp .LBB0_2
.LBB0_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $58, %edx
jmp .LBB0_2
.LBB0_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $55, %edx
jmp .LBB0_2
.LBB0_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $54, %edx
jmp .LBB0_2
.LBB0_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $52, %edx
jmp .LBB0_2
.LBB0_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $51, %edx
jmp .LBB0_2
.LBB0_37:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $73, %edx
jmp .LBB0_2
.LBB0_34:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $69, %edx
jmp .LBB0_2
.LBB0_32:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $68, %edx
jmp .LBB0_2
.LBB0_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $67, %edx
jmp .LBB0_2
.LBB0_52:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $94, %edx
jmp .LBB0_2
.LBB0_50:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $92, %edx
jmp .LBB0_2
.LBB0_48:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $91, %edx
jmp .LBB0_2
.LBB0_46:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $79, %edx
jmp .LBB0_2
.LBB0_44:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $78, %edx
jmp .LBB0_2
.LBB0_42:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $77, %edx
jmp .LBB0_2
.LBB0_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $29, %edx
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $30, %edx
jmp .LBB0_2
.LBB0_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $46, %edx
jmp .LBB0_2
.LBB0_54:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $106, %edx
jmp .LBB0_2
.LBB0_56:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movl $.L.str, %esi
movl $107, %edx
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/nricklin/ubuntu-gpu-test/master/test.hip"
.size .L.str, 98
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of CUDA Devices = %d\n"
.size .L.str.1, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device %d has name %s with compute capability %d.%d canMapHostMemory=%d\n"
.size .L.str.3, 73
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " global memory = %1.5g\n"
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "HostToDevice PCI Express BW=%g GB/s\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "DeviceToHost PCI Express BW=%g GB/s\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s(%i) : cudaSafeCall() Runtime API error : %s.\n"
.size .L.str.7, 49
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "==========================="
.size .Lstr, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void nllLoss_grad(int x_stride, float *yGrad, int* target, float* xGrad) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
xGrad[offset] += -1 * yGrad[tid];
} | code for sm_80
Function : _Z12nllLoss_gradiPfPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R4, R7, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R6, R4.reuse, c[0x0][0x160], R3 ; /* 0x0000580004067a24 */
/* 0x044fe400078e0203 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ FADD R9, -R4, R9 ; /* 0x0000000904097221 */
/* 0x004fca0000000100 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void nllLoss_grad(int x_stride, float *yGrad, int* target, float* xGrad) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
xGrad[offset] += -1 * yGrad[tid];
} | .file "tmpxft_00158cf4_00000000-6_nllLoss_grad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_
.type _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_, @function
_Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12nllLoss_gradiPfPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_, .-_Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_
.globl _Z12nllLoss_gradiPfPiS_
.type _Z12nllLoss_gradiPfPiS_, @function
_Z12nllLoss_gradiPfPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12nllLoss_gradiPfPiS_, .-_Z12nllLoss_gradiPfPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12nllLoss_gradiPfPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12nllLoss_gradiPfPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void nllLoss_grad(int x_stride, float *yGrad, int* target, float* xGrad) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
xGrad[offset] += -1 * yGrad[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nllLoss_grad(int x_stride, float *yGrad, int* target, float* xGrad) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
xGrad[offset] += -1 * yGrad[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nllLoss_grad(int x_stride, float *yGrad, int* target, float* xGrad) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
xGrad[offset] += -1 * yGrad[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12nllLoss_gradiPfPiS_
.globl _Z12nllLoss_gradiPfPiS_
.p2align 8
.type _Z12nllLoss_gradiPfPiS_,@function
_Z12nllLoss_gradiPfPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12nllLoss_gradiPfPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12nllLoss_gradiPfPiS_, .Lfunc_end0-_Z12nllLoss_gradiPfPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12nllLoss_gradiPfPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12nllLoss_gradiPfPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nllLoss_grad(int x_stride, float *yGrad, int* target, float* xGrad) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
xGrad[offset] += -1 * yGrad[tid];
} | .text
.file "nllLoss_grad.hip"
.globl _Z27__device_stub__nllLoss_gradiPfPiS_ # -- Begin function _Z27__device_stub__nllLoss_gradiPfPiS_
.p2align 4, 0x90
.type _Z27__device_stub__nllLoss_gradiPfPiS_,@function
_Z27__device_stub__nllLoss_gradiPfPiS_: # @_Z27__device_stub__nllLoss_gradiPfPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12nllLoss_gradiPfPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__nllLoss_gradiPfPiS_, .Lfunc_end0-_Z27__device_stub__nllLoss_gradiPfPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12nllLoss_gradiPfPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12nllLoss_gradiPfPiS_,@object # @_Z12nllLoss_gradiPfPiS_
.section .rodata,"a",@progbits
.globl _Z12nllLoss_gradiPfPiS_
.p2align 3, 0x0
_Z12nllLoss_gradiPfPiS_:
.quad _Z27__device_stub__nllLoss_gradiPfPiS_
.size _Z12nllLoss_gradiPfPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12nllLoss_gradiPfPiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__nllLoss_gradiPfPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12nllLoss_gradiPfPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12nllLoss_gradiPfPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R4, R7, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R6, R4.reuse, c[0x0][0x160], R3 ; /* 0x0000580004067a24 */
/* 0x044fe400078e0203 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ FADD R9, -R4, R9 ; /* 0x0000000904097221 */
/* 0x004fca0000000100 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12nllLoss_gradiPfPiS_
.globl _Z12nllLoss_gradiPfPiS_
.p2align 8
.type _Z12nllLoss_gradiPfPiS_,@function
_Z12nllLoss_gradiPfPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12nllLoss_gradiPfPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12nllLoss_gradiPfPiS_, .Lfunc_end0-_Z12nllLoss_gradiPfPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12nllLoss_gradiPfPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12nllLoss_gradiPfPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00158cf4_00000000-6_nllLoss_grad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_
.type _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_, @function
_Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12nllLoss_gradiPfPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_, .-_Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_
.globl _Z12nllLoss_gradiPfPiS_
.type _Z12nllLoss_gradiPfPiS_, @function
_Z12nllLoss_gradiPfPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12nllLoss_gradiPfPiS_iPfPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12nllLoss_gradiPfPiS_, .-_Z12nllLoss_gradiPfPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12nllLoss_gradiPfPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12nllLoss_gradiPfPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nllLoss_grad.hip"
.globl _Z27__device_stub__nllLoss_gradiPfPiS_ # -- Begin function _Z27__device_stub__nllLoss_gradiPfPiS_
.p2align 4, 0x90
.type _Z27__device_stub__nllLoss_gradiPfPiS_,@function
_Z27__device_stub__nllLoss_gradiPfPiS_: # @_Z27__device_stub__nllLoss_gradiPfPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12nllLoss_gradiPfPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__nllLoss_gradiPfPiS_, .Lfunc_end0-_Z27__device_stub__nllLoss_gradiPfPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12nllLoss_gradiPfPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12nllLoss_gradiPfPiS_,@object # @_Z12nllLoss_gradiPfPiS_
.section .rodata,"a",@progbits
.globl _Z12nllLoss_gradiPfPiS_
.p2align 3, 0x0
_Z12nllLoss_gradiPfPiS_:
.quad _Z27__device_stub__nllLoss_gradiPfPiS_
.size _Z12nllLoss_gradiPfPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12nllLoss_gradiPfPiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__nllLoss_gradiPfPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12nllLoss_gradiPfPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -x hip | FileCheck -check-prefix=ASAN %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -x hip \
// RUN: | FileCheck %s
// REQUIRES: amdgpu-registered-target
// ASAN-DAG: declare void @__amdgpu_device_library_preserve_asan_functions()
// ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant void ()* @__amdgpu_device_library_preserve_asan_functions
// ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr
// CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions_ptr | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -x hip | FileCheck -check-prefix=ASAN %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -x hip \
// RUN: | FileCheck %s
// REQUIRES: amdgpu-registered-target
// ASAN-DAG: declare void @__amdgpu_device_library_preserve_asan_functions()
// ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant void ()* @__amdgpu_device_library_preserve_asan_functions
// ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr
// CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions_ptr | .file "tmpxft_000ba7ae_00000000-6_amdgpu-asan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -x hip | FileCheck -check-prefix=ASAN %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -x hip \
// RUN: | FileCheck %s
// REQUIRES: amdgpu-registered-target
// ASAN-DAG: declare void @__amdgpu_device_library_preserve_asan_functions()
// ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant void ()* @__amdgpu_device_library_preserve_asan_functions
// ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr
// CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions_ptr | #include <hip/hip_runtime.h>
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -x hip | FileCheck -check-prefix=ASAN %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -x hip \
// RUN: | FileCheck %s
// REQUIRES: amdgpu-registered-target
// ASAN-DAG: declare void @__amdgpu_device_library_preserve_asan_functions()
// ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant void ()* @__amdgpu_device_library_preserve_asan_functions
// ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr
// CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions_ptr |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -x hip | FileCheck -check-prefix=ASAN %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -x hip \
// RUN: | FileCheck %s
// REQUIRES: amdgpu-registered-target
// ASAN-DAG: declare void @__amdgpu_device_library_preserve_asan_functions()
// ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant void ()* @__amdgpu_device_library_preserve_asan_functions
// ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr
// CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions_ptr | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
// RUN: -x hip | FileCheck -check-prefix=ASAN %s
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
// RUN: -fcuda-is-device -target-cpu gfx906 -x hip \
// RUN: | FileCheck %s
// REQUIRES: amdgpu-registered-target
// ASAN-DAG: declare void @__amdgpu_device_library_preserve_asan_functions()
// ASAN-DAG: @__amdgpu_device_library_preserve_asan_functions_ptr = weak addrspace(1) constant void ()* @__amdgpu_device_library_preserve_asan_functions
// ASAN-DAG: @llvm.compiler.used = {{.*}}@__amdgpu_device_library_preserve_asan_functions_ptr
// CHECK-NOT: @__amdgpu_device_library_preserve_asan_functions_ptr | .text
.file "amdgpu-asan.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ba7ae_00000000-6_amdgpu-asan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "amdgpu-asan.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
void printImg(int * img,int width,int height);
void copyImg(int *img ,int *h_img,int width ,int height);
__global__ void mandelKernel(float lowerX,float lowerY,int* d_img,int resX,int resY,float stepX,float stepY,int maxIterations) {
// To avoid error caused by the floating number, use the following pseudo code
int thisX = blockIdx.x * blockDim.x + threadIdx.x;
int thisY = blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x,c_im = y;
float z_re = x,z_im= y;
int i,count=0;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
//count ++;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_img[thisY*resX+thisX] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int imageSize = resX * resY * sizeof(int);
//int * h_img = (int*) malloc(imageSize);
int *d_img;
int BLOCK_SIZE_X = 16;
int BLOCK_SIZE_Y = 16;
cudaMalloc((void**)&d_img, resX * resY*sizeof(int));
dim3 blockSize(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 numBlock(resX / BLOCK_SIZE_X, resY / BLOCK_SIZE_Y);
//cudaMemcpy(d_img,img,resX*resY*sizeof(int),cudaMemcpyHostToDevice);
mandelKernel<<<numBlock, blockSize>>>(lowerX,lowerY,d_img,resX,resY,stepX,stepY,maxIterations);
cudaMemcpy(img,d_img,resX*resY*sizeof(int),cudaMemcpyDeviceToHost);
//printf("width %d height %d \n",resX,resY);
//printImg(img,resX,1);
cudaFree(d_img);
return ;
}
void copyImg(int *img ,int *h_img,int width ,int height){
for(int j=0;j<height;j++){
for(int i =0 ;i<width;i++){
img[j*width + i ] = h_img[j*width+i];
}
}
}
void printImg(int * img,int width,int height){
for(int j=0;j<height;j++){
for(int i=0;i<width;i++){
printf("%d ",img[j*height+i]);
}
printf("\n");
}
} | code for sm_80
Function : _Z12mandelKernelffPiiiffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000201400 */
/*0090*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ MOV R5, c[0x0][0x180] ; /* 0x0000600000057a02 */
/* 0x000fcc0000000f00 */
/*00b0*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x000e620000201400 */
/*00c0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f06270 */
/*00d0*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fca0000000f00 */
/*00e0*/ FFMA R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027623 */
/* 0x001fe20000000005 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0100*/ FFMA R4, R4, R7, c[0x0][0x164] ; /* 0x0000590004047623 */
/* 0x002fc80000000007 */
/*0110*/ @!P0 BRA 0x230 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x230 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0130*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc60000000f00 */
/*0160*/ FMUL R9, R7, R7 ; /* 0x0000000707097220 */
/* 0x000fe40000400000 */
/*0170*/ FMUL R8, R6, R6 ; /* 0x0000000606087220 */
/* 0x000fc80000400000 */
/*0180*/ FADD R10, R9, R8 ; /* 0x00000008090a7221 */
/* 0x000fca0000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f04000 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*01d0*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*01e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ FFMA R7, R6, R7, R4 ; /* 0x0000000706077223 */
/* 0x000fe40000000004 */
/*0200*/ FADD R6, R2, R9 ; /* 0x0000000902067221 */
/* 0x000fd40000000000 */
/*0210*/ @!P0 BRA 0x160 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*0250*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0260*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
void printImg(int * img,int width,int height);
void copyImg(int *img ,int *h_img,int width ,int height);
__global__ void mandelKernel(float lowerX,float lowerY,int* d_img,int resX,int resY,float stepX,float stepY,int maxIterations) {
// To avoid error caused by the floating number, use the following pseudo code
int thisX = blockIdx.x * blockDim.x + threadIdx.x;
int thisY = blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x,c_im = y;
float z_re = x,z_im= y;
int i,count=0;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
//count ++;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_img[thisY*resX+thisX] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int imageSize = resX * resY * sizeof(int);
//int * h_img = (int*) malloc(imageSize);
int *d_img;
int BLOCK_SIZE_X = 16;
int BLOCK_SIZE_Y = 16;
cudaMalloc((void**)&d_img, resX * resY*sizeof(int));
dim3 blockSize(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 numBlock(resX / BLOCK_SIZE_X, resY / BLOCK_SIZE_Y);
//cudaMemcpy(d_img,img,resX*resY*sizeof(int),cudaMemcpyHostToDevice);
mandelKernel<<<numBlock, blockSize>>>(lowerX,lowerY,d_img,resX,resY,stepX,stepY,maxIterations);
cudaMemcpy(img,d_img,resX*resY*sizeof(int),cudaMemcpyDeviceToHost);
//printf("width %d height %d \n",resX,resY);
//printImg(img,resX,1);
cudaFree(d_img);
return ;
}
void copyImg(int *img ,int *h_img,int width ,int height){
for(int j=0;j<height;j++){
for(int i =0 ;i<width;i++){
img[j*width + i ] = h_img[j*width+i];
}
}
}
void printImg(int * img,int width,int height){
for(int j=0;j<height;j++){
for(int i=0;i<width;i++){
printf("%d ",img[j*height+i]);
}
printf("\n");
}
} | .file "tmpxft_0000178b_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7copyImgPiS_ii
.type _Z7copyImgPiS_ii, @function
_Z7copyImgPiS_ii:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r8
movq %rsi, %r9
movl $0, %r11d
movl $0, %r10d
movslq %edx, %rbx
jmp .L5
.L7:
movslq %r11d, %rdi
leaq 0(,%rdi,4), %rax
addq %rbx, %rdi
salq $2, %rdi
.L6:
movl (%r9,%rax), %esi
movl %esi, (%r8,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L6
.L8:
addl $1, %r10d
addl %edx, %r11d
cmpl %r10d, %ecx
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
ret
.cfi_endproc
.LFE2058:
.size _Z7copyImgPiS_ii, .-_Z7copyImgPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z8printImgPiii
.type _Z8printImgPiii, @function
_Z8printImgPiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %edx, %edx
jle .L14
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L16
.L18:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L17:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
.L19:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, %r15d
je .L14
.L16:
cmpl $0, 12(%rsp)
jg .L18
jmp .L19
.L14:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8printImgPiii, .-_Z8printImgPiii
.globl _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
.type _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi, @function
_Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movq %rdi, 32(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelffPiiiffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi, .-_Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
.globl _Z12mandelKernelffPiiiffi
.type _Z12mandelKernelffPiiiffi, @function
_Z12mandelKernelffPiiiffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12mandelKernelffPiiiffi, .-_Z12mandelKernelffPiiiffi
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r13
movl %esi, %ebx
movl %edx, %ebp
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %r12d
imull %edx, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
leal 15(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $4, %eax
movl %eax, 44(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L31:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movss 4(%rsp), %xmm3
movss 12(%rsp), %xmm4
subss %xmm4, %xmm3
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
movss (%rsp), %xmm2
movss 8(%rsp), %xmm5
subss %xmm5, %xmm2
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movl %r14d, %ecx
divss %xmm1, %xmm3
divss %xmm0, %xmm2
movl %ebp, %edx
movl %ebx, %esi
movq 24(%rsp), %rdi
movaps %xmm4, %xmm1
movaps %xmm5, %xmm0
call _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1
.LC2:
.string "_Z12mandelKernelffPiiiffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelffPiiiffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
void printImg(int * img,int width,int height);
void copyImg(int *img ,int *h_img,int width ,int height);
__global__ void mandelKernel(float lowerX,float lowerY,int* d_img,int resX,int resY,float stepX,float stepY,int maxIterations) {
// To avoid error caused by the floating number, use the following pseudo code
int thisX = blockIdx.x * blockDim.x + threadIdx.x;
int thisY = blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x,c_im = y;
float z_re = x,z_im= y;
int i,count=0;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
//count ++;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_img[thisY*resX+thisX] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int imageSize = resX * resY * sizeof(int);
//int * h_img = (int*) malloc(imageSize);
int *d_img;
int BLOCK_SIZE_X = 16;
int BLOCK_SIZE_Y = 16;
cudaMalloc((void**)&d_img, resX * resY*sizeof(int));
dim3 blockSize(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 numBlock(resX / BLOCK_SIZE_X, resY / BLOCK_SIZE_Y);
//cudaMemcpy(d_img,img,resX*resY*sizeof(int),cudaMemcpyHostToDevice);
mandelKernel<<<numBlock, blockSize>>>(lowerX,lowerY,d_img,resX,resY,stepX,stepY,maxIterations);
cudaMemcpy(img,d_img,resX*resY*sizeof(int),cudaMemcpyDeviceToHost);
//printf("width %d height %d \n",resX,resY);
//printImg(img,resX,1);
cudaFree(d_img);
return ;
}
void copyImg(int *img ,int *h_img,int width ,int height){
for(int j=0;j<height;j++){
for(int i =0 ;i<width;i++){
img[j*width + i ] = h_img[j*width+i];
}
}
}
void printImg(int * img,int width,int height){
for(int j=0;j<height;j++){
for(int i=0;i<width;i++){
printf("%d ",img[j*height+i]);
}
printf("\n");
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void printImg(int * img,int width,int height);
void copyImg(int *img ,int *h_img,int width ,int height);
__global__ void mandelKernel(float lowerX,float lowerY,int* d_img,int resX,int resY,float stepX,float stepY,int maxIterations) {
// To avoid error caused by the floating number, use the following pseudo code
int thisX = blockIdx.x * blockDim.x + threadIdx.x;
int thisY = blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x,c_im = y;
float z_re = x,z_im= y;
int i,count=0;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
//count ++;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_img[thisY*resX+thisX] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int imageSize = resX * resY * sizeof(int);
//int * h_img = (int*) malloc(imageSize);
int *d_img;
int BLOCK_SIZE_X = 16;
int BLOCK_SIZE_Y = 16;
hipMalloc((void**)&d_img, resX * resY*sizeof(int));
dim3 blockSize(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 numBlock(resX / BLOCK_SIZE_X, resY / BLOCK_SIZE_Y);
//cudaMemcpy(d_img,img,resX*resY*sizeof(int),cudaMemcpyHostToDevice);
mandelKernel<<<numBlock, blockSize>>>(lowerX,lowerY,d_img,resX,resY,stepX,stepY,maxIterations);
hipMemcpy(img,d_img,resX*resY*sizeof(int),hipMemcpyDeviceToHost);
//printf("width %d height %d \n",resX,resY);
//printImg(img,resX,1);
hipFree(d_img);
return ;
}
void copyImg(int *img ,int *h_img,int width ,int height){
for(int j=0;j<height;j++){
for(int i =0 ;i<width;i++){
img[j*width + i ] = h_img[j*width+i];
}
}
}
void printImg(int * img,int width,int height){
for(int j=0;j<height;j++){
for(int i=0;i<width;i++){
printf("%d ",img[j*height+i]);
}
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void printImg(int * img,int width,int height);
void copyImg(int *img ,int *h_img,int width ,int height);
__global__ void mandelKernel(float lowerX,float lowerY,int* d_img,int resX,int resY,float stepX,float stepY,int maxIterations) {
// To avoid error caused by the floating number, use the following pseudo code
int thisX = blockIdx.x * blockDim.x + threadIdx.x;
int thisY = blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x,c_im = y;
float z_re = x,z_im= y;
int i,count=0;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
//count ++;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_img[thisY*resX+thisX] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int imageSize = resX * resY * sizeof(int);
//int * h_img = (int*) malloc(imageSize);
int *d_img;
int BLOCK_SIZE_X = 16;
int BLOCK_SIZE_Y = 16;
hipMalloc((void**)&d_img, resX * resY*sizeof(int));
dim3 blockSize(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 numBlock(resX / BLOCK_SIZE_X, resY / BLOCK_SIZE_Y);
//cudaMemcpy(d_img,img,resX*resY*sizeof(int),cudaMemcpyHostToDevice);
mandelKernel<<<numBlock, blockSize>>>(lowerX,lowerY,d_img,resX,resY,stepX,stepY,maxIterations);
hipMemcpy(img,d_img,resX*resY*sizeof(int),hipMemcpyDeviceToHost);
//printf("width %d height %d \n",resX,resY);
//printImg(img,resX,1);
hipFree(d_img);
return ;
}
void copyImg(int *img ,int *h_img,int width ,int height){
for(int j=0;j<height;j++){
for(int i =0 ;i<width;i++){
img[j*width + i ] = h_img[j*width+i];
}
}
}
void printImg(int * img,int width,int height){
for(int j=0;j<height;j++){
for(int i=0;i<width;i++){
printf("%d ",img[j*height+i]);
}
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelffPiiiffi
.globl _Z12mandelKernelffPiiiffi
.p2align 8
.type _Z12mandelKernelffPiiiffi,@function
_Z12mandelKernelffPiiiffi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, s6, s4
v_fma_f32 v3, v3, s7, s5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v2
v_mov_b32_e32 v4, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v6
s_or_b32 s5, s5, exec_lo
v_fma_f32 v5, v4, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mul_f32 v5, v4, v4 :: v_dual_add_f32 v6, v6, v6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, s4
v_sub_f32_e32 v7, v7, v5
s_cselect_b32 s7, -1, 0
v_mov_b32_e32 v5, s2
v_fma_f32 v4, v4, v6, v3
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v5, 0
.LBB0_7:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelffPiiiffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelffPiiiffi, .Lfunc_end0-_Z12mandelKernelffPiiiffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelffPiiiffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelffPiiiffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void printImg(int * img,int width,int height);
void copyImg(int *img ,int *h_img,int width ,int height);
__global__ void mandelKernel(float lowerX,float lowerY,int* d_img,int resX,int resY,float stepX,float stepY,int maxIterations) {
// To avoid error caused by the floating number, use the following pseudo code
int thisX = blockIdx.x * blockDim.x + threadIdx.x;
int thisY = blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x,c_im = y;
float z_re = x,z_im= y;
int i,count=0;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
//count ++;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_img[thisY*resX+thisX] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int imageSize = resX * resY * sizeof(int);
//int * h_img = (int*) malloc(imageSize);
int *d_img;
int BLOCK_SIZE_X = 16;
int BLOCK_SIZE_Y = 16;
hipMalloc((void**)&d_img, resX * resY*sizeof(int));
dim3 blockSize(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 numBlock(resX / BLOCK_SIZE_X, resY / BLOCK_SIZE_Y);
//cudaMemcpy(d_img,img,resX*resY*sizeof(int),cudaMemcpyHostToDevice);
mandelKernel<<<numBlock, blockSize>>>(lowerX,lowerY,d_img,resX,resY,stepX,stepY,maxIterations);
hipMemcpy(img,d_img,resX*resY*sizeof(int),hipMemcpyDeviceToHost);
//printf("width %d height %d \n",resX,resY);
//printImg(img,resX,1);
hipFree(d_img);
return ;
}
void copyImg(int *img ,int *h_img,int width ,int height){
for(int j=0;j<height;j++){
for(int i =0 ;i<width;i++){
img[j*width + i ] = h_img[j*width+i];
}
}
}
void printImg(int * img,int width,int height){
for(int j=0;j<height;j++){
for(int i=0;i<width;i++){
printf("%d ",img[j*height+i]);
}
printf("\n");
}
} | .text
.file "kernel1.hip"
.globl _Z27__device_stub__mandelKernelffPiiiffi # -- Begin function _Z27__device_stub__mandelKernelffPiiiffi
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelffPiiiffi,@function
_Z27__device_stub__mandelKernelffPiiiffi: # @_Z27__device_stub__mandelKernelffPiiiffi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mandelKernelffPiiiffi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelffPiiiffi, .Lfunc_end0-_Z27__device_stub__mandelKernelffPiiiffi
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
movss %xmm3, 16(%rsp) # 4-byte Spill
movss %xmm2, 12(%rsp) # 4-byte Spill
movss %xmm1, 24(%rsp) # 4-byte Spill
movss %xmm0, 20(%rsp) # 4-byte Spill
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r14
shlq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
testl %r12d, %r12d
cmovnsl %r12d, %eax
sarl $4, %eax
leal 15(%r15), %edi
testl %r15d, %r15d
cmovnsl %r15d, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss 24(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
subss %xmm3, %xmm2
xorps %xmm1, %xmm1
cvtsi2ss %r12d, %xmm1
divss %xmm0, %xmm2
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
subss %xmm4, %xmm0
divss %xmm1, %xmm0
movq (%rsp), %rax
movss %xmm4, 52(%rsp)
movss %xmm3, 48(%rsp)
movq %rax, 104(%rsp)
movl %r12d, 44(%rsp)
movl %r15d, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm2, 32(%rsp)
movl %ebp, 28(%rsp)
leaq 52(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12mandelKernelffPiiiffi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.globl _Z7copyImgPiS_ii # -- Begin function _Z7copyImgPiS_ii
.p2align 4, 0x90
.type _Z7copyImgPiS_ii,@function
_Z7copyImgPiS_ii: # @_Z7copyImgPiS_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %edx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r9
addl %edx, %r8d
cmpq %rax, %r9
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %edx, %edx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r8d, %r11d
leaq (%rdi,%r11,4), %r10
leaq (%rsi,%r11,4), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r11,%rbx,4), %ebp
movl %ebp, (%r10,%rbx,4)
incq %rbx
cmpq %rbx, %rcx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB2_7: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z7copyImgPiS_ii, .Lfunc_end2-_Z7copyImgPiS_ii
.cfi_endproc
# -- End function
.globl _Z8printImgPiii # -- Begin function _Z8printImgPiii
.p2align 4, 0x90
.type _Z8printImgPiii,@function
_Z8printImgPiii: # @_Z8printImgPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebx, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z8printImgPiii, .Lfunc_end3-_Z8printImgPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelffPiiiffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelffPiiiffi,@object # @_Z12mandelKernelffPiiiffi
.section .rodata,"a",@progbits
.globl _Z12mandelKernelffPiiiffi
.p2align 3, 0x0
_Z12mandelKernelffPiiiffi:
.quad _Z27__device_stub__mandelKernelffPiiiffi
.size _Z12mandelKernelffPiiiffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12mandelKernelffPiiiffi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelffPiiiffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelffPiiiffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12mandelKernelffPiiiffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000201400 */
/*0090*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ MOV R5, c[0x0][0x180] ; /* 0x0000600000057a02 */
/* 0x000fcc0000000f00 */
/*00b0*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x000e620000201400 */
/*00c0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f06270 */
/*00d0*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fca0000000f00 */
/*00e0*/ FFMA R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027623 */
/* 0x001fe20000000005 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0100*/ FFMA R4, R4, R7, c[0x0][0x164] ; /* 0x0000590004047623 */
/* 0x002fc80000000007 */
/*0110*/ @!P0 BRA 0x230 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x230 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0130*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc60000000f00 */
/*0160*/ FMUL R9, R7, R7 ; /* 0x0000000707097220 */
/* 0x000fe40000400000 */
/*0170*/ FMUL R8, R6, R6 ; /* 0x0000000606087220 */
/* 0x000fc80000400000 */
/*0180*/ FADD R10, R9, R8 ; /* 0x00000008090a7221 */
/* 0x000fca0000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f04000 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*01d0*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*01e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ FFMA R7, R6, R7, R4 ; /* 0x0000000706077223 */
/* 0x000fe40000000004 */
/*0200*/ FADD R6, R2, R9 ; /* 0x0000000902067221 */
/* 0x000fd40000000000 */
/*0210*/ @!P0 BRA 0x160 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0200 */
/*0250*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0260*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelffPiiiffi
.globl _Z12mandelKernelffPiiiffi
.p2align 8
.type _Z12mandelKernelffPiiiffi,@function
_Z12mandelKernelffPiiiffi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, s6, s4
v_fma_f32 v3, v3, s7, s5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v2
v_mov_b32_e32 v4, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v6
s_or_b32 s5, s5, exec_lo
v_fma_f32 v5, v4, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mul_f32 v5, v4, v4 :: v_dual_add_f32 v6, v6, v6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, s4
v_sub_f32_e32 v7, v7, v5
s_cselect_b32 s7, -1, 0
v_mov_b32_e32 v5, s2
v_fma_f32 v4, v4, v6, v3
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v5, 0
.LBB0_7:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelffPiiiffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelffPiiiffi, .Lfunc_end0-_Z12mandelKernelffPiiiffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelffPiiiffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelffPiiiffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000178b_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7copyImgPiS_ii
.type _Z7copyImgPiS_ii, @function
_Z7copyImgPiS_ii:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r8
movq %rsi, %r9
movl $0, %r11d
movl $0, %r10d
movslq %edx, %rbx
jmp .L5
.L7:
movslq %r11d, %rdi
leaq 0(,%rdi,4), %rax
addq %rbx, %rdi
salq $2, %rdi
.L6:
movl (%r9,%rax), %esi
movl %esi, (%r8,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L6
.L8:
addl $1, %r10d
addl %edx, %r11d
cmpl %r10d, %ecx
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
ret
.cfi_endproc
.LFE2058:
.size _Z7copyImgPiS_ii, .-_Z7copyImgPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z8printImgPiii
.type _Z8printImgPiii, @function
_Z8printImgPiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %edx, %edx
jle .L14
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L16
.L18:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L17:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
.L19:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, %r15d
je .L14
.L16:
cmpl $0, 12(%rsp)
jg .L18
jmp .L19
.L14:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8printImgPiii, .-_Z8printImgPiii
.globl _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
.type _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi, @function
_Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movq %rdi, 32(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelffPiiiffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi, .-_Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
.globl _Z12mandelKernelffPiiiffi
.type _Z12mandelKernelffPiiiffi, @function
_Z12mandelKernelffPiiiffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12mandelKernelffPiiiffi, .-_Z12mandelKernelffPiiiffi
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r13
movl %esi, %ebx
movl %edx, %ebp
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %r12d
imull %edx, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
leal 15(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $4, %eax
movl %eax, 44(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L31:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movss 4(%rsp), %xmm3
movss 12(%rsp), %xmm4
subss %xmm4, %xmm3
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
movss (%rsp), %xmm2
movss 8(%rsp), %xmm5
subss %xmm5, %xmm2
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movl %r14d, %ecx
divss %xmm1, %xmm3
divss %xmm0, %xmm2
movl %ebp, %edx
movl %ebx, %esi
movq 24(%rsp), %rdi
movaps %xmm4, %xmm1
movaps %xmm5, %xmm0
call _Z39__device_stub__Z12mandelKernelffPiiiffiffPiiiffi
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1
.LC2:
.string "_Z12mandelKernelffPiiiffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelffPiiiffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel1.hip"
.globl _Z27__device_stub__mandelKernelffPiiiffi # -- Begin function _Z27__device_stub__mandelKernelffPiiiffi
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelffPiiiffi,@function
_Z27__device_stub__mandelKernelffPiiiffi: # @_Z27__device_stub__mandelKernelffPiiiffi
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mandelKernelffPiiiffi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelffPiiiffi, .Lfunc_end0-_Z27__device_stub__mandelKernelffPiiiffi
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
movss %xmm3, 16(%rsp) # 4-byte Spill
movss %xmm2, 12(%rsp) # 4-byte Spill
movss %xmm1, 24(%rsp) # 4-byte Spill
movss %xmm0, 20(%rsp) # 4-byte Spill
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r14
shlq $2, %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
testl %r12d, %r12d
cmovnsl %r12d, %eax
sarl $4, %eax
leal 15(%r15), %edi
testl %r15d, %r15d
cmovnsl %r15d, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss 24(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
subss %xmm3, %xmm2
xorps %xmm1, %xmm1
cvtsi2ss %r12d, %xmm1
divss %xmm0, %xmm2
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
subss %xmm4, %xmm0
divss %xmm1, %xmm0
movq (%rsp), %rax
movss %xmm4, 52(%rsp)
movss %xmm3, 48(%rsp)
movq %rax, 104(%rsp)
movl %r12d, 44(%rsp)
movl %r15d, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm2, 32(%rsp)
movl %ebp, 28(%rsp)
leaq 52(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12mandelKernelffPiiiffi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.globl _Z7copyImgPiS_ii # -- Begin function _Z7copyImgPiS_ii
.p2align 4, 0x90
.type _Z7copyImgPiS_ii,@function
_Z7copyImgPiS_ii: # @_Z7copyImgPiS_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %edx, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r9
addl %edx, %r8d
cmpq %rax, %r9
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %edx, %edx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r8d, %r11d
leaq (%rdi,%r11,4), %r10
leaq (%rsi,%r11,4), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r11,%rbx,4), %ebp
movl %ebp, (%r10,%rbx,4)
incq %rbx
cmpq %rbx, %rcx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB2_7: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z7copyImgPiS_ii, .Lfunc_end2-_Z7copyImgPiS_ii
.cfi_endproc
# -- End function
.globl _Z8printImgPiii # -- Begin function _Z8printImgPiii
.p2align 4, 0x90
.type _Z8printImgPiii,@function
_Z8printImgPiii: # @_Z8printImgPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebx, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z8printImgPiii, .Lfunc_end3-_Z8printImgPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelffPiiiffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelffPiiiffi,@object # @_Z12mandelKernelffPiiiffi
.section .rodata,"a",@progbits
.globl _Z12mandelKernelffPiiiffi
.p2align 3, 0x0
_Z12mandelKernelffPiiiffi:
.quad _Z27__device_stub__mandelKernelffPiiiffi
.size _Z12mandelKernelffPiiiffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12mandelKernelffPiiiffi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelffPiiiffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelffPiiiffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
void init(float *x, int s){
int i=0;
for(i=0; i<s; i++){
x[i]=1.0f * (float)i;
}
}
__global__
void compute(float *x, float *y, int s){
int i=0;
for(i=0; i<s; i++){
y[i]= x[i]*x[i];
}
}
int main(){
int N = 1<<20;
float *x;// = malloc(sizeof(float)*N);
float *y;// = malloc(sizeof(float)*N);
cudaMallocManaged(&x, sizeof(float)*N);
cudaMallocManaged(&y, sizeof(float)*N);
init(x, N);
init(y, N);
int i=0;
compute<<<1,1>>>(x, y, N);
cudaDeviceSynchronize();
for(i=0; i<N; i++){
printf("%d %f %f\n", i, x[i], y[i]);
}
} | code for sm_80
Function : _Z7computePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x8f0 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fd60000000f00 */
/*0110*/ @!P0 BRA 0x780 ; /* 0x0000066000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x510 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FMUL R7, R7, R7 ; /* 0x0000000707077220 */
/* 0x004fca0000400000 */
/*0180*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0190*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*01b0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0003e8000c10190a */
/*01c0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*01e0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0005e8000c10190a */
/*01f0*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0200*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*0210*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0007e8000c10190a */
/*0220*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000e24000c1e1900 */
/*0230*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*0240*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0001e8000c10190a */
/*0250*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e64000c1e1900 */
/*0260*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*0270*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0003e8000c10190a */
/*0280*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*02a0*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x0005e8000c10190a */
/*02b0*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x000ee4000c1e1900 */
/*02c0*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*02d0*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0007e8000c10190a */
/*02e0*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000e24000c1e1900 */
/*02f0*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*0300*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0001e8000c10190a */
/*0310*/ LDG.E R8, [R2.64+0x24] ; /* 0x0000240a02087981 */
/* 0x000e64000c1e1900 */
/*0320*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*0330*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0003e8000c10190a */
/*0340*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280a02087981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0360*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0005e8000c10190a */
/*0370*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0380*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*0390*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x000fe8000c10190a */
/*03a0*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000e24000c1e1900 */
/*03b0*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*03c0*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0001e8000c10190a */
/*03d0*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340a02087981 */
/* 0x000e64000c1e1900 */
/*03e0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*03f0*/ STG.E [R4.64+0x34], R9 ; /* 0x0000340904007986 */
/* 0x000fe8000c10190a */
/*0400*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380a02087981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0420*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0430*/ STG.E [R4.64+0x38], R11 ; /* 0x0000380b04007986 */
/* 0x000fe8000c10190a */
/*0440*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0a02087981 */
/* 0x0002a2000c1e1900 */
/*0450*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0460*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0470*/ IADD3 R7, P3, R4, 0x40, RZ ; /* 0x0000004004077810 */
/* 0x001fe40007f7e0ff */
/*0480*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*0490*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x002fe400017fe4ff */
/*04a0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*04b0*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x004fe40000400000 */
/*04c0*/ IMAD.X R8, RZ, RZ, R5, P3 ; /* 0x000000ffff087224 */
/* 0x000fc600018e0605 */
/*04d0*/ STG.E [R4.64+0x3c], R13 ; /* 0x00003c0d04007986 */
/* 0x0001e4000c10190a */
/*04e0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*04f0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0500*/ @P1 BRA 0x160 ; /* 0xfffffc5000001947 */
/* 0x000fea000383ffff */
/*0510*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0520*/ @!P1 BRA 0x760 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*0530*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea4000c1e1900 */
/*0540*/ FMUL R7, R7, R7 ; /* 0x0000000707077220 */
/* 0x004fca0000400000 */
/*0550*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0560*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*0580*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0003e8000c10190a */
/*0590*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*05b0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0005e8000c10190a */
/*05c0*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ee4000c1e1900 */
/*05d0*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*05e0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*05f0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000e24000c1e1900 */
/*0600*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*0610*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0001e8000c10190a */
/*0620*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e64000c1e1900 */
/*0630*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*0640*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0003e8000c10190a */
/*0650*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000ea4000c1e1900 */
/*0660*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0670*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0680*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x0004e2000c1e1900 */
/*0690*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fe20007f3e0ff */
/*06a0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*06b0*/ IADD3 R7, P2, R4, 0x20, RZ ; /* 0x0000002004077810 */
/* 0x001fe40007f5e0ff */
/*06c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*06d0*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x002fe200008e0603 */
/*06e0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x004fc600078e000a */
/*0700*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x000fe20000000f00 */
/*0710*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fe20000400000 */
/*0720*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*0730*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0001e4000c10190a */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*0750*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe40000000f00 */
/*0760*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0770*/ @!P0 BRA 0x8f0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea4000c1e1900 */
/*0790*/ FMUL R7, R7, R7 ; /* 0x0000000707077220 */
/* 0x004fca0000400000 */
/*07a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*07b0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*07c0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*07d0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*07e0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0800*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0810*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*0820*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x0002a2000c1e1900 */
/*0830*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0840*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0850*/ IADD3 R7, P2, R4, 0x10, RZ ; /* 0x0000001004077810 */
/* 0x001fe40007f5e0ff */
/*0860*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fca0007f3e0ff */
/*0870*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x002fe200008e0603 */
/*0880*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0890*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x004fe20000400000 */
/*08a0*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*08b0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e4000c10190a */
/*08c0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*08d0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*08e0*/ @P0 BRA 0x780 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*08f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0900*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0910*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0920*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0930*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*0940*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0950*/ UIMAD.WIDE UR4, UR4, UR5, UR8 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0208 */
/*0960*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fca000f8e00ff */
/*0980*/ LDG.E R2, [R2.64] ; /* 0x0000000a02027981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ UIADD3 UR4, UP1, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff3e03f */
/*09b0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x001fe20008000f00 */
/*09c0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*09d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*09e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; /* 0x000000053f057290 */
/* 0x000fe20008ffe43f */
/*09f0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe20008000f00 */
/*0a00*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a10*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0a20*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0a30*/ @P0 BRA 0x960 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0a40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
void init(float *x, int s){
int i=0;
for(i=0; i<s; i++){
x[i]=1.0f * (float)i;
}
}
__global__
void compute(float *x, float *y, int s){
int i=0;
for(i=0; i<s; i++){
y[i]= x[i]*x[i];
}
}
int main(){
int N = 1<<20;
float *x;// = malloc(sizeof(float)*N);
float *y;// = malloc(sizeof(float)*N);
cudaMallocManaged(&x, sizeof(float)*N);
cudaMallocManaged(&y, sizeof(float)*N);
init(x, N);
init(y, N);
int i=0;
compute<<<1,1>>>(x, y, N);
cudaDeviceSynchronize();
for(i=0; i<N; i++){
printf("%d %f %f\n", i, x[i], y[i]);
}
} | .file "tmpxft_00030643_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPfi
.type _Z4initPfi, @function
_Z4initPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z4initPfi, .-_Z4initPfi
.globl _Z29__device_stub__Z7computePfS_iPfS_i
.type _Z29__device_stub__Z7computePfS_iPfS_i, @function
_Z29__device_stub__Z7computePfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7computePfS_iPfS_i, .-_Z29__device_stub__Z7computePfS_iPfS_i
.globl _Z7computePfS_i
.type _Z7computePfS_i, @function
_Z7computePfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7computePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computePfS_i, .-_Z7computePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $1048576, %esi
movq (%rsp), %rdi
call _Z4initPfi
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z4initPfi
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L17:
movq (%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq 8(%rsp), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1048576, %rbx
jne .L17
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $1048576, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7computePfS_iPfS_i
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z7computePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
void init(float *x, int s){
int i=0;
for(i=0; i<s; i++){
x[i]=1.0f * (float)i;
}
}
__global__
void compute(float *x, float *y, int s){
int i=0;
for(i=0; i<s; i++){
y[i]= x[i]*x[i];
}
}
int main(){
int N = 1<<20;
float *x;// = malloc(sizeof(float)*N);
float *y;// = malloc(sizeof(float)*N);
cudaMallocManaged(&x, sizeof(float)*N);
cudaMallocManaged(&y, sizeof(float)*N);
init(x, N);
init(y, N);
int i=0;
compute<<<1,1>>>(x, y, N);
cudaDeviceSynchronize();
for(i=0; i<N; i++){
printf("%d %f %f\n", i, x[i], y[i]);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void init(float *x, int s){
int i=0;
for(i=0; i<s; i++){
x[i]=1.0f * (float)i;
}
}
__global__
void compute(float *x, float *y, int s){
int i=0;
for(i=0; i<s; i++){
y[i]= x[i]*x[i];
}
}
int main(){
int N = 1<<20;
float *x;// = malloc(sizeof(float)*N);
float *y;// = malloc(sizeof(float)*N);
hipMallocManaged(&x, sizeof(float)*N);
hipMallocManaged(&y, sizeof(float)*N);
init(x, N);
init(y, N);
int i=0;
compute<<<1,1>>>(x, y, N);
hipDeviceSynchronize();
for(i=0; i<N; i++){
printf("%d %f %f\n", i, x[i], y[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void init(float *x, int s){
int i=0;
for(i=0; i<s; i++){
x[i]=1.0f * (float)i;
}
}
__global__
void compute(float *x, float *y, int s){
int i=0;
for(i=0; i<s; i++){
y[i]= x[i]*x[i];
}
}
int main(){
int N = 1<<20;
float *x;// = malloc(sizeof(float)*N);
float *y;// = malloc(sizeof(float)*N);
hipMallocManaged(&x, sizeof(float)*N);
hipMallocManaged(&y, sizeof(float)*N);
init(x, N);
init(y, N);
int i=0;
compute<<<1,1>>>(x, y, N);
hipDeviceSynchronize();
for(i=0; i<N; i++){
printf("%d %f %f\n", i, x[i], y[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfS_i
.globl _Z7computePfS_i
.p2align 8
.type _Z7computePfS_i,@function
_Z7computePfS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfS_i, .Lfunc_end0-_Z7computePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z7computePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void init(float *x, int s){
int i=0;
for(i=0; i<s; i++){
x[i]=1.0f * (float)i;
}
}
__global__
void compute(float *x, float *y, int s){
int i=0;
for(i=0; i<s; i++){
y[i]= x[i]*x[i];
}
}
int main(){
int N = 1<<20;
float *x;// = malloc(sizeof(float)*N);
float *y;// = malloc(sizeof(float)*N);
hipMallocManaged(&x, sizeof(float)*N);
hipMallocManaged(&y, sizeof(float)*N);
init(x, N);
init(y, N);
int i=0;
compute<<<1,1>>>(x, y, N);
hipDeviceSynchronize();
for(i=0; i<N; i++){
printf("%d %f %f\n", i, x[i], y[i]);
}
} | .text
.file "add.hip"
.globl _Z4initPfi # -- Begin function _Z4initPfi
.p2align 4, 0x90
.type _Z4initPfi,@function
_Z4initPfi: # @_Z4initPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4initPfi, .Lfunc_end0-_Z4initPfi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfS_i # -- Begin function _Z22__device_stub__computePfS_i
.p2align 4, 0x90
.type _Z22__device_stub__computePfS_i,@function
_Z22__device_stub__computePfS_i: # @_Z22__device_stub__computePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__computePfS_i, .Lfunc_end1-_Z22__device_stub__computePfS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 16(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rcx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_1
# %bb.2: # %_Z4initPfi.exit
movq 8(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB2_3
# %bb.4: # %_Z4initPfi.exit18
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1048576, 28(%rsp) # imm = 0x100000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computePfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB2_7
# %bb.8:
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePfS_i,@object # @_Z7computePfS_i
.section .rodata,"a",@progbits
.globl _Z7computePfS_i
.p2align 3, 0x0
_Z7computePfS_i:
.quad _Z22__device_stub__computePfS_i
.size _Z7computePfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f %f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x8f0 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fd60000000f00 */
/*0110*/ @!P0 BRA 0x780 ; /* 0x0000066000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x510 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FMUL R7, R7, R7 ; /* 0x0000000707077220 */
/* 0x004fca0000400000 */
/*0180*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0190*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*01b0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0003e8000c10190a */
/*01c0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*01e0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0005e8000c10190a */
/*01f0*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0200*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*0210*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0007e8000c10190a */
/*0220*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000e24000c1e1900 */
/*0230*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*0240*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0001e8000c10190a */
/*0250*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e64000c1e1900 */
/*0260*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*0270*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0003e8000c10190a */
/*0280*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*02a0*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x0005e8000c10190a */
/*02b0*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x000ee4000c1e1900 */
/*02c0*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*02d0*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0007e8000c10190a */
/*02e0*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000e24000c1e1900 */
/*02f0*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*0300*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0001e8000c10190a */
/*0310*/ LDG.E R8, [R2.64+0x24] ; /* 0x0000240a02087981 */
/* 0x000e64000c1e1900 */
/*0320*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*0330*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0003e8000c10190a */
/*0340*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280a02087981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0360*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0005e8000c10190a */
/*0370*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0380*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*0390*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x000fe8000c10190a */
/*03a0*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000e24000c1e1900 */
/*03b0*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*03c0*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0001e8000c10190a */
/*03d0*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340a02087981 */
/* 0x000e64000c1e1900 */
/*03e0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*03f0*/ STG.E [R4.64+0x34], R9 ; /* 0x0000340904007986 */
/* 0x000fe8000c10190a */
/*0400*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380a02087981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0420*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0430*/ STG.E [R4.64+0x38], R11 ; /* 0x0000380b04007986 */
/* 0x000fe8000c10190a */
/*0440*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0a02087981 */
/* 0x0002a2000c1e1900 */
/*0450*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0460*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0470*/ IADD3 R7, P3, R4, 0x40, RZ ; /* 0x0000004004077810 */
/* 0x001fe40007f7e0ff */
/*0480*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*0490*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x002fe400017fe4ff */
/*04a0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*04b0*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x004fe40000400000 */
/*04c0*/ IMAD.X R8, RZ, RZ, R5, P3 ; /* 0x000000ffff087224 */
/* 0x000fc600018e0605 */
/*04d0*/ STG.E [R4.64+0x3c], R13 ; /* 0x00003c0d04007986 */
/* 0x0001e4000c10190a */
/*04e0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*04f0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0500*/ @P1 BRA 0x160 ; /* 0xfffffc5000001947 */
/* 0x000fea000383ffff */
/*0510*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0520*/ @!P1 BRA 0x760 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*0530*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea4000c1e1900 */
/*0540*/ FMUL R7, R7, R7 ; /* 0x0000000707077220 */
/* 0x004fca0000400000 */
/*0550*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0560*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*0580*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0003e8000c10190a */
/*0590*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*05b0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0005e8000c10190a */
/*05c0*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ee4000c1e1900 */
/*05d0*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*05e0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*05f0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000e24000c1e1900 */
/*0600*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x001fca0000400000 */
/*0610*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0001e8000c10190a */
/*0620*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e64000c1e1900 */
/*0630*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x002fca0000400000 */
/*0640*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0003e8000c10190a */
/*0650*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000ea4000c1e1900 */
/*0660*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0670*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0680*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x0004e2000c1e1900 */
/*0690*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fe20007f3e0ff */
/*06a0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*06b0*/ IADD3 R7, P2, R4, 0x20, RZ ; /* 0x0000002004077810 */
/* 0x001fe40007f5e0ff */
/*06c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*06d0*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x002fe200008e0603 */
/*06e0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x004fc600078e000a */
/*0700*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x000fe20000000f00 */
/*0710*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fe20000400000 */
/*0720*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*0730*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0001e4000c10190a */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*0750*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe40000000f00 */
/*0760*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0770*/ @!P0 BRA 0x8f0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea4000c1e1900 */
/*0790*/ FMUL R7, R7, R7 ; /* 0x0000000707077220 */
/* 0x004fca0000400000 */
/*07a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*07b0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*07c0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*07d0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*07e0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0800*/ FMUL R11, R8, R8 ; /* 0x00000008080b7220 */
/* 0x004fca0000400000 */
/*0810*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*0820*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x0002a2000c1e1900 */
/*0830*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0840*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0850*/ IADD3 R7, P2, R4, 0x10, RZ ; /* 0x0000001004077810 */
/* 0x001fe40007f5e0ff */
/*0860*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fca0007f3e0ff */
/*0870*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x002fe200008e0603 */
/*0880*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0890*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x004fe20000400000 */
/*08a0*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*08b0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e4000c10190a */
/*08c0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*08d0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*08e0*/ @P0 BRA 0x780 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*08f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0900*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0910*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0920*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0930*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*0940*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0950*/ UIMAD.WIDE UR4, UR4, UR5, UR8 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0208 */
/*0960*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fca000f8e00ff */
/*0980*/ LDG.E R2, [R2.64] ; /* 0x0000000a02027981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ UIADD3 UR4, UP1, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff3e03f */
/*09b0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x001fe20008000f00 */
/*09c0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*09d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*09e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; /* 0x000000053f057290 */
/* 0x000fe20008ffe43f */
/*09f0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe20008000f00 */
/*0a00*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a10*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0a20*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0a30*/ @P0 BRA 0x960 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0a40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfS_i
.globl _Z7computePfS_i
.p2align 8
.type _Z7computePfS_i,@function
_Z7computePfS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfS_i, .Lfunc_end0-_Z7computePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z7computePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00030643_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPfi
.type _Z4initPfi, @function
_Z4initPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z4initPfi, .-_Z4initPfi
.globl _Z29__device_stub__Z7computePfS_iPfS_i
.type _Z29__device_stub__Z7computePfS_iPfS_i, @function
_Z29__device_stub__Z7computePfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7computePfS_iPfS_i, .-_Z29__device_stub__Z7computePfS_iPfS_i
.globl _Z7computePfS_i
.type _Z7computePfS_i, @function
_Z7computePfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7computePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computePfS_i, .-_Z7computePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $1048576, %esi
movq (%rsp), %rdi
call _Z4initPfi
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z4initPfi
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L17:
movq (%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq 8(%rsp), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1048576, %rbx
jne .L17
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $1048576, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7computePfS_iPfS_i
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z7computePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z4initPfi # -- Begin function _Z4initPfi
.p2align 4, 0x90
.type _Z4initPfi,@function
_Z4initPfi: # @_Z4initPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4initPfi, .Lfunc_end0-_Z4initPfi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfS_i # -- Begin function _Z22__device_stub__computePfS_i
.p2align 4, 0x90
.type _Z22__device_stub__computePfS_i,@function
_Z22__device_stub__computePfS_i: # @_Z22__device_stub__computePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__computePfS_i, .Lfunc_end1-_Z22__device_stub__computePfS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 16(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rcx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_1
# %bb.2: # %_Z4initPfi.exit
movq 8(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB2_3
# %bb.4: # %_Z4initPfi.exit18
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1048576, 28(%rsp) # imm = 0x100000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computePfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB2_7
# %bb.8:
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePfS_i,@object # @_Z7computePfS_i
.section .rodata,"a",@progbits
.globl _Z7computePfS_i
.p2align 3, 0x0
_Z7computePfS_i:
.quad _Z22__device_stub__computePfS_i
.size _Z7computePfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f %f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void interleave(float* input, float* output, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads) {
output[2 * i] = input[i];
output[2 * i + 1] = input[size + 2 + i];
}
} | code for sm_80
Function : _Z10interleavePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x430 ; /* 0x000003a000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.IADD R2, R0.reuse, 0x1, R3 ; /* 0x0000000100027824 */
/* 0x040fe200078e0203 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0220*/ LOP3.LUT P1, R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */
/* 0x000fc8000782c0ff */
/*0230*/ IADD3 R2, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x000fd20007ffe0ff */
/*0240*/ @!P1 BRA 0x420 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0250*/ SHF.L.U32 R4, R3.reuse, 0x1, RZ ; /* 0x0000000103047819 */
/* 0x040fe200000006ff */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0270*/ SHF.R.S32.HI R7, RZ, 0x1f, R3 ; /* 0x0000001fff077819 */
/* 0x000fe40000011403 */
/*0280*/ IADD3 R9, P1, R3, R2, RZ ; /* 0x0000000203097210 */
/* 0x000fe20007f3e0ff */
/*0290*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e020b */
/*02a0*/ MOV R14, R6 ; /* 0x00000006000e7202 */
/* 0x000fe40000000f00 */
/*02b0*/ LEA.HI.X.SX32 R10, R2, R7, 0x1, P1 ; /* 0x00000007020a7211 */
/* 0x000fe400008f0eff */
/*02c0*/ IADD3 R16, P1, R4, 0x4, RZ ; /* 0x0000000404107810 */
/* 0x000fc40007f3e0ff */
/*02d0*/ LEA R8, P2, R9.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580009087a11 */
/* 0x040fe400078410ff */
/*02e0*/ SHF.L.U32 R15, R0, 0x1, RZ ; /* 0x00000001000f7819 */
/* 0x000fe200000006ff */
/*02f0*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0605 */
/*0300*/ LEA.HI.X R9, R9, c[0x0][0x164], R10, 0x2, P2 ; /* 0x0000590009097a11 */
/* 0x000fe200010f140a */
/*0310*/ IMAD.WIDE R4, R3, R11, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e020b */
/*0320*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x001ea2000c1e1900 */
/*0330*/ IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0010 */
/*0340*/ MOV R11, R7 ; /* 0x00000007000b7202 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0360*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fc60000000f00 */
/*0370*/ STG.E [R10.64+-0x4], R17 ; /* 0xfffffc110a007986 */
/* 0x0041e8000c101904 */
/*0380*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE R6, R15, 0x4, R10 ; /* 0x000000040f067825 */
/* 0x000fe200078e020a */
/*03b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*03d0*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0006 */
/*03f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x000fe200078e0204 */
/*0400*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0041ea000c101904 */
/*0410*/ @P1 BRA 0x320 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x000fe400078e00ff */
/*0450*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x004fd400000001ff */
/*0460*/ IMAD.WIDE R6, R3, R9, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0209 */
/*0470*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.SHL.U32 R8, R3, 0x2, RZ ; /* 0x0000000203087824 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.WIDE R10, R2, 0x4, R6 ; /* 0x00000004020a7825 */
/* 0x001fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*04b0*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0041e8000c101904 */
/*04c0*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*04e0*/ STG.E [R8.64+0x4], R21 ; /* 0x0000041508007986 */
/* 0x0043e8000c101904 */
/*04f0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IMAD.WIDE R14, R4, 0x4, R8 ; /* 0x00000004040e7825 */
/* 0x000fc800078e0208 */
/*0510*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x040fe200078e020a */
/*0520*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0045e8000c101904 */
/*0530*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000ee2000c1e1900 */
/*0540*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc600078e020c */
/*0550*/ STG.E [R14.64+0x4], R25 ; /* 0x000004190e007986 */
/* 0x0085e8000c101904 */
/*0560*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD.WIDE R10, R4, 0x4, R14 ; /* 0x00000004040a7825 */
/* 0x000fc800078e020e */
/*0580*/ IMAD.WIDE R18, R0.reuse, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x040fe200078e0210 */
/*0590*/ STG.E [R10.64], R5 ; /* 0x000000050a007986 */
/* 0x0085e8000c101904 */
/*05a0*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x002ee2000c1e1900 */
/*05b0*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc600078e0206 */
/*05c0*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0085e8000c101904 */
/*05d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fc800078e020a */
/*05f0*/ IMAD.WIDE R16, R0.reuse, 0x4, R18 ; /* 0x0000000400107825 */
/* 0x040fe200078e0212 */
/*0600*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0085ea000c101904 */
/*0610*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee2000c1e1900 */
/*0620*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0630*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0640*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0650*/ STG.E [R12.64+0x4], R17 ; /* 0x000004110c007986 */
/* 0x0085d8000c101904 */
/*0660*/ @!P0 BRA 0x450 ; /* 0xfffffde000008947 */
/* 0x000fea000383ffff */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ BRA 0x680; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void interleave(float* input, float* output, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads) {
output[2 * i] = input[i];
output[2 * i + 1] = input[size + 2 + i];
}
} | .file "tmpxft_0014527d_00000000-6_interleave.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10interleavePfS_iPfS_i
.type _Z33__device_stub__Z10interleavePfS_iPfS_i, @function
_Z33__device_stub__Z10interleavePfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10interleavePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10interleavePfS_iPfS_i, .-_Z33__device_stub__Z10interleavePfS_iPfS_i
.globl _Z10interleavePfS_i
.type _Z10interleavePfS_i, @function
_Z10interleavePfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10interleavePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10interleavePfS_i, .-_Z10interleavePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10interleavePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10interleavePfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void interleave(float* input, float* output, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads) {
output[2 * i] = input[i];
output[2 * i + 1] = input[size + 2 + i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void interleave(float* input, float* output, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads) {
output[2 * i] = input[i];
output[2 * i + 1] = input[size + 2 + i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void interleave(float* input, float* output, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads) {
output[2 * i] = input[i];
output[2 * i + 1] = input[size + 2 + i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10interleavePfS_i
.globl _Z10interleavePfS_i
.p2align 8
.type _Z10interleavePfS_i,@function
_Z10interleavePfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s1, s10, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_lshlrev_b32_e32 v2, 1, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b32 s11, s2, 1
s_lshl_b64 s[8:9], s[2:3], 2
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
global_load_b32 v0, v[4:5], off
v_add_nc_u32_e32 v6, s1, v1
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v8, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v0, off
global_load_b32 v0, v[6:7], off
v_add_nc_u32_e32 v6, 1, v2
v_add_nc_u32_e32 v2, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s6, v6
v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10interleavePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10interleavePfS_i, .Lfunc_end0-_Z10interleavePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10interleavePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10interleavePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void interleave(float* input, float* output, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads) {
output[2 * i] = input[i];
output[2 * i + 1] = input[size + 2 + i];
}
} | .text
.file "interleave.hip"
.globl _Z25__device_stub__interleavePfS_i # -- Begin function _Z25__device_stub__interleavePfS_i
.p2align 4, 0x90
.type _Z25__device_stub__interleavePfS_i,@function
_Z25__device_stub__interleavePfS_i: # @_Z25__device_stub__interleavePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10interleavePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__interleavePfS_i, .Lfunc_end0-_Z25__device_stub__interleavePfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10interleavePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10interleavePfS_i,@object # @_Z10interleavePfS_i
.section .rodata,"a",@progbits
.globl _Z10interleavePfS_i
.p2align 3, 0x0
_Z10interleavePfS_i:
.quad _Z25__device_stub__interleavePfS_i
.size _Z10interleavePfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10interleavePfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__interleavePfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10interleavePfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10interleavePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x430 ; /* 0x000003a000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.IADD R2, R0.reuse, 0x1, R3 ; /* 0x0000000100027824 */
/* 0x040fe200078e0203 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0220*/ LOP3.LUT P1, R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */
/* 0x000fc8000782c0ff */
/*0230*/ IADD3 R2, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x000fd20007ffe0ff */
/*0240*/ @!P1 BRA 0x420 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0250*/ SHF.L.U32 R4, R3.reuse, 0x1, RZ ; /* 0x0000000103047819 */
/* 0x040fe200000006ff */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0270*/ SHF.R.S32.HI R7, RZ, 0x1f, R3 ; /* 0x0000001fff077819 */
/* 0x000fe40000011403 */
/*0280*/ IADD3 R9, P1, R3, R2, RZ ; /* 0x0000000203097210 */
/* 0x000fe20007f3e0ff */
/*0290*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e020b */
/*02a0*/ MOV R14, R6 ; /* 0x00000006000e7202 */
/* 0x000fe40000000f00 */
/*02b0*/ LEA.HI.X.SX32 R10, R2, R7, 0x1, P1 ; /* 0x00000007020a7211 */
/* 0x000fe400008f0eff */
/*02c0*/ IADD3 R16, P1, R4, 0x4, RZ ; /* 0x0000000404107810 */
/* 0x000fc40007f3e0ff */
/*02d0*/ LEA R8, P2, R9.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580009087a11 */
/* 0x040fe400078410ff */
/*02e0*/ SHF.L.U32 R15, R0, 0x1, RZ ; /* 0x00000001000f7819 */
/* 0x000fe200000006ff */
/*02f0*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0605 */
/*0300*/ LEA.HI.X R9, R9, c[0x0][0x164], R10, 0x2, P2 ; /* 0x0000590009097a11 */
/* 0x000fe200010f140a */
/*0310*/ IMAD.WIDE R4, R3, R11, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e020b */
/*0320*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x001ea2000c1e1900 */
/*0330*/ IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0010 */
/*0340*/ MOV R11, R7 ; /* 0x00000007000b7202 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0360*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fc60000000f00 */
/*0370*/ STG.E [R10.64+-0x4], R17 ; /* 0xfffffc110a007986 */
/* 0x0041e8000c101904 */
/*0380*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE R6, R15, 0x4, R10 ; /* 0x000000040f067825 */
/* 0x000fe200078e020a */
/*03b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*03d0*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0006 */
/*03f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x000fe200078e0204 */
/*0400*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0041ea000c101904 */
/*0410*/ @P1 BRA 0x320 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x000fe400078e00ff */
/*0450*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x004fd400000001ff */
/*0460*/ IMAD.WIDE R6, R3, R9, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0209 */
/*0470*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.SHL.U32 R8, R3, 0x2, RZ ; /* 0x0000000203087824 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.WIDE R10, R2, 0x4, R6 ; /* 0x00000004020a7825 */
/* 0x001fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*04b0*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0041e8000c101904 */
/*04c0*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*04e0*/ STG.E [R8.64+0x4], R21 ; /* 0x0000041508007986 */
/* 0x0043e8000c101904 */
/*04f0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IMAD.WIDE R14, R4, 0x4, R8 ; /* 0x00000004040e7825 */
/* 0x000fc800078e0208 */
/*0510*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x040fe200078e020a */
/*0520*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0045e8000c101904 */
/*0530*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000ee2000c1e1900 */
/*0540*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc600078e020c */
/*0550*/ STG.E [R14.64+0x4], R25 ; /* 0x000004190e007986 */
/* 0x0085e8000c101904 */
/*0560*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD.WIDE R10, R4, 0x4, R14 ; /* 0x00000004040a7825 */
/* 0x000fc800078e020e */
/*0580*/ IMAD.WIDE R18, R0.reuse, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x040fe200078e0210 */
/*0590*/ STG.E [R10.64], R5 ; /* 0x000000050a007986 */
/* 0x0085e8000c101904 */
/*05a0*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x002ee2000c1e1900 */
/*05b0*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc600078e0206 */
/*05c0*/ STG.E [R10.64+0x4], R21 ; /* 0x000004150a007986 */
/* 0x0085e8000c101904 */
/*05d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fc800078e020a */
/*05f0*/ IMAD.WIDE R16, R0.reuse, 0x4, R18 ; /* 0x0000000400107825 */
/* 0x040fe200078e0212 */
/*0600*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0085ea000c101904 */
/*0610*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee2000c1e1900 */
/*0620*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0630*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0640*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0650*/ STG.E [R12.64+0x4], R17 ; /* 0x000004110c007986 */
/* 0x0085d8000c101904 */
/*0660*/ @!P0 BRA 0x450 ; /* 0xfffffde000008947 */
/* 0x000fea000383ffff */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ BRA 0x680; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10interleavePfS_i
.globl _Z10interleavePfS_i
.p2align 8
.type _Z10interleavePfS_i,@function
_Z10interleavePfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s1, s10, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_lshlrev_b32_e32 v2, 1, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b32 s11, s2, 1
s_lshl_b64 s[8:9], s[2:3], 2
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
global_load_b32 v0, v[4:5], off
v_add_nc_u32_e32 v6, s1, v1
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v8, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v0, off
global_load_b32 v0, v[6:7], off
v_add_nc_u32_e32 v6, 1, v2
v_add_nc_u32_e32 v2, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s6, v6
v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10interleavePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10interleavePfS_i, .Lfunc_end0-_Z10interleavePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10interleavePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10interleavePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014527d_00000000-6_interleave.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10interleavePfS_iPfS_i
.type _Z33__device_stub__Z10interleavePfS_iPfS_i, @function
_Z33__device_stub__Z10interleavePfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10interleavePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10interleavePfS_iPfS_i, .-_Z33__device_stub__Z10interleavePfS_iPfS_i
.globl _Z10interleavePfS_i
.type _Z10interleavePfS_i, @function
_Z10interleavePfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10interleavePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10interleavePfS_i, .-_Z10interleavePfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10interleavePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10interleavePfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "interleave.hip"
.globl _Z25__device_stub__interleavePfS_i # -- Begin function _Z25__device_stub__interleavePfS_i
.p2align 4, 0x90
.type _Z25__device_stub__interleavePfS_i,@function
_Z25__device_stub__interleavePfS_i: # @_Z25__device_stub__interleavePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10interleavePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__interleavePfS_i, .Lfunc_end0-_Z25__device_stub__interleavePfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10interleavePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10interleavePfS_i,@object # @_Z10interleavePfS_i
.section .rodata,"a",@progbits
.globl _Z10interleavePfS_i
.p2align 3, 0x0
_Z10interleavePfS_i:
.quad _Z25__device_stub__interleavePfS_i
.size _Z10interleavePfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10interleavePfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__interleavePfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10interleavePfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = ( blockIdx.x * blockDim.x ) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if ( global_index_1d < num_coordinates )
{
unsigned int image_index_1d = d_coordinates[ imgSize - global_index_1d - 1 ];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for ( int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++ )
{
for ( int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++ )
{
int2 image_offset_index_2d = make_int2( x, y );
int2 image_offset_index_2d_clamped = make_int2( min( nx - 1, max( 0, image_offset_index_2d.x ) ), min( ny - 1, max( 0, image_offset_index_2d.y ) ) );
int image_offset_index_1d_clamped = ( nx * image_offset_index_2d_clamped.y ) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[ image_offset_index_1d_clamped ];
unsigned char b_value = d_b[ image_offset_index_1d_clamped ];
unsigned int gb_average = ( g_value + b_value ) / 2;
d_r_output[ image_offset_index_1d_clamped ] = (unsigned char)gb_average;
}
}
}
} | code for sm_80
Function : _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff037212 */
/* 0x000fe200078e33ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R3, R4, c[0x0][0x18c], R3 ; /* 0x0000630004037a24 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ I2F.U32.RP R0, c[0x0][0x190] ; /* 0x0000640000007b06 */
/* 0x000e300000209000 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R6, R0, 0xffffffe, RZ ; /* 0x0ffffffe00067810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a07 */
/*0130*/ IMAD R5, R5, c[0x0][0x190], RZ ; /* 0x0000640005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fe200078e0006 */
/*0150*/ LOP3.LUT R6, RZ, c[0x0][0x190], RZ, 0x33, !PT ; /* 0x00006400ff067a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x004fc800078e00ff */
/*0170*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*0180*/ IMAD R2, R3, c[0x0][0x190], R2 ; /* 0x0000640003027a24 */
/* 0x000fca00078e0202 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R2, R2, -c[0x0][0x190], RZ ; /* 0x8000640002020a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe40003f26070 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x190], PT ; /* 0x00006400ff007a0c */
/* 0x000fd60003f05070 */
/*01e0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ SEL R7, R6, R7, !P0 ; /* 0x0000000706077207 */
/* 0x000fc80004000000 */
/*0200*/ LOP3.LUT R7, R7, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff07077812 */
/* 0x000fc800078ec0ff */
/*0210*/ IADD3 R5, R7.reuse, -c[0x0][0x194], RZ ; /* 0x8000650007057a10 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R0, R7, c[0x0][0x194], RZ ; /* 0x0000650007007a10 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GT.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44270 */
/*0240*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R3, R2, -c[0x0][0x190], RZ ; /* 0x8000640002037a10 */
/* 0x000fe20007ffe0ff */
/*0260*/ ULDC UR4, c[0x0][0x18c] ; /* 0x0000630000047ab9 */
/* 0x000fe20000000800 */
/*0270*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0280*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0290*/ @P0 SEL R6, R3, R2, P1 ; /* 0x0000000203060207 */
/* 0x000fc80000800000 */
/*02a0*/ LOP3.LUT R7, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06077812 */
/* 0x000fc800078ec0ff */
/*02b0*/ IADD3 R2, R7.reuse, -c[0x0][0x198], RZ ; /* 0x8000660007027a10 */
/* 0x040fe40007ffe0ff */
/*02c0*/ IADD3 R3, R7, c[0x0][0x198], RZ ; /* 0x0000660007037a10 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IMNMX R9, RZ, R2, !PT ; /* 0x00000002ff097217 */
/* 0x000fe40007800200 */
/*02e0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fe40007800200 */
/*02f0*/ IMNMX R9, R9, R4, PT ; /* 0x0000000409097217 */
/* 0x000fe40003800200 */
/*0300*/ IADD3 R8, R8, c[0x0][0x198], RZ ; /* 0x0000660008087a10 */
/* 0x000fc80007ffe0ff */
/*0310*/ IADD3 R24, -R6, 0x1, R8 ; /* 0x0000000106187810 */
/* 0x000fe20007ffe108 */
/*0320*/ IMAD.IADD R7, R8, 0x1, -R7 ; /* 0x0000000108077824 */
/* 0x000fe200078e0a07 */
/*0330*/ IADD3 R6, R2.reuse, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x040fe40007ffe0ff */
/*0340*/ IADD3 R8, R2.reuse, 0x3, RZ ; /* 0x0000000302087810 */
/* 0x040fe40007ffe0ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f06070 */
/*0360*/ IADD3 R7, R2, 0x2, RZ ; /* 0x0000000202077810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IMNMX R11, RZ, R6, !PT ; /* 0x00000006ff0b7217 */
/* 0x000fc40007800200 */
/*0380*/ IMNMX R13, RZ, R7, !PT ; /* 0x00000007ff0d7217 */
/* 0x000fe40007800200 */
/*0390*/ IMNMX R10, R4.reuse, R11, PT ; /* 0x0000000b040a7217 */
/* 0x040fe40003800200 */
/*03a0*/ IMNMX R11, R4, R13, PT ; /* 0x0000000d040b7217 */
/* 0x000fe40003800200 */
/*03b0*/ LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ; /* 0x0000000318187812 */
/* 0x000fe400078ec0ff */
/*03c0*/ ISETP.GT.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe20003f24270 */
/*03d0*/ BSSY B0, 0xb90 ; /* 0x000007b000007945 */
/* 0x000fd80003800000 */
/*03e0*/ @P1 BRA 0xb80 ; /* 0x0000079000001947 */
/* 0x001fea0003800000 */
/*03f0*/ ISETP.NE.AND P1, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f25270 */
/*0400*/ BSSY B1, 0x740 ; /* 0x0000033000017945 */
/* 0x000fe20003800000 */
/*0410*/ IMNMX R26, RZ, R5, !PT ; /* 0x00000005ff1a7217 */
/* 0x000fe20007800200 */
/*0420*/ IMAD.MOV.U32 R18, RZ, RZ, R2 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0002 */
/*0430*/ IMNMX R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fce000b800200 */
/*0440*/ @!P1 BRA 0x730 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R16, R26, c[0x0][0x190], R9 ; /* 0x000064001a107a24 */
/* 0x000fca00078e0209 */
/*0460*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0470*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0480*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0490*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*04a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*04b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*04c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*04d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*04e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*04f0*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fe20003f25270 */
/*0500*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0510*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0520*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0530*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0540*/ @!P1 BRA 0x730 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD R16, R26, c[0x0][0x190], R10 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020a */
/*0560*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0570*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0580*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0590*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*05a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*05b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*05c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*05d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*05e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*05f0*/ ISETP.NE.AND P1, PT, R24, 0x2, PT ; /* 0x000000021800780c */
/* 0x000fe20003f25270 */
/*0600*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0610*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0620*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0630*/ IMAD.MOV.U32 R18, RZ, RZ, R7 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0007 */
/*0640*/ @!P1 BRA 0x730 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD R16, R26, c[0x0][0x190], R11 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020b */
/*0660*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0670*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0680*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0690*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*06a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*06b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*06c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*06d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*06e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe20000ffe4ff */
/*06f0*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0700*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0710*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0720*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0008 */
/*0730*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0740*/ @!P0 BRA 0xb80 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R28, R18, 0x3, RZ ; /* 0x00000003121c7810 */
/* 0x000fc80007ffe0ff */
/*0760*/ IADD3 R12, R28, -0x3, RZ ; /* 0xfffffffd1c0c7810 */
/* 0x001fc80007ffe0ff */
/*0770*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0780*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0790*/ IMAD R22, R26, c[0x0][0x190], R13 ; /* 0x000064001a167a24 */
/* 0x000fca00078e020d */
/*07a0*/ SHF.R.S32.HI R19, RZ, 0x1f, R22 ; /* 0x0000001fff137819 */
/* 0x001fe40000011416 */
/*07b0*/ IADD3 R12, P2, R22.reuse, c[0x0][0x170], RZ ; /* 0x00005c00160c7a10 */
/* 0x040fe40007f5e0ff */
/*07c0*/ IADD3 R14, P1, R22, c[0x0][0x178], RZ ; /* 0x00005e00160e7a10 */
/* 0x000fe40007f3e0ff */
/*07d0*/ IADD3.X R13, R19.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00130d7a10 */
/* 0x040fe400017fe4ff */
/*07e0*/ IADD3.X R15, R19, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00130f7a10 */
/* 0x000fc80000ffe4ff */
/*07f0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*0800*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*0810*/ IADD3 R16, R28, -0x2, RZ ; /* 0xfffffffe1c107810 */
/* 0x000fc80007ffe0ff */
/*0820*/ IMNMX R17, RZ, R16, !PT ; /* 0x00000010ff117217 */
/* 0x000fc80007800200 */
/*0830*/ IMNMX R17, R4, R17, PT ; /* 0x0000001104117217 */
/* 0x000fca0003800200 */
/*0840*/ IMAD R16, R26, c[0x0][0x190], R17 ; /* 0x000064001a107a24 */
/* 0x000fe200078e0211 */
/*0850*/ IADD3 R22, P1, R22, c[0x0][0x180], RZ ; /* 0x0000600016167a10 */
/* 0x000fc80007f3e0ff */
/*0860*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0870*/ IADD3 R18, P3, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c0010127a10 */
/* 0x040fe40007f7e0ff */
/*0880*/ IADD3 R20, P2, R16, c[0x0][0x178], RZ ; /* 0x00005e0010147a10 */
/* 0x000fe40007f5e0ff */
/*0890*/ IADD3.X R23, R19, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610013177a10 */
/* 0x000fe40000ffe4ff */
/*08a0*/ IADD3.X R19, R17.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0011137a10 */
/* 0x040fe40001ffe4ff */
/*08b0*/ IADD3.X R21, R17, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0011157a10 */
/* 0x000fe200017fe4ff */
/*08c0*/ IMAD.IADD R25, R14, 0x1, R13 ; /* 0x000000010e197824 */
/* 0x004fca00078e020d */
/*08d0*/ SHF.R.U32.HI R29, RZ, 0x1, R25 ; /* 0x00000001ff1d7819 */
/* 0x000fca0000011619 */
/*08e0*/ STG.E.U8 [R22.64], R29 ; /* 0x0000001d16007986 */
/* 0x0001e8000c101106 */
/*08f0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000e28000c1e1100 */
/*0900*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000e22000c1e1100 */
/*0910*/ IADD3 R12, R28, -0x1, RZ ; /* 0xffffffff1c0c7810 */
/* 0x000fc80007ffe0ff */
/*0920*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0930*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0940*/ IMAD R27, R26, c[0x0][0x190], R13 ; /* 0x000064001a1b7a24 */
/* 0x000fe200078e020d */
/*0950*/ IADD3 R12, P1, R16, c[0x0][0x180], RZ ; /* 0x00006000100c7a10 */
/* 0x000fc80007f3e0ff */
/*0960*/ SHF.R.S32.HI R25, RZ, 0x1f, R27 ; /* 0x0000001fff197819 */
/* 0x000fe4000001141b */
/*0970*/ IADD3 R16, P3, R27.reuse, c[0x0][0x170], RZ ; /* 0x00005c001b107a10 */
/* 0x040fe40007f7e0ff */
/*0980*/ IADD3 R14, P2, R27, c[0x0][0x178], RZ ; /* 0x00005e001b0e7a10 */
/* 0x000fe40007f5e0ff */
/*0990*/ IADD3.X R13, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100110d7a10 */
/* 0x000fe40000ffe4ff */
/*09a0*/ IADD3.X R17, R25.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0019117a10 */
/* 0x040fe40001ffe4ff */
/*09b0*/ IADD3.X R15, R25, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00190f7a10 */
/* 0x000fe200017fe4ff */
/*09c0*/ IMAD.IADD R22, R20, 0x1, R19 ; /* 0x0000000114167824 */
/* 0x001fca00078e0213 */
/*09d0*/ SHF.R.U32.HI R19, RZ, 0x1, R22 ; /* 0x00000001ff137819 */
/* 0x000fca0000011616 */
/*09e0*/ STG.E.U8 [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101106 */
/*09f0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x0002a8000c1e1100 */
/*0a00*/ LDG.E.U8 R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1100 */
/*0a10*/ IMNMX R21, RZ, R28, !PT ; /* 0x0000001cff157217 */
/* 0x000fc80007800200 */
/*0a20*/ IMNMX R21, R4, R21, PT ; /* 0x0000001504157217 */
/* 0x000fe40003800200 */
/*0a30*/ IADD3 R22, P1, R27, c[0x0][0x180], RZ ; /* 0x000060001b167a10 */
/* 0x000fc60007f3e0ff */
/*0a40*/ IMAD R15, R26, c[0x0][0x190], R21 ; /* 0x000064001a0f7a24 */
/* 0x002fe200078e0215 */
/*0a50*/ IADD3.X R23, R25, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610019177a10 */
/* 0x000fc80000ffe4ff */
/*0a60*/ SHF.R.S32.HI R29, RZ, 0x1f, R15 ; /* 0x0000001fff1d7819 */
/* 0x000fe4000001140f */
/*0a70*/ IADD3 R20, P3, R15.reuse, c[0x0][0x170], RZ ; /* 0x00005c000f147a10 */
/* 0x040fe40007f7e0ff */
/*0a80*/ IADD3 R18, P2, R15, c[0x0][0x178], RZ ; /* 0x00005e000f127a10 */
/* 0x000fe40007f5e0ff */
/*0a90*/ IADD3.X R21, R29.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d001d157a10 */
/* 0x040fe40001ffe4ff */
/*0aa0*/ IADD3.X R19, R29, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f001d137a10 */
/* 0x001fe200017fe4ff */
/*0ab0*/ IMAD.IADD R27, R14, 0x1, R17 ; /* 0x000000010e1b7824 */
/* 0x004fca00078e0211 */
/*0ac0*/ SHF.R.U32.HI R27, RZ, 0x1, R27 ; /* 0x00000001ff1b7819 */
/* 0x000fca000001161b */
/*0ad0*/ STG.E.U8 [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0001e8000c101106 */
/*0ae0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea8000c1e1100 */
/*0af0*/ LDG.E.U8 R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea2000c1e1100 */
/*0b00*/ IADD3 R12, P1, R15, c[0x0][0x180], RZ ; /* 0x000060000f0c7a10 */
/* 0x000fc80007f3e0ff */
/*0b10*/ IADD3.X R13, R29, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061001d0d7a10 */
/* 0x000fe40000ffe4ff */
/*0b20*/ ISETP.GE.AND P1, PT, R28.reuse, R3, PT ; /* 0x000000031c00720c */
/* 0x040fe40003f26270 */
/*0b30*/ IADD3 R28, R28, 0x4, RZ ; /* 0x000000041c1c7810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD.IADD R14, R18, 0x1, R21 ; /* 0x00000001120e7824 */
/* 0x004fca00078e0215 */
/*0b50*/ SHF.R.U32.HI R15, RZ, 0x1, R14 ; /* 0x00000001ff0f7819 */
/* 0x000fca000001160e */
/*0b60*/ STG.E.U8 [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e2000c101106 */
/*0b70*/ @!P1 BRA 0x760 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.GE.AND P1, PT, R5.reuse, R0, PT ; /* 0x000000000500720c */
/* 0x040fe40003f26270 */
/*0ba0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fd60007ffe0ff */
/*0bb0*/ @!P1 BRA 0x3c0 ; /* 0xfffff80000009947 */
/* 0x000fea000383ffff */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = ( blockIdx.x * blockDim.x ) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if ( global_index_1d < num_coordinates )
{
unsigned int image_index_1d = d_coordinates[ imgSize - global_index_1d - 1 ];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for ( int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++ )
{
for ( int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++ )
{
int2 image_offset_index_2d = make_int2( x, y );
int2 image_offset_index_2d_clamped = make_int2( min( nx - 1, max( 0, image_offset_index_2d.x ) ), min( ny - 1, max( 0, image_offset_index_2d.y ) ) );
int image_offset_index_1d_clamped = ( nx * image_offset_index_2d_clamped.y ) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[ image_offset_index_1d_clamped ];
unsigned char b_value = d_b[ image_offset_index_1d_clamped ];
unsigned int gb_average = ( g_value + b_value ) / 2;
d_r_output[ image_offset_index_1d_clamped ] = (unsigned char)gb_average;
}
}
}
} | .file "tmpxft_0008b061_00000000-6_remove_redness_from_coordinates.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.type _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, @function
_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, .-_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, @function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = ( blockIdx.x * blockDim.x ) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if ( global_index_1d < num_coordinates )
{
unsigned int image_index_1d = d_coordinates[ imgSize - global_index_1d - 1 ];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for ( int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++ )
{
for ( int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++ )
{
int2 image_offset_index_2d = make_int2( x, y );
int2 image_offset_index_2d_clamped = make_int2( min( nx - 1, max( 0, image_offset_index_2d.x ) ), min( ny - 1, max( 0, image_offset_index_2d.y ) ) );
int image_offset_index_1d_clamped = ( nx * image_offset_index_2d_clamped.y ) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[ image_offset_index_1d_clamped ];
unsigned char b_value = d_b[ image_offset_index_1d_clamped ];
unsigned int gb_average = ( g_value + b_value ) / 2;
d_r_output[ image_offset_index_1d_clamped ] = (unsigned char)gb_average;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = ( blockIdx.x * blockDim.x ) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if ( global_index_1d < num_coordinates )
{
unsigned int image_index_1d = d_coordinates[ imgSize - global_index_1d - 1 ];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for ( int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++ )
{
for ( int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++ )
{
int2 image_offset_index_2d = make_int2( x, y );
int2 image_offset_index_2d_clamped = make_int2( min( nx - 1, max( 0, image_offset_index_2d.x ) ), min( ny - 1, max( 0, image_offset_index_2d.y ) ) );
int image_offset_index_1d_clamped = ( nx * image_offset_index_2d_clamped.y ) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[ image_offset_index_1d_clamped ];
unsigned char b_value = d_b[ image_offset_index_1d_clamped ];
unsigned int gb_average = ( g_value + b_value ) / 2;
d_r_output[ image_offset_index_1d_clamped ] = (unsigned char)gb_average;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = ( blockIdx.x * blockDim.x ) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if ( global_index_1d < num_coordinates )
{
unsigned int image_index_1d = d_coordinates[ imgSize - global_index_1d - 1 ];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for ( int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++ )
{
for ( int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++ )
{
int2 image_offset_index_2d = make_int2( x, y );
int2 image_offset_index_2d_clamped = make_int2( min( nx - 1, max( 0, image_offset_index_2d.x ) ), min( ny - 1, max( 0, image_offset_index_2d.y ) ) );
int image_offset_index_1d_clamped = ( nx * image_offset_index_2d_clamped.y ) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[ image_offset_index_1d_clamped ];
unsigned char b_value = d_b[ image_offset_index_1d_clamped ];
unsigned int gb_average = ( g_value + b_value ) / 2;
d_r_output[ image_offset_index_1d_clamped ] = (unsigned char)gb_average;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 8
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x34
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v0, v1, -1, s7
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_sub_i32 s4, 0, s3
global_load_b32 v0, v[0:1], off
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s3
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_perm_b32 v2, v1, v0, 0x5040100
v_lshrrev_b32_e32 v0, 16, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s6, v0
v_add_nc_u32_e32 v0, s6, v0
v_cmp_le_i32_e32 vcc_lo, v1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s12, s[0:1], 0x38
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
v_and_b32_e32 v3, 0xffff, v2
s_add_i32 s11, s3, -1
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v2, s12, v3
v_add_nc_u32_e32 v3, s12, v3
s_lshl_b32 s0, s12, 1
s_or_b32 s12, s0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, v2, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, 1, v1
v_cmp_eq_u32_e64 s0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v3
s_or_b32 s10, s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_7
.LBB0_4:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_3
v_maxmin_i32 v3, v1, 0, s2
v_mov_b32_e32 v4, v2
s_mov_b32 s14, s12
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s3
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v5, v4, 0, s11
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v5, v3
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, s1, s6, v9
v_add_co_u32 v5, s0, s4, v9
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s1, s7, v10, s1
v_add_co_ci_u32_e64 v6, s0, s5, v10, s0
global_load_u8 v7, v[7:8], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v7, v5, v7
v_add_co_u32 v5, s0, s8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, s9, v10, s0
v_lshrrev_b16 v7, 1, v7
global_store_b8 v[5:6], v7, off
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = ( blockIdx.x * blockDim.x ) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if ( global_index_1d < num_coordinates )
{
unsigned int image_index_1d = d_coordinates[ imgSize - global_index_1d - 1 ];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for ( int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++ )
{
for ( int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++ )
{
int2 image_offset_index_2d = make_int2( x, y );
int2 image_offset_index_2d_clamped = make_int2( min( nx - 1, max( 0, image_offset_index_2d.x ) ), min( ny - 1, max( 0, image_offset_index_2d.y ) ) );
int image_offset_index_1d_clamped = ( nx * image_offset_index_2d_clamped.y ) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[ image_offset_index_1d_clamped ];
unsigned char b_value = d_b[ image_offset_index_1d_clamped ];
unsigned int gb_average = ( g_value + b_value ) / 2;
d_r_output[ image_offset_index_1d_clamped ] = (unsigned char)gb_average;
}
}
}
} | .text
.file "remove_redness_from_coordinates.hip"
.globl _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii # -- Begin function _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 4, 0x90
.type _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii: # @_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@object # @_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata,"a",@progbits
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 3, 0x0
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.quad _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff037212 */
/* 0x000fe200078e33ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R3, R4, c[0x0][0x18c], R3 ; /* 0x0000630004037a24 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ I2F.U32.RP R0, c[0x0][0x190] ; /* 0x0000640000007b06 */
/* 0x000e300000209000 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R6, R0, 0xffffffe, RZ ; /* 0x0ffffffe00067810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a07 */
/*0130*/ IMAD R5, R5, c[0x0][0x190], RZ ; /* 0x0000640005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fe200078e0006 */
/*0150*/ LOP3.LUT R6, RZ, c[0x0][0x190], RZ, 0x33, !PT ; /* 0x00006400ff067a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x004fc800078e00ff */
/*0170*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*0180*/ IMAD R2, R3, c[0x0][0x190], R2 ; /* 0x0000640003027a24 */
/* 0x000fca00078e0202 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R2, R2, -c[0x0][0x190], RZ ; /* 0x8000640002020a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe40003f26070 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x190], PT ; /* 0x00006400ff007a0c */
/* 0x000fd60003f05070 */
/*01e0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ SEL R7, R6, R7, !P0 ; /* 0x0000000706077207 */
/* 0x000fc80004000000 */
/*0200*/ LOP3.LUT R7, R7, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff07077812 */
/* 0x000fc800078ec0ff */
/*0210*/ IADD3 R5, R7.reuse, -c[0x0][0x194], RZ ; /* 0x8000650007057a10 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R0, R7, c[0x0][0x194], RZ ; /* 0x0000650007007a10 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GT.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44270 */
/*0240*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R3, R2, -c[0x0][0x190], RZ ; /* 0x8000640002037a10 */
/* 0x000fe20007ffe0ff */
/*0260*/ ULDC UR4, c[0x0][0x18c] ; /* 0x0000630000047ab9 */
/* 0x000fe20000000800 */
/*0270*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0280*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0290*/ @P0 SEL R6, R3, R2, P1 ; /* 0x0000000203060207 */
/* 0x000fc80000800000 */
/*02a0*/ LOP3.LUT R7, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06077812 */
/* 0x000fc800078ec0ff */
/*02b0*/ IADD3 R2, R7.reuse, -c[0x0][0x198], RZ ; /* 0x8000660007027a10 */
/* 0x040fe40007ffe0ff */
/*02c0*/ IADD3 R3, R7, c[0x0][0x198], RZ ; /* 0x0000660007037a10 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IMNMX R9, RZ, R2, !PT ; /* 0x00000002ff097217 */
/* 0x000fe40007800200 */
/*02e0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fe40007800200 */
/*02f0*/ IMNMX R9, R9, R4, PT ; /* 0x0000000409097217 */
/* 0x000fe40003800200 */
/*0300*/ IADD3 R8, R8, c[0x0][0x198], RZ ; /* 0x0000660008087a10 */
/* 0x000fc80007ffe0ff */
/*0310*/ IADD3 R24, -R6, 0x1, R8 ; /* 0x0000000106187810 */
/* 0x000fe20007ffe108 */
/*0320*/ IMAD.IADD R7, R8, 0x1, -R7 ; /* 0x0000000108077824 */
/* 0x000fe200078e0a07 */
/*0330*/ IADD3 R6, R2.reuse, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x040fe40007ffe0ff */
/*0340*/ IADD3 R8, R2.reuse, 0x3, RZ ; /* 0x0000000302087810 */
/* 0x040fe40007ffe0ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f06070 */
/*0360*/ IADD3 R7, R2, 0x2, RZ ; /* 0x0000000202077810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IMNMX R11, RZ, R6, !PT ; /* 0x00000006ff0b7217 */
/* 0x000fc40007800200 */
/*0380*/ IMNMX R13, RZ, R7, !PT ; /* 0x00000007ff0d7217 */
/* 0x000fe40007800200 */
/*0390*/ IMNMX R10, R4.reuse, R11, PT ; /* 0x0000000b040a7217 */
/* 0x040fe40003800200 */
/*03a0*/ IMNMX R11, R4, R13, PT ; /* 0x0000000d040b7217 */
/* 0x000fe40003800200 */
/*03b0*/ LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ; /* 0x0000000318187812 */
/* 0x000fe400078ec0ff */
/*03c0*/ ISETP.GT.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe20003f24270 */
/*03d0*/ BSSY B0, 0xb90 ; /* 0x000007b000007945 */
/* 0x000fd80003800000 */
/*03e0*/ @P1 BRA 0xb80 ; /* 0x0000079000001947 */
/* 0x001fea0003800000 */
/*03f0*/ ISETP.NE.AND P1, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f25270 */
/*0400*/ BSSY B1, 0x740 ; /* 0x0000033000017945 */
/* 0x000fe20003800000 */
/*0410*/ IMNMX R26, RZ, R5, !PT ; /* 0x00000005ff1a7217 */
/* 0x000fe20007800200 */
/*0420*/ IMAD.MOV.U32 R18, RZ, RZ, R2 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0002 */
/*0430*/ IMNMX R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fce000b800200 */
/*0440*/ @!P1 BRA 0x730 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R16, R26, c[0x0][0x190], R9 ; /* 0x000064001a107a24 */
/* 0x000fca00078e0209 */
/*0460*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0470*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0480*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0490*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*04a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*04b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*04c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*04d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*04e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*04f0*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fe20003f25270 */
/*0500*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0510*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0520*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0530*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0540*/ @!P1 BRA 0x730 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD R16, R26, c[0x0][0x190], R10 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020a */
/*0560*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0570*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0580*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0590*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*05a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*05b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*05c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*05d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*05e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*05f0*/ ISETP.NE.AND P1, PT, R24, 0x2, PT ; /* 0x000000021800780c */
/* 0x000fe20003f25270 */
/*0600*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0610*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0620*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0630*/ IMAD.MOV.U32 R18, RZ, RZ, R7 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0007 */
/*0640*/ @!P1 BRA 0x730 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD R16, R26, c[0x0][0x190], R11 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020b */
/*0660*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0670*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0680*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0690*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*06a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*06b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*06c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*06d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*06e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe20000ffe4ff */
/*06f0*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0700*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0710*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0720*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0008 */
/*0730*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0740*/ @!P0 BRA 0xb80 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R28, R18, 0x3, RZ ; /* 0x00000003121c7810 */
/* 0x000fc80007ffe0ff */
/*0760*/ IADD3 R12, R28, -0x3, RZ ; /* 0xfffffffd1c0c7810 */
/* 0x001fc80007ffe0ff */
/*0770*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0780*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0790*/ IMAD R22, R26, c[0x0][0x190], R13 ; /* 0x000064001a167a24 */
/* 0x000fca00078e020d */
/*07a0*/ SHF.R.S32.HI R19, RZ, 0x1f, R22 ; /* 0x0000001fff137819 */
/* 0x001fe40000011416 */
/*07b0*/ IADD3 R12, P2, R22.reuse, c[0x0][0x170], RZ ; /* 0x00005c00160c7a10 */
/* 0x040fe40007f5e0ff */
/*07c0*/ IADD3 R14, P1, R22, c[0x0][0x178], RZ ; /* 0x00005e00160e7a10 */
/* 0x000fe40007f3e0ff */
/*07d0*/ IADD3.X R13, R19.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00130d7a10 */
/* 0x040fe400017fe4ff */
/*07e0*/ IADD3.X R15, R19, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00130f7a10 */
/* 0x000fc80000ffe4ff */
/*07f0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*0800*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*0810*/ IADD3 R16, R28, -0x2, RZ ; /* 0xfffffffe1c107810 */
/* 0x000fc80007ffe0ff */
/*0820*/ IMNMX R17, RZ, R16, !PT ; /* 0x00000010ff117217 */
/* 0x000fc80007800200 */
/*0830*/ IMNMX R17, R4, R17, PT ; /* 0x0000001104117217 */
/* 0x000fca0003800200 */
/*0840*/ IMAD R16, R26, c[0x0][0x190], R17 ; /* 0x000064001a107a24 */
/* 0x000fe200078e0211 */
/*0850*/ IADD3 R22, P1, R22, c[0x0][0x180], RZ ; /* 0x0000600016167a10 */
/* 0x000fc80007f3e0ff */
/*0860*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0870*/ IADD3 R18, P3, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c0010127a10 */
/* 0x040fe40007f7e0ff */
/*0880*/ IADD3 R20, P2, R16, c[0x0][0x178], RZ ; /* 0x00005e0010147a10 */
/* 0x000fe40007f5e0ff */
/*0890*/ IADD3.X R23, R19, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610013177a10 */
/* 0x000fe40000ffe4ff */
/*08a0*/ IADD3.X R19, R17.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0011137a10 */
/* 0x040fe40001ffe4ff */
/*08b0*/ IADD3.X R21, R17, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0011157a10 */
/* 0x000fe200017fe4ff */
/*08c0*/ IMAD.IADD R25, R14, 0x1, R13 ; /* 0x000000010e197824 */
/* 0x004fca00078e020d */
/*08d0*/ SHF.R.U32.HI R29, RZ, 0x1, R25 ; /* 0x00000001ff1d7819 */
/* 0x000fca0000011619 */
/*08e0*/ STG.E.U8 [R22.64], R29 ; /* 0x0000001d16007986 */
/* 0x0001e8000c101106 */
/*08f0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000e28000c1e1100 */
/*0900*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000e22000c1e1100 */
/*0910*/ IADD3 R12, R28, -0x1, RZ ; /* 0xffffffff1c0c7810 */
/* 0x000fc80007ffe0ff */
/*0920*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0930*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0940*/ IMAD R27, R26, c[0x0][0x190], R13 ; /* 0x000064001a1b7a24 */
/* 0x000fe200078e020d */
/*0950*/ IADD3 R12, P1, R16, c[0x0][0x180], RZ ; /* 0x00006000100c7a10 */
/* 0x000fc80007f3e0ff */
/*0960*/ SHF.R.S32.HI R25, RZ, 0x1f, R27 ; /* 0x0000001fff197819 */
/* 0x000fe4000001141b */
/*0970*/ IADD3 R16, P3, R27.reuse, c[0x0][0x170], RZ ; /* 0x00005c001b107a10 */
/* 0x040fe40007f7e0ff */
/*0980*/ IADD3 R14, P2, R27, c[0x0][0x178], RZ ; /* 0x00005e001b0e7a10 */
/* 0x000fe40007f5e0ff */
/*0990*/ IADD3.X R13, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100110d7a10 */
/* 0x000fe40000ffe4ff */
/*09a0*/ IADD3.X R17, R25.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0019117a10 */
/* 0x040fe40001ffe4ff */
/*09b0*/ IADD3.X R15, R25, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00190f7a10 */
/* 0x000fe200017fe4ff */
/*09c0*/ IMAD.IADD R22, R20, 0x1, R19 ; /* 0x0000000114167824 */
/* 0x001fca00078e0213 */
/*09d0*/ SHF.R.U32.HI R19, RZ, 0x1, R22 ; /* 0x00000001ff137819 */
/* 0x000fca0000011616 */
/*09e0*/ STG.E.U8 [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101106 */
/*09f0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x0002a8000c1e1100 */
/*0a00*/ LDG.E.U8 R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1100 */
/*0a10*/ IMNMX R21, RZ, R28, !PT ; /* 0x0000001cff157217 */
/* 0x000fc80007800200 */
/*0a20*/ IMNMX R21, R4, R21, PT ; /* 0x0000001504157217 */
/* 0x000fe40003800200 */
/*0a30*/ IADD3 R22, P1, R27, c[0x0][0x180], RZ ; /* 0x000060001b167a10 */
/* 0x000fc60007f3e0ff */
/*0a40*/ IMAD R15, R26, c[0x0][0x190], R21 ; /* 0x000064001a0f7a24 */
/* 0x002fe200078e0215 */
/*0a50*/ IADD3.X R23, R25, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610019177a10 */
/* 0x000fc80000ffe4ff */
/*0a60*/ SHF.R.S32.HI R29, RZ, 0x1f, R15 ; /* 0x0000001fff1d7819 */
/* 0x000fe4000001140f */
/*0a70*/ IADD3 R20, P3, R15.reuse, c[0x0][0x170], RZ ; /* 0x00005c000f147a10 */
/* 0x040fe40007f7e0ff */
/*0a80*/ IADD3 R18, P2, R15, c[0x0][0x178], RZ ; /* 0x00005e000f127a10 */
/* 0x000fe40007f5e0ff */
/*0a90*/ IADD3.X R21, R29.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d001d157a10 */
/* 0x040fe40001ffe4ff */
/*0aa0*/ IADD3.X R19, R29, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f001d137a10 */
/* 0x001fe200017fe4ff */
/*0ab0*/ IMAD.IADD R27, R14, 0x1, R17 ; /* 0x000000010e1b7824 */
/* 0x004fca00078e0211 */
/*0ac0*/ SHF.R.U32.HI R27, RZ, 0x1, R27 ; /* 0x00000001ff1b7819 */
/* 0x000fca000001161b */
/*0ad0*/ STG.E.U8 [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0001e8000c101106 */
/*0ae0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea8000c1e1100 */
/*0af0*/ LDG.E.U8 R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea2000c1e1100 */
/*0b00*/ IADD3 R12, P1, R15, c[0x0][0x180], RZ ; /* 0x000060000f0c7a10 */
/* 0x000fc80007f3e0ff */
/*0b10*/ IADD3.X R13, R29, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061001d0d7a10 */
/* 0x000fe40000ffe4ff */
/*0b20*/ ISETP.GE.AND P1, PT, R28.reuse, R3, PT ; /* 0x000000031c00720c */
/* 0x040fe40003f26270 */
/*0b30*/ IADD3 R28, R28, 0x4, RZ ; /* 0x000000041c1c7810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD.IADD R14, R18, 0x1, R21 ; /* 0x00000001120e7824 */
/* 0x004fca00078e0215 */
/*0b50*/ SHF.R.U32.HI R15, RZ, 0x1, R14 ; /* 0x00000001ff0f7819 */
/* 0x000fca000001160e */
/*0b60*/ STG.E.U8 [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e2000c101106 */
/*0b70*/ @!P1 BRA 0x760 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.GE.AND P1, PT, R5.reuse, R0, PT ; /* 0x000000000500720c */
/* 0x040fe40003f26270 */
/*0ba0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fd60007ffe0ff */
/*0bb0*/ @!P1 BRA 0x3c0 ; /* 0xfffff80000009947 */
/* 0x000fea000383ffff */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 8
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x34
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v0, v1, -1, s7
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_sub_i32 s4, 0, s3
global_load_b32 v0, v[0:1], off
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s3
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_perm_b32 v2, v1, v0, 0x5040100
v_lshrrev_b32_e32 v0, 16, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s6, v0
v_add_nc_u32_e32 v0, s6, v0
v_cmp_le_i32_e32 vcc_lo, v1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s12, s[0:1], 0x38
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
v_and_b32_e32 v3, 0xffff, v2
s_add_i32 s11, s3, -1
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v2, s12, v3
v_add_nc_u32_e32 v3, s12, v3
s_lshl_b32 s0, s12, 1
s_or_b32 s12, s0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, v2, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, 1, v1
v_cmp_eq_u32_e64 s0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v3
s_or_b32 s10, s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_7
.LBB0_4:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_3
v_maxmin_i32 v3, v1, 0, s2
v_mov_b32_e32 v4, v2
s_mov_b32 s14, s12
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s3
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v5, v4, 0, s11
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v5, v3
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, s1, s6, v9
v_add_co_u32 v5, s0, s4, v9
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s1, s7, v10, s1
v_add_co_ci_u32_e64 v6, s0, s5, v10, s0
global_load_u8 v7, v[7:8], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v7, v5, v7
v_add_co_u32 v5, s0, s8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, s9, v10, s0
v_lshrrev_b16 v7, 1, v7
global_store_b8 v[5:6], v7, off
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008b061_00000000-6_remove_redness_from_coordinates.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.type _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, @function
_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, .-_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, @function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "remove_redness_from_coordinates.hip"
.globl _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii # -- Begin function _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 4, 0x90
.type _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii: # @_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@object # @_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata,"a",@progbits
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 3, 0x0
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.quad _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const size_t DSIZE = 16384; // matrix side dimension
const int block_size = 256; // CUDA maximum is 1024
// matrix row-sum kernel
// we will assign one block per row
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = blockIdx.x; // our block index becomes our row indicator
if (idx < ds){
__shared__ float sdata[block_size];
int tid = threadIdx.x;
sdata[tid] = 0.0f;
size_t tidx = tid;
while (tidx < ds) { // block stride loop to load data
sdata[tid] += A[idx*ds+tidx];
tidx += blockDim.x;
}
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
__syncthreads();
if (tid < s) // parallel sweep reduction
sdata[tid] += sdata[tid + s];
}
if (tid == 0) sums[idx] = sdata[0];
}
}
// matrix column-sum kernel
__global__ void column_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx+ds*i]; // write a for loop that will cause the thread to iterate down a column, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}}
bool validate(float *data, size_t sz){
for (size_t i = 0; i < sz; i++)
if (data[i] != (float)sz) {printf("results mismatch at %lu, was: %f, should be: %f\n", i, data[i], (float)sz); return false;}
return true;
}
int main(){
float *h_A, *h_sums, *d_A, *d_sums;
h_A = new float[DSIZE*DSIZE]; // allocate space for data in host memory
h_sums = new float[DSIZE]();
for (int i = 0; i < DSIZE*DSIZE; i++) // initialize matrix in host memory
h_A[i] = 1.0f;
cudaMalloc(&d_A, DSIZE*DSIZE*sizeof(float)); // allocate device space for A
cudaMalloc(&d_sums, DSIZE*sizeof(float)); // allocate device space for vector d_sums
cudaCheckErrors("cudaMalloc failure"); // error checking
// copy matrix A to device:
cudaMemcpy(d_A, h_A, DSIZE*DSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaCheckErrors("cudaMemcpy H2D failure");
//cuda processing sequence step 1 is complete
row_sums<<<DSIZE, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
cudaMemcpy(h_sums, d_sums, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or cudaMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("row sums correct!\n");
cudaMemset(d_sums, 0, DSIZE*sizeof(float));
column_sums<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
cudaMemcpy(h_sums, d_sums, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or cudaMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("column sums correct!\n");
return 0;
} | code for sm_80
Function : _Z11column_sumsPKfPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ UMOV UR7, 0x3 ; /* 0x0000000300077882 */
/* 0x000fe20000000000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R0, P1, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007f3e1ff */
/*00e0*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0100*/ ULOP3.LUT UR7, UR7, UR4, URZ, 0xc0, !UPT ; /* 0x0000000407077292 */
/* 0x000fe2000f8ec03f */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0120*/ IADD3.X R0, R6, -0x1, RZ, P1, !PT ; /* 0xffffffff06007810 */
/* 0x000fc80000ffe4ff */
/*0130*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f06100 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*0150*/ @!P0 BRA 0x3a0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0160*/ UMOV UR4, 0x4 ; /* 0x0000000400047882 */
/* 0x000fe20000000000 */
/*0170*/ IMAD.SHL.U32 R17, R6, 0x4, RZ ; /* 0x0000000406117824 */
/* 0x000fe200078e00ff */
/*0180*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*0190*/ LEA R8, P0, R2.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580002087a11 */
/* 0x040fe200078010ff */
/*01a0*/ UIMAD.WIDE.U32 UR4, UR4, UR8, URZ ; /* 0x00000008040472a5 */
/* 0x000fe2000f8e003f */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ UIADD3 UR12, UP0, UR7, -UR8, URZ ; /* 0x80000008070c7290 */
/* 0x000fe2000ff1e03f */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01e0*/ LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002057a11 */
/* 0x000fe200000f1403 */
/*01f0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R17, R17, UR5, RZ ; /* 0x0000000511117c10 */
/* 0x000fe2000fffe0ff */
/*0210*/ UIADD3.X UR6, URZ, ~UR9, URZ, UP0, !UPT ; /* 0x800000093f067290 */
/* 0x000fc400087fe43f */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0230*/ IADD3 R10, P0, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff1e0ff */
/*0240*/ IADD3.X R11, R5, R17, RZ, P0, !PT ; /* 0x00000011050b7210 */
/* 0x000fe200007fe4ff */
/*0250*/ LDG.E R9, [R8.64] ; /* 0x0000000a08097981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IADD3 R12, P0, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x000fc6000ff1e0ff */
/*0270*/ LDG.E R10, [R10.64] ; /* 0x0000000a0a0a7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.X R13, R11, 0x1, R17, P0 ; /* 0x000000010b0d7824 */
/* 0x000fe200000e0611 */
/*0290*/ IADD3 R4, P0, R12, UR4, RZ ; /* 0x000000040c047c10 */
/* 0x000fc8000ff1e0ff */
/*02a0*/ LDG.E R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.X R5, R13, 0x1, R17, P0 ; /* 0x000000010d057824 */
/* 0x000fca00000e0611 */
/*02c0*/ LDG.E R14, [R4.64] ; /* 0x0000000a040e7981 */
/* 0x000162000c1e1900 */
/*02d0*/ IADD3 R7, P0, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc80007f1e0ff */
/*02e0*/ IADD3 R15, P1, R7, UR12, RZ ; /* 0x0000000c070f7c10 */
/* 0x000fe2000ff3e0ff */
/*02f0*/ IMAD.X R16, RZ, RZ, R16, P0 ; /* 0x000000ffff107224 */
/* 0x000fc600000e0610 */
/*0300*/ ISETP.NE.U32.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f05070 */
/*0310*/ FADD R9, R9, R0 ; /* 0x0000000009097221 */
/* 0x004fe20000000000 */
/*0320*/ IADD3.X R0, R16, UR6, RZ, P1, !PT ; /* 0x0000000610007c10 */
/* 0x000fc80008ffe4ff */
/*0330*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*0340*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x008fe20000000000 */
/*0350*/ IADD3 R8, P1, R4, UR4, RZ ; /* 0x0000000404087c10 */
/* 0x000fc6000ff3e0ff */
/*0360*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x010fe40000000000 */
/*0370*/ IMAD.X R5, R5, 0x1, R17, P1 ; /* 0x0000000105057824 */
/* 0x001fe400008e0611 */
/*0380*/ FADD R0, R9, R14 ; /* 0x0000000e09007221 */
/* 0x020fc80000000000 */
/*0390*/ @P0 BRA 0x220 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*03a0*/ ISETP.NE.U32.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fe4000bf05070 */
/*03b0*/ LEA R4, P1, R2.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x040fe400078210ff */
/*03c0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*03d0*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0002057a11 */
/* 0x000fd600008f1403 */
/*03e0*/ @!P0 BRA 0x540 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD R16, R16, c[0x0][0x170], RZ ; /* 0x00005c0010107a24 */
/* 0x000fe200078e02ff */
/*0400*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0410*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; /* 0x00005c0007027a25 */
/* 0x000fe200078e0002 */
/*0420*/ UIADD3 UR4, UP0, URZ, -UR7, URZ ; /* 0x800000073f047290 */
/* 0x000fc6000ff1e03f */
/*0430*/ IMAD R9, R7, c[0x0][0x174], R16 ; /* 0x00005d0007097a24 */
/* 0x000fe200078e0210 */
/*0440*/ LEA R7, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002077a11 */
/* 0x000fe200078010ff */
/*0450*/ UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f057890 */
/* 0x000fe400087fe43f */
/*0460*/ IMAD.IADD R3, R3, 0x1, R9 ; /* 0x0000000103037824 */
/* 0x000fe200078e0209 */
/*0470*/ SHF.L.U64.HI R9, R8, 0x2, R6 ; /* 0x0000000208097819 */
/* 0x000fc80000010206 */
/*0480*/ LEA.HI.X R6, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002067a11 */
/* 0x000fca00000f1403 */
/*0490*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0007 */
/*04b0*/ LDG.E R3, [R2.64] ; /* 0x0000000a02037981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*04d0*/ LEA R7, P1, R8, R7, 0x2 ; /* 0x0000000708077211 */
/* 0x000fc600078210ff */
/*04e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*04f0*/ ISETP.NE.U32.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05070 */
/*0500*/ IMAD.X R6, R6, 0x1, R9, P1 ; /* 0x0000000106067824 */
/* 0x000fc600008e0609 */
/*0510*/ ISETP.NE.AND.EX P0, PT, RZ, UR5, PT, P0 ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf05300 */
/*0520*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x004fd80000000000 */
/*0530*/ @P0 BRA 0x490 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0540*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c10190a */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8row_sumsPKfPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x001fe40003f06070 */
/*0030*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011407 */
/*0040*/ ISETP.GE.U32.AND.EX P0, PT, R8, c[0x0][0x174], PT, P0 ; /* 0x00005d0008007a0c */
/* 0x000fda0003f06100 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x250 ; /* 0x000001c000007945 */
/* 0x000fe40003800000 */
/*0090*/ STS [R9.X4], RZ ; /* 0x000000ff09007388 */
/* 0x0011e20000004800 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x040fe20003f06070 */
/*00b0*/ IMAD.SHL.U32 R0, R9, 0x4, RZ ; /* 0x0000000409007824 */
/* 0x000fe200078e00ff */
/*00c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R9 ; /* 0x0000001fff027819 */
/* 0x000fc80000011409 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*00e0*/ @P0 BRA 0x240 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD R4, R8, c[0x0][0x170], RZ ; /* 0x00005c0008047a24 */
/* 0x001fe200078e02ff */
/*0100*/ BSSY B1, 0x230 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0002 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0009 */
/*0140*/ IMAD R13, R7, c[0x0][0x174], R4 ; /* 0x00005d00070d7a24 */
/* 0x000fe400078e0204 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fc800078e000b */
/*0170*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; /* 0x00005c0007027a25 */
/* 0x000fc800078e0002 */
/*0180*/ IMAD.IADD R3, R3, 0x1, R13 ; /* 0x0000000103037824 */
/* 0x000fe200078e020d */
/*0190*/ LEA R4, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002047a11 */
/* 0x000fc800078010ff */
/*01a0*/ LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002057a11 */
/* 0x000fcc00000f1403 */
/*01b0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R10, P0, R10, c[0x0][0x0], RZ ; /* 0x000000000a0a7a10 */
/* 0x000fca0007f1e0ff */
/*01d0*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fc80003f06070 */
/*01f0*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x174], PT, P0 ; /* 0x00005d000b007a0c */
/* 0x000fe20003f06100 */
/*0200*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x004fd80000000000 */
/*0210*/ @!P0 BRA 0x150 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ STS [R9.X4], R6 ; /* 0x0000000609007388 */
/* 0x0001e40000004800 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0250*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0260*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0270*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0280*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0290*/ @!P1 BRA 0x350 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fc8000f8e00ff */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GE.U32.AND P1, PT, R9, R3, PT ; /* 0x000000030900720c */
/* 0x000fda0003f26070 */
/*02d0*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*02e0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*02f0*/ @!P1 LDS R4, [R9.X4] ; /* 0x0000000009049984 */
/* 0x000fe80000004800 */
/*0300*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0310*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0320*/ @!P1 STS [R9.X4], R4 ; /* 0x0000000409009388 */
/* 0x0001e20000004800 */
/*0330*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0340*/ @P1 BRA 0x2b0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0360*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0370*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fc800078010ff */
/*0380*/ LEA.HI.X R3, R7, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fca00000f1408 */
/*0390*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const size_t DSIZE = 16384; // matrix side dimension
const int block_size = 256; // CUDA maximum is 1024
// matrix row-sum kernel
// we will assign one block per row
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = blockIdx.x; // our block index becomes our row indicator
if (idx < ds){
__shared__ float sdata[block_size];
int tid = threadIdx.x;
sdata[tid] = 0.0f;
size_t tidx = tid;
while (tidx < ds) { // block stride loop to load data
sdata[tid] += A[idx*ds+tidx];
tidx += blockDim.x;
}
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
__syncthreads();
if (tid < s) // parallel sweep reduction
sdata[tid] += sdata[tid + s];
}
if (tid == 0) sums[idx] = sdata[0];
}
}
// matrix column-sum kernel
__global__ void column_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx+ds*i]; // write a for loop that will cause the thread to iterate down a column, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}}
bool validate(float *data, size_t sz){
for (size_t i = 0; i < sz; i++)
if (data[i] != (float)sz) {printf("results mismatch at %lu, was: %f, should be: %f\n", i, data[i], (float)sz); return false;}
return true;
}
int main(){
float *h_A, *h_sums, *d_A, *d_sums;
h_A = new float[DSIZE*DSIZE]; // allocate space for data in host memory
h_sums = new float[DSIZE]();
for (int i = 0; i < DSIZE*DSIZE; i++) // initialize matrix in host memory
h_A[i] = 1.0f;
cudaMalloc(&d_A, DSIZE*DSIZE*sizeof(float)); // allocate device space for A
cudaMalloc(&d_sums, DSIZE*sizeof(float)); // allocate device space for vector d_sums
cudaCheckErrors("cudaMalloc failure"); // error checking
// copy matrix A to device:
cudaMemcpy(d_A, h_A, DSIZE*DSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaCheckErrors("cudaMemcpy H2D failure");
//cuda processing sequence step 1 is complete
row_sums<<<DSIZE, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
cudaMemcpy(h_sums, d_sums, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or cudaMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("row sums correct!\n");
cudaMemset(d_sums, 0, DSIZE*sizeof(float));
column_sums<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
cudaMemcpy(h_sums, d_sums, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or cudaMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("column sums correct!\n");
return 0;
} | .file "tmpxft_000b3654_00000000-6_matrix_sums_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "results mismatch at %lu, was: %f, should be: %f\n"
.text
.globl _Z8validatePfm
.type _Z8validatePfm, @function
_Z8validatePfm:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L10
movl $0, %edx
movq %rsi, %rcx
andl $1, %ecx
jmp .L9
.L5:
movq %rsi, %rax
shrq %rax
orq %rcx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
.L6:
ucomiss %xmm1, %xmm0
jp .L11
jne .L11
addq $1, %rdx
cmpq %rdx, %rsi
je .L16
.L9:
movss (%rdi,%rdx,4), %xmm0
testq %rsi, %rsi
js .L5
pxor %xmm1, %xmm1
cvtsi2ssq %rsi, %xmm1
jmp .L6
.L11:
subq $8, %rsp
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
movl $1, %eax
ret
.L10:
movl $1, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z8validatePfm, .-_Z8validatePfm
.globl _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.type _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, @function
_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8row_sumsPKfPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, .-_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.globl _Z8row_sumsPKfPfm
.type _Z8row_sumsPKfPfm, @function
_Z8row_sumsPKfPfm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8row_sumsPKfPfm, .-_Z8row_sumsPKfPfm
.globl _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
.type _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm, @function
_Z35__device_stub__Z11column_sumsPKfPfmPKfPfm:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11column_sumsPKfPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm, .-_Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
.globl _Z11column_sumsPKfPfm
.type _Z11column_sumsPKfPfm, @function
_Z11column_sumsPKfPfm:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11column_sumsPKfPfm, .-_Z11column_sumsPKfPfm
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mlwong/cuda-training-series/master/exercises/hw5/matrix_sums_solution.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "cudaMalloc failure"
.section .rodata.str1.8
.align 8
.LC5:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC6:
.string "*** FAILED - ABORTING\n"
.LC7:
.string "cudaMemcpy H2D failure"
.LC8:
.string "kernel launch failure"
.section .rodata.str1.8
.align 8
.LC9:
.string "kernel execution failure or cudaMemcpy H2D failure"
.section .rodata.str1.1
.LC10:
.string "row sums correct!\n"
.LC11:
.string "column sums correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %rbp
movl $65536, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 65536(%rax), %rdx
.L34:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L34
movq %rbp, %rax
leaq 1073741824(%rbp), %rdx
movss .LC2(%rip), %xmm0
.L35:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L35
movq %rsp, %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L51
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L38:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L54
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L55
movl $16384, %esi
movq %rbx, %rdi
call _Z8validatePfm
testb %al, %al
je .L46
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $65536, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L42:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L57
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L58
movl $16384, %esi
movq %rbx, %rdi
call _Z8validatePfm
testb %al, %al
je .L47
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L33:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L59
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $69
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $72
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC7(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl $16384, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
jmp .L38
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $75
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $80
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC9(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $16384, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
jmp .L42
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $85
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $90
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC9(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl $-1, %eax
jmp .L33
.L47:
movl $-1, %eax
jmp .L33
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11column_sumsPKfPfm"
.LC13:
.string "_Z8row_sumsPKfPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11column_sumsPKfPfm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8row_sumsPKfPfm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const size_t DSIZE = 16384; // matrix side dimension
const int block_size = 256; // CUDA maximum is 1024
// matrix row-sum kernel
// we will assign one block per row
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = blockIdx.x; // our block index becomes our row indicator
if (idx < ds){
__shared__ float sdata[block_size];
int tid = threadIdx.x;
sdata[tid] = 0.0f;
size_t tidx = tid;
while (tidx < ds) { // block stride loop to load data
sdata[tid] += A[idx*ds+tidx];
tidx += blockDim.x;
}
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
__syncthreads();
if (tid < s) // parallel sweep reduction
sdata[tid] += sdata[tid + s];
}
if (tid == 0) sums[idx] = sdata[0];
}
}
// matrix column-sum kernel
__global__ void column_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx+ds*i]; // write a for loop that will cause the thread to iterate down a column, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}}
bool validate(float *data, size_t sz){
for (size_t i = 0; i < sz; i++)
if (data[i] != (float)sz) {printf("results mismatch at %lu, was: %f, should be: %f\n", i, data[i], (float)sz); return false;}
return true;
}
int main(){
float *h_A, *h_sums, *d_A, *d_sums;
h_A = new float[DSIZE*DSIZE]; // allocate space for data in host memory
h_sums = new float[DSIZE]();
for (int i = 0; i < DSIZE*DSIZE; i++) // initialize matrix in host memory
h_A[i] = 1.0f;
cudaMalloc(&d_A, DSIZE*DSIZE*sizeof(float)); // allocate device space for A
cudaMalloc(&d_sums, DSIZE*sizeof(float)); // allocate device space for vector d_sums
cudaCheckErrors("cudaMalloc failure"); // error checking
// copy matrix A to device:
cudaMemcpy(d_A, h_A, DSIZE*DSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaCheckErrors("cudaMemcpy H2D failure");
//cuda processing sequence step 1 is complete
row_sums<<<DSIZE, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
cudaMemcpy(h_sums, d_sums, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or cudaMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("row sums correct!\n");
cudaMemset(d_sums, 0, DSIZE*sizeof(float));
column_sums<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
cudaMemcpy(h_sums, d_sums, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or cudaMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("column sums correct!\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const size_t DSIZE = 16384; // matrix side dimension
const int block_size = 256; // CUDA maximum is 1024
// matrix row-sum kernel
// we will assign one block per row
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = blockIdx.x; // our block index becomes our row indicator
if (idx < ds){
__shared__ float sdata[block_size];
int tid = threadIdx.x;
sdata[tid] = 0.0f;
size_t tidx = tid;
while (tidx < ds) { // block stride loop to load data
sdata[tid] += A[idx*ds+tidx];
tidx += blockDim.x;
}
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
__syncthreads();
if (tid < s) // parallel sweep reduction
sdata[tid] += sdata[tid + s];
}
if (tid == 0) sums[idx] = sdata[0];
}
}
// matrix column-sum kernel
__global__ void column_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx+ds*i]; // write a for loop that will cause the thread to iterate down a column, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}}
bool validate(float *data, size_t sz){
for (size_t i = 0; i < sz; i++)
if (data[i] != (float)sz) {printf("results mismatch at %lu, was: %f, should be: %f\n", i, data[i], (float)sz); return false;}
return true;
}
int main(){
float *h_A, *h_sums, *d_A, *d_sums;
h_A = new float[DSIZE*DSIZE]; // allocate space for data in host memory
h_sums = new float[DSIZE]();
for (int i = 0; i < DSIZE*DSIZE; i++) // initialize matrix in host memory
h_A[i] = 1.0f;
hipMalloc(&d_A, DSIZE*DSIZE*sizeof(float)); // allocate device space for A
hipMalloc(&d_sums, DSIZE*sizeof(float)); // allocate device space for vector d_sums
cudaCheckErrors("hipMalloc failure"); // error checking
// copy matrix A to device:
hipMemcpy(d_A, h_A, DSIZE*DSIZE*sizeof(float), hipMemcpyHostToDevice);
cudaCheckErrors("hipMemcpy H2D failure");
//cuda processing sequence step 1 is complete
row_sums<<<DSIZE, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
hipMemcpy(h_sums, d_sums, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or hipMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("row sums correct!\n");
hipMemset(d_sums, 0, DSIZE*sizeof(float));
column_sums<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
hipMemcpy(h_sums, d_sums, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or hipMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("column sums correct!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const size_t DSIZE = 16384; // matrix side dimension
const int block_size = 256; // CUDA maximum is 1024
// matrix row-sum kernel
// we will assign one block per row
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = blockIdx.x; // our block index becomes our row indicator
if (idx < ds){
__shared__ float sdata[block_size];
int tid = threadIdx.x;
sdata[tid] = 0.0f;
size_t tidx = tid;
while (tidx < ds) { // block stride loop to load data
sdata[tid] += A[idx*ds+tidx];
tidx += blockDim.x;
}
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
__syncthreads();
if (tid < s) // parallel sweep reduction
sdata[tid] += sdata[tid + s];
}
if (tid == 0) sums[idx] = sdata[0];
}
}
// matrix column-sum kernel
__global__ void column_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx+ds*i]; // write a for loop that will cause the thread to iterate down a column, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}}
bool validate(float *data, size_t sz){
for (size_t i = 0; i < sz; i++)
if (data[i] != (float)sz) {printf("results mismatch at %lu, was: %f, should be: %f\n", i, data[i], (float)sz); return false;}
return true;
}
int main(){
float *h_A, *h_sums, *d_A, *d_sums;
h_A = new float[DSIZE*DSIZE]; // allocate space for data in host memory
h_sums = new float[DSIZE]();
for (int i = 0; i < DSIZE*DSIZE; i++) // initialize matrix in host memory
h_A[i] = 1.0f;
hipMalloc(&d_A, DSIZE*DSIZE*sizeof(float)); // allocate device space for A
hipMalloc(&d_sums, DSIZE*sizeof(float)); // allocate device space for vector d_sums
cudaCheckErrors("hipMalloc failure"); // error checking
// copy matrix A to device:
hipMemcpy(d_A, h_A, DSIZE*DSIZE*sizeof(float), hipMemcpyHostToDevice);
cudaCheckErrors("hipMemcpy H2D failure");
//cuda processing sequence step 1 is complete
row_sums<<<DSIZE, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
hipMemcpy(h_sums, d_sums, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or hipMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("row sums correct!\n");
hipMemset(d_sums, 0, DSIZE*sizeof(float));
column_sums<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
hipMemcpy(h_sums, d_sums, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or hipMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("column sums correct!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8row_sumsPKfPfm
.globl _Z8row_sumsPKfPfm
.p2align 8
.type _Z8row_sumsPKfPfm,@function
_Z8row_sumsPKfPfm:
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
s_waitcnt lgkmcnt(0)
v_cmp_ge_u64_e64 s2, s[4:5], s[6:7]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_12
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v6, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v6, v1
v_cmpx_gt_u64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[10:11], s[0:1], 0x0
ds_load_b32 v7, v6
s_mul_i32 s9, s6, s5
s_mul_hi_u32 s12, s6, s4
s_mul_i32 s13, s7, s4
s_add_i32 s9, s12, s9
s_mul_i32 s12, s6, s4
s_add_i32 s13, s9, s13
v_dual_mov_b32 v5, v1 :: v_dual_lshlrev_b32 v2, 2, v0
s_lshl_b64 s[12:13], s[12:13], 2
v_mov_b32_e32 v4, v0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s2, 0xffff
s_add_u32 s2, s10, s12
s_addc_u32 s10, s11, s13
v_add_co_u32 v2, s2, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s10, 0, s2
s_lshl_b32 s10, s9, 2
s_mov_b32 s12, s8
s_mov_b32 s11, s8
.LBB0_3:
global_load_b32 v1, v[2:3], off
v_add_co_u32 v4, vcc_lo, v4, s9
v_add_co_ci_u32_e32 v5, vcc_lo, s8, v5, vcc_lo
v_add_co_u32 v2, s2, v2, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s12, v3, s2
v_cmp_le_u64_e32 vcc_lo, s[6:7], v[4:5]
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v1, v7
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s11
ds_store_b32 v6, v7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s3, s2, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_cbranch_scc1 .LBB0_10
.LBB0_8:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_7
v_add_lshl_u32 v1, s2, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v6, v1
s_branch .LBB0_7
.LBB0_10:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8row_sumsPKfPfm
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8row_sumsPKfPfm, .Lfunc_end0-_Z8row_sumsPKfPfm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11column_sumsPKfPfm
.globl _Z11column_sumsPKfPfm
.p2align 8
.type _Z11column_sumsPKfPfm,@function
_Z11column_sumsPKfPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB1_4
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 2
.LBB1_2:
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, s4
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
s_cbranch_scc0 .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11column_sumsPKfPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11column_sumsPKfPfm, .Lfunc_end1-_Z11column_sumsPKfPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8row_sumsPKfPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8row_sumsPKfPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11column_sumsPKfPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11column_sumsPKfPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const size_t DSIZE = 16384; // matrix side dimension
const int block_size = 256; // CUDA maximum is 1024
// matrix row-sum kernel
// we will assign one block per row
__global__ void row_sums(const float *A, float *sums, size_t ds){
int idx = blockIdx.x; // our block index becomes our row indicator
if (idx < ds){
__shared__ float sdata[block_size];
int tid = threadIdx.x;
sdata[tid] = 0.0f;
size_t tidx = tid;
while (tidx < ds) { // block stride loop to load data
sdata[tid] += A[idx*ds+tidx];
tidx += blockDim.x;
}
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
__syncthreads();
if (tid < s) // parallel sweep reduction
sdata[tid] += sdata[tid + s];
}
if (tid == 0) sums[idx] = sdata[0];
}
}
// matrix column-sum kernel
__global__ void column_sums(const float *A, float *sums, size_t ds){
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create typical 1D thread index from built-in variables
if (idx < ds){
float sum = 0.0f;
for (size_t i = 0; i < ds; i++)
sum += A[idx+ds*i]; // write a for loop that will cause the thread to iterate down a column, keeeping a running sum, and write the result to sums
sums[idx] = sum;
}}
bool validate(float *data, size_t sz){
for (size_t i = 0; i < sz; i++)
if (data[i] != (float)sz) {printf("results mismatch at %lu, was: %f, should be: %f\n", i, data[i], (float)sz); return false;}
return true;
}
int main(){
float *h_A, *h_sums, *d_A, *d_sums;
h_A = new float[DSIZE*DSIZE]; // allocate space for data in host memory
h_sums = new float[DSIZE]();
for (int i = 0; i < DSIZE*DSIZE; i++) // initialize matrix in host memory
h_A[i] = 1.0f;
hipMalloc(&d_A, DSIZE*DSIZE*sizeof(float)); // allocate device space for A
hipMalloc(&d_sums, DSIZE*sizeof(float)); // allocate device space for vector d_sums
cudaCheckErrors("hipMalloc failure"); // error checking
// copy matrix A to device:
hipMemcpy(d_A, h_A, DSIZE*DSIZE*sizeof(float), hipMemcpyHostToDevice);
cudaCheckErrors("hipMemcpy H2D failure");
//cuda processing sequence step 1 is complete
row_sums<<<DSIZE, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
hipMemcpy(h_sums, d_sums, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or hipMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("row sums correct!\n");
hipMemset(d_sums, 0, DSIZE*sizeof(float));
column_sums<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_sums, DSIZE);
cudaCheckErrors("kernel launch failure");
//cuda processing sequence step 2 is complete
// copy vector sums from device to host:
hipMemcpy(h_sums, d_sums, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
//cuda processing sequence step 3 is complete
cudaCheckErrors("kernel execution failure or hipMemcpy H2D failure");
if (!validate(h_sums, DSIZE)) return -1;
printf("column sums correct!\n");
return 0;
} | .text
.file "matrix_sums_solution.hip"
.globl _Z23__device_stub__row_sumsPKfPfm # -- Begin function _Z23__device_stub__row_sumsPKfPfm
.p2align 4, 0x90
.type _Z23__device_stub__row_sumsPKfPfm,@function
_Z23__device_stub__row_sumsPKfPfm: # @_Z23__device_stub__row_sumsPKfPfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8row_sumsPKfPfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__row_sumsPKfPfm, .Lfunc_end0-_Z23__device_stub__row_sumsPKfPfm
.cfi_endproc
# -- End function
.globl _Z26__device_stub__column_sumsPKfPfm # -- Begin function _Z26__device_stub__column_sumsPKfPfm
.p2align 4, 0x90
.type _Z26__device_stub__column_sumsPKfPfm,@function
_Z26__device_stub__column_sumsPKfPfm: # @_Z26__device_stub__column_sumsPKfPfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11column_sumsPKfPfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__column_sumsPKfPfm, .Lfunc_end1-_Z26__device_stub__column_sumsPKfPfm
.cfi_endproc
# -- End function
.globl _Z8validatePfm # -- Begin function _Z8validatePfm
.p2align 4, 0x90
.type _Z8validatePfm,@function
_Z8validatePfm: # @_Z8validatePfm
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
testq %rsi, %rsi
sete %bl
je .LBB2_12
# %bb.1: # %.lr.ph
js .LBB2_2
# %bb.3: # %.lr.ph
cvtsi2ss %rsi, %xmm1
jmp .LBB2_4
.LBB2_2:
movq %rsi, %rax
shrq %rax
movl %esi, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm1
addss %xmm1, %xmm1
.LBB2_4: # %.lr.ph
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB2_5
jnp .LBB2_9
.LBB2_5:
xorl %eax, %eax
jmp .LBB2_8
.LBB2_9: # %.lr.ph32.preheader
leaq -1(%rsi), %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_10: # %.lr.ph32
# =>This Inner Loop Header: Depth=1
cmpq %rax, %rcx
je .LBB2_11
# %bb.6: # in Loop: Header=BB2_10 Depth=1
movss 4(%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %rax
ucomiss %xmm1, %xmm0
jne .LBB2_7
jnp .LBB2_10
.LBB2_7: # %._crit_edge.loopexit
cmpq %rsi, %rax
setae %bl
.LBB2_8: # %._crit_edge
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movq %rax, %rsi
movb $2, %al
callq printf
.LBB2_12: # %.loopexit
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 16
movb $1, %bl
jmp .LBB2_12
.Lfunc_end2:
.size _Z8validatePfm, .Lfunc_end2-_Z8validatePfm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x46800000 # float 16384
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x40d0000000000000 # double 16384
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r14
movl $65536, %edi # imm = 0x10000
callq _Znam
movq %rax, %rbx
xorl %r15d, %r15d
movl $65536, %edx # imm = 0x10000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%r15,4) # imm = 0x3F800000
incq %r15
cmpq $268435456, %r15 # imm = 0x10000000
jne .LBB3_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB3_3
# %bb.5:
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_6
# %bb.7:
movabsq $4294967552, %r14 # imm = 0x100000100
leaq 16128(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $16384, 72(%rsp) # imm = 0x4000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8row_sumsPKfPfm, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_10
# %bb.11:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_14
# %bb.12: # %.preheader61
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI3_0(%rip), %xmm0
jne .LBB3_13
jnp .LBB3_18
.LBB3_13:
xorl %r15d, %r15d
xorl %esi, %esi
jmp .LBB3_17
.LBB3_18: # %.lr.ph.preheader
xorl %esi, %esi
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $16383, %rsi # imm = 0x3FFF
je .LBB3_20
# %bb.15: # in Loop: Header=BB3_19 Depth=1
movss 4(%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %rsi
ucomiss %xmm1, %xmm0
jne .LBB3_16
jnp .LBB3_19
.LBB3_16: # %._crit_edge.loopexit
leaq -1(%rsi), %rax
cmpq $16383, %rax # imm = 0x3FFF
setae %r15b
.LBB3_17: # %._crit_edge
cvtss2sd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
movl $.L.str, %edi
movb $2, %al
callq printf
.LBB3_21: # %_Z8validatePfm.exit
movl $-1, %ebp
testb %r15b, %r15b
je .LBB3_38
# %bb.22:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
xorl %esi, %esi
callq hipMemset
leaq -192(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_24
# %bb.23:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $16384, 72(%rsp) # imm = 0x4000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11column_sumsPKfPfm, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_24:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_25
# %bb.26:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_29
# %bb.27: # %.preheader
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI3_0(%rip), %xmm0
jne .LBB3_28
jnp .LBB3_33
.LBB3_28:
xorl %ebx, %ebx
xorl %esi, %esi
jmp .LBB3_32
.LBB3_20: # %_Z8validatePfm.exit.loopexit
setae %r15b
jmp .LBB3_21
.LBB3_33: # %.lr.ph78.preheader
xorl %esi, %esi
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_34: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
cmpq $16383, %rsi # imm = 0x3FFF
je .LBB3_35
# %bb.30: # in Loop: Header=BB3_34 Depth=1
movss 4(%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %rsi
ucomiss %xmm1, %xmm0
jne .LBB3_31
jnp .LBB3_34
.LBB3_31: # %._crit_edge79.loopexit
leaq -1(%rsi), %rax
cmpq $16383, %rax # imm = 0x3FFF
setae %bl
.LBB3_32: # %._crit_edge79
cvtss2sd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
movl $.L.str, %edi
movb $2, %al
callq printf
testb %bl, %bl
je .LBB3_38
.LBB3_37:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebp, %ebp
.LBB3_38:
movl %ebp, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_35: # %_Z8validatePfm.exit51.loopexit
.cfi_def_cfa_offset 160
setae %bl
testb %bl, %bl
jne .LBB3_37
jmp .LBB3_38
.LBB3_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $71, %r9d
jmp .LBB3_4
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.5, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $74, %r9d
jmp .LBB3_4
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.6, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $77, %r9d
jmp .LBB3_4
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.7, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $82, %r9d
jmp .LBB3_4
.LBB3_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.6, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $87, %r9d
jmp .LBB3_4
.LBB3_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.7, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $92, %r9d
.LBB3_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8row_sumsPKfPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11column_sumsPKfPfm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8row_sumsPKfPfm,@object # @_Z8row_sumsPKfPfm
.section .rodata,"a",@progbits
.globl _Z8row_sumsPKfPfm
.p2align 3, 0x0
_Z8row_sumsPKfPfm:
.quad _Z23__device_stub__row_sumsPKfPfm
.size _Z8row_sumsPKfPfm, 8
.type _Z11column_sumsPKfPfm,@object # @_Z11column_sumsPKfPfm
.globl _Z11column_sumsPKfPfm
.p2align 3, 0x0
_Z11column_sumsPKfPfm:
.quad _Z26__device_stub__column_sumsPKfPfm
.size _Z11column_sumsPKfPfm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "results mismatch at %lu, was: %f, should be: %f\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc failure"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mlwong/cuda-training-series/master/exercises/hw5/matrix_sums_solution.hip"
.size .L.str.3, 131
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy H2D failure"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "kernel launch failure"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "kernel execution failure or hipMemcpy H2D failure"
.size .L.str.7, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8row_sumsPKfPfm"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11column_sumsPKfPfm"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "row sums correct!"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "column sums correct!"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__row_sumsPKfPfm
.addrsig_sym _Z26__device_stub__column_sumsPKfPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8row_sumsPKfPfm
.addrsig_sym _Z11column_sumsPKfPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11column_sumsPKfPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ UMOV UR7, 0x3 ; /* 0x0000000300077882 */
/* 0x000fe20000000000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R0, P1, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007f3e1ff */
/*00e0*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0100*/ ULOP3.LUT UR7, UR7, UR4, URZ, 0xc0, !UPT ; /* 0x0000000407077292 */
/* 0x000fe2000f8ec03f */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0120*/ IADD3.X R0, R6, -0x1, RZ, P1, !PT ; /* 0xffffffff06007810 */
/* 0x000fc80000ffe4ff */
/*0130*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f06100 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*0150*/ @!P0 BRA 0x3a0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0160*/ UMOV UR4, 0x4 ; /* 0x0000000400047882 */
/* 0x000fe20000000000 */
/*0170*/ IMAD.SHL.U32 R17, R6, 0x4, RZ ; /* 0x0000000406117824 */
/* 0x000fe200078e00ff */
/*0180*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*0190*/ LEA R8, P0, R2.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580002087a11 */
/* 0x040fe200078010ff */
/*01a0*/ UIMAD.WIDE.U32 UR4, UR4, UR8, URZ ; /* 0x00000008040472a5 */
/* 0x000fe2000f8e003f */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ UIADD3 UR12, UP0, UR7, -UR8, URZ ; /* 0x80000008070c7290 */
/* 0x000fe2000ff1e03f */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01e0*/ LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002057a11 */
/* 0x000fe200000f1403 */
/*01f0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R17, R17, UR5, RZ ; /* 0x0000000511117c10 */
/* 0x000fe2000fffe0ff */
/*0210*/ UIADD3.X UR6, URZ, ~UR9, URZ, UP0, !UPT ; /* 0x800000093f067290 */
/* 0x000fc400087fe43f */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0230*/ IADD3 R10, P0, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff1e0ff */
/*0240*/ IADD3.X R11, R5, R17, RZ, P0, !PT ; /* 0x00000011050b7210 */
/* 0x000fe200007fe4ff */
/*0250*/ LDG.E R9, [R8.64] ; /* 0x0000000a08097981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IADD3 R12, P0, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x000fc6000ff1e0ff */
/*0270*/ LDG.E R10, [R10.64] ; /* 0x0000000a0a0a7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.X R13, R11, 0x1, R17, P0 ; /* 0x000000010b0d7824 */
/* 0x000fe200000e0611 */
/*0290*/ IADD3 R4, P0, R12, UR4, RZ ; /* 0x000000040c047c10 */
/* 0x000fc8000ff1e0ff */
/*02a0*/ LDG.E R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.X R5, R13, 0x1, R17, P0 ; /* 0x000000010d057824 */
/* 0x000fca00000e0611 */
/*02c0*/ LDG.E R14, [R4.64] ; /* 0x0000000a040e7981 */
/* 0x000162000c1e1900 */
/*02d0*/ IADD3 R7, P0, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc80007f1e0ff */
/*02e0*/ IADD3 R15, P1, R7, UR12, RZ ; /* 0x0000000c070f7c10 */
/* 0x000fe2000ff3e0ff */
/*02f0*/ IMAD.X R16, RZ, RZ, R16, P0 ; /* 0x000000ffff107224 */
/* 0x000fc600000e0610 */
/*0300*/ ISETP.NE.U32.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f05070 */
/*0310*/ FADD R9, R9, R0 ; /* 0x0000000009097221 */
/* 0x004fe20000000000 */
/*0320*/ IADD3.X R0, R16, UR6, RZ, P1, !PT ; /* 0x0000000610007c10 */
/* 0x000fc80008ffe4ff */
/*0330*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*0340*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x008fe20000000000 */
/*0350*/ IADD3 R8, P1, R4, UR4, RZ ; /* 0x0000000404087c10 */
/* 0x000fc6000ff3e0ff */
/*0360*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x010fe40000000000 */
/*0370*/ IMAD.X R5, R5, 0x1, R17, P1 ; /* 0x0000000105057824 */
/* 0x001fe400008e0611 */
/*0380*/ FADD R0, R9, R14 ; /* 0x0000000e09007221 */
/* 0x020fc80000000000 */
/*0390*/ @P0 BRA 0x220 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*03a0*/ ISETP.NE.U32.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fe4000bf05070 */
/*03b0*/ LEA R4, P1, R2.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x040fe400078210ff */
/*03c0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*03d0*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0002057a11 */
/* 0x000fd600008f1403 */
/*03e0*/ @!P0 BRA 0x540 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD R16, R16, c[0x0][0x170], RZ ; /* 0x00005c0010107a24 */
/* 0x000fe200078e02ff */
/*0400*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0410*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; /* 0x00005c0007027a25 */
/* 0x000fe200078e0002 */
/*0420*/ UIADD3 UR4, UP0, URZ, -UR7, URZ ; /* 0x800000073f047290 */
/* 0x000fc6000ff1e03f */
/*0430*/ IMAD R9, R7, c[0x0][0x174], R16 ; /* 0x00005d0007097a24 */
/* 0x000fe200078e0210 */
/*0440*/ LEA R7, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002077a11 */
/* 0x000fe200078010ff */
/*0450*/ UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f057890 */
/* 0x000fe400087fe43f */
/*0460*/ IMAD.IADD R3, R3, 0x1, R9 ; /* 0x0000000103037824 */
/* 0x000fe200078e0209 */
/*0470*/ SHF.L.U64.HI R9, R8, 0x2, R6 ; /* 0x0000000208097819 */
/* 0x000fc80000010206 */
/*0480*/ LEA.HI.X R6, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002067a11 */
/* 0x000fca00000f1403 */
/*0490*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0007 */
/*04b0*/ LDG.E R3, [R2.64] ; /* 0x0000000a02037981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*04d0*/ LEA R7, P1, R8, R7, 0x2 ; /* 0x0000000708077211 */
/* 0x000fc600078210ff */
/*04e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*04f0*/ ISETP.NE.U32.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05070 */
/*0500*/ IMAD.X R6, R6, 0x1, R9, P1 ; /* 0x0000000106067824 */
/* 0x000fc600008e0609 */
/*0510*/ ISETP.NE.AND.EX P0, PT, RZ, UR5, PT, P0 ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf05300 */
/*0520*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x004fd80000000000 */
/*0530*/ @P0 BRA 0x490 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0540*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c10190a */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8row_sumsPKfPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x001fe40003f06070 */
/*0030*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011407 */
/*0040*/ ISETP.GE.U32.AND.EX P0, PT, R8, c[0x0][0x174], PT, P0 ; /* 0x00005d0008007a0c */
/* 0x000fda0003f06100 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x250 ; /* 0x000001c000007945 */
/* 0x000fe40003800000 */
/*0090*/ STS [R9.X4], RZ ; /* 0x000000ff09007388 */
/* 0x0011e20000004800 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x040fe20003f06070 */
/*00b0*/ IMAD.SHL.U32 R0, R9, 0x4, RZ ; /* 0x0000000409007824 */
/* 0x000fe200078e00ff */
/*00c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R9 ; /* 0x0000001fff027819 */
/* 0x000fc80000011409 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*00e0*/ @P0 BRA 0x240 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD R4, R8, c[0x0][0x170], RZ ; /* 0x00005c0008047a24 */
/* 0x001fe200078e02ff */
/*0100*/ BSSY B1, 0x230 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0002 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0009 */
/*0140*/ IMAD R13, R7, c[0x0][0x174], R4 ; /* 0x00005d00070d7a24 */
/* 0x000fe400078e0204 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fc800078e000b */
/*0170*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; /* 0x00005c0007027a25 */
/* 0x000fc800078e0002 */
/*0180*/ IMAD.IADD R3, R3, 0x1, R13 ; /* 0x0000000103037824 */
/* 0x000fe200078e020d */
/*0190*/ LEA R4, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002047a11 */
/* 0x000fc800078010ff */
/*01a0*/ LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002057a11 */
/* 0x000fcc00000f1403 */
/*01b0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R10, P0, R10, c[0x0][0x0], RZ ; /* 0x000000000a0a7a10 */
/* 0x000fca0007f1e0ff */
/*01d0*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fc80003f06070 */
/*01f0*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x174], PT, P0 ; /* 0x00005d000b007a0c */
/* 0x000fe20003f06100 */
/*0200*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x004fd80000000000 */
/*0210*/ @!P0 BRA 0x150 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ STS [R9.X4], R6 ; /* 0x0000000609007388 */
/* 0x0001e40000004800 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0250*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0260*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0270*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0280*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0290*/ @!P1 BRA 0x350 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fc8000f8e00ff */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GE.U32.AND P1, PT, R9, R3, PT ; /* 0x000000030900720c */
/* 0x000fda0003f26070 */
/*02d0*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*02e0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*02f0*/ @!P1 LDS R4, [R9.X4] ; /* 0x0000000009049984 */
/* 0x000fe80000004800 */
/*0300*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0310*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0320*/ @!P1 STS [R9.X4], R4 ; /* 0x0000000409009388 */
/* 0x0001e20000004800 */
/*0330*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0340*/ @P1 BRA 0x2b0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0360*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0370*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fc800078010ff */
/*0380*/ LEA.HI.X R3, R7, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fca00000f1408 */
/*0390*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8row_sumsPKfPfm
.globl _Z8row_sumsPKfPfm
.p2align 8
.type _Z8row_sumsPKfPfm,@function
_Z8row_sumsPKfPfm:
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
s_waitcnt lgkmcnt(0)
v_cmp_ge_u64_e64 s2, s[4:5], s[6:7]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_12
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v6, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v6, v1
v_cmpx_gt_u64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[10:11], s[0:1], 0x0
ds_load_b32 v7, v6
s_mul_i32 s9, s6, s5
s_mul_hi_u32 s12, s6, s4
s_mul_i32 s13, s7, s4
s_add_i32 s9, s12, s9
s_mul_i32 s12, s6, s4
s_add_i32 s13, s9, s13
v_dual_mov_b32 v5, v1 :: v_dual_lshlrev_b32 v2, 2, v0
s_lshl_b64 s[12:13], s[12:13], 2
v_mov_b32_e32 v4, v0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s2, 0xffff
s_add_u32 s2, s10, s12
s_addc_u32 s10, s11, s13
v_add_co_u32 v2, s2, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s10, 0, s2
s_lshl_b32 s10, s9, 2
s_mov_b32 s12, s8
s_mov_b32 s11, s8
.LBB0_3:
global_load_b32 v1, v[2:3], off
v_add_co_u32 v4, vcc_lo, v4, s9
v_add_co_ci_u32_e32 v5, vcc_lo, s8, v5, vcc_lo
v_add_co_u32 v2, s2, v2, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s12, v3, s2
v_cmp_le_u64_e32 vcc_lo, s[6:7], v[4:5]
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v1, v7
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s11
ds_store_b32 v6, v7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s3, s2, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_cbranch_scc1 .LBB0_10
.LBB0_8:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_7
v_add_lshl_u32 v1, s2, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v6, v1
s_branch .LBB0_7
.LBB0_10:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8row_sumsPKfPfm
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8row_sumsPKfPfm, .Lfunc_end0-_Z8row_sumsPKfPfm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11column_sumsPKfPfm
.globl _Z11column_sumsPKfPfm
.p2align 8
.type _Z11column_sumsPKfPfm,@function
_Z11column_sumsPKfPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB1_4
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 2
.LBB1_2:
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, s4
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
s_cbranch_scc0 .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11column_sumsPKfPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11column_sumsPKfPfm, .Lfunc_end1-_Z11column_sumsPKfPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8row_sumsPKfPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8row_sumsPKfPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11column_sumsPKfPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11column_sumsPKfPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b3654_00000000-6_matrix_sums_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "results mismatch at %lu, was: %f, should be: %f\n"
.text
.globl _Z8validatePfm
.type _Z8validatePfm, @function
_Z8validatePfm:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L10
movl $0, %edx
movq %rsi, %rcx
andl $1, %ecx
jmp .L9
.L5:
movq %rsi, %rax
shrq %rax
orq %rcx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
.L6:
ucomiss %xmm1, %xmm0
jp .L11
jne .L11
addq $1, %rdx
cmpq %rdx, %rsi
je .L16
.L9:
movss (%rdi,%rdx,4), %xmm0
testq %rsi, %rsi
js .L5
pxor %xmm1, %xmm1
cvtsi2ssq %rsi, %xmm1
jmp .L6
.L11:
subq $8, %rsp
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
movl $1, %eax
ret
.L10:
movl $1, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z8validatePfm, .-_Z8validatePfm
.globl _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.type _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, @function
_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8row_sumsPKfPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm, .-_Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
.globl _Z8row_sumsPKfPfm
.type _Z8row_sumsPKfPfm, @function
_Z8row_sumsPKfPfm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8row_sumsPKfPfm, .-_Z8row_sumsPKfPfm
.globl _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
.type _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm, @function
_Z35__device_stub__Z11column_sumsPKfPfmPKfPfm:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11column_sumsPKfPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm, .-_Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
.globl _Z11column_sumsPKfPfm
.type _Z11column_sumsPKfPfm, @function
_Z11column_sumsPKfPfm:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11column_sumsPKfPfm, .-_Z11column_sumsPKfPfm
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mlwong/cuda-training-series/master/exercises/hw5/matrix_sums_solution.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "cudaMalloc failure"
.section .rodata.str1.8
.align 8
.LC5:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC6:
.string "*** FAILED - ABORTING\n"
.LC7:
.string "cudaMemcpy H2D failure"
.LC8:
.string "kernel launch failure"
.section .rodata.str1.8
.align 8
.LC9:
.string "kernel execution failure or cudaMemcpy H2D failure"
.section .rodata.str1.1
.LC10:
.string "row sums correct!\n"
.LC11:
.string "column sums correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call _Znam@PLT
movq %rax, %rbp
movl $65536, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 65536(%rax), %rdx
.L34:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L34
movq %rbp, %rax
leaq 1073741824(%rbp), %rdx
movss .LC2(%rip), %xmm0
.L35:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L35
movq %rsp, %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L51
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L38:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L54
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L55
movl $16384, %esi
movq %rbx, %rdi
call _Z8validatePfm
testb %al, %al
je .L46
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $65536, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L42:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L57
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L58
movl $16384, %esi
movq %rbx, %rdi
call _Z8validatePfm
testb %al, %al
je .L47
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L33:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L59
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $69
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $72
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC7(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl $16384, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z8row_sumsPKfPfmPKfPfm
jmp .L38
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $75
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $80
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC9(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $16384, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z11column_sumsPKfPfmPKfPfm
jmp .L42
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $85
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $90
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC9(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl $-1, %eax
jmp .L33
.L47:
movl $-1, %eax
jmp .L33
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11column_sumsPKfPfm"
.LC13:
.string "_Z8row_sumsPKfPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11column_sumsPKfPfm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8row_sumsPKfPfm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_sums_solution.hip"
.globl _Z23__device_stub__row_sumsPKfPfm # -- Begin function _Z23__device_stub__row_sumsPKfPfm
.p2align 4, 0x90
.type _Z23__device_stub__row_sumsPKfPfm,@function
_Z23__device_stub__row_sumsPKfPfm: # @_Z23__device_stub__row_sumsPKfPfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8row_sumsPKfPfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__row_sumsPKfPfm, .Lfunc_end0-_Z23__device_stub__row_sumsPKfPfm
.cfi_endproc
# -- End function
.globl _Z26__device_stub__column_sumsPKfPfm # -- Begin function _Z26__device_stub__column_sumsPKfPfm
.p2align 4, 0x90
.type _Z26__device_stub__column_sumsPKfPfm,@function
_Z26__device_stub__column_sumsPKfPfm: # @_Z26__device_stub__column_sumsPKfPfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11column_sumsPKfPfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__column_sumsPKfPfm, .Lfunc_end1-_Z26__device_stub__column_sumsPKfPfm
.cfi_endproc
# -- End function
.globl _Z8validatePfm # -- Begin function _Z8validatePfm
.p2align 4, 0x90
.type _Z8validatePfm,@function
_Z8validatePfm: # @_Z8validatePfm
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
testq %rsi, %rsi
sete %bl
je .LBB2_12
# %bb.1: # %.lr.ph
js .LBB2_2
# %bb.3: # %.lr.ph
cvtsi2ss %rsi, %xmm1
jmp .LBB2_4
.LBB2_2:
movq %rsi, %rax
shrq %rax
movl %esi, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm1
addss %xmm1, %xmm1
.LBB2_4: # %.lr.ph
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB2_5
jnp .LBB2_9
.LBB2_5:
xorl %eax, %eax
jmp .LBB2_8
.LBB2_9: # %.lr.ph32.preheader
leaq -1(%rsi), %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_10: # %.lr.ph32
# =>This Inner Loop Header: Depth=1
cmpq %rax, %rcx
je .LBB2_11
# %bb.6: # in Loop: Header=BB2_10 Depth=1
movss 4(%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %rax
ucomiss %xmm1, %xmm0
jne .LBB2_7
jnp .LBB2_10
.LBB2_7: # %._crit_edge.loopexit
cmpq %rsi, %rax
setae %bl
.LBB2_8: # %._crit_edge
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movq %rax, %rsi
movb $2, %al
callq printf
.LBB2_12: # %.loopexit
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 16
movb $1, %bl
jmp .LBB2_12
.Lfunc_end2:
.size _Z8validatePfm, .Lfunc_end2-_Z8validatePfm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x46800000 # float 16384
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x40d0000000000000 # double 16384
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq _Znam
movq %rax, %r14
movl $65536, %edi # imm = 0x10000
callq _Znam
movq %rax, %rbx
xorl %r15d, %r15d
movl $65536, %edx # imm = 0x10000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%r15,4) # imm = 0x3F800000
incq %r15
cmpq $268435456, %r15 # imm = 0x10000000
jne .LBB3_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB3_3
# %bb.5:
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_6
# %bb.7:
movabsq $4294967552, %r14 # imm = 0x100000100
leaq 16128(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $16384, 72(%rsp) # imm = 0x4000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8row_sumsPKfPfm, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_10
# %bb.11:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_14
# %bb.12: # %.preheader61
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI3_0(%rip), %xmm0
jne .LBB3_13
jnp .LBB3_18
.LBB3_13:
xorl %r15d, %r15d
xorl %esi, %esi
jmp .LBB3_17
.LBB3_18: # %.lr.ph.preheader
xorl %esi, %esi
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $16383, %rsi # imm = 0x3FFF
je .LBB3_20
# %bb.15: # in Loop: Header=BB3_19 Depth=1
movss 4(%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %rsi
ucomiss %xmm1, %xmm0
jne .LBB3_16
jnp .LBB3_19
.LBB3_16: # %._crit_edge.loopexit
leaq -1(%rsi), %rax
cmpq $16383, %rax # imm = 0x3FFF
setae %r15b
.LBB3_17: # %._crit_edge
cvtss2sd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
movl $.L.str, %edi
movb $2, %al
callq printf
.LBB3_21: # %_Z8validatePfm.exit
movl $-1, %ebp
testb %r15b, %r15b
je .LBB3_38
# %bb.22:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
xorl %esi, %esi
callq hipMemset
leaq -192(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_24
# %bb.23:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $16384, 72(%rsp) # imm = 0x4000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11column_sumsPKfPfm, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_24:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_25
# %bb.26:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_29
# %bb.27: # %.preheader
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI3_0(%rip), %xmm0
jne .LBB3_28
jnp .LBB3_33
.LBB3_28:
xorl %ebx, %ebx
xorl %esi, %esi
jmp .LBB3_32
.LBB3_20: # %_Z8validatePfm.exit.loopexit
setae %r15b
jmp .LBB3_21
.LBB3_33: # %.lr.ph78.preheader
xorl %esi, %esi
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_34: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
cmpq $16383, %rsi # imm = 0x3FFF
je .LBB3_35
# %bb.30: # in Loop: Header=BB3_34 Depth=1
movss 4(%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %rsi
ucomiss %xmm1, %xmm0
jne .LBB3_31
jnp .LBB3_34
.LBB3_31: # %._crit_edge79.loopexit
leaq -1(%rsi), %rax
cmpq $16383, %rax # imm = 0x3FFF
setae %bl
.LBB3_32: # %._crit_edge79
cvtss2sd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
movl $.L.str, %edi
movb $2, %al
callq printf
testb %bl, %bl
je .LBB3_38
.LBB3_37:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebp, %ebp
.LBB3_38:
movl %ebp, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_35: # %_Z8validatePfm.exit51.loopexit
.cfi_def_cfa_offset 160
setae %bl
testb %bl, %bl
jne .LBB3_37
jmp .LBB3_38
.LBB3_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $71, %r9d
jmp .LBB3_4
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.5, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $74, %r9d
jmp .LBB3_4
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.6, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $77, %r9d
jmp .LBB3_4
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.7, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $82, %r9d
jmp .LBB3_4
.LBB3_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.6, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $87, %r9d
jmp .LBB3_4
.LBB3_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.7, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $92, %r9d
.LBB3_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8row_sumsPKfPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11column_sumsPKfPfm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8row_sumsPKfPfm,@object # @_Z8row_sumsPKfPfm
.section .rodata,"a",@progbits
.globl _Z8row_sumsPKfPfm
.p2align 3, 0x0
_Z8row_sumsPKfPfm:
.quad _Z23__device_stub__row_sumsPKfPfm
.size _Z8row_sumsPKfPfm, 8
.type _Z11column_sumsPKfPfm,@object # @_Z11column_sumsPKfPfm
.globl _Z11column_sumsPKfPfm
.p2align 3, 0x0
_Z11column_sumsPKfPfm:
.quad _Z26__device_stub__column_sumsPKfPfm
.size _Z11column_sumsPKfPfm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "results mismatch at %lu, was: %f, should be: %f\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc failure"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mlwong/cuda-training-series/master/exercises/hw5/matrix_sums_solution.hip"
.size .L.str.3, 131
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy H2D failure"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "kernel launch failure"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "kernel execution failure or hipMemcpy H2D failure"
.size .L.str.7, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8row_sumsPKfPfm"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11column_sumsPKfPfm"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "row sums correct!"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "column sums correct!"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__row_sumsPKfPfm
.addrsig_sym _Z26__device_stub__column_sumsPKfPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8row_sumsPKfPfm
.addrsig_sym _Z11column_sumsPKfPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
class A {
public:
int x;
};
A * var;
__global__ void test(A * dvar){
dvar->x = 1;
}
int main(int argc, char* argv[])
{
//int num = 25;
//cudaMemcpyToSymbol(dim,&num,sizeof(int),0,cudaMemcpyHostToDevice);
//int *gpu_Num;
cudaMalloc(&var,sizeof(A));
test<<<1,1>>>(var);
int p;
cudaMemcpy(&p,&(var->x),sizeof(int),cudaMemcpyDefault);
printf("Result: %i\n",p);
} | code for sm_80
Function : _Z4testP1A
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
class A {
public:
int x;
};
A * var;
__global__ void test(A * dvar){
dvar->x = 1;
}
int main(int argc, char* argv[])
{
//int num = 25;
//cudaMemcpyToSymbol(dim,&num,sizeof(int),0,cudaMemcpyHostToDevice);
//int *gpu_Num;
cudaMalloc(&var,sizeof(A));
test<<<1,1>>>(var);
int p;
cudaMemcpy(&p,&(var->x),sizeof(int),cudaMemcpyDefault);
printf("Result: %i\n",p);
} | .file "tmpxft_0004fc26_00000000-6_tosymbol_class.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4testP1AP1A
.type _Z24__device_stub__Z4testP1AP1A, @function
_Z24__device_stub__Z4testP1AP1A:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testP1A(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z4testP1AP1A, .-_Z24__device_stub__Z4testP1AP1A
.globl _Z4testP1A
.type _Z4testP1A, @function
_Z4testP1A:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4testP1AP1A
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4testP1A, .-_Z4testP1A
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result: %i\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4, %esi
leaq var(%rip), %rdi
call cudaMalloc@PLT
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, (%rsp)
movl $1, 4(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 12(%rsp), %rdi
movl $4, %ecx
movl $4, %edx
movq var(%rip), %rsi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq var(%rip), %rdi
call _Z24__device_stub__Z4testP1AP1A
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4testP1A"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testP1A(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl var
.bss
.align 8
.type var, @object
.size var, 8
var:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
class A {
public:
int x;
};
A * var;
__global__ void test(A * dvar){
dvar->x = 1;
}
int main(int argc, char* argv[])
{
//int num = 25;
//cudaMemcpyToSymbol(dim,&num,sizeof(int),0,cudaMemcpyHostToDevice);
//int *gpu_Num;
cudaMalloc(&var,sizeof(A));
test<<<1,1>>>(var);
int p;
cudaMemcpy(&p,&(var->x),sizeof(int),cudaMemcpyDefault);
printf("Result: %i\n",p);
} | #include "stdio.h"
#include <iostream>
#include <hip/hip_runtime.h>
class A {
public:
int x;
};
A * var;
__global__ void test(A * dvar){
dvar->x = 1;
}
int main(int argc, char* argv[])
{
//int num = 25;
//cudaMemcpyToSymbol(dim,&num,sizeof(int),0,cudaMemcpyHostToDevice);
//int *gpu_Num;
hipMalloc(&var,sizeof(A));
test<<<1,1>>>(var);
int p;
hipMemcpy(&p,&(var->x),sizeof(int),hipMemcpyDefault);
printf("Result: %i\n",p);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "stdio.h"
#include <iostream>
#include <hip/hip_runtime.h>
class A {
public:
int x;
};
A * var;
__global__ void test(A * dvar){
dvar->x = 1;
}
int main(int argc, char* argv[])
{
//int num = 25;
//cudaMemcpyToSymbol(dim,&num,sizeof(int),0,cudaMemcpyHostToDevice);
//int *gpu_Num;
hipMalloc(&var,sizeof(A));
test<<<1,1>>>(var);
int p;
hipMemcpy(&p,&(var->x),sizeof(int),hipMemcpyDefault);
printf("Result: %i\n",p);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testP1A
.globl _Z4testP1A
.p2align 8
.type _Z4testP1A,@function
_Z4testP1A:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testP1A
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testP1A, .Lfunc_end0-_Z4testP1A
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testP1A
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z4testP1A.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "stdio.h"
#include <iostream>
#include <hip/hip_runtime.h>
class A {
public:
int x;
};
A * var;
__global__ void test(A * dvar){
dvar->x = 1;
}
int main(int argc, char* argv[])
{
//int num = 25;
//cudaMemcpyToSymbol(dim,&num,sizeof(int),0,cudaMemcpyHostToDevice);
//int *gpu_Num;
hipMalloc(&var,sizeof(A));
test<<<1,1>>>(var);
int p;
hipMemcpy(&p,&(var->x),sizeof(int),hipMemcpyDefault);
printf("Result: %i\n",p);
} | .text
.file "tosymbol_class.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testP1A # -- Begin function _Z19__device_stub__testP1A
.p2align 4, 0x90
.type _Z19__device_stub__testP1A,@function
_Z19__device_stub__testP1A: # @_Z19__device_stub__testP1A
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4testP1A, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__testP1A, .Lfunc_end0-_Z19__device_stub__testP1A
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $var, %edi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq var(%rip), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4testP1A, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq var(%rip), %rsi
movq %rsp, %rdi
movl $4, %edx
movl $4, %ecx
callq hipMemcpy
movl (%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testP1A, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type var,@object # @var
.bss
.globl var
.p2align 3, 0x0
var:
.quad 0
.size var, 8
.type _Z4testP1A,@object # @_Z4testP1A
.section .rodata,"a",@progbits
.globl _Z4testP1A
.p2align 3, 0x0
_Z4testP1A:
.quad _Z19__device_stub__testP1A
.size _Z4testP1A, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result: %i\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testP1A"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testP1A
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym var
.addrsig_sym _Z4testP1A
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testP1A
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testP1A
.globl _Z4testP1A
.p2align 8
.type _Z4testP1A,@function
_Z4testP1A:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testP1A
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testP1A, .Lfunc_end0-_Z4testP1A
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testP1A
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z4testP1A.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004fc26_00000000-6_tosymbol_class.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4testP1AP1A
.type _Z24__device_stub__Z4testP1AP1A, @function
_Z24__device_stub__Z4testP1AP1A:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testP1A(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z4testP1AP1A, .-_Z24__device_stub__Z4testP1AP1A
.globl _Z4testP1A
.type _Z4testP1A, @function
_Z4testP1A:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4testP1AP1A
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4testP1A, .-_Z4testP1A
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result: %i\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4, %esi
leaq var(%rip), %rdi
call cudaMalloc@PLT
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, (%rsp)
movl $1, 4(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 12(%rsp), %rdi
movl $4, %ecx
movl $4, %edx
movq var(%rip), %rsi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq var(%rip), %rdi
call _Z24__device_stub__Z4testP1AP1A
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4testP1A"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testP1A(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl var
.bss
.align 8
.type var, @object
.size var, 8
var:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tosymbol_class.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testP1A # -- Begin function _Z19__device_stub__testP1A
.p2align 4, 0x90
.type _Z19__device_stub__testP1A,@function
_Z19__device_stub__testP1A: # @_Z19__device_stub__testP1A
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4testP1A, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__testP1A, .Lfunc_end0-_Z19__device_stub__testP1A
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $var, %edi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq var(%rip), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4testP1A, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq var(%rip), %rsi
movq %rsp, %rdi
movl $4, %edx
movl $4, %ecx
callq hipMemcpy
movl (%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testP1A, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type var,@object # @var
.bss
.globl var
.p2align 3, 0x0
var:
.quad 0
.size var, 8
.type _Z4testP1A,@object # @_Z4testP1A
.section .rodata,"a",@progbits
.globl _Z4testP1A
.p2align 3, 0x0
_Z4testP1A:
.quad _Z19__device_stub__testP1A
.size _Z4testP1A, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result: %i\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testP1A"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testP1A
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym var
.addrsig_sym _Z4testP1A
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void fillTwoIntegerArraysKernel(
int numberRows,
int numberEntries,
int* firstArray,
int firstConstant,
int* secondArray,
int secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | code for sm_80
Function : _Z26fillTwoIntegerArraysKerneliiPiiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R0, R0, c[0x0][0x160], R5 ; /* 0x0000580000007a24 */
/* 0x001fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R3, c[0x0][0x164], R0 ; /* 0x0000590003007a24 */
/* 0x002fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void fillTwoIntegerArraysKernel(
int numberRows,
int numberEntries,
int* firstArray,
int firstConstant,
int* secondArray,
int secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | .file "tmpxft_0009fc46_00000000-6_FillTwoIntegerArraysKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i
.type _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i, @function
_Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26fillTwoIntegerArraysKerneliiPiiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i, .-_Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i
.globl _Z26fillTwoIntegerArraysKerneliiPiiS_i
.type _Z26fillTwoIntegerArraysKerneliiPiiS_i, @function
_Z26fillTwoIntegerArraysKerneliiPiiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26fillTwoIntegerArraysKerneliiPiiS_i, .-_Z26fillTwoIntegerArraysKerneliiPiiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26fillTwoIntegerArraysKerneliiPiiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26fillTwoIntegerArraysKerneliiPiiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void fillTwoIntegerArraysKernel(
int numberRows,
int numberEntries,
int* firstArray,
int firstConstant,
int* secondArray,
int secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | #include <hip/hip_runtime.h>
__global__ void fillTwoIntegerArraysKernel(
int numberRows,
int numberEntries,
int* firstArray,
int firstConstant,
int* secondArray,
int secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void fillTwoIntegerArraysKernel(
int numberRows,
int numberEntries,
int* firstArray,
int firstConstant,
int* secondArray,
int secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26fillTwoIntegerArraysKerneliiPiiS_i
.globl _Z26fillTwoIntegerArraysKerneliiPiiS_i
.p2align 8
.type _Z26fillTwoIntegerArraysKerneliiPiiS_i,@function
_Z26fillTwoIntegerArraysKerneliiPiiS_i:
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
v_add3_u32 v0, s14, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26fillTwoIntegerArraysKerneliiPiiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26fillTwoIntegerArraysKerneliiPiiS_i, .Lfunc_end0-_Z26fillTwoIntegerArraysKerneliiPiiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26fillTwoIntegerArraysKerneliiPiiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26fillTwoIntegerArraysKerneliiPiiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void fillTwoIntegerArraysKernel(
int numberRows,
int numberEntries,
int* firstArray,
int firstConstant,
int* secondArray,
int secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | .text
.file "FillTwoIntegerArraysKernel.hip"
.globl _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i # -- Begin function _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.p2align 4, 0x90
.type _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i,@function
_Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i: # @_Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26fillTwoIntegerArraysKerneliiPiiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i, .Lfunc_end0-_Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26fillTwoIntegerArraysKerneliiPiiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26fillTwoIntegerArraysKerneliiPiiS_i,@object # @_Z26fillTwoIntegerArraysKerneliiPiiS_i
.section .rodata,"a",@progbits
.globl _Z26fillTwoIntegerArraysKerneliiPiiS_i
.p2align 3, 0x0
_Z26fillTwoIntegerArraysKerneliiPiiS_i:
.quad _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.size _Z26fillTwoIntegerArraysKerneliiPiiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26fillTwoIntegerArraysKerneliiPiiS_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26fillTwoIntegerArraysKerneliiPiiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26fillTwoIntegerArraysKerneliiPiiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R0, R0, c[0x0][0x160], R5 ; /* 0x0000580000007a24 */
/* 0x001fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R3, c[0x0][0x164], R0 ; /* 0x0000590003007a24 */
/* 0x002fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26fillTwoIntegerArraysKerneliiPiiS_i
.globl _Z26fillTwoIntegerArraysKerneliiPiiS_i
.p2align 8
.type _Z26fillTwoIntegerArraysKerneliiPiiS_i,@function
_Z26fillTwoIntegerArraysKerneliiPiiS_i:
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
v_add3_u32 v0, s14, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26fillTwoIntegerArraysKerneliiPiiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26fillTwoIntegerArraysKerneliiPiiS_i, .Lfunc_end0-_Z26fillTwoIntegerArraysKerneliiPiiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26fillTwoIntegerArraysKerneliiPiiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26fillTwoIntegerArraysKerneliiPiiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009fc46_00000000-6_FillTwoIntegerArraysKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i
.type _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i, @function
_Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26fillTwoIntegerArraysKerneliiPiiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i, .-_Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i
.globl _Z26fillTwoIntegerArraysKerneliiPiiS_i
.type _Z26fillTwoIntegerArraysKerneliiPiiS_i, @function
_Z26fillTwoIntegerArraysKerneliiPiiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26fillTwoIntegerArraysKerneliiPiiS_iiiPiiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26fillTwoIntegerArraysKerneliiPiiS_i, .-_Z26fillTwoIntegerArraysKerneliiPiiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26fillTwoIntegerArraysKerneliiPiiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26fillTwoIntegerArraysKerneliiPiiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FillTwoIntegerArraysKernel.hip"
.globl _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i # -- Begin function _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.p2align 4, 0x90
.type _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i,@function
_Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i: # @_Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26fillTwoIntegerArraysKerneliiPiiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i, .Lfunc_end0-_Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26fillTwoIntegerArraysKerneliiPiiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26fillTwoIntegerArraysKerneliiPiiS_i,@object # @_Z26fillTwoIntegerArraysKerneliiPiiS_i
.section .rodata,"a",@progbits
.globl _Z26fillTwoIntegerArraysKerneliiPiiS_i
.p2align 3, 0x0
_Z26fillTwoIntegerArraysKerneliiPiiS_i:
.quad _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.size _Z26fillTwoIntegerArraysKerneliiPiiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26fillTwoIntegerArraysKerneliiPiiS_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__fillTwoIntegerArraysKerneliiPiiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26fillTwoIntegerArraysKerneliiPiiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: XIAO Tong (email: xiaotong@mail.neu.edu.cn) 2018-04-24
*/
#include "CopyValues.h"
#include "CopyValues.cuh"
#include "../../XUtility.h"
#include "../../XDevice.h"
namespace nts { // namespace nts(NiuTrans.Tensor)
#ifdef USE_CUDA
/*
copy a range of elements from a source vector to a target vector
>> s - source matrix
>> t - target matrix
<< return - succeed or not
*/
void _CudaCopyValues(const XTensor * s, XTensor * t)
{
CheckNTErrors(s != NULL && t != NULL, "The input tensor and output tensor must be nonempty!");
CheckNTErrors(s->dataType == t->dataType, "Unmatched data type!");
CheckNTErrors(s->unitSize == t->unitSize, "Incompatible data types in value copy.");
CheckNTErrors(s->unitNum == t->unitNum, "The data items are be the same.");
CheckNTErrors(s->denseRatio <= t->denseRatio, "Incompatible vectors in value copy.");
/* dense -> dense */
if (!s->isSparse && !t->isSparse) {
XMemCopy(t->data, t->devID, s->data, s->devID, s->unitSize * s->unitNum);
}
/* dense -> sparse */
else if (!s->isSparse && t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
ShowNTErrors("TODO!");
}
/* sparse -> dense */
else if (s->isSparse && !t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
ShowNTErrors("TODO!");
}
/* sparse -> sparse */
else if (s->isSparse && t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
int num = s->unitNumNonZero;
int size = sizeof(int) + num * (s->unitSize + sizeof(int));
XMemCopy(t->data, t->devID, s->data, s->devID, size);
t->unitNumNonZero = num;
}
else {
ShowNTErrors("TODO!");
}
}
#endif // USE_CUDA
} // namespace nts(NiuTrans.Tensor) | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: XIAO Tong (email: xiaotong@mail.neu.edu.cn) 2018-04-24
*/
#include "CopyValues.h"
#include "CopyValues.cuh"
#include "../../XUtility.h"
#include "../../XDevice.h"
namespace nts { // namespace nts(NiuTrans.Tensor)
#ifdef USE_CUDA
/*
copy a range of elements from a source vector to a target vector
>> s - source matrix
>> t - target matrix
<< return - succeed or not
*/
void _CudaCopyValues(const XTensor * s, XTensor * t)
{
CheckNTErrors(s != NULL && t != NULL, "The input tensor and output tensor must be nonempty!");
CheckNTErrors(s->dataType == t->dataType, "Unmatched data type!");
CheckNTErrors(s->unitSize == t->unitSize, "Incompatible data types in value copy.");
CheckNTErrors(s->unitNum == t->unitNum, "The data items are be the same.");
CheckNTErrors(s->denseRatio <= t->denseRatio, "Incompatible vectors in value copy.");
/* dense -> dense */
if (!s->isSparse && !t->isSparse) {
XMemCopy(t->data, t->devID, s->data, s->devID, s->unitSize * s->unitNum);
}
/* dense -> sparse */
else if (!s->isSparse && t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
ShowNTErrors("TODO!");
}
/* sparse -> dense */
else if (s->isSparse && !t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
ShowNTErrors("TODO!");
}
/* sparse -> sparse */
else if (s->isSparse && t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
int num = s->unitNumNonZero;
int size = sizeof(int) + num * (s->unitSize + sizeof(int));
XMemCopy(t->data, t->devID, s->data, s->devID, size);
t->unitNumNonZero = num;
}
else {
ShowNTErrors("TODO!");
}
}
#endif // USE_CUDA
} // namespace nts(NiuTrans.Tensor) | .file "tmpxft_000a8ec5_00000000-6_CopyValues.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3094:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3117:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3117:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: XIAO Tong (email: xiaotong@mail.neu.edu.cn) 2018-04-24
*/
#include "CopyValues.h"
#include "CopyValues.cuh"
#include "../../XUtility.h"
#include "../../XDevice.h"
namespace nts { // namespace nts(NiuTrans.Tensor)
#ifdef USE_CUDA
/*
copy a range of elements from a source vector to a target vector
>> s - source matrix
>> t - target matrix
<< return - succeed or not
*/
void _CudaCopyValues(const XTensor * s, XTensor * t)
{
CheckNTErrors(s != NULL && t != NULL, "The input tensor and output tensor must be nonempty!");
CheckNTErrors(s->dataType == t->dataType, "Unmatched data type!");
CheckNTErrors(s->unitSize == t->unitSize, "Incompatible data types in value copy.");
CheckNTErrors(s->unitNum == t->unitNum, "The data items are be the same.");
CheckNTErrors(s->denseRatio <= t->denseRatio, "Incompatible vectors in value copy.");
/* dense -> dense */
if (!s->isSparse && !t->isSparse) {
XMemCopy(t->data, t->devID, s->data, s->devID, s->unitSize * s->unitNum);
}
/* dense -> sparse */
else if (!s->isSparse && t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
ShowNTErrors("TODO!");
}
/* sparse -> dense */
else if (s->isSparse && !t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
ShowNTErrors("TODO!");
}
/* sparse -> sparse */
else if (s->isSparse && t->isSparse &&
s->dataType == DEFAULT_DTYPE &&
t->dataType == DEFAULT_DTYPE)
{
int num = s->unitNumNonZero;
int size = sizeof(int) + num * (s->unitSize + sizeof(int));
XMemCopy(t->data, t->devID, s->data, s->devID, size);
t->unitNumNonZero = num;
}
else {
ShowNTErrors("TODO!");
}
}
#endif // USE_CUDA
} // namespace nts(NiuTrans.Tensor) | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: XIAO Tong (email: xiaotong@mail.neu.edu.cn) 2018-04-24
*/
#ifndef __COPYVALUES_CUH__
#define __COPYVALUES_CUH__
#include "../../XTensor.h"
namespace nts { // namespace nts(NiuTrans.Tensor)
#ifdef USE_CUDA
/* copy all elements from a source matrix to a target matrix */
void _CudaCopyValues(const XTensor * s, XTensor * t);
#endif // USE_CUDA
} // namespace nts(NiuTrans.Tensor)
#endif // __COPYVALUES_CUH__ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: XIAO Tong (email: xiaotong@mail.neu.edu.cn) 2018-04-24
*/
#ifndef __COPYVALUES_CUH__
#define __COPYVALUES_CUH__
#include "../../XTensor.h"
namespace nts { // namespace nts(NiuTrans.Tensor)
#ifdef USE_CUDA
/* copy all elements from a source matrix to a target matrix */
void _CudaCopyValues(const XTensor * s, XTensor * t);
#endif // USE_CUDA
} // namespace nts(NiuTrans.Tensor)
#endif // __COPYVALUES_CUH__ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* $Created by: XIAO Tong (email: xiaotong@mail.neu.edu.cn) 2018-04-24
*/
#ifndef __COPYVALUES_CUH__
#define __COPYVALUES_CUH__
#include "../../XTensor.h"
namespace nts { // namespace nts(NiuTrans.Tensor)
#ifdef USE_CUDA
/* copy all elements from a source matrix to a target matrix */
void _CudaCopyValues(const XTensor * s, XTensor * t);
#endif // USE_CUDA
} // namespace nts(NiuTrans.Tensor)
#endif // __COPYVALUES_CUH__ | .text
.file "CopyValues.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a8ec5_00000000-6_CopyValues.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3094:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3117:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3117:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CopyValues.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void prefixSum_multiBlocks(float* in, int in_length, float* out, float* temp ){
extern __shared__ float DSM[];
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//load in shared memory
if(idx < in_length){
DSM[threadIdx.x] = in[idx];
//partial sums phase
for(int stride = 1; stride <= blockDim.x; stride *= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux < blockDim.x)
DSM[index_aux] += DSM[index_aux - stride];
}
//reduction phase
for(int stride=blockDim.x/4 ; stride > 0 ; stride /= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux + stride < blockDim.x)
DSM[index_aux + stride] += DSM[index_aux];
}
__syncthreads();
//save intermediary values on temp to post combine for multi blocks
if(threadIdx.x == 0)
temp[blockIdx.x] = DSM[blockDim.x - 1];
out[idx] = DSM[threadIdx.x];
}
} | code for sm_80
Function : _Z21prefixSum_multiBlocksPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R9 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0209 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f25270 */
/*00b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*00c0*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041f40000004800 */
/*00d0*/ @!P1 BRA 0x1b0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*00e0*/ LEA R3, R9, 0x2, 0x1 ; /* 0x0000000209037811 */
/* 0x000fe200078e08ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x001fc800078e00ff */
/*0100*/ IMAD R7, R3, R4, -0x1 ; /* 0xffffffff03077424 */
/* 0x000fe200078e0204 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f26070 */
/*0130*/ @!P1 IADD3 R5, R7, -R4, RZ ; /* 0x8000000407059210 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fe200078e00ff */
/*0150*/ @!P1 LDS R6, [R7.X4] ; /* 0x0000000007069984 */
/* 0x000fe80000004800 */
/*0160*/ @!P1 LDS R5, [R5.X4] ; /* 0x0000000005059984 */
/* 0x000e240000004800 */
/*0170*/ @!P1 FADD R6, R6, R5 ; /* 0x0000000506069221 */
/* 0x001fca0000000000 */
/*0180*/ @!P1 STS [R7.X4], R6 ; /* 0x0000000607009388 */
/* 0x0001e20000004800 */
/*0190*/ ISETP.GT.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f24070 */
/*01a0*/ @!P1 BRA 0x100 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*01b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*01c0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff078624 */
/* 0x000fe200078e00ff */
/*01d0*/ USHF.R.U32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fc80008011604 */
/*01e0*/ @!P0 LEA R7, R7, 0xfffffffc, 0x2 ; /* 0xfffffffc07078811 */
/* 0x000fe400078e10ff */
/*01f0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0200*/ @!P1 BRA 0x300 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0210*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe40008000f00 */
/*0220*/ LEA R8, R9, 0x2, 0x1 ; /* 0x0000000209087811 */
/* 0x000fca00078e08ff */
/*0230*/ IMAD R6, R8, R3, -0x1 ; /* 0xffffffff08067424 */
/* 0x000fe200078e0203 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ IMAD.IADD R4, R6, 0x1, R3 ; /* 0x0000000106047824 */
/* 0x001fca00078e0203 */
/*0260*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0270*/ @!P1 IMAD.SHL.U32 R4, R6, 0x4, RZ ; /* 0x0000000406049824 */
/* 0x000fe400078e00ff */
/*0280*/ @!P1 LDS R6, [R6.X4] ; /* 0x0000000006069984 */
/* 0x000fe60000004800 */
/*0290*/ @!P1 LEA R4, R3, R4, 0x2 ; /* 0x0000000403049211 */
/* 0x000fe400078e10ff */
/*02a0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*02b0*/ @!P1 LDS R5, [R4] ; /* 0x0000000004059984 */
/* 0x000e240000000800 */
/*02c0*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*02d0*/ @!P1 STS [R4], R5 ; /* 0x0000000504009388 */
/* 0x0001e20000000800 */
/*02e0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*02f0*/ @P1 BRA 0x230 ; /* 0xffffff3000001947 */
/* 0x001fea000383ffff */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0310*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe20000011402 */
/*0320*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b8424 */
/* 0x000fe200078e00ff */
/*0330*/ LEA R4, P1, R2, c[0x0][0x170], 0x2 ; /* 0x00005c0002047a11 */
/* 0x001fc800078210ff */
/*0340*/ LEA.HI.X R5, R2, c[0x0][0x174], R3, 0x2, P1 ; /* 0x00005d0002057a11 */
/* 0x000fe200008f1403 */
/*0350*/ @!P0 IMAD.WIDE.U32 R2, R0, R11, c[0x0][0x178] ; /* 0x00005e0000028625 */
/* 0x000fe200078e000b */
/*0360*/ @!P0 LDS R7, [R7] ; /* 0x0000000007078984 */
/* 0x000e280000000800 */
/*0370*/ LDS R9, [R9.X4] ; /* 0x0000000009097984 */
/* 0x000e680000004800 */
/*0380*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x001fe8000c101906 */
/*0390*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void prefixSum_multiBlocks(float* in, int in_length, float* out, float* temp ){
extern __shared__ float DSM[];
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//load in shared memory
if(idx < in_length){
DSM[threadIdx.x] = in[idx];
//partial sums phase
for(int stride = 1; stride <= blockDim.x; stride *= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux < blockDim.x)
DSM[index_aux] += DSM[index_aux - stride];
}
//reduction phase
for(int stride=blockDim.x/4 ; stride > 0 ; stride /= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux + stride < blockDim.x)
DSM[index_aux + stride] += DSM[index_aux];
}
__syncthreads();
//save intermediary values on temp to post combine for multi blocks
if(threadIdx.x == 0)
temp[blockIdx.x] = DSM[blockDim.x - 1];
out[idx] = DSM[threadIdx.x];
}
} | .file "tmpxft_0007c4a5_00000000-6_prefixSum_multiBlocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_
.type _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_, @function
_Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21prefixSum_multiBlocksPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_, .-_Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_
.globl _Z21prefixSum_multiBlocksPfiS_S_
.type _Z21prefixSum_multiBlocksPfiS_S_, @function
_Z21prefixSum_multiBlocksPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21prefixSum_multiBlocksPfiS_S_, .-_Z21prefixSum_multiBlocksPfiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21prefixSum_multiBlocksPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21prefixSum_multiBlocksPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void prefixSum_multiBlocks(float* in, int in_length, float* out, float* temp ){
extern __shared__ float DSM[];
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//load in shared memory
if(idx < in_length){
DSM[threadIdx.x] = in[idx];
//partial sums phase
for(int stride = 1; stride <= blockDim.x; stride *= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux < blockDim.x)
DSM[index_aux] += DSM[index_aux - stride];
}
//reduction phase
for(int stride=blockDim.x/4 ; stride > 0 ; stride /= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux + stride < blockDim.x)
DSM[index_aux + stride] += DSM[index_aux];
}
__syncthreads();
//save intermediary values on temp to post combine for multi blocks
if(threadIdx.x == 0)
temp[blockIdx.x] = DSM[blockDim.x - 1];
out[idx] = DSM[threadIdx.x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prefixSum_multiBlocks(float* in, int in_length, float* out, float* temp ){
extern __shared__ float DSM[];
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//load in shared memory
if(idx < in_length){
DSM[threadIdx.x] = in[idx];
//partial sums phase
for(int stride = 1; stride <= blockDim.x; stride *= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux < blockDim.x)
DSM[index_aux] += DSM[index_aux - stride];
}
//reduction phase
for(int stride=blockDim.x/4 ; stride > 0 ; stride /= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux + stride < blockDim.x)
DSM[index_aux + stride] += DSM[index_aux];
}
__syncthreads();
//save intermediary values on temp to post combine for multi blocks
if(threadIdx.x == 0)
temp[blockIdx.x] = DSM[blockDim.x - 1];
out[idx] = DSM[threadIdx.x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prefixSum_multiBlocks(float* in, int in_length, float* out, float* temp ){
extern __shared__ float DSM[];
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//load in shared memory
if(idx < in_length){
DSM[threadIdx.x] = in[idx];
//partial sums phase
for(int stride = 1; stride <= blockDim.x; stride *= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux < blockDim.x)
DSM[index_aux] += DSM[index_aux - stride];
}
//reduction phase
for(int stride=blockDim.x/4 ; stride > 0 ; stride /= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux + stride < blockDim.x)
DSM[index_aux + stride] += DSM[index_aux];
}
__syncthreads();
//save intermediary values on temp to post combine for multi blocks
if(threadIdx.x == 0)
temp[blockIdx.x] = DSM[blockDim.x - 1];
out[idx] = DSM[threadIdx.x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21prefixSum_multiBlocksPfiS_S_
.globl _Z21prefixSum_multiBlocksPfiS_S_
.p2align 8
.type _Z21prefixSum_multiBlocksPfiS_S_,@function
_Z21prefixSum_multiBlocksPfiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_eq_u16_e64 s3, s3, 0
v_lshl_add_u32 v5, v0, 2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_and_b32 vcc_lo, exec_lo, s3
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3
s_cbranch_vccnz .LBB0_6
v_lshl_add_u32 v6, v0, 1, 2
s_mov_b32 s3, 1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s3, s4
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s3, v6, -1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v3
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v4, s3, v3
v_lshl_add_u32 v3, v3, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v4, v4
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v7
ds_store_b32 v3, v4
s_branch .LBB0_3
.LBB0_6:
s_cmp_lt_u32 s4, 4
s_cbranch_scc1 .LBB0_11
v_lshl_add_u32 v3, v0, 1, 2
s_lshr_b32 s3, s4, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s5, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s5
s_cbranch_scc1 .LBB0_11
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v6, s3, v3, -1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v4, s3, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s4, v4
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v6, v6, 2, 0
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v6, v6
ds_load_b32 v7, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v4, v6
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_13
s_lshl_b32 s4, s4, 2
s_load_b64 s[6:7], s[0:1], 0x18
s_add_i32 s4, s4, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_add_i32 s4, s4, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
global_store_b32 v3, v0, s[2:3]
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v3, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21prefixSum_multiBlocksPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21prefixSum_multiBlocksPfiS_S_, .Lfunc_end0-_Z21prefixSum_multiBlocksPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21prefixSum_multiBlocksPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21prefixSum_multiBlocksPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void prefixSum_multiBlocks(float* in, int in_length, float* out, float* temp ){
extern __shared__ float DSM[];
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//load in shared memory
if(idx < in_length){
DSM[threadIdx.x] = in[idx];
//partial sums phase
for(int stride = 1; stride <= blockDim.x; stride *= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux < blockDim.x)
DSM[index_aux] += DSM[index_aux - stride];
}
//reduction phase
for(int stride=blockDim.x/4 ; stride > 0 ; stride /= 2){
__syncthreads();
int index_aux = (threadIdx.x + 1) * 2 * stride - 1;
if(index_aux + stride < blockDim.x)
DSM[index_aux + stride] += DSM[index_aux];
}
__syncthreads();
//save intermediary values on temp to post combine for multi blocks
if(threadIdx.x == 0)
temp[blockIdx.x] = DSM[blockDim.x - 1];
out[idx] = DSM[threadIdx.x];
}
} | .text
.file "prefixSum_multiBlocks.hip"
.globl _Z36__device_stub__prefixSum_multiBlocksPfiS_S_ # -- Begin function _Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.p2align 4, 0x90
.type _Z36__device_stub__prefixSum_multiBlocksPfiS_S_,@function
_Z36__device_stub__prefixSum_multiBlocksPfiS_S_: # @_Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21prefixSum_multiBlocksPfiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__prefixSum_multiBlocksPfiS_S_, .Lfunc_end0-_Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21prefixSum_multiBlocksPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21prefixSum_multiBlocksPfiS_S_,@object # @_Z21prefixSum_multiBlocksPfiS_S_
.section .rodata,"a",@progbits
.globl _Z21prefixSum_multiBlocksPfiS_S_
.p2align 3, 0x0
_Z21prefixSum_multiBlocksPfiS_S_:
.quad _Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.size _Z21prefixSum_multiBlocksPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21prefixSum_multiBlocksPfiS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21prefixSum_multiBlocksPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21prefixSum_multiBlocksPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R9 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0209 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f25270 */
/*00b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*00c0*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041f40000004800 */
/*00d0*/ @!P1 BRA 0x1b0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*00e0*/ LEA R3, R9, 0x2, 0x1 ; /* 0x0000000209037811 */
/* 0x000fe200078e08ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x001fc800078e00ff */
/*0100*/ IMAD R7, R3, R4, -0x1 ; /* 0xffffffff03077424 */
/* 0x000fe200078e0204 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f26070 */
/*0130*/ @!P1 IADD3 R5, R7, -R4, RZ ; /* 0x8000000407059210 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fe200078e00ff */
/*0150*/ @!P1 LDS R6, [R7.X4] ; /* 0x0000000007069984 */
/* 0x000fe80000004800 */
/*0160*/ @!P1 LDS R5, [R5.X4] ; /* 0x0000000005059984 */
/* 0x000e240000004800 */
/*0170*/ @!P1 FADD R6, R6, R5 ; /* 0x0000000506069221 */
/* 0x001fca0000000000 */
/*0180*/ @!P1 STS [R7.X4], R6 ; /* 0x0000000607009388 */
/* 0x0001e20000004800 */
/*0190*/ ISETP.GT.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f24070 */
/*01a0*/ @!P1 BRA 0x100 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*01b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*01c0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff078624 */
/* 0x000fe200078e00ff */
/*01d0*/ USHF.R.U32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fc80008011604 */
/*01e0*/ @!P0 LEA R7, R7, 0xfffffffc, 0x2 ; /* 0xfffffffc07078811 */
/* 0x000fe400078e10ff */
/*01f0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0200*/ @!P1 BRA 0x300 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0210*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe40008000f00 */
/*0220*/ LEA R8, R9, 0x2, 0x1 ; /* 0x0000000209087811 */
/* 0x000fca00078e08ff */
/*0230*/ IMAD R6, R8, R3, -0x1 ; /* 0xffffffff08067424 */
/* 0x000fe200078e0203 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ IMAD.IADD R4, R6, 0x1, R3 ; /* 0x0000000106047824 */
/* 0x001fca00078e0203 */
/*0260*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0270*/ @!P1 IMAD.SHL.U32 R4, R6, 0x4, RZ ; /* 0x0000000406049824 */
/* 0x000fe400078e00ff */
/*0280*/ @!P1 LDS R6, [R6.X4] ; /* 0x0000000006069984 */
/* 0x000fe60000004800 */
/*0290*/ @!P1 LEA R4, R3, R4, 0x2 ; /* 0x0000000403049211 */
/* 0x000fe400078e10ff */
/*02a0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*02b0*/ @!P1 LDS R5, [R4] ; /* 0x0000000004059984 */
/* 0x000e240000000800 */
/*02c0*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*02d0*/ @!P1 STS [R4], R5 ; /* 0x0000000504009388 */
/* 0x0001e20000000800 */
/*02e0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*02f0*/ @P1 BRA 0x230 ; /* 0xffffff3000001947 */
/* 0x001fea000383ffff */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0310*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe20000011402 */
/*0320*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b8424 */
/* 0x000fe200078e00ff */
/*0330*/ LEA R4, P1, R2, c[0x0][0x170], 0x2 ; /* 0x00005c0002047a11 */
/* 0x001fc800078210ff */
/*0340*/ LEA.HI.X R5, R2, c[0x0][0x174], R3, 0x2, P1 ; /* 0x00005d0002057a11 */
/* 0x000fe200008f1403 */
/*0350*/ @!P0 IMAD.WIDE.U32 R2, R0, R11, c[0x0][0x178] ; /* 0x00005e0000028625 */
/* 0x000fe200078e000b */
/*0360*/ @!P0 LDS R7, [R7] ; /* 0x0000000007078984 */
/* 0x000e280000000800 */
/*0370*/ LDS R9, [R9.X4] ; /* 0x0000000009097984 */
/* 0x000e680000004800 */
/*0380*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x001fe8000c101906 */
/*0390*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21prefixSum_multiBlocksPfiS_S_
.globl _Z21prefixSum_multiBlocksPfiS_S_
.p2align 8
.type _Z21prefixSum_multiBlocksPfiS_S_,@function
_Z21prefixSum_multiBlocksPfiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_eq_u16_e64 s3, s3, 0
v_lshl_add_u32 v5, v0, 2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_and_b32 vcc_lo, exec_lo, s3
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3
s_cbranch_vccnz .LBB0_6
v_lshl_add_u32 v6, v0, 1, 2
s_mov_b32 s3, 1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s3, s4
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s3, v6, -1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v3
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v4, s3, v3
v_lshl_add_u32 v3, v3, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v4, v4
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v7
ds_store_b32 v3, v4
s_branch .LBB0_3
.LBB0_6:
s_cmp_lt_u32 s4, 4
s_cbranch_scc1 .LBB0_11
v_lshl_add_u32 v3, v0, 1, 2
s_lshr_b32 s3, s4, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s5, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s5
s_cbranch_scc1 .LBB0_11
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v6, s3, v3, -1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v4, s3, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s4, v4
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v6, v6, 2, 0
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v6, v6
ds_load_b32 v7, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v4, v6
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_13
s_lshl_b32 s4, s4, 2
s_load_b64 s[6:7], s[0:1], 0x18
s_add_i32 s4, s4, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_add_i32 s4, s4, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
global_store_b32 v3, v0, s[2:3]
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v3, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21prefixSum_multiBlocksPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21prefixSum_multiBlocksPfiS_S_, .Lfunc_end0-_Z21prefixSum_multiBlocksPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21prefixSum_multiBlocksPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21prefixSum_multiBlocksPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007c4a5_00000000-6_prefixSum_multiBlocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_
.type _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_, @function
_Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21prefixSum_multiBlocksPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_, .-_Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_
.globl _Z21prefixSum_multiBlocksPfiS_S_
.type _Z21prefixSum_multiBlocksPfiS_S_, @function
_Z21prefixSum_multiBlocksPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21prefixSum_multiBlocksPfiS_S_PfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21prefixSum_multiBlocksPfiS_S_, .-_Z21prefixSum_multiBlocksPfiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21prefixSum_multiBlocksPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21prefixSum_multiBlocksPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prefixSum_multiBlocks.hip"
.globl _Z36__device_stub__prefixSum_multiBlocksPfiS_S_ # -- Begin function _Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.p2align 4, 0x90
.type _Z36__device_stub__prefixSum_multiBlocksPfiS_S_,@function
_Z36__device_stub__prefixSum_multiBlocksPfiS_S_: # @_Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21prefixSum_multiBlocksPfiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__prefixSum_multiBlocksPfiS_S_, .Lfunc_end0-_Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21prefixSum_multiBlocksPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21prefixSum_multiBlocksPfiS_S_,@object # @_Z21prefixSum_multiBlocksPfiS_S_
.section .rodata,"a",@progbits
.globl _Z21prefixSum_multiBlocksPfiS_S_
.p2align 3, 0x0
_Z21prefixSum_multiBlocksPfiS_S_:
.quad _Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.size _Z21prefixSum_multiBlocksPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21prefixSum_multiBlocksPfiS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__prefixSum_multiBlocksPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21prefixSum_multiBlocksPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <string>
#include <sstream>
#include <fstream>
#include <algorithm>
#include <chrono>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <cuda.h>
#include <unistd.h>
//#define _DEBUG_
//#define _TIME_MEASURE_
#ifdef _DEBUG_
#include <string>
#include <sstream>
int __print_step = 0;
void __pt_log(const char *h_, const char *f_, ...){
std::stringstream ss;
ss << h_ << f_ << '\n';
std::string format = ss.str();
va_list va;
va_start(va, f_);
vprintf(format.c_str(), va);
va_end(va);
__print_step++;
}
#define VA_ARGS(...) , ##__VA_ARGS__
#define LOG(f_, ...) __pt_log(\
"[LOG] Step %3d: ", (f_), \
__print_step VA_ARGS(__VA_ARGS__))
#else
#define LOG(f_, ...)
#endif
#define INF 1000000000
#define CEIL(a, b) (( (a) - 1 ) / (b) + 1 )
int **Dist;
int *data;
int block_size;
int vert, edge;
int vert2;
inline void init(){
vert2 = vert*vert;
Dist = new int*[vert];
data = new int[vert2];
std::fill(data, data + vert2, INF);
for(int i=0;i<vert;++i){
Dist[i] = data + i*vert;
Dist[i][i] = 0;
}
if(vert < block_size){
block_size = vert;
}
}
inline void finalize(){
delete[] Dist;
delete[] data;
}
void dump_from_file_and_init(const char *file){
std::ifstream fin(file);
std::stringstream ss;
ss << fin.rdbuf();
ss >> vert >> edge;
LOG("vert: %d, edge: %d", vert, edge);
init();
int i, j, w;
while(--edge >=0){
ss >> i >> j >> w;
Dist[i][j] = w;
}
fin.close();
}
void dump_to_file(const char *file){
std::ofstream fout(file);
fout.write((char*)data, sizeof(int)*vert2);
fout.close();
}
__global__ void init_gpu(int reps){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx >= reps) return;
}
__global__ void phase_one(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int c = block_size * round + ty;
const int r = block_size * round + tx;
const int cell = c*width+r;
const int s_cell = ty*block_size+tx;
if(c >= vert || r >= vert){
s[s_cell] = INF;
}else{
s[s_cell] = dist[cell];
}
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
// min(dist[ty][tx], dist[ty][i] + dist[i][tx])
n = s[ty*block_size+k] + s[k*block_size+tx];
if(n < s[s_cell]){
s[s_cell] = n;
}
__syncthreads();
}
dist[cell] = s[s_cell];
}
__global__ void phase_two(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s2[];
int* const s_m = s2; //main(block)
int* const s_c = s2 + block_size*block_size; //center(pivot)
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
int mc, mr; //main
int cc, cr; //center(pivot)
if(bx >= round)++bx; //shift
if(by == 0){ //horizontal
mc = block_size * round + ty;
mr = block_size * bx + tx;
cc = mc;
cr = block_size * round + tx;
}else{ //vertical
mc = block_size * bx + ty;
mr = block_size * round + tx;
cc = block_size * round + ty;
cr = mr;
}
int m_cell = mc * width + mr;
int c_cell = cc * width + cr;
int s_cell = ty * block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(cc >= vert || cr >= vert) s_c[s_cell] = INF;
else s_c[s_cell] = dist[c_cell];
__syncthreads();
int n, k;
if(by == 0){
for(k=0;k<block_size;++k){
n = s_c[ty*block_size+k] + s_m[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}else{
for(k=0;k<block_size;++k){
n = s_m[ty*block_size+k] + s_c[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}
dist[m_cell] = s_m[s_cell];
}
__global__ void phase_three(int32_t* const dist, int block_size, int round, int width, int vert){
int bs2 = block_size*block_size;
extern __shared__ int s3[];
int* const s_m = s3;
int* const s_l = s3 + bs2;
int* const s_r = s_l + bs2;
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= round)++bx; //shift x
if(by >= round)++by; //shift y
const int mc = block_size * by + ty;
const int mr = block_size * bx + tx;
const int lc = mc;
const int lr = block_size * round + tx;
const int rc = block_size * round + ty;
const int rr = mr;
const int m_cell = mc*width + mr;
const int l_cell = lc*width + lr;
const int r_cell = rc*width + rr;
const int s_cell = ty*block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(lc >= vert || lr >= vert) s_l[s_cell] = INF;
else s_l[s_cell] = dist[l_cell];
if(rc >= vert || rr >= vert) s_r[s_cell] = INF;
else s_r[s_cell] = dist[r_cell];
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
n = s_l[ty*block_size+k] + s_r[k*block_size+tx];
if(n<s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
dist[m_cell] = s_m[s_cell];
}
extern __shared__ int S[];
void block_FW(){
#ifdef _TIME_MEASURE_
auto start = std::chrono::high_resolution_clock::now();
#endif
cudaStream_t init_stream;
cudaStreamCreate(&init_stream);
int Round = CEIL(vert, block_size);
int padded_size = Round * block_size;
size_t vert_w_bytes = vert * sizeof(int);
size_t padded_w_bytes = padded_size * sizeof(int);
int32_t *device_ptr;
//size_t pitch;
dim3 p2b(Round-1, 2, 1); //phase 2 block
dim3 p3b(Round-1, Round-1, 1); //phase 3 block
dim3 dimt(block_size, block_size, 1); //thread
//cudaMallocPitch(&device_ptr, &pitch, vert_byte, vert_byte, vert);
cudaMalloc(&device_ptr, padded_w_bytes * padded_size);
//size_t pitch_int = pitch / sizeof(int);
//LOG("pitch => %zu bytes (%zu words)", pitch, pitch_int);
LOG("the number of blocks: %d", Round);
init_gpu<<< 1, dimt >>>(32);
//dst_ptr, dst_pitch, src, src_pitch, w, h, kind
cudaMemcpy2DAsync(device_ptr, padded_w_bytes, data, vert_w_bytes,
vert_w_bytes, vert, cudaMemcpyHostToDevice, init_stream);
size_t bs2b3 = block_size * block_size * sizeof(int) * 3;
cudaDeviceSynchronize();
for(int r=0; r < Round; ++r){
LOG("Round %d/%d", r+1, Round);
phase_one<<< 1 , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_two<<< p2b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_three<<< p3b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
}
cudaMemcpy2D(data, vert_w_bytes, device_ptr, padded_w_bytes,
vert_w_bytes, vert, cudaMemcpyDeviceToHost);
cudaFree(device_ptr);
cudaStreamDestroy(init_stream);
#ifdef _TIME_MEASURE_
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
double elapsed_time = diff.count() * 1000;
printf("Total time: %f ms (%f GFLOPS)\n", elapsed_time, 2*vert*vert*vert / (elapsed_time * 1e6));
#endif
}
int main(int argc, char **argv){
dump_from_file_and_init(argv[1]);
block_size = std::atoi(argv[3]);
block_FW();
dump_to_file(argv[2]);
finalize();
return 0;
} | .file "tmpxft_0007b91b_00000000-6_HW4_cuda_002_wake.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4231:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4231:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8init_gpuii
.type _Z26__device_stub__Z8init_gpuii, @function
_Z26__device_stub__Z8init_gpuii:
.LFB4253:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8init_gpui(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4253:
.size _Z26__device_stub__Z8init_gpuii, .-_Z26__device_stub__Z8init_gpuii
.globl _Z8init_gpui
.type _Z8init_gpui, @function
_Z8init_gpui:
.LFB4254:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8init_gpuii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4254:
.size _Z8init_gpui, .-_Z8init_gpui
.globl _Z32__device_stub__Z9phase_onePiiiiiPiiiii
.type _Z32__device_stub__Z9phase_onePiiiiiPiiiii, @function
_Z32__device_stub__Z9phase_onePiiiiiPiiiii:
.LFB4255:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9phase_onePiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4255:
.size _Z32__device_stub__Z9phase_onePiiiiiPiiiii, .-_Z32__device_stub__Z9phase_onePiiiiiPiiiii
.globl _Z9phase_onePiiiii
.type _Z9phase_onePiiiii, @function
_Z9phase_onePiiiii:
.LFB4256:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9phase_onePiiiiiPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4256:
.size _Z9phase_onePiiiii, .-_Z9phase_onePiiiii
.globl _Z32__device_stub__Z9phase_twoPiiiiiPiiiii
.type _Z32__device_stub__Z9phase_twoPiiiiiPiiiii, @function
_Z32__device_stub__Z9phase_twoPiiiiiPiiiii:
.LFB4257:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9phase_twoPiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4257:
.size _Z32__device_stub__Z9phase_twoPiiiiiPiiiii, .-_Z32__device_stub__Z9phase_twoPiiiiiPiiiii
.globl _Z9phase_twoPiiiii
.type _Z9phase_twoPiiiii, @function
_Z9phase_twoPiiiii:
.LFB4258:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9phase_twoPiiiiiPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4258:
.size _Z9phase_twoPiiiii, .-_Z9phase_twoPiiiii
.globl _Z35__device_stub__Z11phase_threePiiiiiPiiiii
.type _Z35__device_stub__Z11phase_threePiiiiiPiiiii, @function
_Z35__device_stub__Z11phase_threePiiiiiPiiiii:
.LFB4259:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11phase_threePiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4259:
.size _Z35__device_stub__Z11phase_threePiiiiiPiiiii, .-_Z35__device_stub__Z11phase_threePiiiiiPiiiii
.globl _Z11phase_threePiiiii
.type _Z11phase_threePiiiii, @function
_Z11phase_threePiiiii:
.LFB4260:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11phase_threePiiiiiPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4260:
.size _Z11phase_threePiiiii, .-_Z11phase_threePiiiii
.globl _Z8block_FWv
.type _Z8block_FWv, @function
_Z8block_FWv:
.LFB4227:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
movl vert(%rip), %r13d
movl block_size(%rip), %ecx
leal -1(%r13), %r12d
movl %r12d, %eax
cltd
idivl %ecx
movl %eax, %r12d
leal 1(%rax), %ebx
movl %ecx, %r14d
imull %ebx, %r14d
movslq %r13d, %r13
salq $2, %r13
movslq %r14d, %rsi
leaq 0(,%rsi,4), %r15
movl %eax, 24(%rsp)
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl %eax, 36(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl %ecx, 48(%rsp)
movl %ecx, 52(%rsp)
movl $1, 56(%rsp)
imulq %r15, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L36:
pushq 8(%rsp)
.cfi_def_cfa_offset 152
pushq $1
.cfi_def_cfa_offset 160
movslq vert(%rip), %r9
movq %r13, %r8
movq %r13, %rcx
movq data(%rip), %rdx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy2DAsync@PLT
movl block_size(%rip), %eax
imull %eax, %eax
cltq
leaq (%rax,%rax,2), %rbp
salq $2, %rbp
addq $16, %rsp
.cfi_def_cfa_offset 144
call cudaDeviceSynchronize@PLT
testl %ebx, %ebx
jle .L37
addl $1, %r12d
movl $0, %ebx
jmp .L41
.L45:
movl $32, %edi
call _Z26__device_stub__Z8init_gpuii
jmp .L36
.L46:
movl vert(%rip), %r8d
movl %r14d, %ecx
movl %ebx, %edx
movl block_size(%rip), %esi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9phase_onePiiiiiPiiiii
jmp .L38
.L47:
movl vert(%rip), %r8d
movl %r14d, %ecx
movl %ebx, %edx
movl block_size(%rip), %esi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9phase_twoPiiiiiPiiiii
jmp .L39
.L40:
addl $1, %ebx
cmpl %ebx, %r12d
je .L37
.L41:
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movq %rbp, %r8
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L38:
movl 56(%rsp), %ecx
movl $0, %r9d
movq %rbp, %r8
movq 48(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L39:
movl 56(%rsp), %ecx
movl $0, %r9d
movq %rbp, %r8
movq 48(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L40
movl vert(%rip), %r8d
movl %r14d, %ecx
movl %ebx, %edx
movl block_size(%rip), %esi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11phase_threePiiiiiPiiiii
jmp .L40
.L37:
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq $2
.cfi_def_cfa_offset 160
movslq vert(%rip), %r9
movq %r13, %r8
movq %r15, %rcx
movq 32(%rsp), %rdx
movq %r13, %rsi
movq data(%rip), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4227:
.size _Z8block_FWv, .-_Z8block_FWv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11phase_threePiiiii"
.LC1:
.string "_Z9phase_twoPiiiii"
.LC2:
.string "_Z9phase_onePiiiii"
.LC3:
.string "_Z8init_gpui"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4262:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11phase_threePiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9phase_twoPiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9phase_onePiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8init_gpui(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4262:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.globl _Z23dump_from_file_and_initPKc
.type _Z23dump_from_file_and_initPKc, @function
_Z23dump_from_file_and_initPKc:
.LFB4225:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4225
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $952, %rsp
.cfi_def_cfa_offset 1008
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 936(%rsp)
xorl %eax, %eax
leaq 416(%rsp), %r12
leaq 672(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 672(%rsp)
movq $0, 888(%rsp)
movb $0, 896(%rsp)
movb $0, 897(%rsp)
movq $0, 904(%rsp)
movq $0, 912(%rsp)
movq $0, 920(%rsp)
movq $0, 928(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rbp
movq %rbp, 416(%rsp)
movq -24(%rbp), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 416(%rsp,%rax)
movq $0, 424(%rsp)
movq 416(%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 416(%rsp)
leaq 40(%rax), %rax
movq %rax, 672(%rsp)
leaq 432(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 432(%rsp), %rsi
leaq 672(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 432(%rsp), %rdi
movl $8, %edx
movq %rbx, %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L102
movq 416(%rsp), %rax
movq -24(%rax), %rax
leaq 416(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L53
.L102:
movq 416(%rsp), %rax
movq -24(%rax), %rax
leaq 416(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE2:
.L53:
leaq 16(%rsp), %rbx
leaq 144(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 144(%rsp)
movq $0, 360(%rsp)
movb $0, 368(%rsp)
movb $0, 369(%rsp)
movq $0, 376(%rsp)
movq $0, 384(%rsp)
movq $0, 392(%rsp)
movq $0, 400(%rsp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r12
movq %r12, 16(%rsp)
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r15
movq -24(%r12), %rax
movq %r15, 16(%rsp,%rax)
movq $0, 24(%rsp)
movq 16(%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB3:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE3:
jmp .L103
.L90:
endbr64
movq %rax, %rbx
leaq 432(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L56:
movq %rbp, 416(%rsp)
movq -24(%rbp), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 416(%rsp,%rax)
movq $0, 424(%rsp)
.L57:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 672(%rsp)
leaq 672(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 936(%rsp), %rax
subq %fs:40, %rax
je .L58
call __stack_chk_fail@PLT
.L89:
endbr64
movq %rax, %rbx
jmp .L56
.L88:
endbr64
movq %rax, %rbx
jmp .L57
.L58:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L103:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r13
movq %r13, 32(%rsp)
movq -24(%r13), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, 32(%rsp,%rax)
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
.LEHB5:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE5:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
movq %r14, 16(%rsp)
movq -24(%r14), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, 16(%rsp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 80(%rax), %rax
movq %rax, 144(%rsp)
leaq -40(%rax), %rax
movq %rax, 32(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 40(%rsp)
movl $24, 104(%rsp)
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq $0, 120(%rsp)
movb $0, 128(%rsp)
leaq 40(%rsp), %rsi
leaq 144(%rsp), %rdi
.LEHB6:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE6:
jmp .L104
.L91:
endbr64
movq %r12, 16(%rsp)
movq -24(%r12), %rdx
movq %r15, 16(%rsp,%rdx)
movq $0, 24(%rsp)
movq %rax, %rbx
.L61:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 144(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L64:
leaq 416(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 936(%rsp), %rax
subq %fs:40, %rax
je .L82
call __stack_chk_fail@PLT
.L87:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 40(%rsp)
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .L63
movq 128(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L63:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 16(%rsp), %rbp
leaq 96(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rbp, %rdi
call _ZNSdD2Ev@PLT
jmp .L61
.L86:
endbr64
movq %rax, %rbx
jmp .L61
.L104:
leaq 432(%rsp), %rsi
leaq 32(%rsp), %rdi
.LEHB7:
call _ZNSolsEPSt15basic_streambufIcSt11char_traitsIcEE@PLT
leaq 16(%rsp), %rdi
leaq vert(%rip), %rsi
call _ZNSirsERi@PLT
movq %rax, %rdi
leaq edge(%rip), %rsi
call _ZNSirsERi@PLT
movl vert(%rip), %edi
movl %edi, %eax
imull %edi, %eax
movl %eax, vert2(%rip)
movslq %edi, %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L65
salq $3, %rdi
call _Znam@PLT
movq %rax, Dist(%rip)
movslq vert2(%rip), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L105
salq $2, %rdi
call _Znam@PLT
jmp .L106
.L65:
movq 936(%rsp), %rax
subq %fs:40, %rax
je .L68
call __stack_chk_fail@PLT
.L68:
call __cxa_throw_bad_array_new_length@PLT
.L85:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L64
.L106:
movq %rax, data(%rip)
movslq vert2(%rip), %rdx
leaq (%rax,%rdx,4), %rdx
cmpq %rdx, %rax
je .L69
.L70:
movl $1000000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L70
.L69:
movl vert(%rip), %eax
movl $0, %edx
testl %eax, %eax
jle .L72
.L71:
imull %edx, %eax
cltq
movq data(%rip), %rcx
leaq (%rcx,%rax,4), %rcx
movq Dist(%rip), %rax
movq %rcx, (%rax,%rdx,8)
movq Dist(%rip), %rax
movq (%rax,%rdx,8), %rax
movl $0, (%rax,%rdx,4)
movl vert(%rip), %eax
addq $1, %rdx
cmpl %edx, %eax
jg .L71
.L72:
cmpl %eax, block_size(%rip)
jle .L74
movl %eax, block_size(%rip)
.L74:
movl edge(%rip), %eax
subl $1, %eax
movl %eax, edge(%rip)
js .L75
leaq 4(%rsp), %rbx
jmp .L76
.L105:
movq 936(%rsp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L73:
call __cxa_throw_bad_array_new_length@PLT
.L107:
movq %rax, %rdi
leaq 8(%rsp), %rsi
call _ZNSirsERi@PLT
movq %rax, %rdi
leaq 12(%rsp), %rsi
call _ZNSirsERi@PLT
movslq 4(%rsp), %rcx
movslq 8(%rsp), %rdx
movq Dist(%rip), %rax
movq (%rax,%rcx,8), %rax
movl 12(%rsp), %ecx
movl %ecx, (%rax,%rdx,4)
movl edge(%rip), %eax
subl $1, %eax
movl %eax, edge(%rip)
js .L75
.L76:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _ZNSirsERi@PLT
jmp .L107
.L75:
leaq 432(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE7:
testq %rax, %rax
je .L108
.L77:
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 80(%rax), %rax
movq %rax, 144(%rsp)
leaq -40(%rax), %rax
movq %rax, 32(%rsp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 40(%rsp)
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .L78
movq 128(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L78:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, 16(%rsp)
movq -24(%r14), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, 16(%rsp,%rax)
movq %r13, 32(%rsp)
movq -24(%r13), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, 32(%rsp,%rax)
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r15, 16(%rsp,%rax)
movq $0, 24(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 144(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 416(%rsp)
leaq 40(%rax), %rax
movq %rax, 672(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 432(%rsp)
leaq 432(%rsp), %rdi
.LEHB8:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE8:
jmp .L80
.L108:
movq 416(%rsp), %rax
movq -24(%rax), %rax
leaq 416(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB9:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE9:
jmp .L77
.L92:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L80:
leaq 536(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 432(%rsp)
leaq 488(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %rbp, 416(%rsp)
movq -24(%rbp), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rbx
movq %rbx, 416(%rsp,%rax)
movq $0, 424(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 672(%rsp)
leaq 672(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 936(%rsp), %rax
subq %fs:40, %rax
jne .L109
addq $952, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
movq %rbx, %rdi
.LEHB10:
call _Unwind_Resume@PLT
.LEHE10:
.L109:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4225:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4225:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4225-.LLSDATTD4225
.LLSDATTD4225:
.byte 0x1
.uleb128 .LLSDACSE4225-.LLSDACSB4225
.LLSDACSB4225:
.uleb128 .LEHB0-.LFB4225
.uleb128 .LEHE0-.LEHB0
.uleb128 .L88-.LFB4225
.uleb128 0
.uleb128 .LEHB1-.LFB4225
.uleb128 .LEHE1-.LEHB1
.uleb128 .L89-.LFB4225
.uleb128 0
.uleb128 .LEHB2-.LFB4225
.uleb128 .LEHE2-.LEHB2
.uleb128 .L90-.LFB4225
.uleb128 0
.uleb128 .LEHB3-.LFB4225
.uleb128 .LEHE3-.LEHB3
.uleb128 .L86-.LFB4225
.uleb128 0
.uleb128 .LEHB4-.LFB4225
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4225
.uleb128 .LEHE5-.LEHB5
.uleb128 .L91-.LFB4225
.uleb128 0
.uleb128 .LEHB6-.LFB4225
.uleb128 .LEHE6-.LEHB6
.uleb128 .L87-.LFB4225
.uleb128 0
.uleb128 .LEHB7-.LFB4225
.uleb128 .LEHE7-.LEHB7
.uleb128 .L85-.LFB4225
.uleb128 0
.uleb128 .LEHB8-.LFB4225
.uleb128 .LEHE8-.LEHB8
.uleb128 .L92-.LFB4225
.uleb128 0x1
.uleb128 .LEHB9-.LFB4225
.uleb128 .LEHE9-.LEHB9
.uleb128 .L85-.LFB4225
.uleb128 0
.uleb128 .LEHB10-.LFB4225
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.LLSDACSE4225:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4225:
.text
.size _Z23dump_from_file_and_initPKc, .-_Z23dump_from_file_and_initPKc
.globl _Z12dump_to_filePKc
.type _Z12dump_to_filePKc, @function
_Z12dump_to_filePKc:
.LFB4226:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4226
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $536, %rsp
.cfi_def_cfa_offset 576
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 520(%rsp)
xorl %eax, %eax
movq %rsp, %r12
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
movq $0, 464(%rsp)
movb $0, 472(%rsp)
movb $0, 473(%rsp)
movq $0, 480(%rsp)
movq $0, 488(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rbx
movq %rbx, (%rsp)
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r13
movq -24(%rbx), %rax
movq %r13, (%rsp,%rax)
movq (%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB11:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE11:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 248(%rsp)
leaq 8(%rsp), %rdi
.LEHB12:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE12:
leaq 8(%rsp), %rsi
leaq 248(%rsp), %rdi
.LEHB13:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 8(%rsp), %rdi
movl $16, %edx
movq %rbp, %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L132
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L112
.L132:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE13:
.L112:
movslq vert2(%rip), %rdx
salq $2, %rdx
movq %rsp, %rdi
movq data(%rip), %rsi
.LEHB14:
call _ZNSo5writeEPKcl@PLT
.LEHE14:
jmp .L133
.L127:
endbr64
movq %rax, %rbp
leaq 8(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
movq %rbp, %rax
.L115:
movq %rbx, (%rsp)
movq -24(%rbx), %rdx
movq %r13, (%rsp,%rdx)
movq %rax, %rbx
.L116:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L117
call __stack_chk_fail@PLT
.L126:
endbr64
jmp .L115
.L125:
endbr64
movq %rax, %rbx
jmp .L116
.L117:
movq %rbx, %rdi
.LEHB15:
call _Unwind_Resume@PLT
.LEHE15:
.L133:
leaq 8(%rsp), %rdi
.LEHB16:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE16:
testq %rax, %rax
je .L134
.L118:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 248(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
.LEHB17:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE17:
jmp .L120
.L134:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB18:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE18:
jmp .L118
.L128:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L120:
leaq 112(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %rbx, (%rsp)
movq -24(%rbx), %rax
movq %r13, (%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 248(%rsp)
leaq 248(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
jne .L135
addq $536, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L124:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L122
call __stack_chk_fail@PLT
.L122:
movq %rbx, %rdi
.LEHB19:
call _Unwind_Resume@PLT
.LEHE19:
.L135:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4226:
.section .gcc_except_table
.align 4
.LLSDA4226:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4226-.LLSDATTD4226
.LLSDATTD4226:
.byte 0x1
.uleb128 .LLSDACSE4226-.LLSDACSB4226
.LLSDACSB4226:
.uleb128 .LEHB11-.LFB4226
.uleb128 .LEHE11-.LEHB11
.uleb128 .L125-.LFB4226
.uleb128 0
.uleb128 .LEHB12-.LFB4226
.uleb128 .LEHE12-.LEHB12
.uleb128 .L126-.LFB4226
.uleb128 0
.uleb128 .LEHB13-.LFB4226
.uleb128 .LEHE13-.LEHB13
.uleb128 .L127-.LFB4226
.uleb128 0
.uleb128 .LEHB14-.LFB4226
.uleb128 .LEHE14-.LEHB14
.uleb128 .L124-.LFB4226
.uleb128 0
.uleb128 .LEHB15-.LFB4226
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.uleb128 .LEHB16-.LFB4226
.uleb128 .LEHE16-.LEHB16
.uleb128 .L124-.LFB4226
.uleb128 0
.uleb128 .LEHB17-.LFB4226
.uleb128 .LEHE17-.LEHB17
.uleb128 .L128-.LFB4226
.uleb128 0x1
.uleb128 .LEHB18-.LFB4226
.uleb128 .LEHE18-.LEHB18
.uleb128 .L124-.LFB4226
.uleb128 0
.uleb128 .LEHB19-.LFB4226
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.LLSDACSE4226:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4226:
.text
.size _Z12dump_to_filePKc, .-_Z12dump_to_filePKc
.globl main
.type main, @function
main:
.LFB4228:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
call _Z23dump_from_file_and_initPKc
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, block_size(%rip)
call _Z8block_FWv
movq 16(%rbx), %rdi
call _Z12dump_to_filePKc
movq Dist(%rip), %rdi
testq %rdi, %rdi
je .L137
call _ZdaPv@PLT
.L137:
movq data(%rip), %rdi
testq %rdi, %rdi
je .L138
call _ZdaPv@PLT
.L138:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4228:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl vert2
.bss
.align 4
.type vert2, @object
.size vert2, 4
vert2:
.zero 4
.globl edge
.align 4
.type edge, @object
.size edge, 4
edge:
.zero 4
.globl vert
.align 4
.type vert, @object
.size vert, 4
vert:
.zero 4
.globl block_size
.align 4
.type block_size, @object
.size block_size, 4
block_size:
.zero 4
.globl data
.align 8
.type data, @object
.size data, 8
data:
.zero 8
.globl Dist
.align 8
.type Dist, @object
.size Dist, 8
Dist:
.zero 8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <string>
#include <sstream>
#include <fstream>
#include <algorithm>
#include <chrono>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <cuda.h>
#include <unistd.h>
//#define _DEBUG_
//#define _TIME_MEASURE_
#ifdef _DEBUG_
#include <string>
#include <sstream>
int __print_step = 0;
void __pt_log(const char *h_, const char *f_, ...){
std::stringstream ss;
ss << h_ << f_ << '\n';
std::string format = ss.str();
va_list va;
va_start(va, f_);
vprintf(format.c_str(), va);
va_end(va);
__print_step++;
}
#define VA_ARGS(...) , ##__VA_ARGS__
#define LOG(f_, ...) __pt_log(\
"[LOG] Step %3d: ", (f_), \
__print_step VA_ARGS(__VA_ARGS__))
#else
#define LOG(f_, ...)
#endif
#define INF 1000000000
#define CEIL(a, b) (( (a) - 1 ) / (b) + 1 )
int **Dist;
int *data;
int block_size;
int vert, edge;
int vert2;
inline void init(){
vert2 = vert*vert;
Dist = new int*[vert];
data = new int[vert2];
std::fill(data, data + vert2, INF);
for(int i=0;i<vert;++i){
Dist[i] = data + i*vert;
Dist[i][i] = 0;
}
if(vert < block_size){
block_size = vert;
}
}
inline void finalize(){
delete[] Dist;
delete[] data;
}
void dump_from_file_and_init(const char *file){
std::ifstream fin(file);
std::stringstream ss;
ss << fin.rdbuf();
ss >> vert >> edge;
LOG("vert: %d, edge: %d", vert, edge);
init();
int i, j, w;
while(--edge >=0){
ss >> i >> j >> w;
Dist[i][j] = w;
}
fin.close();
}
void dump_to_file(const char *file){
std::ofstream fout(file);
fout.write((char*)data, sizeof(int)*vert2);
fout.close();
}
__global__ void init_gpu(int reps){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx >= reps) return;
}
__global__ void phase_one(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int c = block_size * round + ty;
const int r = block_size * round + tx;
const int cell = c*width+r;
const int s_cell = ty*block_size+tx;
if(c >= vert || r >= vert){
s[s_cell] = INF;
}else{
s[s_cell] = dist[cell];
}
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
// min(dist[ty][tx], dist[ty][i] + dist[i][tx])
n = s[ty*block_size+k] + s[k*block_size+tx];
if(n < s[s_cell]){
s[s_cell] = n;
}
__syncthreads();
}
dist[cell] = s[s_cell];
}
__global__ void phase_two(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s2[];
int* const s_m = s2; //main(block)
int* const s_c = s2 + block_size*block_size; //center(pivot)
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
int mc, mr; //main
int cc, cr; //center(pivot)
if(bx >= round)++bx; //shift
if(by == 0){ //horizontal
mc = block_size * round + ty;
mr = block_size * bx + tx;
cc = mc;
cr = block_size * round + tx;
}else{ //vertical
mc = block_size * bx + ty;
mr = block_size * round + tx;
cc = block_size * round + ty;
cr = mr;
}
int m_cell = mc * width + mr;
int c_cell = cc * width + cr;
int s_cell = ty * block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(cc >= vert || cr >= vert) s_c[s_cell] = INF;
else s_c[s_cell] = dist[c_cell];
__syncthreads();
int n, k;
if(by == 0){
for(k=0;k<block_size;++k){
n = s_c[ty*block_size+k] + s_m[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}else{
for(k=0;k<block_size;++k){
n = s_m[ty*block_size+k] + s_c[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}
dist[m_cell] = s_m[s_cell];
}
__global__ void phase_three(int32_t* const dist, int block_size, int round, int width, int vert){
int bs2 = block_size*block_size;
extern __shared__ int s3[];
int* const s_m = s3;
int* const s_l = s3 + bs2;
int* const s_r = s_l + bs2;
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= round)++bx; //shift x
if(by >= round)++by; //shift y
const int mc = block_size * by + ty;
const int mr = block_size * bx + tx;
const int lc = mc;
const int lr = block_size * round + tx;
const int rc = block_size * round + ty;
const int rr = mr;
const int m_cell = mc*width + mr;
const int l_cell = lc*width + lr;
const int r_cell = rc*width + rr;
const int s_cell = ty*block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(lc >= vert || lr >= vert) s_l[s_cell] = INF;
else s_l[s_cell] = dist[l_cell];
if(rc >= vert || rr >= vert) s_r[s_cell] = INF;
else s_r[s_cell] = dist[r_cell];
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
n = s_l[ty*block_size+k] + s_r[k*block_size+tx];
if(n<s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
dist[m_cell] = s_m[s_cell];
}
extern __shared__ int S[];
void block_FW(){
#ifdef _TIME_MEASURE_
auto start = std::chrono::high_resolution_clock::now();
#endif
cudaStream_t init_stream;
cudaStreamCreate(&init_stream);
int Round = CEIL(vert, block_size);
int padded_size = Round * block_size;
size_t vert_w_bytes = vert * sizeof(int);
size_t padded_w_bytes = padded_size * sizeof(int);
int32_t *device_ptr;
//size_t pitch;
dim3 p2b(Round-1, 2, 1); //phase 2 block
dim3 p3b(Round-1, Round-1, 1); //phase 3 block
dim3 dimt(block_size, block_size, 1); //thread
//cudaMallocPitch(&device_ptr, &pitch, vert_byte, vert_byte, vert);
cudaMalloc(&device_ptr, padded_w_bytes * padded_size);
//size_t pitch_int = pitch / sizeof(int);
//LOG("pitch => %zu bytes (%zu words)", pitch, pitch_int);
LOG("the number of blocks: %d", Round);
init_gpu<<< 1, dimt >>>(32);
//dst_ptr, dst_pitch, src, src_pitch, w, h, kind
cudaMemcpy2DAsync(device_ptr, padded_w_bytes, data, vert_w_bytes,
vert_w_bytes, vert, cudaMemcpyHostToDevice, init_stream);
size_t bs2b3 = block_size * block_size * sizeof(int) * 3;
cudaDeviceSynchronize();
for(int r=0; r < Round; ++r){
LOG("Round %d/%d", r+1, Round);
phase_one<<< 1 , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_two<<< p2b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_three<<< p3b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
}
cudaMemcpy2D(data, vert_w_bytes, device_ptr, padded_w_bytes,
vert_w_bytes, vert, cudaMemcpyDeviceToHost);
cudaFree(device_ptr);
cudaStreamDestroy(init_stream);
#ifdef _TIME_MEASURE_
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
double elapsed_time = diff.count() * 1000;
printf("Total time: %f ms (%f GFLOPS)\n", elapsed_time, 2*vert*vert*vert / (elapsed_time * 1e6));
#endif
}
int main(int argc, char **argv){
dump_from_file_and_init(argv[1]);
block_size = std::atoi(argv[3]);
block_FW();
dump_to_file(argv[2]);
finalize();
return 0;
} | #include <iostream>
#include <string>
#include <sstream>
#include <fstream>
#include <algorithm>
#include <chrono>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
//#define _DEBUG_
//#define _TIME_MEASURE_
#ifdef _DEBUG_
#include <string>
#include <sstream>
int __print_step = 0;
void __pt_log(const char *h_, const char *f_, ...){
std::stringstream ss;
ss << h_ << f_ << '\n';
std::string format = ss.str();
va_list va;
va_start(va, f_);
vprintf(format.c_str(), va);
va_end(va);
__print_step++;
}
#define VA_ARGS(...) , ##__VA_ARGS__
#define LOG(f_, ...) __pt_log(\
"[LOG] Step %3d: ", (f_), \
__print_step VA_ARGS(__VA_ARGS__))
#else
#define LOG(f_, ...)
#endif
#define INF 1000000000
#define CEIL(a, b) (( (a) - 1 ) / (b) + 1 )
int **Dist;
int *data;
int block_size;
int vert, edge;
int vert2;
inline void init(){
vert2 = vert*vert;
Dist = new int*[vert];
data = new int[vert2];
std::fill(data, data + vert2, INF);
for(int i=0;i<vert;++i){
Dist[i] = data + i*vert;
Dist[i][i] = 0;
}
if(vert < block_size){
block_size = vert;
}
}
inline void finalize(){
delete[] Dist;
delete[] data;
}
void dump_from_file_and_init(const char *file){
std::ifstream fin(file);
std::stringstream ss;
ss << fin.rdbuf();
ss >> vert >> edge;
LOG("vert: %d, edge: %d", vert, edge);
init();
int i, j, w;
while(--edge >=0){
ss >> i >> j >> w;
Dist[i][j] = w;
}
fin.close();
}
void dump_to_file(const char *file){
std::ofstream fout(file);
fout.write((char*)data, sizeof(int)*vert2);
fout.close();
}
__global__ void init_gpu(int reps){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx >= reps) return;
}
__global__ void phase_one(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int c = block_size * round + ty;
const int r = block_size * round + tx;
const int cell = c*width+r;
const int s_cell = ty*block_size+tx;
if(c >= vert || r >= vert){
s[s_cell] = INF;
}else{
s[s_cell] = dist[cell];
}
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
// min(dist[ty][tx], dist[ty][i] + dist[i][tx])
n = s[ty*block_size+k] + s[k*block_size+tx];
if(n < s[s_cell]){
s[s_cell] = n;
}
__syncthreads();
}
dist[cell] = s[s_cell];
}
__global__ void phase_two(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s2[];
int* const s_m = s2; //main(block)
int* const s_c = s2 + block_size*block_size; //center(pivot)
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
int mc, mr; //main
int cc, cr; //center(pivot)
if(bx >= round)++bx; //shift
if(by == 0){ //horizontal
mc = block_size * round + ty;
mr = block_size * bx + tx;
cc = mc;
cr = block_size * round + tx;
}else{ //vertical
mc = block_size * bx + ty;
mr = block_size * round + tx;
cc = block_size * round + ty;
cr = mr;
}
int m_cell = mc * width + mr;
int c_cell = cc * width + cr;
int s_cell = ty * block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(cc >= vert || cr >= vert) s_c[s_cell] = INF;
else s_c[s_cell] = dist[c_cell];
__syncthreads();
int n, k;
if(by == 0){
for(k=0;k<block_size;++k){
n = s_c[ty*block_size+k] + s_m[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}else{
for(k=0;k<block_size;++k){
n = s_m[ty*block_size+k] + s_c[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}
dist[m_cell] = s_m[s_cell];
}
__global__ void phase_three(int32_t* const dist, int block_size, int round, int width, int vert){
int bs2 = block_size*block_size;
extern __shared__ int s3[];
int* const s_m = s3;
int* const s_l = s3 + bs2;
int* const s_r = s_l + bs2;
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= round)++bx; //shift x
if(by >= round)++by; //shift y
const int mc = block_size * by + ty;
const int mr = block_size * bx + tx;
const int lc = mc;
const int lr = block_size * round + tx;
const int rc = block_size * round + ty;
const int rr = mr;
const int m_cell = mc*width + mr;
const int l_cell = lc*width + lr;
const int r_cell = rc*width + rr;
const int s_cell = ty*block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(lc >= vert || lr >= vert) s_l[s_cell] = INF;
else s_l[s_cell] = dist[l_cell];
if(rc >= vert || rr >= vert) s_r[s_cell] = INF;
else s_r[s_cell] = dist[r_cell];
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
n = s_l[ty*block_size+k] + s_r[k*block_size+tx];
if(n<s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
dist[m_cell] = s_m[s_cell];
}
extern __shared__ int S[];
void block_FW(){
#ifdef _TIME_MEASURE_
auto start = std::chrono::high_resolution_clock::now();
#endif
hipStream_t init_stream;
hipStreamCreate(&init_stream);
int Round = CEIL(vert, block_size);
int padded_size = Round * block_size;
size_t vert_w_bytes = vert * sizeof(int);
size_t padded_w_bytes = padded_size * sizeof(int);
int32_t *device_ptr;
//size_t pitch;
dim3 p2b(Round-1, 2, 1); //phase 2 block
dim3 p3b(Round-1, Round-1, 1); //phase 3 block
dim3 dimt(block_size, block_size, 1); //thread
//cudaMallocPitch(&device_ptr, &pitch, vert_byte, vert_byte, vert);
hipMalloc(&device_ptr, padded_w_bytes * padded_size);
//size_t pitch_int = pitch / sizeof(int);
//LOG("pitch => %zu bytes (%zu words)", pitch, pitch_int);
LOG("the number of blocks: %d", Round);
init_gpu<<< 1, dimt >>>(32);
//dst_ptr, dst_pitch, src, src_pitch, w, h, kind
hipMemcpy2DAsync(device_ptr, padded_w_bytes, data, vert_w_bytes,
vert_w_bytes, vert, hipMemcpyHostToDevice, init_stream);
size_t bs2b3 = block_size * block_size * sizeof(int) * 3;
hipDeviceSynchronize();
for(int r=0; r < Round; ++r){
LOG("Round %d/%d", r+1, Round);
phase_one<<< 1 , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_two<<< p2b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_three<<< p3b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
}
hipMemcpy2D(data, vert_w_bytes, device_ptr, padded_w_bytes,
vert_w_bytes, vert, hipMemcpyDeviceToHost);
hipFree(device_ptr);
hipStreamDestroy(init_stream);
#ifdef _TIME_MEASURE_
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
double elapsed_time = diff.count() * 1000;
printf("Total time: %f ms (%f GFLOPS)\n", elapsed_time, 2*vert*vert*vert / (elapsed_time * 1e6));
#endif
}
int main(int argc, char **argv){
dump_from_file_and_init(argv[1]);
block_size = std::atoi(argv[3]);
block_FW();
dump_to_file(argv[2]);
finalize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <string>
#include <sstream>
#include <fstream>
#include <algorithm>
#include <chrono>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
//#define _DEBUG_
//#define _TIME_MEASURE_
#ifdef _DEBUG_
#include <string>
#include <sstream>
int __print_step = 0;
void __pt_log(const char *h_, const char *f_, ...){
std::stringstream ss;
ss << h_ << f_ << '\n';
std::string format = ss.str();
va_list va;
va_start(va, f_);
vprintf(format.c_str(), va);
va_end(va);
__print_step++;
}
#define VA_ARGS(...) , ##__VA_ARGS__
#define LOG(f_, ...) __pt_log(\
"[LOG] Step %3d: ", (f_), \
__print_step VA_ARGS(__VA_ARGS__))
#else
#define LOG(f_, ...)
#endif
#define INF 1000000000
#define CEIL(a, b) (( (a) - 1 ) / (b) + 1 )
int **Dist;
int *data;
int block_size;
int vert, edge;
int vert2;
inline void init(){
vert2 = vert*vert;
Dist = new int*[vert];
data = new int[vert2];
std::fill(data, data + vert2, INF);
for(int i=0;i<vert;++i){
Dist[i] = data + i*vert;
Dist[i][i] = 0;
}
if(vert < block_size){
block_size = vert;
}
}
inline void finalize(){
delete[] Dist;
delete[] data;
}
void dump_from_file_and_init(const char *file){
std::ifstream fin(file);
std::stringstream ss;
ss << fin.rdbuf();
ss >> vert >> edge;
LOG("vert: %d, edge: %d", vert, edge);
init();
int i, j, w;
while(--edge >=0){
ss >> i >> j >> w;
Dist[i][j] = w;
}
fin.close();
}
void dump_to_file(const char *file){
std::ofstream fout(file);
fout.write((char*)data, sizeof(int)*vert2);
fout.close();
}
__global__ void init_gpu(int reps){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx >= reps) return;
}
__global__ void phase_one(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int c = block_size * round + ty;
const int r = block_size * round + tx;
const int cell = c*width+r;
const int s_cell = ty*block_size+tx;
if(c >= vert || r >= vert){
s[s_cell] = INF;
}else{
s[s_cell] = dist[cell];
}
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
// min(dist[ty][tx], dist[ty][i] + dist[i][tx])
n = s[ty*block_size+k] + s[k*block_size+tx];
if(n < s[s_cell]){
s[s_cell] = n;
}
__syncthreads();
}
dist[cell] = s[s_cell];
}
__global__ void phase_two(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s2[];
int* const s_m = s2; //main(block)
int* const s_c = s2 + block_size*block_size; //center(pivot)
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
int mc, mr; //main
int cc, cr; //center(pivot)
if(bx >= round)++bx; //shift
if(by == 0){ //horizontal
mc = block_size * round + ty;
mr = block_size * bx + tx;
cc = mc;
cr = block_size * round + tx;
}else{ //vertical
mc = block_size * bx + ty;
mr = block_size * round + tx;
cc = block_size * round + ty;
cr = mr;
}
int m_cell = mc * width + mr;
int c_cell = cc * width + cr;
int s_cell = ty * block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(cc >= vert || cr >= vert) s_c[s_cell] = INF;
else s_c[s_cell] = dist[c_cell];
__syncthreads();
int n, k;
if(by == 0){
for(k=0;k<block_size;++k){
n = s_c[ty*block_size+k] + s_m[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}else{
for(k=0;k<block_size;++k){
n = s_m[ty*block_size+k] + s_c[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}
dist[m_cell] = s_m[s_cell];
}
__global__ void phase_three(int32_t* const dist, int block_size, int round, int width, int vert){
int bs2 = block_size*block_size;
extern __shared__ int s3[];
int* const s_m = s3;
int* const s_l = s3 + bs2;
int* const s_r = s_l + bs2;
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= round)++bx; //shift x
if(by >= round)++by; //shift y
const int mc = block_size * by + ty;
const int mr = block_size * bx + tx;
const int lc = mc;
const int lr = block_size * round + tx;
const int rc = block_size * round + ty;
const int rr = mr;
const int m_cell = mc*width + mr;
const int l_cell = lc*width + lr;
const int r_cell = rc*width + rr;
const int s_cell = ty*block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(lc >= vert || lr >= vert) s_l[s_cell] = INF;
else s_l[s_cell] = dist[l_cell];
if(rc >= vert || rr >= vert) s_r[s_cell] = INF;
else s_r[s_cell] = dist[r_cell];
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
n = s_l[ty*block_size+k] + s_r[k*block_size+tx];
if(n<s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
dist[m_cell] = s_m[s_cell];
}
extern __shared__ int S[];
void block_FW(){
#ifdef _TIME_MEASURE_
auto start = std::chrono::high_resolution_clock::now();
#endif
hipStream_t init_stream;
hipStreamCreate(&init_stream);
int Round = CEIL(vert, block_size);
int padded_size = Round * block_size;
size_t vert_w_bytes = vert * sizeof(int);
size_t padded_w_bytes = padded_size * sizeof(int);
int32_t *device_ptr;
//size_t pitch;
dim3 p2b(Round-1, 2, 1); //phase 2 block
dim3 p3b(Round-1, Round-1, 1); //phase 3 block
dim3 dimt(block_size, block_size, 1); //thread
//cudaMallocPitch(&device_ptr, &pitch, vert_byte, vert_byte, vert);
hipMalloc(&device_ptr, padded_w_bytes * padded_size);
//size_t pitch_int = pitch / sizeof(int);
//LOG("pitch => %zu bytes (%zu words)", pitch, pitch_int);
LOG("the number of blocks: %d", Round);
init_gpu<<< 1, dimt >>>(32);
//dst_ptr, dst_pitch, src, src_pitch, w, h, kind
hipMemcpy2DAsync(device_ptr, padded_w_bytes, data, vert_w_bytes,
vert_w_bytes, vert, hipMemcpyHostToDevice, init_stream);
size_t bs2b3 = block_size * block_size * sizeof(int) * 3;
hipDeviceSynchronize();
for(int r=0; r < Round; ++r){
LOG("Round %d/%d", r+1, Round);
phase_one<<< 1 , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_two<<< p2b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_three<<< p3b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
}
hipMemcpy2D(data, vert_w_bytes, device_ptr, padded_w_bytes,
vert_w_bytes, vert, hipMemcpyDeviceToHost);
hipFree(device_ptr);
hipStreamDestroy(init_stream);
#ifdef _TIME_MEASURE_
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
double elapsed_time = diff.count() * 1000;
printf("Total time: %f ms (%f GFLOPS)\n", elapsed_time, 2*vert*vert*vert / (elapsed_time * 1e6));
#endif
}
int main(int argc, char **argv){
dump_from_file_and_init(argv[1]);
block_size = std::atoi(argv[3]);
block_FW();
dump_to_file(argv[2]);
finalize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8init_gpui
.globl _Z8init_gpui
.p2align 8
.type _Z8init_gpui,@function
_Z8init_gpui:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8init_gpui
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8init_gpui, .Lfunc_end0-_Z8init_gpui
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9phase_onePiiiii
.globl _Z9phase_onePiiiii
.p2align 8
.type _Z9phase_onePiiiii,@function
_Z9phase_onePiiiii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s7, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s2, v2
v_mad_u64_u32 v[0:1], null, v5, s0, v[3:4]
v_max_i32_e32 v1, v5, v3
v_mov_b32_e32 v5, 0x3b9aca00
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s1, v1
v_ashrrev_i32_e32 v1, 31, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
v_mad_u64_u32 v[6:7], null, v4, s6, v[2:3]
s_cmp_lt_i32 s6, 1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v6, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
v_mul_lo_u32 v4, v4, s6
v_lshl_add_u32 v2, v2, 2, 0
s_lshl_b32 s0, s6, 2
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v4, v4, 2, 0
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, s0, v2
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s6, s6, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_7
.LBB1_5:
ds_load_b32 v5, v4
ds_load_b32 v6, v2
ds_load_b32 v7, v3
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v6, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v5, v7
s_cbranch_execz .LBB1_4
ds_store_b32 v3, v5
s_branch .LBB1_4
.LBB1_7:
ds_load_b32 v2, v3
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9phase_onePiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9phase_onePiiiii, .Lfunc_end1-_Z9phase_onePiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9phase_twoPiiiii
.globl _Z9phase_twoPiiiii
.p2align 8
.type _Z9phase_twoPiiiii,@function
_Z9phase_twoPiiiii:
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s3
s_mul_i32 s3, s3, s2
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s4, s14, 0
s_cmp_lg_u32 s15, 0
s_cselect_b32 s6, -1, 0
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccz .LBB2_2
v_mad_u64_u32 v[5:6], null, s4, s2, v[0:1]
v_add_nc_u32_e32 v4, s3, v1
v_add_nc_u32_e32 v8, s3, v0
s_branch .LBB2_3
.LBB2_2:
s_mov_b32 s5, -1
.LBB2_3:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v6, v4
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB2_5
v_add_nc_u32_e32 v8, s3, v0
v_mad_u64_u32 v[6:7], null, s4, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v5, v8 :: v_dual_add_nc_u32 v4, s3, v1
.LBB2_5:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v5, s4, v[6:7]
v_max_i32_e32 v3, v5, v6
v_dual_mov_b32 v6, 0x3b9aca00 :: v_dual_mov_b32 v7, 0x3b9aca00
v_cmp_gt_i32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB2_7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_co_u32 v9, vcc_lo, s0, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_load_b32 v7, v[9:10], off
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s3
v_mul_lo_u32 v5, v0, s2
v_max_i32_e32 v9, v8, v4
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v5, v1
v_lshl_add_u32 v10, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v10, v7
v_cmpx_gt_i32_e64 s5, v9
s_cbranch_execz .LBB2_9
v_mad_u64_u32 v[6:7], null, v8, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v6, v[6:7], off
.LBB2_9:
s_or_b32 exec_lo, exec_lo, s3
s_mul_i32 s3, s2, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s3, s3, 2
s_add_i32 s3, s3, 0
s_cmp_gt_i32 s2, 0
v_lshl_add_u32 v7, v0, 2, s3
s_cselect_b32 s4, -1, 0
s_and_not1_b32 vcc_lo, exec_lo, s6
v_cndmask_b32_e64 v4, 0, 1, s4
s_waitcnt vmcnt(0)
ds_store_b32 v7, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB2_16
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB2_15
v_lshl_add_u32 v6, v1, 2, s3
v_lshl_add_u32 v7, v5, 2, 0
v_lshl_add_u32 v8, v0, 2, 0
s_lshl_b32 s4, s2, 2
s_mov_b32 s5, s2
s_branch .LBB2_13
.p2align 6
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v6, s4, v6
v_add_nc_u32_e32 v7, 4, v7
s_add_i32 s5, s5, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s5, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_15
.LBB2_13:
ds_load_b32 v9, v7
ds_load_b32 v10, v6
ds_load_b32 v11, v8
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v9, v10, v9
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v9, v11
s_cbranch_execz .LBB2_12
ds_store_b32 v8, v9
s_branch .LBB2_12
.LBB2_15:
s_cbranch_execz .LBB2_17
s_branch .LBB2_22
.LBB2_16:
.LBB2_17:
v_cmp_ne_u32_e32 vcc_lo, 1, v4
s_cbranch_vccnz .LBB2_22
v_lshl_add_u32 v1, v1, 2, 0
v_lshl_add_u32 v4, v5, 2, s3
v_lshl_add_u32 v5, v0, 2, 0
s_lshl_b32 s3, s2, 2
s_branch .LBB2_20
.p2align 6
.LBB2_19:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v1, s3, v1
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_22
.LBB2_20:
ds_load_b32 v6, v4
ds_load_b32 v7, v1
ds_load_b32 v8, v5
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v6, v7, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v6, v8
s_cbranch_execz .LBB2_19
ds_store_b32 v5, v6
s_branch .LBB2_19
.LBB2_22:
v_lshl_add_u32 v0, v0, 2, 0
ds_load_b32 v4, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9phase_twoPiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9phase_twoPiiiii, .Lfunc_end2-_Z9phase_twoPiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11phase_threePiiiii
.globl _Z11phase_threePiiiii
.p2align 8
.type _Z11phase_threePiiiii,@function
_Z11phase_threePiiiii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v5, v0, 10, 10
v_mov_b32_e32 v9, 0x3b9aca00
v_mov_b32_e32 v7, 0x3b9aca00
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s7
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_addc_u32 s0, s14, 0
s_cmp_ge_i32 s15, s7
s_cselect_b32 s1, -1, 0
s_cmp_lg_u32 s1, 0
s_addc_u32 s1, s15, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s1, s6, v[5:6]
v_and_b32_e32 v2, 0x3ff, v0
v_mad_u64_u32 v[3:4], null, s0, s6, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, v1, s2
v_cmp_gt_i32_e64 s0, s3, v1
v_cmp_gt_i32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, v8, v3
s_and_b32 s1, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_and_saveexec_b32 s8, s1
s_cbranch_execz .LBB3_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_co_u32 v9, s1, s4, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s1, s5, v10, s1
global_load_b32 v9, v[9:10], off
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s8
v_mul_lo_u32 v6, v5, s6
s_mul_i32 s8, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, s8, v2
v_cmp_gt_i32_e64 s1, s3, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v6, v2
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v11, v4, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v11, v9
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB3_4
v_add_nc_u32_e32 v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s0, s4, v7
v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
global_load_b32 v7, v[7:8], off
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v5, 0x3b9aca00 :: v_dual_add_nc_u32 v8, s8, v5
s_mul_i32 s7, s6, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s0, s7, 2
s_add_i32 s1, s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s0, s3, v8
v_lshl_add_u32 v9, v4, 2, s1
s_and_b32 s3, s0, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v9, v7
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB3_6
v_mad_u64_u32 v[9:10], null, v8, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[7:8], off
.LBB3_6:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s0, s7, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s0, s1, s0
s_cmp_lt_i32 s6, 1
v_lshl_add_u32 v3, v4, 2, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_11
v_lshl_add_u32 v2, v2, 2, s0
v_lshl_add_u32 v3, v6, 2, s1
v_lshl_add_u32 v5, v4, 2, 0
s_lshl_b32 s0, s6, 2
s_branch .LBB3_9
.p2align 6
.LBB3_8:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, s0, v2
v_add_nc_u32_e32 v3, 4, v3
s_add_i32 s6, s6, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB3_11
.LBB3_9:
ds_load_b32 v6, v3
ds_load_b32 v7, v2
ds_load_b32 v8, v5
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v6, v7, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v6, v8
s_cbranch_execz .LBB3_8
ds_store_b32 v5, v6
s_branch .LBB3_8
.LBB3_11:
v_lshl_add_u32 v2, v4, 2, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
ds_load_b32 v2, v2
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11phase_threePiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11phase_threePiiiii, .Lfunc_end3-_Z11phase_threePiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8init_gpui
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8init_gpui.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9phase_onePiiiii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9phase_onePiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9phase_twoPiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9phase_twoPiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11phase_threePiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11phase_threePiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <string>
#include <sstream>
#include <fstream>
#include <algorithm>
#include <chrono>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
//#define _DEBUG_
//#define _TIME_MEASURE_
#ifdef _DEBUG_
#include <string>
#include <sstream>
int __print_step = 0;
void __pt_log(const char *h_, const char *f_, ...){
std::stringstream ss;
ss << h_ << f_ << '\n';
std::string format = ss.str();
va_list va;
va_start(va, f_);
vprintf(format.c_str(), va);
va_end(va);
__print_step++;
}
#define VA_ARGS(...) , ##__VA_ARGS__
#define LOG(f_, ...) __pt_log(\
"[LOG] Step %3d: ", (f_), \
__print_step VA_ARGS(__VA_ARGS__))
#else
#define LOG(f_, ...)
#endif
#define INF 1000000000
#define CEIL(a, b) (( (a) - 1 ) / (b) + 1 )
int **Dist;
int *data;
int block_size;
int vert, edge;
int vert2;
inline void init(){
vert2 = vert*vert;
Dist = new int*[vert];
data = new int[vert2];
std::fill(data, data + vert2, INF);
for(int i=0;i<vert;++i){
Dist[i] = data + i*vert;
Dist[i][i] = 0;
}
if(vert < block_size){
block_size = vert;
}
}
inline void finalize(){
delete[] Dist;
delete[] data;
}
void dump_from_file_and_init(const char *file){
std::ifstream fin(file);
std::stringstream ss;
ss << fin.rdbuf();
ss >> vert >> edge;
LOG("vert: %d, edge: %d", vert, edge);
init();
int i, j, w;
while(--edge >=0){
ss >> i >> j >> w;
Dist[i][j] = w;
}
fin.close();
}
void dump_to_file(const char *file){
std::ofstream fout(file);
fout.write((char*)data, sizeof(int)*vert2);
fout.close();
}
__global__ void init_gpu(int reps){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx >= reps) return;
}
__global__ void phase_one(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int c = block_size * round + ty;
const int r = block_size * round + tx;
const int cell = c*width+r;
const int s_cell = ty*block_size+tx;
if(c >= vert || r >= vert){
s[s_cell] = INF;
}else{
s[s_cell] = dist[cell];
}
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
// min(dist[ty][tx], dist[ty][i] + dist[i][tx])
n = s[ty*block_size+k] + s[k*block_size+tx];
if(n < s[s_cell]){
s[s_cell] = n;
}
__syncthreads();
}
dist[cell] = s[s_cell];
}
__global__ void phase_two(int32_t* const dist, int block_size, int round, int width, int vert){
extern __shared__ int s2[];
int* const s_m = s2; //main(block)
int* const s_c = s2 + block_size*block_size; //center(pivot)
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
int mc, mr; //main
int cc, cr; //center(pivot)
if(bx >= round)++bx; //shift
if(by == 0){ //horizontal
mc = block_size * round + ty;
mr = block_size * bx + tx;
cc = mc;
cr = block_size * round + tx;
}else{ //vertical
mc = block_size * bx + ty;
mr = block_size * round + tx;
cc = block_size * round + ty;
cr = mr;
}
int m_cell = mc * width + mr;
int c_cell = cc * width + cr;
int s_cell = ty * block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(cc >= vert || cr >= vert) s_c[s_cell] = INF;
else s_c[s_cell] = dist[c_cell];
__syncthreads();
int n, k;
if(by == 0){
for(k=0;k<block_size;++k){
n = s_c[ty*block_size+k] + s_m[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}else{
for(k=0;k<block_size;++k){
n = s_m[ty*block_size+k] + s_c[k*block_size+tx];
if(n < s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
}
dist[m_cell] = s_m[s_cell];
}
__global__ void phase_three(int32_t* const dist, int block_size, int round, int width, int vert){
int bs2 = block_size*block_size;
extern __shared__ int s3[];
int* const s_m = s3;
int* const s_l = s3 + bs2;
int* const s_r = s_l + bs2;
const int tx = threadIdx.x;
const int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= round)++bx; //shift x
if(by >= round)++by; //shift y
const int mc = block_size * by + ty;
const int mr = block_size * bx + tx;
const int lc = mc;
const int lr = block_size * round + tx;
const int rc = block_size * round + ty;
const int rr = mr;
const int m_cell = mc*width + mr;
const int l_cell = lc*width + lr;
const int r_cell = rc*width + rr;
const int s_cell = ty*block_size + tx;
if(mc >= vert || mr >= vert) s_m[s_cell] = INF;
else s_m[s_cell] = dist[m_cell];
if(lc >= vert || lr >= vert) s_l[s_cell] = INF;
else s_l[s_cell] = dist[l_cell];
if(rc >= vert || rr >= vert) s_r[s_cell] = INF;
else s_r[s_cell] = dist[r_cell];
__syncthreads();
int n, k;
for(k=0;k<block_size;++k){
n = s_l[ty*block_size+k] + s_r[k*block_size+tx];
if(n<s_m[s_cell]){
s_m[s_cell] = n;
}
__syncthreads();
}
dist[m_cell] = s_m[s_cell];
}
extern __shared__ int S[];
void block_FW(){
#ifdef _TIME_MEASURE_
auto start = std::chrono::high_resolution_clock::now();
#endif
hipStream_t init_stream;
hipStreamCreate(&init_stream);
int Round = CEIL(vert, block_size);
int padded_size = Round * block_size;
size_t vert_w_bytes = vert * sizeof(int);
size_t padded_w_bytes = padded_size * sizeof(int);
int32_t *device_ptr;
//size_t pitch;
dim3 p2b(Round-1, 2, 1); //phase 2 block
dim3 p3b(Round-1, Round-1, 1); //phase 3 block
dim3 dimt(block_size, block_size, 1); //thread
//cudaMallocPitch(&device_ptr, &pitch, vert_byte, vert_byte, vert);
hipMalloc(&device_ptr, padded_w_bytes * padded_size);
//size_t pitch_int = pitch / sizeof(int);
//LOG("pitch => %zu bytes (%zu words)", pitch, pitch_int);
LOG("the number of blocks: %d", Round);
init_gpu<<< 1, dimt >>>(32);
//dst_ptr, dst_pitch, src, src_pitch, w, h, kind
hipMemcpy2DAsync(device_ptr, padded_w_bytes, data, vert_w_bytes,
vert_w_bytes, vert, hipMemcpyHostToDevice, init_stream);
size_t bs2b3 = block_size * block_size * sizeof(int) * 3;
hipDeviceSynchronize();
for(int r=0; r < Round; ++r){
LOG("Round %d/%d", r+1, Round);
phase_one<<< 1 , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_two<<< p2b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
phase_three<<< p3b , dimt , bs2b3 >>>(device_ptr, block_size, r, padded_size, vert);
}
hipMemcpy2D(data, vert_w_bytes, device_ptr, padded_w_bytes,
vert_w_bytes, vert, hipMemcpyDeviceToHost);
hipFree(device_ptr);
hipStreamDestroy(init_stream);
#ifdef _TIME_MEASURE_
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> diff = end - start;
double elapsed_time = diff.count() * 1000;
printf("Total time: %f ms (%f GFLOPS)\n", elapsed_time, 2*vert*vert*vert / (elapsed_time * 1e6));
#endif
}
int main(int argc, char **argv){
dump_from_file_and_init(argv[1]);
block_size = std::atoi(argv[3]);
block_FW();
dump_to_file(argv[2]);
finalize();
return 0;
} | .text
.file "HW4_cuda_002_wake.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23dump_from_file_and_initPKc # -- Begin function _Z23dump_from_file_and_initPKc
.p2align 4, 0x90
.type _Z23dump_from_file_and_initPKc,@function
_Z23dump_from_file_and_initPKc: # @_Z23dump_from_file_and_initPKc
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 992
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rsi
leaq 416(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
leaq 24(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1Ev
.Ltmp1:
# %bb.1:
leaq 40(%rsp), %rdi
leaq 432(%rsp), %rbx
.Ltmp3:
movq %rbx, %rsi
callq _ZNSolsEPSt15basic_streambufIcSt11char_traitsIcEE
.Ltmp4:
# %bb.2:
.Ltmp5:
leaq 24(%rsp), %rdi
movl $vert, %esi
callq _ZNSirsERi
.Ltmp6:
# %bb.3:
.Ltmp7:
movl $edge, %esi
movq %rax, %rdi
callq _ZNSirsERi
.Ltmp8:
# %bb.4:
movslq vert(%rip), %r15
movl %r15d, %ebp
imull %r15d, %ebp
leaq (,%r15,8), %rax
testq %r15, %r15
movl %ebp, vert2(%rip)
movq $-1, %rdi
cmovnsq %rax, %rdi
.Ltmp9:
callq _Znam
.Ltmp10:
# %bb.5: # %.noexc
movq %rax, Dist(%rip)
movl %ebp, %r14d
shlq $2, %r14
.Ltmp11:
movq %r14, %rdi
callq _Znam
.Ltmp12:
# %bb.6: # %.noexc6
movq %rax, data(%rip)
testl %r15d, %r15d
je .LBB0_9
# %bb.7: # %.lr.ph.i.i.i.i.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_8: # %.lr.ph.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1000000000, (%rax,%rcx) # imm = 0x3B9ACA00
addq $4, %rcx
cmpq %rcx, %r14
jne .LBB0_8
.LBB0_9: # %_ZSt4fillIPiiEvT_S1_RKT0_.exit.i
testl %r15d, %r15d
jle .LBB0_12
# %bb.10: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imull %r15d, %ecx
movslq %ecx, %rcx
shlq $2, %rcx
addq data(%rip), %rcx
movq Dist(%rip), %rdx
movq %rcx, (%rdx,%rax,8)
movq Dist(%rip), %rcx
movq (%rcx,%rax,8), %rcx
movl $0, (%rcx,%rax,4)
incq %rax
movslq vert(%rip), %r15
cmpq %r15, %rax
jl .LBB0_11
.LBB0_12: # %._crit_edge.i
cmpl block_size(%rip), %r15d
jge .LBB0_14
# %bb.13:
movl %r15d, block_size(%rip)
.LBB0_14: # %_Z4initv.exit
movl edge(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, edge(%rip)
testl %eax, %eax
jle .LBB0_20
# %bb.15: # %.lr.ph.preheader
leaq 24(%rsp), %r14
leaq 20(%rsp), %r15
leaq 16(%rsp), %r12
leaq 12(%rsp), %r13
.p2align 4, 0x90
.LBB0_16: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp14:
movq %r14, %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp15:
# %bb.17: # in Loop: Header=BB0_16 Depth=1
.Ltmp16:
movq %rax, %rdi
movq %r12, %rsi
callq _ZNSirsERi
.Ltmp17:
# %bb.18: # in Loop: Header=BB0_16 Depth=1
.Ltmp18:
movq %rax, %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp19:
# %bb.19: # in Loop: Header=BB0_16 Depth=1
movl 12(%rsp), %eax
movq Dist(%rip), %rcx
movslq 20(%rsp), %rdx
movq (%rcx,%rdx,8), %rcx
movslq 16(%rsp), %rdx
movl %eax, (%rcx,%rdx,4)
movl edge(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, edge(%rip)
testl %eax, %eax
jg .LBB0_16
.LBB0_20: # %._crit_edge
.Ltmp21:
movq %rbx, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp22:
# %bb.21: # %.noexc7
testq %rax, %rax
jne .LBB0_23
# %bb.22:
movq 416(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $416, %rdi # imm = 0x1A0
movl 448(%rsp,%rax), %esi
orl $4, %esi
.Ltmp23:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp24:
.LBB0_23: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 24(%rsp)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+64(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 24(%rsp,%rax)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+72(%rip), %rax
movq %rax, 40(%rsp)
movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 48(%rsp)
movq 120(%rsp), %rdi
leaq 136(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_25
# %bb.24: # %.critedge.i.i.i.i.i
callq _ZdlPv
.LBB0_25: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev.exit
movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 48(%rsp)
leaq 104(%rsp), %rdi
callq _ZNSt6localeD1Ev
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rax
movq %rax, 24(%rsp)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 24(%rsp,%rax)
movq $0, 32(%rsp)
leaq 152(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
leaq 416(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 672(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_26:
.cfi_def_cfa_offset 992
.Ltmp2:
movq %rax, %rbx
jmp .LBB0_31
.LBB0_28: # %.loopexit.split-lp
.Ltmp25:
jmp .LBB0_30
.LBB0_29:
.Ltmp13:
jmp .LBB0_30
.LBB0_27: # %.loopexit
.Ltmp20:
.LBB0_30:
movq %rax, %rbx
leaq 24(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev
.LBB0_31:
leaq 416(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 672(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z23dump_from_file_and_initPKc, .Lfunc_end0-_Z23dump_from_file_and_initPKc
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp19-.Ltmp14 # Call between .Ltmp14 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp24-.Ltmp21 # Call between .Ltmp21 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp24 # Call between .Ltmp24 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z12dump_to_filePKc # -- Begin function _Z12dump_to_filePKc
.p2align 4, 0x90
.type _Z12dump_to_filePKc,@function
_Z12dump_to_filePKc: # @_Z12dump_to_filePKc
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $512, %rsp # imm = 0x200
.cfi_def_cfa_offset 528
.cfi_offset %rbx, -16
movq %rdi, %rsi
movq %rsp, %rbx
movq %rbx, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq data(%rip), %rsi
movslq vert2(%rip), %rdx
shlq $2, %rdx
.Ltmp26:
movq %rbx, %rdi
callq _ZNSo5writeEPKcl
.Ltmp27:
# %bb.1:
leaq 8(%rsp), %rdi
.Ltmp28:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp29:
# %bb.2: # %.noexc
testq %rax, %rax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rsp,%rax), %esi
orl $4, %esi
.Ltmp30:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp31:
.LBB1_4: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq %rsp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
addq $512, %rsp # imm = 0x200
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 528
.Ltmp32:
movq %rax, %rbx
movq %rsp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z12dump_to_filePKc, .Lfunc_end1-_Z12dump_to_filePKc
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp26-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp26
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp31-.Ltmp26 # Call between .Ltmp26 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin1 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Lfunc_end1-.Ltmp31 # Call between .Ltmp31 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl _Z23__device_stub__init_gpui # -- Begin function _Z23__device_stub__init_gpui
.p2align 4, 0x90
.type _Z23__device_stub__init_gpui,@function
_Z23__device_stub__init_gpui: # @_Z23__device_stub__init_gpui
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8init_gpui, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z23__device_stub__init_gpui, .Lfunc_end2-_Z23__device_stub__init_gpui
.cfi_endproc
# -- End function
.globl _Z24__device_stub__phase_onePiiiii # -- Begin function _Z24__device_stub__phase_onePiiiii
.p2align 4, 0x90
.type _Z24__device_stub__phase_onePiiiii,@function
_Z24__device_stub__phase_onePiiiii: # @_Z24__device_stub__phase_onePiiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9phase_onePiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z24__device_stub__phase_onePiiiii, .Lfunc_end3-_Z24__device_stub__phase_onePiiiii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__phase_twoPiiiii # -- Begin function _Z24__device_stub__phase_twoPiiiii
.p2align 4, 0x90
.type _Z24__device_stub__phase_twoPiiiii,@function
_Z24__device_stub__phase_twoPiiiii: # @_Z24__device_stub__phase_twoPiiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9phase_twoPiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z24__device_stub__phase_twoPiiiii, .Lfunc_end4-_Z24__device_stub__phase_twoPiiiii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__phase_threePiiiii # -- Begin function _Z26__device_stub__phase_threePiiiii
.p2align 4, 0x90
.type _Z26__device_stub__phase_threePiiiii,@function
_Z26__device_stub__phase_threePiiiii: # @_Z26__device_stub__phase_threePiiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11phase_threePiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z26__device_stub__phase_threePiiiii, .Lfunc_end5-_Z26__device_stub__phase_threePiiiii
.cfi_endproc
# -- End function
.globl _Z8block_FWv # -- Begin function _Z8block_FWv
.p2align 4, 0x90
.type _Z8block_FWv,@function
_Z8block_FWv: # @_Z8block_FWv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r13 # imm = 0x100000001
leaq 128(%rsp), %rdi
callq hipStreamCreate
movslq vert(%rip), %rbx
leal -1(%rbx), %eax
movl block_size(%rip), %ecx
cltd
idivl %ecx
movl %eax, %r15d
leal 1(%r15), %r14d
movl %r14d, 124(%rsp) # 4-byte Spill
imull %ecx, %r14d
shlq $2, %rbx
movslq %r14d, %rsi
leaq (,%rsi,4), %rbp
movq %rcx, %r12
shlq $32, %r12
orq %rcx, %r12
imulq %rbp, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
leaq 24(%rsp), %rax
movl $32, 24(%rsp)
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8init_gpui, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 72(%rsp), %rdi
movq data(%rip), %rdx
movslq vert(%rip), %r9
movq %rbp, 136(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %rbx, %rcx
movq %rbx, 144(%rsp) # 8-byte Spill
movq %rbx, %r8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq hipMemcpy2DAsync
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl block_size(%rip), %ebx
callq hipDeviceSynchronize
testl %r15d, %r15d
js .LBB6_11
# %bb.3: # %.lr.ph
movabsq $8589934592, %r13 # imm = 0x200000000
movq %r15, %rbp
shlq $32, %rbp
orq %r15, %r13
orq %r15, %rbp
imull %ebx, %ebx
shlq $2, %rbx
leaq (%rbx,%rbx,2), %r15
xorl %ebx, %ebx
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_10: # in Loop: Header=BB6_4 Depth=1
incl %ebx
cmpl %ebx, 124(%rsp) # 4-byte Folded Reload
je .LBB6_11
.LBB6_4: # =>This Inner Loop Header: Depth=1
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5: # in Loop: Header=BB6_4 Depth=1
movq 72(%rsp), %rax
movl block_size(%rip), %ecx
movl vert(%rip), %edx
movq %rax, 48(%rsp)
movl %ecx, 12(%rsp)
movl %ebx, 8(%rsp)
movl %r14d, 4(%rsp)
movl %edx, (%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z9phase_onePiiiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6: # in Loop: Header=BB6_4 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_8
# %bb.7: # in Loop: Header=BB6_4 Depth=1
movq 72(%rsp), %rax
movl block_size(%rip), %ecx
movl vert(%rip), %edx
movq %rax, 48(%rsp)
movl %ecx, 12(%rsp)
movl %ebx, 8(%rsp)
movl %r14d, 4(%rsp)
movl %edx, (%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z9phase_twoPiiiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_8: # in Loop: Header=BB6_4 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_10
# %bb.9: # in Loop: Header=BB6_4 Depth=1
movq 72(%rsp), %rax
movl block_size(%rip), %ecx
movl vert(%rip), %edx
movq %rax, 48(%rsp)
movl %ecx, 12(%rsp)
movl %ebx, 8(%rsp)
movl %r14d, 4(%rsp)
movl %edx, (%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z11phase_threePiiiii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_10
.LBB6_11: # %._crit_edge
movq data(%rip), %rdi
movq 72(%rsp), %rdx
movslq vert(%rip), %r9
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq 152(%rsp), %rsi # 8-byte Reload
movq 144(%rsp), %rcx # 8-byte Reload
movq %rsi, %r8
pushq $2
.cfi_adjust_cfa_offset 8
callq hipMemcpy2D
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq 72(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipStreamDestroy
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8block_FWv, .Lfunc_end6-_Z8block_FWv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
callq _Z23dump_from_file_and_initPKc
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, block_size(%rip)
callq _Z8block_FWv
movq 16(%rbx), %rdi
callq _Z12dump_to_filePKc
movq Dist(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
callq _ZdaPv
.LBB7_2:
movq data(%rip), %rdi
testq %rdi, %rdi
je .LBB7_4
# %bb.3:
callq _ZdaPv
.LBB7_4: # %_Z8finalizev.exit
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8init_gpui, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9phase_onePiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9phase_twoPiiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11phase_threePiiiii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type Dist,@object # @Dist
.bss
.globl Dist
.p2align 3, 0x0
Dist:
.quad 0
.size Dist, 8
.type data,@object # @data
.globl data
.p2align 3, 0x0
data:
.quad 0
.size data, 8
.type block_size,@object # @block_size
.globl block_size
.p2align 2, 0x0
block_size:
.long 0 # 0x0
.size block_size, 4
.type vert,@object # @vert
.globl vert
.p2align 2, 0x0
vert:
.long 0 # 0x0
.size vert, 4
.type edge,@object # @edge
.globl edge
.p2align 2, 0x0
edge:
.long 0 # 0x0
.size edge, 4
.type vert2,@object # @vert2
.globl vert2
.p2align 2, 0x0
vert2:
.long 0 # 0x0
.size vert2, 4
.type _Z8init_gpui,@object # @_Z8init_gpui
.section .rodata,"a",@progbits
.globl _Z8init_gpui
.p2align 3, 0x0
_Z8init_gpui:
.quad _Z23__device_stub__init_gpui
.size _Z8init_gpui, 8
.type _Z9phase_onePiiiii,@object # @_Z9phase_onePiiiii
.globl _Z9phase_onePiiiii
.p2align 3, 0x0
_Z9phase_onePiiiii:
.quad _Z24__device_stub__phase_onePiiiii
.size _Z9phase_onePiiiii, 8
.type _Z9phase_twoPiiiii,@object # @_Z9phase_twoPiiiii
.globl _Z9phase_twoPiiiii
.p2align 3, 0x0
_Z9phase_twoPiiiii:
.quad _Z24__device_stub__phase_twoPiiiii
.size _Z9phase_twoPiiiii, 8
.type _Z11phase_threePiiiii,@object # @_Z11phase_threePiiiii
.globl _Z11phase_threePiiiii
.p2align 3, 0x0
_Z11phase_threePiiiii:
.quad _Z26__device_stub__phase_threePiiiii
.size _Z11phase_threePiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8init_gpui"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9phase_onePiiiii"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9phase_twoPiiiii"
.size .L__unnamed_3, 19
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11phase_threePiiiii"
.size .L__unnamed_4, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z23__device_stub__init_gpui
.addrsig_sym _Z24__device_stub__phase_onePiiiii
.addrsig_sym _Z24__device_stub__phase_twoPiiiii
.addrsig_sym _Z26__device_stub__phase_threePiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym vert
.addrsig_sym edge
.addrsig_sym _Z8init_gpui
.addrsig_sym _Z9phase_onePiiiii
.addrsig_sym _Z9phase_twoPiiiii
.addrsig_sym _Z11phase_threePiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void matrix_product(int *g_A, int *g_B, int *g_C) {
int gx = threadIdx.x + blockIdx.x * 32;
int gy = threadIdx.y + blockIdx.y * 32;
int c = 0;
int k;
for (k = 0; k < N; k++) {
c += g_A[k + gy*N] * g_B[gx + k*N];
}
g_C[gx + gy*N] = c;
}
int main() {
int i;
int *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = (int*)malloc(sizeof(int)*N*N);
h_B = (int*)malloc(sizeof(int)*N*N);
h_C = (int*)malloc(sizeof(int)*N*N);
cudaMalloc(&d_A, sizeof(int)*N*N);
cudaMalloc(&d_B, sizeof(int)*N*N);
cudaMalloc(&d_C, sizeof(int)*N*N);
for (i = 0; i < N*N; i++) {
h_A[i] = h_B[i] = 1;
}
cudaMemcpy(d_A, h_A, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemset(d_C, 0, sizeof(int)*N*N);
dim3 grid(32, 32);
dim3 block(32, 32);
matrix_product<<< grid, block >>> (d_A, d_B, d_C);
cudaMemcpy(h_C, d_C, sizeof(int)*N*N, cudaMemcpyDeviceToHost);
int flag = 0;
for(int y=0; y<N; y++){
for(int x=0; x<N; x++){
int c = 0;
for(int k=0; k<N; k++){
c += h_A[y*N + k] * h_B[k*N + x];
}
if(h_C[y*N + x] != c){
flag = 1;
}
}
}
if(flag==0)
printf("OK\n");
else
printf("NG\n");
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | code for sm_80
Function : _Z14matrix_productPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0060*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0090*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R7, R7, R2, 0x5 ; /* 0x0000000207077211 */
/* 0x001fc800078e28ff */
/*00b0*/ SHF.L.U32 R8, R7, 0xa, RZ ; /* 0x0000000a07087819 */
/* 0x000fe400000006ff */
/*00c0*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x002fe400078e28ff */
/*00d0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe40008000f00 */
/*00e0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe40008000f00 */
/*00f0*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe40008000f00 */
/*0100*/ MOV R3, UR9 ; /* 0x0000000900037c02 */
/* 0x000fe20008000f00 */
/*0110*/ IMAD.WIDE R4, R8, 0x4, R4 ; /* 0x0000000408047825 */
/* 0x000fc800078e0204 */
/*0120*/ IMAD.WIDE R2, R0, 0x4, R2 ; /* 0x0000000400027825 */
/* 0x000fe200078e0202 */
/*0130*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R18, [R2.64+0x1000] ; /* 0x0010000402127981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R19, [R2.64+0x2000] ; /* 0x0020000402137981 */
/* 0x000f28000c1e1900 */
/*0180*/ LDG.E R20, [R4.64+0x8] ; /* 0x0000080404147981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R22, [R2.64+0x3000] ; /* 0x0030000402167981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0404157981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R23, [R2.64+0x4000] ; /* 0x0040000402177981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100404187981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R9, [R2.64+0x5000] ; /* 0x0050000402097981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R11, [R2.64+0x6000] ; /* 0x00600004020b7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R2.64+0x7000] ; /* 0x00700004020d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R28, [R4.64+0x38] ; /* 0x00003804041c7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R26, [R2.64+0xf000] ; /* 0x00f00004021a7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R27, [R4.64+0x3c] ; /* 0x00003c04041b7981 */
/* 0x000f62000c1e1900 */
/*0260*/ IMAD R17, R16, R17, R15 ; /* 0x0000001110117224 */
/* 0x004fc600078e020f */
/*0270*/ LDG.E R15, [R2.64+0x8000] ; /* 0x00800004020f7981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD R25, R18, R25, R17 ; /* 0x0000001912197224 */
/* 0x008fc600078e0211 */
/*02a0*/ LDG.E R17, [R2.64+0x9000] ; /* 0x0090000402117981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x010fc600078e0219 */
/*02d0*/ LDG.E R19, [R2.64+0xa000] ; /* 0x00a0000402137981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R4.64+0x28] ; /* 0x0000280404147981 */
/* 0x000f22000c1e1900 */
/*02f0*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0300*/ LDG.E R21, [R2.64+0xb000] ; /* 0x00b0000402157981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R22, [R4.64+0x2c] ; /* 0x00002c0404167981 */
/* 0x000f62000c1e1900 */
/*0320*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x000fc600078e0219 */
/*0330*/ LDG.E R23, [R2.64+0xc000] ; /* 0x00c0000402177981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R24, [R4.64+0x30] ; /* 0x0000300404187981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD R29, R9, R10, R25 ; /* 0x0000000a091d7224 */
/* 0x000fc600078e0219 */
/*0360*/ LDG.E R10, [R2.64+0xd000] ; /* 0x00d00004020a7981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R25, [R4.64+0x34] ; /* 0x0000340404197981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R9, [R2.64+0xe000] ; /* 0x00e0000402097981 */
/* 0x000f62000c1e1900 */
/*0390*/ IMAD R11, R11, R12, R29 ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e021d */
/*03a0*/ IMAD R11, R13, R14, R11 ; /* 0x0000000e0d0b7224 */
/* 0x000fe200078e020b */
/*03b0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R6, 0x400, PT ; /* 0x000004000600780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR8, UP0, UR8, 0x10000, URZ ; /* 0x0001000008087890 */
/* 0x000fe4000ff1e03f */
/*03e0*/ UIADD3 UR6, UP1, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe4000ff3e03f */
/*03f0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0400*/ UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ; /* 0x000000073f077290 */
/* 0x000fe20008ffe43f */
/*0410*/ IMAD R11, R15, R16, R11 ; /* 0x000000100f0b7224 */
/* 0x004fc800078e020b */
/*0420*/ IMAD R11, R17, R18, R11 ; /* 0x00000012110b7224 */
/* 0x008fc800078e020b */
/*0430*/ IMAD R11, R19, R20, R11 ; /* 0x00000014130b7224 */
/* 0x010fc800078e020b */
/*0440*/ IMAD R11, R21, R22, R11 ; /* 0x00000016150b7224 */
/* 0x020fc800078e020b */
/*0450*/ IMAD R11, R23, R24, R11 ; /* 0x00000018170b7224 */
/* 0x000fc800078e020b */
/*0460*/ IMAD R10, R10, R25, R11 ; /* 0x000000190a0a7224 */
/* 0x000fc800078e020b */
/*0470*/ IMAD R9, R9, R28, R10 ; /* 0x0000001c09097224 */
/* 0x000fc800078e020a */
/*0480*/ IMAD R15, R26, R27, R9 ; /* 0x0000001b1a0f7224 */
/* 0x000fe200078e0209 */
/*0490*/ @P0 BRA 0xd0 ; /* 0xfffffc3000000947 */
/* 0x000fea000383ffff */
/*04a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04b0*/ LEA R2, R7, R0, 0xa ; /* 0x0000000007027211 */
/* 0x000fd200078e50ff */
/*04c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void matrix_product(int *g_A, int *g_B, int *g_C) {
int gx = threadIdx.x + blockIdx.x * 32;
int gy = threadIdx.y + blockIdx.y * 32;
int c = 0;
int k;
for (k = 0; k < N; k++) {
c += g_A[k + gy*N] * g_B[gx + k*N];
}
g_C[gx + gy*N] = c;
}
int main() {
int i;
int *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = (int*)malloc(sizeof(int)*N*N);
h_B = (int*)malloc(sizeof(int)*N*N);
h_C = (int*)malloc(sizeof(int)*N*N);
cudaMalloc(&d_A, sizeof(int)*N*N);
cudaMalloc(&d_B, sizeof(int)*N*N);
cudaMalloc(&d_C, sizeof(int)*N*N);
for (i = 0; i < N*N; i++) {
h_A[i] = h_B[i] = 1;
}
cudaMemcpy(d_A, h_A, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemset(d_C, 0, sizeof(int)*N*N);
dim3 grid(32, 32);
dim3 block(32, 32);
matrix_product<<< grid, block >>> (d_A, d_B, d_C);
cudaMemcpy(h_C, d_C, sizeof(int)*N*N, cudaMemcpyDeviceToHost);
int flag = 0;
for(int y=0; y<N; y++){
for(int x=0; x<N; x++){
int c = 0;
for(int k=0; k<N; k++){
c += h_A[y*N + k] * h_B[k*N + x];
}
if(h_C[y*N + x] != c){
flag = 1;
}
}
}
if(flag==0)
printf("OK\n");
else
printf("NG\n");
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | .file "tmpxft_00143726_00000000-6_matrix_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
.type _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_, @function
_Z38__device_stub__Z14matrix_productPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrix_productPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_, .-_Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
.globl _Z14matrix_productPiS_S_
.type _Z14matrix_productPiS_S_, @function
_Z14matrix_productPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14matrix_productPiS_S_, .-_Z14matrix_productPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "OK\n"
.LC1:
.string "NG\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl $1, (%rbx,%rax)
movl $1, 0(%rbp,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L13:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %r14d
movl $0, %r9d
movl $1, %r11d
.L14:
leaq 4194304(%rbx), %rdi
movq %r14, %r10
salq $12, %r10
leaq 0(%rbp,%r10), %r13
addq %r12, %r10
movl $0, %r8d
.L19:
leaq -4194304(%rdi), %rax
movq %r13, %rcx
movl $0, %esi
.L15:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $4096, %rax
cmpq %rdi, %rax
jne .L15
cmpl %esi, (%r10,%r8,4)
cmovne %r11d, %r9d
addq $1, %r8
addq $4, %rdi
cmpq $1024, %r8
jne .L19
addq $1, %r14
cmpq $1024, %r14
jne .L14
testl %r9d, %r9d
jne .L20
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
jmp .L13
.L20:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14matrix_productPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrix_productPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void matrix_product(int *g_A, int *g_B, int *g_C) {
int gx = threadIdx.x + blockIdx.x * 32;
int gy = threadIdx.y + blockIdx.y * 32;
int c = 0;
int k;
for (k = 0; k < N; k++) {
c += g_A[k + gy*N] * g_B[gx + k*N];
}
g_C[gx + gy*N] = c;
}
int main() {
int i;
int *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = (int*)malloc(sizeof(int)*N*N);
h_B = (int*)malloc(sizeof(int)*N*N);
h_C = (int*)malloc(sizeof(int)*N*N);
cudaMalloc(&d_A, sizeof(int)*N*N);
cudaMalloc(&d_B, sizeof(int)*N*N);
cudaMalloc(&d_C, sizeof(int)*N*N);
for (i = 0; i < N*N; i++) {
h_A[i] = h_B[i] = 1;
}
cudaMemcpy(d_A, h_A, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizeof(int)*N*N, cudaMemcpyHostToDevice);
cudaMemset(d_C, 0, sizeof(int)*N*N);
dim3 grid(32, 32);
dim3 block(32, 32);
matrix_product<<< grid, block >>> (d_A, d_B, d_C);
cudaMemcpy(h_C, d_C, sizeof(int)*N*N, cudaMemcpyDeviceToHost);
int flag = 0;
for(int y=0; y<N; y++){
for(int x=0; x<N; x++){
int c = 0;
for(int k=0; k<N; k++){
c += h_A[y*N + k] * h_B[k*N + x];
}
if(h_C[y*N + x] != c){
flag = 1;
}
}
}
if(flag==0)
printf("OK\n");
else
printf("NG\n");
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void matrix_product(int *g_A, int *g_B, int *g_C) {
int gx = threadIdx.x + blockIdx.x * 32;
int gy = threadIdx.y + blockIdx.y * 32;
int c = 0;
int k;
for (k = 0; k < N; k++) {
c += g_A[k + gy*N] * g_B[gx + k*N];
}
g_C[gx + gy*N] = c;
}
int main() {
int i;
int *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = (int*)malloc(sizeof(int)*N*N);
h_B = (int*)malloc(sizeof(int)*N*N);
h_C = (int*)malloc(sizeof(int)*N*N);
hipMalloc(&d_A, sizeof(int)*N*N);
hipMalloc(&d_B, sizeof(int)*N*N);
hipMalloc(&d_C, sizeof(int)*N*N);
for (i = 0; i < N*N; i++) {
h_A[i] = h_B[i] = 1;
}
hipMemcpy(d_A, h_A, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemset(d_C, 0, sizeof(int)*N*N);
dim3 grid(32, 32);
dim3 block(32, 32);
matrix_product<<< grid, block >>> (d_A, d_B, d_C);
hipMemcpy(h_C, d_C, sizeof(int)*N*N, hipMemcpyDeviceToHost);
int flag = 0;
for(int y=0; y<N; y++){
for(int x=0; x<N; x++){
int c = 0;
for(int k=0; k<N; k++){
c += h_A[y*N + k] * h_B[k*N + x];
}
if(h_C[y*N + x] != c){
flag = 1;
}
}
}
if(flag==0)
printf("OK\n");
else
printf("NG\n");
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void matrix_product(int *g_A, int *g_B, int *g_C) {
int gx = threadIdx.x + blockIdx.x * 32;
int gy = threadIdx.y + blockIdx.y * 32;
int c = 0;
int k;
for (k = 0; k < N; k++) {
c += g_A[k + gy*N] * g_B[gx + k*N];
}
g_C[gx + gy*N] = c;
}
int main() {
int i;
int *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = (int*)malloc(sizeof(int)*N*N);
h_B = (int*)malloc(sizeof(int)*N*N);
h_C = (int*)malloc(sizeof(int)*N*N);
hipMalloc(&d_A, sizeof(int)*N*N);
hipMalloc(&d_B, sizeof(int)*N*N);
hipMalloc(&d_C, sizeof(int)*N*N);
for (i = 0; i < N*N; i++) {
h_A[i] = h_B[i] = 1;
}
hipMemcpy(d_A, h_A, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemset(d_C, 0, sizeof(int)*N*N);
dim3 grid(32, 32);
dim3 block(32, 32);
matrix_product<<< grid, block >>> (d_A, d_B, d_C);
hipMemcpy(h_C, d_C, sizeof(int)*N*N, hipMemcpyDeviceToHost);
int flag = 0;
for(int y=0; y<N; y++){
for(int x=0; x<N; x++){
int c = 0;
for(int k=0; k<N; k++){
c += h_A[y*N + k] * h_B[k*N + x];
}
if(h_C[y*N + x] != c){
flag = 1;
}
}
}
if(flag==0)
printf("OK\n");
else
printf("NG\n");
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrix_productPiS_S_
.globl _Z14matrix_productPiS_S_
.p2align 8
.type _Z14matrix_productPiS_S_,@function
_Z14matrix_productPiS_S_:
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 5, v1
v_lshl_add_u32 v6, s14, 5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 10, v5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v1, vcc_lo
v_mov_b32_e32 v0, v6
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v3, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_nc_u32_e32 v0, 0x400, v0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x1000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v1, v[3:4], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v9, v1, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v3
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v5, 10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrix_productPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrix_productPiS_S_, .Lfunc_end0-_Z14matrix_productPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrix_productPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrix_productPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void matrix_product(int *g_A, int *g_B, int *g_C) {
int gx = threadIdx.x + blockIdx.x * 32;
int gy = threadIdx.y + blockIdx.y * 32;
int c = 0;
int k;
for (k = 0; k < N; k++) {
c += g_A[k + gy*N] * g_B[gx + k*N];
}
g_C[gx + gy*N] = c;
}
int main() {
int i;
int *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = (int*)malloc(sizeof(int)*N*N);
h_B = (int*)malloc(sizeof(int)*N*N);
h_C = (int*)malloc(sizeof(int)*N*N);
hipMalloc(&d_A, sizeof(int)*N*N);
hipMalloc(&d_B, sizeof(int)*N*N);
hipMalloc(&d_C, sizeof(int)*N*N);
for (i = 0; i < N*N; i++) {
h_A[i] = h_B[i] = 1;
}
hipMemcpy(d_A, h_A, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizeof(int)*N*N, hipMemcpyHostToDevice);
hipMemset(d_C, 0, sizeof(int)*N*N);
dim3 grid(32, 32);
dim3 block(32, 32);
matrix_product<<< grid, block >>> (d_A, d_B, d_C);
hipMemcpy(h_C, d_C, sizeof(int)*N*N, hipMemcpyDeviceToHost);
int flag = 0;
for(int y=0; y<N; y++){
for(int x=0; x<N; x++){
int c = 0;
for(int k=0; k<N; k++){
c += h_A[y*N + k] * h_B[k*N + x];
}
if(h_C[y*N + x] != c){
flag = 1;
}
}
}
if(flag==0)
printf("OK\n");
else
printf("NG\n");
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} | .text
.file "matrix_product.hip"
.globl _Z29__device_stub__matrix_productPiS_S_ # -- Begin function _Z29__device_stub__matrix_productPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__matrix_productPiS_S_,@function
_Z29__device_stub__matrix_productPiS_S_: # @_Z29__device_stub__matrix_productPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrix_productPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__matrix_productPiS_S_, .Lfunc_end0-_Z29__device_stub__matrix_productPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $1, %ebp
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matrix_productPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader45
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_7 Depth 3
movq %rcx, %rdx
shlq $12, %rdx
addq %r15, %rdx
movq %r14, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_6: # %.preheader
# Parent Loop BB1_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
xorl %r8d, %r8d
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# Parent Loop BB1_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rax,%r8,4), %r11d
addl %r11d, %r10d
incq %r8
addq $4096, %r9 # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB1_7
# %bb.8: # in Loop: Header=BB1_6 Depth=2
cmpl %r10d, (%rdx,%rdi,4)
cmovnel %ebp, %r12d
incq %rdi
addq $4, %rsi
cmpq $1024, %rdi # imm = 0x400
jne .LBB1_6
# %bb.9: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rcx # imm = 0x400
jne .LBB1_5
# %bb.10:
testl %r12d, %r12d
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrix_productPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrix_productPiS_S_,@object # @_Z14matrix_productPiS_S_
.section .rodata,"a",@progbits
.globl _Z14matrix_productPiS_S_
.p2align 3, 0x0
_Z14matrix_productPiS_S_:
.quad _Z29__device_stub__matrix_productPiS_S_
.size _Z14matrix_productPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrix_productPiS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "NG"
.size .Lstr, 3
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OK"
.size .Lstr.1, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrix_productPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrix_productPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14matrix_productPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0060*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0090*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R7, R7, R2, 0x5 ; /* 0x0000000207077211 */
/* 0x001fc800078e28ff */
/*00b0*/ SHF.L.U32 R8, R7, 0xa, RZ ; /* 0x0000000a07087819 */
/* 0x000fe400000006ff */
/*00c0*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x002fe400078e28ff */
/*00d0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe40008000f00 */
/*00e0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe40008000f00 */
/*00f0*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe40008000f00 */
/*0100*/ MOV R3, UR9 ; /* 0x0000000900037c02 */
/* 0x000fe20008000f00 */
/*0110*/ IMAD.WIDE R4, R8, 0x4, R4 ; /* 0x0000000408047825 */
/* 0x000fc800078e0204 */
/*0120*/ IMAD.WIDE R2, R0, 0x4, R2 ; /* 0x0000000400027825 */
/* 0x000fe200078e0202 */
/*0130*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R18, [R2.64+0x1000] ; /* 0x0010000402127981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R19, [R2.64+0x2000] ; /* 0x0020000402137981 */
/* 0x000f28000c1e1900 */
/*0180*/ LDG.E R20, [R4.64+0x8] ; /* 0x0000080404147981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R22, [R2.64+0x3000] ; /* 0x0030000402167981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0404157981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R23, [R2.64+0x4000] ; /* 0x0040000402177981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100404187981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R9, [R2.64+0x5000] ; /* 0x0050000402097981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R11, [R2.64+0x6000] ; /* 0x00600004020b7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R2.64+0x7000] ; /* 0x00700004020d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R28, [R4.64+0x38] ; /* 0x00003804041c7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R26, [R2.64+0xf000] ; /* 0x00f00004021a7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R27, [R4.64+0x3c] ; /* 0x00003c04041b7981 */
/* 0x000f62000c1e1900 */
/*0260*/ IMAD R17, R16, R17, R15 ; /* 0x0000001110117224 */
/* 0x004fc600078e020f */
/*0270*/ LDG.E R15, [R2.64+0x8000] ; /* 0x00800004020f7981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD R25, R18, R25, R17 ; /* 0x0000001912197224 */
/* 0x008fc600078e0211 */
/*02a0*/ LDG.E R17, [R2.64+0x9000] ; /* 0x0090000402117981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x010fc600078e0219 */
/*02d0*/ LDG.E R19, [R2.64+0xa000] ; /* 0x00a0000402137981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R4.64+0x28] ; /* 0x0000280404147981 */
/* 0x000f22000c1e1900 */
/*02f0*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0300*/ LDG.E R21, [R2.64+0xb000] ; /* 0x00b0000402157981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R22, [R4.64+0x2c] ; /* 0x00002c0404167981 */
/* 0x000f62000c1e1900 */
/*0320*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x000fc600078e0219 */
/*0330*/ LDG.E R23, [R2.64+0xc000] ; /* 0x00c0000402177981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R24, [R4.64+0x30] ; /* 0x0000300404187981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD R29, R9, R10, R25 ; /* 0x0000000a091d7224 */
/* 0x000fc600078e0219 */
/*0360*/ LDG.E R10, [R2.64+0xd000] ; /* 0x00d00004020a7981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R25, [R4.64+0x34] ; /* 0x0000340404197981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R9, [R2.64+0xe000] ; /* 0x00e0000402097981 */
/* 0x000f62000c1e1900 */
/*0390*/ IMAD R11, R11, R12, R29 ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e021d */
/*03a0*/ IMAD R11, R13, R14, R11 ; /* 0x0000000e0d0b7224 */
/* 0x000fe200078e020b */
/*03b0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R6, 0x400, PT ; /* 0x000004000600780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR8, UP0, UR8, 0x10000, URZ ; /* 0x0001000008087890 */
/* 0x000fe4000ff1e03f */
/*03e0*/ UIADD3 UR6, UP1, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe4000ff3e03f */
/*03f0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0400*/ UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ; /* 0x000000073f077290 */
/* 0x000fe20008ffe43f */
/*0410*/ IMAD R11, R15, R16, R11 ; /* 0x000000100f0b7224 */
/* 0x004fc800078e020b */
/*0420*/ IMAD R11, R17, R18, R11 ; /* 0x00000012110b7224 */
/* 0x008fc800078e020b */
/*0430*/ IMAD R11, R19, R20, R11 ; /* 0x00000014130b7224 */
/* 0x010fc800078e020b */
/*0440*/ IMAD R11, R21, R22, R11 ; /* 0x00000016150b7224 */
/* 0x020fc800078e020b */
/*0450*/ IMAD R11, R23, R24, R11 ; /* 0x00000018170b7224 */
/* 0x000fc800078e020b */
/*0460*/ IMAD R10, R10, R25, R11 ; /* 0x000000190a0a7224 */
/* 0x000fc800078e020b */
/*0470*/ IMAD R9, R9, R28, R10 ; /* 0x0000001c09097224 */
/* 0x000fc800078e020a */
/*0480*/ IMAD R15, R26, R27, R9 ; /* 0x0000001b1a0f7224 */
/* 0x000fe200078e0209 */
/*0490*/ @P0 BRA 0xd0 ; /* 0xfffffc3000000947 */
/* 0x000fea000383ffff */
/*04a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04b0*/ LEA R2, R7, R0, 0xa ; /* 0x0000000007027211 */
/* 0x000fd200078e50ff */
/*04c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*04d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrix_productPiS_S_
.globl _Z14matrix_productPiS_S_
.p2align 8
.type _Z14matrix_productPiS_S_,@function
_Z14matrix_productPiS_S_:
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 5, v1
v_lshl_add_u32 v6, s14, 5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 10, v5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v1, vcc_lo
v_mov_b32_e32 v0, v6
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v3, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_nc_u32_e32 v0, 0x400, v0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x1000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v1, v[3:4], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v9, v1, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v3
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v5, 10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrix_productPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrix_productPiS_S_, .Lfunc_end0-_Z14matrix_productPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrix_productPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrix_productPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00143726_00000000-6_matrix_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
.type _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_, @function
_Z38__device_stub__Z14matrix_productPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrix_productPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_, .-_Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
.globl _Z14matrix_productPiS_S_
.type _Z14matrix_productPiS_S_, @function
_Z14matrix_productPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14matrix_productPiS_S_, .-_Z14matrix_productPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "OK\n"
.LC1:
.string "NG\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl $1, (%rbx,%rax)
movl $1, 0(%rbp,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L13:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %r14d
movl $0, %r9d
movl $1, %r11d
.L14:
leaq 4194304(%rbx), %rdi
movq %r14, %r10
salq $12, %r10
leaq 0(%rbp,%r10), %r13
addq %r12, %r10
movl $0, %r8d
.L19:
leaq -4194304(%rdi), %rax
movq %r13, %rcx
movl $0, %esi
.L15:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $4096, %rax
cmpq %rdi, %rax
jne .L15
cmpl %esi, (%r10,%r8,4)
cmovne %r11d, %r9d
addq $1, %r8
addq $4, %rdi
cmpq $1024, %r8
jne .L19
addq $1, %r14
cmpq $1024, %r14
jne .L14
testl %r9d, %r9d
jne .L20
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
jmp .L13
.L20:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14matrix_productPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrix_productPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_product.hip"
.globl _Z29__device_stub__matrix_productPiS_S_ # -- Begin function _Z29__device_stub__matrix_productPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__matrix_productPiS_S_,@function
_Z29__device_stub__matrix_productPiS_S_: # @_Z29__device_stub__matrix_productPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrix_productPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__matrix_productPiS_S_, .Lfunc_end0-_Z29__device_stub__matrix_productPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $1, %ebp
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matrix_productPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader45
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_7 Depth 3
movq %rcx, %rdx
shlq $12, %rdx
addq %r15, %rdx
movq %r14, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_6: # %.preheader
# Parent Loop BB1_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
xorl %r8d, %r8d
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# Parent Loop BB1_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rax,%r8,4), %r11d
addl %r11d, %r10d
incq %r8
addq $4096, %r9 # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB1_7
# %bb.8: # in Loop: Header=BB1_6 Depth=2
cmpl %r10d, (%rdx,%rdi,4)
cmovnel %ebp, %r12d
incq %rdi
addq $4, %rsi
cmpq $1024, %rdi # imm = 0x400
jne .LBB1_6
# %bb.9: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rcx # imm = 0x400
jne .LBB1_5
# %bb.10:
testl %r12d, %r12d
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrix_productPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrix_productPiS_S_,@object # @_Z14matrix_productPiS_S_
.section .rodata,"a",@progbits
.globl _Z14matrix_productPiS_S_
.p2align 3, 0x0
_Z14matrix_productPiS_S_:
.quad _Z29__device_stub__matrix_productPiS_S_
.size _Z14matrix_productPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrix_productPiS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "NG"
.size .Lstr, 3
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OK"
.size .Lstr.1, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrix_productPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrix_productPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* calculating pi via area under the curve
* This code uses an algorithm fairly easily ported to all parallel methods.
* Since it calculates pi, it is easy to verify that results are correct.
* It can also be used to explore accuracy of results and techniques for managing error.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define NUMRECT 10000000
/* students learn in grammar school that the area of a circle is pi*radius*radius.
* They learn in high school that the formula of a circle is x^2 + y^2 = radius^2.
*
* These facts allows students calculating pi by estimating area of mid-point rectangles
*
* Area of unit circle is pi, y = sqrt(1-x^2) is formula for semicircle from -1 to 1
*/
// constants useful to CUDA
const int threadsPerBlock = 256;
const int blocksPerGrid = 32;
const int totalThreads = threadsPerBlock * blocksPerGrid;
const float overallWidth = 2.0f;
const float block_width = overallWidth / blocksPerGrid;
__global__ void calcArea(int *d_rectPerThread, float *d_width, float *partPiByBlock) {
__shared__ float partPiByThread[threadsPerBlock];
int reduce_i = blockDim.x / 2; // index for reducing thread results to single block value
float width = *d_width;
int rectPerThread = *d_rectPerThread;
float x = -1.0f
+ (overallWidth * blockIdx.x) / blocksPerGrid
+ (block_width * threadIdx.x) / threadsPerBlock
- width / 2;
float partPi = 0.0f;
for (int i = 0; i < rectPerThread; i++) {
x += width;
partPi += width * sqrtf(1.0f - x * x);
}
partPiByThread[threadIdx.x] = partPi;
// reduce all threads in the block to a single block value
while (reduce_i != 0) {
__syncthreads();
if (threadIdx.x < reduce_i)
partPiByThread[threadIdx.x] += partPiByThread[threadIdx.x + reduce_i];
reduce_i /= 2;
}
// store block result in correct spot for reducing on CPU side
if (threadIdx.x == 0)
partPiByBlock[blockIdx.x] = partPiByThread[0];
}
int main(int argc, char **argv) {
int numRect; // number of rectangles
int *d_rectPerThread, rectPerThread; // number of rectangles per thread
int i; // loop index
float *d_width, width; // width of each rectangle
float *d_partPiByBlock, h_partPiByBlock[blocksPerGrid]; // partial pi values returned by CUDA
float pi, halfPI = 0.0; // sum of area of rectangles gives pi/2
numRect = argc == 2 ? atoi(argv[1]) : NUMRECT; // get number of rectangles
rectPerThread = numRect / totalThreads;
numRect = rectPerThread * totalThreads;
width = overallWidth / numRect; // calculate width of each rectangle
cudaMalloc((void**)&d_rectPerThread, sizeof(int));
cudaMalloc((void**)&d_width, sizeof(int));
cudaMalloc((void**)&d_partPiByBlock, sizeof(float) * blocksPerGrid);
cudaMemcpy(d_rectPerThread, &rectPerThread, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_width, &width, sizeof(float), cudaMemcpyHostToDevice);
calcArea <<<blocksPerGrid, threadsPerBlock>>> (d_rectPerThread, d_width, d_partPiByBlock);
cudaMemcpy(h_partPiByBlock, d_partPiByBlock, sizeof(float) * blocksPerGrid,
cudaMemcpyDeviceToHost);
for (i = 0; i < blocksPerGrid; ++i)
halfPI += h_partPiByBlock[i]; /* calculate pi/4, with room for better error mgmt */
pi = 2.0 * halfPI;
printf ("\n==\n==\t%20s = %15.10f\n", "pi", pi);
printf ("==\t%20s = %15d\n", "total rectangles", numRect);
printf ("==\t%20s = %15d\n==\n\n", "CUDA threads", totalThreads);
return 0;
} | code for sm_80
Function : _Z8calcAreaPiPfS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*0050*/ HFMA2.MMA R10, -RZ, RZ, 1.25, 0 ; /* 0x3d000000ff0a7435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0090*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*00a0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*00b0*/ I2F.U32 R3, R0 ; /* 0x0000000000037306 */
/* 0x001e300000201000 */
/*00c0*/ I2F.U32 R6, R2 ; /* 0x0000000200067306 */
/* 0x002e620000201000 */
/*00d0*/ FADD R3, R3, R3 ; /* 0x0000000303037221 */
/* 0x001fc80000000000 */
/*00e0*/ FFMA R3, R3, R10, -1 ; /* 0xbf80000003037423 */
/* 0x000fe4000000000a */
/*00f0*/ FMUL R6, R6, 0.0625 ; /* 0x3d80000006067820 */
/* 0x002fc80000400000 */
/*0100*/ FFMA R7, R6, 0.00390625, R3 ; /* 0x3b80000006077823 */
/* 0x000fe20000000003 */
/*0110*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe40008000f00 */
/*0120*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x004fda0003f06270 */
/*0130*/ @!P0 BRA 0x790 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fca0000000f00 */
/*0160*/ LDG.E R4, [R10.64] ; /* 0x000000060a047981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IADD3 R5, R8.reuse, -0x1, RZ ; /* 0xffffffff08057810 */
/* 0x040fe40007ffe0ff */
/*0180*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*01a0*/ LOP3.LUT R5, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308057812 */
/* 0x000fe200078ec0ff */
/*01b0*/ FFMA R7, R4, -0.5, R7 ; /* 0xbf00000004077823 */
/* 0x004fd40000000007 */
/*01c0*/ @!P0 BRA 0x630 ; /* 0x0000046000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R6, R8, -R5, RZ ; /* 0x8000000508067210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*01f0*/ FADD R17, R4, R7 ; /* 0x0000000704117221 */
/* 0x000fe20000000000 */
/*0200*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0210*/ BSSY B0, 0x300 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0220*/ FFMA R14, -R17, R17, 1 ; /* 0x3f800000110e7423 */
/* 0x000fe20000000111 */
/*0230*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0240*/ MUFU.RSQ R7, R14 ; /* 0x0000000e00077308 */
/* 0x0000620000001400 */
/*0250*/ IADD3 R8, R14, -0xd000000, RZ ; /* 0xf30000000e087810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P1, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f24070 */
/*0270*/ @!P1 BRA 0x2b0 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0280*/ MOV R15, 0x2a0 ; /* 0x000002a0000f7802 */
/* 0x003fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x900 ; /* 0x0000066000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ BRA 0x2f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*02b0*/ FMUL.FTZ R8, R14, R7 ; /* 0x000000070e087220 */
/* 0x003fe40000410000 */
/*02c0*/ FMUL.FTZ R10, R7, 0.5 ; /* 0x3f000000070a7820 */
/* 0x000fe40000410000 */
/*02d0*/ FFMA R7, -R8, R8, R14 ; /* 0x0000000808077223 */
/* 0x000fc8000000010e */
/*02e0*/ FFMA R8, R7, R10, R8 ; /* 0x0000000a07087223 */
/* 0x000fe40000000008 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ FADD R7, R4.reuse, R17 ; /* 0x0000001104077221 */
/* 0x040fe20000000000 */
/*0310*/ BSSY B0, 0x400 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0320*/ FFMA R9, R4, R8, R9 ; /* 0x0000000804097223 */
/* 0x000fe40000000009 */
/*0330*/ FFMA R14, -R7, R7, 1 ; /* 0x3f800000070e7423 */
/* 0x000fc80000000107 */
/*0340*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0000620000001400 */
/*0350*/ IADD3 R10, R14, -0xd000000, RZ ; /* 0xf30000000e0a7810 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GT.U32.AND P1, PT, R10, 0x727fffff, PT ; /* 0x727fffff0a00780c */
/* 0x000fda0003f24070 */
/*0370*/ @!P1 BRA 0x3b0 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0380*/ MOV R15, 0x3a0 ; /* 0x000003a0000f7802 */
/* 0x003fe40000000f00 */
/*0390*/ CALL.REL.NOINC 0x900 ; /* 0x0000056000007944 */
/* 0x000fea0003c00000 */
/*03a0*/ BRA 0x3f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*03b0*/ FMUL.FTZ R8, R14, R11 ; /* 0x0000000b0e087220 */
/* 0x003fe40000410000 */
/*03c0*/ FMUL.FTZ R10, R11, 0.5 ; /* 0x3f0000000b0a7820 */
/* 0x000fe40000410000 */
/*03d0*/ FFMA R11, -R8, R8, R14 ; /* 0x00000008080b7223 */
/* 0x000fc8000000010e */
/*03e0*/ FFMA R8, R11, R10, R8 ; /* 0x0000000a0b087223 */
/* 0x000fe40000000008 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ FADD R7, R4.reuse, R7 ; /* 0x0000000704077221 */
/* 0x040fe20000000000 */
/*0410*/ BSSY B0, 0x500 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0420*/ FFMA R9, R4, R8, R9 ; /* 0x0000000804097223 */
/* 0x000fe40000000009 */
/*0430*/ FFMA R14, -R7, R7, 1 ; /* 0x3f800000070e7423 */
/* 0x000fc80000000107 */
/*0440*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0000620000001400 */
/*0450*/ IADD3 R10, R14, -0xd000000, RZ ; /* 0xf30000000e0a7810 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GT.U32.AND P1, PT, R10, 0x727fffff, PT ; /* 0x727fffff0a00780c */
/* 0x000fda0003f24070 */
/*0470*/ @!P1 BRA 0x4b0 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0480*/ MOV R15, 0x4a0 ; /* 0x000004a0000f7802 */
/* 0x003fe40000000f00 */
/*0490*/ CALL.REL.NOINC 0x900 ; /* 0x0000046000007944 */
/* 0x000fea0003c00000 */
/*04a0*/ BRA 0x4f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04b0*/ FMUL.FTZ R8, R14, R11 ; /* 0x0000000b0e087220 */
/* 0x003fe40000410000 */
/*04c0*/ FMUL.FTZ R10, R11, 0.5 ; /* 0x3f0000000b0a7820 */
/* 0x000fe40000410000 */
/*04d0*/ FFMA R11, -R8, R8, R14 ; /* 0x00000008080b7223 */
/* 0x000fc8000000010e */
/*04e0*/ FFMA R8, R11, R10, R8 ; /* 0x0000000a0b087223 */
/* 0x000fe40000000008 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ FADD R7, R4.reuse, R7 ; /* 0x0000000704077221 */
/* 0x040fe20000000000 */
/*0510*/ BSSY B0, 0x610 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0520*/ FFMA R16, R4, R8, R9 ; /* 0x0000000804107223 */
/* 0x000fe40000000009 */
/*0530*/ FFMA R14, -R7, R7, 1 ; /* 0x3f800000070e7423 */
/* 0x000fc80000000107 */
/*0540*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0000620000001400 */
/*0550*/ IADD3 R10, R14, -0xd000000, RZ ; /* 0xf30000000e0a7810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.U32.AND P1, PT, R10, 0x727fffff, PT ; /* 0x727fffff0a00780c */
/* 0x000fda0003f24070 */
/*0570*/ @!P1 BRA 0x5c0 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0580*/ MOV R15, 0x5a0 ; /* 0x000005a0000f7802 */
/* 0x003fe40000000f00 */
/*0590*/ CALL.REL.NOINC 0x900 ; /* 0x0000036000007944 */
/* 0x000fea0003c00000 */
/*05a0*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0008 */
/*05b0*/ BRA 0x600 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*05c0*/ FMUL.FTZ R9, R14, R11 ; /* 0x0000000b0e097220 */
/* 0x003fe40000410000 */
/*05d0*/ FMUL.FTZ R10, R11, 0.5 ; /* 0x3f0000000b0a7820 */
/* 0x000fe40000410000 */
/*05e0*/ FFMA R8, -R9, R9, R14 ; /* 0x0000000909087223 */
/* 0x000fc8000000010e */
/*05f0*/ FFMA R9, R8, R10, R9 ; /* 0x0000000a08097223 */
/* 0x000fe40000000009 */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ FFMA R9, R4, R9, R16 ; /* 0x0000000904097223 */
/* 0x000fe20000000010 */
/*0620*/ @P0 BRA 0x1f0 ; /* 0xfffffbc000000947 */
/* 0x000fea000383ffff */
/*0630*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0640*/ @!P0 BRA 0x790 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0650*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x000fe20000000000 */
/*0660*/ BSSY B0, 0x750 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0670*/ FFMA R14, -R7, R7, 1 ; /* 0x3f800000070e7423 */
/* 0x000fc80000000107 */
/*0680*/ MUFU.RSQ R11, R14 ; /* 0x0000000e000b7308 */
/* 0x0000620000001400 */
/*0690*/ IADD3 R6, R14, -0xd000000, RZ ; /* 0xf30000000e067810 */
/* 0x000fc80007ffe0ff */
/*06a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*06b0*/ @!P0 BRA 0x700 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R15, 0x6e0 ; /* 0x000006e0000f7802 */
/* 0x003fe40000000f00 */
/*06d0*/ CALL.REL.NOINC 0x900 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*06e0*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe20000000f00 */
/*06f0*/ BRA 0x740 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0700*/ FMUL.FTZ R6, R14, R11 ; /* 0x0000000b0e067220 */
/* 0x003fe40000410000 */
/*0710*/ FMUL.FTZ R8, R11, 0.5 ; /* 0x3f0000000b087820 */
/* 0x000fe40000410000 */
/*0720*/ FFMA R11, -R6, R6, R14 ; /* 0x00000006060b7223 */
/* 0x000fc8000000010e */
/*0730*/ FFMA R6, R11, R8, R6 ; /* 0x000000080b067223 */
/* 0x000fe40000000006 */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0760*/ FFMA R9, R4, R6, R9 ; /* 0x0000000604097223 */
/* 0x000fc60000000009 */
/*0770*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0780*/ @P0 BRA 0x650 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0790*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x0001e20000004800 */
/*07a0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*07b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f05270 */
/*07c0*/ @!P1 BRA 0x8a0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*07d0*/ SHF.L.U32 R4, R2, 0x2, RZ ; /* 0x0000000202047819 */
/* 0x001fe400000006ff */
/*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07f0*/ ISETP.GE.U32.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f26070 */
/*0800*/ @!P1 LEA R5, R3.reuse, R4, 0x2 ; /* 0x0000000403059211 */
/* 0x040fe200078e10ff */
/*0810*/ @!P1 LDS R6, [R2.X4] ; /* 0x0000000002069984 */
/* 0x000fea0000004800 */
/*0820*/ @!P1 LDS R5, [R5] ; /* 0x0000000005059984 */
/* 0x000e240000000800 */
/*0830*/ @!P1 FADD R7, R6, R5 ; /* 0x0000000506079221 */
/* 0x001fe20000000000 */
/*0840*/ IADD3 R6, R3.reuse, 0x1, RZ ; /* 0x0000000103067810 */
/* 0x040fe40007ffe0ff */
/*0850*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0860*/ @!P1 STS [R2.X4], R7 ; /* 0x0000000702009388 */
/* 0x0001e20000004800 */
/*0870*/ ISETP.GT.U32.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe40003f24070 */
/*0880*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0890*/ @P1 BRA 0x7e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*08a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*08b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*08c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*08d0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*08e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fda000782c0ff */
/*0910*/ @!P1 IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff089224 */
/* 0x000fe200078e000e */
/*0920*/ @!P1 BRA 0xa30 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0930*/ FSETP.GEU.FTZ.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720b */
/* 0x000fda0003f3e000 */
/*0940*/ @!P1 MOV R8, 0x7fffffff ; /* 0x7fffffff00089802 */
/* 0x000fe20000000f00 */
/*0950*/ @!P1 BRA 0xa30 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0960*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fda0003f3c200 */
/*0970*/ @P1 FADD.FTZ R8, R14, 1 ; /* 0x3f8000000e081421 */
/* 0x000fe20000010000 */
/*0980*/ @P1 BRA 0xa30 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0990*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fda0003f3d200 */
/*09a0*/ @P1 FFMA R10, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0a1823 */
/* 0x000fc800000000ff */
/*09b0*/ @P1 MUFU.RSQ R11, R10 ; /* 0x0000000a000b1308 */
/* 0x000e240000001400 */
/*09c0*/ @P1 FMUL.FTZ R13, R10, R11 ; /* 0x0000000b0a0d1220 */
/* 0x001fe40000410000 */
/*09d0*/ @P1 FMUL.FTZ R11, R11, 0.5 ; /* 0x3f0000000b0b1820 */
/* 0x000fe40000410000 */
/*09e0*/ @P1 FADD.FTZ R8, -R13, -RZ ; /* 0x800000ff0d081221 */
/* 0x000fc80000010100 */
/*09f0*/ @P1 FFMA R12, R13, R8, R10 ; /* 0x000000080d0c1223 */
/* 0x000fe2000000000a */
/*0a00*/ @!P1 MOV R8, R14 ; /* 0x0000000e00089202 */
/* 0x000fc60000000f00 */
/*0a10*/ @P1 FFMA R11, R12, R11, R13 ; /* 0x0000000b0c0b1223 */
/* 0x000fc8000000000d */
/*0a20*/ @P1 FMUL.FTZ R8, R11, 2.3283064365386962891e-10 ; /* 0x2f8000000b081820 */
/* 0x000fe40000410000 */
/*0a30*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0a40*/ MOV R10, R15 ; /* 0x0000000f000a7202 */
/* 0x000fca0000000f00 */
/*0a50*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff5a00a007950 */
/* 0x000fea0003c3ffff */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* calculating pi via area under the curve
* This code uses an algorithm fairly easily ported to all parallel methods.
* Since it calculates pi, it is easy to verify that results are correct.
* It can also be used to explore accuracy of results and techniques for managing error.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define NUMRECT 10000000
/* students learn in grammar school that the area of a circle is pi*radius*radius.
* They learn in high school that the formula of a circle is x^2 + y^2 = radius^2.
*
* These facts allows students calculating pi by estimating area of mid-point rectangles
*
* Area of unit circle is pi, y = sqrt(1-x^2) is formula for semicircle from -1 to 1
*/
// constants useful to CUDA
const int threadsPerBlock = 256;
const int blocksPerGrid = 32;
const int totalThreads = threadsPerBlock * blocksPerGrid;
const float overallWidth = 2.0f;
const float block_width = overallWidth / blocksPerGrid;
__global__ void calcArea(int *d_rectPerThread, float *d_width, float *partPiByBlock) {
__shared__ float partPiByThread[threadsPerBlock];
int reduce_i = blockDim.x / 2; // index for reducing thread results to single block value
float width = *d_width;
int rectPerThread = *d_rectPerThread;
float x = -1.0f
+ (overallWidth * blockIdx.x) / blocksPerGrid
+ (block_width * threadIdx.x) / threadsPerBlock
- width / 2;
float partPi = 0.0f;
for (int i = 0; i < rectPerThread; i++) {
x += width;
partPi += width * sqrtf(1.0f - x * x);
}
partPiByThread[threadIdx.x] = partPi;
// reduce all threads in the block to a single block value
while (reduce_i != 0) {
__syncthreads();
if (threadIdx.x < reduce_i)
partPiByThread[threadIdx.x] += partPiByThread[threadIdx.x + reduce_i];
reduce_i /= 2;
}
// store block result in correct spot for reducing on CPU side
if (threadIdx.x == 0)
partPiByBlock[blockIdx.x] = partPiByThread[0];
}
int main(int argc, char **argv) {
int numRect; // number of rectangles
int *d_rectPerThread, rectPerThread; // number of rectangles per thread
int i; // loop index
float *d_width, width; // width of each rectangle
float *d_partPiByBlock, h_partPiByBlock[blocksPerGrid]; // partial pi values returned by CUDA
float pi, halfPI = 0.0; // sum of area of rectangles gives pi/2
numRect = argc == 2 ? atoi(argv[1]) : NUMRECT; // get number of rectangles
rectPerThread = numRect / totalThreads;
numRect = rectPerThread * totalThreads;
width = overallWidth / numRect; // calculate width of each rectangle
cudaMalloc((void**)&d_rectPerThread, sizeof(int));
cudaMalloc((void**)&d_width, sizeof(int));
cudaMalloc((void**)&d_partPiByBlock, sizeof(float) * blocksPerGrid);
cudaMemcpy(d_rectPerThread, &rectPerThread, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_width, &width, sizeof(float), cudaMemcpyHostToDevice);
calcArea <<<blocksPerGrid, threadsPerBlock>>> (d_rectPerThread, d_width, d_partPiByBlock);
cudaMemcpy(h_partPiByBlock, d_partPiByBlock, sizeof(float) * blocksPerGrid,
cudaMemcpyDeviceToHost);
for (i = 0; i < blocksPerGrid; ++i)
halfPI += h_partPiByBlock[i]; /* calculate pi/4, with room for better error mgmt */
pi = 2.0 * halfPI;
printf ("\n==\n==\t%20s = %15.10f\n", "pi", pi);
printf ("==\t%20s = %15d\n", "total rectangles", numRect);
printf ("==\t%20s = %15d\n==\n\n", "CUDA threads", totalThreads);
return 0;
} | .file "tmpxft_00162233_00000000-6_pi_area_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8calcAreaPiPfS0_PiPfS0_
.type _Z32__device_stub__Z8calcAreaPiPfS0_PiPfS0_, @function
_Z32__device_stub__Z8calcAreaPiPfS0_PiPfS0_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8calcAreaPiPfS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8calcAreaPiPfS0_PiPfS0_, .-_Z32__device_stub__Z8calcAreaPiPfS0_PiPfS0_
.globl _Z8calcAreaPiPfS0_
.type _Z8calcAreaPiPfS0_, @function
_Z8calcAreaPiPfS0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8calcAreaPiPfS0_PiPfS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8calcAreaPiPfS0_, .-_Z8calcAreaPiPfS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "pi"
.LC3:
.string "\n==\n==\t%20s = %15.10f\n"
.LC4:
.string "total rectangles"
.LC5:
.string "==\t%20s = %15d\n"
.LC6:
.string "CUDA threads"
.LC7:
.string "==\t%20s = %15d\n==\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $216, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl $10000000, %eax
cmpl $2, %edi
je .L19
.L12:
leal 8191(%rax), %ebp
testl %eax, %eax
cmovns %eax, %ebp
sarl $13, %ebp
movl %ebp, 8(%rsp)
sall $13, %ebp
pxor %xmm1, %xmm1
cvtsi2ssl %ebp, %xmm1
movss .LC1(%rip), %xmm0
divss %xmm1, %xmm0
movss %xmm0, 12(%rsp)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 192(%rsp), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
addss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebp, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8192, %ecx
leaq .LC6(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L12
.L20:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z8calcAreaPiPfS0_PiPfS0_
jmp .L13
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z8calcAreaPiPfS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8calcAreaPiPfS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* calculating pi via area under the curve
* This code uses an algorithm fairly easily ported to all parallel methods.
* Since it calculates pi, it is easy to verify that results are correct.
* It can also be used to explore accuracy of results and techniques for managing error.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define NUMRECT 10000000
/* students learn in grammar school that the area of a circle is pi*radius*radius.
* They learn in high school that the formula of a circle is x^2 + y^2 = radius^2.
*
* These facts allows students calculating pi by estimating area of mid-point rectangles
*
* Area of unit circle is pi, y = sqrt(1-x^2) is formula for semicircle from -1 to 1
*/
// constants useful to CUDA
const int threadsPerBlock = 256;
const int blocksPerGrid = 32;
const int totalThreads = threadsPerBlock * blocksPerGrid;
const float overallWidth = 2.0f;
const float block_width = overallWidth / blocksPerGrid;
__global__ void calcArea(int *d_rectPerThread, float *d_width, float *partPiByBlock) {
__shared__ float partPiByThread[threadsPerBlock];
int reduce_i = blockDim.x / 2; // index for reducing thread results to single block value
float width = *d_width;
int rectPerThread = *d_rectPerThread;
float x = -1.0f
+ (overallWidth * blockIdx.x) / blocksPerGrid
+ (block_width * threadIdx.x) / threadsPerBlock
- width / 2;
float partPi = 0.0f;
for (int i = 0; i < rectPerThread; i++) {
x += width;
partPi += width * sqrtf(1.0f - x * x);
}
partPiByThread[threadIdx.x] = partPi;
// reduce all threads in the block to a single block value
while (reduce_i != 0) {
__syncthreads();
if (threadIdx.x < reduce_i)
partPiByThread[threadIdx.x] += partPiByThread[threadIdx.x + reduce_i];
reduce_i /= 2;
}
// store block result in correct spot for reducing on CPU side
if (threadIdx.x == 0)
partPiByBlock[blockIdx.x] = partPiByThread[0];
}
int main(int argc, char **argv) {
int numRect; // number of rectangles
int *d_rectPerThread, rectPerThread; // number of rectangles per thread
int i; // loop index
float *d_width, width; // width of each rectangle
float *d_partPiByBlock, h_partPiByBlock[blocksPerGrid]; // partial pi values returned by CUDA
float pi, halfPI = 0.0; // sum of area of rectangles gives pi/2
numRect = argc == 2 ? atoi(argv[1]) : NUMRECT; // get number of rectangles
rectPerThread = numRect / totalThreads;
numRect = rectPerThread * totalThreads;
width = overallWidth / numRect; // calculate width of each rectangle
cudaMalloc((void**)&d_rectPerThread, sizeof(int));
cudaMalloc((void**)&d_width, sizeof(int));
cudaMalloc((void**)&d_partPiByBlock, sizeof(float) * blocksPerGrid);
cudaMemcpy(d_rectPerThread, &rectPerThread, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_width, &width, sizeof(float), cudaMemcpyHostToDevice);
calcArea <<<blocksPerGrid, threadsPerBlock>>> (d_rectPerThread, d_width, d_partPiByBlock);
cudaMemcpy(h_partPiByBlock, d_partPiByBlock, sizeof(float) * blocksPerGrid,
cudaMemcpyDeviceToHost);
for (i = 0; i < blocksPerGrid; ++i)
halfPI += h_partPiByBlock[i]; /* calculate pi/4, with room for better error mgmt */
pi = 2.0 * halfPI;
printf ("\n==\n==\t%20s = %15.10f\n", "pi", pi);
printf ("==\t%20s = %15d\n", "total rectangles", numRect);
printf ("==\t%20s = %15d\n==\n\n", "CUDA threads", totalThreads);
return 0;
} | /* calculating pi via area under the curve
* This code uses an algorithm fairly easily ported to all parallel methods.
* Since it calculates pi, it is easy to verify that results are correct.
* It can also be used to explore accuracy of results and techniques for managing error.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define NUMRECT 10000000
/* students learn in grammar school that the area of a circle is pi*radius*radius.
* They learn in high school that the formula of a circle is x^2 + y^2 = radius^2.
*
* These facts allows students calculating pi by estimating area of mid-point rectangles
*
* Area of unit circle is pi, y = sqrt(1-x^2) is formula for semicircle from -1 to 1
*/
// constants useful to CUDA
const int threadsPerBlock = 256;
const int blocksPerGrid = 32;
const int totalThreads = threadsPerBlock * blocksPerGrid;
const float overallWidth = 2.0f;
const float block_width = overallWidth / blocksPerGrid;
__global__ void calcArea(int *d_rectPerThread, float *d_width, float *partPiByBlock) {
__shared__ float partPiByThread[threadsPerBlock];
int reduce_i = blockDim.x / 2; // index for reducing thread results to single block value
float width = *d_width;
int rectPerThread = *d_rectPerThread;
float x = -1.0f
+ (overallWidth * blockIdx.x) / blocksPerGrid
+ (block_width * threadIdx.x) / threadsPerBlock
- width / 2;
float partPi = 0.0f;
for (int i = 0; i < rectPerThread; i++) {
x += width;
partPi += width * sqrtf(1.0f - x * x);
}
partPiByThread[threadIdx.x] = partPi;
// reduce all threads in the block to a single block value
while (reduce_i != 0) {
__syncthreads();
if (threadIdx.x < reduce_i)
partPiByThread[threadIdx.x] += partPiByThread[threadIdx.x + reduce_i];
reduce_i /= 2;
}
// store block result in correct spot for reducing on CPU side
if (threadIdx.x == 0)
partPiByBlock[blockIdx.x] = partPiByThread[0];
}
int main(int argc, char **argv) {
int numRect; // number of rectangles
int *d_rectPerThread, rectPerThread; // number of rectangles per thread
int i; // loop index
float *d_width, width; // width of each rectangle
float *d_partPiByBlock, h_partPiByBlock[blocksPerGrid]; // partial pi values returned by CUDA
float pi, halfPI = 0.0; // sum of area of rectangles gives pi/2
numRect = argc == 2 ? atoi(argv[1]) : NUMRECT; // get number of rectangles
rectPerThread = numRect / totalThreads;
numRect = rectPerThread * totalThreads;
width = overallWidth / numRect; // calculate width of each rectangle
hipMalloc((void**)&d_rectPerThread, sizeof(int));
hipMalloc((void**)&d_width, sizeof(int));
hipMalloc((void**)&d_partPiByBlock, sizeof(float) * blocksPerGrid);
hipMemcpy(d_rectPerThread, &rectPerThread, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_width, &width, sizeof(float), hipMemcpyHostToDevice);
calcArea <<<blocksPerGrid, threadsPerBlock>>> (d_rectPerThread, d_width, d_partPiByBlock);
hipMemcpy(h_partPiByBlock, d_partPiByBlock, sizeof(float) * blocksPerGrid,
hipMemcpyDeviceToHost);
for (i = 0; i < blocksPerGrid; ++i)
halfPI += h_partPiByBlock[i]; /* calculate pi/4, with room for better error mgmt */
pi = 2.0 * halfPI;
printf ("\n==\n==\t%20s = %15.10f\n", "pi", pi);
printf ("==\t%20s = %15d\n", "total rectangles", numRect);
printf ("==\t%20s = %15d\n==\n\n", "CUDA threads", totalThreads);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* calculating pi via area under the curve
* This code uses an algorithm fairly easily ported to all parallel methods.
* Since it calculates pi, it is easy to verify that results are correct.
* It can also be used to explore accuracy of results and techniques for managing error.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define NUMRECT 10000000
/* students learn in grammar school that the area of a circle is pi*radius*radius.
* They learn in high school that the formula of a circle is x^2 + y^2 = radius^2.
*
* These facts allows students calculating pi by estimating area of mid-point rectangles
*
* Area of unit circle is pi, y = sqrt(1-x^2) is formula for semicircle from -1 to 1
*/
// constants useful to CUDA
const int threadsPerBlock = 256;
const int blocksPerGrid = 32;
const int totalThreads = threadsPerBlock * blocksPerGrid;
const float overallWidth = 2.0f;
const float block_width = overallWidth / blocksPerGrid;
__global__ void calcArea(int *d_rectPerThread, float *d_width, float *partPiByBlock) {
__shared__ float partPiByThread[threadsPerBlock];
int reduce_i = blockDim.x / 2; // index for reducing thread results to single block value
float width = *d_width;
int rectPerThread = *d_rectPerThread;
float x = -1.0f
+ (overallWidth * blockIdx.x) / blocksPerGrid
+ (block_width * threadIdx.x) / threadsPerBlock
- width / 2;
float partPi = 0.0f;
for (int i = 0; i < rectPerThread; i++) {
x += width;
partPi += width * sqrtf(1.0f - x * x);
}
partPiByThread[threadIdx.x] = partPi;
// reduce all threads in the block to a single block value
while (reduce_i != 0) {
__syncthreads();
if (threadIdx.x < reduce_i)
partPiByThread[threadIdx.x] += partPiByThread[threadIdx.x + reduce_i];
reduce_i /= 2;
}
// store block result in correct spot for reducing on CPU side
if (threadIdx.x == 0)
partPiByBlock[blockIdx.x] = partPiByThread[0];
}
int main(int argc, char **argv) {
int numRect; // number of rectangles
int *d_rectPerThread, rectPerThread; // number of rectangles per thread
int i; // loop index
float *d_width, width; // width of each rectangle
float *d_partPiByBlock, h_partPiByBlock[blocksPerGrid]; // partial pi values returned by CUDA
float pi, halfPI = 0.0; // sum of area of rectangles gives pi/2
numRect = argc == 2 ? atoi(argv[1]) : NUMRECT; // get number of rectangles
rectPerThread = numRect / totalThreads;
numRect = rectPerThread * totalThreads;
width = overallWidth / numRect; // calculate width of each rectangle
hipMalloc((void**)&d_rectPerThread, sizeof(int));
hipMalloc((void**)&d_width, sizeof(int));
hipMalloc((void**)&d_partPiByBlock, sizeof(float) * blocksPerGrid);
hipMemcpy(d_rectPerThread, &rectPerThread, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_width, &width, sizeof(float), hipMemcpyHostToDevice);
calcArea <<<blocksPerGrid, threadsPerBlock>>> (d_rectPerThread, d_width, d_partPiByBlock);
hipMemcpy(h_partPiByBlock, d_partPiByBlock, sizeof(float) * blocksPerGrid,
hipMemcpyDeviceToHost);
for (i = 0; i < blocksPerGrid; ++i)
halfPI += h_partPiByBlock[i]; /* calculate pi/4, with room for better error mgmt */
pi = 2.0 * halfPI;
printf ("\n==\n==\t%20s = %15.10f\n", "pi", pi);
printf ("==\t%20s = %15d\n", "total rectangles", numRect);
printf ("==\t%20s = %15d\n==\n\n", "CUDA threads", totalThreads);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8calcAreaPiPfS0_
.globl _Z8calcAreaPiPfS0_
.p2align 8
.type _Z8calcAreaPiPfS0_,@function
_Z8calcAreaPiPfS0_:
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x8
v_cvt_f32_u32_e32 v1, s4
v_cvt_f32_u32_e32 v2, v0
v_mov_b32_e32 v3, -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v1, v1, v1 :: v_dual_mul_f32 v2, 0x3d800000, v2
v_fmamk_f32 v1, v1, 0x3d000000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v2, v2, 0x3b800000, v1 :: v_dual_mov_b32 v1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e64 v2, s5, -0.5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v2, s5, v2
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v2, v2, 1.0
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v4, v3
v_fma_f32 v8, -v6, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v4, v4, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v8
v_cndmask_b32_e64 v4, v4, v6, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
v_fmac_f32_e32 v1, s5, v3
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v1, 0
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_load_b32 s2, s[0:1], 0x24
v_lshlrev_b32_e32 v2, 2, v0
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s3, s2, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_9
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_gt_u32 s2, 1
s_mov_b32 s2, s3
s_cbranch_scc0 .LBB0_9
.LBB0_7:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v1, s2, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v3, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v3
ds_store_b32 v2, v1
s_branch .LBB0_6
.LBB0_9:
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8calcAreaPiPfS0_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8calcAreaPiPfS0_, .Lfunc_end0-_Z8calcAreaPiPfS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8calcAreaPiPfS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8calcAreaPiPfS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* calculating pi via area under the curve
* This code uses an algorithm fairly easily ported to all parallel methods.
* Since it calculates pi, it is easy to verify that results are correct.
* It can also be used to explore accuracy of results and techniques for managing error.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define NUMRECT 10000000
/* students learn in grammar school that the area of a circle is pi*radius*radius.
* They learn in high school that the formula of a circle is x^2 + y^2 = radius^2.
*
* These facts allows students calculating pi by estimating area of mid-point rectangles
*
* Area of unit circle is pi, y = sqrt(1-x^2) is formula for semicircle from -1 to 1
*/
// constants useful to CUDA
const int threadsPerBlock = 256;
const int blocksPerGrid = 32;
const int totalThreads = threadsPerBlock * blocksPerGrid;
const float overallWidth = 2.0f;
const float block_width = overallWidth / blocksPerGrid;
__global__ void calcArea(int *d_rectPerThread, float *d_width, float *partPiByBlock) {
__shared__ float partPiByThread[threadsPerBlock];
int reduce_i = blockDim.x / 2; // index for reducing thread results to single block value
float width = *d_width;
int rectPerThread = *d_rectPerThread;
float x = -1.0f
+ (overallWidth * blockIdx.x) / blocksPerGrid
+ (block_width * threadIdx.x) / threadsPerBlock
- width / 2;
float partPi = 0.0f;
for (int i = 0; i < rectPerThread; i++) {
x += width;
partPi += width * sqrtf(1.0f - x * x);
}
partPiByThread[threadIdx.x] = partPi;
// reduce all threads in the block to a single block value
while (reduce_i != 0) {
__syncthreads();
if (threadIdx.x < reduce_i)
partPiByThread[threadIdx.x] += partPiByThread[threadIdx.x + reduce_i];
reduce_i /= 2;
}
// store block result in correct spot for reducing on CPU side
if (threadIdx.x == 0)
partPiByBlock[blockIdx.x] = partPiByThread[0];
}
int main(int argc, char **argv) {
int numRect; // number of rectangles
int *d_rectPerThread, rectPerThread; // number of rectangles per thread
int i; // loop index
float *d_width, width; // width of each rectangle
float *d_partPiByBlock, h_partPiByBlock[blocksPerGrid]; // partial pi values returned by CUDA
float pi, halfPI = 0.0; // sum of area of rectangles gives pi/2
numRect = argc == 2 ? atoi(argv[1]) : NUMRECT; // get number of rectangles
rectPerThread = numRect / totalThreads;
numRect = rectPerThread * totalThreads;
width = overallWidth / numRect; // calculate width of each rectangle
hipMalloc((void**)&d_rectPerThread, sizeof(int));
hipMalloc((void**)&d_width, sizeof(int));
hipMalloc((void**)&d_partPiByBlock, sizeof(float) * blocksPerGrid);
hipMemcpy(d_rectPerThread, &rectPerThread, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_width, &width, sizeof(float), hipMemcpyHostToDevice);
calcArea <<<blocksPerGrid, threadsPerBlock>>> (d_rectPerThread, d_width, d_partPiByBlock);
hipMemcpy(h_partPiByBlock, d_partPiByBlock, sizeof(float) * blocksPerGrid,
hipMemcpyDeviceToHost);
for (i = 0; i < blocksPerGrid; ++i)
halfPI += h_partPiByBlock[i]; /* calculate pi/4, with room for better error mgmt */
pi = 2.0 * halfPI;
printf ("\n==\n==\t%20s = %15.10f\n", "pi", pi);
printf ("==\t%20s = %15d\n", "total rectangles", numRect);
printf ("==\t%20s = %15d\n==\n\n", "CUDA threads", totalThreads);
return 0;
} | .text
.file "pi_area_cuda.hip"
.globl _Z23__device_stub__calcAreaPiPfS0_ # -- Begin function _Z23__device_stub__calcAreaPiPfS0_
.p2align 4, 0x90
.type _Z23__device_stub__calcAreaPiPfS0_,@function
_Z23__device_stub__calcAreaPiPfS0_: # @_Z23__device_stub__calcAreaPiPfS0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8calcAreaPiPfS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__calcAreaPiPfS0_, .Lfunc_end0-_Z23__device_stub__calcAreaPiPfS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40000000 # float 2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
movl $1220, %ebx # imm = 0x4C4
cmpl $2, %edi
jne .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leal 8191(%rax), %ebx
testl %eax, %eax
cmovnsl %eax, %ebx
sarl $13, %ebx
.LBB1_2:
movl %ebx, 12(%rsp)
shll $13, %ebx
cvtsi2ss %ebx, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 8(%rsp)
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8calcAreaPiPfS0_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss 112(%rsp,%rax,4), %xmm0
incq %rax
cmpq $32, %rax
jne .LBB1_5
# %bb.6:
addss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl $.L.str.1, %esi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $8192, %edx # imm = 0x2000
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8calcAreaPiPfS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8calcAreaPiPfS0_,@object # @_Z8calcAreaPiPfS0_
.section .rodata,"a",@progbits
.globl _Z8calcAreaPiPfS0_
.p2align 3, 0x0
_Z8calcAreaPiPfS0_:
.quad _Z23__device_stub__calcAreaPiPfS0_
.size _Z8calcAreaPiPfS0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n==\n==\t%20s = %15.10f\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "pi"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "==\t%20s = %15d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "total rectangles"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "==\t%20s = %15d\n==\n\n"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA threads"
.size .L.str.5, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8calcAreaPiPfS0_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__calcAreaPiPfS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8calcAreaPiPfS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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