system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,int var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
for (int i=0; i < var_1; ++i) {
if (comp > (var_2 * (var_3 - (+1.8532E-43f / +1.9626E14f * (+1.7886E-37f * var_4))))) {
if (comp >= (var_5 * (var_6 - var_7))) {
comp += (-0.0f - sinhf((-0.0f / var_9 + floorf(+1.5832E-42f))));
float tmp_1 = -1.1252E-15f;
float tmp_2 = -1.3006E-24f;
comp += tmp_2 - tmp_1 - sinhf((-0.0f - (var_10 / var_11 + (var_12 / +1.1462E34f + var_13))));
if (comp >= atanf(+1.0472E-42f)) {
float tmp_3 = -1.4667E36f;
comp += tmp_3 + (var_14 + (var_15 * var_16 * var_17));
}
for (int i=0; i < var_8; ++i) {
comp = log10f(+1.2622E-35f);
}
if (comp == atan2f(floorf(+1.8171E-8f), (-1.3632E-43f / var_18 - (+0.0f - +1.9495E-41f)))) {
comp = (-1.3993E25f / (+1.0080E-42f * var_19 + var_20));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
int tmp_9 = atoi(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,int var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
for (int i=0; i < var_1; ++i) {
if (comp > (var_2 * (var_3 - (+1.8532E-43f / +1.9626E14f * (+1.7886E-37f * var_4))))) {
if (comp >= (var_5 * (var_6 - var_7))) {
comp += (-0.0f - sinhf((-0.0f / var_9 + floorf(+1.5832E-42f))));
float tmp_1 = -1.1252E-15f;
float tmp_2 = -1.3006E-24f;
comp += tmp_2 - tmp_1 - sinhf((-0.0f - (var_10 / var_11 + (var_12 / +1.1462E34f + var_13))));
if (comp >= atanf(+1.0472E-42f)) {
float tmp_3 = -1.4667E36f;
comp += tmp_3 + (var_14 + (var_15 * var_16 * var_17));
}
for (int i=0; i < var_8; ++i) {
comp = log10f(+1.2622E-35f);
}
if (comp == atan2f(floorf(+1.8171E-8f), (-1.3632E-43f / var_18 - (+0.0f - +1.9495E-41f)))) {
comp = (-1.3993E25f / (+1.0080E-42f * var_19 + var_20));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
int tmp_9 = atoi(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,int var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
for (int i=0; i < var_1; ++i) {
if (comp > (var_2 * (var_3 - (+1.8532E-43f / +1.9626E14f * (+1.7886E-37f * var_4))))) {
if (comp >= (var_5 * (var_6 - var_7))) {
comp += (-0.0f - sinhf((-0.0f / var_9 + floorf(+1.5832E-42f))));
float tmp_1 = -1.1252E-15f;
float tmp_2 = -1.3006E-24f;
comp += tmp_2 - tmp_1 - sinhf((-0.0f - (var_10 / var_11 + (var_12 / +1.1462E34f + var_13))));
if (comp >= atanf(+1.0472E-42f)) {
float tmp_3 = -1.4667E36f;
comp += tmp_3 + (var_14 + (var_15 * var_16 * var_17));
}
for (int i=0; i < var_8; ++i) {
comp = log10f(+1.2622E-35f);
}
if (comp == atan2f(floorf(+1.8171E-8f), (-1.3632E-43f / var_18 - (+0.0f - +1.9495E-41f)))) {
comp = (-1.3993E25f / (+1.0080E-42f * var_19 + var_20));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
int tmp_9 = atoi(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiffffffiffffffffffff # -- Begin function _Z22__device_stub__computefiffffffiffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiffffffiffffffffffff,@function
_Z22__device_stub__computefiffffffiffffffffffff: # @_Z22__device_stub__computefiffffffiffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movl %esi, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 320(%rsp), %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
leaq 352(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiffffffiffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiffffffiffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiffffffiffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $240, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 88(%rsp) # 4-byte Spill
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 80(%rsp)
movss %xmm9, 72(%rsp)
movss %xmm10, 64(%rsp)
movss %xmm11, 56(%rsp)
movss %xmm12, 48(%rsp)
movss %xmm13, 40(%rsp)
movss %xmm14, 32(%rsp)
movss %xmm15, 24(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, (%rsp)
movl %ebx, %edi
movaps %xmm7, %xmm4
movss 104(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 96(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movl %r15d, %esi
movss 88(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiffffffiffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiffffffiffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiffffffiffffffffffff,@object # @_Z7computefiffffffiffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiffffffiffffffffffff
.p2align 3, 0x0
_Z7computefiffffffiffffffffffff:
.quad _Z22__device_stub__computefiffffffiffffffffffff
.size _Z7computefiffffffiffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiffffffiffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiffffffiffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiffffffiffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aa209_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
.type _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff, @function
_Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movl %esi, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 312
pushq 56(%rsp)
.cfi_def_cfa_offset 320
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiffffffiffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff, .-_Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
.globl _Z7computefiffffffiffffffffffff
.type _Z7computefiffffffiffffffffffff, @function
_Z7computefiffffffiffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiffffffiffffffffffff, .-_Z7computefiffffffiffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $192, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 72(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
subq $96, %rsp
.cfi_def_cfa_offset 320
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
movl %ebp, %esi
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movl %r12d, %edi
call _Z45__device_stub__Z7computefiffffffifffffffffffffiffffffiffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiffffffiffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiffffffiffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiffffffiffffffffffff # -- Begin function _Z22__device_stub__computefiffffffiffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiffffffiffffffffffff,@function
_Z22__device_stub__computefiffffffiffffffffffff: # @_Z22__device_stub__computefiffffffiffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movl %esi, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 320(%rsp), %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
leaq 352(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiffffffiffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiffffffiffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiffffffiffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $240, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 88(%rsp) # 4-byte Spill
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 80(%rsp)
movss %xmm9, 72(%rsp)
movss %xmm10, 64(%rsp)
movss %xmm11, 56(%rsp)
movss %xmm12, 48(%rsp)
movss %xmm13, 40(%rsp)
movss %xmm14, 32(%rsp)
movss %xmm15, 24(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, (%rsp)
movl %ebx, %edi
movaps %xmm7, %xmm4
movss 104(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 96(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movl %r15d, %esi
movss 88(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiffffffiffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiffffffiffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiffffffiffffffffffff,@object # @_Z7computefiffffffiffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiffffffiffffffffffff
.p2align 3, 0x0
_Z7computefiffffffiffffffffffff:
.quad _Z22__device_stub__computefiffffffiffffffffffff
.size _Z7computefiffffffiffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiffffffiffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiffffffiffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiffffffiffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <limits.h>
__device__ static inline unsigned int argmin(unsigned int a, unsigned int b, unsigned int c)
{
if (a < b)
{
if (a < c)
return 0;
else
return 2;
}
if (b < c)
return 1;
else return 2;
}
__global__ void matching(int *D, unsigned int *phi, int m, int n)
{
// matrix m x n
int pnt = 2;
const int tid = threadIdx.x;// + blockDim.x * blockIdx.x;
if (tid < m)
{
int j = 0;
int reserve = -threadIdx.x + 1;
for (j = reserve; j < n; j++)
{
if (j >= 1){
int tmp[3] = {D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1]+pnt, D[(tid+1)*(n+1)+j]+pnt};
int arg = argmin(tmp[0], tmp[1], tmp[2]);
int dmin = tmp[arg];
D[(tid+1)*(n+1)+j+1] = D[(tid+1)*(n+1)+j+1] + dmin;
phi[tid * n + j] = arg + 1;
}
__syncthreads();
}
}
}
// if (tid == 2){
// printf("j: %d\n", j);
// printf("idx: %d %d %d %d\n",(tid * (n+1)) + j + 1, (tid * (n+1)) + j + 2, (tid+1)*(n+1)+j+1, (tid+1)*(n+1)+j+2);
// printf("tmp: %d %d %d\n",D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1], D[(tid+1)*(n+1)+j]);
// // printf("min: %d\n", tmp[arg]);
// printf("D[i+1][j+1]: %d\n", D[(tid+1)*(n+1)+j+1]);
// } | code for sm_80
Function : _Z8matchingPiPjii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x001fda0003f06270 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IADD3 R0, -R3, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x000fc80007ffe1ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R3, c[0x0][0x174], RZ ; /* 0x00005d0003027a10 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ LOP3.LUT P0, R10, R4, 0x3, RZ, 0xc0, !PT ; /* 0x00000003040a7812 */
/* 0x000fda000780c0ff */
/*00c0*/ @!P0 BRA 0x410 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*0100*/ IADD3 R4, R6, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R5, R5, R6.reuse, 0x2 ; /* 0x0000000205057424 */
/* 0x080fe400078e0206 */
/*0120*/ IMAD R6, R3, R6, 0x1 ; /* 0x0000000103067424 */
/* 0x000fe400078e0206 */
/*0130*/ IMAD R8, R4, R3, 0x1 ; /* 0x0000000104087424 */
/* 0x000fe400078e0203 */
/*0140*/ IMAD.WIDE R4, R5, R9, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0209 */
/*0150*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0209 */
/*0160*/ IADD3 R4, P0, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007f1e0ff */
/*0170*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0209 */
/*0180*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007f3e0ff */
/*0190*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe400000e0605 */
/*01a0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, R9 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0009 */
/*01c0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*01d0*/ @!P0 BRA 0x350 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R11, [R6.64] ; /* 0x00000006060b7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R9, [R6.64+-0x4] ; /* 0xfffffc0606097981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc06040d7981 */
/* 0x000f28000c1e1900 */
/*0210*/ LDG.E R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000f62000c1e1900 */
/*0220*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0230*/ IADD3 R12, R11, 0x2, RZ ; /* 0x000000020b0c7810 */
/* 0x004fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R9, R12, PT ; /* 0x0000000c0900720c */
/* 0x008fe40003f06070 */
/*0250*/ IADD3 R13, R13, 0x2, RZ ; /* 0x000000020d0d7810 */
/* 0x010fc80007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R9, R13.reuse, PT ; /* 0x0000000d0900720c */
/* 0x080fe40003f26070 */
/*0270*/ ISETP.GE.U32.AND P2, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x000fe40003f46070 */
/*0280*/ SEL R11, RZ, 0x2, !P1 ; /* 0x00000002ff0b7807 */
/* 0x000fc60004800000 */
/*0290*/ @P0 SEL R11, R14, 0x2, !P2 ; /* 0x000000020e0b0807 */
/* 0x000fca0005000000 */
/*02a0*/ IMAD.SHL.U32 R14, R11.reuse, 0x4, RZ ; /* 0x000000040b0e7824 */
/* 0x040fe200078e00ff */
/*02b0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.EQ.AND P1, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f22270 */
/*02d0*/ ISETP.EQ.AND P2, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f42270 */
/*02e0*/ ISETP.EQ.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f02270 */
/*02f0*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R12 ; /* 0x000000ffff091224 */
/* 0x000fe400078e000c */
/*0300*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff092224 */
/* 0x000fc800078e000d */
/*0310*/ IMAD.IADD R15, R15, 0x1, R9 ; /* 0x000000010f0f7824 */
/* 0x020fe400078e0209 */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0011 */
/*0330*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101906 */
/*0340*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e4000c101906 */
/*0350*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0360*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe40007f5e0ff */
/*0390*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*03a0*/ IADD3 R6, P3, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007f7e0ff */
/*03b0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*03c0*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007f3e0ff */
/*03d0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0607 */
/*03f0*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fc800008e0611 */
/*0400*/ @P0 BRA 0x1c0 ; /* 0xfffffdb000000947 */
/* 0x000fea000383ffff */
/*0410*/ IADD3 R2, R2, -0x2, RZ ; /* 0xfffffffe02027810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0450*/ IADD3 R2, R0, c[0x0][0x174], RZ ; /* 0x00005d0000027a10 */
/* 0x000fe20007ffe0ff */
/*0460*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0470*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD R4, R3, c[0x0][0x174], R0 ; /* 0x00005d0003047a24 */
/* 0x000fc600078e0200 */
/*0490*/ IMAD R2, R3, UR4, R2 ; /* 0x0000000403027c24 */
/* 0x000fe4000f8e0202 */
/*04a0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*04b0*/ IMAD.WIDE R6, R2, R13, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x000fc800078e020d */
/*04c0*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x000fe2000f8e0200 */
/*04d0*/ IADD3 R8, P0, R6, 0x4, RZ ; /* 0x0000000406087810 */
/* 0x000fe20007f1e0ff */
/*04e0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*04f0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0005 */
/*0500*/ IMAD.X R9, RZ, RZ, R7, P0 ; /* 0x000000ffff097224 */
/* 0x000fe400000e0607 */
/*0510*/ IMAD.WIDE R2, R3, R13, c[0x2][0x0] ; /* 0x0080000003027625 */
/* 0x000fc800078e020d */
/*0520*/ ISETP.GE.AND P2, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f46270 */
/*0530*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*0540*/ IADD3 R4, P3, R2, UR8, RZ ; /* 0x0000000802047c10 */
/* 0x000fc4000ff7e0ff */
/*0550*/ ISETP.GE.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f06270 */
/*0560*/ ISETP.GE.AND P1, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fe40003f26270 */
/*0570*/ IADD3.X R5, R3, UR9, RZ, P3, !PT ; /* 0x0000000903057c10 */
/* 0x000fca0009ffe4ff */
/*0580*/ @!P2 BRA 0x6f0 ; /* 0x000001600000a947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R10, [R4.64+-0x4] ; /* 0xfffffc06040a7981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000f28000c1e1900 */
/*05c0*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000406080f7981 */
/* 0x000f62000c1e1900 */
/*05d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*05e0*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f46070 */
/*0600*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*0610*/ ISETP.GE.U32.AND P3, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f66070 */
/*0620*/ ISETP.GE.U32.AND P4, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f86070 */
/*0630*/ SEL R13, RZ, 0x2, !P3 ; /* 0x00000002ff0d7807 */
/* 0x000fc60005800000 */
/*0640*/ @P2 SEL R13, R14, 0x2, !P4 ; /* 0x000000020e0d2807 */
/* 0x000fca0006000000 */
/*0650*/ IMAD.SHL.U32 R14, R13.reuse, 0x4, RZ ; /* 0x000000040d0e7824 */
/* 0x040fe200078e00ff */
/*0660*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.EQ.AND P3, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f62270 */
/*0680*/ ISETP.EQ.AND P4, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f82270 */
/*0690*/ ISETP.EQ.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f42270 */
/*06a0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e000b */
/*06b0*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a4224 */
/* 0x000fc800078e000c */
/*06c0*/ IMAD.IADD R15, R15, 0x1, R10 ; /* 0x000000010f0f7824 */
/* 0x020fca00078e020a */
/*06d0*/ STG.E [R8.64+0x4], R15 ; /* 0x0000040f08007986 */
/* 0x0001e8000c101906 */
/*06e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e4000c101906 */
/*06f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0710*/ BSSY B0, 0x8a0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0720*/ @!P0 BRA 0x890 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0730*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ee8000c1e1900 */
/*0750*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000406080c7981 */
/* 0x000f28000c1e1900 */
/*0760*/ LDG.E R15, [R8.64+0x8] ; /* 0x00000806080f7981 */
/* 0x001f62000c1e1900 */
/*0770*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0780*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*0790*/ ISETP.GE.U32.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f06070 */
/*07a0*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*07b0*/ ISETP.GE.U32.AND P2, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f46070 */
/*07c0*/ ISETP.GE.U32.AND P3, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f66070 */
/*07d0*/ SEL R13, RZ, 0x2, !P2 ; /* 0x00000002ff0d7807 */
/* 0x000fc60005000000 */
/*07e0*/ @P0 SEL R13, R14, 0x2, !P3 ; /* 0x000000020e0d0807 */
/* 0x000fca0005800000 */
/*07f0*/ IMAD.SHL.U32 R14, R13.reuse, 0x4, RZ ; /* 0x000000040d0e7824 */
/* 0x040fe200078e00ff */
/*0800*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*0810*/ ISETP.EQ.AND P2, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f42270 */
/*0820*/ ISETP.EQ.AND P3, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f62270 */
/*0830*/ ISETP.EQ.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f02270 */
/*0840*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a2224 */
/* 0x000fe400078e000b */
/*0850*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a3224 */
/* 0x000fc800078e000c */
/*0860*/ IMAD.IADD R15, R15, 0x1, R10 ; /* 0x000000010f0f7824 */
/* 0x020fca00078e020a */
/*0870*/ STG.E [R8.64+0x8], R15 ; /* 0x0000080f08007986 */
/* 0x0001e8000c101906 */
/*0880*/ STG.E [R6.64+0x4], R13 ; /* 0x0000040d06007986 */
/* 0x0001e4000c101906 */
/*0890*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08b0*/ BSSY B0, 0xa40 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*08c0*/ @!P1 BRA 0xa30 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000806040b7981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R12, [R8.64+0x8] ; /* 0x00000806080c7981 */
/* 0x000f28000c1e1900 */
/*0900*/ LDG.E R15, [R8.64+0xc] ; /* 0x00000c06080f7981 */
/* 0x001f62000c1e1900 */
/*0910*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0920*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f06070 */
/*0940*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*0950*/ ISETP.GE.U32.AND P1, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f26070 */
/*0960*/ ISETP.GE.U32.AND P2, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f46070 */
/*0970*/ SEL R13, RZ, 0x2, !P1 ; /* 0x00000002ff0d7807 */
/* 0x000fc60004800000 */
/*0980*/ @P0 SEL R13, R14, 0x2, !P2 ; /* 0x000000020e0d0807 */
/* 0x000fca0005000000 */
/*0990*/ IMAD.SHL.U32 R14, R13.reuse, 0x4, RZ ; /* 0x000000040d0e7824 */
/* 0x040fe200078e00ff */
/*09a0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*09b0*/ ISETP.EQ.AND P1, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f22270 */
/*09c0*/ ISETP.EQ.AND P2, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f42270 */
/*09d0*/ ISETP.EQ.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f02270 */
/*09e0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000b */
/*09f0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a2224 */
/* 0x000fc800078e000c */
/*0a00*/ IMAD.IADD R15, R15, 0x1, R10 ; /* 0x000000010f0f7824 */
/* 0x020fca00078e020a */
/*0a10*/ STG.E [R8.64+0xc], R15 ; /* 0x00000c0f08007986 */
/* 0x0001e8000c101906 */
/*0a20*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x0001e4000c101906 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a50*/ ISETP.GE.AND P0, PT, R0, -0x2, PT ; /* 0xfffffffe0000780c */
/* 0x000fca0003f06270 */
/*0a60*/ BSSY B0, 0xbf0 ; /* 0x0000018000007945 */
/* 0x000ff00003800000 */
/*0a70*/ @!P0 BRA 0xbe0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0a80*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c06040b7981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000806040a7981 */
/* 0x000ee8000c1e1900 */
/*0aa0*/ LDG.E R12, [R8.64+0xc] ; /* 0x00000c06080c7981 */
/* 0x000f28000c1e1900 */
/*0ab0*/ LDG.E R14, [R8.64+0x10] ; /* 0x00001006080e7981 */
/* 0x000f62000c1e1900 */
/*0ac0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x001fe200078e00ff */
/*0ad0*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*0ae0*/ ISETP.GE.U32.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f06070 */
/*0af0*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P1, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f26070 */
/*0b10*/ ISETP.GE.U32.AND P2, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f46070 */
/*0b20*/ SEL R13, RZ, 0x2, !P1 ; /* 0x00000002ff0d7807 */
/* 0x000fc60004800000 */
/*0b30*/ @P0 SEL R13, R15, 0x2, !P2 ; /* 0x000000020f0d0807 */
/* 0x000fca0005000000 */
/*0b40*/ IMAD.SHL.U32 R4, R13.reuse, 0x4, RZ ; /* 0x000000040d047824 */
/* 0x040fe200078e00ff */
/*0b50*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*0b60*/ ISETP.EQ.AND P1, PT, R4.reuse, 0x4, PT ; /* 0x000000040400780c */
/* 0x040fe40003f22270 */
/*0b70*/ ISETP.EQ.AND P2, PT, R4.reuse, 0x8, PT ; /* 0x000000080400780c */
/* 0x040fe40003f42270 */
/*0b80*/ ISETP.EQ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd20003f02270 */
/*0b90*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000b */
/*0ba0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a2224 */
/* 0x000fc800078e000c */
/*0bb0*/ IMAD.IADD R5, R14, 0x1, R10 ; /* 0x000000010e057824 */
/* 0x020fca00078e020a */
/*0bc0*/ STG.E [R8.64+0x10], R5 ; /* 0x0000100508007986 */
/* 0x0001e8000c101906 */
/*0bd0*/ STG.E [R6.64+0xc], R13 ; /* 0x00000c0d06007986 */
/* 0x0001e4000c101906 */
/*0be0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bf0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*0c10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0c20*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x001fe40007f3e0ff */
/*0c30*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0c40*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0c50*/ IADD3 R6, P2, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe20007f5e0ff */
/*0c60*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fc800008e0609 */
/*0c70*/ IMAD.X R11, RZ, RZ, R7, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00010e0607 */
/*0c80*/ @!P0 BRA 0x520 ; /* 0xfffff89000008947 */
/* 0x000fea000383ffff */
/*0c90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ca0*/ BRA 0xca0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <limits.h>
__device__ static inline unsigned int argmin(unsigned int a, unsigned int b, unsigned int c)
{
if (a < b)
{
if (a < c)
return 0;
else
return 2;
}
if (b < c)
return 1;
else return 2;
}
__global__ void matching(int *D, unsigned int *phi, int m, int n)
{
// matrix m x n
int pnt = 2;
const int tid = threadIdx.x;// + blockDim.x * blockIdx.x;
if (tid < m)
{
int j = 0;
int reserve = -threadIdx.x + 1;
for (j = reserve; j < n; j++)
{
if (j >= 1){
int tmp[3] = {D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1]+pnt, D[(tid+1)*(n+1)+j]+pnt};
int arg = argmin(tmp[0], tmp[1], tmp[2]);
int dmin = tmp[arg];
D[(tid+1)*(n+1)+j+1] = D[(tid+1)*(n+1)+j+1] + dmin;
phi[tid * n + j] = arg + 1;
}
__syncthreads();
}
}
}
// if (tid == 2){
// printf("j: %d\n", j);
// printf("idx: %d %d %d %d\n",(tid * (n+1)) + j + 1, (tid * (n+1)) + j + 2, (tid+1)*(n+1)+j+1, (tid+1)*(n+1)+j+2);
// printf("tmp: %d %d %d\n",D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1], D[(tid+1)*(n+1)+j]);
// // printf("min: %d\n", tmp[arg]);
// printf("D[i+1][j+1]: %d\n", D[(tid+1)*(n+1)+j+1]);
// } | .file "tmpxft_00192adf_00000000-6_cu_testing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8matchingPiPjiiPiPjii
.type _Z31__device_stub__Z8matchingPiPjiiPiPjii, @function
_Z31__device_stub__Z8matchingPiPjiiPiPjii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8matchingPiPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8matchingPiPjiiPiPjii, .-_Z31__device_stub__Z8matchingPiPjiiPiPjii
.globl _Z8matchingPiPjii
.type _Z8matchingPiPjii, @function
_Z8matchingPiPjii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8matchingPiPjiiPiPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8matchingPiPjii, .-_Z8matchingPiPjii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8matchingPiPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matchingPiPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <limits.h>
__device__ static inline unsigned int argmin(unsigned int a, unsigned int b, unsigned int c)
{
if (a < b)
{
if (a < c)
return 0;
else
return 2;
}
if (b < c)
return 1;
else return 2;
}
__global__ void matching(int *D, unsigned int *phi, int m, int n)
{
// matrix m x n
int pnt = 2;
const int tid = threadIdx.x;// + blockDim.x * blockIdx.x;
if (tid < m)
{
int j = 0;
int reserve = -threadIdx.x + 1;
for (j = reserve; j < n; j++)
{
if (j >= 1){
int tmp[3] = {D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1]+pnt, D[(tid+1)*(n+1)+j]+pnt};
int arg = argmin(tmp[0], tmp[1], tmp[2]);
int dmin = tmp[arg];
D[(tid+1)*(n+1)+j+1] = D[(tid+1)*(n+1)+j+1] + dmin;
phi[tid * n + j] = arg + 1;
}
__syncthreads();
}
}
}
// if (tid == 2){
// printf("j: %d\n", j);
// printf("idx: %d %d %d %d\n",(tid * (n+1)) + j + 1, (tid * (n+1)) + j + 2, (tid+1)*(n+1)+j+1, (tid+1)*(n+1)+j+2);
// printf("tmp: %d %d %d\n",D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1], D[(tid+1)*(n+1)+j]);
// // printf("min: %d\n", tmp[arg]);
// printf("D[i+1][j+1]: %d\n", D[(tid+1)*(n+1)+j+1]);
// } | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <limits.h>
__device__ static inline unsigned int argmin(unsigned int a, unsigned int b, unsigned int c)
{
if (a < b)
{
if (a < c)
return 0;
else
return 2;
}
if (b < c)
return 1;
else return 2;
}
__global__ void matching(int *D, unsigned int *phi, int m, int n)
{
// matrix m x n
int pnt = 2;
const int tid = threadIdx.x;// + blockDim.x * blockIdx.x;
if (tid < m)
{
int j = 0;
int reserve = -threadIdx.x + 1;
for (j = reserve; j < n; j++)
{
if (j >= 1){
int tmp[3] = {D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1]+pnt, D[(tid+1)*(n+1)+j]+pnt};
int arg = argmin(tmp[0], tmp[1], tmp[2]);
int dmin = tmp[arg];
D[(tid+1)*(n+1)+j+1] = D[(tid+1)*(n+1)+j+1] + dmin;
phi[tid * n + j] = arg + 1;
}
__syncthreads();
}
}
}
// if (tid == 2){
// printf("j: %d\n", j);
// printf("idx: %d %d %d %d\n",(tid * (n+1)) + j + 1, (tid * (n+1)) + j + 2, (tid+1)*(n+1)+j+1, (tid+1)*(n+1)+j+2);
// printf("tmp: %d %d %d\n",D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1], D[(tid+1)*(n+1)+j]);
// // printf("min: %d\n", tmp[arg]);
// printf("D[i+1][j+1]: %d\n", D[(tid+1)*(n+1)+j+1]);
// } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <limits.h>
__device__ static inline unsigned int argmin(unsigned int a, unsigned int b, unsigned int c)
{
if (a < b)
{
if (a < c)
return 0;
else
return 2;
}
if (b < c)
return 1;
else return 2;
}
__global__ void matching(int *D, unsigned int *phi, int m, int n)
{
// matrix m x n
int pnt = 2;
const int tid = threadIdx.x;// + blockDim.x * blockIdx.x;
if (tid < m)
{
int j = 0;
int reserve = -threadIdx.x + 1;
for (j = reserve; j < n; j++)
{
if (j >= 1){
int tmp[3] = {D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1]+pnt, D[(tid+1)*(n+1)+j]+pnt};
int arg = argmin(tmp[0], tmp[1], tmp[2]);
int dmin = tmp[arg];
D[(tid+1)*(n+1)+j+1] = D[(tid+1)*(n+1)+j+1] + dmin;
phi[tid * n + j] = arg + 1;
}
__syncthreads();
}
}
}
// if (tid == 2){
// printf("j: %d\n", j);
// printf("idx: %d %d %d %d\n",(tid * (n+1)) + j + 1, (tid * (n+1)) + j + 2, (tid+1)*(n+1)+j+1, (tid+1)*(n+1)+j+2);
// printf("tmp: %d %d %d\n",D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1], D[(tid+1)*(n+1)+j]);
// // printf("min: %d\n", tmp[arg]);
// printf("D[i+1][j+1]: %d\n", D[(tid+1)*(n+1)+j+1]);
// } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8matchingPiPjii
.globl _Z8matchingPiPjii
.p2align 8
.type _Z8matchingPiPjii,@function
_Z8matchingPiPjii:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[0:1], 0x14
v_sub_nc_u32_e32 v6, 1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v3, 1, v0
s_add_i32 s5, s4, -1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s4, v[3:4]
v_mad_u64_u32 v[2:3], null, v0, s5, 1
v_mad_u64_u32 v[4:5], null, v0, s4, 1
s_mov_b32 s5, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v6, 1, v6
v_add_nc_u32_e32 v2, 1, v2
v_add_nc_u32_e32 v4, 1, v4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
v_cmp_eq_u32_e32 vcc_lo, s4, v6
buffer_gl0_inv
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_6
.LBB0_4:
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0, v6
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v7, v1, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_clause 0x1
global_load_b64 v[11:12], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 2, v10
v_add_nc_u32_e32 v0, 2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_ge_u32_e32 vcc_lo, v9, v0
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 1, v3
v_cndmask_b32_e64 v10, 2, 1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, v9, v5
v_cndmask_b32_e32 v11, v10, v3, vcc_lo
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 1, v11
v_cndmask_b32_e32 v5, v9, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v11
v_lshlrev_b64 v[9:10], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v5, v0, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_nc_u32_e32 v0, v0, v12
v_add_nc_u32_e32 v3, 1, v11
global_store_b32 v[7:8], v0, off offset:4
global_store_b32 v[9:10], v3, off
s_branch .LBB0_3
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8matchingPiPjii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8matchingPiPjii, .Lfunc_end0-_Z8matchingPiPjii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8matchingPiPjii
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z8matchingPiPjii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <limits.h>
__device__ static inline unsigned int argmin(unsigned int a, unsigned int b, unsigned int c)
{
if (a < b)
{
if (a < c)
return 0;
else
return 2;
}
if (b < c)
return 1;
else return 2;
}
__global__ void matching(int *D, unsigned int *phi, int m, int n)
{
// matrix m x n
int pnt = 2;
const int tid = threadIdx.x;// + blockDim.x * blockIdx.x;
if (tid < m)
{
int j = 0;
int reserve = -threadIdx.x + 1;
for (j = reserve; j < n; j++)
{
if (j >= 1){
int tmp[3] = {D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1]+pnt, D[(tid+1)*(n+1)+j]+pnt};
int arg = argmin(tmp[0], tmp[1], tmp[2]);
int dmin = tmp[arg];
D[(tid+1)*(n+1)+j+1] = D[(tid+1)*(n+1)+j+1] + dmin;
phi[tid * n + j] = arg + 1;
}
__syncthreads();
}
}
}
// if (tid == 2){
// printf("j: %d\n", j);
// printf("idx: %d %d %d %d\n",(tid * (n+1)) + j + 1, (tid * (n+1)) + j + 2, (tid+1)*(n+1)+j+1, (tid+1)*(n+1)+j+2);
// printf("tmp: %d %d %d\n",D[(tid * (n+1)) + j], D[(tid * (n+1)) + j + 1], D[(tid+1)*(n+1)+j]);
// // printf("min: %d\n", tmp[arg]);
// printf("D[i+1][j+1]: %d\n", D[(tid+1)*(n+1)+j+1]);
// } | .text
.file "cu_testing.hip"
.globl _Z23__device_stub__matchingPiPjii # -- Begin function _Z23__device_stub__matchingPiPjii
.p2align 4, 0x90
.type _Z23__device_stub__matchingPiPjii,@function
_Z23__device_stub__matchingPiPjii: # @_Z23__device_stub__matchingPiPjii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8matchingPiPjii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__matchingPiPjii, .Lfunc_end0-_Z23__device_stub__matchingPiPjii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matchingPiPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8matchingPiPjii,@object # @_Z8matchingPiPjii
.section .rodata,"a",@progbits
.globl _Z8matchingPiPjii
.p2align 3, 0x0
_Z8matchingPiPjii:
.quad _Z23__device_stub__matchingPiPjii
.size _Z8matchingPiPjii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8matchingPiPjii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__matchingPiPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8matchingPiPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8matchingPiPjii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x001fda0003f06270 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IADD3 R0, -R3, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x000fc80007ffe1ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R3, c[0x0][0x174], RZ ; /* 0x00005d0003027a10 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ LOP3.LUT P0, R10, R4, 0x3, RZ, 0xc0, !PT ; /* 0x00000003040a7812 */
/* 0x000fda000780c0ff */
/*00c0*/ @!P0 BRA 0x410 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*0100*/ IADD3 R4, R6, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R5, R5, R6.reuse, 0x2 ; /* 0x0000000205057424 */
/* 0x080fe400078e0206 */
/*0120*/ IMAD R6, R3, R6, 0x1 ; /* 0x0000000103067424 */
/* 0x000fe400078e0206 */
/*0130*/ IMAD R8, R4, R3, 0x1 ; /* 0x0000000104087424 */
/* 0x000fe400078e0203 */
/*0140*/ IMAD.WIDE R4, R5, R9, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0209 */
/*0150*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0209 */
/*0160*/ IADD3 R4, P0, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007f1e0ff */
/*0170*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0209 */
/*0180*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007f3e0ff */
/*0190*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe400000e0605 */
/*01a0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, R9 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0009 */
/*01c0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*01d0*/ @!P0 BRA 0x350 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R11, [R6.64] ; /* 0x00000006060b7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R9, [R6.64+-0x4] ; /* 0xfffffc0606097981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc06040d7981 */
/* 0x000f28000c1e1900 */
/*0210*/ LDG.E R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000f62000c1e1900 */
/*0220*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0230*/ IADD3 R12, R11, 0x2, RZ ; /* 0x000000020b0c7810 */
/* 0x004fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R9, R12, PT ; /* 0x0000000c0900720c */
/* 0x008fe40003f06070 */
/*0250*/ IADD3 R13, R13, 0x2, RZ ; /* 0x000000020d0d7810 */
/* 0x010fc80007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P1, PT, R9, R13.reuse, PT ; /* 0x0000000d0900720c */
/* 0x080fe40003f26070 */
/*0270*/ ISETP.GE.U32.AND P2, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x000fe40003f46070 */
/*0280*/ SEL R11, RZ, 0x2, !P1 ; /* 0x00000002ff0b7807 */
/* 0x000fc60004800000 */
/*0290*/ @P0 SEL R11, R14, 0x2, !P2 ; /* 0x000000020e0b0807 */
/* 0x000fca0005000000 */
/*02a0*/ IMAD.SHL.U32 R14, R11.reuse, 0x4, RZ ; /* 0x000000040b0e7824 */
/* 0x040fe200078e00ff */
/*02b0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.EQ.AND P1, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f22270 */
/*02d0*/ ISETP.EQ.AND P2, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f42270 */
/*02e0*/ ISETP.EQ.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f02270 */
/*02f0*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R12 ; /* 0x000000ffff091224 */
/* 0x000fe400078e000c */
/*0300*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff092224 */
/* 0x000fc800078e000d */
/*0310*/ IMAD.IADD R15, R15, 0x1, R9 ; /* 0x000000010f0f7824 */
/* 0x020fe400078e0209 */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0011 */
/*0330*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101906 */
/*0340*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e4000c101906 */
/*0350*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0360*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe40007f5e0ff */
/*0390*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*03a0*/ IADD3 R6, P3, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007f7e0ff */
/*03b0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*03c0*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007f3e0ff */
/*03d0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0607 */
/*03f0*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fc800008e0611 */
/*0400*/ @P0 BRA 0x1c0 ; /* 0xfffffdb000000947 */
/* 0x000fea000383ffff */
/*0410*/ IADD3 R2, R2, -0x2, RZ ; /* 0xfffffffe02027810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0450*/ IADD3 R2, R0, c[0x0][0x174], RZ ; /* 0x00005d0000027a10 */
/* 0x000fe20007ffe0ff */
/*0460*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0470*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD R4, R3, c[0x0][0x174], R0 ; /* 0x00005d0003047a24 */
/* 0x000fc600078e0200 */
/*0490*/ IMAD R2, R3, UR4, R2 ; /* 0x0000000403027c24 */
/* 0x000fe4000f8e0202 */
/*04a0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*04b0*/ IMAD.WIDE R6, R2, R13, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x000fc800078e020d */
/*04c0*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x000fe2000f8e0200 */
/*04d0*/ IADD3 R8, P0, R6, 0x4, RZ ; /* 0x0000000406087810 */
/* 0x000fe20007f1e0ff */
/*04e0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*04f0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0005 */
/*0500*/ IMAD.X R9, RZ, RZ, R7, P0 ; /* 0x000000ffff097224 */
/* 0x000fe400000e0607 */
/*0510*/ IMAD.WIDE R2, R3, R13, c[0x2][0x0] ; /* 0x0080000003027625 */
/* 0x000fc800078e020d */
/*0520*/ ISETP.GE.AND P2, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f46270 */
/*0530*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*0540*/ IADD3 R4, P3, R2, UR8, RZ ; /* 0x0000000802047c10 */
/* 0x000fc4000ff7e0ff */
/*0550*/ ISETP.GE.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f06270 */
/*0560*/ ISETP.GE.AND P1, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x000fe40003f26270 */
/*0570*/ IADD3.X R5, R3, UR9, RZ, P3, !PT ; /* 0x0000000903057c10 */
/* 0x000fca0009ffe4ff */
/*0580*/ @!P2 BRA 0x6f0 ; /* 0x000001600000a947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R10, [R4.64+-0x4] ; /* 0xfffffc06040a7981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000f28000c1e1900 */
/*05c0*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000406080f7981 */
/* 0x000f62000c1e1900 */
/*05d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*05e0*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f46070 */
/*0600*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*0610*/ ISETP.GE.U32.AND P3, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f66070 */
/*0620*/ ISETP.GE.U32.AND P4, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f86070 */
/*0630*/ SEL R13, RZ, 0x2, !P3 ; /* 0x00000002ff0d7807 */
/* 0x000fc60005800000 */
/*0640*/ @P2 SEL R13, R14, 0x2, !P4 ; /* 0x000000020e0d2807 */
/* 0x000fca0006000000 */
/*0650*/ IMAD.SHL.U32 R14, R13.reuse, 0x4, RZ ; /* 0x000000040d0e7824 */
/* 0x040fe200078e00ff */
/*0660*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.EQ.AND P3, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f62270 */
/*0680*/ ISETP.EQ.AND P4, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f82270 */
/*0690*/ ISETP.EQ.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f42270 */
/*06a0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e000b */
/*06b0*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a4224 */
/* 0x000fc800078e000c */
/*06c0*/ IMAD.IADD R15, R15, 0x1, R10 ; /* 0x000000010f0f7824 */
/* 0x020fca00078e020a */
/*06d0*/ STG.E [R8.64+0x4], R15 ; /* 0x0000040f08007986 */
/* 0x0001e8000c101906 */
/*06e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e4000c101906 */
/*06f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0710*/ BSSY B0, 0x8a0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0720*/ @!P0 BRA 0x890 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0730*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ee8000c1e1900 */
/*0750*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000406080c7981 */
/* 0x000f28000c1e1900 */
/*0760*/ LDG.E R15, [R8.64+0x8] ; /* 0x00000806080f7981 */
/* 0x001f62000c1e1900 */
/*0770*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0780*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*0790*/ ISETP.GE.U32.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f06070 */
/*07a0*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*07b0*/ ISETP.GE.U32.AND P2, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f46070 */
/*07c0*/ ISETP.GE.U32.AND P3, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f66070 */
/*07d0*/ SEL R13, RZ, 0x2, !P2 ; /* 0x00000002ff0d7807 */
/* 0x000fc60005000000 */
/*07e0*/ @P0 SEL R13, R14, 0x2, !P3 ; /* 0x000000020e0d0807 */
/* 0x000fca0005800000 */
/*07f0*/ IMAD.SHL.U32 R14, R13.reuse, 0x4, RZ ; /* 0x000000040d0e7824 */
/* 0x040fe200078e00ff */
/*0800*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*0810*/ ISETP.EQ.AND P2, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f42270 */
/*0820*/ ISETP.EQ.AND P3, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f62270 */
/*0830*/ ISETP.EQ.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f02270 */
/*0840*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a2224 */
/* 0x000fe400078e000b */
/*0850*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a3224 */
/* 0x000fc800078e000c */
/*0860*/ IMAD.IADD R15, R15, 0x1, R10 ; /* 0x000000010f0f7824 */
/* 0x020fca00078e020a */
/*0870*/ STG.E [R8.64+0x8], R15 ; /* 0x0000080f08007986 */
/* 0x0001e8000c101906 */
/*0880*/ STG.E [R6.64+0x4], R13 ; /* 0x0000040d06007986 */
/* 0x0001e4000c101906 */
/*0890*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08b0*/ BSSY B0, 0xa40 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*08c0*/ @!P1 BRA 0xa30 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000806040b7981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R12, [R8.64+0x8] ; /* 0x00000806080c7981 */
/* 0x000f28000c1e1900 */
/*0900*/ LDG.E R15, [R8.64+0xc] ; /* 0x00000c06080f7981 */
/* 0x001f62000c1e1900 */
/*0910*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0920*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f06070 */
/*0940*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*0950*/ ISETP.GE.U32.AND P1, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f26070 */
/*0960*/ ISETP.GE.U32.AND P2, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f46070 */
/*0970*/ SEL R13, RZ, 0x2, !P1 ; /* 0x00000002ff0d7807 */
/* 0x000fc60004800000 */
/*0980*/ @P0 SEL R13, R14, 0x2, !P2 ; /* 0x000000020e0d0807 */
/* 0x000fca0005000000 */
/*0990*/ IMAD.SHL.U32 R14, R13.reuse, 0x4, RZ ; /* 0x000000040d0e7824 */
/* 0x040fe200078e00ff */
/*09a0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*09b0*/ ISETP.EQ.AND P1, PT, R14.reuse, 0x4, PT ; /* 0x000000040e00780c */
/* 0x040fe40003f22270 */
/*09c0*/ ISETP.EQ.AND P2, PT, R14.reuse, 0x8, PT ; /* 0x000000080e00780c */
/* 0x040fe40003f42270 */
/*09d0*/ ISETP.EQ.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd20003f02270 */
/*09e0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000b */
/*09f0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a2224 */
/* 0x000fc800078e000c */
/*0a00*/ IMAD.IADD R15, R15, 0x1, R10 ; /* 0x000000010f0f7824 */
/* 0x020fca00078e020a */
/*0a10*/ STG.E [R8.64+0xc], R15 ; /* 0x00000c0f08007986 */
/* 0x0001e8000c101906 */
/*0a20*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x0001e4000c101906 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a50*/ ISETP.GE.AND P0, PT, R0, -0x2, PT ; /* 0xfffffffe0000780c */
/* 0x000fca0003f06270 */
/*0a60*/ BSSY B0, 0xbf0 ; /* 0x0000018000007945 */
/* 0x000ff00003800000 */
/*0a70*/ @!P0 BRA 0xbe0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0a80*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c06040b7981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000806040a7981 */
/* 0x000ee8000c1e1900 */
/*0aa0*/ LDG.E R12, [R8.64+0xc] ; /* 0x00000c06080c7981 */
/* 0x000f28000c1e1900 */
/*0ab0*/ LDG.E R14, [R8.64+0x10] ; /* 0x00001006080e7981 */
/* 0x000f62000c1e1900 */
/*0ac0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x001fe200078e00ff */
/*0ad0*/ IADD3 R11, R11, 0x2, RZ ; /* 0x000000020b0b7810 */
/* 0x004fc80007ffe0ff */
/*0ae0*/ ISETP.GE.U32.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x008fe40003f06070 */
/*0af0*/ IADD3 R12, R12, 0x2, RZ ; /* 0x000000020c0c7810 */
/* 0x010fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P1, PT, R10, R12.reuse, PT ; /* 0x0000000c0a00720c */
/* 0x080fe40003f26070 */
/*0b10*/ ISETP.GE.U32.AND P2, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f46070 */
/*0b20*/ SEL R13, RZ, 0x2, !P1 ; /* 0x00000002ff0d7807 */
/* 0x000fc60004800000 */
/*0b30*/ @P0 SEL R13, R15, 0x2, !P2 ; /* 0x000000020f0d0807 */
/* 0x000fca0005000000 */
/*0b40*/ IMAD.SHL.U32 R4, R13.reuse, 0x4, RZ ; /* 0x000000040d047824 */
/* 0x040fe200078e00ff */
/*0b50*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc80007ffe0ff */
/*0b60*/ ISETP.EQ.AND P1, PT, R4.reuse, 0x4, PT ; /* 0x000000040400780c */
/* 0x040fe40003f22270 */
/*0b70*/ ISETP.EQ.AND P2, PT, R4.reuse, 0x8, PT ; /* 0x000000080400780c */
/* 0x040fe40003f42270 */
/*0b80*/ ISETP.EQ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd20003f02270 */
/*0b90*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000b */
/*0ba0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a2224 */
/* 0x000fc800078e000c */
/*0bb0*/ IMAD.IADD R5, R14, 0x1, R10 ; /* 0x000000010e057824 */
/* 0x020fca00078e020a */
/*0bc0*/ STG.E [R8.64+0x10], R5 ; /* 0x0000100508007986 */
/* 0x0001e8000c101906 */
/*0bd0*/ STG.E [R6.64+0xc], R13 ; /* 0x00000c0d06007986 */
/* 0x0001e4000c101906 */
/*0be0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bf0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*0c10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0c20*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x001fe40007f3e0ff */
/*0c30*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0c40*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0c50*/ IADD3 R6, P2, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe20007f5e0ff */
/*0c60*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fc800008e0609 */
/*0c70*/ IMAD.X R11, RZ, RZ, R7, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00010e0607 */
/*0c80*/ @!P0 BRA 0x520 ; /* 0xfffff89000008947 */
/* 0x000fea000383ffff */
/*0c90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ca0*/ BRA 0xca0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8matchingPiPjii
.globl _Z8matchingPiPjii
.p2align 8
.type _Z8matchingPiPjii,@function
_Z8matchingPiPjii:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[0:1], 0x14
v_sub_nc_u32_e32 v6, 1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v3, 1, v0
s_add_i32 s5, s4, -1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s4, v[3:4]
v_mad_u64_u32 v[2:3], null, v0, s5, 1
v_mad_u64_u32 v[4:5], null, v0, s4, 1
s_mov_b32 s5, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v6, 1, v6
v_add_nc_u32_e32 v2, 1, v2
v_add_nc_u32_e32 v4, 1, v4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
v_cmp_eq_u32_e32 vcc_lo, s4, v6
buffer_gl0_inv
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_6
.LBB0_4:
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0, v6
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v7, v1, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_clause 0x1
global_load_b64 v[11:12], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 2, v10
v_add_nc_u32_e32 v0, 2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_ge_u32_e32 vcc_lo, v9, v0
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 1, v3
v_cndmask_b32_e64 v10, 2, 1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, v9, v5
v_cndmask_b32_e32 v11, v10, v3, vcc_lo
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 1, v11
v_cndmask_b32_e32 v5, v9, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v11
v_lshlrev_b64 v[9:10], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v5, v0, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_nc_u32_e32 v0, v0, v12
v_add_nc_u32_e32 v3, 1, v11
global_store_b32 v[7:8], v0, off offset:4
global_store_b32 v[9:10], v3, off
s_branch .LBB0_3
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8matchingPiPjii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8matchingPiPjii, .Lfunc_end0-_Z8matchingPiPjii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8matchingPiPjii
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z8matchingPiPjii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00192adf_00000000-6_cu_testing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8matchingPiPjiiPiPjii
.type _Z31__device_stub__Z8matchingPiPjiiPiPjii, @function
_Z31__device_stub__Z8matchingPiPjiiPiPjii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8matchingPiPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8matchingPiPjiiPiPjii, .-_Z31__device_stub__Z8matchingPiPjiiPiPjii
.globl _Z8matchingPiPjii
.type _Z8matchingPiPjii, @function
_Z8matchingPiPjii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8matchingPiPjiiPiPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8matchingPiPjii, .-_Z8matchingPiPjii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8matchingPiPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matchingPiPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cu_testing.hip"
.globl _Z23__device_stub__matchingPiPjii # -- Begin function _Z23__device_stub__matchingPiPjii
.p2align 4, 0x90
.type _Z23__device_stub__matchingPiPjii,@function
_Z23__device_stub__matchingPiPjii: # @_Z23__device_stub__matchingPiPjii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8matchingPiPjii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__matchingPiPjii, .Lfunc_end0-_Z23__device_stub__matchingPiPjii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matchingPiPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8matchingPiPjii,@object # @_Z8matchingPiPjii
.section .rodata,"a",@progbits
.globl _Z8matchingPiPjii
.p2align 3, 0x0
_Z8matchingPiPjii:
.quad _Z23__device_stub__matchingPiPjii
.size _Z8matchingPiPjii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8matchingPiPjii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__matchingPiPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8matchingPiPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <cuda_profiler_api.h>
#include <assert.h>
#define min(x,y) (y + ((x - y) & ((x - y) >> (sizeof(long) * 8 - 1))))
const int Tile_Width = 1;
const int WIDTH = 3;
void print_matrix(long *m) {
for (int i = 0; i < WIDTH; i++)
for (int j = 0; j < WIDTH; j++)
printf("%ld%c", m[i * WIDTH + j], " \n"[j == WIDTH-1]);
printf("\n");
}
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
__global__ void reduction(long* Pd, long* Nd, int ndsize) {
long Pvalue = LONG_MAX;
int i = blockIdx.y * Tile_Width + threadIdx.y;
int j = blockIdx.x * Tile_Width + threadIdx.x;
for (int k = 0; k < ndsize; ++k) {
Pvalue = min(Pvalue, Nd[k * WIDTH * WIDTH + i * WIDTH + j]);
}
Pd[i * WIDTH + j] = Pvalue;
}
void *emalloc(size_t size) {
void *memory = malloc(size);
if (!memory) {
fprintf(stderr, "ERROR: Failed to malloc.\n");
exit(1);
}
return memory;
}
void file_to_matrix(FILE *path_matr, long* m, int ind) {
/*Reads a file and get the matrix 3x3 from it*/
// Creating matrix
char line[20];
fscanf(path_matr, " %[^\n]", line);
// Filling matrix
for (int i = 0; i < WIDTH; i++) {
for (int j = 0; j < WIDTH; j++) {
fscanf(path_matr, "%ld", &m[(ind * WIDTH * WIDTH) + i * WIDTH + j]);
}
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix file>\n", argv[0]);
return EXIT_FAILURE;
}
FILE *path_matr = fopen(argv[1], "r");
if (path_matr == NULL) {
fprintf(stderr, "ERROR: Invalid file to matrices.\n");
exit(1);
}
int n_matr; // Number of matrices
fscanf(path_matr, "%d", &n_matr);
long* M = (long*) emalloc(n_matr * WIDTH * WIDTH * sizeof(long*));
long* P = (long*) emalloc(WIDTH * WIDTH * sizeof(long));
for (int i = 0; i < n_matr; i++) {
file_to_matrix(path_matr, M, i);
}
checkCuda( cudaSetDevice(0) );
cudaDeviceReset();
// allocate device matrices (linearized)
//printf("Allocate device matrices (linearized)...\n");
long* Nd = NULL;
long* Pd = NULL;
checkCuda( cudaMalloc((void**) &Nd, n_matr * WIDTH * WIDTH * sizeof(long)) );
checkCuda( cudaMalloc((void**) &Pd, WIDTH * WIDTH * sizeof(long)) );
struct timeval begin, end;
gettimeofday(&begin, NULL);
// copy host memory to device
// cudaMemcpy -> faz copias de vetores do host para o device
checkCuda( cudaMemcpy(Nd, M, n_matr * WIDTH * WIDTH * sizeof(long), cudaMemcpyHostToDevice) );
checkCuda( cudaMemcpy(Pd, P, WIDTH * WIDTH * sizeof(long), cudaMemcpyHostToDevice) );
// execute the kernel
printf("Execute the kernel...\n");
int GridSize = (WIDTH + Tile_Width-1) / Tile_Width;
dim3 gridDim(GridSize, GridSize);
dim3 blockDim(Tile_Width, Tile_Width);
cudaProfilerStart();
reduction<<< gridDim, blockDim >>>(Pd, Nd, n_matr);
cudaProfilerStop();
// copy result from device to host
checkCuda( cudaMemcpy( P, Pd, WIDTH * WIDTH * sizeof(long),cudaMemcpyDeviceToHost) );
gettimeofday(&end, NULL);
double gpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
gpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("Execution Time (microseconds): %9.2f\n", gpuTime);
print_matrix(P);
// clean up memory
free(M);
free(P);
checkCuda( cudaFree(Nd) );
checkCuda( cudaFree(Pd) );
return 0;
} | code for sm_80
Function : _Z9reductionPlS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0080*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*0090*/ IADD3 R2, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x001fe4000fffe0ff */
/*00a0*/ IADD3 R5, R5, UR5, RZ ; /* 0x0000000505057c10 */
/* 0x002fe2000fffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00c0*/ @!P0 BRA 0x550 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R0, R4.reuse, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff037424 */
/* 0x000fe200078e00ff */
/*00f0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f05270 */
/*0140*/ @!P1 BRA 0x430 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R12, R2, 0x3, R5 ; /* 0x00000003020c7824 */
/* 0x000fe200078e0205 */
/*0160*/ IADD3 R9, R4, -c[0x0][0x170], RZ ; /* 0x80005c0004097a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff037424 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R12, R12, 0x1b, RZ ; /* 0x0000001b0c0c7810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*01b0*/ IADD3 R16, R12, -0x1b, RZ ; /* 0xffffffe50c107810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; /* 0x00000008ff137424 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.WIDE R16, R16, R19, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fcc00078e0213 */
/*01e0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ IADD3 R18, R12, -0x12, RZ ; /* 0xffffffee0c127810 */
/* 0x000fca0007ffe0ff */
/*0200*/ IMAD.WIDE R18, R18, R19, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fca00078e0213 */
/*0210*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ee8000c1e1b00 */
/*0220*/ LDG.E.64 R10, [R18.64+0x48] ; /* 0x00004804120a7981 */
/* 0x000f28000c1e1b00 */
/*0230*/ LDG.E.64 R6, [R18.64+0x90] ; /* 0x0000900412067981 */
/* 0x000f62000c1e1b00 */
/*0240*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R12, R12, 0x24, RZ ; /* 0x000000240c0c7810 */
/* 0x000fc40007ffe0ff */
/*0260*/ IADD3 R0, P1, -R16, R0, RZ ; /* 0x0000000010007210 */
/* 0x004fca0007f3e1ff */
/*0270*/ IMAD.X R20, R3, 0x1, ~R17, P1 ; /* 0x0000000103147824 */
/* 0x000fca00008e0e11 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1f, R20.reuse ; /* 0x0000001fff037819 */
/* 0x100fe40000011414 */
/*0290*/ SHF.R.S32.HI R13, RZ, 0x1f, R20 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011414 */
/*02a0*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*02b0*/ LOP3.LUT R13, R13, R20, RZ, 0xc0, !PT ; /* 0x000000140d0d7212 */
/* 0x000fe400078ec0ff */
/*02c0*/ IADD3 R0, P1, P2, -R14, R3, R16 ; /* 0x000000030e007210 */
/* 0x008fc80007a3e110 */
/*02d0*/ IADD3.X R16, ~R15, R13, R17, P1, P2 ; /* 0x0000000d0f107210 */
/* 0x000fc80000fe4511 */
/*02e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R16.reuse ; /* 0x0000001fff037819 */
/* 0x100fe40000011410 */
/*02f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R16 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011410 */
/*0300*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*0310*/ LOP3.LUT R13, R13, R16, RZ, 0xc0, !PT ; /* 0x000000100d0d7212 */
/* 0x000fe400078ec0ff */
/*0320*/ IADD3 R0, P1, P2, -R10, R3, R14 ; /* 0x000000030a007210 */
/* 0x010fc80007a3e10e */
/*0330*/ IADD3.X R14, ~R11, R13, R15, P1, P2 ; /* 0x0000000d0b0e7210 */
/* 0x000fc80000fe450f */
/*0340*/ SHF.R.S32.HI R3, RZ, 0x1f, R14.reuse ; /* 0x0000001fff037819 */
/* 0x100fe4000001140e */
/*0350*/ SHF.R.S32.HI R13, RZ, 0x1f, R14 ; /* 0x0000001fff0d7819 */
/* 0x000fe4000001140e */
/*0360*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*0370*/ LOP3.LUT R13, R13, R14, RZ, 0xc0, !PT ; /* 0x0000000e0d0d7212 */
/* 0x000fe400078ec0ff */
/*0380*/ IADD3 R0, P1, P2, -R6, R3, R10 ; /* 0x0000000306007210 */
/* 0x020fc80007a3e10a */
/*0390*/ IADD3.X R11, ~R7, R13, R11, P1, P2 ; /* 0x0000000d070b7210 */
/* 0x000fe20000fe450b */
/*03a0*/ IMAD.IADD R13, R9, 0x1, R8 ; /* 0x00000001090d7824 */
/* 0x000fc600078e0208 */
/*03b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R11.reuse ; /* 0x0000001fff037819 */
/* 0x100fe4000001140b */
/*03c0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f25270 */
/*03d0*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*03e0*/ SHF.R.S32.HI R10, RZ, 0x1f, R11 ; /* 0x0000001fff0a7819 */
/* 0x000fe4000001140b */
/*03f0*/ IADD3 R0, P2, R6, R3, RZ ; /* 0x0000000306007210 */
/* 0x000fe40007f5e0ff */
/*0400*/ LOP3.LUT R3, R10, R11, RZ, 0xc0, !PT ; /* 0x0000000b0a037212 */
/* 0x000fca00078ec0ff */
/*0410*/ IMAD.X R3, R7, 0x1, R3, P2 ; /* 0x0000000107037824 */
/* 0x000fe200010e0603 */
/*0420*/ @P1 BRA 0x1b0 ; /* 0xfffffd8000001947 */
/* 0x000fea000383ffff */
/*0430*/ @!P0 BRA 0x550 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD R7, R8, 0x9, R5 ; /* 0x0000000908077824 */
/* 0x000fc800078e0205 */
/*0450*/ IMAD R8, R2, 0x3, R7 ; /* 0x0000000302087824 */
/* 0x000fe400078e0207 */
/*0460*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0470*/ IMAD.WIDE R6, R8, R7, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fcc00078e0207 */
/*0480*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0490*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ IADD3 R8, R8, 0x9, RZ ; /* 0x0000000908087810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R0, P0, -R6, R0, RZ ; /* 0x0000000006007210 */
/* 0x004fca0007f1e1ff */
/*04c0*/ IMAD.X R10, R3, 0x1, ~R7, P0 ; /* 0x00000001030a7824 */
/* 0x000fe200000e0e07 */
/*04d0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*04e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R10.reuse ; /* 0x0000001fff037819 */
/* 0x100fe4000001140a */
/*04f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R10 ; /* 0x0000001fff097819 */
/* 0x000fe4000001140a */
/*0500*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fc800078ec0ff */
/*0510*/ IADD3 R0, P1, R6, R3, RZ ; /* 0x0000000306007210 */
/* 0x000fe40007f3e0ff */
/*0520*/ LOP3.LUT R3, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09037212 */
/* 0x000fca00078ec0ff */
/*0530*/ IMAD.X R3, R7, 0x1, R3, P1 ; /* 0x0000000107037824 */
/* 0x000fe200008e0603 */
/*0540*/ @P0 BRA 0x460 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD R5, R2, 0x3, R5 ; /* 0x0000000302057824 */
/* 0x000fe400078e0205 */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0580*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0204 */
/*0590*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <cuda_profiler_api.h>
#include <assert.h>
#define min(x,y) (y + ((x - y) & ((x - y) >> (sizeof(long) * 8 - 1))))
const int Tile_Width = 1;
const int WIDTH = 3;
void print_matrix(long *m) {
for (int i = 0; i < WIDTH; i++)
for (int j = 0; j < WIDTH; j++)
printf("%ld%c", m[i * WIDTH + j], " \n"[j == WIDTH-1]);
printf("\n");
}
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
__global__ void reduction(long* Pd, long* Nd, int ndsize) {
long Pvalue = LONG_MAX;
int i = blockIdx.y * Tile_Width + threadIdx.y;
int j = blockIdx.x * Tile_Width + threadIdx.x;
for (int k = 0; k < ndsize; ++k) {
Pvalue = min(Pvalue, Nd[k * WIDTH * WIDTH + i * WIDTH + j]);
}
Pd[i * WIDTH + j] = Pvalue;
}
void *emalloc(size_t size) {
void *memory = malloc(size);
if (!memory) {
fprintf(stderr, "ERROR: Failed to malloc.\n");
exit(1);
}
return memory;
}
void file_to_matrix(FILE *path_matr, long* m, int ind) {
/*Reads a file and get the matrix 3x3 from it*/
// Creating matrix
char line[20];
fscanf(path_matr, " %[^\n]", line);
// Filling matrix
for (int i = 0; i < WIDTH; i++) {
for (int j = 0; j < WIDTH; j++) {
fscanf(path_matr, "%ld", &m[(ind * WIDTH * WIDTH) + i * WIDTH + j]);
}
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix file>\n", argv[0]);
return EXIT_FAILURE;
}
FILE *path_matr = fopen(argv[1], "r");
if (path_matr == NULL) {
fprintf(stderr, "ERROR: Invalid file to matrices.\n");
exit(1);
}
int n_matr; // Number of matrices
fscanf(path_matr, "%d", &n_matr);
long* M = (long*) emalloc(n_matr * WIDTH * WIDTH * sizeof(long*));
long* P = (long*) emalloc(WIDTH * WIDTH * sizeof(long));
for (int i = 0; i < n_matr; i++) {
file_to_matrix(path_matr, M, i);
}
checkCuda( cudaSetDevice(0) );
cudaDeviceReset();
// allocate device matrices (linearized)
//printf("Allocate device matrices (linearized)...\n");
long* Nd = NULL;
long* Pd = NULL;
checkCuda( cudaMalloc((void**) &Nd, n_matr * WIDTH * WIDTH * sizeof(long)) );
checkCuda( cudaMalloc((void**) &Pd, WIDTH * WIDTH * sizeof(long)) );
struct timeval begin, end;
gettimeofday(&begin, NULL);
// copy host memory to device
// cudaMemcpy -> faz copias de vetores do host para o device
checkCuda( cudaMemcpy(Nd, M, n_matr * WIDTH * WIDTH * sizeof(long), cudaMemcpyHostToDevice) );
checkCuda( cudaMemcpy(Pd, P, WIDTH * WIDTH * sizeof(long), cudaMemcpyHostToDevice) );
// execute the kernel
printf("Execute the kernel...\n");
int GridSize = (WIDTH + Tile_Width-1) / Tile_Width;
dim3 gridDim(GridSize, GridSize);
dim3 blockDim(Tile_Width, Tile_Width);
cudaProfilerStart();
reduction<<< gridDim, blockDim >>>(Pd, Nd, n_matr);
cudaProfilerStop();
// copy result from device to host
checkCuda( cudaMemcpy( P, Pd, WIDTH * WIDTH * sizeof(long),cudaMemcpyDeviceToHost) );
gettimeofday(&end, NULL);
double gpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
gpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("Execution Time (microseconds): %9.2f\n", gpuTime);
print_matrix(P);
// clean up memory
free(M);
free(P);
checkCuda( cudaFree(Nd) );
checkCuda( cudaFree(Pd) );
return 0;
} | .file "tmpxft_001075ea_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%ld%c"
.LC2:
.string "\n"
.LC0:
.string " \n"
.text
.globl _Z12print_matrixPl
.type _Z12print_matrixPl, @function
_Z12print_matrixPl:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r12
jmp .L4
.L9:
addl $3, %r14d
addq $24, %rbp
cmpl $9, %r14d
je .L6
.L4:
movl $0, %ebx
.L5:
cmpl $2, %ebx
sete %al
movzbl %al, %eax
movsbl 0(%r13,%rax), %ecx
movq 0(%rbp,%rbx,8), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
jmp .L9
.L6:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPl, .-_Z12print_matrixPl
.section .rodata.str1.1
.LC3:
.string "ERROR: Failed to malloc.\n"
.text
.globl _Z7emallocm
.type _Z7emallocm, @function
_Z7emallocm:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call malloc@PLT
testq %rax, %rax
je .L13
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z7emallocm, .-_Z7emallocm
.section .rodata.str1.1
.LC4:
.string " %[^\n]"
.LC5:
.string "%ld"
.text
.globl _Z14file_to_matrixP8_IO_FILEPli
.type _Z14file_to_matrixP8_IO_FILEPli, @function
_Z14file_to_matrixP8_IO_FILEPli:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %rbp
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdx
leaq .LC4(%rip), %rsi
call __isoc23_fscanf@PLT
leal (%rbx,%rbx,8), %r15d
movl %r15d, %r14d
movslq %r15d, %rax
leaq 24(%rbp,%rax,8), %rbp
addl $9, %r15d
leaq .LC5(%rip), %r13
jmp .L15
.L21:
addl $3, %r14d
addq $24, %rbp
cmpl %r15d, %r14d
je .L14
.L15:
leaq -24(%rbp), %rbx
.L16:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L16
jmp .L21
.L14:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z14file_to_matrixP8_IO_FILEPli, .-_Z14file_to_matrixP8_IO_FILEPli
.globl _Z31__device_stub__Z9reductionPlS_iPlS_i
.type _Z31__device_stub__Z9reductionPlS_iPlS_i, @function
_Z31__device_stub__Z9reductionPlS_iPlS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPlS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z31__device_stub__Z9reductionPlS_iPlS_i, .-_Z31__device_stub__Z9reductionPlS_iPlS_i
.globl _Z9reductionPlS_i
.type _Z9reductionPlS_i, @function
_Z9reductionPlS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPlS_iPlS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9reductionPlS_i, .-_Z9reductionPlS_i
.section .rodata.str1.1
.LC6:
.string "Syntax: %s <matrix file>\n"
.LC7:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "ERROR: Invalid file to matrices.\n"
.section .rodata.str1.1
.LC9:
.string "%d"
.LC10:
.string "Execute the kernel...\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Execution Time (microseconds): %9.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L32
movq (%rsi), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
.L31:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L41
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 8(%rsi), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L42
leaq 4(%rsp), %rdx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
imull $9, 4(%rsp), %edi
movslq %edi, %rdi
salq $3, %rdi
call _Z7emallocm
movq %rax, %rbp
movl $72, %edi
call _Z7emallocm
movq %rax, %r13
cmpl $0, 4(%rsp)
jle .L35
movl $0, %ebx
.L36:
movl %ebx, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14file_to_matrixP8_IO_FILEPli
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L36
.L35:
movl $0, %edi
call cudaSetDevice@PLT
call cudaDeviceReset@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
imull $9, 4(%rsp), %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imull $9, 4(%rsp), %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $72, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 24(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call cudaProfilerStart@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L37:
call cudaProfilerStop@PLT
movl $2, %ecx
movl $72, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC11(%rip), %xmm1
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call _Z12print_matrixPl
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L31
.L42:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl 4(%rsp), %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z9reductionPlS_iPlS_i
jmp .L37
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z9reductionPlS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPlS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <cuda_profiler_api.h>
#include <assert.h>
#define min(x,y) (y + ((x - y) & ((x - y) >> (sizeof(long) * 8 - 1))))
const int Tile_Width = 1;
const int WIDTH = 3;
void print_matrix(long *m) {
for (int i = 0; i < WIDTH; i++)
for (int j = 0; j < WIDTH; j++)
printf("%ld%c", m[i * WIDTH + j], " \n"[j == WIDTH-1]);
printf("\n");
}
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
__global__ void reduction(long* Pd, long* Nd, int ndsize) {
long Pvalue = LONG_MAX;
int i = blockIdx.y * Tile_Width + threadIdx.y;
int j = blockIdx.x * Tile_Width + threadIdx.x;
for (int k = 0; k < ndsize; ++k) {
Pvalue = min(Pvalue, Nd[k * WIDTH * WIDTH + i * WIDTH + j]);
}
Pd[i * WIDTH + j] = Pvalue;
}
void *emalloc(size_t size) {
void *memory = malloc(size);
if (!memory) {
fprintf(stderr, "ERROR: Failed to malloc.\n");
exit(1);
}
return memory;
}
void file_to_matrix(FILE *path_matr, long* m, int ind) {
/*Reads a file and get the matrix 3x3 from it*/
// Creating matrix
char line[20];
fscanf(path_matr, " %[^\n]", line);
// Filling matrix
for (int i = 0; i < WIDTH; i++) {
for (int j = 0; j < WIDTH; j++) {
fscanf(path_matr, "%ld", &m[(ind * WIDTH * WIDTH) + i * WIDTH + j]);
}
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix file>\n", argv[0]);
return EXIT_FAILURE;
}
FILE *path_matr = fopen(argv[1], "r");
if (path_matr == NULL) {
fprintf(stderr, "ERROR: Invalid file to matrices.\n");
exit(1);
}
int n_matr; // Number of matrices
fscanf(path_matr, "%d", &n_matr);
long* M = (long*) emalloc(n_matr * WIDTH * WIDTH * sizeof(long*));
long* P = (long*) emalloc(WIDTH * WIDTH * sizeof(long));
for (int i = 0; i < n_matr; i++) {
file_to_matrix(path_matr, M, i);
}
checkCuda( cudaSetDevice(0) );
cudaDeviceReset();
// allocate device matrices (linearized)
//printf("Allocate device matrices (linearized)...\n");
long* Nd = NULL;
long* Pd = NULL;
checkCuda( cudaMalloc((void**) &Nd, n_matr * WIDTH * WIDTH * sizeof(long)) );
checkCuda( cudaMalloc((void**) &Pd, WIDTH * WIDTH * sizeof(long)) );
struct timeval begin, end;
gettimeofday(&begin, NULL);
// copy host memory to device
// cudaMemcpy -> faz copias de vetores do host para o device
checkCuda( cudaMemcpy(Nd, M, n_matr * WIDTH * WIDTH * sizeof(long), cudaMemcpyHostToDevice) );
checkCuda( cudaMemcpy(Pd, P, WIDTH * WIDTH * sizeof(long), cudaMemcpyHostToDevice) );
// execute the kernel
printf("Execute the kernel...\n");
int GridSize = (WIDTH + Tile_Width-1) / Tile_Width;
dim3 gridDim(GridSize, GridSize);
dim3 blockDim(Tile_Width, Tile_Width);
cudaProfilerStart();
reduction<<< gridDim, blockDim >>>(Pd, Nd, n_matr);
cudaProfilerStop();
// copy result from device to host
checkCuda( cudaMemcpy( P, Pd, WIDTH * WIDTH * sizeof(long),cudaMemcpyDeviceToHost) );
gettimeofday(&end, NULL);
double gpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
gpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("Execution Time (microseconds): %9.2f\n", gpuTime);
print_matrix(P);
// clean up memory
free(M);
free(P);
checkCuda( cudaFree(Nd) );
checkCuda( cudaFree(Pd) );
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <hip/hip_runtime_api.h>
#include <assert.h>
#define min(x,y) (y + ((x - y) & ((x - y) >> (sizeof(long) * 8 - 1))))
const int Tile_Width = 1;
const int WIDTH = 3;
void print_matrix(long *m) {
for (int i = 0; i < WIDTH; i++)
for (int j = 0; j < WIDTH; j++)
printf("%ld%c", m[i * WIDTH + j], " \n"[j == WIDTH-1]);
printf("\n");
}
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
__global__ void reduction(long* Pd, long* Nd, int ndsize) {
long Pvalue = LONG_MAX;
int i = blockIdx.y * Tile_Width + threadIdx.y;
int j = blockIdx.x * Tile_Width + threadIdx.x;
for (int k = 0; k < ndsize; ++k) {
Pvalue = min(Pvalue, Nd[k * WIDTH * WIDTH + i * WIDTH + j]);
}
Pd[i * WIDTH + j] = Pvalue;
}
void *emalloc(size_t size) {
void *memory = malloc(size);
if (!memory) {
fprintf(stderr, "ERROR: Failed to malloc.\n");
exit(1);
}
return memory;
}
void file_to_matrix(FILE *path_matr, long* m, int ind) {
/*Reads a file and get the matrix 3x3 from it*/
// Creating matrix
char line[20];
fscanf(path_matr, " %[^\n]", line);
// Filling matrix
for (int i = 0; i < WIDTH; i++) {
for (int j = 0; j < WIDTH; j++) {
fscanf(path_matr, "%ld", &m[(ind * WIDTH * WIDTH) + i * WIDTH + j]);
}
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix file>\n", argv[0]);
return EXIT_FAILURE;
}
FILE *path_matr = fopen(argv[1], "r");
if (path_matr == NULL) {
fprintf(stderr, "ERROR: Invalid file to matrices.\n");
exit(1);
}
int n_matr; // Number of matrices
fscanf(path_matr, "%d", &n_matr);
long* M = (long*) emalloc(n_matr * WIDTH * WIDTH * sizeof(long*));
long* P = (long*) emalloc(WIDTH * WIDTH * sizeof(long));
for (int i = 0; i < n_matr; i++) {
file_to_matrix(path_matr, M, i);
}
checkCuda( hipSetDevice(0) );
hipDeviceReset();
// allocate device matrices (linearized)
//printf("Allocate device matrices (linearized)...\n");
long* Nd = NULL;
long* Pd = NULL;
checkCuda( hipMalloc((void**) &Nd, n_matr * WIDTH * WIDTH * sizeof(long)) );
checkCuda( hipMalloc((void**) &Pd, WIDTH * WIDTH * sizeof(long)) );
struct timeval begin, end;
gettimeofday(&begin, NULL);
// copy host memory to device
// cudaMemcpy -> faz copias de vetores do host para o device
checkCuda( hipMemcpy(Nd, M, n_matr * WIDTH * WIDTH * sizeof(long), hipMemcpyHostToDevice) );
checkCuda( hipMemcpy(Pd, P, WIDTH * WIDTH * sizeof(long), hipMemcpyHostToDevice) );
// execute the kernel
printf("Execute the kernel...\n");
int GridSize = (WIDTH + Tile_Width-1) / Tile_Width;
dim3 gridDim(GridSize, GridSize);
dim3 blockDim(Tile_Width, Tile_Width);
hipProfilerStart();
reduction<<< gridDim, blockDim >>>(Pd, Nd, n_matr);
hipProfilerStop();
// copy result from device to host
checkCuda( hipMemcpy( P, Pd, WIDTH * WIDTH * sizeof(long),hipMemcpyDeviceToHost) );
gettimeofday(&end, NULL);
double gpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
gpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("Execution Time (microseconds): %9.2f\n", gpuTime);
print_matrix(P);
// clean up memory
free(M);
free(P);
checkCuda( hipFree(Nd) );
checkCuda( hipFree(Pd) );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <hip/hip_runtime_api.h>
#include <assert.h>
#define min(x,y) (y + ((x - y) & ((x - y) >> (sizeof(long) * 8 - 1))))
const int Tile_Width = 1;
const int WIDTH = 3;
void print_matrix(long *m) {
for (int i = 0; i < WIDTH; i++)
for (int j = 0; j < WIDTH; j++)
printf("%ld%c", m[i * WIDTH + j], " \n"[j == WIDTH-1]);
printf("\n");
}
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
__global__ void reduction(long* Pd, long* Nd, int ndsize) {
long Pvalue = LONG_MAX;
int i = blockIdx.y * Tile_Width + threadIdx.y;
int j = blockIdx.x * Tile_Width + threadIdx.x;
for (int k = 0; k < ndsize; ++k) {
Pvalue = min(Pvalue, Nd[k * WIDTH * WIDTH + i * WIDTH + j]);
}
Pd[i * WIDTH + j] = Pvalue;
}
void *emalloc(size_t size) {
void *memory = malloc(size);
if (!memory) {
fprintf(stderr, "ERROR: Failed to malloc.\n");
exit(1);
}
return memory;
}
void file_to_matrix(FILE *path_matr, long* m, int ind) {
/*Reads a file and get the matrix 3x3 from it*/
// Creating matrix
char line[20];
fscanf(path_matr, " %[^\n]", line);
// Filling matrix
for (int i = 0; i < WIDTH; i++) {
for (int j = 0; j < WIDTH; j++) {
fscanf(path_matr, "%ld", &m[(ind * WIDTH * WIDTH) + i * WIDTH + j]);
}
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix file>\n", argv[0]);
return EXIT_FAILURE;
}
FILE *path_matr = fopen(argv[1], "r");
if (path_matr == NULL) {
fprintf(stderr, "ERROR: Invalid file to matrices.\n");
exit(1);
}
int n_matr; // Number of matrices
fscanf(path_matr, "%d", &n_matr);
long* M = (long*) emalloc(n_matr * WIDTH * WIDTH * sizeof(long*));
long* P = (long*) emalloc(WIDTH * WIDTH * sizeof(long));
for (int i = 0; i < n_matr; i++) {
file_to_matrix(path_matr, M, i);
}
checkCuda( hipSetDevice(0) );
hipDeviceReset();
// allocate device matrices (linearized)
//printf("Allocate device matrices (linearized)...\n");
long* Nd = NULL;
long* Pd = NULL;
checkCuda( hipMalloc((void**) &Nd, n_matr * WIDTH * WIDTH * sizeof(long)) );
checkCuda( hipMalloc((void**) &Pd, WIDTH * WIDTH * sizeof(long)) );
struct timeval begin, end;
gettimeofday(&begin, NULL);
// copy host memory to device
// cudaMemcpy -> faz copias de vetores do host para o device
checkCuda( hipMemcpy(Nd, M, n_matr * WIDTH * WIDTH * sizeof(long), hipMemcpyHostToDevice) );
checkCuda( hipMemcpy(Pd, P, WIDTH * WIDTH * sizeof(long), hipMemcpyHostToDevice) );
// execute the kernel
printf("Execute the kernel...\n");
int GridSize = (WIDTH + Tile_Width-1) / Tile_Width;
dim3 gridDim(GridSize, GridSize);
dim3 blockDim(Tile_Width, Tile_Width);
hipProfilerStart();
reduction<<< gridDim, blockDim >>>(Pd, Nd, n_matr);
hipProfilerStop();
// copy result from device to host
checkCuda( hipMemcpy( P, Pd, WIDTH * WIDTH * sizeof(long),hipMemcpyDeviceToHost) );
gettimeofday(&end, NULL);
double gpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
gpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("Execution Time (microseconds): %9.2f\n", gpuTime);
print_matrix(P);
// clean up memory
free(M);
free(P);
checkCuda( hipFree(Nd) );
checkCuda( hipFree(Pd) );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPlS_i
.globl _Z9reductionPlS_i
.p2align 8
.type _Z9reductionPlS_i,@function
_Z9reductionPlS_i:
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_brev_b32 s5, -2
s_mov_b32 s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v1
v_lshl_add_u32 v5, v1, 1, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_add3_u32 v2, v4, s14, v5
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s6, s6, -1
s_cmp_eq_u32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[2:3]
v_add_nc_u32_e32 v2, 9, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_sub_co_u32 v0, vcc_lo, v0, v6
v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, v3, v0
v_and_b32_e32 v1, v3, v1
v_add_co_u32 v0, vcc_lo, v0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_add3_u32 v2, s14, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPlS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPlS_i, .Lfunc_end0-_Z9reductionPlS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPlS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPlS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <hip/hip_runtime_api.h>
#include <assert.h>
#define min(x,y) (y + ((x - y) & ((x - y) >> (sizeof(long) * 8 - 1))))
const int Tile_Width = 1;
const int WIDTH = 3;
void print_matrix(long *m) {
for (int i = 0; i < WIDTH; i++)
for (int j = 0; j < WIDTH; j++)
printf("%ld%c", m[i * WIDTH + j], " \n"[j == WIDTH-1]);
printf("\n");
}
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
__global__ void reduction(long* Pd, long* Nd, int ndsize) {
long Pvalue = LONG_MAX;
int i = blockIdx.y * Tile_Width + threadIdx.y;
int j = blockIdx.x * Tile_Width + threadIdx.x;
for (int k = 0; k < ndsize; ++k) {
Pvalue = min(Pvalue, Nd[k * WIDTH * WIDTH + i * WIDTH + j]);
}
Pd[i * WIDTH + j] = Pvalue;
}
void *emalloc(size_t size) {
void *memory = malloc(size);
if (!memory) {
fprintf(stderr, "ERROR: Failed to malloc.\n");
exit(1);
}
return memory;
}
void file_to_matrix(FILE *path_matr, long* m, int ind) {
/*Reads a file and get the matrix 3x3 from it*/
// Creating matrix
char line[20];
fscanf(path_matr, " %[^\n]", line);
// Filling matrix
for (int i = 0; i < WIDTH; i++) {
for (int j = 0; j < WIDTH; j++) {
fscanf(path_matr, "%ld", &m[(ind * WIDTH * WIDTH) + i * WIDTH + j]);
}
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix file>\n", argv[0]);
return EXIT_FAILURE;
}
FILE *path_matr = fopen(argv[1], "r");
if (path_matr == NULL) {
fprintf(stderr, "ERROR: Invalid file to matrices.\n");
exit(1);
}
int n_matr; // Number of matrices
fscanf(path_matr, "%d", &n_matr);
long* M = (long*) emalloc(n_matr * WIDTH * WIDTH * sizeof(long*));
long* P = (long*) emalloc(WIDTH * WIDTH * sizeof(long));
for (int i = 0; i < n_matr; i++) {
file_to_matrix(path_matr, M, i);
}
checkCuda( hipSetDevice(0) );
hipDeviceReset();
// allocate device matrices (linearized)
//printf("Allocate device matrices (linearized)...\n");
long* Nd = NULL;
long* Pd = NULL;
checkCuda( hipMalloc((void**) &Nd, n_matr * WIDTH * WIDTH * sizeof(long)) );
checkCuda( hipMalloc((void**) &Pd, WIDTH * WIDTH * sizeof(long)) );
struct timeval begin, end;
gettimeofday(&begin, NULL);
// copy host memory to device
// cudaMemcpy -> faz copias de vetores do host para o device
checkCuda( hipMemcpy(Nd, M, n_matr * WIDTH * WIDTH * sizeof(long), hipMemcpyHostToDevice) );
checkCuda( hipMemcpy(Pd, P, WIDTH * WIDTH * sizeof(long), hipMemcpyHostToDevice) );
// execute the kernel
printf("Execute the kernel...\n");
int GridSize = (WIDTH + Tile_Width-1) / Tile_Width;
dim3 gridDim(GridSize, GridSize);
dim3 blockDim(Tile_Width, Tile_Width);
hipProfilerStart();
reduction<<< gridDim, blockDim >>>(Pd, Nd, n_matr);
hipProfilerStop();
// copy result from device to host
checkCuda( hipMemcpy( P, Pd, WIDTH * WIDTH * sizeof(long),hipMemcpyDeviceToHost) );
gettimeofday(&end, NULL);
double gpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
gpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("Execution Time (microseconds): %9.2f\n", gpuTime);
print_matrix(P);
// clean up memory
free(M);
free(P);
checkCuda( hipFree(Nd) );
checkCuda( hipFree(Pd) );
return 0;
} | .text
.file "cuda.hip"
.globl _Z12print_matrixPl # -- Begin function _Z12print_matrixPl
.p2align 4, 0x90
.type _Z12print_matrixPl,@function
_Z12print_matrixPl: # @_Z12print_matrixPl
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r15,8), %rsi
xorl %eax, %eax
cmpq $2, %r15
sete %al
movsbl .L.str.1(%rax), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $3, %r15
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $24, %rbx
cmpq $3, %r14
jne .LBB0_1
# %bb.4:
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z12print_matrixPl, .Lfunc_end0-_Z12print_matrixPl
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reductionPlS_i # -- Begin function _Z24__device_stub__reductionPlS_i
.p2align 4, 0x90
.type _Z24__device_stub__reductionPlS_i,@function
_Z24__device_stub__reductionPlS_i: # @_Z24__device_stub__reductionPlS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPlS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__reductionPlS_i, .Lfunc_end1-_Z24__device_stub__reductionPlS_i
.cfi_endproc
# -- End function
.globl _Z7emallocm # -- Begin function _Z7emallocm
.p2align 4, 0x90
.type _Z7emallocm,@function
_Z7emallocm: # @_Z7emallocm
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq malloc
testq %rax, %rax
je .LBB2_2
# %bb.1:
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z7emallocm, .Lfunc_end2-_Z7emallocm
.cfi_endproc
# -- End function
.globl _Z14file_to_matrixP8_IO_FILEPli # -- Begin function _Z14file_to_matrixP8_IO_FILEPli
.p2align 4, 0x90
.type _Z14file_to_matrixP8_IO_FILEPli,@function
_Z14file_to_matrixP8_IO_FILEPli: # @_Z14file_to_matrixP8_IO_FILEPli
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r14d
movq %rsi, %r15
movq %rdi, %rbx
movq %rsp, %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq __isoc23_fscanf
leal (%r14,%r14,8), %eax
cltq
leaq (%r15,%rax,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r14,%r12), %rdx
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
cmpq $24, %r12
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r15
addq $24, %r14
cmpq $3, %r15
jne .LBB3_1
# %bb.4:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14file_to_matrixP8_IO_FILEPli, .Lfunc_end3-_Z14file_to_matrixP8_IO_FILEPli
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB4_1
# %bb.2:
movq 8(%rsi), %rdi
movl $.L.str.7, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.5:
movq %rax, %r15
leaq 12(%rsp), %rdx
movl $.L.str.9, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
leal (%rax,%rax,8), %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB4_6
# %bb.7: # %_Z7emallocm.exit
movl $72, %edi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB4_6
# %bb.8: # %_Z7emallocm.exit30.preheader
cmpl $0, 12(%rsp)
jle .LBB4_15
# %bb.9: # %.lr.ph.preheader
leaq 48(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_10: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_11 Depth 2
# Child Loop BB4_12 Depth 3
movl $.L.str.4, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r13, %rax
shlq $32, %rax
leaq (%rax,%rax,8), %rbp
sarq $29, %rbp
addq 32(%rsp), %rbp # 8-byte Folded Reload
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_11: # %.preheader.i
# Parent Loop BB4_10 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_12 Depth 3
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_10 Depth=1
# Parent Loop BB4_11 Depth=2
# => This Inner Loop Header: Depth=3
leaq (%rbx,%rbp), %rdx
movl $.L.str.5, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %rbx
cmpq $24, %rbx
jne .LBB4_12
# %bb.13: # in Loop: Header=BB4_11 Depth=2
incq %r14
addq $24, %rbp
cmpq $3, %r14
jne .LBB4_11
# %bb.14: # %_Z14file_to_matrixP8_IO_FILEPli.exit
# in Loop: Header=BB4_10 Depth=1
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB4_10
.LBB4_15: # %_Z7emallocm.exit30._crit_edge
xorl %edi, %edi
callq hipSetDevice
callq hipDeviceReset
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl 12(%rsp), %eax
leal (%rax,%rax,8), %eax
movslq %eax, %rsi
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rdi
movl 12(%rsp), %eax
leal (%rax,%rax,8), %eax
movslq %eax, %rdx
shlq $3, %rdx
movq 32(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $72, %edx
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
callq hipProfilerStart
movabsq $12884901891, %rdi # imm = 0x300000003
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movl 12(%rsp), %edx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %edx, 44(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9reductionPlS_i, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_17:
callq hipProfilerStop
movq 16(%rsp), %rsi
movl $72, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
subq 152(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 160(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_18: # %.preheader.i31
# =>This Loop Header: Depth=1
# Child Loop BB4_19 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_19: # Parent Loop BB4_18 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r15,%r14,8), %rsi
xorl %eax, %eax
cmpq $2, %r14
sete %al
movsbl .L.str.1(%rax), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB4_19
# %bb.20: # in Loop: Header=BB4_18 Depth=1
incq %r12
addq $24, %r15
cmpq $3, %r12
jne .LBB4_18
# %bb.21: # %_Z12print_matrixPl.exit
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB4_22:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
movl $1, %eax
jmp .LBB4_22
.LBB4_6:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
jmp .LBB4_4
.LBB4_3:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $33, %esi
.LBB4_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPlS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%ld%c"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " \n"
.size .L.str.1, 3
.type _Z9reductionPlS_i,@object # @_Z9reductionPlS_i
.section .rodata,"a",@progbits
.globl _Z9reductionPlS_i
.p2align 3, 0x0
_Z9reductionPlS_i:
.quad _Z24__device_stub__reductionPlS_i
.size _Z9reductionPlS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "ERROR: Failed to malloc.\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " %[^\n]"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%ld"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Syntax: %s <matrix file>\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "r"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ERROR: Invalid file to matrices.\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Execution Time (microseconds): %9.2f\n"
.size .L.str.11, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPlS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Execute the kernel..."
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPlS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPlS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPlS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0080*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*0090*/ IADD3 R2, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x001fe4000fffe0ff */
/*00a0*/ IADD3 R5, R5, UR5, RZ ; /* 0x0000000505057c10 */
/* 0x002fe2000fffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00c0*/ @!P0 BRA 0x550 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R0, R4.reuse, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff037424 */
/* 0x000fe200078e00ff */
/*00f0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f05270 */
/*0140*/ @!P1 BRA 0x430 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R12, R2, 0x3, R5 ; /* 0x00000003020c7824 */
/* 0x000fe200078e0205 */
/*0160*/ IADD3 R9, R4, -c[0x0][0x170], RZ ; /* 0x80005c0004097a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff037424 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R12, R12, 0x1b, RZ ; /* 0x0000001b0c0c7810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*01b0*/ IADD3 R16, R12, -0x1b, RZ ; /* 0xffffffe50c107810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; /* 0x00000008ff137424 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.WIDE R16, R16, R19, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fcc00078e0213 */
/*01e0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ IADD3 R18, R12, -0x12, RZ ; /* 0xffffffee0c127810 */
/* 0x000fca0007ffe0ff */
/*0200*/ IMAD.WIDE R18, R18, R19, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fca00078e0213 */
/*0210*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ee8000c1e1b00 */
/*0220*/ LDG.E.64 R10, [R18.64+0x48] ; /* 0x00004804120a7981 */
/* 0x000f28000c1e1b00 */
/*0230*/ LDG.E.64 R6, [R18.64+0x90] ; /* 0x0000900412067981 */
/* 0x000f62000c1e1b00 */
/*0240*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R12, R12, 0x24, RZ ; /* 0x000000240c0c7810 */
/* 0x000fc40007ffe0ff */
/*0260*/ IADD3 R0, P1, -R16, R0, RZ ; /* 0x0000000010007210 */
/* 0x004fca0007f3e1ff */
/*0270*/ IMAD.X R20, R3, 0x1, ~R17, P1 ; /* 0x0000000103147824 */
/* 0x000fca00008e0e11 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1f, R20.reuse ; /* 0x0000001fff037819 */
/* 0x100fe40000011414 */
/*0290*/ SHF.R.S32.HI R13, RZ, 0x1f, R20 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011414 */
/*02a0*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*02b0*/ LOP3.LUT R13, R13, R20, RZ, 0xc0, !PT ; /* 0x000000140d0d7212 */
/* 0x000fe400078ec0ff */
/*02c0*/ IADD3 R0, P1, P2, -R14, R3, R16 ; /* 0x000000030e007210 */
/* 0x008fc80007a3e110 */
/*02d0*/ IADD3.X R16, ~R15, R13, R17, P1, P2 ; /* 0x0000000d0f107210 */
/* 0x000fc80000fe4511 */
/*02e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R16.reuse ; /* 0x0000001fff037819 */
/* 0x100fe40000011410 */
/*02f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R16 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011410 */
/*0300*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*0310*/ LOP3.LUT R13, R13, R16, RZ, 0xc0, !PT ; /* 0x000000100d0d7212 */
/* 0x000fe400078ec0ff */
/*0320*/ IADD3 R0, P1, P2, -R10, R3, R14 ; /* 0x000000030a007210 */
/* 0x010fc80007a3e10e */
/*0330*/ IADD3.X R14, ~R11, R13, R15, P1, P2 ; /* 0x0000000d0b0e7210 */
/* 0x000fc80000fe450f */
/*0340*/ SHF.R.S32.HI R3, RZ, 0x1f, R14.reuse ; /* 0x0000001fff037819 */
/* 0x100fe4000001140e */
/*0350*/ SHF.R.S32.HI R13, RZ, 0x1f, R14 ; /* 0x0000001fff0d7819 */
/* 0x000fe4000001140e */
/*0360*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*0370*/ LOP3.LUT R13, R13, R14, RZ, 0xc0, !PT ; /* 0x0000000e0d0d7212 */
/* 0x000fe400078ec0ff */
/*0380*/ IADD3 R0, P1, P2, -R6, R3, R10 ; /* 0x0000000306007210 */
/* 0x020fc80007a3e10a */
/*0390*/ IADD3.X R11, ~R7, R13, R11, P1, P2 ; /* 0x0000000d070b7210 */
/* 0x000fe20000fe450b */
/*03a0*/ IMAD.IADD R13, R9, 0x1, R8 ; /* 0x00000001090d7824 */
/* 0x000fc600078e0208 */
/*03b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R11.reuse ; /* 0x0000001fff037819 */
/* 0x100fe4000001140b */
/*03c0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f25270 */
/*03d0*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fe400078ec0ff */
/*03e0*/ SHF.R.S32.HI R10, RZ, 0x1f, R11 ; /* 0x0000001fff0a7819 */
/* 0x000fe4000001140b */
/*03f0*/ IADD3 R0, P2, R6, R3, RZ ; /* 0x0000000306007210 */
/* 0x000fe40007f5e0ff */
/*0400*/ LOP3.LUT R3, R10, R11, RZ, 0xc0, !PT ; /* 0x0000000b0a037212 */
/* 0x000fca00078ec0ff */
/*0410*/ IMAD.X R3, R7, 0x1, R3, P2 ; /* 0x0000000107037824 */
/* 0x000fe200010e0603 */
/*0420*/ @P1 BRA 0x1b0 ; /* 0xfffffd8000001947 */
/* 0x000fea000383ffff */
/*0430*/ @!P0 BRA 0x550 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD R7, R8, 0x9, R5 ; /* 0x0000000908077824 */
/* 0x000fc800078e0205 */
/*0450*/ IMAD R8, R2, 0x3, R7 ; /* 0x0000000302087824 */
/* 0x000fe400078e0207 */
/*0460*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0470*/ IMAD.WIDE R6, R8, R7, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fcc00078e0207 */
/*0480*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0490*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ IADD3 R8, R8, 0x9, RZ ; /* 0x0000000908087810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R0, P0, -R6, R0, RZ ; /* 0x0000000006007210 */
/* 0x004fca0007f1e1ff */
/*04c0*/ IMAD.X R10, R3, 0x1, ~R7, P0 ; /* 0x00000001030a7824 */
/* 0x000fe200000e0e07 */
/*04d0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*04e0*/ SHF.R.S32.HI R3, RZ, 0x1f, R10.reuse ; /* 0x0000001fff037819 */
/* 0x100fe4000001140a */
/*04f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R10 ; /* 0x0000001fff097819 */
/* 0x000fe4000001140a */
/*0500*/ LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ; /* 0x0000000003037212 */
/* 0x000fc800078ec0ff */
/*0510*/ IADD3 R0, P1, R6, R3, RZ ; /* 0x0000000306007210 */
/* 0x000fe40007f3e0ff */
/*0520*/ LOP3.LUT R3, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09037212 */
/* 0x000fca00078ec0ff */
/*0530*/ IMAD.X R3, R7, 0x1, R3, P1 ; /* 0x0000000107037824 */
/* 0x000fe200008e0603 */
/*0540*/ @P0 BRA 0x460 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD R5, R2, 0x3, R5 ; /* 0x0000000302057824 */
/* 0x000fe400078e0205 */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0580*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0204 */
/*0590*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPlS_i
.globl _Z9reductionPlS_i
.p2align 8
.type _Z9reductionPlS_i,@function
_Z9reductionPlS_i:
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_brev_b32 s5, -2
s_mov_b32 s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v1
v_lshl_add_u32 v5, v1, 1, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_add3_u32 v2, v4, s14, v5
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s6, s6, -1
s_cmp_eq_u32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[2:3]
v_add_nc_u32_e32 v2, 9, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_sub_co_u32 v0, vcc_lo, v0, v6
v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, v3, v0
v_and_b32_e32 v1, v3, v1
v_add_co_u32 v0, vcc_lo, v0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_add3_u32 v2, s14, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPlS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPlS_i, .Lfunc_end0-_Z9reductionPlS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPlS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPlS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001075ea_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%ld%c"
.LC2:
.string "\n"
.LC0:
.string " \n"
.text
.globl _Z12print_matrixPl
.type _Z12print_matrixPl, @function
_Z12print_matrixPl:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r12
jmp .L4
.L9:
addl $3, %r14d
addq $24, %rbp
cmpl $9, %r14d
je .L6
.L4:
movl $0, %ebx
.L5:
cmpl $2, %ebx
sete %al
movzbl %al, %eax
movsbl 0(%r13,%rax), %ecx
movq 0(%rbp,%rbx,8), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
jmp .L9
.L6:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPl, .-_Z12print_matrixPl
.section .rodata.str1.1
.LC3:
.string "ERROR: Failed to malloc.\n"
.text
.globl _Z7emallocm
.type _Z7emallocm, @function
_Z7emallocm:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call malloc@PLT
testq %rax, %rax
je .L13
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z7emallocm, .-_Z7emallocm
.section .rodata.str1.1
.LC4:
.string " %[^\n]"
.LC5:
.string "%ld"
.text
.globl _Z14file_to_matrixP8_IO_FILEPli
.type _Z14file_to_matrixP8_IO_FILEPli, @function
_Z14file_to_matrixP8_IO_FILEPli:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %rbp
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdx
leaq .LC4(%rip), %rsi
call __isoc23_fscanf@PLT
leal (%rbx,%rbx,8), %r15d
movl %r15d, %r14d
movslq %r15d, %rax
leaq 24(%rbp,%rax,8), %rbp
addl $9, %r15d
leaq .LC5(%rip), %r13
jmp .L15
.L21:
addl $3, %r14d
addq $24, %rbp
cmpl %r15d, %r14d
je .L14
.L15:
leaq -24(%rbp), %rbx
.L16:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L16
jmp .L21
.L14:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z14file_to_matrixP8_IO_FILEPli, .-_Z14file_to_matrixP8_IO_FILEPli
.globl _Z31__device_stub__Z9reductionPlS_iPlS_i
.type _Z31__device_stub__Z9reductionPlS_iPlS_i, @function
_Z31__device_stub__Z9reductionPlS_iPlS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPlS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z31__device_stub__Z9reductionPlS_iPlS_i, .-_Z31__device_stub__Z9reductionPlS_iPlS_i
.globl _Z9reductionPlS_i
.type _Z9reductionPlS_i, @function
_Z9reductionPlS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPlS_iPlS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9reductionPlS_i, .-_Z9reductionPlS_i
.section .rodata.str1.1
.LC6:
.string "Syntax: %s <matrix file>\n"
.LC7:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "ERROR: Invalid file to matrices.\n"
.section .rodata.str1.1
.LC9:
.string "%d"
.LC10:
.string "Execute the kernel...\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Execution Time (microseconds): %9.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L32
movq (%rsi), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
.L31:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L41
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 8(%rsi), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L42
leaq 4(%rsp), %rdx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
imull $9, 4(%rsp), %edi
movslq %edi, %rdi
salq $3, %rdi
call _Z7emallocm
movq %rax, %rbp
movl $72, %edi
call _Z7emallocm
movq %rax, %r13
cmpl $0, 4(%rsp)
jle .L35
movl $0, %ebx
.L36:
movl %ebx, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14file_to_matrixP8_IO_FILEPli
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L36
.L35:
movl $0, %edi
call cudaSetDevice@PLT
call cudaDeviceReset@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
imull $9, 4(%rsp), %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imull $9, 4(%rsp), %edx
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $72, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 24(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call cudaProfilerStart@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L37:
call cudaProfilerStop@PLT
movl $2, %ecx
movl $72, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC11(%rip), %xmm1
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call _Z12print_matrixPl
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L31
.L42:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl 4(%rsp), %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z9reductionPlS_iPlS_i
jmp .L37
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z9reductionPlS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPlS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z12print_matrixPl # -- Begin function _Z12print_matrixPl
.p2align 4, 0x90
.type _Z12print_matrixPl,@function
_Z12print_matrixPl: # @_Z12print_matrixPl
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r15,8), %rsi
xorl %eax, %eax
cmpq $2, %r15
sete %al
movsbl .L.str.1(%rax), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $3, %r15
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $24, %rbx
cmpq $3, %r14
jne .LBB0_1
# %bb.4:
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z12print_matrixPl, .Lfunc_end0-_Z12print_matrixPl
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reductionPlS_i # -- Begin function _Z24__device_stub__reductionPlS_i
.p2align 4, 0x90
.type _Z24__device_stub__reductionPlS_i,@function
_Z24__device_stub__reductionPlS_i: # @_Z24__device_stub__reductionPlS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPlS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__reductionPlS_i, .Lfunc_end1-_Z24__device_stub__reductionPlS_i
.cfi_endproc
# -- End function
.globl _Z7emallocm # -- Begin function _Z7emallocm
.p2align 4, 0x90
.type _Z7emallocm,@function
_Z7emallocm: # @_Z7emallocm
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq malloc
testq %rax, %rax
je .LBB2_2
# %bb.1:
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z7emallocm, .Lfunc_end2-_Z7emallocm
.cfi_endproc
# -- End function
.globl _Z14file_to_matrixP8_IO_FILEPli # -- Begin function _Z14file_to_matrixP8_IO_FILEPli
.p2align 4, 0x90
.type _Z14file_to_matrixP8_IO_FILEPli,@function
_Z14file_to_matrixP8_IO_FILEPli: # @_Z14file_to_matrixP8_IO_FILEPli
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r14d
movq %rsi, %r15
movq %rdi, %rbx
movq %rsp, %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq __isoc23_fscanf
leal (%r14,%r14,8), %eax
cltq
leaq (%r15,%rax,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r14,%r12), %rdx
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
cmpq $24, %r12
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r15
addq $24, %r14
cmpq $3, %r15
jne .LBB3_1
# %bb.4:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14file_to_matrixP8_IO_FILEPli, .Lfunc_end3-_Z14file_to_matrixP8_IO_FILEPli
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB4_1
# %bb.2:
movq 8(%rsi), %rdi
movl $.L.str.7, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.5:
movq %rax, %r15
leaq 12(%rsp), %rdx
movl $.L.str.9, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
leal (%rax,%rax,8), %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB4_6
# %bb.7: # %_Z7emallocm.exit
movl $72, %edi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB4_6
# %bb.8: # %_Z7emallocm.exit30.preheader
cmpl $0, 12(%rsp)
jle .LBB4_15
# %bb.9: # %.lr.ph.preheader
leaq 48(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_10: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_11 Depth 2
# Child Loop BB4_12 Depth 3
movl $.L.str.4, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r13, %rax
shlq $32, %rax
leaq (%rax,%rax,8), %rbp
sarq $29, %rbp
addq 32(%rsp), %rbp # 8-byte Folded Reload
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_11: # %.preheader.i
# Parent Loop BB4_10 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_12 Depth 3
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_10 Depth=1
# Parent Loop BB4_11 Depth=2
# => This Inner Loop Header: Depth=3
leaq (%rbx,%rbp), %rdx
movl $.L.str.5, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %rbx
cmpq $24, %rbx
jne .LBB4_12
# %bb.13: # in Loop: Header=BB4_11 Depth=2
incq %r14
addq $24, %rbp
cmpq $3, %r14
jne .LBB4_11
# %bb.14: # %_Z14file_to_matrixP8_IO_FILEPli.exit
# in Loop: Header=BB4_10 Depth=1
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB4_10
.LBB4_15: # %_Z7emallocm.exit30._crit_edge
xorl %edi, %edi
callq hipSetDevice
callq hipDeviceReset
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl 12(%rsp), %eax
leal (%rax,%rax,8), %eax
movslq %eax, %rsi
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rdi
movl 12(%rsp), %eax
leal (%rax,%rax,8), %eax
movslq %eax, %rdx
shlq $3, %rdx
movq 32(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $72, %edx
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
callq hipProfilerStart
movabsq $12884901891, %rdi # imm = 0x300000003
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movl 12(%rsp), %edx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %edx, 44(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9reductionPlS_i, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_17:
callq hipProfilerStop
movq 16(%rsp), %rsi
movl $72, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
subq 152(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 160(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_18: # %.preheader.i31
# =>This Loop Header: Depth=1
# Child Loop BB4_19 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_19: # Parent Loop BB4_18 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r15,%r14,8), %rsi
xorl %eax, %eax
cmpq $2, %r14
sete %al
movsbl .L.str.1(%rax), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB4_19
# %bb.20: # in Loop: Header=BB4_18 Depth=1
incq %r12
addq $24, %r15
cmpq $3, %r12
jne .LBB4_18
# %bb.21: # %_Z12print_matrixPl.exit
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB4_22:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
movl $1, %eax
jmp .LBB4_22
.LBB4_6:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
jmp .LBB4_4
.LBB4_3:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $33, %esi
.LBB4_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPlS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%ld%c"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " \n"
.size .L.str.1, 3
.type _Z9reductionPlS_i,@object # @_Z9reductionPlS_i
.section .rodata,"a",@progbits
.globl _Z9reductionPlS_i
.p2align 3, 0x0
_Z9reductionPlS_i:
.quad _Z24__device_stub__reductionPlS_i
.size _Z9reductionPlS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "ERROR: Failed to malloc.\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " %[^\n]"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%ld"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Syntax: %s <matrix file>\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "r"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ERROR: Invalid file to matrices.\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d"
.size .L.str.9, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Execution Time (microseconds): %9.2f\n"
.size .L.str.11, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPlS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Execute the kernel..."
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPlS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPlS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void KernelVersionShim() { } | code for sm_80
Function : _Z17KernelVersionShimv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void KernelVersionShim() { } | .file "tmpxft_0006efcb_00000000-6_KernelVersionShim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z17KernelVersionShimvv
.type _Z36__device_stub__Z17KernelVersionShimvv, @function
_Z36__device_stub__Z17KernelVersionShimvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17KernelVersionShimv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z17KernelVersionShimvv, .-_Z36__device_stub__Z17KernelVersionShimvv
.globl _Z17KernelVersionShimv
.type _Z17KernelVersionShimv, @function
_Z17KernelVersionShimv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17KernelVersionShimvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17KernelVersionShimv, .-_Z17KernelVersionShimv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17KernelVersionShimv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17KernelVersionShimv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void KernelVersionShim() { } | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KernelVersionShim() { } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KernelVersionShim() { } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17KernelVersionShimv
.globl _Z17KernelVersionShimv
.p2align 8
.type _Z17KernelVersionShimv,@function
_Z17KernelVersionShimv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17KernelVersionShimv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17KernelVersionShimv, .Lfunc_end0-_Z17KernelVersionShimv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17KernelVersionShimv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17KernelVersionShimv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KernelVersionShim() { } | .text
.file "KernelVersionShim.hip"
.globl _Z32__device_stub__KernelVersionShimv # -- Begin function _Z32__device_stub__KernelVersionShimv
.p2align 4, 0x90
.type _Z32__device_stub__KernelVersionShimv,@function
_Z32__device_stub__KernelVersionShimv: # @_Z32__device_stub__KernelVersionShimv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17KernelVersionShimv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z32__device_stub__KernelVersionShimv, .Lfunc_end0-_Z32__device_stub__KernelVersionShimv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17KernelVersionShimv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17KernelVersionShimv,@object # @_Z17KernelVersionShimv
.section .rodata,"a",@progbits
.globl _Z17KernelVersionShimv
.p2align 3, 0x0
_Z17KernelVersionShimv:
.quad _Z32__device_stub__KernelVersionShimv
.size _Z17KernelVersionShimv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17KernelVersionShimv"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__KernelVersionShimv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17KernelVersionShimv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17KernelVersionShimv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17KernelVersionShimv
.globl _Z17KernelVersionShimv
.p2align 8
.type _Z17KernelVersionShimv,@function
_Z17KernelVersionShimv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17KernelVersionShimv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17KernelVersionShimv, .Lfunc_end0-_Z17KernelVersionShimv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17KernelVersionShimv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17KernelVersionShimv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006efcb_00000000-6_KernelVersionShim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z17KernelVersionShimvv
.type _Z36__device_stub__Z17KernelVersionShimvv, @function
_Z36__device_stub__Z17KernelVersionShimvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17KernelVersionShimv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z17KernelVersionShimvv, .-_Z36__device_stub__Z17KernelVersionShimvv
.globl _Z17KernelVersionShimv
.type _Z17KernelVersionShimv, @function
_Z17KernelVersionShimv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17KernelVersionShimvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17KernelVersionShimv, .-_Z17KernelVersionShimv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17KernelVersionShimv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17KernelVersionShimv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "KernelVersionShim.hip"
.globl _Z32__device_stub__KernelVersionShimv # -- Begin function _Z32__device_stub__KernelVersionShimv
.p2align 4, 0x90
.type _Z32__device_stub__KernelVersionShimv,@function
_Z32__device_stub__KernelVersionShimv: # @_Z32__device_stub__KernelVersionShimv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17KernelVersionShimv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z32__device_stub__KernelVersionShimv, .Lfunc_end0-_Z32__device_stub__KernelVersionShimv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17KernelVersionShimv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17KernelVersionShimv,@object # @_Z17KernelVersionShimv
.section .rodata,"a",@progbits
.globl _Z17KernelVersionShimv
.p2align 3, 0x0
_Z17KernelVersionShimv:
.quad _Z32__device_stub__KernelVersionShimv
.size _Z17KernelVersionShimv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17KernelVersionShimv"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__KernelVersionShimv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17KernelVersionShimv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
#define IMG_WIDTH 2024
#define IMG_HEIGHT 2024
#define SPHERES 10
#define INF 2e10f
#define rnd(x) (x*rand() / (float)RAND_MAX)
class Sphere {
public:
float r,g,b;
float radius;
float x,y,z;
__device__ float hit(float ox, float oy, float *n) {
float dx = ox - x;
float dy = oy - y;
if (dx*dx + dy*dy < radius*radius) {
float dz = sqrtf(radius*radius - dx*dx - dy*dy);
*n = dz/sqrtf(radius*radius);
return dz+z;
}
return -INF;
}
};
Sphere *dev_s;
__global__ void kernel(int *ptr, Sphere *dev_s) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float ox = (x - (float)IMG_WIDTH/2);
float oy = (y - (float)IMG_HEIGHT/2);
float r=0, g=0, b=0;
float maxz = -INF;
for (int i=0; i < SPHERES; i++) {
float n;
float t = dev_s[i].hit(ox,oy,&n);
if (t > maxz) {
float fscale = n;
r = dev_s[i].r * fscale;
g = dev_s[i].g * fscale;
b = dev_s[i].b * fscale;
}
}
ptr[offset*3 + 0] = (int) 255 * r;
ptr[offset*3 + 1] = (int) 255 * g;
ptr[offset*3 + 2] = (int) 255 * b;
}
int main( void ) {
// Init img on host
int img_size = IMG_WIDTH*IMG_HEIGHT*3;
size_t img_size_t = (size_t)IMG_WIDTH*IMG_HEIGHT*3*sizeof(float);
int *img;
img = (int*)malloc(img_size_t);
for (int i=0; i<img_size; i+=3) { // init empty img
img[i+0] = 0;
img[i+1] = 0;
img[i+2] = 0;
}
// Init spheres on host
Sphere *temp_s = (Sphere*)malloc( sizeof(Sphere) * SPHERES );
for (int i=0; i<SPHERES; i++) {
temp_s[i].r = (float) rnd(1.0f);
temp_s[i].g = (float) rnd(1.0f);
temp_s[i].b = (float) rnd(1.0f);
temp_s[i].x = (float) rnd(1000.0f) - 500;
temp_s[i].y = (float) rnd(1000.0f) - 500;
temp_s[i].z = (float) rnd(1000.0f) - 500;
temp_s[i].radius = (float) rnd(100.0f) + 20;
}
cudaEvent_t start, stop;
HANDLE_ERROR( cudaEventCreate( &start ) );
HANDLE_ERROR( cudaEventCreate( &stop ) );
HANDLE_ERROR( cudaEventRecord( start,0 ) );
int *dev_img;
HANDLE_ERROR(cudaMalloc(&dev_img, img_size_t));
HANDLE_ERROR(cudaMalloc(
(void**)&dev_s,
sizeof(Sphere) * (size_t)SPHERES));
HANDLE_ERROR(cudaMemcpy(
dev_s,
temp_s,
sizeof(Sphere) * (size_t)SPHERES,
cudaMemcpyHostToDevice));
free(temp_s);
dim3 grids(IMG_WIDTH/16,IMG_HEIGHT/16);
dim3 threads(16,16);
kernel<<<grids, threads>>>(dev_img, dev_s);
HANDLE_ERROR(cudaMemcpy(
img,
dev_img,
img_size_t,
cudaMemcpyDeviceToHost));
HANDLE_ERROR(cudaFree(dev_img));
HANDLE_ERROR(cudaFree(dev_s));
HANDLE_ERROR( cudaEventRecord( stop,0 ) );
float elapsedTime;
HANDLE_ERROR( cudaEventElapsedTime( &elapsedTime,
start, stop ));
std::cout << "Time to generate: " << elapsedTime << "ms" << std::endl;
// write img
std::ofstream ofs;
ofs.open("img.ppm");
ofs << "P3\n" << IMG_WIDTH << " " << IMG_HEIGHT << "\n255\n";
for (int i=0; i<img_size; i+=3) {
ofs
<< img[i+0] << " "
<< img[i+1] << " "
<< img[i+2] << "\n";
}
ofs.close();
return 0;
} | .file "tmpxft_000b6c6e_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " line "
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3800:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
.type _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere, @function
_Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere:
.LFB3827:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiP6Sphere(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3827:
.size _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere, .-_Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
.globl _Z6kernelPiP6Sphere
.type _Z6kernelPiP6Sphere, @function
_Z6kernelPiP6Sphere:
.LFB3828:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3828:
.size _Z6kernelPiP6Sphere, .-_Z6kernelPiP6Sphere
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPiP6Sphere"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiP6Sphere(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Nyriu/Esercizi_Esempi_CUDA/main/04_raytracer/v1/main.cu"
.section .rodata.str1.1
.LC9:
.string "Time to generate: "
.LC10:
.string "ms"
.LC11:
.string "img.ppm"
.LC12:
.string "P3\n"
.LC13:
.string " "
.LC14:
.string "\n255\n"
.LC15:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
movl $49158912, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbx
leaq 49158912(%rax), %r13
.L20:
movl $0, (%rax)
movl $0, 4(%rax)
movl $0, 8(%rax)
addq $12, %rax
cmpq %r13, %rax
jne .L20
movl $280, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rbp
leaq 280(%rax), %r12
.L21:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
mulss .LC3(%rip), %xmm0
subss .LC5(%rip), %xmm0
movss %xmm0, 16(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
mulss .LC3(%rip), %xmm0
subss .LC5(%rip), %xmm0
movss %xmm0, 20(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
mulss .LC3(%rip), %xmm0
subss .LC5(%rip), %xmm0
movss %xmm0, 24(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC6(%rip), %xmm0
mulss .LC3(%rip), %xmm0
addss .LC7(%rip), %xmm0
movss %xmm0, 12(%rbp)
addq $28, %rbp
cmpq %r12, %rbp
jne .L21
leaq 16(%rsp), %rdi
.LEHB0:
call cudaEventCreate@PLT
movl %eax, %edi
movl $93, %edx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $94, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $95, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 32(%rsp), %rdi
movl $49158912, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $98, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $280, %esi
leaq dev_s(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $99, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, %ecx
movl $280, %edx
movq %r15, %rsi
movq dev_s(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $102, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq %r15, %rdi
call free@PLT
movl $126, 40(%rsp)
movl $126, 44(%rsp)
movl $16, 52(%rsp)
movl $16, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L22:
movl $2, %ecx
movl $49158912, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $114, %edx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $119, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq dev_s(%rip), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $120, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $121, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $124, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 64(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC11(%rip), %rsi
movq %rbp, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L34
.L33:
movq dev_s(%rip), %rsi
movq 32(%rsp), %rdi
.LEHB2:
call _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
.LEHE2:
jmp .L22
.L34:
movq %rbp, %rdi
leaq .LC12(%rip), %rsi
.LEHB3:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $2024, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $2024, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %r15
leaq .LC13(%rip), %r14
jmp .L23
.L36:
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC15(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $12, %rbx
cmpq %r13, %rbx
je .L35
.L23:
movl (%rbx), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
jmp .L36
.L35:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE3:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L25
call __stack_chk_fail@PLT
.L25:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3802:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB0-.LFB3802
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3802
.uleb128 .LEHE1-.LEHB1
.uleb128 .L27-.LFB3802
.uleb128 0
.uleb128 .LEHB2-.LFB3802
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3802
.uleb128 .LEHE3-.LEHB3
.uleb128 .L27-.LFB3802
.uleb128 0
.uleb128 .LEHB4-.LFB3802
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dev_s
.bss
.align 8
.type dev_s, @object
.size dev_s, 8
dev_s:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1148846080
.align 4
.LC5:
.long 1140457472
.align 4
.LC6:
.long 1120403456
.align 4
.LC7:
.long 1101004800
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
#define IMG_WIDTH 2024
#define IMG_HEIGHT 2024
#define SPHERES 10
#define INF 2e10f
#define rnd(x) (x*rand() / (float)RAND_MAX)
class Sphere {
public:
float r,g,b;
float radius;
float x,y,z;
__device__ float hit(float ox, float oy, float *n) {
float dx = ox - x;
float dy = oy - y;
if (dx*dx + dy*dy < radius*radius) {
float dz = sqrtf(radius*radius - dx*dx - dy*dy);
*n = dz/sqrtf(radius*radius);
return dz+z;
}
return -INF;
}
};
Sphere *dev_s;
__global__ void kernel(int *ptr, Sphere *dev_s) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float ox = (x - (float)IMG_WIDTH/2);
float oy = (y - (float)IMG_HEIGHT/2);
float r=0, g=0, b=0;
float maxz = -INF;
for (int i=0; i < SPHERES; i++) {
float n;
float t = dev_s[i].hit(ox,oy,&n);
if (t > maxz) {
float fscale = n;
r = dev_s[i].r * fscale;
g = dev_s[i].g * fscale;
b = dev_s[i].b * fscale;
}
}
ptr[offset*3 + 0] = (int) 255 * r;
ptr[offset*3 + 1] = (int) 255 * g;
ptr[offset*3 + 2] = (int) 255 * b;
}
int main( void ) {
// Init img on host
int img_size = IMG_WIDTH*IMG_HEIGHT*3;
size_t img_size_t = (size_t)IMG_WIDTH*IMG_HEIGHT*3*sizeof(float);
int *img;
img = (int*)malloc(img_size_t);
for (int i=0; i<img_size; i+=3) { // init empty img
img[i+0] = 0;
img[i+1] = 0;
img[i+2] = 0;
}
// Init spheres on host
Sphere *temp_s = (Sphere*)malloc( sizeof(Sphere) * SPHERES );
for (int i=0; i<SPHERES; i++) {
temp_s[i].r = (float) rnd(1.0f);
temp_s[i].g = (float) rnd(1.0f);
temp_s[i].b = (float) rnd(1.0f);
temp_s[i].x = (float) rnd(1000.0f) - 500;
temp_s[i].y = (float) rnd(1000.0f) - 500;
temp_s[i].z = (float) rnd(1000.0f) - 500;
temp_s[i].radius = (float) rnd(100.0f) + 20;
}
cudaEvent_t start, stop;
HANDLE_ERROR( cudaEventCreate( &start ) );
HANDLE_ERROR( cudaEventCreate( &stop ) );
HANDLE_ERROR( cudaEventRecord( start,0 ) );
int *dev_img;
HANDLE_ERROR(cudaMalloc(&dev_img, img_size_t));
HANDLE_ERROR(cudaMalloc(
(void**)&dev_s,
sizeof(Sphere) * (size_t)SPHERES));
HANDLE_ERROR(cudaMemcpy(
dev_s,
temp_s,
sizeof(Sphere) * (size_t)SPHERES,
cudaMemcpyHostToDevice));
free(temp_s);
dim3 grids(IMG_WIDTH/16,IMG_HEIGHT/16);
dim3 threads(16,16);
kernel<<<grids, threads>>>(dev_img, dev_s);
HANDLE_ERROR(cudaMemcpy(
img,
dev_img,
img_size_t,
cudaMemcpyDeviceToHost));
HANDLE_ERROR(cudaFree(dev_img));
HANDLE_ERROR(cudaFree(dev_s));
HANDLE_ERROR( cudaEventRecord( stop,0 ) );
float elapsedTime;
HANDLE_ERROR( cudaEventElapsedTime( &elapsedTime,
start, stop ));
std::cout << "Time to generate: " << elapsedTime << "ms" << std::endl;
// write img
std::ofstream ofs;
ofs.open("img.ppm");
ofs << "P3\n" << IMG_WIDTH << " " << IMG_HEIGHT << "\n255\n";
for (int i=0; i<img_size; i+=3) {
ofs
<< img[i+0] << " "
<< img[i+1] << " "
<< img[i+2] << "\n";
}
ofs.close();
return 0;
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
#define IMG_WIDTH 2024
#define IMG_HEIGHT 2024
#define SPHERES 10
#define INF 2e10f
#define rnd(x) (x*rand() / (float)RAND_MAX)
class Sphere {
public:
float r,g,b;
float radius;
float x,y,z;
__device__ float hit(float ox, float oy, float *n) {
float dx = ox - x;
float dy = oy - y;
if (dx*dx + dy*dy < radius*radius) {
float dz = sqrtf(radius*radius - dx*dx - dy*dy);
*n = dz/sqrtf(radius*radius);
return dz+z;
}
return -INF;
}
};
Sphere *dev_s;
__global__ void kernel(int *ptr, Sphere *dev_s) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float ox = (x - (float)IMG_WIDTH/2);
float oy = (y - (float)IMG_HEIGHT/2);
float r=0, g=0, b=0;
float maxz = -INF;
for (int i=0; i < SPHERES; i++) {
float n;
float t = dev_s[i].hit(ox,oy,&n);
if (t > maxz) {
float fscale = n;
r = dev_s[i].r * fscale;
g = dev_s[i].g * fscale;
b = dev_s[i].b * fscale;
}
}
ptr[offset*3 + 0] = (int) 255 * r;
ptr[offset*3 + 1] = (int) 255 * g;
ptr[offset*3 + 2] = (int) 255 * b;
}
int main( void ) {
// Init img on host
int img_size = IMG_WIDTH*IMG_HEIGHT*3;
size_t img_size_t = (size_t)IMG_WIDTH*IMG_HEIGHT*3*sizeof(float);
int *img;
img = (int*)malloc(img_size_t);
for (int i=0; i<img_size; i+=3) { // init empty img
img[i+0] = 0;
img[i+1] = 0;
img[i+2] = 0;
}
// Init spheres on host
Sphere *temp_s = (Sphere*)malloc( sizeof(Sphere) * SPHERES );
for (int i=0; i<SPHERES; i++) {
temp_s[i].r = (float) rnd(1.0f);
temp_s[i].g = (float) rnd(1.0f);
temp_s[i].b = (float) rnd(1.0f);
temp_s[i].x = (float) rnd(1000.0f) - 500;
temp_s[i].y = (float) rnd(1000.0f) - 500;
temp_s[i].z = (float) rnd(1000.0f) - 500;
temp_s[i].radius = (float) rnd(100.0f) + 20;
}
hipEvent_t start, stop;
HANDLE_ERROR( hipEventCreate( &start ) );
HANDLE_ERROR( hipEventCreate( &stop ) );
HANDLE_ERROR( hipEventRecord( start,0 ) );
int *dev_img;
HANDLE_ERROR(hipMalloc(&dev_img, img_size_t));
HANDLE_ERROR(hipMalloc(
(void**)&dev_s,
sizeof(Sphere) * (size_t)SPHERES));
HANDLE_ERROR(hipMemcpy(
dev_s,
temp_s,
sizeof(Sphere) * (size_t)SPHERES,
hipMemcpyHostToDevice));
free(temp_s);
dim3 grids(IMG_WIDTH/16,IMG_HEIGHT/16);
dim3 threads(16,16);
kernel<<<grids, threads>>>(dev_img, dev_s);
HANDLE_ERROR(hipMemcpy(
img,
dev_img,
img_size_t,
hipMemcpyDeviceToHost));
HANDLE_ERROR(hipFree(dev_img));
HANDLE_ERROR(hipFree(dev_s));
HANDLE_ERROR( hipEventRecord( stop,0 ) );
float elapsedTime;
HANDLE_ERROR( hipEventElapsedTime( &elapsedTime,
start, stop ));
std::cout << "Time to generate: " << elapsedTime << "ms" << std::endl;
// write img
std::ofstream ofs;
ofs.open("img.ppm");
ofs << "P3\n" << IMG_WIDTH << " " << IMG_HEIGHT << "\n255\n";
for (int i=0; i<img_size; i+=3) {
ofs
<< img[i+0] << " "
<< img[i+1] << " "
<< img[i+2] << "\n";
}
ofs.close();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
#define IMG_WIDTH 2024
#define IMG_HEIGHT 2024
#define SPHERES 10
#define INF 2e10f
#define rnd(x) (x*rand() / (float)RAND_MAX)
class Sphere {
public:
float r,g,b;
float radius;
float x,y,z;
__device__ float hit(float ox, float oy, float *n) {
float dx = ox - x;
float dy = oy - y;
if (dx*dx + dy*dy < radius*radius) {
float dz = sqrtf(radius*radius - dx*dx - dy*dy);
*n = dz/sqrtf(radius*radius);
return dz+z;
}
return -INF;
}
};
Sphere *dev_s;
__global__ void kernel(int *ptr, Sphere *dev_s) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float ox = (x - (float)IMG_WIDTH/2);
float oy = (y - (float)IMG_HEIGHT/2);
float r=0, g=0, b=0;
float maxz = -INF;
for (int i=0; i < SPHERES; i++) {
float n;
float t = dev_s[i].hit(ox,oy,&n);
if (t > maxz) {
float fscale = n;
r = dev_s[i].r * fscale;
g = dev_s[i].g * fscale;
b = dev_s[i].b * fscale;
}
}
ptr[offset*3 + 0] = (int) 255 * r;
ptr[offset*3 + 1] = (int) 255 * g;
ptr[offset*3 + 2] = (int) 255 * b;
}
int main( void ) {
// Init img on host
int img_size = IMG_WIDTH*IMG_HEIGHT*3;
size_t img_size_t = (size_t)IMG_WIDTH*IMG_HEIGHT*3*sizeof(float);
int *img;
img = (int*)malloc(img_size_t);
for (int i=0; i<img_size; i+=3) { // init empty img
img[i+0] = 0;
img[i+1] = 0;
img[i+2] = 0;
}
// Init spheres on host
Sphere *temp_s = (Sphere*)malloc( sizeof(Sphere) * SPHERES );
for (int i=0; i<SPHERES; i++) {
temp_s[i].r = (float) rnd(1.0f);
temp_s[i].g = (float) rnd(1.0f);
temp_s[i].b = (float) rnd(1.0f);
temp_s[i].x = (float) rnd(1000.0f) - 500;
temp_s[i].y = (float) rnd(1000.0f) - 500;
temp_s[i].z = (float) rnd(1000.0f) - 500;
temp_s[i].radius = (float) rnd(100.0f) + 20;
}
hipEvent_t start, stop;
HANDLE_ERROR( hipEventCreate( &start ) );
HANDLE_ERROR( hipEventCreate( &stop ) );
HANDLE_ERROR( hipEventRecord( start,0 ) );
int *dev_img;
HANDLE_ERROR(hipMalloc(&dev_img, img_size_t));
HANDLE_ERROR(hipMalloc(
(void**)&dev_s,
sizeof(Sphere) * (size_t)SPHERES));
HANDLE_ERROR(hipMemcpy(
dev_s,
temp_s,
sizeof(Sphere) * (size_t)SPHERES,
hipMemcpyHostToDevice));
free(temp_s);
dim3 grids(IMG_WIDTH/16,IMG_HEIGHT/16);
dim3 threads(16,16);
kernel<<<grids, threads>>>(dev_img, dev_s);
HANDLE_ERROR(hipMemcpy(
img,
dev_img,
img_size_t,
hipMemcpyDeviceToHost));
HANDLE_ERROR(hipFree(dev_img));
HANDLE_ERROR(hipFree(dev_s));
HANDLE_ERROR( hipEventRecord( stop,0 ) );
float elapsedTime;
HANDLE_ERROR( hipEventElapsedTime( &elapsedTime,
start, stop ));
std::cout << "Time to generate: " << elapsedTime << "ms" << std::endl;
// write img
std::ofstream ofs;
ofs.open("img.ppm");
ofs << "P3\n" << IMG_WIDTH << " " << IMG_HEIGHT << "\n255\n";
for (int i=0; i<img_size; i+=3) {
ofs
<< img[i+0] << " "
<< img[i+1] << " "
<< img[i+2] << "\n";
}
ofs.close();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiP6Sphere
.globl _Z6kernelPiP6Sphere
.p2align 8
.type _Z6kernelPiP6Sphere,@function
_Z6kernelPiP6Sphere:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s10, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s11, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cvt_f32_i32_e32 v2, v0
v_mov_b32_e32 v4, 0
v_cvt_f32_i32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v5, 0xc47d0000, v2 :: v_dual_mov_b32 v2, 0
v_add_f32_e32 v6, 0xc47d0000, v6
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
s_add_u32 s6, s6, 28
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s6, 0x118
s_cbranch_scc1 .LBB0_6
.LBB0_2:
s_add_u32 s8, s4, s6
s_addc_u32 s9, s5, s7
s_clause 0x1
s_load_b32 s12, s[8:9], 0x14
s_load_b64 s[2:3], s[8:9], 0xc
s_waitcnt lgkmcnt(0)
v_subrev_f32_e32 v8, s12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_subrev_f32 v10, s3, v5 :: v_dual_mul_f32 v9, v8, v8
v_mul_f32_e64 v8, s2, s2
v_fma_f32 v11, v10, v10, v9
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v11, v8
v_mov_b32_e32 v11, 0xd09502f9
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v8
v_mul_f32_e32 v7, v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v8, v7
v_sub_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v9, 0x4f800000, v8 :: v_dual_mul_f32 v10, 0x4f800000, v7
v_cndmask_b32_e32 v8, v8, v9, vcc_lo
v_cmp_gt_f32_e64 s2, 0xf800000, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v9, v8
v_cndmask_b32_e64 v7, v7, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v10, v7
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v11, -1, v9
v_add_nc_u32_e32 v13, 1, v9
v_fma_f32 v14, -v11, v9, v8
v_add_nc_u32_e32 v12, -1, v10
v_add_nc_u32_e32 v15, 1, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v17, -v13, v9, v8
v_cmp_ge_f32_e64 s3, 0, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v12, v10, v7
v_cndmask_b32_e64 v9, v9, v11, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s3, 0, v16
v_fma_f32 v11, -v15, v10, v7
v_cndmask_b32_e64 v10, v10, v12, s3
v_cmp_lt_f32_e64 s3, 0, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v9, v13, s3
v_cmp_lt_f32_e64 s3, 0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, 0x37800000, v9
v_cndmask_b32_e64 v10, v10, v15, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v9, v9, v11 :: v_dual_mul_f32 v12, 0x37800000, v10
v_cmp_class_f32_e64 vcc_lo, v8, 0x260
v_cndmask_b32_e64 v10, v10, v12, s2
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v8, v9, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v7, 0x260
s_add_u32 s2, s4, s6
s_addc_u32 s3, s5, s7
s_load_b32 s2, s[2:3], 0x18
v_cndmask_b32_e32 v9, v10, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v7, null, v8, v8, v9
v_div_scale_f32 v12, vcc_lo, v9, v8, v9
v_rcp_f32_e32 v10, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v7, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v10
v_mul_f32_e32 v11, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v7, v11, v12
v_fmac_f32_e32 v11, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v11, v12
v_div_fmas_f32 v7, v7, v10, v11
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v11, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v7, v7, v8, v9
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_f32_e32 0xd09502f9, v11
s_cbranch_execz .LBB0_1
s_add_u32 s12, s4, s6
s_addc_u32 s13, s5, s7
s_clause 0x1
s_load_b32 s3, s[8:9], 0x0
s_load_b64 s[8:9], s[12:13], 0x4
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v4, s3, v7
v_mul_f32_e32 v3, s8, v7
v_mul_f32_e32 v2, s9, v7
s_branch .LBB0_1
.LBB0_6:
s_mul_i32 s10, s10, s11
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[5:6], null, s10, v1, v[0:1]
v_mul_f32_e32 v2, 0x437f0000, v2
v_mul_f32_e32 v6, 0x437f0000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v2, v2
v_lshl_add_u32 v0, v5, 1, v5
v_mul_f32_e32 v5, 0x437f0000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v0, v5
v_cvt_i32_f32_e32 v1, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b96 v[3:4], v[0:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiP6Sphere
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiP6Sphere, .Lfunc_end0-_Z6kernelPiP6Sphere
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiP6Sphere
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiP6Sphere.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
#define IMG_WIDTH 2024
#define IMG_HEIGHT 2024
#define SPHERES 10
#define INF 2e10f
#define rnd(x) (x*rand() / (float)RAND_MAX)
class Sphere {
public:
float r,g,b;
float radius;
float x,y,z;
__device__ float hit(float ox, float oy, float *n) {
float dx = ox - x;
float dy = oy - y;
if (dx*dx + dy*dy < radius*radius) {
float dz = sqrtf(radius*radius - dx*dx - dy*dy);
*n = dz/sqrtf(radius*radius);
return dz+z;
}
return -INF;
}
};
Sphere *dev_s;
__global__ void kernel(int *ptr, Sphere *dev_s) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float ox = (x - (float)IMG_WIDTH/2);
float oy = (y - (float)IMG_HEIGHT/2);
float r=0, g=0, b=0;
float maxz = -INF;
for (int i=0; i < SPHERES; i++) {
float n;
float t = dev_s[i].hit(ox,oy,&n);
if (t > maxz) {
float fscale = n;
r = dev_s[i].r * fscale;
g = dev_s[i].g * fscale;
b = dev_s[i].b * fscale;
}
}
ptr[offset*3 + 0] = (int) 255 * r;
ptr[offset*3 + 1] = (int) 255 * g;
ptr[offset*3 + 2] = (int) 255 * b;
}
int main( void ) {
// Init img on host
int img_size = IMG_WIDTH*IMG_HEIGHT*3;
size_t img_size_t = (size_t)IMG_WIDTH*IMG_HEIGHT*3*sizeof(float);
int *img;
img = (int*)malloc(img_size_t);
for (int i=0; i<img_size; i+=3) { // init empty img
img[i+0] = 0;
img[i+1] = 0;
img[i+2] = 0;
}
// Init spheres on host
Sphere *temp_s = (Sphere*)malloc( sizeof(Sphere) * SPHERES );
for (int i=0; i<SPHERES; i++) {
temp_s[i].r = (float) rnd(1.0f);
temp_s[i].g = (float) rnd(1.0f);
temp_s[i].b = (float) rnd(1.0f);
temp_s[i].x = (float) rnd(1000.0f) - 500;
temp_s[i].y = (float) rnd(1000.0f) - 500;
temp_s[i].z = (float) rnd(1000.0f) - 500;
temp_s[i].radius = (float) rnd(100.0f) + 20;
}
hipEvent_t start, stop;
HANDLE_ERROR( hipEventCreate( &start ) );
HANDLE_ERROR( hipEventCreate( &stop ) );
HANDLE_ERROR( hipEventRecord( start,0 ) );
int *dev_img;
HANDLE_ERROR(hipMalloc(&dev_img, img_size_t));
HANDLE_ERROR(hipMalloc(
(void**)&dev_s,
sizeof(Sphere) * (size_t)SPHERES));
HANDLE_ERROR(hipMemcpy(
dev_s,
temp_s,
sizeof(Sphere) * (size_t)SPHERES,
hipMemcpyHostToDevice));
free(temp_s);
dim3 grids(IMG_WIDTH/16,IMG_HEIGHT/16);
dim3 threads(16,16);
kernel<<<grids, threads>>>(dev_img, dev_s);
HANDLE_ERROR(hipMemcpy(
img,
dev_img,
img_size_t,
hipMemcpyDeviceToHost));
HANDLE_ERROR(hipFree(dev_img));
HANDLE_ERROR(hipFree(dev_s));
HANDLE_ERROR( hipEventRecord( stop,0 ) );
float elapsedTime;
HANDLE_ERROR( hipEventElapsedTime( &elapsedTime,
start, stop ));
std::cout << "Time to generate: " << elapsedTime << "ms" << std::endl;
// write img
std::ofstream ofs;
ofs.open("img.ppm");
ofs << "P3\n" << IMG_WIDTH << " " << IMG_HEIGHT << "\n255\n";
for (int i=0; i<img_size; i+=3) {
ofs
<< img[i+0] << " "
<< img[i+1] << " "
<< img[i+2] << "\n";
}
ofs.close();
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiP6Sphere # -- Begin function _Z21__device_stub__kernelPiP6Sphere
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiP6Sphere,@function
_Z21__device_stub__kernelPiP6Sphere: # @_Z21__device_stub__kernelPiP6Sphere
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiP6Sphere, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiP6Sphere, .Lfunc_end0-_Z21__device_stub__kernelPiP6Sphere
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x447a0000 # float 1000
.LCPI1_2:
.long 0xc3fa0000 # float -500
.LCPI1_3:
.long 0x42c80000 # float 100
.LCPI1_4:
.long 0x41a00000 # float 20
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $608, %rsp # imm = 0x260
.cfi_def_cfa_offset 656
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $49158912, %edi # imm = 0x2EE1B00
callq malloc
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $49158912, %edx # imm = 0x2EE1B00
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.cfi_escape 0x2e, 0x00
movl $280, %edi # imm = 0x118
callq malloc
movq %rax, %r14
movl $24, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, -24(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -20(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -16(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, -8(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_2(%rip), %xmm0
movss %xmm0, -4(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_2(%rip), %xmm0
movss %xmm0, (%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_3(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_4(%rip), %xmm0
movss %xmm0, -12(%r14,%r15)
addq $28, %r15
cmpq $304, %r15 # imm = 0x130
jne .LBB1_1
# %bb.2:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $95, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $96, %esi
callq _ZL11HandleError10hipError_tPKci
movq 40(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $97, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $49158912, %esi # imm = 0x2EE1B00
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $100, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
movl $dev_s, %edi
movl $280, %esi # imm = 0x118
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $103, %esi
callq _ZL11HandleError10hipError_tPKci
movq dev_s(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $280, %edx # imm = 0x118
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $108, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
movabsq $541165879422, %rdi # imm = 0x7E0000007E
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq dev_s(%rip), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z6kernelPiP6Sphere, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $49158912, %edx # imm = 0x2EE1B00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $120, %esi
callq _ZL11HandleError10hipError_tPKci
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $121, %esi
callq _ZL11HandleError10hipError_tPKci
movq dev_s(%rip), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $122, %esi
callq _ZL11HandleError10hipError_tPKci
movq 32(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $123, %esi
callq _ZL11HandleError10hipError_tPKci
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $127, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_31
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB1_8
.LBB1_7:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %r15
movq %r15, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 104(%rsp), %r14
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movq %r14, %rdi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.9: # %.noexc
movq 96(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_11
# %bb.10:
movl 32(%r15), %esi
orl $4, %esi
.LBB1_11: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.12: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $.L.str.4, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp5:
# %bb.13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $2024, %esi # imm = 0x7E8
callq _ZNSolsEi
.Ltmp7:
# %bb.14:
.Ltmp8:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp9:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $2024, %esi # imm = 0x7E8
callq _ZNSolsEi
.Ltmp11:
# %bb.16:
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit59.preheader.preheader
movq $-3, %r13
leaq 96(%rsp), %r15
.p2align 4, 0x90
.LBB1_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit59.preheader
# =>This Inner Loop Header: Depth=1
movl 12(%rbx,%r13,4), %esi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSolsEi
.Ltmp15:
# %bb.19: # in Loop: Header=BB1_18 Depth=1
.Ltmp16:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64
# in Loop: Header=BB1_18 Depth=1
movl 16(%rbx,%r13,4), %esi
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSolsEi
.Ltmp19:
# %bb.21: # in Loop: Header=BB1_18 Depth=1
.Ltmp20:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp21:
# %bb.22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit66
# in Loop: Header=BB1_18 Depth=1
movl 20(%rbx,%r13,4), %esi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSolsEi
.Ltmp23:
# %bb.23: # in Loop: Header=BB1_18 Depth=1
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit68
# in Loop: Header=BB1_18 Depth=1
addq $3, %r13
cmpq $12289725, %r13 # imm = 0xBB86BD
jb .LBB1_18
# %bb.25:
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp28:
# %bb.26: # %.noexc61
testq %rax, %rax
jne .LBB1_28
# %bb.27:
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $96, %rdi
movl 128(%rsp,%rax), %esi
orl $4, %esi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp30:
.LBB1_28: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $608, %rsp # imm = 0x260
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 656
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_29:
.Ltmp31:
jmp .LBB1_30
.LBB1_32:
.Ltmp26:
.LBB1_30:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp0 # Call between .Ltmp0 and .Ltmp13
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp25-.Ltmp14 # Call between .Ltmp14 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp30-.Ltmp27 # Call between .Ltmp27 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end1-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZL11HandleError10hipError_tPKci
.type _ZL11HandleError10hipError_tPKci,@function
_ZL11HandleError10hipError_tPKci: # @_ZL11HandleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.9, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end2:
.size _ZL11HandleError10hipError_tPKci, .Lfunc_end2-_ZL11HandleError10hipError_tPKci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiP6Sphere, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_s,@object # @dev_s
.bss
.globl dev_s
.p2align 3, 0x0
dev_s:
.quad 0
.size dev_s, 8
.type _Z6kernelPiP6Sphere,@object # @_Z6kernelPiP6Sphere
.section .rodata,"a",@progbits
.globl _Z6kernelPiP6Sphere
.p2align 3, 0x0
_Z6kernelPiP6Sphere:
.quad _Z21__device_stub__kernelPiP6Sphere
.size _Z6kernelPiP6Sphere, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Nyriu/Esercizi_Esempi_CUDA/main/04_raytracer/v1/main.hip"
.size .L.str, 114
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to generate: "
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "img.ppm"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P3\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n255\n"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " in "
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " line "
.size .L.str.9, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiP6Sphere"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiP6Sphere
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym dev_s
.addrsig_sym _Z6kernelPiP6Sphere
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b6c6e_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " line "
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3800:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
.type _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere, @function
_Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere:
.LFB3827:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiP6Sphere(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3827:
.size _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere, .-_Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
.globl _Z6kernelPiP6Sphere
.type _Z6kernelPiP6Sphere, @function
_Z6kernelPiP6Sphere:
.LFB3828:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3828:
.size _Z6kernelPiP6Sphere, .-_Z6kernelPiP6Sphere
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPiP6Sphere"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiP6Sphere(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Nyriu/Esercizi_Esempi_CUDA/main/04_raytracer/v1/main.cu"
.section .rodata.str1.1
.LC9:
.string "Time to generate: "
.LC10:
.string "ms"
.LC11:
.string "img.ppm"
.LC12:
.string "P3\n"
.LC13:
.string " "
.LC14:
.string "\n255\n"
.LC15:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
movl $49158912, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbx
leaq 49158912(%rax), %r13
.L20:
movl $0, (%rax)
movl $0, 4(%rax)
movl $0, 8(%rax)
addq $12, %rax
cmpq %r13, %rax
jne .L20
movl $280, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rbp
leaq 280(%rax), %r12
.L21:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
mulss .LC3(%rip), %xmm0
subss .LC5(%rip), %xmm0
movss %xmm0, 16(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
mulss .LC3(%rip), %xmm0
subss .LC5(%rip), %xmm0
movss %xmm0, 20(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
mulss .LC3(%rip), %xmm0
subss .LC5(%rip), %xmm0
movss %xmm0, 24(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC6(%rip), %xmm0
mulss .LC3(%rip), %xmm0
addss .LC7(%rip), %xmm0
movss %xmm0, 12(%rbp)
addq $28, %rbp
cmpq %r12, %rbp
jne .L21
leaq 16(%rsp), %rdi
.LEHB0:
call cudaEventCreate@PLT
movl %eax, %edi
movl $93, %edx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $94, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $95, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 32(%rsp), %rdi
movl $49158912, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $98, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $280, %esi
leaq dev_s(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $99, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, %ecx
movl $280, %edx
movq %r15, %rsi
movq dev_s(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $102, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq %r15, %rdi
call free@PLT
movl $126, 40(%rsp)
movl $126, 44(%rsp)
movl $16, 52(%rsp)
movl $16, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L22:
movl $2, %ecx
movl $49158912, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $114, %edx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $119, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movq dev_s(%rip), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $120, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $121, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $124, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 64(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC11(%rip), %rsi
movq %rbp, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L34
.L33:
movq dev_s(%rip), %rsi
movq 32(%rsp), %rdi
.LEHB2:
call _Z33__device_stub__Z6kernelPiP6SpherePiP6Sphere
.LEHE2:
jmp .L22
.L34:
movq %rbp, %rdi
leaq .LC12(%rip), %rsi
.LEHB3:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $2024, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $2024, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %r15
leaq .LC13(%rip), %r14
jmp .L23
.L36:
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC15(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $12, %rbx
cmpq %r13, %rbx
je .L35
.L23:
movl (%rbx), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
jmp .L36
.L35:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE3:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L25
call __stack_chk_fail@PLT
.L25:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3802:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB0-.LFB3802
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3802
.uleb128 .LEHE1-.LEHB1
.uleb128 .L27-.LFB3802
.uleb128 0
.uleb128 .LEHB2-.LFB3802
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3802
.uleb128 .LEHE3-.LEHB3
.uleb128 .L27-.LFB3802
.uleb128 0
.uleb128 .LEHB4-.LFB3802
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dev_s
.bss
.align 8
.type dev_s, @object
.size dev_s, 8
dev_s:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1148846080
.align 4
.LC5:
.long 1140457472
.align 4
.LC6:
.long 1120403456
.align 4
.LC7:
.long 1101004800
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiP6Sphere # -- Begin function _Z21__device_stub__kernelPiP6Sphere
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiP6Sphere,@function
_Z21__device_stub__kernelPiP6Sphere: # @_Z21__device_stub__kernelPiP6Sphere
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiP6Sphere, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiP6Sphere, .Lfunc_end0-_Z21__device_stub__kernelPiP6Sphere
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x447a0000 # float 1000
.LCPI1_2:
.long 0xc3fa0000 # float -500
.LCPI1_3:
.long 0x42c80000 # float 100
.LCPI1_4:
.long 0x41a00000 # float 20
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $608, %rsp # imm = 0x260
.cfi_def_cfa_offset 656
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $49158912, %edi # imm = 0x2EE1B00
callq malloc
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $49158912, %edx # imm = 0x2EE1B00
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.cfi_escape 0x2e, 0x00
movl $280, %edi # imm = 0x118
callq malloc
movq %rax, %r14
movl $24, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, -24(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -20(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -16(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, -8(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_2(%rip), %xmm0
movss %xmm0, -4(%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_2(%rip), %xmm0
movss %xmm0, (%r14,%r15)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_3(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
addss .LCPI1_4(%rip), %xmm0
movss %xmm0, -12(%r14,%r15)
addq $28, %r15
cmpq $304, %r15 # imm = 0x130
jne .LBB1_1
# %bb.2:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $95, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $96, %esi
callq _ZL11HandleError10hipError_tPKci
movq 40(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $97, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $49158912, %esi # imm = 0x2EE1B00
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $100, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
movl $dev_s, %edi
movl $280, %esi # imm = 0x118
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $103, %esi
callq _ZL11HandleError10hipError_tPKci
movq dev_s(%rip), %rdi
.cfi_escape 0x2e, 0x00
movl $280, %edx # imm = 0x118
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $108, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
movabsq $541165879422, %rdi # imm = 0x7E0000007E
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq dev_s(%rip), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z6kernelPiP6Sphere, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $49158912, %edx # imm = 0x2EE1B00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $120, %esi
callq _ZL11HandleError10hipError_tPKci
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $121, %esi
callq _ZL11HandleError10hipError_tPKci
movq dev_s(%rip), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $122, %esi
callq _ZL11HandleError10hipError_tPKci
movq 32(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $123, %esi
callq _ZL11HandleError10hipError_tPKci
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $127, %esi
callq _ZL11HandleError10hipError_tPKci
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_31
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB1_8
.LBB1_7:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %r15
movq %r15, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 104(%rsp), %r14
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movq %r14, %rdi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.9: # %.noexc
movq 96(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_11
# %bb.10:
movl 32(%r15), %esi
orl $4, %esi
.LBB1_11: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.12: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $.L.str.4, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp5:
# %bb.13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $2024, %esi # imm = 0x7E8
callq _ZNSolsEi
.Ltmp7:
# %bb.14:
.Ltmp8:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp9:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $2024, %esi # imm = 0x7E8
callq _ZNSolsEi
.Ltmp11:
# %bb.16:
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit59.preheader.preheader
movq $-3, %r13
leaq 96(%rsp), %r15
.p2align 4, 0x90
.LBB1_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit59.preheader
# =>This Inner Loop Header: Depth=1
movl 12(%rbx,%r13,4), %esi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSolsEi
.Ltmp15:
# %bb.19: # in Loop: Header=BB1_18 Depth=1
.Ltmp16:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64
# in Loop: Header=BB1_18 Depth=1
movl 16(%rbx,%r13,4), %esi
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSolsEi
.Ltmp19:
# %bb.21: # in Loop: Header=BB1_18 Depth=1
.Ltmp20:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp21:
# %bb.22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit66
# in Loop: Header=BB1_18 Depth=1
movl 20(%rbx,%r13,4), %esi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSolsEi
.Ltmp23:
# %bb.23: # in Loop: Header=BB1_18 Depth=1
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit68
# in Loop: Header=BB1_18 Depth=1
addq $3, %r13
cmpq $12289725, %r13 # imm = 0xBB86BD
jb .LBB1_18
# %bb.25:
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp28:
# %bb.26: # %.noexc61
testq %rax, %rax
jne .LBB1_28
# %bb.27:
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $96, %rdi
movl 128(%rsp,%rax), %esi
orl $4, %esi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp30:
.LBB1_28: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $608, %rsp # imm = 0x260
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 656
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_29:
.Ltmp31:
jmp .LBB1_30
.LBB1_32:
.Ltmp26:
.LBB1_30:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp0 # Call between .Ltmp0 and .Ltmp13
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp25-.Ltmp14 # Call between .Ltmp14 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp30-.Ltmp27 # Call between .Ltmp27 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end1-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZL11HandleError10hipError_tPKci
.type _ZL11HandleError10hipError_tPKci,@function
_ZL11HandleError10hipError_tPKci: # @_ZL11HandleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.9, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end2:
.size _ZL11HandleError10hipError_tPKci, .Lfunc_end2-_ZL11HandleError10hipError_tPKci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiP6Sphere, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_s,@object # @dev_s
.bss
.globl dev_s
.p2align 3, 0x0
dev_s:
.quad 0
.size dev_s, 8
.type _Z6kernelPiP6Sphere,@object # @_Z6kernelPiP6Sphere
.section .rodata,"a",@progbits
.globl _Z6kernelPiP6Sphere
.p2align 3, 0x0
_Z6kernelPiP6Sphere:
.quad _Z21__device_stub__kernelPiP6Sphere
.size _Z6kernelPiP6Sphere, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Nyriu/Esercizi_Esempi_CUDA/main/04_raytracer/v1/main.hip"
.size .L.str, 114
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to generate: "
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "img.ppm"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P3\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n255\n"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " in "
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " line "
.size .L.str.9, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiP6Sphere"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiP6Sphere
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym dev_s
.addrsig_sym _Z6kernelPiP6Sphere
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* demonstration of asynchronous program execution
*/
#include <stdio.h>
__global__ void myhost(void) {
printf("Hello World from the host\n");
}
int main(void) {
printf("Hello World! 123\n");
myhost<<<1,1>>>();
//sync threads
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z6myhostv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* demonstration of asynchronous program execution
*/
#include <stdio.h>
__global__ void myhost(void) {
printf("Hello World from the host\n");
}
int main(void) {
printf("Hello World! 123\n");
myhost<<<1,1>>>();
//sync threads
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0015aa86_00000000-6_hw_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6myhostvv
.type _Z24__device_stub__Z6myhostvv, @function
_Z24__device_stub__Z6myhostvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6myhostv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6myhostvv, .-_Z24__device_stub__Z6myhostvv
.globl _Z6myhostv
.type _Z6myhostv, @function
_Z6myhostv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6myhostvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6myhostv, .-_Z6myhostv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World! 123\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6myhostvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6myhostv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6myhostv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* demonstration of asynchronous program execution
*/
#include <stdio.h>
__global__ void myhost(void) {
printf("Hello World from the host\n");
}
int main(void) {
printf("Hello World! 123\n");
myhost<<<1,1>>>();
//sync threads
cudaDeviceSynchronize();
return 0;
} | /**
* demonstration of asynchronous program execution
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void myhost(void) {
printf("Hello World from the host\n");
}
int main(void) {
printf("Hello World! 123\n");
myhost<<<1,1>>>();
//sync threads
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* demonstration of asynchronous program execution
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void myhost(void) {
printf("Hello World from the host\n");
}
int main(void) {
printf("Hello World! 123\n");
myhost<<<1,1>>>();
//sync threads
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6myhostv
.globl _Z6myhostv
.p2align 8
.type _Z6myhostv,@function
_Z6myhostv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 27
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6myhostv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6myhostv, .Lfunc_end0-_Z6myhostv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from the host\n"
.size .str, 27
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6myhostv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6myhostv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* demonstration of asynchronous program execution
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void myhost(void) {
printf("Hello World from the host\n");
}
int main(void) {
printf("Hello World! 123\n");
myhost<<<1,1>>>();
//sync threads
hipDeviceSynchronize();
return 0;
} | .text
.file "hw_device.hip"
.globl _Z21__device_stub__myhostv # -- Begin function _Z21__device_stub__myhostv
.p2align 4, 0x90
.type _Z21__device_stub__myhostv,@function
_Z21__device_stub__myhostv: # @_Z21__device_stub__myhostv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6myhostv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__myhostv, .Lfunc_end0-_Z21__device_stub__myhostv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6myhostv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6myhostv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6myhostv,@object # @_Z6myhostv
.section .rodata,"a",@progbits
.globl _Z6myhostv
.p2align 3, 0x0
_Z6myhostv:
.quad _Z21__device_stub__myhostv
.size _Z6myhostv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6myhostv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World! 123"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__myhostv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6myhostv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6myhostv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6myhostv
.globl _Z6myhostv
.p2align 8
.type _Z6myhostv,@function
_Z6myhostv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 27
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6myhostv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6myhostv, .Lfunc_end0-_Z6myhostv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from the host\n"
.size .str, 27
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6myhostv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6myhostv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015aa86_00000000-6_hw_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6myhostvv
.type _Z24__device_stub__Z6myhostvv, @function
_Z24__device_stub__Z6myhostvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6myhostv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6myhostvv, .-_Z24__device_stub__Z6myhostvv
.globl _Z6myhostv
.type _Z6myhostv, @function
_Z6myhostv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6myhostvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6myhostv, .-_Z6myhostv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World! 123\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6myhostvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6myhostv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6myhostv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hw_device.hip"
.globl _Z21__device_stub__myhostv # -- Begin function _Z21__device_stub__myhostv
.p2align 4, 0x90
.type _Z21__device_stub__myhostv,@function
_Z21__device_stub__myhostv: # @_Z21__device_stub__myhostv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6myhostv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__myhostv, .Lfunc_end0-_Z21__device_stub__myhostv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6myhostv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6myhostv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6myhostv,@object # @_Z6myhostv
.section .rodata,"a",@progbits
.globl _Z6myhostv
.p2align 3, 0x0
_Z6myhostv:
.quad _Z21__device_stub__myhostv
.size _Z6myhostv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6myhostv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World! 123"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__myhostv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6myhostv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
#include "iostream"
__global__ void test_min(int * min_num) {
int thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if (thread_id < 5) {
return;
}
printf("%d %d\n", *min_num, thread_id);
atomicMin(min_num, thread_id);
}
int main(int argc, char * argv[]) {
int * min_num;
int num = 220;
cudaMalloc((void **) &min_num, sizeof(int));
cudaMemcpy(min_num, &num, sizeof(int), cudaMemcpyHostToDevice);
test_min <<<1000, 1>>> (min_num);
cudaMemcpy(&num, min_num, sizeof(int), cudaMemcpyDeviceToHost);
std::cout << num << std::endl;;
} | code for sm_80
Function : _Z8test_minPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R19, SR_CTAID.X ; /* 0x0000000000137919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD R19, R19, c[0x0][0x0], R0 ; /* 0x0000000013137a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R19, 0x5, PT ; /* 0x000000051300780c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fca00078e00ff */
/*00b0*/ LDG.E R18, [R16.64] ; /* 0x0000002410127981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0100*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0110*/ STL.64 [R1], R18 ; /* 0x0000001201007387 */
/* 0x0043ea0000100a00 */
/*0120*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*0130*/ MOV R11, 0x1a0 ; /* 0x000001a0000b7802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R20, 0x120 ; /* 0x0000012000147802 */
/* 0x000fc40000000f00 */
/*0150*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0170*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0180*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0190*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*01a0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*01b0*/ REDUX.MIN.S32 UR5, R19 ; /* 0x00000000130573c4 */
/* 0x000e620000010200 */
/*01c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*01d0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*01e0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*01f0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x002fd8000f8e00ff */
/*0200*/ @P0 RED.E.MIN.S32.STRONG.GPU [R16.64], R3 ; /* 0x000000031000098e */
/* 0x000fe2000c90e3a4 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
#include "iostream"
__global__ void test_min(int * min_num) {
int thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if (thread_id < 5) {
return;
}
printf("%d %d\n", *min_num, thread_id);
atomicMin(min_num, thread_id);
}
int main(int argc, char * argv[]) {
int * min_num;
int num = 220;
cudaMalloc((void **) &min_num, sizeof(int));
cudaMemcpy(min_num, &num, sizeof(int), cudaMemcpyHostToDevice);
test_min <<<1000, 1>>> (min_num);
cudaMemcpy(&num, min_num, sizeof(int), cudaMemcpyDeviceToHost);
std::cout << num << std::endl;;
} | .file "tmpxft_00151a2b_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8test_minPiPi
.type _Z27__device_stub__Z8test_minPiPi, @function
_Z27__device_stub__Z8test_minPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8test_minPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z8test_minPiPi, .-_Z27__device_stub__Z8test_minPiPi
.globl _Z8test_minPi
.type _Z8test_minPi, @function
_Z8test_minPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8test_minPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8test_minPi, .-_Z8test_minPi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $220, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1000, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z27__device_stub__Z8test_minPiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8test_minPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8test_minPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
#include "iostream"
__global__ void test_min(int * min_num) {
int thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if (thread_id < 5) {
return;
}
printf("%d %d\n", *min_num, thread_id);
atomicMin(min_num, thread_id);
}
int main(int argc, char * argv[]) {
int * min_num;
int num = 220;
cudaMalloc((void **) &min_num, sizeof(int));
cudaMemcpy(min_num, &num, sizeof(int), cudaMemcpyHostToDevice);
test_min <<<1000, 1>>> (min_num);
cudaMemcpy(&num, min_num, sizeof(int), cudaMemcpyDeviceToHost);
std::cout << num << std::endl;;
} | #include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include "iostream"
__global__ void test_min(int * min_num) {
int thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if (thread_id < 5) {
return;
}
printf("%d %d\n", *min_num, thread_id);
atomicMin(min_num, thread_id);
}
int main(int argc, char * argv[]) {
int * min_num;
int num = 220;
hipMalloc((void **) &min_num, sizeof(int));
hipMemcpy(min_num, &num, sizeof(int), hipMemcpyHostToDevice);
test_min <<<1000, 1>>> (min_num);
hipMemcpy(&num, min_num, sizeof(int), hipMemcpyDeviceToHost);
std::cout << num << std::endl;;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include "iostream"
__global__ void test_min(int * min_num) {
int thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if (thread_id < 5) {
return;
}
printf("%d %d\n", *min_num, thread_id);
atomicMin(min_num, thread_id);
}
int main(int argc, char * argv[]) {
int * min_num;
int num = 220;
hipMalloc((void **) &min_num, sizeof(int));
hipMemcpy(min_num, &num, sizeof(int), hipMemcpyHostToDevice);
test_min <<<1000, 1>>> (min_num);
hipMemcpy(&num, min_num, sizeof(int), hipMemcpyDeviceToHost);
std::cout << num << std::endl;;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__test_minPi # -- Begin function _Z23__device_stub__test_minPi
.p2align 4, 0x90
.type _Z23__device_stub__test_minPi,@function
_Z23__device_stub__test_minPi: # @_Z23__device_stub__test_minPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8test_minPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__test_minPi, .Lfunc_end0-_Z23__device_stub__test_minPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $220, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8test_minPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8test_minPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8test_minPi,@object # @_Z8test_minPi
.section .rodata,"a",@progbits
.globl _Z8test_minPi
.p2align 3, 0x0
_Z8test_minPi:
.quad _Z23__device_stub__test_minPi
.size _Z8test_minPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8test_minPi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__test_minPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8test_minPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00151a2b_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8test_minPiPi
.type _Z27__device_stub__Z8test_minPiPi, @function
_Z27__device_stub__Z8test_minPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8test_minPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z8test_minPiPi, .-_Z27__device_stub__Z8test_minPiPi
.globl _Z8test_minPi
.type _Z8test_minPi, @function
_Z8test_minPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8test_minPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8test_minPi, .-_Z8test_minPi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $220, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1000, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z27__device_stub__Z8test_minPiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8test_minPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8test_minPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__test_minPi # -- Begin function _Z23__device_stub__test_minPi
.p2align 4, 0x90
.type _Z23__device_stub__test_minPi,@function
_Z23__device_stub__test_minPi: # @_Z23__device_stub__test_minPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8test_minPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__test_minPi, .Lfunc_end0-_Z23__device_stub__test_minPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $220, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8test_minPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8test_minPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8test_minPi,@object # @_Z8test_minPi
.section .rodata,"a",@progbits
.globl _Z8test_minPi
.p2align 3, 0x0
_Z8test_minPi:
.quad _Z23__device_stub__test_minPi
.size _Z8test_minPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8test_minPi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__test_minPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8test_minPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void saxpy_float4s ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS/4; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 tmp1_x, tmp1_y;
tmp1_x = x_as_float4[idx];
tmp1_y = y_as_float4[idx];
float4 result_y;
result_y.x = a * tmp1_x.x + tmp1_y.x;
result_y.y = a * tmp1_x.y + tmp1_y.y;
result_y.z = a * tmp1_x.z + tmp1_y.z;
result_y.w = a * tmp1_x.w + tmp1_y.w;
y_as_float4[idx] = result_y;
}
} | code for sm_80
Function : _Z13saxpy_float4sPfS_fPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R0, R0, R3, 0x7 ; /* 0x0000000300007211 */
/* 0x001fe200078e38ff */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 0.00390625 ; /* 0x00001c00ff037435 */
/* 0x000fc600000001ff */
/*0060*/ IADD3 R2, R0, 0x3100, RZ ; /* 0x0000310000027810 */
/* 0x000fe40007ffe0ff */
/*0070*/ MOV R5, 0x10 ; /* 0x0000001000057802 */
/* 0x001fca0000000f00 */
/*0080*/ IMAD.WIDE.U32 R20, R0, R5, c[0x0][0x168] ; /* 0x00005a0000147625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R6, R0, R5, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0005 */
/*00a0*/ LDG.E.128 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea8000c1e1d00 */
/*00b0*/ LDG.E.128 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1d00 */
/*00c0*/ IADD3 R26, R2, -0x2a00, RZ ; /* 0xffffd600021a7810 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD.WIDE.U32 R28, R26, R5, c[0x0][0x168] ; /* 0x00005a001a1c7625 */
/* 0x000fc800078e0005 */
/*00e0*/ IMAD.WIDE.U32 R26, R26, R5, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fc800078e0005 */
/*00f0*/ FFMA R19, R11, c[0x0][0x170], R15 ; /* 0x00005c000b137a23 */
/* 0x004fe4000000000f */
/*0100*/ FFMA R18, R10, c[0x0][0x170], R14 ; /* 0x00005c000a127a23 */
/* 0x000fe4000000000e */
/*0110*/ FFMA R17, R9, c[0x0][0x170], R13 ; /* 0x00005c0009117a23 */
/* 0x000fe4000000000d */
/*0120*/ FFMA R16, R8, c[0x0][0x170], R12 ; /* 0x00005c0008107a23 */
/* 0x000fca000000000c */
/*0130*/ STG.E.128 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x0001e8000c101d04 */
/*0140*/ LDG.E.128 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x0002a8000c1e1d00 */
/*0150*/ LDG.E.128 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x000ea2000c1e1d00 */
/*0160*/ IADD3 R24, R2, -0x2300, RZ ; /* 0xffffdd0002187810 */
/* 0x000fca0007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R28, R24, R5, c[0x0][0x168] ; /* 0x00005a00181c7625 */
/* 0x002fc800078e0005 */
/*0180*/ IMAD.WIDE.U32 R24, R24, R5, c[0x0][0x160] ; /* 0x0000580018187625 */
/* 0x000fc800078e0005 */
/*0190*/ FFMA R23, R11, c[0x0][0x170], R15 ; /* 0x00005c000b177a23 */
/* 0x004fe4000000000f */
/*01a0*/ FFMA R22, R10, c[0x0][0x170], R14 ; /* 0x00005c000a167a23 */
/* 0x000fe4000000000e */
/*01b0*/ FFMA R21, R9, c[0x0][0x170], R13 ; /* 0x00005c0009157a23 */
/* 0x000fe4000000000d */
/*01c0*/ FFMA R20, R8, c[0x0][0x170], R12 ; /* 0x00005c0008147a23 */
/* 0x000fca000000000c */
/*01d0*/ STG.E.128 [R26.64], R20 ; /* 0x000000141a007986 */
/* 0x0003e8000c101d04 */
/*01e0*/ LDG.E.128 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x0004e8000c1e1d00 */
/*01f0*/ LDG.E.128 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000ee2000c1e1d00 */
/*0200*/ IADD3 R6, R2, -0x1c00, RZ ; /* 0xffffe40002067810 */
/* 0x001fca0007ffe0ff */
/*0210*/ IMAD.WIDE.U32 R28, R6, R5, c[0x0][0x168] ; /* 0x00005a00061c7625 */
/* 0x004fc800078e0005 */
/*0220*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0005 */
/*0230*/ FFMA R19, R11, c[0x0][0x170], R15 ; /* 0x00005c000b137a23 */
/* 0x008fe4000000000f */
/*0240*/ FFMA R18, R10, c[0x0][0x170], R14 ; /* 0x00005c000a127a23 */
/* 0x000fe4000000000e */
/*0250*/ FFMA R17, R9, c[0x0][0x170], R13 ; /* 0x00005c0009117a23 */
/* 0x000fe4000000000d */
/*0260*/ FFMA R16, R8, c[0x0][0x170], R12 ; /* 0x00005c0008107a23 */
/* 0x000fca000000000c */
/*0270*/ STG.E.128 [R24.64], R16 ; /* 0x0000001018007986 */
/* 0x0001e8000c101d04 */
/*0280*/ LDG.E.128 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ea8000c1e1d00 */
/*0290*/ LDG.E.128 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1d00 */
/*02a0*/ IADD3 R20, R2, -0x1500, RZ ; /* 0xffffeb0002147810 */
/* 0x002fca0007ffe0ff */
/*02b0*/ IMAD.WIDE.U32 R26, R20, R5, c[0x0][0x168] ; /* 0x00005a00141a7625 */
/* 0x000fc800078e0005 */
/*02c0*/ IMAD.WIDE.U32 R20, R20, R5, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fc800078e0005 */
/*02d0*/ FFMA R11, R11, c[0x0][0x170], R15 ; /* 0x00005c000b0b7a23 */
/* 0x004fe4000000000f */
/*02e0*/ FFMA R10, R10, c[0x0][0x170], R14 ; /* 0x00005c000a0a7a23 */
/* 0x000fe4000000000e */
/*02f0*/ FFMA R9, R9, c[0x0][0x170], R13 ; /* 0x00005c0009097a23 */
/* 0x000fe4000000000d */
/*0300*/ FFMA R8, R8, c[0x0][0x170], R12 ; /* 0x00005c0008087a23 */
/* 0x000fca000000000c */
/*0310*/ STG.E.128 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0003e8000c101d04 */
/*0320*/ LDG.E.128 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x000ea8000c1e1d00 */
/*0330*/ LDG.E.128 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x001ea2000c1e1d00 */
/*0340*/ IADD3 R22, R2, -0xe00, RZ ; /* 0xfffff20002167810 */
/* 0x000fca0007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R24, R22, R5, c[0x0][0x168] ; /* 0x00005a0016187625 */
/* 0x000fc800078e0005 */
/*0360*/ IMAD.WIDE.U32 R22, R22, R5, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fc800078e0005 */
/*0370*/ FFMA R15, R15, c[0x0][0x170], R19 ; /* 0x00005c000f0f7a23 */
/* 0x004fe40000000013 */
/*0380*/ FFMA R14, R14, c[0x0][0x170], R18 ; /* 0x00005c000e0e7a23 */
/* 0x000fe40000000012 */
/*0390*/ FFMA R13, R13, c[0x0][0x170], R17 ; /* 0x00005c000d0d7a23 */
/* 0x000fe40000000011 */
/*03a0*/ FFMA R12, R12, c[0x0][0x170], R16 ; /* 0x00005c000c0c7a23 */
/* 0x000fca0000000010 */
/*03b0*/ STG.E.128 [R20.64], R12 ; /* 0x0000000c14007986 */
/* 0x0001e8000c101d04 */
/*03c0*/ LDG.E.128 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x002ea8000c1e1d00 */
/*03d0*/ LDG.E.128 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1d00 */
/*03e0*/ IADD3 R6, R2, -0x700, RZ ; /* 0xfffff90002067810 */
/* 0x000fca0007ffe0ff */
/*03f0*/ IMAD.WIDE.U32 R26, R6, R5, c[0x0][0x168] ; /* 0x00005a00061a7625 */
/* 0x000fc800078e0005 */
/*0400*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0005 */
/*0410*/ FFMA R11, R11, c[0x0][0x170], R19 ; /* 0x00005c000b0b7a23 */
/* 0x004fe40000000013 */
/*0420*/ FFMA R10, R10, c[0x0][0x170], R18 ; /* 0x00005c000a0a7a23 */
/* 0x000fe40000000012 */
/*0430*/ FFMA R9, R9, c[0x0][0x170], R17 ; /* 0x00005c0009097a23 */
/* 0x000fe40000000011 */
/*0440*/ FFMA R8, R8, c[0x0][0x170], R16 ; /* 0x00005c0008087a23 */
/* 0x000fca0000000010 */
/*0450*/ STG.E.128 [R22.64], R8 ; /* 0x0000000816007986 */
/* 0x0003e8000c101d04 */
/*0460*/ LDG.E.128 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x001ea8000c1e1d00 */
/*0470*/ LDG.E.128 R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea2000c1e1d00 */
/*0480*/ IADD3 R3, R3, 0x3800, RZ ; /* 0x0000380003037810 */
/* 0x000fe20007ffe0ff */
/*0490*/ FFMA R13, R13, c[0x0][0x170], R17 ; /* 0x00005c000d0d7a23 */
/* 0x004fc40000000011 */
/*04a0*/ FFMA R12, R12, c[0x0][0x170], R16 ; /* 0x00005c000c0c7a23 */
/* 0x000fe40000000010 */
/*04b0*/ FFMA R15, R15, c[0x0][0x170], R19 ; /* 0x00005c000f0f7a23 */
/* 0x000fe40000000013 */
/*04c0*/ FFMA R14, R14, c[0x0][0x170], R18 ; /* 0x00005c000e0e7a23 */
/* 0x000fe40000000012 */
/*04d0*/ IMAD.WIDE.U32 R16, R2, R5, c[0x0][0x168] ; /* 0x00005a0002107625 */
/* 0x000fc600078e0005 */
/*04e0*/ STG.E.128 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001e2000c101d04 */
/*04f0*/ IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc600078e0005 */
/*0500*/ LDG.E.128 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1d00 */
/*0510*/ LDG.E.128 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x002ea2000c1e1d00 */
/*0520*/ ISETP.NE.AND P0, PT, R3, 0xe1c00, PT ; /* 0x000e1c000300780c */
/* 0x000fe40003f05270 */
/*0530*/ IADD3 R2, R2, 0x3800, RZ ; /* 0x0000380002027810 */
/* 0x000fe40007ffe0ff */
/*0540*/ IADD3 R0, R0, 0x3800, RZ ; /* 0x0000380000007810 */
/* 0x000fe20007ffe0ff */
/*0550*/ FFMA R11, R19, c[0x0][0x170], R11 ; /* 0x00005c00130b7a23 */
/* 0x004fc4000000000b */
/*0560*/ FFMA R10, R18, c[0x0][0x170], R10 ; /* 0x00005c00120a7a23 */
/* 0x000fe4000000000a */
/*0570*/ FFMA R9, R17, c[0x0][0x170], R9 ; /* 0x00005c0011097a23 */
/* 0x000fe40000000009 */
/*0580*/ FFMA R8, R16, c[0x0][0x170], R8 ; /* 0x00005c0010087a23 */
/* 0x000fca0000000008 */
/*0590*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e2000c101d04 */
/*05a0*/ @P0 BRA 0x70 ; /* 0xfffffac000000947 */
/* 0x000fea000383ffff */
/*05b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void saxpy_float4s ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS/4; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 tmp1_x, tmp1_y;
tmp1_x = x_as_float4[idx];
tmp1_y = y_as_float4[idx];
float4 result_y;
result_y.x = a * tmp1_x.x + tmp1_y.x;
result_y.y = a * tmp1_x.y + tmp1_y.y;
result_y.z = a * tmp1_x.z + tmp1_y.z;
result_y.w = a * tmp1_x.w + tmp1_y.w;
y_as_float4[idx] = result_y;
}
} | .file "tmpxft_0013df3f_00000000-6_saxpy_float4s.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl
.type _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl, @function
_Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13saxpy_float4sPfS_fPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl, .-_Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl
.globl _Z13saxpy_float4sPfS_fPl
.type _Z13saxpy_float4sPfS_fPl, @function
_Z13saxpy_float4sPfS_fPl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13saxpy_float4sPfS_fPl, .-_Z13saxpy_float4sPfS_fPl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13saxpy_float4sPfS_fPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13saxpy_float4sPfS_fPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void saxpy_float4s ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS/4; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 tmp1_x, tmp1_y;
tmp1_x = x_as_float4[idx];
tmp1_y = y_as_float4[idx];
float4 result_y;
result_y.x = a * tmp1_x.x + tmp1_y.x;
result_y.y = a * tmp1_x.y + tmp1_y.y;
result_y.z = a * tmp1_x.z + tmp1_y.z;
result_y.w = a * tmp1_x.w + tmp1_y.w;
y_as_float4[idx] = result_y;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_float4s ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS/4; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 tmp1_x, tmp1_y;
tmp1_x = x_as_float4[idx];
tmp1_y = y_as_float4[idx];
float4 result_y;
result_y.x = a * tmp1_x.x + tmp1_y.x;
result_y.y = a * tmp1_x.y + tmp1_y.y;
result_y.z = a * tmp1_x.z + tmp1_y.z;
result_y.w = a * tmp1_x.w + tmp1_y.w;
y_as_float4[idx] = result_y;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_float4s ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS/4; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 tmp1_x, tmp1_y;
tmp1_x = x_as_float4[idx];
tmp1_y = y_as_float4[idx];
float4 result_y;
result_y.x = a * tmp1_x.x + tmp1_y.x;
result_y.y = a * tmp1_x.y + tmp1_y.y;
result_y.z = a * tmp1_x.z + tmp1_y.z;
result_y.w = a * tmp1_x.w + tmp1_y.w;
y_as_float4[idx] = result_y;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13saxpy_float4sPfS_fPl
.globl _Z13saxpy_float4sPfS_fPl
.p2align 8
.type _Z13saxpy_float4sPfS_fPl,@function
_Z13saxpy_float4sPfS_fPl:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_lshl_add_u32 v2, s15, 7, v0
v_mov_b32_e32 v1, 0
s_mov_b32 s1, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, s1, v2
s_addk_i32 s1, 0x700
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s1, 0xe0000
v_lshlrev_b64 v[3:4], 4, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
global_load_b128 v[3:6], v[5:6], off
global_load_b128 v[7:10], v[11:12], off
s_waitcnt vmcnt(0)
v_fma_f32 v7, s0, v3, v7
v_fma_f32 v8, s0, v4, v8
v_fma_f32 v9, s0, v5, v9
v_fmac_f32_e32 v10, s0, v6
global_store_b128 v[11:12], v[7:10], off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13saxpy_float4sPfS_fPl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13saxpy_float4sPfS_fPl, .Lfunc_end0-_Z13saxpy_float4sPfS_fPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13saxpy_float4sPfS_fPl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13saxpy_float4sPfS_fPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_float4s ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS/4; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 tmp1_x, tmp1_y;
tmp1_x = x_as_float4[idx];
tmp1_y = y_as_float4[idx];
float4 result_y;
result_y.x = a * tmp1_x.x + tmp1_y.x;
result_y.y = a * tmp1_x.y + tmp1_y.y;
result_y.z = a * tmp1_x.z + tmp1_y.z;
result_y.w = a * tmp1_x.w + tmp1_y.w;
y_as_float4[idx] = result_y;
}
} | .text
.file "saxpy_float4s.hip"
.globl _Z28__device_stub__saxpy_float4sPfS_fPl # -- Begin function _Z28__device_stub__saxpy_float4sPfS_fPl
.p2align 4, 0x90
.type _Z28__device_stub__saxpy_float4sPfS_fPl,@function
_Z28__device_stub__saxpy_float4sPfS_fPl: # @_Z28__device_stub__saxpy_float4sPfS_fPl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13saxpy_float4sPfS_fPl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__saxpy_float4sPfS_fPl, .Lfunc_end0-_Z28__device_stub__saxpy_float4sPfS_fPl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13saxpy_float4sPfS_fPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13saxpy_float4sPfS_fPl,@object # @_Z13saxpy_float4sPfS_fPl
.section .rodata,"a",@progbits
.globl _Z13saxpy_float4sPfS_fPl
.p2align 3, 0x0
_Z13saxpy_float4sPfS_fPl:
.quad _Z28__device_stub__saxpy_float4sPfS_fPl
.size _Z13saxpy_float4sPfS_fPl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13saxpy_float4sPfS_fPl"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__saxpy_float4sPfS_fPl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13saxpy_float4sPfS_fPl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13saxpy_float4sPfS_fPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R0, R0, R3, 0x7 ; /* 0x0000000300007211 */
/* 0x001fe200078e38ff */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 0.00390625 ; /* 0x00001c00ff037435 */
/* 0x000fc600000001ff */
/*0060*/ IADD3 R2, R0, 0x3100, RZ ; /* 0x0000310000027810 */
/* 0x000fe40007ffe0ff */
/*0070*/ MOV R5, 0x10 ; /* 0x0000001000057802 */
/* 0x001fca0000000f00 */
/*0080*/ IMAD.WIDE.U32 R20, R0, R5, c[0x0][0x168] ; /* 0x00005a0000147625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R6, R0, R5, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0005 */
/*00a0*/ LDG.E.128 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea8000c1e1d00 */
/*00b0*/ LDG.E.128 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1d00 */
/*00c0*/ IADD3 R26, R2, -0x2a00, RZ ; /* 0xffffd600021a7810 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD.WIDE.U32 R28, R26, R5, c[0x0][0x168] ; /* 0x00005a001a1c7625 */
/* 0x000fc800078e0005 */
/*00e0*/ IMAD.WIDE.U32 R26, R26, R5, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fc800078e0005 */
/*00f0*/ FFMA R19, R11, c[0x0][0x170], R15 ; /* 0x00005c000b137a23 */
/* 0x004fe4000000000f */
/*0100*/ FFMA R18, R10, c[0x0][0x170], R14 ; /* 0x00005c000a127a23 */
/* 0x000fe4000000000e */
/*0110*/ FFMA R17, R9, c[0x0][0x170], R13 ; /* 0x00005c0009117a23 */
/* 0x000fe4000000000d */
/*0120*/ FFMA R16, R8, c[0x0][0x170], R12 ; /* 0x00005c0008107a23 */
/* 0x000fca000000000c */
/*0130*/ STG.E.128 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x0001e8000c101d04 */
/*0140*/ LDG.E.128 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x0002a8000c1e1d00 */
/*0150*/ LDG.E.128 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x000ea2000c1e1d00 */
/*0160*/ IADD3 R24, R2, -0x2300, RZ ; /* 0xffffdd0002187810 */
/* 0x000fca0007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R28, R24, R5, c[0x0][0x168] ; /* 0x00005a00181c7625 */
/* 0x002fc800078e0005 */
/*0180*/ IMAD.WIDE.U32 R24, R24, R5, c[0x0][0x160] ; /* 0x0000580018187625 */
/* 0x000fc800078e0005 */
/*0190*/ FFMA R23, R11, c[0x0][0x170], R15 ; /* 0x00005c000b177a23 */
/* 0x004fe4000000000f */
/*01a0*/ FFMA R22, R10, c[0x0][0x170], R14 ; /* 0x00005c000a167a23 */
/* 0x000fe4000000000e */
/*01b0*/ FFMA R21, R9, c[0x0][0x170], R13 ; /* 0x00005c0009157a23 */
/* 0x000fe4000000000d */
/*01c0*/ FFMA R20, R8, c[0x0][0x170], R12 ; /* 0x00005c0008147a23 */
/* 0x000fca000000000c */
/*01d0*/ STG.E.128 [R26.64], R20 ; /* 0x000000141a007986 */
/* 0x0003e8000c101d04 */
/*01e0*/ LDG.E.128 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x0004e8000c1e1d00 */
/*01f0*/ LDG.E.128 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000ee2000c1e1d00 */
/*0200*/ IADD3 R6, R2, -0x1c00, RZ ; /* 0xffffe40002067810 */
/* 0x001fca0007ffe0ff */
/*0210*/ IMAD.WIDE.U32 R28, R6, R5, c[0x0][0x168] ; /* 0x00005a00061c7625 */
/* 0x004fc800078e0005 */
/*0220*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0005 */
/*0230*/ FFMA R19, R11, c[0x0][0x170], R15 ; /* 0x00005c000b137a23 */
/* 0x008fe4000000000f */
/*0240*/ FFMA R18, R10, c[0x0][0x170], R14 ; /* 0x00005c000a127a23 */
/* 0x000fe4000000000e */
/*0250*/ FFMA R17, R9, c[0x0][0x170], R13 ; /* 0x00005c0009117a23 */
/* 0x000fe4000000000d */
/*0260*/ FFMA R16, R8, c[0x0][0x170], R12 ; /* 0x00005c0008107a23 */
/* 0x000fca000000000c */
/*0270*/ STG.E.128 [R24.64], R16 ; /* 0x0000001018007986 */
/* 0x0001e8000c101d04 */
/*0280*/ LDG.E.128 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ea8000c1e1d00 */
/*0290*/ LDG.E.128 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1d00 */
/*02a0*/ IADD3 R20, R2, -0x1500, RZ ; /* 0xffffeb0002147810 */
/* 0x002fca0007ffe0ff */
/*02b0*/ IMAD.WIDE.U32 R26, R20, R5, c[0x0][0x168] ; /* 0x00005a00141a7625 */
/* 0x000fc800078e0005 */
/*02c0*/ IMAD.WIDE.U32 R20, R20, R5, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fc800078e0005 */
/*02d0*/ FFMA R11, R11, c[0x0][0x170], R15 ; /* 0x00005c000b0b7a23 */
/* 0x004fe4000000000f */
/*02e0*/ FFMA R10, R10, c[0x0][0x170], R14 ; /* 0x00005c000a0a7a23 */
/* 0x000fe4000000000e */
/*02f0*/ FFMA R9, R9, c[0x0][0x170], R13 ; /* 0x00005c0009097a23 */
/* 0x000fe4000000000d */
/*0300*/ FFMA R8, R8, c[0x0][0x170], R12 ; /* 0x00005c0008087a23 */
/* 0x000fca000000000c */
/*0310*/ STG.E.128 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0003e8000c101d04 */
/*0320*/ LDG.E.128 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x000ea8000c1e1d00 */
/*0330*/ LDG.E.128 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x001ea2000c1e1d00 */
/*0340*/ IADD3 R22, R2, -0xe00, RZ ; /* 0xfffff20002167810 */
/* 0x000fca0007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R24, R22, R5, c[0x0][0x168] ; /* 0x00005a0016187625 */
/* 0x000fc800078e0005 */
/*0360*/ IMAD.WIDE.U32 R22, R22, R5, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fc800078e0005 */
/*0370*/ FFMA R15, R15, c[0x0][0x170], R19 ; /* 0x00005c000f0f7a23 */
/* 0x004fe40000000013 */
/*0380*/ FFMA R14, R14, c[0x0][0x170], R18 ; /* 0x00005c000e0e7a23 */
/* 0x000fe40000000012 */
/*0390*/ FFMA R13, R13, c[0x0][0x170], R17 ; /* 0x00005c000d0d7a23 */
/* 0x000fe40000000011 */
/*03a0*/ FFMA R12, R12, c[0x0][0x170], R16 ; /* 0x00005c000c0c7a23 */
/* 0x000fca0000000010 */
/*03b0*/ STG.E.128 [R20.64], R12 ; /* 0x0000000c14007986 */
/* 0x0001e8000c101d04 */
/*03c0*/ LDG.E.128 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x002ea8000c1e1d00 */
/*03d0*/ LDG.E.128 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1d00 */
/*03e0*/ IADD3 R6, R2, -0x700, RZ ; /* 0xfffff90002067810 */
/* 0x000fca0007ffe0ff */
/*03f0*/ IMAD.WIDE.U32 R26, R6, R5, c[0x0][0x168] ; /* 0x00005a00061a7625 */
/* 0x000fc800078e0005 */
/*0400*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0005 */
/*0410*/ FFMA R11, R11, c[0x0][0x170], R19 ; /* 0x00005c000b0b7a23 */
/* 0x004fe40000000013 */
/*0420*/ FFMA R10, R10, c[0x0][0x170], R18 ; /* 0x00005c000a0a7a23 */
/* 0x000fe40000000012 */
/*0430*/ FFMA R9, R9, c[0x0][0x170], R17 ; /* 0x00005c0009097a23 */
/* 0x000fe40000000011 */
/*0440*/ FFMA R8, R8, c[0x0][0x170], R16 ; /* 0x00005c0008087a23 */
/* 0x000fca0000000010 */
/*0450*/ STG.E.128 [R22.64], R8 ; /* 0x0000000816007986 */
/* 0x0003e8000c101d04 */
/*0460*/ LDG.E.128 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x001ea8000c1e1d00 */
/*0470*/ LDG.E.128 R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea2000c1e1d00 */
/*0480*/ IADD3 R3, R3, 0x3800, RZ ; /* 0x0000380003037810 */
/* 0x000fe20007ffe0ff */
/*0490*/ FFMA R13, R13, c[0x0][0x170], R17 ; /* 0x00005c000d0d7a23 */
/* 0x004fc40000000011 */
/*04a0*/ FFMA R12, R12, c[0x0][0x170], R16 ; /* 0x00005c000c0c7a23 */
/* 0x000fe40000000010 */
/*04b0*/ FFMA R15, R15, c[0x0][0x170], R19 ; /* 0x00005c000f0f7a23 */
/* 0x000fe40000000013 */
/*04c0*/ FFMA R14, R14, c[0x0][0x170], R18 ; /* 0x00005c000e0e7a23 */
/* 0x000fe40000000012 */
/*04d0*/ IMAD.WIDE.U32 R16, R2, R5, c[0x0][0x168] ; /* 0x00005a0002107625 */
/* 0x000fc600078e0005 */
/*04e0*/ STG.E.128 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001e2000c101d04 */
/*04f0*/ IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc600078e0005 */
/*0500*/ LDG.E.128 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1d00 */
/*0510*/ LDG.E.128 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x002ea2000c1e1d00 */
/*0520*/ ISETP.NE.AND P0, PT, R3, 0xe1c00, PT ; /* 0x000e1c000300780c */
/* 0x000fe40003f05270 */
/*0530*/ IADD3 R2, R2, 0x3800, RZ ; /* 0x0000380002027810 */
/* 0x000fe40007ffe0ff */
/*0540*/ IADD3 R0, R0, 0x3800, RZ ; /* 0x0000380000007810 */
/* 0x000fe20007ffe0ff */
/*0550*/ FFMA R11, R19, c[0x0][0x170], R11 ; /* 0x00005c00130b7a23 */
/* 0x004fc4000000000b */
/*0560*/ FFMA R10, R18, c[0x0][0x170], R10 ; /* 0x00005c00120a7a23 */
/* 0x000fe4000000000a */
/*0570*/ FFMA R9, R17, c[0x0][0x170], R9 ; /* 0x00005c0011097a23 */
/* 0x000fe40000000009 */
/*0580*/ FFMA R8, R16, c[0x0][0x170], R8 ; /* 0x00005c0010087a23 */
/* 0x000fca0000000008 */
/*0590*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e2000c101d04 */
/*05a0*/ @P0 BRA 0x70 ; /* 0xfffffac000000947 */
/* 0x000fea000383ffff */
/*05b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13saxpy_float4sPfS_fPl
.globl _Z13saxpy_float4sPfS_fPl
.p2align 8
.type _Z13saxpy_float4sPfS_fPl,@function
_Z13saxpy_float4sPfS_fPl:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_lshl_add_u32 v2, s15, 7, v0
v_mov_b32_e32 v1, 0
s_mov_b32 s1, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, s1, v2
s_addk_i32 s1, 0x700
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s1, 0xe0000
v_lshlrev_b64 v[3:4], 4, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
global_load_b128 v[3:6], v[5:6], off
global_load_b128 v[7:10], v[11:12], off
s_waitcnt vmcnt(0)
v_fma_f32 v7, s0, v3, v7
v_fma_f32 v8, s0, v4, v8
v_fma_f32 v9, s0, v5, v9
v_fmac_f32_e32 v10, s0, v6
global_store_b128 v[11:12], v[7:10], off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13saxpy_float4sPfS_fPl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13saxpy_float4sPfS_fPl, .Lfunc_end0-_Z13saxpy_float4sPfS_fPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13saxpy_float4sPfS_fPl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13saxpy_float4sPfS_fPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013df3f_00000000-6_saxpy_float4s.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl
.type _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl, @function
_Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13saxpy_float4sPfS_fPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl, .-_Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl
.globl _Z13saxpy_float4sPfS_fPl
.type _Z13saxpy_float4sPfS_fPl, @function
_Z13saxpy_float4sPfS_fPl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13saxpy_float4sPfS_fPlPfS_fPl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13saxpy_float4sPfS_fPl, .-_Z13saxpy_float4sPfS_fPl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13saxpy_float4sPfS_fPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13saxpy_float4sPfS_fPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_float4s.hip"
.globl _Z28__device_stub__saxpy_float4sPfS_fPl # -- Begin function _Z28__device_stub__saxpy_float4sPfS_fPl
.p2align 4, 0x90
.type _Z28__device_stub__saxpy_float4sPfS_fPl,@function
_Z28__device_stub__saxpy_float4sPfS_fPl: # @_Z28__device_stub__saxpy_float4sPfS_fPl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13saxpy_float4sPfS_fPl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__saxpy_float4sPfS_fPl, .Lfunc_end0-_Z28__device_stub__saxpy_float4sPfS_fPl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13saxpy_float4sPfS_fPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13saxpy_float4sPfS_fPl,@object # @_Z13saxpy_float4sPfS_fPl
.section .rodata,"a",@progbits
.globl _Z13saxpy_float4sPfS_fPl
.p2align 3, 0x0
_Z13saxpy_float4sPfS_fPl:
.quad _Z28__device_stub__saxpy_float4sPfS_fPl
.size _Z13saxpy_float4sPfS_fPl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13saxpy_float4sPfS_fPl"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__saxpy_float4sPfS_fPl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13saxpy_float4sPfS_fPl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define MASK_WIDTH 5
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
void Smoothing_CPU_Serial(PPMImage *image, PPMImage *image_copy) {
int i, j, y, x;
int total_red, total_blue, total_green;
for (i = 0; i < image->y; i++) {
for (j = 0; j < image->x; j++) {
total_red = total_blue = total_green = 0;
for (y = i - ((MASK_WIDTH-1)/2); y <= (i + ((MASK_WIDTH-1)/2)); y++) {
for (x = j - ((MASK_WIDTH-1)/2); x <= (j + ((MASK_WIDTH-1)/2)); x++) {
if (x >= 0 && y >= 0 && y < image->y && x < image->x) {
total_red += image_copy->data[(y * image->x) + x].red;
total_blue += image_copy->data[(y * image->x) + x].blue;
total_green += image_copy->data[(y * image->x) + x].green;
}
}
}
image->data[(i * image->x) + j].red = total_red / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
char *filename = argv[1];
float milliseconds = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
cudaEventRecord(start);
Smoothing_CPU_Serial(image_output, image);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//t_end = rtclock();
//writePPM(image_output);
printf("Tempo: %0.3f\n",milliseconds);
// fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define MASK_WIDTH 5
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
void Smoothing_CPU_Serial(PPMImage *image, PPMImage *image_copy) {
int i, j, y, x;
int total_red, total_blue, total_green;
for (i = 0; i < image->y; i++) {
for (j = 0; j < image->x; j++) {
total_red = total_blue = total_green = 0;
for (y = i - ((MASK_WIDTH-1)/2); y <= (i + ((MASK_WIDTH-1)/2)); y++) {
for (x = j - ((MASK_WIDTH-1)/2); x <= (j + ((MASK_WIDTH-1)/2)); x++) {
if (x >= 0 && y >= 0 && y < image->y && x < image->x) {
total_red += image_copy->data[(y * image->x) + x].red;
total_blue += image_copy->data[(y * image->x) + x].blue;
total_green += image_copy->data[(y * image->x) + x].green;
}
}
}
image->data[(i * image->x) + j].red = total_red / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
char *filename = argv[1];
float milliseconds = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
cudaEventRecord(start);
Smoothing_CPU_Serial(image_output, image);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//t_end = rtclock();
//writePPM(image_output);
printf("Tempo: %0.3f\n",milliseconds);
// fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
return 0;
} | .file "tmpxft_001a4cdb_00000000-6_serial.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC3:
.string "Unable to allocate memory\n"
.LC4:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC5:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC6:
.string "%d"
.section .rodata.str1.8
.align 8
.LC7:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC8:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC9:
.string "Error loading image '%s'\n"
#NO_APP
.text
.type _ZL7readPPMPKc, @function
_ZL7readPPMPKc:
.LFB2058:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L21
cmpb $80, 16(%rsp)
jne .L4
cmpb $54, 17(%rsp)
jne .L4
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L22
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L7
.L8:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L8
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L8
.L7:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%rbp), %rcx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L23
leaq 12(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L24
cmpl $255, 12(%rsp)
jne .L25
.L12:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L12
movl 0(%rbp), %r14d
movl 4(%rbp), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%rbp)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movslq 4(%rbp), %rdx
cmpq %rax, %rdx
jne .L26
movq %rbx, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movq %rbp, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq %r12, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movq %r12, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L4:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movq %r12, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %r12, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movq %r12, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movq %r12, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL7readPPMPKc, .-_ZL7readPPMPKc
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8
.align 8
.LC10:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L34
.L31:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC11(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.section .rodata.str1.1
.LC12:
.string "P6\n"
.LC13:
.string "Histogram_GPU"
.LC14:
.string "# %s\n"
.LC15:
.string "%d %d\n"
.LC16:
.string "%d\n"
.text
.globl _Z8writePPMP8PPMImage
.type _Z8writePPMP8PPMImage, @function
_Z8writePPMP8PPMImage:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl (%rbx), %ecx
movl 4(%rbx), %r8d
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq 4(%rbx), %rdx
movl (%rbx), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
movq 8(%rbx), %rdi
movq stdout(%rip), %rcx
call fwrite@PLT
movq stdout(%rip), %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8writePPMP8PPMImage, .-_Z8writePPMP8PPMImage
.globl _Z20Smoothing_CPU_SerialP8PPMImageS0_
.type _Z20Smoothing_CPU_SerialP8PPMImageS0_, @function
_Z20Smoothing_CPU_SerialP8PPMImageS0_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r15
movq %rsi, -16(%rsp)
movl $3, %r14d
movl $0, %r8d
cmpl $0, 4(%rdi)
jg .L39
.L38:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
addl $1, %eax
addl $1, %edx
cmpl %esi, %eax
je .L56
.L42:
movl %r8d, %r12d
orl %eax, %r12d
js .L41
cmpl %r8d, 4(%r15)
jle .L41
cmpl %eax, %edi
jle .L41
movslq %edx, %r12
leaq (%r12,%r12,2), %r12
movq -16(%rsp), %rcx
addq 8(%rcx), %r12
movzbl (%r12), %ecx
addl %ecx, %ebp
movzbl 2(%r12), %ecx
addl %ecx, %ebx
movzbl 1(%r12), %r12d
addl %r12d, %r11d
jmp .L41
.L56:
movl -20(%rsp), %ecx
addl $1, %r8d
addl %r13d, %r10d
cmpl %r14d, %r8d
je .L57
.L43:
movl %r9d, %eax
movl %r10d, %edx
movl %ecx, -20(%rsp)
jmp .L42
.L57:
movl -8(%rsp), %edx
movl -4(%rsp), %eax
movl %ecx, %r12d
imull %edx, %edi
leal (%rdi,%rax), %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,2), %rdi
addq 8(%r15), %rdi
movslq %ebp, %rcx
imulq $1374389535, %rcx, %rcx
sarq $35, %rcx
sarl $31, %ebp
subl %ebp, %ecx
movb %cl, (%rdi)
movl %edx, %ecx
imull (%r15), %ecx
addl %eax, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,2), %rdi
addq 8(%r15), %rdi
movslq %ebx, %rcx
imulq $1374389535, %rcx, %rcx
sarq $35, %rcx
sarl $31, %ebx
subl %ebx, %ecx
movb %cl, 2(%rdi)
movl %edx, %ecx
imull (%r15), %ecx
addl %eax, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,2), %rdi
addq 8(%r15), %rdi
movslq %r11d, %rcx
imulq $1374389535, %rcx, %rcx
sarq $35, %rcx
sarl $31, %r11d
subl %r11d, %ecx
movb %cl, 1(%rdi)
addl $1, %eax
movl (%r15), %edi
addl $1, %esi
addl $1, %r9d
cmpl %eax, %edi
jle .L58
.L44:
movl %r12d, %r8d
movl %edi, %r13d
movl %edi, %ecx
imull %r12d, %ecx
leal -2(%rax,%rcx), %r10d
movl $0, %r11d
movl $0, %ebx
movl $0, %ebp
movl %edx, -8(%rsp)
movl %eax, -4(%rsp)
movl %r12d, %ecx
jmp .L43
.L58:
movl %edx, %r8d
.L45:
addl $1, %r8d
addl $1, %r14d
cmpl %r8d, 4(%r15)
jle .L38
.L39:
movl (%r15), %edi
movl $-2, %r13d
movl $3, %esi
movl $0, %eax
leal -2(%r8), %ebp
movl %r8d, %edx
movl %r13d, %r9d
movl %ebp, %r12d
testl %edi, %edi
jg .L44
jmp .L45
.cfi_endproc
.LFE2060:
.size _Z20Smoothing_CPU_SerialP8PPMImageS0_, .-_Z20Smoothing_CPU_SerialP8PPMImageS0_
.section .rodata.str1.8
.align 8
.LC17:
.string "Too many or no one arguments supplied.\n"
.section .rodata.str1.1
.LC19:
.string "Tempo: %0.3f\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L63
.L60:
movq 8(%rbx), %rbx
movl $0x00000000, 4(%rsp)
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbp
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z20Smoothing_CPU_SerialP8PPMImageS0_
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
leaq .LC17(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L60
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define MASK_WIDTH 5
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
void Smoothing_CPU_Serial(PPMImage *image, PPMImage *image_copy) {
int i, j, y, x;
int total_red, total_blue, total_green;
for (i = 0; i < image->y; i++) {
for (j = 0; j < image->x; j++) {
total_red = total_blue = total_green = 0;
for (y = i - ((MASK_WIDTH-1)/2); y <= (i + ((MASK_WIDTH-1)/2)); y++) {
for (x = j - ((MASK_WIDTH-1)/2); x <= (j + ((MASK_WIDTH-1)/2)); x++) {
if (x >= 0 && y >= 0 && y < image->y && x < image->x) {
total_red += image_copy->data[(y * image->x) + x].red;
total_blue += image_copy->data[(y * image->x) + x].blue;
total_green += image_copy->data[(y * image->x) + x].green;
}
}
}
image->data[(i * image->x) + j].red = total_red / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
char *filename = argv[1];
float milliseconds = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
cudaEventRecord(start);
Smoothing_CPU_Serial(image_output, image);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//t_end = rtclock();
//writePPM(image_output);
printf("Tempo: %0.3f\n",milliseconds);
// fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define MASK_WIDTH 5
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
void Smoothing_CPU_Serial(PPMImage *image, PPMImage *image_copy) {
int i, j, y, x;
int total_red, total_blue, total_green;
for (i = 0; i < image->y; i++) {
for (j = 0; j < image->x; j++) {
total_red = total_blue = total_green = 0;
for (y = i - ((MASK_WIDTH-1)/2); y <= (i + ((MASK_WIDTH-1)/2)); y++) {
for (x = j - ((MASK_WIDTH-1)/2); x <= (j + ((MASK_WIDTH-1)/2)); x++) {
if (x >= 0 && y >= 0 && y < image->y && x < image->x) {
total_red += image_copy->data[(y * image->x) + x].red;
total_blue += image_copy->data[(y * image->x) + x].blue;
total_green += image_copy->data[(y * image->x) + x].green;
}
}
}
image->data[(i * image->x) + j].red = total_red / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
char *filename = argv[1];
float milliseconds = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
hipEventRecord(start);
Smoothing_CPU_Serial(image_output, image);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//t_end = rtclock();
//writePPM(image_output);
printf("Tempo: %0.3f\n",milliseconds);
// fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define MASK_WIDTH 5
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
void Smoothing_CPU_Serial(PPMImage *image, PPMImage *image_copy) {
int i, j, y, x;
int total_red, total_blue, total_green;
for (i = 0; i < image->y; i++) {
for (j = 0; j < image->x; j++) {
total_red = total_blue = total_green = 0;
for (y = i - ((MASK_WIDTH-1)/2); y <= (i + ((MASK_WIDTH-1)/2)); y++) {
for (x = j - ((MASK_WIDTH-1)/2); x <= (j + ((MASK_WIDTH-1)/2)); x++) {
if (x >= 0 && y >= 0 && y < image->y && x < image->x) {
total_red += image_copy->data[(y * image->x) + x].red;
total_blue += image_copy->data[(y * image->x) + x].blue;
total_green += image_copy->data[(y * image->x) + x].green;
}
}
}
image->data[(i * image->x) + j].red = total_red / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
char *filename = argv[1];
float milliseconds = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
hipEventRecord(start);
Smoothing_CPU_Serial(image_output, image);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//t_end = rtclock();
//writePPM(image_output);
printf("Tempo: %0.3f\n",milliseconds);
// fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define MASK_WIDTH 5
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
void Smoothing_CPU_Serial(PPMImage *image, PPMImage *image_copy) {
int i, j, y, x;
int total_red, total_blue, total_green;
for (i = 0; i < image->y; i++) {
for (j = 0; j < image->x; j++) {
total_red = total_blue = total_green = 0;
for (y = i - ((MASK_WIDTH-1)/2); y <= (i + ((MASK_WIDTH-1)/2)); y++) {
for (x = j - ((MASK_WIDTH-1)/2); x <= (j + ((MASK_WIDTH-1)/2)); x++) {
if (x >= 0 && y >= 0 && y < image->y && x < image->x) {
total_red += image_copy->data[(y * image->x) + x].red;
total_blue += image_copy->data[(y * image->x) + x].blue;
total_green += image_copy->data[(y * image->x) + x].green;
}
}
}
image->data[(i * image->x) + j].red = total_red / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
image->data[(i * image->x) + j].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
char *filename = argv[1];
float milliseconds = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
hipEventRecord(start);
Smoothing_CPU_Serial(image_output, image);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//t_end = rtclock();
//writePPM(image_output);
printf("Tempo: %0.3f\n",milliseconds);
// fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
return 0;
} | .text
.file "serial.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z8writePPMP8PPMImage # -- Begin function _Z8writePPMP8PPMImage
.p2align 4, 0x90
.type _Z8writePPMP8PPMImage,@function
_Z8writePPMP8PPMImage: # @_Z8writePPMP8PPMImage
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
callq fwrite
movq stdout(%rip), %rdi
movl $.L.str.2, %esi
movl $.L.str.3, %edx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl (%rbx), %edx
movl 4(%rbx), %ecx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movl $255, %edx
xorl %eax, %eax
callq fprintf
movq 8(%rbx), %rdi
movslq (%rbx), %rax
leaq (%rax,%rax,2), %rsi
movslq 4(%rbx), %rdx
movq stdout(%rip), %rcx
callq fwrite
movq stdout(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z8writePPMP8PPMImage, .Lfunc_end1-_Z8writePPMP8PPMImage
.cfi_endproc
# -- End function
.globl _Z20Smoothing_CPU_SerialP8PPMImageS0_ # -- Begin function _Z20Smoothing_CPU_SerialP8PPMImageS0_
.p2align 4, 0x90
.type _Z20Smoothing_CPU_SerialP8PPMImageS0_,@function
_Z20Smoothing_CPU_SerialP8PPMImageS0_: # @_Z20Smoothing_CPU_SerialP8PPMImageS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, -72(%rsp) # 8-byte Spill
movl 4(%rdi), %eax
testl %eax, %eax
jle .LBB2_14
# %bb.1: # %.preheader.lr.ph
movq -72(%rsp), %rcx # 8-byte Reload
movl (%rcx), %ecx
movq %rcx, -48(%rsp) # 8-byte Spill
movslq %ecx, %rdx
leaq (%rdx,%rdx), %rcx
leaq (%rcx,%rcx,2), %rcx
movq $-4, %rdi
subq %rcx, %rdi
movq %rdi, -64(%rsp) # 8-byte Spill
leaq (%rdx,%rdx,2), %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
movq $-2, -56(%rsp) # 8-byte Folded Spill
xorl %ecx, %ecx
movq %rcx, -80(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_13: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq -80(%rsp), %rdi # 8-byte Reload
incq %rdi
incq -56(%rsp) # 8-byte Folded Spill
movq -40(%rsp), %rcx # 8-byte Reload
addq %rcx, -64(%rsp) # 8-byte Folded Spill
movq %rdi, %rcx
movq %rdi, -80(%rsp) # 8-byte Spill
cmpq %rax, %rdi
je .LBB2_14
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
cmpl $0, -48(%rsp) # 4-byte Folded Reload
jle .LBB2_13
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq -80(%rsp), %rdi # 8-byte Reload
leaq 2(%rdi), %rbx
movq -72(%rsp), %rcx # 8-byte Reload
movq 8(%rcx), %rcx
movq %rcx, -24(%rsp) # 8-byte Spill
imulq %rdx, %rdi
movq %rdi, -32(%rsp) # 8-byte Spill
movq $-3, %r14
movq -64(%rsp), %rcx # 8-byte Reload
xorl %r11d, %r11d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_4 Depth=2
movslq %r15d, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %r9
shrq $63, %r9
shrq $35, %rcx
addl %r9d, %ecx
movq -32(%rsp), %r9 # 8-byte Reload
movq -16(%rsp), %r11 # 8-byte Reload
addq %r11, %r9
leaq (%r9,%r9,2), %r9
movq -24(%rsp), %r10 # 8-byte Reload
movb %cl, (%r10,%r9)
movslq %edi, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %rdi
shrq $63, %rdi
shrq $35, %rcx
addl %edi, %ecx
movb %cl, 2(%r10,%r9)
movslq %r8d, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %rdi
shrq $63, %rdi
shrq $35, %rcx
addl %edi, %ecx
movb %cl, 1(%r10,%r9)
incq %r11
incq %r14
movq -8(%rsp), %rcx # 8-byte Reload
addq $3, %rcx
cmpq -48(%rsp), %r11 # 8-byte Folded Reload
je .LBB2_13
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
movq %r11, -16(%rsp) # 8-byte Spill
addq $2, %r11
xorl %r8d, %r8d
movq %rcx, -8(%rsp) # 8-byte Spill
movq -56(%rsp), %r10 # 8-byte Reload
xorl %edi, %edi
xorl %r15d, %r15d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_5 Depth=3
leaq 1(%r10), %r9
addq -40(%rsp), %rcx # 8-byte Folded Reload
cmpq %rbx, %r10
movq %r9, %r10
jge .LBB2_12
.LBB2_5: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_6 Depth 4
movq %rcx, %r13
movq %r14, %r12
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_6 Depth=4
addq $3, %r13
cmpq %r11, %r12
jge .LBB2_11
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# Parent Loop BB2_5 Depth=3
# => This Inner Loop Header: Depth=4
incq %r12
cmpq %rdx, %r12
jge .LBB2_10
# %bb.7: # in Loop: Header=BB2_6 Depth=4
cmpq %rax, %r10
jge .LBB2_10
# %bb.8: # in Loop: Header=BB2_6 Depth=4
movl %r12d, %ebp
orl %r10d, %ebp
andl $-2147483648, %ebp # imm = 0x80000000
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_6 Depth=4
movq 8(%rsi), %rbp
movzbl -2(%rbp,%r13), %r9d
addl %r9d, %r15d
movzbl (%rbp,%r13), %r9d
addl %r9d, %edi
movzbl -1(%rbp,%r13), %r9d
addl %r9d, %r8d
jmp .LBB2_10
.LBB2_14: # %._crit_edge74
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20Smoothing_CPU_SerialP8PPMImageS0_, .Lfunc_end2-_Z20Smoothing_CPU_SerialP8PPMImageS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movq 8(%rbx), %r14
movl $0, 4(%rsp)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %rbx
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %r14
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movq %rbx, %rsi
callq _Z20Smoothing_CPU_SerialP8PPMImageS0_
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL7readPPMPKc
.type _ZL7readPPMPKc,@function
_ZL7readPPMPKc: # @_ZL7readPPMPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.8, %esi
callq fopen
testq %rax, %rax
je .LBB4_1
# %bb.3:
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB4_23
# %bb.4:
cmpb $80, 16(%rsp)
jne .LBB4_6
# %bb.5:
cmpb $54, 17(%rsp)
jne .LBB4_6
# %bb.8:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB4_9
# %bb.10:
movq %rax, %r15
.p2align 4, 0x90
.LBB4_11: # =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
movq %r14, %rdi
callq getc
cmpl $35, %eax
jne .LBB4_13
.LBB4_12: # %.preheader44
# Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
callq getc
cmpl $10, %eax
jne .LBB4_12
jmp .LBB4_11
.LBB4_13: # %._crit_edge
movl %eax, %edi
movq %r14, %rsi
callq ungetc
movq %r15, %rcx
addq $4, %rcx
movl $.L.str.12, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB4_14
# %bb.15:
leaq 12(%rsp), %rdx
movl $.L.str.14, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB4_16
# %bb.17:
cmpl $255, 12(%rsp)
jne .LBB4_18
.p2align 4, 0x90
.LBB4_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB4_19
# %bb.20:
movslq (%r15), %rax
movslq 4(%r15), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r15)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movslq 4(%r15), %rcx
cmpq %rcx, %rax
jne .LBB4_21
# %bb.22:
movq %r14, %rdi
callq fclose
movq %r15, %rax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
jmp .LBB4_2
.LBB4_23:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB4_6:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $36, %esi
jmp .LBB4_7
.LBB4_9:
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $26, %esi
.LBB4_7:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB4_14:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
jmp .LBB4_2
.LBB4_16:
movq stderr(%rip), %rdi
movl $.L.str.15, %esi
jmp .LBB4_2
.LBB4_18:
movq stderr(%rip), %rdi
movl $.L.str.16, %esi
jmp .LBB4_2
.LBB4_21:
movq stderr(%rip), %rdi
movl $.L.str.17, %esi
.LBB4_2:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _ZL7readPPMPKc, .Lfunc_end4-_ZL7readPPMPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "P6\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# %s\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Histogram_GPU"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %d\n"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Tempo: %0.3f\n"
.size .L.str.7, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "rb"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Unable to open file '%s'\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.10, 37
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Unable to allocate memory\n"
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d %d"
.size .L.str.12, 6
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.13, 41
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%d"
.size .L.str.14, 3
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.15, 44
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.16, 38
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Error loading image '%s'\n"
.size .L.str.17, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a4cdb_00000000-6_serial.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC3:
.string "Unable to allocate memory\n"
.LC4:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC5:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC6:
.string "%d"
.section .rodata.str1.8
.align 8
.LC7:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC8:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC9:
.string "Error loading image '%s'\n"
#NO_APP
.text
.type _ZL7readPPMPKc, @function
_ZL7readPPMPKc:
.LFB2058:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L21
cmpb $80, 16(%rsp)
jne .L4
cmpb $54, 17(%rsp)
jne .L4
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L22
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L7
.L8:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L8
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L8
.L7:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%rbp), %rcx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L23
leaq 12(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L24
cmpl $255, 12(%rsp)
jne .L25
.L12:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L12
movl 0(%rbp), %r14d
movl 4(%rbp), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%rbp)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movslq 4(%rbp), %rdx
cmpq %rax, %rdx
jne .L26
movq %rbx, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movq %rbp, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq %r12, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movq %r12, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L4:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movq %r12, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %r12, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movq %r12, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movq %r12, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL7readPPMPKc, .-_ZL7readPPMPKc
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8
.align 8
.LC10:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L34
.L31:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC11(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.section .rodata.str1.1
.LC12:
.string "P6\n"
.LC13:
.string "Histogram_GPU"
.LC14:
.string "# %s\n"
.LC15:
.string "%d %d\n"
.LC16:
.string "%d\n"
.text
.globl _Z8writePPMP8PPMImage
.type _Z8writePPMP8PPMImage, @function
_Z8writePPMP8PPMImage:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl (%rbx), %ecx
movl 4(%rbx), %r8d
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq 4(%rbx), %rdx
movl (%rbx), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
movq 8(%rbx), %rdi
movq stdout(%rip), %rcx
call fwrite@PLT
movq stdout(%rip), %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8writePPMP8PPMImage, .-_Z8writePPMP8PPMImage
.globl _Z20Smoothing_CPU_SerialP8PPMImageS0_
.type _Z20Smoothing_CPU_SerialP8PPMImageS0_, @function
_Z20Smoothing_CPU_SerialP8PPMImageS0_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r15
movq %rsi, -16(%rsp)
movl $3, %r14d
movl $0, %r8d
cmpl $0, 4(%rdi)
jg .L39
.L38:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
addl $1, %eax
addl $1, %edx
cmpl %esi, %eax
je .L56
.L42:
movl %r8d, %r12d
orl %eax, %r12d
js .L41
cmpl %r8d, 4(%r15)
jle .L41
cmpl %eax, %edi
jle .L41
movslq %edx, %r12
leaq (%r12,%r12,2), %r12
movq -16(%rsp), %rcx
addq 8(%rcx), %r12
movzbl (%r12), %ecx
addl %ecx, %ebp
movzbl 2(%r12), %ecx
addl %ecx, %ebx
movzbl 1(%r12), %r12d
addl %r12d, %r11d
jmp .L41
.L56:
movl -20(%rsp), %ecx
addl $1, %r8d
addl %r13d, %r10d
cmpl %r14d, %r8d
je .L57
.L43:
movl %r9d, %eax
movl %r10d, %edx
movl %ecx, -20(%rsp)
jmp .L42
.L57:
movl -8(%rsp), %edx
movl -4(%rsp), %eax
movl %ecx, %r12d
imull %edx, %edi
leal (%rdi,%rax), %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,2), %rdi
addq 8(%r15), %rdi
movslq %ebp, %rcx
imulq $1374389535, %rcx, %rcx
sarq $35, %rcx
sarl $31, %ebp
subl %ebp, %ecx
movb %cl, (%rdi)
movl %edx, %ecx
imull (%r15), %ecx
addl %eax, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,2), %rdi
addq 8(%r15), %rdi
movslq %ebx, %rcx
imulq $1374389535, %rcx, %rcx
sarq $35, %rcx
sarl $31, %ebx
subl %ebx, %ecx
movb %cl, 2(%rdi)
movl %edx, %ecx
imull (%r15), %ecx
addl %eax, %ecx
movslq %ecx, %rcx
leaq (%rcx,%rcx,2), %rdi
addq 8(%r15), %rdi
movslq %r11d, %rcx
imulq $1374389535, %rcx, %rcx
sarq $35, %rcx
sarl $31, %r11d
subl %r11d, %ecx
movb %cl, 1(%rdi)
addl $1, %eax
movl (%r15), %edi
addl $1, %esi
addl $1, %r9d
cmpl %eax, %edi
jle .L58
.L44:
movl %r12d, %r8d
movl %edi, %r13d
movl %edi, %ecx
imull %r12d, %ecx
leal -2(%rax,%rcx), %r10d
movl $0, %r11d
movl $0, %ebx
movl $0, %ebp
movl %edx, -8(%rsp)
movl %eax, -4(%rsp)
movl %r12d, %ecx
jmp .L43
.L58:
movl %edx, %r8d
.L45:
addl $1, %r8d
addl $1, %r14d
cmpl %r8d, 4(%r15)
jle .L38
.L39:
movl (%r15), %edi
movl $-2, %r13d
movl $3, %esi
movl $0, %eax
leal -2(%r8), %ebp
movl %r8d, %edx
movl %r13d, %r9d
movl %ebp, %r12d
testl %edi, %edi
jg .L44
jmp .L45
.cfi_endproc
.LFE2060:
.size _Z20Smoothing_CPU_SerialP8PPMImageS0_, .-_Z20Smoothing_CPU_SerialP8PPMImageS0_
.section .rodata.str1.8
.align 8
.LC17:
.string "Too many or no one arguments supplied.\n"
.section .rodata.str1.1
.LC19:
.string "Tempo: %0.3f\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L63
.L60:
movq 8(%rbx), %rbx
movl $0x00000000, 4(%rsp)
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbp
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z20Smoothing_CPU_SerialP8PPMImageS0_
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
leaq .LC17(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L60
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "serial.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z8writePPMP8PPMImage # -- Begin function _Z8writePPMP8PPMImage
.p2align 4, 0x90
.type _Z8writePPMP8PPMImage,@function
_Z8writePPMP8PPMImage: # @_Z8writePPMP8PPMImage
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
callq fwrite
movq stdout(%rip), %rdi
movl $.L.str.2, %esi
movl $.L.str.3, %edx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl (%rbx), %edx
movl 4(%rbx), %ecx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movl $255, %edx
xorl %eax, %eax
callq fprintf
movq 8(%rbx), %rdi
movslq (%rbx), %rax
leaq (%rax,%rax,2), %rsi
movslq 4(%rbx), %rdx
movq stdout(%rip), %rcx
callq fwrite
movq stdout(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z8writePPMP8PPMImage, .Lfunc_end1-_Z8writePPMP8PPMImage
.cfi_endproc
# -- End function
.globl _Z20Smoothing_CPU_SerialP8PPMImageS0_ # -- Begin function _Z20Smoothing_CPU_SerialP8PPMImageS0_
.p2align 4, 0x90
.type _Z20Smoothing_CPU_SerialP8PPMImageS0_,@function
_Z20Smoothing_CPU_SerialP8PPMImageS0_: # @_Z20Smoothing_CPU_SerialP8PPMImageS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, -72(%rsp) # 8-byte Spill
movl 4(%rdi), %eax
testl %eax, %eax
jle .LBB2_14
# %bb.1: # %.preheader.lr.ph
movq -72(%rsp), %rcx # 8-byte Reload
movl (%rcx), %ecx
movq %rcx, -48(%rsp) # 8-byte Spill
movslq %ecx, %rdx
leaq (%rdx,%rdx), %rcx
leaq (%rcx,%rcx,2), %rcx
movq $-4, %rdi
subq %rcx, %rdi
movq %rdi, -64(%rsp) # 8-byte Spill
leaq (%rdx,%rdx,2), %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
movq $-2, -56(%rsp) # 8-byte Folded Spill
xorl %ecx, %ecx
movq %rcx, -80(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_13: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq -80(%rsp), %rdi # 8-byte Reload
incq %rdi
incq -56(%rsp) # 8-byte Folded Spill
movq -40(%rsp), %rcx # 8-byte Reload
addq %rcx, -64(%rsp) # 8-byte Folded Spill
movq %rdi, %rcx
movq %rdi, -80(%rsp) # 8-byte Spill
cmpq %rax, %rdi
je .LBB2_14
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
cmpl $0, -48(%rsp) # 4-byte Folded Reload
jle .LBB2_13
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq -80(%rsp), %rdi # 8-byte Reload
leaq 2(%rdi), %rbx
movq -72(%rsp), %rcx # 8-byte Reload
movq 8(%rcx), %rcx
movq %rcx, -24(%rsp) # 8-byte Spill
imulq %rdx, %rdi
movq %rdi, -32(%rsp) # 8-byte Spill
movq $-3, %r14
movq -64(%rsp), %rcx # 8-byte Reload
xorl %r11d, %r11d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_4 Depth=2
movslq %r15d, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %r9
shrq $63, %r9
shrq $35, %rcx
addl %r9d, %ecx
movq -32(%rsp), %r9 # 8-byte Reload
movq -16(%rsp), %r11 # 8-byte Reload
addq %r11, %r9
leaq (%r9,%r9,2), %r9
movq -24(%rsp), %r10 # 8-byte Reload
movb %cl, (%r10,%r9)
movslq %edi, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %rdi
shrq $63, %rdi
shrq $35, %rcx
addl %edi, %ecx
movb %cl, 2(%r10,%r9)
movslq %r8d, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %rdi
shrq $63, %rdi
shrq $35, %rcx
addl %edi, %ecx
movb %cl, 1(%r10,%r9)
incq %r11
incq %r14
movq -8(%rsp), %rcx # 8-byte Reload
addq $3, %rcx
cmpq -48(%rsp), %r11 # 8-byte Folded Reload
je .LBB2_13
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
movq %r11, -16(%rsp) # 8-byte Spill
addq $2, %r11
xorl %r8d, %r8d
movq %rcx, -8(%rsp) # 8-byte Spill
movq -56(%rsp), %r10 # 8-byte Reload
xorl %edi, %edi
xorl %r15d, %r15d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_5 Depth=3
leaq 1(%r10), %r9
addq -40(%rsp), %rcx # 8-byte Folded Reload
cmpq %rbx, %r10
movq %r9, %r10
jge .LBB2_12
.LBB2_5: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_6 Depth 4
movq %rcx, %r13
movq %r14, %r12
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_6 Depth=4
addq $3, %r13
cmpq %r11, %r12
jge .LBB2_11
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# Parent Loop BB2_5 Depth=3
# => This Inner Loop Header: Depth=4
incq %r12
cmpq %rdx, %r12
jge .LBB2_10
# %bb.7: # in Loop: Header=BB2_6 Depth=4
cmpq %rax, %r10
jge .LBB2_10
# %bb.8: # in Loop: Header=BB2_6 Depth=4
movl %r12d, %ebp
orl %r10d, %ebp
andl $-2147483648, %ebp # imm = 0x80000000
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_6 Depth=4
movq 8(%rsi), %rbp
movzbl -2(%rbp,%r13), %r9d
addl %r9d, %r15d
movzbl (%rbp,%r13), %r9d
addl %r9d, %edi
movzbl -1(%rbp,%r13), %r9d
addl %r9d, %r8d
jmp .LBB2_10
.LBB2_14: # %._crit_edge74
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20Smoothing_CPU_SerialP8PPMImageS0_, .Lfunc_end2-_Z20Smoothing_CPU_SerialP8PPMImageS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movq 8(%rbx), %r14
movl $0, 4(%rsp)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %rbx
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %r14
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movq %rbx, %rsi
callq _Z20Smoothing_CPU_SerialP8PPMImageS0_
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL7readPPMPKc
.type _ZL7readPPMPKc,@function
_ZL7readPPMPKc: # @_ZL7readPPMPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.8, %esi
callq fopen
testq %rax, %rax
je .LBB4_1
# %bb.3:
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB4_23
# %bb.4:
cmpb $80, 16(%rsp)
jne .LBB4_6
# %bb.5:
cmpb $54, 17(%rsp)
jne .LBB4_6
# %bb.8:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB4_9
# %bb.10:
movq %rax, %r15
.p2align 4, 0x90
.LBB4_11: # =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
movq %r14, %rdi
callq getc
cmpl $35, %eax
jne .LBB4_13
.LBB4_12: # %.preheader44
# Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
callq getc
cmpl $10, %eax
jne .LBB4_12
jmp .LBB4_11
.LBB4_13: # %._crit_edge
movl %eax, %edi
movq %r14, %rsi
callq ungetc
movq %r15, %rcx
addq $4, %rcx
movl $.L.str.12, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB4_14
# %bb.15:
leaq 12(%rsp), %rdx
movl $.L.str.14, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB4_16
# %bb.17:
cmpl $255, 12(%rsp)
jne .LBB4_18
.p2align 4, 0x90
.LBB4_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB4_19
# %bb.20:
movslq (%r15), %rax
movslq 4(%r15), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r15)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movslq 4(%r15), %rcx
cmpq %rcx, %rax
jne .LBB4_21
# %bb.22:
movq %r14, %rdi
callq fclose
movq %r15, %rax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
jmp .LBB4_2
.LBB4_23:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB4_6:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $36, %esi
jmp .LBB4_7
.LBB4_9:
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $26, %esi
.LBB4_7:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB4_14:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
jmp .LBB4_2
.LBB4_16:
movq stderr(%rip), %rdi
movl $.L.str.15, %esi
jmp .LBB4_2
.LBB4_18:
movq stderr(%rip), %rdi
movl $.L.str.16, %esi
jmp .LBB4_2
.LBB4_21:
movq stderr(%rip), %rdi
movl $.L.str.17, %esi
.LBB4_2:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _ZL7readPPMPKc, .Lfunc_end4-_ZL7readPPMPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "P6\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# %s\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Histogram_GPU"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %d\n"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Tempo: %0.3f\n"
.size .L.str.7, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "rb"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Unable to open file '%s'\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.10, 37
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Unable to allocate memory\n"
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d %d"
.size .L.str.12, 6
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.13, 41
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%d"
.size .L.str.14, 3
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.15, 44
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.16, 38
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Error loading image '%s'\n"
.size .L.str.17, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
a[i] = initialValue;
} | code for sm_80
Function : _Z20initializeElementsToiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x160] ; /* 0x0000580000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
a[i] = initialValue;
} | .file "tmpxft_0013a83e_00000000-6_initializeElementsTo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z20initializeElementsToiPiiiPii
.type _Z42__device_stub__Z20initializeElementsToiPiiiPii, @function
_Z42__device_stub__Z20initializeElementsToiPiiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20initializeElementsToiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z20initializeElementsToiPiiiPii, .-_Z42__device_stub__Z20initializeElementsToiPiiiPii
.globl _Z20initializeElementsToiPii
.type _Z20initializeElementsToiPii, @function
_Z20initializeElementsToiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20initializeElementsToiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20initializeElementsToiPii, .-_Z20initializeElementsToiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20initializeElementsToiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20initializeElementsToiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
a[i] = initialValue;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
a[i] = initialValue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
a[i] = initialValue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20initializeElementsToiPii
.globl _Z20initializeElementsToiPii
.p2align 8
.type _Z20initializeElementsToiPii,@function
_Z20initializeElementsToiPii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20initializeElementsToiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20initializeElementsToiPii, .Lfunc_end0-_Z20initializeElementsToiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20initializeElementsToiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20initializeElementsToiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
a[i] = initialValue;
} | .text
.file "initializeElementsTo.hip"
.globl _Z35__device_stub__initializeElementsToiPii # -- Begin function _Z35__device_stub__initializeElementsToiPii
.p2align 4, 0x90
.type _Z35__device_stub__initializeElementsToiPii,@function
_Z35__device_stub__initializeElementsToiPii: # @_Z35__device_stub__initializeElementsToiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20initializeElementsToiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__initializeElementsToiPii, .Lfunc_end0-_Z35__device_stub__initializeElementsToiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20initializeElementsToiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20initializeElementsToiPii,@object # @_Z20initializeElementsToiPii
.section .rodata,"a",@progbits
.globl _Z20initializeElementsToiPii
.p2align 3, 0x0
_Z20initializeElementsToiPii:
.quad _Z35__device_stub__initializeElementsToiPii
.size _Z20initializeElementsToiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20initializeElementsToiPii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__initializeElementsToiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20initializeElementsToiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20initializeElementsToiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x160] ; /* 0x0000580000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20initializeElementsToiPii
.globl _Z20initializeElementsToiPii
.p2align 8
.type _Z20initializeElementsToiPii,@function
_Z20initializeElementsToiPii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20initializeElementsToiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20initializeElementsToiPii, .Lfunc_end0-_Z20initializeElementsToiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20initializeElementsToiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20initializeElementsToiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a83e_00000000-6_initializeElementsTo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z20initializeElementsToiPiiiPii
.type _Z42__device_stub__Z20initializeElementsToiPiiiPii, @function
_Z42__device_stub__Z20initializeElementsToiPiiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20initializeElementsToiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z20initializeElementsToiPiiiPii, .-_Z42__device_stub__Z20initializeElementsToiPiiiPii
.globl _Z20initializeElementsToiPii
.type _Z20initializeElementsToiPii, @function
_Z20initializeElementsToiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20initializeElementsToiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20initializeElementsToiPii, .-_Z20initializeElementsToiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20initializeElementsToiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20initializeElementsToiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "initializeElementsTo.hip"
.globl _Z35__device_stub__initializeElementsToiPii # -- Begin function _Z35__device_stub__initializeElementsToiPii
.p2align 4, 0x90
.type _Z35__device_stub__initializeElementsToiPii,@function
_Z35__device_stub__initializeElementsToiPii: # @_Z35__device_stub__initializeElementsToiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20initializeElementsToiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__initializeElementsToiPii, .Lfunc_end0-_Z35__device_stub__initializeElementsToiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20initializeElementsToiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20initializeElementsToiPii,@object # @_Z20initializeElementsToiPii
.section .rodata,"a",@progbits
.globl _Z20initializeElementsToiPii
.p2align 3, 0x0
_Z20initializeElementsToiPii:
.quad _Z35__device_stub__initializeElementsToiPii
.size _Z20initializeElementsToiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20initializeElementsToiPii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__initializeElementsToiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20initializeElementsToiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/**
* This is my first program in learning parallel programming using CUDA.
* Equivalent to a hello World program :-)
* This program basically performs two tasks:
* 1. It selects suitable CUDA enabled device(GPU) and prints the device properties
* 2. It demonstrate basic parallel addition of two arrays on the device(GPU) using add kernel.
* Author: Shubham Singh
**/
#define N 10 /*N is size of arrays*/
using namespace std;
/************************************************************************************************************
* Function: Kernel to perform addition of two arrays in parallel on device(GPU)
* Input: Takes 3 pointer to int variables pointing to some memory locations on the device(GPU)
* Output: None
************************************************************************************************************/
__global__ void add(int *a, int *b, int *c)
{
int i = blockIdx.x; /*blockIDx.x holds ID of block and acts as index*/
if (i < N)
c[i] = a[i] + b[i];
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* This is my first program in learning parallel programming using CUDA.
* Equivalent to a hello World program :-)
* This program basically performs two tasks:
* 1. It selects suitable CUDA enabled device(GPU) and prints the device properties
* 2. It demonstrate basic parallel addition of two arrays on the device(GPU) using add kernel.
* Author: Shubham Singh
**/
#define N 10 /*N is size of arrays*/
using namespace std;
/************************************************************************************************************
* Function: Kernel to perform addition of two arrays in parallel on device(GPU)
* Input: Takes 3 pointer to int variables pointing to some memory locations on the device(GPU)
* Output: None
************************************************************************************************************/
__global__ void add(int *a, int *b, int *c)
{
int i = blockIdx.x; /*blockIDx.x holds ID of block and acts as index*/
if (i < N)
c[i] = a[i] + b[i];
} | .file "tmpxft_0013f86e_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* This is my first program in learning parallel programming using CUDA.
* Equivalent to a hello World program :-)
* This program basically performs two tasks:
* 1. It selects suitable CUDA enabled device(GPU) and prints the device properties
* 2. It demonstrate basic parallel addition of two arrays on the device(GPU) using add kernel.
* Author: Shubham Singh
**/
#define N 10 /*N is size of arrays*/
using namespace std;
/************************************************************************************************************
* Function: Kernel to perform addition of two arrays in parallel on device(GPU)
* Input: Takes 3 pointer to int variables pointing to some memory locations on the device(GPU)
* Output: None
************************************************************************************************************/
__global__ void add(int *a, int *b, int *c)
{
int i = blockIdx.x; /*blockIDx.x holds ID of block and acts as index*/
if (i < N)
c[i] = a[i] + b[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* This is my first program in learning parallel programming using CUDA.
* Equivalent to a hello World program :-)
* This program basically performs two tasks:
* 1. It selects suitable CUDA enabled device(GPU) and prints the device properties
* 2. It demonstrate basic parallel addition of two arrays on the device(GPU) using add kernel.
* Author: Shubham Singh
**/
#define N 10 /*N is size of arrays*/
using namespace std;
/************************************************************************************************************
* Function: Kernel to perform addition of two arrays in parallel on device(GPU)
* Input: Takes 3 pointer to int variables pointing to some memory locations on the device(GPU)
* Output: None
************************************************************************************************************/
__global__ void add(int *a, int *b, int *c)
{
int i = blockIdx.x; /*blockIDx.x holds ID of block and acts as index*/
if (i < N)
c[i] = a[i] + b[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* This is my first program in learning parallel programming using CUDA.
* Equivalent to a hello World program :-)
* This program basically performs two tasks:
* 1. It selects suitable CUDA enabled device(GPU) and prints the device properties
* 2. It demonstrate basic parallel addition of two arrays on the device(GPU) using add kernel.
* Author: Shubham Singh
**/
#define N 10 /*N is size of arrays*/
using namespace std;
/************************************************************************************************************
* Function: Kernel to perform addition of two arrays in parallel on device(GPU)
* Input: Takes 3 pointer to int variables pointing to some memory locations on the device(GPU)
* Output: None
************************************************************************************************************/
__global__ void add(int *a, int *b, int *c)
{
int i = blockIdx.x; /*blockIDx.x holds ID of block and acts as index*/
if (i < N)
c[i] = a[i] + b[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* This is my first program in learning parallel programming using CUDA.
* Equivalent to a hello World program :-)
* This program basically performs two tasks:
* 1. It selects suitable CUDA enabled device(GPU) and prints the device properties
* 2. It demonstrate basic parallel addition of two arrays on the device(GPU) using add kernel.
* Author: Shubham Singh
**/
#define N 10 /*N is size of arrays*/
using namespace std;
/************************************************************************************************************
* Function: Kernel to perform addition of two arrays in parallel on device(GPU)
* Input: Takes 3 pointer to int variables pointing to some memory locations on the device(GPU)
* Output: None
************************************************************************************************************/
__global__ void add(int *a, int *b, int *c)
{
int i = blockIdx.x; /*blockIDx.x holds ID of block and acts as index*/
if (i < N)
c[i] = a[i] + b[i];
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f86e_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void callOperationSharedDynamic(int *a, int *b, int *res, int k, int p, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid>= n)
{
return;
}
extern __shared__ int data[];
int *s_a = data;
int *s_b = &s_a[n];
int *s_res = &s_b[n];
__shared__ int s_k, s_p;
s_k = k;
s_p = p;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = res[tid];
s_res[tid] = s_a[tid] + s_b[tid];
if (s_res[tid] > s_k)
{
s_res[tid] = s_p;
}
res[tid] = s_res[tid];
} | code for sm_80
Function : _Z26callOperationSharedDynamicPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R6, R0.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x0c0fe400078e020b */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R11, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x040fe400078e020b */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f22000c1e1900 */
/*00e0*/ LEA R8, R0, 0x10, 0x2 ; /* 0x0000001000087811 */
/* 0x000fc400078e10ff */
/*00f0*/ MOV R12, c[0x0][0x178] ; /* 0x00005e00000c7a02 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R9, R11, c[0x0][0x180], R8 ; /* 0x000060000b097a24 */
/* 0x000fc800078e0208 */
/*0120*/ IMAD R11, R11, c[0x0][0x180], R9 ; /* 0x000060000b0b7a24 */
/* 0x000fe200078e0209 */
/*0130*/ STS.64 [RZ], R12 ; /* 0x0000000cff007388 */
/* 0x000fe80000000a00 */
/*0140*/ STS [R0.X4+0x10], R5 ; /* 0x0000100500007388 */
/* 0x004fe80000004800 */
/*0150*/ STS [R9], R6 ; /* 0x0000000609007388 */
/* 0x008fe80000000800 */
/*0160*/ STS [R11], R10 ; /* 0x0000000a0b007388 */
/* 0x010fe80000000800 */
/*0170*/ LDS R4, [R9] ; /* 0x0000000009047984 */
/* 0x000fe80000000800 */
/*0180*/ LDS R7, [R0.X4+0x10] ; /* 0x0000100000077984 */
/* 0x000e240000004800 */
/*0190*/ IADD3 R4, R4, R7, RZ ; /* 0x0000000704047210 */
/* 0x001fc80007ffe0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f04270 */
/*01b0*/ SEL R4, R4, c[0x0][0x17c], !P0 ; /* 0x00005f0004047a07 */
/* 0x000fca0004000000 */
/*01c0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STS [R11], R4 ; /* 0x000000040b007388 */
/* 0x000fe20000000800 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void callOperationSharedDynamic(int *a, int *b, int *res, int k, int p, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid>= n)
{
return;
}
extern __shared__ int data[];
int *s_a = data;
int *s_b = &s_a[n];
int *s_res = &s_b[n];
__shared__ int s_k, s_p;
s_k = k;
s_p = p;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = res[tid];
s_res[tid] = s_a[tid] + s_b[tid];
if (s_res[tid] > s_k)
{
s_res[tid] = s_p;
}
res[tid] = s_res[tid];
} | .file "tmpxft_00094407_00000000-6_callOperationSharedDynamic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii
.type _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii, @function
_Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26callOperationSharedDynamicPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii, .-_Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii
.globl _Z26callOperationSharedDynamicPiS_S_iii
.type _Z26callOperationSharedDynamicPiS_S_iii, @function
_Z26callOperationSharedDynamicPiS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26callOperationSharedDynamicPiS_S_iii, .-_Z26callOperationSharedDynamicPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26callOperationSharedDynamicPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26callOperationSharedDynamicPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void callOperationSharedDynamic(int *a, int *b, int *res, int k, int p, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid>= n)
{
return;
}
extern __shared__ int data[];
int *s_a = data;
int *s_b = &s_a[n];
int *s_res = &s_b[n];
__shared__ int s_k, s_p;
s_k = k;
s_p = p;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = res[tid];
s_res[tid] = s_a[tid] + s_b[tid];
if (s_res[tid] > s_k)
{
s_res[tid] = s_p;
}
res[tid] = s_res[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperationSharedDynamic(int *a, int *b, int *res, int k, int p, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid>= n)
{
return;
}
extern __shared__ int data[];
int *s_a = data;
int *s_b = &s_a[n];
int *s_res = &s_b[n];
__shared__ int s_k, s_p;
s_k = k;
s_p = p;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = res[tid];
s_res[tid] = s_a[tid] + s_b[tid];
if (s_res[tid] > s_k)
{
s_res[tid] = s_p;
}
res[tid] = s_res[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperationSharedDynamic(int *a, int *b, int *res, int k, int p, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid>= n)
{
return;
}
extern __shared__ int data[];
int *s_a = data;
int *s_b = &s_a[n];
int *s_res = &s_b[n];
__shared__ int s_k, s_p;
s_k = k;
s_p = p;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = res[tid];
s_res[tid] = s_a[tid] + s_b[tid];
if (s_res[tid] > s_k)
{
s_res[tid] = s_p;
}
res[tid] = s_res[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26callOperationSharedDynamicPiS_S_iii
.globl _Z26callOperationSharedDynamicPiS_S_iii
.p2align 8
.type _Z26callOperationSharedDynamicPiS_S_iii,@function
_Z26callOperationSharedDynamicPiS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[2:3], off
s_lshl_b32 s0, s8, 2
v_add_nc_u32_e32 v6, 0, v1
s_add_i32 s1, s0, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v7, s1, v1
v_add3_u32 v1, s1, s0, v1
s_waitcnt vmcnt(2)
ds_store_b32 v6, v0
s_waitcnt vmcnt(1)
ds_store_b32 v7, v4
s_waitcnt vmcnt(0)
ds_store_b32 v1, v5
ds_load_b32 v0, v6
ds_load_b32 v4, v7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s6, v0
v_cndmask_b32_e64 v0, v0, s7, vcc_lo
ds_store_b32 v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26callOperationSharedDynamicPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26callOperationSharedDynamicPiS_S_iii, .Lfunc_end0-_Z26callOperationSharedDynamicPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26callOperationSharedDynamicPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26callOperationSharedDynamicPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void callOperationSharedDynamic(int *a, int *b, int *res, int k, int p, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid>= n)
{
return;
}
extern __shared__ int data[];
int *s_a = data;
int *s_b = &s_a[n];
int *s_res = &s_b[n];
__shared__ int s_k, s_p;
s_k = k;
s_p = p;
s_a[tid] = a[tid];
s_b[tid] = b[tid];
s_res[tid] = res[tid];
s_res[tid] = s_a[tid] + s_b[tid];
if (s_res[tid] > s_k)
{
s_res[tid] = s_p;
}
res[tid] = s_res[tid];
} | .text
.file "callOperationSharedDynamic.hip"
.globl _Z41__device_stub__callOperationSharedDynamicPiS_S_iii # -- Begin function _Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.p2align 4, 0x90
.type _Z41__device_stub__callOperationSharedDynamicPiS_S_iii,@function
_Z41__device_stub__callOperationSharedDynamicPiS_S_iii: # @_Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26callOperationSharedDynamicPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__callOperationSharedDynamicPiS_S_iii, .Lfunc_end0-_Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26callOperationSharedDynamicPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26callOperationSharedDynamicPiS_S_iii,@object # @_Z26callOperationSharedDynamicPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z26callOperationSharedDynamicPiS_S_iii
.p2align 3, 0x0
_Z26callOperationSharedDynamicPiS_S_iii:
.quad _Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.size _Z26callOperationSharedDynamicPiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26callOperationSharedDynamicPiS_S_iii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26callOperationSharedDynamicPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26callOperationSharedDynamicPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R6, R0.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x0c0fe400078e020b */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R11, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x040fe400078e020b */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f22000c1e1900 */
/*00e0*/ LEA R8, R0, 0x10, 0x2 ; /* 0x0000001000087811 */
/* 0x000fc400078e10ff */
/*00f0*/ MOV R12, c[0x0][0x178] ; /* 0x00005e00000c7a02 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R9, R11, c[0x0][0x180], R8 ; /* 0x000060000b097a24 */
/* 0x000fc800078e0208 */
/*0120*/ IMAD R11, R11, c[0x0][0x180], R9 ; /* 0x000060000b0b7a24 */
/* 0x000fe200078e0209 */
/*0130*/ STS.64 [RZ], R12 ; /* 0x0000000cff007388 */
/* 0x000fe80000000a00 */
/*0140*/ STS [R0.X4+0x10], R5 ; /* 0x0000100500007388 */
/* 0x004fe80000004800 */
/*0150*/ STS [R9], R6 ; /* 0x0000000609007388 */
/* 0x008fe80000000800 */
/*0160*/ STS [R11], R10 ; /* 0x0000000a0b007388 */
/* 0x010fe80000000800 */
/*0170*/ LDS R4, [R9] ; /* 0x0000000009047984 */
/* 0x000fe80000000800 */
/*0180*/ LDS R7, [R0.X4+0x10] ; /* 0x0000100000077984 */
/* 0x000e240000004800 */
/*0190*/ IADD3 R4, R4, R7, RZ ; /* 0x0000000704047210 */
/* 0x001fc80007ffe0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f04270 */
/*01b0*/ SEL R4, R4, c[0x0][0x17c], !P0 ; /* 0x00005f0004047a07 */
/* 0x000fca0004000000 */
/*01c0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STS [R11], R4 ; /* 0x000000040b007388 */
/* 0x000fe20000000800 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26callOperationSharedDynamicPiS_S_iii
.globl _Z26callOperationSharedDynamicPiS_S_iii
.p2align 8
.type _Z26callOperationSharedDynamicPiS_S_iii,@function
_Z26callOperationSharedDynamicPiS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[2:3], off
s_lshl_b32 s0, s8, 2
v_add_nc_u32_e32 v6, 0, v1
s_add_i32 s1, s0, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v7, s1, v1
v_add3_u32 v1, s1, s0, v1
s_waitcnt vmcnt(2)
ds_store_b32 v6, v0
s_waitcnt vmcnt(1)
ds_store_b32 v7, v4
s_waitcnt vmcnt(0)
ds_store_b32 v1, v5
ds_load_b32 v0, v6
ds_load_b32 v4, v7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s6, v0
v_cndmask_b32_e64 v0, v0, s7, vcc_lo
ds_store_b32 v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26callOperationSharedDynamicPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26callOperationSharedDynamicPiS_S_iii, .Lfunc_end0-_Z26callOperationSharedDynamicPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26callOperationSharedDynamicPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26callOperationSharedDynamicPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094407_00000000-6_callOperationSharedDynamic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii
.type _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii, @function
_Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26callOperationSharedDynamicPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii, .-_Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii
.globl _Z26callOperationSharedDynamicPiS_S_iii
.type _Z26callOperationSharedDynamicPiS_S_iii, @function
_Z26callOperationSharedDynamicPiS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z26callOperationSharedDynamicPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26callOperationSharedDynamicPiS_S_iii, .-_Z26callOperationSharedDynamicPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26callOperationSharedDynamicPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26callOperationSharedDynamicPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "callOperationSharedDynamic.hip"
.globl _Z41__device_stub__callOperationSharedDynamicPiS_S_iii # -- Begin function _Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.p2align 4, 0x90
.type _Z41__device_stub__callOperationSharedDynamicPiS_S_iii,@function
_Z41__device_stub__callOperationSharedDynamicPiS_S_iii: # @_Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26callOperationSharedDynamicPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__callOperationSharedDynamicPiS_S_iii, .Lfunc_end0-_Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26callOperationSharedDynamicPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26callOperationSharedDynamicPiS_S_iii,@object # @_Z26callOperationSharedDynamicPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z26callOperationSharedDynamicPiS_S_iii
.p2align 3, 0x0
_Z26callOperationSharedDynamicPiS_S_iii:
.quad _Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.size _Z26callOperationSharedDynamicPiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26callOperationSharedDynamicPiS_S_iii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__callOperationSharedDynamicPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26callOperationSharedDynamicPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C"
__global__ void reverseVec(int n, float *a, float *b)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
b[n-1-i] = a[i];
}
} | code for sm_80
Function : reverseVec
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*00b0*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
__global__ void reverseVec(int n, float *a, float *b)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
b[n-1-i] = a[i];
}
} | .file "tmpxft_000acc81_00000000-6_reverseVec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10reverseVeciPfS_iPfS_
.type _Z33__device_stub__Z10reverseVeciPfS_iPfS_, @function
_Z33__device_stub__Z10reverseVeciPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq reverseVec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10reverseVeciPfS_iPfS_, .-_Z33__device_stub__Z10reverseVeciPfS_iPfS_
.globl reverseVec
.type reverseVec, @function
reverseVec:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10reverseVeciPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size reverseVec, .-reverseVec
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "reverseVec"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq reverseVec(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
__global__ void reverseVec(int n, float *a, float *b)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
b[n-1-i] = a[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void reverseVec(int n, float *a, float *b)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
b[n-1-i] = a[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void reverseVec(int n, float *a, float *b)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
b[n-1-i] = a[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected reverseVec
.globl reverseVec
.p2align 8
.type reverseVec,@function
reverseVec:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel reverseVec
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size reverseVec, .Lfunc_end0-reverseVec
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: reverseVec
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: reverseVec.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void reverseVec(int n, float *a, float *b)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
b[n-1-i] = a[i];
}
} | .text
.file "reverseVec.hip"
.globl __device_stub__reverseVec # -- Begin function __device_stub__reverseVec
.p2align 4, 0x90
.type __device_stub__reverseVec,@function
__device_stub__reverseVec: # @__device_stub__reverseVec
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $reverseVec, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__reverseVec, .Lfunc_end0-__device_stub__reverseVec
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $reverseVec, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type reverseVec,@object # @reverseVec
.section .rodata,"a",@progbits
.globl reverseVec
.p2align 3, 0x0
reverseVec:
.quad __device_stub__reverseVec
.size reverseVec, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "reverseVec"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__reverseVec
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym reverseVec
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : reverseVec
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*00b0*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected reverseVec
.globl reverseVec
.p2align 8
.type reverseVec,@function
reverseVec:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel reverseVec
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size reverseVec, .Lfunc_end0-reverseVec
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: reverseVec
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: reverseVec.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000acc81_00000000-6_reverseVec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10reverseVeciPfS_iPfS_
.type _Z33__device_stub__Z10reverseVeciPfS_iPfS_, @function
_Z33__device_stub__Z10reverseVeciPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq reverseVec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10reverseVeciPfS_iPfS_, .-_Z33__device_stub__Z10reverseVeciPfS_iPfS_
.globl reverseVec
.type reverseVec, @function
reverseVec:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10reverseVeciPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size reverseVec, .-reverseVec
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "reverseVec"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq reverseVec(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reverseVec.hip"
.globl __device_stub__reverseVec # -- Begin function __device_stub__reverseVec
.p2align 4, 0x90
.type __device_stub__reverseVec,@function
__device_stub__reverseVec: # @__device_stub__reverseVec
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $reverseVec, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__reverseVec, .Lfunc_end0-__device_stub__reverseVec
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $reverseVec, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type reverseVec,@object # @reverseVec
.section .rodata,"a",@progbits
.globl reverseVec
.p2align 3, 0x0
reverseVec:
.quad __device_stub__reverseVec
.size reverseVec, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "reverseVec"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__reverseVec
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym reverseVec
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define LENGTH_V 1024*1024
#define LENGTH_SHOW 10
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/scan.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
#include <time.h>
void show_vector(char *myString, int lengthMyString, thrust::host_vector<int> vector) {
int j;
printf("\n%s\n",myString);
for (j = 0; j < lengthMyString; j++)
printf("-");
printf("\n");
if (LENGTH_SHOW * 2 < LENGTH_V) {
for (j = 0; j < LENGTH_SHOW; j++)
printf(" %d", vector[j]);
printf(" ...");
for (j = LENGTH_V-LENGTH_SHOW; j < LENGTH_V; j++)
printf(" %d", vector[j]);
printf("\n");
} else {
for (j=0 ; j<LENGTH_V; j++)
printf(" %d", vector[j]);
printf("\n");
}
printf("\n");
}
int RandomNumber () { return ( (std::rand() % 100) - 50); }
int main(void) {
clock_t start, end;
double time_used;
// -----------------------
thrust::host_vector<int> h_vec(LENGTH_V);
srand(time(NULL));
std::generate(h_vec.begin(), h_vec.end(), RandomNumber);
char msg1[] = "Vector original";
show_vector(msg1, strlen(msg1), h_vec);
// -----------------------
// Vector scan (Thrust)
// -----------------------
thrust::device_vector<int> d_vec = h_vec;
start = clock();
thrust::inclusive_scan(d_vec.begin(), d_vec.end(), d_vec.begin());
end = clock();
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
// -----------------------
char msg2[] = "Scan result (GPU)";
show_vector(msg2, strlen(msg2), h_vec);
time_used = 1000.0 * ((double)(end - start)) / CLOCKS_PER_SEC;
printf("Thrust scan kernel processing time: %f millisec. (nº elements %d)\n",time_used, LENGTH_V);
printf("...\n");
return 0;
} | #define LENGTH_V 1024*1024
#define LENGTH_SHOW 10
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/scan.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
#include <time.h>
void show_vector(char *myString, int lengthMyString, thrust::host_vector<int> vector) {
int j;
printf("\n%s\n",myString);
for (j = 0; j < lengthMyString; j++)
printf("-");
printf("\n");
if (LENGTH_SHOW * 2 < LENGTH_V) {
for (j = 0; j < LENGTH_SHOW; j++)
printf(" %d", vector[j]);
printf(" ...");
for (j = LENGTH_V-LENGTH_SHOW; j < LENGTH_V; j++)
printf(" %d", vector[j]);
printf("\n");
} else {
for (j=0 ; j<LENGTH_V; j++)
printf(" %d", vector[j]);
printf("\n");
}
printf("\n");
}
int RandomNumber () { return ( (std::rand() % 100) - 50); }
int main(void) {
clock_t start, end;
double time_used;
// -----------------------
thrust::host_vector<int> h_vec(LENGTH_V);
srand(time(NULL));
std::generate(h_vec.begin(), h_vec.end(), RandomNumber);
char msg1[] = "Vector original";
show_vector(msg1, strlen(msg1), h_vec);
// -----------------------
// Vector scan (Thrust)
// -----------------------
thrust::device_vector<int> d_vec = h_vec;
start = clock();
thrust::inclusive_scan(d_vec.begin(), d_vec.end(), d_vec.begin());
end = clock();
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
// -----------------------
char msg2[] = "Scan result (GPU)";
show_vector(msg2, strlen(msg2), h_vec);
time_used = 1000.0 * ((double)(end - start)) / CLOCKS_PER_SEC;
printf("Thrust scan kernel processing time: %f millisec. (nº elements %d)\n",time_used, LENGTH_V);
printf("...\n");
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void smem_dynamic_test(int * in, int * out, int size)
{
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int smem[];
if (gid < size)
{
smem[tid] = in[gid];
out[gid] = smem[tid];
}
} | code for sm_80
Function : _Z17smem_dynamic_testPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R0 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*00c0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x000fe20000004800 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void smem_dynamic_test(int * in, int * out, int size)
{
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int smem[];
if (gid < size)
{
smem[tid] = in[gid];
out[gid] = smem[tid];
}
} | .file "tmpxft_00045b5a_00000000-6_smem_dynamic_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i
.type _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i, @function
_Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17smem_dynamic_testPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i, .-_Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i
.globl _Z17smem_dynamic_testPiS_i
.type _Z17smem_dynamic_testPiS_i, @function
_Z17smem_dynamic_testPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17smem_dynamic_testPiS_i, .-_Z17smem_dynamic_testPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17smem_dynamic_testPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17smem_dynamic_testPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void smem_dynamic_test(int * in, int * out, int size)
{
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int smem[];
if (gid < size)
{
smem[tid] = in[gid];
out[gid] = smem[tid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smem_dynamic_test(int * in, int * out, int size)
{
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int smem[];
if (gid < size)
{
smem[tid] = in[gid];
out[gid] = smem[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smem_dynamic_test(int * in, int * out, int size)
{
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int smem[];
if (gid < size)
{
smem[tid] = in[gid];
out[gid] = smem[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17smem_dynamic_testPiS_i
.globl _Z17smem_dynamic_testPiS_i
.p2align 8
.type _Z17smem_dynamic_testPiS_i,@function
_Z17smem_dynamic_testPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshl_add_u32 v4, v0, 2, 0
v_add_co_u32 v0, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17smem_dynamic_testPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17smem_dynamic_testPiS_i, .Lfunc_end0-_Z17smem_dynamic_testPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17smem_dynamic_testPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17smem_dynamic_testPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smem_dynamic_test(int * in, int * out, int size)
{
int tid = threadIdx.x;
int gid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int smem[];
if (gid < size)
{
smem[tid] = in[gid];
out[gid] = smem[tid];
}
} | .text
.file "smem_dynamic_test.hip"
.globl _Z32__device_stub__smem_dynamic_testPiS_i # -- Begin function _Z32__device_stub__smem_dynamic_testPiS_i
.p2align 4, 0x90
.type _Z32__device_stub__smem_dynamic_testPiS_i,@function
_Z32__device_stub__smem_dynamic_testPiS_i: # @_Z32__device_stub__smem_dynamic_testPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17smem_dynamic_testPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__smem_dynamic_testPiS_i, .Lfunc_end0-_Z32__device_stub__smem_dynamic_testPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17smem_dynamic_testPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17smem_dynamic_testPiS_i,@object # @_Z17smem_dynamic_testPiS_i
.section .rodata,"a",@progbits
.globl _Z17smem_dynamic_testPiS_i
.p2align 3, 0x0
_Z17smem_dynamic_testPiS_i:
.quad _Z32__device_stub__smem_dynamic_testPiS_i
.size _Z17smem_dynamic_testPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17smem_dynamic_testPiS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__smem_dynamic_testPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17smem_dynamic_testPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17smem_dynamic_testPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R0 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*00c0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x000fe20000004800 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17smem_dynamic_testPiS_i
.globl _Z17smem_dynamic_testPiS_i
.p2align 8
.type _Z17smem_dynamic_testPiS_i,@function
_Z17smem_dynamic_testPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshl_add_u32 v4, v0, 2, 0
v_add_co_u32 v0, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17smem_dynamic_testPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17smem_dynamic_testPiS_i, .Lfunc_end0-_Z17smem_dynamic_testPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17smem_dynamic_testPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17smem_dynamic_testPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045b5a_00000000-6_smem_dynamic_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i
.type _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i, @function
_Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17smem_dynamic_testPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i, .-_Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i
.globl _Z17smem_dynamic_testPiS_i
.type _Z17smem_dynamic_testPiS_i, @function
_Z17smem_dynamic_testPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17smem_dynamic_testPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17smem_dynamic_testPiS_i, .-_Z17smem_dynamic_testPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17smem_dynamic_testPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17smem_dynamic_testPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "smem_dynamic_test.hip"
.globl _Z32__device_stub__smem_dynamic_testPiS_i # -- Begin function _Z32__device_stub__smem_dynamic_testPiS_i
.p2align 4, 0x90
.type _Z32__device_stub__smem_dynamic_testPiS_i,@function
_Z32__device_stub__smem_dynamic_testPiS_i: # @_Z32__device_stub__smem_dynamic_testPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17smem_dynamic_testPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__smem_dynamic_testPiS_i, .Lfunc_end0-_Z32__device_stub__smem_dynamic_testPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17smem_dynamic_testPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17smem_dynamic_testPiS_i,@object # @_Z17smem_dynamic_testPiS_i
.section .rodata,"a",@progbits
.globl _Z17smem_dynamic_testPiS_i
.p2align 3, 0x0
_Z17smem_dynamic_testPiS_i:
.quad _Z32__device_stub__smem_dynamic_testPiS_i
.size _Z17smem_dynamic_testPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17smem_dynamic_testPiS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__smem_dynamic_testPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17smem_dynamic_testPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<fstream>
#include<math.h>
#include<string>
#include<stdio.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
using namespace std;
//#define length 8
#define PI 3.14159265
#define length 8
#define block_len 16
cudaError_t dctWithCuda_1(const double *d, double *D);
cudaError_t dctWithCuda_2(const double *f, double *F);
/*__global__ void dct1(float *f, float *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*len + tidy;
float tmp;
float beta,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length; i++){
int x = i/length;
int y = i%length;
tmp+=((int)data[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(float)alfa*beta*tmp;
}
}*/
__global__ void dct_1(const double *f,double *F){
int bid = blockIdx.x;
//int tid = threadIdx.x;
int i,j;
//double data[length]={0.0};
double tmp;
if(bid<length){
__shared__ double data[length];
for (i=0; i<length; i++)
data[i] = f[bid*length+i];//load row data from f.
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp = (double)(1.0/sqrt(1.0*length));
F[bid] = 0;//why use F[bid]? Do transpose at the same time.
for(j=0; j<length; j++)
F[bid] +=data[j] ;
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
for(i=0; i<length; i++)
data[i] = F[bid*length+1];
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp=(double)(1.0/sqrt(1.0*length));
F[bid]=0;
for(j=0; j<length; j++)
F[bid] += data[i];
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
}
}
__global__ void dct_2(const double *f, double *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*length + tidy;
int i;
double tmp;
double beta ,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length*length; i++){
int x = i/length;
int y = i%length;
tmp += ((double)f[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(double)alfa * beta * tmp;
}
}
int main(){
ifstream infile("/home/zhujian/cuda-workspace/dct_10.16/gradient.txt");
int i=0;
string line;
double f[length*length] = {0.0};
double F[length*length] = {0.0};
while(i<length*length){
if(getline(infile, line)){
f[i] = atof(line.c_str());
cout<<"f[i]: "<<f[i]<<endl;
}
i++;
}
cout<<"before"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cudaError_t cudaStatus = dctWithCuda_1(f,F);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "dctWithCuda_1 failed!");
return 1;
}
cout<<"after"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
return 0;
}
cudaError_t dctWithCuda_1(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_d,length *length* sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_D,length *length* sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_d, d,length *length*sizeof(double),cudaMemcpyHostToDevice);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMemcpy-- failed");
goto Error;
}
//launch a kernel on the GPU
dct_1<<<length,1>>>(dev_d, dev_D);
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaThreadSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = cudaMemcpy(D, dev_D, length*length* sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_d);
cudaFree(dev_D);
return cudaStatus;
}
cudaError_t dctWithCuda_2(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_d,length * sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_D,length * sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_d, d,length *sizeof(double),cudaMemcpyHostToDevice);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed");
goto Error;
}
//launch a kernel on the GPU
dct_2<<<1, (length/block_len)*(length/block_len), block_len*block_len>>>(dev_d, dev_D);
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaThreadSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = cudaMemcpy(D, dev_D, length*length * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_d);
cudaFree(dev_D);
return cudaStatus;
} | .file "tmpxft_000e87f1_00000000-6_dct.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5dct_1PKdPdPKdPd
.type _Z27__device_stub__Z5dct_1PKdPdPKdPd, @function
_Z27__device_stub__Z5dct_1PKdPdPKdPd:
.LFB3828:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5dct_1PKdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z27__device_stub__Z5dct_1PKdPdPKdPd, .-_Z27__device_stub__Z5dct_1PKdPdPKdPd
.globl _Z5dct_1PKdPd
.type _Z5dct_1PKdPd, @function
_Z5dct_1PKdPd:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5dct_1PKdPdPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z5dct_1PKdPd, .-_Z5dct_1PKdPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy-- failed"
.section .rodata.str1.8
.align 8
.LC3:
.string "cudaThreadSynchronize returned error code %d after launching addKernel!\n"
.section .rodata.str1.1
.LC4:
.string "cudaMemcpy failed!"
.text
.globl _Z13dctWithCuda_1PKdPd
.type _Z13dctWithCuda_1PKdPd, @function
_Z13dctWithCuda_1PKdPd:
.LFB3802:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L21
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L22
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L23
movl $1, %ecx
movl $512, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $8, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L17:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L21:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L23:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L24:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z5dct_1PKdPdPKdPd
jmp .L17
.L26:
movl %eax, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.size _Z13dctWithCuda_1PKdPd, .-_Z13dctWithCuda_1PKdPd
.globl _Z27__device_stub__Z5dct_2PKdPdPKdPd
.type _Z27__device_stub__Z5dct_2PKdPdPKdPd, @function
_Z27__device_stub__Z5dct_2PKdPdPKdPd:
.LFB3830:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5dct_2PKdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3830:
.size _Z27__device_stub__Z5dct_2PKdPdPKdPd, .-_Z27__device_stub__Z5dct_2PKdPdPKdPd
.globl _Z5dct_2PKdPd
.type _Z5dct_2PKdPd, @function
_Z5dct_2PKdPd:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5dct_2PKdPdPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _Z5dct_2PKdPd, .-_Z5dct_2PKdPd
.section .rodata.str1.1
.LC5:
.string "cudaMalloc failed"
.text
.globl _Z13dctWithCuda_2PKdPd
.type _Z13dctWithCuda_2PKdPd, @function
_Z13dctWithCuda_2PKdPd:
.LFB3803:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L46
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L47
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L48
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L49
movl $0, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $256, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L42:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L51
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L38
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L46:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L38:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L48:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L49:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L50:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z5dct_2PKdPdPKdPd
jmp .L42
.L51:
movl %eax, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L38
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.size _Z13dctWithCuda_2PKdPd, .-_Z13dctWithCuda_2PKdPd
.section .rodata.str1.1
.LC6:
.string "_Z5dct_2PKdPd"
.LC7:
.string "_Z5dct_1PKdPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3833:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5dct_2PKdPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5dct_1PKdPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3833:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC8:
.string "/home/zhujian/cuda-workspace/dct_10.16/gradient.txt"
.section .rodata.str1.1
.LC9:
.string "f[i]: "
.LC10:
.string "before"
.LC11:
.string " "
.LC12:
.string "dctWithCuda_1 failed!"
.LC13:
.string "after"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1592, %rsp
.cfi_def_cfa_offset 1648
movq %fs:40, %rax
movq %rax, 1576(%rsp)
xorl %eax, %eax
leaq 1056(%rsp), %rdi
movl $8, %edx
leaq .LC8(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 32(%rsp), %rdi
movl $0, %eax
movl $64, %ecx
rep stosq
leaq 544(%rsp), %rdi
movl $64, %ecx
rep stosq
leaq 32(%rsp), %rbx
leaq 544(%rsp), %r13
movq %rsp, %r14
leaq 1056(%rsp), %r15
jmp .L65
.L108:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L105
.LEHB1:
call _ZSt16__throw_bad_castv@PLT
.L96:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 1056(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1576(%rsp), %rax
subq %fs:40, %rax
je .L93
call __stack_chk_fail@PLT
.L105:
call __stack_chk_fail@PLT
.L58:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L59
.L109:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
je .L106
.L60:
addq $8, %rbx
cmpq %r13, %rbx
je .L107
.L65:
movq 1056(%rsp), %rax
movq -24(%rax), %rax
movq 1296(%rsp,%rax), %rbp
testq %rbp, %rbp
je .L108
cmpb $0, 56(%rbp)
je .L58
movzbl 67(%rbp), %edx
.L59:
movsbl %dl, %edx
movq %r14, %rsi
movq %r15, %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L109
.L106:
movl $0, %esi
movq (%rsp), %rdi
call strtod@PLT
movsd %xmm0, (%rbx)
movl $7, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%rbx), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L110
cmpb $0, 56(%r12)
je .L63
movzbl 67(%r12), %esi
.L64:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L111
.L110:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L112
call _ZSt16__throw_bad_castv@PLT
.L112:
call __stack_chk_fail@PLT
.L63:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L64
.L111:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L60
.L107:
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC11(%rip), %r12
jmp .L71
.L115:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testb $7, %bl
je .L113
.L66:
addq $1, %rbx
cmpq $65, %rbx
je .L114
.L71:
movsd 24(%rsp,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L115
.L113:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L116
cmpb $0, 56(%r13)
je .L69
movzbl 67(%r13), %esi
.L70:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L117
.L116:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L118
call _ZSt16__throw_bad_castv@PLT
.L118:
call __stack_chk_fail@PLT
.L69:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L70
.L117:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L66
.L114:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC11(%rip), %r12
jmp .L77
.L121:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testb $7, %bl
je .L119
.L72:
addq $1, %rbx
cmpq $65, %rbx
je .L120
.L77:
movsd 536(%rsp,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L121
.L119:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L122
cmpb $0, 56(%r13)
je .L75
movzbl 67(%r13), %esi
.L76:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L123
.L122:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L124
call _ZSt16__throw_bad_castv@PLT
.L124:
call __stack_chk_fail@PLT
.L75:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L76
.L123:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L72
.L120:
leaq 544(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z13dctWithCuda_1PKdPd
testl %eax, %eax
jne .L125
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L126
.L125:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L127
.L126:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC11(%rip), %r12
jmp .L85
.L130:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testb $7, %bl
je .L128
.L80:
addq $1, %rbx
cmpq $65, %rbx
je .L129
.L85:
movsd 24(%rsp,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L130
.L128:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L131
cmpb $0, 56(%r13)
je .L83
movzbl 67(%r13), %esi
.L84:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L132
.L131:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L133
call _ZSt16__throw_bad_castv@PLT
.L133:
call __stack_chk_fail@PLT
.L83:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L84
.L132:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L80
.L129:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC11(%rip), %r12
jmp .L91
.L136:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testb $7, %bl
je .L134
.L86:
addq $1, %rbx
cmpq $65, %rbx
je .L135
.L91:
movsd 536(%rsp,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L136
.L134:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L137
cmpb $0, 56(%r13)
je .L89
movzbl 67(%r13), %esi
.L90:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L138
.L137:
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L139
call _ZSt16__throw_bad_castv@PLT
.L139:
call __stack_chk_fail@PLT
.L89:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L90
.L138:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE1:
jmp .L86
.L135:
movl $0, %ebx
.L79:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 1056(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1576(%rsp), %rax
subq %fs:40, %rax
jne .L140
movl %ebx, %eax
addq $1592, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L127:
.cfi_restore_state
movl $1, %ebx
jmp .L79
.L93:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L140:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L96-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<fstream>
#include<math.h>
#include<string>
#include<stdio.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
using namespace std;
//#define length 8
#define PI 3.14159265
#define length 8
#define block_len 16
cudaError_t dctWithCuda_1(const double *d, double *D);
cudaError_t dctWithCuda_2(const double *f, double *F);
/*__global__ void dct1(float *f, float *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*len + tidy;
float tmp;
float beta,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length; i++){
int x = i/length;
int y = i%length;
tmp+=((int)data[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(float)alfa*beta*tmp;
}
}*/
__global__ void dct_1(const double *f,double *F){
int bid = blockIdx.x;
//int tid = threadIdx.x;
int i,j;
//double data[length]={0.0};
double tmp;
if(bid<length){
__shared__ double data[length];
for (i=0; i<length; i++)
data[i] = f[bid*length+i];//load row data from f.
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp = (double)(1.0/sqrt(1.0*length));
F[bid] = 0;//why use F[bid]? Do transpose at the same time.
for(j=0; j<length; j++)
F[bid] +=data[j] ;
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
for(i=0; i<length; i++)
data[i] = F[bid*length+1];
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp=(double)(1.0/sqrt(1.0*length));
F[bid]=0;
for(j=0; j<length; j++)
F[bid] += data[i];
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
}
}
__global__ void dct_2(const double *f, double *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*length + tidy;
int i;
double tmp;
double beta ,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length*length; i++){
int x = i/length;
int y = i%length;
tmp += ((double)f[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(double)alfa * beta * tmp;
}
}
int main(){
ifstream infile("/home/zhujian/cuda-workspace/dct_10.16/gradient.txt");
int i=0;
string line;
double f[length*length] = {0.0};
double F[length*length] = {0.0};
while(i<length*length){
if(getline(infile, line)){
f[i] = atof(line.c_str());
cout<<"f[i]: "<<f[i]<<endl;
}
i++;
}
cout<<"before"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cudaError_t cudaStatus = dctWithCuda_1(f,F);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "dctWithCuda_1 failed!");
return 1;
}
cout<<"after"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
return 0;
}
cudaError_t dctWithCuda_1(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_d,length *length* sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_D,length *length* sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_d, d,length *length*sizeof(double),cudaMemcpyHostToDevice);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMemcpy-- failed");
goto Error;
}
//launch a kernel on the GPU
dct_1<<<length,1>>>(dev_d, dev_D);
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaThreadSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = cudaMemcpy(D, dev_D, length*length* sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_d);
cudaFree(dev_D);
return cudaStatus;
}
cudaError_t dctWithCuda_2(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_d,length * sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_D,length * sizeof(double));
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_d, d,length *sizeof(double),cudaMemcpyHostToDevice);
if(cudaStatus != cudaSuccess){
fprintf(stderr, "cudaMalloc failed");
goto Error;
}
//launch a kernel on the GPU
dct_2<<<1, (length/block_len)*(length/block_len), block_len*block_len>>>(dev_d, dev_D);
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaThreadSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = cudaMemcpy(D, dev_D, length*length * sizeof(double), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_d);
cudaFree(dev_D);
return cudaStatus;
} | #include<iostream>
#include<fstream>
#include<math.h>
#include<string>
#include<stdio.h>
#include<hip/hip_runtime.h>
using namespace std;
//#define length 8
#define PI 3.14159265
#define length 8
#define block_len 16
hipError_t dctWithCuda_1(const double *d, double *D);
hipError_t dctWithCuda_2(const double *f, double *F);
/*__global__ void dct1(float *f, float *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*len + tidy;
float tmp;
float beta,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length; i++){
int x = i/length;
int y = i%length;
tmp+=((int)data[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(float)alfa*beta*tmp;
}
}*/
__global__ void dct_1(const double *f,double *F){
int bid = blockIdx.x;
//int tid = threadIdx.x;
int i,j;
//double data[length]={0.0};
double tmp;
if(bid<length){
__shared__ double data[length];
for (i=0; i<length; i++)
data[i] = f[bid*length+i];//load row data from f.
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp = (double)(1.0/sqrt(1.0*length));
F[bid] = 0;//why use F[bid]? Do transpose at the same time.
for(j=0; j<length; j++)
F[bid] +=data[j] ;
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
for(i=0; i<length; i++)
data[i] = F[bid*length+1];
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp=(double)(1.0/sqrt(1.0*length));
F[bid]=0;
for(j=0; j<length; j++)
F[bid] += data[i];
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
}
}
__global__ void dct_2(const double *f, double *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*length + tidy;
int i;
double tmp;
double beta ,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length*length; i++){
int x = i/length;
int y = i%length;
tmp += ((double)f[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(double)alfa * beta * tmp;
}
}
int main(){
ifstream infile("/home/zhujian/cuda-workspace/dct_10.16/gradient.txt");
int i=0;
string line;
double f[length*length] = {0.0};
double F[length*length] = {0.0};
while(i<length*length){
if(getline(infile, line)){
f[i] = atof(line.c_str());
cout<<"f[i]: "<<f[i]<<endl;
}
i++;
}
cout<<"before"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
hipError_t cudaStatus = dctWithCuda_1(f,F);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "dctWithCuda_1 failed!");
return 1;
}
cout<<"after"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
return 0;
}
hipError_t dctWithCuda_1(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_d,length *length* sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_D,length *length* sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_d, d,length *length*sizeof(double),hipMemcpyHostToDevice);
if(cudaStatus != hipSuccess){
fprintf(stderr, "cudaMemcpy-- failed");
goto Error;
}
//launch a kernel on the GPU
dct_1<<<length,1>>>(dev_d, dev_D);
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = hipMemcpy(D, dev_D, length*length* sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_d);
hipFree(dev_D);
return cudaStatus;
}
hipError_t dctWithCuda_2(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_d,length * sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_D,length * sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_d, d,length *sizeof(double),hipMemcpyHostToDevice);
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed");
goto Error;
}
//launch a kernel on the GPU
dct_2<<<1, (length/block_len)*(length/block_len), block_len*block_len>>>(dev_d, dev_D);
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = hipMemcpy(D, dev_D, length*length * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_d);
hipFree(dev_D);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<iostream>
#include<fstream>
#include<math.h>
#include<string>
#include<stdio.h>
#include<hip/hip_runtime.h>
using namespace std;
//#define length 8
#define PI 3.14159265
#define length 8
#define block_len 16
hipError_t dctWithCuda_1(const double *d, double *D);
hipError_t dctWithCuda_2(const double *f, double *F);
/*__global__ void dct1(float *f, float *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*len + tidy;
float tmp;
float beta,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length; i++){
int x = i/length;
int y = i%length;
tmp+=((int)data[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(float)alfa*beta*tmp;
}
}*/
__global__ void dct_1(const double *f,double *F){
int bid = blockIdx.x;
//int tid = threadIdx.x;
int i,j;
//double data[length]={0.0};
double tmp;
if(bid<length){
__shared__ double data[length];
for (i=0; i<length; i++)
data[i] = f[bid*length+i];//load row data from f.
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp = (double)(1.0/sqrt(1.0*length));
F[bid] = 0;//why use F[bid]? Do transpose at the same time.
for(j=0; j<length; j++)
F[bid] +=data[j] ;
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
for(i=0; i<length; i++)
data[i] = F[bid*length+1];
__syncthreads();
for(i=0; i<length; i++){
if(i==0){
tmp=(double)(1.0/sqrt(1.0*length));
F[bid]=0;
for(j=0; j<length; j++)
F[bid] += data[i];
F[bid] *= tmp;
}
else{
tmp = (double)(sqrt(2.0/(1.0*length)));
for(i=1; i<length; i++){
F[i*length+bid] = 0;
for(j=0; j<length; j++)
F[i*length+bid] += (double)(data[j]*cos((2*j+1)*i*PI/(2*length)));
F[i*length+bid] *= tmp;
}
}
}
__syncthreads();
}
}
__global__ void dct_2(const double *f, double *F){
int tidy = blockIdx.x*blockDim.x + threadIdx.x;
int tidx = blockIdx.y*blockDim.y + threadIdx.y;
int index = tidx*length + tidy;
int i;
double tmp;
double beta ,alfa;
if(tidx == 0)
beta = sqrt(1.0/length);
else
beta = sqrt(2.0/length);
if(tidy == 0)
alfa = sqrt(1.0/length);
else
alfa = sqrt(2.0/length);
if(tidx<length && tidy<length){
for(i=0; i<length*length; i++){
int x = i/length;
int y = i%length;
tmp += ((double)f[i])*cos((2*x+1)*tidx*PI/(2.0*length))*
cos((2*y+1)*tidy*PI/(2.0*length));
}
F[index]=(double)alfa * beta * tmp;
}
}
int main(){
ifstream infile("/home/zhujian/cuda-workspace/dct_10.16/gradient.txt");
int i=0;
string line;
double f[length*length] = {0.0};
double F[length*length] = {0.0};
while(i<length*length){
if(getline(infile, line)){
f[i] = atof(line.c_str());
cout<<"f[i]: "<<f[i]<<endl;
}
i++;
}
cout<<"before"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
hipError_t cudaStatus = dctWithCuda_1(f,F);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "dctWithCuda_1 failed!");
return 1;
}
cout<<"after"<<endl;
for(i=0; i<length*length; i++){
cout<<f[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
cout<<endl;
for(i=0; i<length*length; i++){
cout<<F[i]<<" ";
if ((i+1)%length==0)
cout<<endl;
}
return 0;
}
hipError_t dctWithCuda_1(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_d,length *length* sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_D,length *length* sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_d, d,length *length*sizeof(double),hipMemcpyHostToDevice);
if(cudaStatus != hipSuccess){
fprintf(stderr, "cudaMemcpy-- failed");
goto Error;
}
//launch a kernel on the GPU
dct_1<<<length,1>>>(dev_d, dev_D);
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = hipMemcpy(D, dev_D, length*length* sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_d);
hipFree(dev_D);
return cudaStatus;
}
hipError_t dctWithCuda_2(const double *d, double *D){
double *dev_d = 0;
double *dev_D = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_d,length * sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_D,length * sizeof(double));
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
//copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_d, d,length *sizeof(double),hipMemcpyHostToDevice);
if(cudaStatus != hipSuccess){
fprintf(stderr, "hipMalloc failed");
goto Error;
}
//launch a kernel on the GPU
dct_2<<<1, (length/block_len)*(length/block_len), block_len*block_len>>>(dev_d, dev_D);
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
cudaStatus = hipMemcpy(D, dev_D, length*length * sizeof(double), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_d);
hipFree(dev_D);
return cudaStatus;
} | .text
.file "dct.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__dct_1PKdPd # -- Begin function _Z20__device_stub__dct_1PKdPd
.p2align 4, 0x90
.type _Z20__device_stub__dct_1PKdPd,@function
_Z20__device_stub__dct_1PKdPd: # @_Z20__device_stub__dct_1PKdPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5dct_1PKdPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__dct_1PKdPd, .Lfunc_end0-_Z20__device_stub__dct_1PKdPd
.cfi_endproc
# -- End function
.globl _Z20__device_stub__dct_2PKdPd # -- Begin function _Z20__device_stub__dct_2PKdPd
.p2align 4, 0x90
.type _Z20__device_stub__dct_2PKdPd,@function
_Z20__device_stub__dct_2PKdPd: # @_Z20__device_stub__dct_2PKdPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5dct_2PKdPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z20__device_stub__dct_2PKdPd, .Lfunc_end1-_Z20__device_stub__dct_2PKdPd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 40(%rsp), %rbx
movl $.L.str, %esi
movq %rbx, %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
leaq 24(%rsp), %r13
movq %r13, 8(%rsp)
movq $0, 16(%rsp)
movb $0, 24(%rsp)
leaq 560(%rsp), %rdi
xorl %ebp, %ebp
movl $512, %edx # imm = 0x200
xorl %esi, %esi
callq memset@PLT
leaq 1072(%rsp), %rdi
movl $512, %edx # imm = 0x200
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %r14
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_19: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB2_1 Depth=1
incq %rbp
cmpq $64, %rbp
je .LBB2_20
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax
movq -24(%rax), %rax
movq 280(%rsp,%rax), %r15
testq %r15, %r15
je .LBB2_2
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_1 Depth=1
cmpb $0, 56(%r15)
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_1 Depth=1
movzbl 67(%r15), %eax
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
.Ltmp0:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp1:
# %bb.7: # %.noexc27
# in Loop: Header=BB2_1 Depth=1
movq (%r15), %rax
.Ltmp2:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp3:
.LBB2_8: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB2_1 Depth=1
.Ltmp4:
movsbl %al, %edx
movq %rbx, %rdi
movq %r14, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp5:
# %bb.9: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# in Loop: Header=BB2_1 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB2_19
# %bb.10: # in Loop: Header=BB2_1 Depth=1
movq 8(%rsp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 560(%rsp,%rbp,8)
.Ltmp6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.11: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB2_1 Depth=1
movsd 560(%rsp,%rbp,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp8:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp9:
# %bb.12: # %_ZNSolsEd.exit
# in Loop: Header=BB2_1 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB2_2
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
# in Loop: Header=BB2_1 Depth=1
cmpb $0, 56(%r12)
je .LBB2_15
# %bb.14: # in Loop: Header=BB2_1 Depth=1
movzbl 67(%r12), %eax
jmp .LBB2_17
.LBB2_15: # in Loop: Header=BB2_1 Depth=1
.Ltmp10:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp11:
# %bb.16: # %.noexc78
# in Loop: Header=BB2_1 Depth=1
movq (%r12), %rax
.Ltmp12:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp13:
.LBB2_17: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i75
# in Loop: Header=BB2_1 Depth=1
.Ltmp14:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp15:
# %bb.18: # %.noexc80
# in Loop: Header=BB2_1 Depth=1
.Ltmp16:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp17:
jmp .LBB2_19
.LBB2_20:
.Ltmp19:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp20:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit34
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_2
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%rbx)
je .LBB2_27
# %bb.23:
movzbl 67(%rbx), %eax
jmp .LBB2_29
.LBB2_27:
.Ltmp21:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp22:
# %bb.28: # %.noexc88
movq (%rbx), %rax
.Ltmp23:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp24:
.LBB2_29: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i85
.Ltmp25:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp26:
# %bb.30: # %.noexc90
.Ltmp27:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp28:
# %bb.31: # %_ZNSolsEPFRSoS_E.exit36.preheader.preheader
movl $1, %r14d
jmp .LBB2_32
.p2align 4, 0x90
.LBB2_42: # %_ZNSolsEPFRSoS_E.exit42
# in Loop: Header=BB2_32 Depth=1
incq %r14
cmpq $65, %r14
je .LBB2_43
.LBB2_32: # %_ZNSolsEPFRSoS_E.exit36.preheader
# =>This Inner Loop Header: Depth=1
movsd 552(%rsp,%r14,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp29:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp30:
# %bb.33: # %_ZNSolsEd.exit38
# in Loop: Header=BB2_32 Depth=1
.Ltmp31:
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp32:
# %bb.34: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit40
# in Loop: Header=BB2_32 Depth=1
testb $7, %r14b
jne .LBB2_42
# %bb.35: # in Loop: Header=BB2_32 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_2
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
# in Loop: Header=BB2_32 Depth=1
cmpb $0, 56(%rbx)
je .LBB2_38
# %bb.37: # in Loop: Header=BB2_32 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB2_40
.LBB2_38: # in Loop: Header=BB2_32 Depth=1
.Ltmp33:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp34:
# %bb.39: # %.noexc99
# in Loop: Header=BB2_32 Depth=1
movq (%rbx), %rax
.Ltmp35:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp36:
.LBB2_40: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i96
# in Loop: Header=BB2_32 Depth=1
.Ltmp37:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp38:
# %bb.41: # %.noexc101
# in Loop: Header=BB2_32 Depth=1
.Ltmp39:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp40:
jmp .LBB2_42
.LBB2_43:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_2
# %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105
cmpb $0, 56(%rbx)
je .LBB2_46
# %bb.45:
movzbl 67(%rbx), %eax
jmp .LBB2_48
.LBB2_46:
.Ltmp42:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp43:
# %bb.47: # %.noexc110
movq (%rbx), %rax
.Ltmp44:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp45:
.LBB2_48: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i107
.Ltmp46:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp47:
# %bb.49: # %.noexc112
.Ltmp48:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp49:
# %bb.50: # %_ZNSolsEPFRSoS_E.exit44.preheader.preheader
movl $1, %r14d
jmp .LBB2_51
.p2align 4, 0x90
.LBB2_61: # %_ZNSolsEPFRSoS_E.exit50
# in Loop: Header=BB2_51 Depth=1
incq %r14
cmpq $65, %r14
je .LBB2_62
.LBB2_51: # %_ZNSolsEPFRSoS_E.exit44.preheader
# =>This Inner Loop Header: Depth=1
movsd 1064(%rsp,%r14,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp50:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp51:
# %bb.52: # %_ZNSolsEd.exit46
# in Loop: Header=BB2_51 Depth=1
.Ltmp52:
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp53:
# %bb.53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit48
# in Loop: Header=BB2_51 Depth=1
testb $7, %r14b
jne .LBB2_61
# %bb.54: # in Loop: Header=BB2_51 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_2
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i116
# in Loop: Header=BB2_51 Depth=1
cmpb $0, 56(%rbx)
je .LBB2_57
# %bb.56: # in Loop: Header=BB2_51 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB2_59
.LBB2_57: # in Loop: Header=BB2_51 Depth=1
.Ltmp54:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp55:
# %bb.58: # %.noexc121
# in Loop: Header=BB2_51 Depth=1
movq (%rbx), %rax
.Ltmp56:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp57:
.LBB2_59: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i118
# in Loop: Header=BB2_51 Depth=1
.Ltmp58:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp59:
# %bb.60: # %.noexc123
# in Loop: Header=BB2_51 Depth=1
.Ltmp60:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp61:
jmp .LBB2_61
.LBB2_62:
.Ltmp63:
leaq 560(%rsp), %rdi
leaq 1072(%rsp), %rsi
callq _Z13dctWithCuda_1PKdPd
.Ltmp64:
# %bb.63:
testl %eax, %eax
jne .LBB2_64
# %bb.68:
.Ltmp65:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp66:
# %bb.69: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit52
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_100
# %bb.70: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i127
cmpb $0, 56(%rbx)
je .LBB2_72
# %bb.71:
movzbl 67(%rbx), %eax
jmp .LBB2_74
.LBB2_72:
.Ltmp67:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp68:
# %bb.73: # %.noexc132
movq (%rbx), %rax
.Ltmp69:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp70:
.LBB2_74: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i129
.Ltmp71:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp72:
# %bb.75: # %.noexc134
.Ltmp73:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp74:
# %bb.76: # %_ZNSolsEPFRSoS_E.exit54.preheader.preheader
movl $1, %r14d
jmp .LBB2_77
.p2align 4, 0x90
.LBB2_87: # %_ZNSolsEPFRSoS_E.exit60
# in Loop: Header=BB2_77 Depth=1
incq %r14
cmpq $65, %r14
je .LBB2_88
.LBB2_77: # %_ZNSolsEPFRSoS_E.exit54.preheader
# =>This Inner Loop Header: Depth=1
movsd 552(%rsp,%r14,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp75:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp76:
# %bb.78: # %_ZNSolsEd.exit56
# in Loop: Header=BB2_77 Depth=1
.Ltmp77:
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp78:
# %bb.79: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit58
# in Loop: Header=BB2_77 Depth=1
testb $7, %r14b
jne .LBB2_87
# %bb.80: # in Loop: Header=BB2_77 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_100
# %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i138
# in Loop: Header=BB2_77 Depth=1
cmpb $0, 56(%rbx)
je .LBB2_83
# %bb.82: # in Loop: Header=BB2_77 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB2_85
.LBB2_83: # in Loop: Header=BB2_77 Depth=1
.Ltmp79:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp80:
# %bb.84: # %.noexc143
# in Loop: Header=BB2_77 Depth=1
movq (%rbx), %rax
.Ltmp81:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp82:
.LBB2_85: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i140
# in Loop: Header=BB2_77 Depth=1
.Ltmp83:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp84:
# %bb.86: # %.noexc145
# in Loop: Header=BB2_77 Depth=1
.Ltmp85:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp86:
jmp .LBB2_87
.LBB2_88:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_100
# %bb.89: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i149
cmpb $0, 56(%rbx)
je .LBB2_91
# %bb.90:
movzbl 67(%rbx), %eax
jmp .LBB2_93
.LBB2_91:
.Ltmp88:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp89:
# %bb.92: # %.noexc154
movq (%rbx), %rax
.Ltmp90:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp91:
.LBB2_93: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i151
.Ltmp92:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp93:
# %bb.94: # %.noexc156
.Ltmp94:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp95:
# %bb.95: # %_ZNSolsEPFRSoS_E.exit62.preheader.preheader
movl $1, %r14d
jmp .LBB2_96
.p2align 4, 0x90
.LBB2_108: # %_ZNSolsEPFRSoS_E.exit68
# in Loop: Header=BB2_96 Depth=1
incq %r14
cmpq $65, %r14
je .LBB2_109
.LBB2_96: # %_ZNSolsEPFRSoS_E.exit62.preheader
# =>This Inner Loop Header: Depth=1
movsd 1064(%rsp,%r14,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp96:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp97:
# %bb.97: # %_ZNSolsEd.exit64
# in Loop: Header=BB2_96 Depth=1
.Ltmp98:
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp99:
# %bb.98: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit66
# in Loop: Header=BB2_96 Depth=1
testb $7, %r14b
jne .LBB2_108
# %bb.99: # in Loop: Header=BB2_96 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_100
# %bb.102: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i160
# in Loop: Header=BB2_96 Depth=1
cmpb $0, 56(%rbx)
je .LBB2_104
# %bb.103: # in Loop: Header=BB2_96 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB2_106
.LBB2_104: # in Loop: Header=BB2_96 Depth=1
.Ltmp100:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp101:
# %bb.105: # %.noexc165
# in Loop: Header=BB2_96 Depth=1
movq (%rbx), %rax
.Ltmp102:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp103:
.LBB2_106: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i162
# in Loop: Header=BB2_96 Depth=1
.Ltmp104:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp105:
# %bb.107: # %.noexc167
# in Loop: Header=BB2_96 Depth=1
.Ltmp106:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp107:
jmp .LBB2_108
.LBB2_109:
xorl %ebx, %ebx
.LBB2_110: # %.loopexit
movq 8(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_112
# %bb.111: # %.critedge.i.i
callq _ZdlPv
.LBB2_112: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
leaq 40(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 296(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movl %ebx, %eax
addq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_64:
.cfi_def_cfa_offset 1648
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $21, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB2_110
.LBB2_2: # %.invoke
.Ltmp112:
callq _ZSt16__throw_bad_castv
.Ltmp113:
# %bb.3: # %.cont
.LBB2_100: # %.invoke209
.Ltmp109:
callq _ZSt16__throw_bad_castv
.Ltmp110:
# %bb.101: # %.cont210
.LBB2_67: # %.loopexit.split-lp.loopexit.split-lp
.Ltmp111:
jmp .LBB2_114
.LBB2_26: # %.loopexit.split-lp175.loopexit.split-lp.loopexit.split-lp
.Ltmp114:
jmp .LBB2_114
.LBB2_65: # %.loopexit170
.Ltmp108:
jmp .LBB2_114
.LBB2_66: # %.loopexit.split-lp.loopexit
.Ltmp87:
jmp .LBB2_114
.LBB2_113: # %.loopexit174
.Ltmp62:
jmp .LBB2_114
.LBB2_24: # %.loopexit.split-lp175.loopexit
.Ltmp41:
jmp .LBB2_114
.LBB2_25: # %.loopexit.split-lp175.loopexit.split-lp.loopexit
.Ltmp18:
.LBB2_114: # %.loopexit.split-lp175
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_116
# %bb.115: # %.critedge.i.i69
callq _ZdlPv
.LBB2_116: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit71
leaq 40(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 296(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp17-.Ltmp0 # Call between .Ltmp0 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp28-.Ltmp19 # Call between .Ltmp19 and .Ltmp28
.uleb128 .Ltmp114-.Lfunc_begin0 # jumps to .Ltmp114
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp40-.Ltmp29 # Call between .Ltmp29 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp49-.Ltmp42 # Call between .Ltmp42 and .Ltmp49
.uleb128 .Ltmp114-.Lfunc_begin0 # jumps to .Ltmp114
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp61-.Ltmp50 # Call between .Ltmp50 and .Ltmp61
.uleb128 .Ltmp62-.Lfunc_begin0 # jumps to .Ltmp62
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp74-.Ltmp63 # Call between .Ltmp63 and .Ltmp74
.uleb128 .Ltmp111-.Lfunc_begin0 # jumps to .Ltmp111
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp86-.Ltmp75 # Call between .Ltmp75 and .Ltmp86
.uleb128 .Ltmp87-.Lfunc_begin0 # jumps to .Ltmp87
.byte 0 # On action: cleanup
.uleb128 .Ltmp88-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp95-.Ltmp88 # Call between .Ltmp88 and .Ltmp95
.uleb128 .Ltmp111-.Lfunc_begin0 # jumps to .Ltmp111
.byte 0 # On action: cleanup
.uleb128 .Ltmp96-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp107-.Ltmp96 # Call between .Ltmp96 and .Ltmp107
.uleb128 .Ltmp108-.Lfunc_begin0 # jumps to .Ltmp108
.byte 0 # On action: cleanup
.uleb128 .Ltmp112-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp113-.Ltmp112 # Call between .Ltmp112 and .Ltmp113
.uleb128 .Ltmp114-.Lfunc_begin0 # jumps to .Ltmp114
.byte 0 # On action: cleanup
.uleb128 .Ltmp109-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp110-.Ltmp109 # Call between .Ltmp109 and .Ltmp110
.uleb128 .Ltmp111-.Lfunc_begin0 # jumps to .Ltmp111
.byte 0 # On action: cleanup
.uleb128 .Ltmp110-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Lfunc_end2-.Ltmp110 # Call between .Ltmp110 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z13dctWithCuda_1PKdPd # -- Begin function _Z13dctWithCuda_1PKdPd
.p2align 4, 0x90
.type _Z13dctWithCuda_1PKdPd,@function
_Z13dctWithCuda_1PKdPd: # @_Z13dctWithCuda_1PKdPd
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB3_10
# %bb.1:
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
testl %eax, %eax
jne .LBB3_9
# %bb.2:
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
testl %eax, %eax
jne .LBB3_9
# %bb.3:
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_11
# %bb.4:
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 7(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5dct_1PKdPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_15
# %bb.7:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB3_14
# %bb.8:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB3_13
.LBB3_9:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
jmp .LBB3_12
.LBB3_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $63, %esi
jmp .LBB3_12
.LBB3_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $19, %esi
.LBB3_12:
movl $1, %edx
.LBB3_13:
callq fwrite@PLT
.LBB3_14:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_15:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB3_14
.Lfunc_end3:
.size _Z13dctWithCuda_1PKdPd, .Lfunc_end3-_Z13dctWithCuda_1PKdPd
.cfi_endproc
# -- End function
.globl _Z13dctWithCuda_2PKdPd # -- Begin function _Z13dctWithCuda_2PKdPd
.p2align 4, 0x90
.type _Z13dctWithCuda_2PKdPd,@function
_Z13dctWithCuda_2PKdPd: # @_Z13dctWithCuda_2PKdPd
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_10
# %bb.1:
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_9
# %bb.2:
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_9
# %bb.3:
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_11
# %bb.4:
movabsq $4294967296, %rdx # imm = 0x100000000
leaq 1(%rdx), %rdi
movl $256, %r8d # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5dct_2PKdPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_15
# %bb.7:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB4_14
# %bb.8:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB4_13
.LBB4_9:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
jmp .LBB4_12
.LBB4_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $63, %esi
jmp .LBB4_12
.LBB4_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $16, %esi
.LBB4_12:
movl $1, %edx
.LBB4_13:
callq fwrite@PLT
.LBB4_14:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_15:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB4_14
.Lfunc_end4:
.size _Z13dctWithCuda_2PKdPd, .Lfunc_end4-_Z13dctWithCuda_2PKdPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5dct_1PKdPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5dct_2PKdPd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5dct_1PKdPd,@object # @_Z5dct_1PKdPd
.section .rodata,"a",@progbits
.globl _Z5dct_1PKdPd
.p2align 3, 0x0
_Z5dct_1PKdPd:
.quad _Z20__device_stub__dct_1PKdPd
.size _Z5dct_1PKdPd, 8
.type _Z5dct_2PKdPd,@object # @_Z5dct_2PKdPd
.globl _Z5dct_2PKdPd
.p2align 3, 0x0
_Z5dct_2PKdPd:
.quad _Z20__device_stub__dct_2PKdPd
.size _Z5dct_2PKdPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/zhujian/cuda-workspace/dct_10.16/gradient.txt"
.size .L.str, 52
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "f[i]: "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "before"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "dctWithCuda_1 failed!"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "after"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.6, 64
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMalloc failed!"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "cudaMemcpy-- failed"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.9, 72
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMemcpy failed!"
.size .L.str.10, 18
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipMalloc failed"
.size .L.str.11, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5dct_1PKdPd"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5dct_2PKdPd"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__dct_1PKdPd
.addrsig_sym _Z20__device_stub__dct_2PKdPd
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z5dct_1PKdPd
.addrsig_sym _Z5dct_2PKdPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2015, September 7 - October 6
// ###
// ###
// ### Thomas Moellenhoff, Robert Maier, Caner Hazirbas
// ###
// ###
// ###
// ### THIS FILE IS SUPPOSED TO REMAIN UNCHANGED
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square_value (float a)
{
return a * a;
}
__global__ void square_array (float *a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n)
{
float val = a[ind];
a[ind] = square_value(val);
}
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// initialize the array on GPU
float *d_a = NULL;
size_t nbytes = n * sizeof(float);
cudaMalloc(&d_a, nbytes); CUDA_CHECK;
// move from host to device memory
cudaMemcpy(d_a, a, nbytes, cudaMemcpyHostToDevice); CUDA_CHECK;
// initialize block and grid size
dim3 block = dim3(2, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// dispatch the kernel
square_array <<<grid, block>>> (d_a, n);
// copy result back to host memory
cudaMemcpy(a, d_a, nbytes, cudaMemcpyDeviceToHost); CUDA_CHECK;
// free the device memory
cudaFree(d_a); CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | code for sm_80
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2015, September 7 - October 6
// ###
// ###
// ### Thomas Moellenhoff, Robert Maier, Caner Hazirbas
// ###
// ###
// ###
// ### THIS FILE IS SUPPOSED TO REMAIN UNCHANGED
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square_value (float a)
{
return a * a;
}
__global__ void square_array (float *a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n)
{
float val = a[ind];
a[ind] = square_value(val);
}
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// initialize the array on GPU
float *d_a = NULL;
size_t nbytes = n * sizeof(float);
cudaMalloc(&d_a, nbytes); CUDA_CHECK;
// move from host to device memory
cudaMemcpy(d_a, a, nbytes, cudaMemcpyHostToDevice); CUDA_CHECK;
// initialize block and grid size
dim3 block = dim3(2, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// dispatch the kernel
square_array <<<grid, block>>> (d_a, n);
// copy result back to host memory
cudaMemcpy(a, d_a, nbytes, cudaMemcpyDeviceToHost); CUDA_CHECK;
// free the device memory
cudaFree(d_a); CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .file "tmpxft_001582e7_00000000-6_squareArray.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z12square_valuef
.type _Z12square_valuef, @function
_Z12square_valuef:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z12square_valuef, .-_Z12square_valuef
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.section .rodata.str1.1
.LC4:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4006:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L28
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L29
cmpq $1, %rax
jne .L24
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L25:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L31
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L31:
call __stack_chk_fail@PLT
.L29:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L23:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L25
.L24:
testq %rax, %rax
je .L25
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4006:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC6:
.string "CPU:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gaow0007/gpu-programming/master/02_basic_kernels/squareArray.cu"
.section .rodata.str1.1
.LC8:
.string "GPU:"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $40, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
.L33:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L33
movq %rbp, %rax
leaq 40(%rbp), %rdx
.L34:
movss (%rax), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L34
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
jmp .L39
.L69:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L67
call _ZSt16__throw_bad_castv@PLT
.L67:
call __stack_chk_fail@PLT
.L37:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L38:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpq $10, %r12
je .L68
.L39:
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L69
cmpb $0, 56(%r15)
je .L37
movzbl 67(%r15), %esi
jmp .L38
.L68:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L40:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L40
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movl $92, %esi
movq %rbx, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
.LEHB2:
call cudaMemcpy@PLT
leaq 36(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $95, %esi
movq %rbx, %rdi
.LEHB3:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L41:
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 15(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $106, %esi
movq %rbx, %rdi
.LEHB5:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE5:
jmp .L71
.L70:
movl $10, %esi
movq 16(%rsp), %rdi
.LEHB6:
call _Z33__device_stub__Z12square_arrayPfiPfi
jmp .L41
.L71:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 15(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movl $109, %esi
movq %rbx, %rdi
.LEHB7:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE7:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB8:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
jmp .L46
.L74:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L72
call _ZSt16__throw_bad_castv@PLT
.L72:
call __stack_chk_fail@PLT
.L44:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L45:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpq $10, %r12
je .L73
.L46:
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L74
cmpb $0, 56(%r15)
je .L44
movzbl 67(%r15), %esi
jmp .L45
.L73:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L75
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L57:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L50:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L58:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L52:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L59:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3671:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 .L56-.LFB3671
.uleb128 0
.uleb128 .LEHB2-.LFB3671
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3671
.uleb128 .LEHE3-.LEHB3
.uleb128 .L57-.LFB3671
.uleb128 0
.uleb128 .LEHB4-.LFB3671
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3671
.uleb128 .LEHE5-.LEHB5
.uleb128 .L58-.LFB3671
.uleb128 0
.uleb128 .LEHB6-.LFB3671
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3671
.uleb128 .LEHE7-.LEHB7
.uleb128 .L59-.LFB3671
.uleb128 0
.uleb128 .LEHB8-.LFB3671
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2015, September 7 - October 6
// ###
// ###
// ### Thomas Moellenhoff, Robert Maier, Caner Hazirbas
// ###
// ###
// ###
// ### THIS FILE IS SUPPOSED TO REMAIN UNCHANGED
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square_value (float a)
{
return a * a;
}
__global__ void square_array (float *a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n)
{
float val = a[ind];
a[ind] = square_value(val);
}
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// initialize the array on GPU
float *d_a = NULL;
size_t nbytes = n * sizeof(float);
cudaMalloc(&d_a, nbytes); CUDA_CHECK;
// move from host to device memory
cudaMemcpy(d_a, a, nbytes, cudaMemcpyHostToDevice); CUDA_CHECK;
// initialize block and grid size
dim3 block = dim3(2, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// dispatch the kernel
square_array <<<grid, block>>> (d_a, n);
// copy result back to host memory
cudaMemcpy(a, d_a, nbytes, cudaMemcpyDeviceToHost); CUDA_CHECK;
// free the device memory
cudaFree(d_a); CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2015, September 7 - October 6
// ###
// ###
// ### Thomas Moellenhoff, Robert Maier, Caner Hazirbas
// ###
// ###
// ###
// ### THIS FILE IS SUPPOSED TO REMAIN UNCHANGED
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square_value (float a)
{
return a * a;
}
__global__ void square_array (float *a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n)
{
float val = a[ind];
a[ind] = square_value(val);
}
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// initialize the array on GPU
float *d_a = NULL;
size_t nbytes = n * sizeof(float);
hipMalloc(&d_a, nbytes); CUDA_CHECK;
// move from host to device memory
hipMemcpy(d_a, a, nbytes, hipMemcpyHostToDevice); CUDA_CHECK;
// initialize block and grid size
dim3 block = dim3(2, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// dispatch the kernel
square_array <<<grid, block>>> (d_a, n);
// copy result back to host memory
hipMemcpy(a, d_a, nbytes, hipMemcpyDeviceToHost); CUDA_CHECK;
// free the device memory
hipFree(d_a); CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2015, September 7 - October 6
// ###
// ###
// ### Thomas Moellenhoff, Robert Maier, Caner Hazirbas
// ###
// ###
// ###
// ### THIS FILE IS SUPPOSED TO REMAIN UNCHANGED
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square_value (float a)
{
return a * a;
}
__global__ void square_array (float *a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n)
{
float val = a[ind];
a[ind] = square_value(val);
}
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// initialize the array on GPU
float *d_a = NULL;
size_t nbytes = n * sizeof(float);
hipMalloc(&d_a, nbytes); CUDA_CHECK;
// move from host to device memory
hipMemcpy(d_a, a, nbytes, hipMemcpyHostToDevice); CUDA_CHECK;
// initialize block and grid size
dim3 block = dim3(2, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// dispatch the kernel
square_array <<<grid, block>>> (d_a, n);
// copy result back to host memory
hipMemcpy(a, d_a, nbytes, hipMemcpyDeviceToHost); CUDA_CHECK;
// free the device memory
hipFree(d_a); CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2015, September 7 - October 6
// ###
// ###
// ### Thomas Moellenhoff, Robert Maier, Caner Hazirbas
// ###
// ###
// ###
// ### THIS FILE IS SUPPOSED TO REMAIN UNCHANGED
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square_value (float a)
{
return a * a;
}
__global__ void square_array (float *a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n)
{
float val = a[ind];
a[ind] = square_value(val);
}
}
int main(int argc,char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// initialize the array on GPU
float *d_a = NULL;
size_t nbytes = n * sizeof(float);
hipMalloc(&d_a, nbytes); CUDA_CHECK;
// move from host to device memory
hipMemcpy(d_a, a, nbytes, hipMemcpyHostToDevice); CUDA_CHECK;
// initialize block and grid size
dim3 block = dim3(2, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// dispatch the kernel
square_array <<<grid, block>>> (d_a, n);
// copy result back to host memory
hipMemcpy(a, d_a, nbytes, hipMemcpyDeviceToHost); CUDA_CHECK;
// free the device memory
hipFree(d_a); CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .text
.file "squareArray.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end1-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $232, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $40, %edi
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_3
# %bb.4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_62
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB2_8
.LBB2_7:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_35: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit125
# in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB2_11
.LBB2_9: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_10
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i122
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r15)
je .LBB2_35
# %bb.34: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_36
.LBB2_11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_63
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i117
cmpb $0, 56(%r14)
je .LBB2_14
# %bb.13:
movzbl 67(%r14), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit120
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_16: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_16
# %bb.17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
movq $0, 8(%rsp)
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 136(%rsp), %r14
movq %r14, 120(%rsp)
.cfi_escape 0x2e, 0x00
movl $122, %edi
callq _Znwm
movq %rax, 120(%rsp)
movq $121, 136(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movups .L.str.5+105(%rip), %xmm0
movups %xmm0, 105(%rax)
movq $121, 128(%rsp)
movb $0, 121(%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
movl $92, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.18:
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.19: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 104(%rsp), %r14
movq %r14, 88(%rsp)
.cfi_escape 0x2e, 0x00
movl $122, %edi
callq _Znwm
movq %rax, 88(%rsp)
movq $121, 104(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movups .L.str.5+105(%rip), %xmm0
movups %xmm0, 105(%rax)
movq $121, 96(%rsp)
movb $0, 121(%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
movl $95, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp4:
# %bb.21:
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_23
# %bb.22: # %.critedge.i.i81
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit83
movabsq $4294967298, %rdx # imm = 0x100000002
leaq 3(%rdx), %rdi
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_25
# %bb.24:
movq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $10, 20(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
.cfi_escape 0x2e, 0x00
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 208(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i90
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 72(%rsp), %r14
movq %r14, 56(%rsp)
.cfi_escape 0x2e, 0x00
movl $122, %edi
callq _Znwm
movq %rax, 56(%rsp)
movq $121, 72(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movups .L.str.5+105(%rip), %xmm0
movups %xmm0, 105(%rax)
movq $121, 64(%rsp)
movb $0, 121(%rax)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
movl $106, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp7:
# %bb.26:
movq 56(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_28
# %bb.27: # %.critedge.i.i97
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_28: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit99
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
leaq 40(%rsp), %r14
movq %r14, 24(%rsp)
.cfi_escape 0x2e, 0x00
movl $122, %edi
callq _Znwm
movq %rax, 24(%rsp)
movq $121, 40(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movups .L.str.5+105(%rip), %xmm0
movups %xmm0, 105(%rax)
movq $121, 32(%rsp)
movb $0, 121(%rax)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $109, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp10:
# %bb.29:
movq 24(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_31
# %bb.30: # %.critedge.i.i107
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit109
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_32
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i127
cmpb $0, 56(%r14)
je .LBB2_45
# %bb.44:
movzbl 67(%r14), %eax
jmp .LBB2_46
.LBB2_45:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit130
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB2_47
.p2align 4, 0x90
.LBB2_60: # in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_61: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit140
# in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB2_49
.LBB2_47: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_48
# %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i137
# in Loop: Header=BB2_47 Depth=1
cmpb $0, 56(%r15)
je .LBB2_60
# %bb.59: # in Loop: Header=BB2_47 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_61
.LBB2_49:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_64
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i132
cmpb $0, 56(%r14)
je .LBB2_52
# %bb.51:
movzbl 67(%r14), %eax
jmp .LBB2_53
.LBB2_52:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_53: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit135
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 272
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_48:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_62:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_63:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_32:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_64:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_56:
.Ltmp11:
movq %rax, %rbx
movq 24(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.57: # %.critedge.i.i113
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_54:
.Ltmp8:
movq %rax, %rbx
movq 56(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.55: # %.critedge.i.i110
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_41:
.Ltmp5:
movq %rax, %rbx
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.42: # %.critedge.i.i87
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_37:
.Ltmp2:
movq %rax, %rbx
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.38: # %.critedge.i.i84
.cfi_escape 0x2e, 0x00
.LBB2_39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit86
callq _ZdlPv
.LBB2_40: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit86
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gaow0007/gpu-programming/master/02_basic_kernels/squareArray.hip"
.size .L.str.5, 122
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU:"
.size .L.str.6, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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