system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*********************************************************************
* Copyright © 2011-2012,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
/*!
* CUDA : This kernel adds a constant value to the input vector into the
* output vector with length N.
*
* @param devArrayInput
* Input vector.
*
* @param constVal
* Constant value to be added to the input device vector.
*
* @param devArrayOutput
* Sum vector.
*
* @param N
* Vector length.
*
* @author
* Marwan Abdellah <abdellah.marwan@gmail.com>
*
* @date
* Created: August, 2012.
* @date
* Last Update: September, 2012.
*
* @note
* Minimum CUDA version 3.2.
* @note
* Minimum Device Compute Capability 1.0.
*/
template <typename T>
__global__
void Constant_Add_1D_Array_Kernel(T* devArrayInput,
T constVal,
T* devArrayOutput,
int N)
{
int xThreadIdx = threadIdx.x;
int blockWidth = blockDim.x;
int index = blockIdx.x * blockWidth + xThreadIdx;
#ifdef VEC_CHECK
if (index < N)
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#else
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#endif
} | .file "tmpxft_00137bdb_00000000-6_Constant_Add_1D_Array_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*********************************************************************
* Copyright © 2011-2012,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
/*!
* CUDA : This kernel adds a constant value to the input vector into the
* output vector with length N.
*
* @param devArrayInput
* Input vector.
*
* @param constVal
* Constant value to be added to the input device vector.
*
* @param devArrayOutput
* Sum vector.
*
* @param N
* Vector length.
*
* @author
* Marwan Abdellah <abdellah.marwan@gmail.com>
*
* @date
* Created: August, 2012.
* @date
* Last Update: September, 2012.
*
* @note
* Minimum CUDA version 3.2.
* @note
* Minimum Device Compute Capability 1.0.
*/
template <typename T>
__global__
void Constant_Add_1D_Array_Kernel(T* devArrayInput,
T constVal,
T* devArrayOutput,
int N)
{
int xThreadIdx = threadIdx.x;
int blockWidth = blockDim.x;
int index = blockIdx.x * blockWidth + xThreadIdx;
#ifdef VEC_CHECK
if (index < N)
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#else
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#endif
} | #include <hip/hip_runtime.h>
/*********************************************************************
* Copyright © 2011-2012,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
/*!
* CUDA : This kernel adds a constant value to the input vector into the
* output vector with length N.
*
* @param devArrayInput
* Input vector.
*
* @param constVal
* Constant value to be added to the input device vector.
*
* @param devArrayOutput
* Sum vector.
*
* @param N
* Vector length.
*
* @author
* Marwan Abdellah <abdellah.marwan@gmail.com>
*
* @date
* Created: August, 2012.
* @date
* Last Update: September, 2012.
*
* @note
* Minimum CUDA version 3.2.
* @note
* Minimum Device Compute Capability 1.0.
*/
template <typename T>
__global__
void Constant_Add_1D_Array_Kernel(T* devArrayInput,
T constVal,
T* devArrayOutput,
int N)
{
int xThreadIdx = threadIdx.x;
int blockWidth = blockDim.x;
int index = blockIdx.x * blockWidth + xThreadIdx;
#ifdef VEC_CHECK
if (index < N)
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#else
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*********************************************************************
* Copyright © 2011-2012,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
/*!
* CUDA : This kernel adds a constant value to the input vector into the
* output vector with length N.
*
* @param devArrayInput
* Input vector.
*
* @param constVal
* Constant value to be added to the input device vector.
*
* @param devArrayOutput
* Sum vector.
*
* @param N
* Vector length.
*
* @author
* Marwan Abdellah <abdellah.marwan@gmail.com>
*
* @date
* Created: August, 2012.
* @date
* Last Update: September, 2012.
*
* @note
* Minimum CUDA version 3.2.
* @note
* Minimum Device Compute Capability 1.0.
*/
template <typename T>
__global__
void Constant_Add_1D_Array_Kernel(T* devArrayInput,
T constVal,
T* devArrayOutput,
int N)
{
int xThreadIdx = threadIdx.x;
int blockWidth = blockDim.x;
int index = blockIdx.x * blockWidth + xThreadIdx;
#ifdef VEC_CHECK
if (index < N)
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#else
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#endif
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*********************************************************************
* Copyright © 2011-2012,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
/*!
* CUDA : This kernel adds a constant value to the input vector into the
* output vector with length N.
*
* @param devArrayInput
* Input vector.
*
* @param constVal
* Constant value to be added to the input device vector.
*
* @param devArrayOutput
* Sum vector.
*
* @param N
* Vector length.
*
* @author
* Marwan Abdellah <abdellah.marwan@gmail.com>
*
* @date
* Created: August, 2012.
* @date
* Last Update: September, 2012.
*
* @note
* Minimum CUDA version 3.2.
* @note
* Minimum Device Compute Capability 1.0.
*/
template <typename T>
__global__
void Constant_Add_1D_Array_Kernel(T* devArrayInput,
T constVal,
T* devArrayOutput,
int N)
{
int xThreadIdx = threadIdx.x;
int blockWidth = blockDim.x;
int index = blockIdx.x * blockWidth + xThreadIdx;
#ifdef VEC_CHECK
if (index < N)
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#else
devArrayOutput[index] = (T) ((T) devArrayInput[index] + (T) constVal);
#endif
} | .text
.file "Constant_Add_1D_Array_Kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00137bdb_00000000-6_Constant_Add_1D_Array_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Constant_Add_1D_Array_Kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#define KERNEL_SIZE 20
__constant__ int kernel[KERNEL_SIZE];
__global__ void conv1d(int *input, int *output, int l) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int s_input[];
int r = KERNEL_SIZE / 2;
int d = r * 2;
int n_padded = blockDim.x + d;
int offset = threadIdx.x + blockDim.x;
int g_offset = blockDim.x * blockIdx.x + offset;
s_input[threadIdx.x] = input[tid];
if (offset < n_padded) {
s_input[offset] = input[g_offset];
}
__syncthreads();
int temp = 0;
for (int j = 0; j < KERNEL_SIZE; j++) {
temp += s_input[threadIdx.x + j] * kernel[j];
}
output[tid] = temp;
}
int main() {
int l = 20480;
int i;
int r = KERNEL_SIZE / 2;
int n = l + r * 2;
int *host_input, *host_kernel, *host_output;
int *dev_input, *dev_output;
cudaMalloc((void**)&dev_input, sizeof(int) * n);
cudaMalloc((void**)&dev_output, sizeof(int) * KERNEL_SIZE);
cudaMallocHost((void**)&host_input, sizeof(int) * n);
cudaMallocHost((void**)&host_kernel, sizeof(int) * KERNEL_SIZE);
cudaMallocHost((void**)&host_output, sizeof(int) * l);
for (i = 0; i < n; i++) {
if ((i < r) || (i >= l + r)) {
host_input[i] = 0;
}
else {
host_input[i] = round(rand());
}
}
for (i = 0; i < KERNEL_SIZE; i++) {
host_kernel[i] = round(rand());
}
printf("Start convolution\n");
clock_t start_time = clock();
cudaMemcpy(dev_input, host_input, sizeof(int) * n, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(kernel, host_kernel, sizeof(int) * KERNEL_SIZE);
int block = 256;
int grid = (l + block - 1) / block;
size_t sharemem = sizeof(int) * (block + r * 2);
conv1d<<<grid, block, sharemem>>>(dev_input, dev_output, l);
cudaMemcpy(host_output, dev_output, sizeof(int) * l, cudaMemcpyDeviceToHost);
clock_t end_time = clock();
printf("Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n", l, KERNEL_SIZE, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
cudaFree(dev_input);
cudaFree(dev_output);
cudaFreeHost(host_input);
cudaFreeHost(host_kernel);
cudaFreeHost(host_output);
return 0;
} | code for sm_80
Function : _Z6conv1dPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0060*/ IADD3 R0, R8, 0x14, RZ ; /* 0x0000001408007810 */
/* 0x000fe40007ffe0ff */
/*0070*/ IADD3 R3, R2, c[0x0][0x0], RZ ; /* 0x0000000002037a10 */
/* 0x001fc80007ffe0ff */
/*0080*/ ISETP.GE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R6, c[0x0][0x0], R2 ; /* 0x0000000006007a24 */
/* 0x002fc800078e0202 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ @!P0 IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006068a24 */
/* 0x000fc800078e0203 */
/*00d0*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006068625 */
/* 0x000fcc00078e0207 */
/*00e0*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000406068981 */
/* 0x000ee2000c1e1900 */
/*00f0*/ SHF.L.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037819 */
/* 0x000fc800000006ff */
/*0100*/ @!P0 LEA R3, R8, R3, 0x2 ; /* 0x0000000308038211 */
/* 0x000fe200078e10ff */
/*0110*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x004fe80000004800 */
/*0120*/ @!P0 STS [R3], R6 ; /* 0x0000000603008388 */
/* 0x008fe80000000800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R8, [R2.X4] ; /* 0x0000000002087984 */
/* 0x000e280000004800 */
/*0150*/ LDS R9, [R2.X4+0x4] ; /* 0x0000040002097984 */
/* 0x000e680000004800 */
/*0160*/ LDS R11, [R2.X4+0x8] ; /* 0x00000800020b7984 */
/* 0x000ea80000004800 */
/*0170*/ LDS R13, [R2.X4+0xc] ; /* 0x00000c00020d7984 */
/* 0x000ee80000004800 */
/*0180*/ LDS R15, [R2.X4+0x10] ; /* 0x00001000020f7984 */
/* 0x000f280000004800 */
/*0190*/ LDS R7, [R2.X4+0x14] ; /* 0x0000140002077984 */
/* 0x000f680000004800 */
/*01a0*/ LDS R10, [R2.X4+0x18] ; /* 0x00001800020a7984 */
/* 0x000f680000004800 */
/*01b0*/ LDS R12, [R2.X4+0x1c] ; /* 0x00001c00020c7984 */
/* 0x000f680000004800 */
/*01c0*/ LDS R14, [R2.X4+0x20] ; /* 0x00002000020e7984 */
/* 0x000f680000004800 */
/*01d0*/ LDS R4, [R2.X4+0x24] ; /* 0x0000240002047984 */
/* 0x000f620000004800 */
/*01e0*/ IMAD R8, R8, c[0x3][0x48], RZ ; /* 0x00c0120008087a24 */
/* 0x001fc600078e02ff */
/*01f0*/ LDS R3, [R2.X4+0x28] ; /* 0x0000280002037984 */
/* 0x000e220000004800 */
/*0200*/ IMAD R8, R9, c[0x3][0x4c], R8 ; /* 0x00c0130009087a24 */
/* 0x002fc600078e0208 */
/*0210*/ LDS R5, [R2.X4+0x2c] ; /* 0x00002c0002057984 */
/* 0x000e620000004800 */
/*0220*/ IMAD R8, R11, c[0x3][0x50], R8 ; /* 0x00c014000b087a24 */
/* 0x004fc600078e0208 */
/*0230*/ LDS R9, [R2.X4+0x30] ; /* 0x0000300002097984 */
/* 0x000ea20000004800 */
/*0240*/ IMAD R8, R13, c[0x3][0x54], R8 ; /* 0x00c015000d087a24 */
/* 0x008fc600078e0208 */
/*0250*/ LDS R11, [R2.X4+0x34] ; /* 0x00003400020b7984 */
/* 0x000ee20000004800 */
/*0260*/ IMAD R8, R15, c[0x3][0x58], R8 ; /* 0x00c016000f087a24 */
/* 0x010fc600078e0208 */
/*0270*/ LDS R13, [R2.X4+0x38] ; /* 0x00003800020d7984 */
/* 0x000f220000004800 */
/*0280*/ IMAD R7, R7, c[0x3][0x5c], R8 ; /* 0x00c0170007077a24 */
/* 0x020fc600078e0208 */
/*0290*/ LDS R15, [R2.X4+0x3c] ; /* 0x00003c00020f7984 */
/* 0x000f620000004800 */
/*02a0*/ IMAD R7, R10, c[0x3][0x60], R7 ; /* 0x00c018000a077a24 */
/* 0x000fc600078e0207 */
/*02b0*/ LDS R17, [R2.X4+0x40] ; /* 0x0000400002117984 */
/* 0x000f620000004800 */
/*02c0*/ IMAD R7, R12, c[0x3][0x64], R7 ; /* 0x00c019000c077a24 */
/* 0x000fc600078e0207 */
/*02d0*/ LDS R19, [R2.X4+0x44] ; /* 0x0000440002137984 */
/* 0x000f620000004800 */
/*02e0*/ IMAD R7, R14, c[0x3][0x68], R7 ; /* 0x00c01a000e077a24 */
/* 0x000fc600078e0207 */
/*02f0*/ LDS R6, [R2.X4+0x48] ; /* 0x0000480002067984 */
/* 0x000f620000004800 */
/*0300*/ IMAD R4, R4, c[0x3][0x6c], R7 ; /* 0x00c01b0004047a24 */
/* 0x000fc600078e0207 */
/*0310*/ LDS R7, [R2.X4+0x4c] ; /* 0x00004c0002077984 */
/* 0x000f620000004800 */
/*0320*/ IMAD R4, R3, c[0x3][0x70], R4 ; /* 0x00c01c0003047a24 */
/* 0x001fc800078e0204 */
/*0330*/ IMAD R4, R5, c[0x3][0x74], R4 ; /* 0x00c01d0005047a24 */
/* 0x002fc800078e0204 */
/*0340*/ IMAD R4, R9, c[0x3][0x78], R4 ; /* 0x00c01e0009047a24 */
/* 0x004fc800078e0204 */
/*0350*/ IMAD R4, R11, c[0x3][0x7c], R4 ; /* 0x00c01f000b047a24 */
/* 0x008fc800078e0204 */
/*0360*/ IMAD R4, R13, c[0x3][0x80], R4 ; /* 0x00c020000d047a24 */
/* 0x010fc800078e0204 */
/*0370*/ IMAD R4, R15, c[0x3][0x84], R4 ; /* 0x00c021000f047a24 */
/* 0x020fc800078e0204 */
/*0380*/ IMAD R4, R17, c[0x3][0x88], R4 ; /* 0x00c0220011047a24 */
/* 0x000fc800078e0204 */
/*0390*/ IMAD R19, R19, c[0x3][0x8c], R4 ; /* 0x00c0230013137a24 */
/* 0x000fe200078e0204 */
/*03a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*03b0*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fe200078010ff */
/*03c0*/ IMAD R6, R6, c[0x3][0x90], R19 ; /* 0x00c0240006067a24 */
/* 0x000fc600078e0213 */
/*03d0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe200000f1403 */
/*03e0*/ IMAD R7, R7, c[0x3][0x94], R6 ; /* 0x00c0250007077a24 */
/* 0x000fca00078e0206 */
/*03f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#define KERNEL_SIZE 20
__constant__ int kernel[KERNEL_SIZE];
__global__ void conv1d(int *input, int *output, int l) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int s_input[];
int r = KERNEL_SIZE / 2;
int d = r * 2;
int n_padded = blockDim.x + d;
int offset = threadIdx.x + blockDim.x;
int g_offset = blockDim.x * blockIdx.x + offset;
s_input[threadIdx.x] = input[tid];
if (offset < n_padded) {
s_input[offset] = input[g_offset];
}
__syncthreads();
int temp = 0;
for (int j = 0; j < KERNEL_SIZE; j++) {
temp += s_input[threadIdx.x + j] * kernel[j];
}
output[tid] = temp;
}
int main() {
int l = 20480;
int i;
int r = KERNEL_SIZE / 2;
int n = l + r * 2;
int *host_input, *host_kernel, *host_output;
int *dev_input, *dev_output;
cudaMalloc((void**)&dev_input, sizeof(int) * n);
cudaMalloc((void**)&dev_output, sizeof(int) * KERNEL_SIZE);
cudaMallocHost((void**)&host_input, sizeof(int) * n);
cudaMallocHost((void**)&host_kernel, sizeof(int) * KERNEL_SIZE);
cudaMallocHost((void**)&host_output, sizeof(int) * l);
for (i = 0; i < n; i++) {
if ((i < r) || (i >= l + r)) {
host_input[i] = 0;
}
else {
host_input[i] = round(rand());
}
}
for (i = 0; i < KERNEL_SIZE; i++) {
host_kernel[i] = round(rand());
}
printf("Start convolution\n");
clock_t start_time = clock();
cudaMemcpy(dev_input, host_input, sizeof(int) * n, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(kernel, host_kernel, sizeof(int) * KERNEL_SIZE);
int block = 256;
int grid = (l + block - 1) / block;
size_t sharemem = sizeof(int) * (block + r * 2);
conv1d<<<grid, block, sharemem>>>(dev_input, dev_output, l);
cudaMemcpy(host_output, dev_output, sizeof(int) * l, cudaMemcpyDeviceToHost);
clock_t end_time = clock();
printf("Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n", l, KERNEL_SIZE, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
cudaFree(dev_input);
cudaFree(dev_output);
cudaFreeHost(host_input);
cudaFreeHost(host_kernel);
cudaFreeHost(host_output);
return 0;
} | .file "tmpxft_000d0caf_00000000-6_share.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6conv1dPiS_iPiS_i
.type _Z28__device_stub__Z6conv1dPiS_iPiS_i, @function
_Z28__device_stub__Z6conv1dPiS_iPiS_i:
.LFB2296:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6conv1dPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z28__device_stub__Z6conv1dPiS_iPiS_i, .-_Z28__device_stub__Z6conv1dPiS_iPiS_i
.globl _Z6conv1dPiS_i
.type _Z6conv1dPiS_i, @function
_Z6conv1dPiS_i:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6conv1dPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z6conv1dPiS_i, .-_Z6conv1dPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Start convolution\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $82000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $82000, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $81920, %esi
call cudaMallocHost@PLT
movl $0, %ebx
movl $-10, %ebp
.L14:
cmpl $20479, %ebp
ja .L21
call rand@PLT
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rbx)
.L13:
addl $1, %ebp
addq $4, %rbx
cmpq $82000, %rbx
jne .L14
movl $0, %ebx
.L15:
call rand@PLT
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $80, %rbx
jne .L15
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $1, %ecx
movl $82000, %edx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movl $80, %edx
movq 16(%rsp), %rsi
leaq _ZL6kernel(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $80, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $1104, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movl $81920, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
movl $20, %ecx
movl $20480, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rax
movl $0, (%rax,%rbx)
jmp .L13
.L22:
movl $20480, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6conv1dPiS_iPiS_i
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6conv1dPiS_i"
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.LC14:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6conv1dPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $80, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6kernel
.comm _ZL6kernel,80,32
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#define KERNEL_SIZE 20
__constant__ int kernel[KERNEL_SIZE];
__global__ void conv1d(int *input, int *output, int l) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int s_input[];
int r = KERNEL_SIZE / 2;
int d = r * 2;
int n_padded = blockDim.x + d;
int offset = threadIdx.x + blockDim.x;
int g_offset = blockDim.x * blockIdx.x + offset;
s_input[threadIdx.x] = input[tid];
if (offset < n_padded) {
s_input[offset] = input[g_offset];
}
__syncthreads();
int temp = 0;
for (int j = 0; j < KERNEL_SIZE; j++) {
temp += s_input[threadIdx.x + j] * kernel[j];
}
output[tid] = temp;
}
int main() {
int l = 20480;
int i;
int r = KERNEL_SIZE / 2;
int n = l + r * 2;
int *host_input, *host_kernel, *host_output;
int *dev_input, *dev_output;
cudaMalloc((void**)&dev_input, sizeof(int) * n);
cudaMalloc((void**)&dev_output, sizeof(int) * KERNEL_SIZE);
cudaMallocHost((void**)&host_input, sizeof(int) * n);
cudaMallocHost((void**)&host_kernel, sizeof(int) * KERNEL_SIZE);
cudaMallocHost((void**)&host_output, sizeof(int) * l);
for (i = 0; i < n; i++) {
if ((i < r) || (i >= l + r)) {
host_input[i] = 0;
}
else {
host_input[i] = round(rand());
}
}
for (i = 0; i < KERNEL_SIZE; i++) {
host_kernel[i] = round(rand());
}
printf("Start convolution\n");
clock_t start_time = clock();
cudaMemcpy(dev_input, host_input, sizeof(int) * n, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(kernel, host_kernel, sizeof(int) * KERNEL_SIZE);
int block = 256;
int grid = (l + block - 1) / block;
size_t sharemem = sizeof(int) * (block + r * 2);
conv1d<<<grid, block, sharemem>>>(dev_input, dev_output, l);
cudaMemcpy(host_output, dev_output, sizeof(int) * l, cudaMemcpyDeviceToHost);
clock_t end_time = clock();
printf("Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n", l, KERNEL_SIZE, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
cudaFree(dev_input);
cudaFree(dev_output);
cudaFreeHost(host_input);
cudaFreeHost(host_kernel);
cudaFreeHost(host_output);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define KERNEL_SIZE 20
__constant__ int kernel[KERNEL_SIZE];
__global__ void conv1d(int *input, int *output, int l) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int s_input[];
int r = KERNEL_SIZE / 2;
int d = r * 2;
int n_padded = blockDim.x + d;
int offset = threadIdx.x + blockDim.x;
int g_offset = blockDim.x * blockIdx.x + offset;
s_input[threadIdx.x] = input[tid];
if (offset < n_padded) {
s_input[offset] = input[g_offset];
}
__syncthreads();
int temp = 0;
for (int j = 0; j < KERNEL_SIZE; j++) {
temp += s_input[threadIdx.x + j] * kernel[j];
}
output[tid] = temp;
}
int main() {
int l = 20480;
int i;
int r = KERNEL_SIZE / 2;
int n = l + r * 2;
int *host_input, *host_kernel, *host_output;
int *dev_input, *dev_output;
hipMalloc((void**)&dev_input, sizeof(int) * n);
hipMalloc((void**)&dev_output, sizeof(int) * KERNEL_SIZE);
hipHostMalloc((void**)&host_input, sizeof(int) * n, hipHostMallocDefault);
hipHostMalloc((void**)&host_kernel, sizeof(int) * KERNEL_SIZE, hipHostMallocDefault);
hipHostMalloc((void**)&host_output, sizeof(int) * l, hipHostMallocDefault);
for (i = 0; i < n; i++) {
if ((i < r) || (i >= l + r)) {
host_input[i] = 0;
}
else {
host_input[i] = round(rand());
}
}
for (i = 0; i < KERNEL_SIZE; i++) {
host_kernel[i] = round(rand());
}
printf("Start convolution\n");
clock_t start_time = clock();
hipMemcpy(dev_input, host_input, sizeof(int) * n, hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(kernel), host_kernel, sizeof(int) * KERNEL_SIZE);
int block = 256;
int grid = (l + block - 1) / block;
size_t sharemem = sizeof(int) * (block + r * 2);
conv1d<<<grid, block, sharemem>>>(dev_input, dev_output, l);
hipMemcpy(host_output, dev_output, sizeof(int) * l, hipMemcpyDeviceToHost);
clock_t end_time = clock();
printf("Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n", l, KERNEL_SIZE, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
hipFree(dev_input);
hipFree(dev_output);
hipHostFree(host_input);
hipHostFree(host_kernel);
hipHostFree(host_output);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define KERNEL_SIZE 20
__constant__ int kernel[KERNEL_SIZE];
__global__ void conv1d(int *input, int *output, int l) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int s_input[];
int r = KERNEL_SIZE / 2;
int d = r * 2;
int n_padded = blockDim.x + d;
int offset = threadIdx.x + blockDim.x;
int g_offset = blockDim.x * blockIdx.x + offset;
s_input[threadIdx.x] = input[tid];
if (offset < n_padded) {
s_input[offset] = input[g_offset];
}
__syncthreads();
int temp = 0;
for (int j = 0; j < KERNEL_SIZE; j++) {
temp += s_input[threadIdx.x + j] * kernel[j];
}
output[tid] = temp;
}
int main() {
int l = 20480;
int i;
int r = KERNEL_SIZE / 2;
int n = l + r * 2;
int *host_input, *host_kernel, *host_output;
int *dev_input, *dev_output;
hipMalloc((void**)&dev_input, sizeof(int) * n);
hipMalloc((void**)&dev_output, sizeof(int) * KERNEL_SIZE);
hipHostMalloc((void**)&host_input, sizeof(int) * n, hipHostMallocDefault);
hipHostMalloc((void**)&host_kernel, sizeof(int) * KERNEL_SIZE, hipHostMallocDefault);
hipHostMalloc((void**)&host_output, sizeof(int) * l, hipHostMallocDefault);
for (i = 0; i < n; i++) {
if ((i < r) || (i >= l + r)) {
host_input[i] = 0;
}
else {
host_input[i] = round(rand());
}
}
for (i = 0; i < KERNEL_SIZE; i++) {
host_kernel[i] = round(rand());
}
printf("Start convolution\n");
clock_t start_time = clock();
hipMemcpy(dev_input, host_input, sizeof(int) * n, hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(kernel), host_kernel, sizeof(int) * KERNEL_SIZE);
int block = 256;
int grid = (l + block - 1) / block;
size_t sharemem = sizeof(int) * (block + r * 2);
conv1d<<<grid, block, sharemem>>>(dev_input, dev_output, l);
hipMemcpy(host_output, dev_output, sizeof(int) * l, hipMemcpyDeviceToHost);
clock_t end_time = clock();
printf("Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n", l, KERNEL_SIZE, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
hipFree(dev_input);
hipFree(dev_output);
hipHostFree(host_input);
hipHostFree(host_kernel);
hipHostFree(host_output);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6conv1dPiS_i
.globl _Z6conv1dPiS_i
.p2align 8
.type _Z6conv1dPiS_i,@function
_Z6conv1dPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_add_u32 v5, v0, 2, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3
v_cmpx_gt_u32_e32 20, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s15, v0
v_lshl_add_u32 v0, v0, 2, 0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_3:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, kernel@rel32@lo+4
s_addc_u32 s5, s5, kernel@rel32@hi+12
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
ds_load_b32 v6, v5
s_load_b32 s4, s[4:5], 0x0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x50
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s4, v6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v3 :: v_dual_add_nc_u32 v5, 4, v5
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6conv1dPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6conv1dPiS_i, .Lfunc_end0-_Z6conv1dPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected kernel
.type kernel,@object
.section .bss,"aw",@nobits
.globl kernel
.p2align 4, 0x0
kernel:
.zero 80
.size kernel, 80
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym kernel
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6conv1dPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6conv1dPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define KERNEL_SIZE 20
__constant__ int kernel[KERNEL_SIZE];
__global__ void conv1d(int *input, int *output, int l) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int s_input[];
int r = KERNEL_SIZE / 2;
int d = r * 2;
int n_padded = blockDim.x + d;
int offset = threadIdx.x + blockDim.x;
int g_offset = blockDim.x * blockIdx.x + offset;
s_input[threadIdx.x] = input[tid];
if (offset < n_padded) {
s_input[offset] = input[g_offset];
}
__syncthreads();
int temp = 0;
for (int j = 0; j < KERNEL_SIZE; j++) {
temp += s_input[threadIdx.x + j] * kernel[j];
}
output[tid] = temp;
}
int main() {
int l = 20480;
int i;
int r = KERNEL_SIZE / 2;
int n = l + r * 2;
int *host_input, *host_kernel, *host_output;
int *dev_input, *dev_output;
hipMalloc((void**)&dev_input, sizeof(int) * n);
hipMalloc((void**)&dev_output, sizeof(int) * KERNEL_SIZE);
hipHostMalloc((void**)&host_input, sizeof(int) * n, hipHostMallocDefault);
hipHostMalloc((void**)&host_kernel, sizeof(int) * KERNEL_SIZE, hipHostMallocDefault);
hipHostMalloc((void**)&host_output, sizeof(int) * l, hipHostMallocDefault);
for (i = 0; i < n; i++) {
if ((i < r) || (i >= l + r)) {
host_input[i] = 0;
}
else {
host_input[i] = round(rand());
}
}
for (i = 0; i < KERNEL_SIZE; i++) {
host_kernel[i] = round(rand());
}
printf("Start convolution\n");
clock_t start_time = clock();
hipMemcpy(dev_input, host_input, sizeof(int) * n, hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(kernel), host_kernel, sizeof(int) * KERNEL_SIZE);
int block = 256;
int grid = (l + block - 1) / block;
size_t sharemem = sizeof(int) * (block + r * 2);
conv1d<<<grid, block, sharemem>>>(dev_input, dev_output, l);
hipMemcpy(host_output, dev_output, sizeof(int) * l, hipMemcpyDeviceToHost);
clock_t end_time = clock();
printf("Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n", l, KERNEL_SIZE, static_cast<double>(end_time - start_time)/CLOCKS_PER_SEC*1000);
hipFree(dev_input);
hipFree(dev_output);
hipHostFree(host_input);
hipHostFree(host_kernel);
hipHostFree(host_output);
return 0;
} | .text
.file "share.hip"
.globl _Z21__device_stub__conv1dPiS_i # -- Begin function _Z21__device_stub__conv1dPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__conv1dPiS_i,@function
_Z21__device_stub__conv1dPiS_i: # @_Z21__device_stub__conv1dPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6conv1dPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__conv1dPiS_i, .Lfunc_end0-_Z21__device_stub__conv1dPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $82000, %esi # imm = 0x14050
callq hipMalloc
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
movl $82000, %esi # imm = 0x14050
xorl %edx, %edx
callq hipHostMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
xorl %edx, %edx
callq hipHostMalloc
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $20500, %rbx # imm = 0x5014
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
leal -20490(%rbx), %ecx
movl $0, %eax
cmpl $-20480, %ecx # imm = 0xB000
jb .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
callq rand
jmp .LBB1_3
.LBB1_4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
callq rand
movq 16(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $20, %rbx
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
callq clock
movq %rax, %rbx
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movl $82000, %edx # imm = 0x14050
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $kernel, %edi
movl $80, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967376, %rdi # imm = 0x100000050
leaq 176(%rdi), %rdx
movl $1104, %r8d # imm = 0x450
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $20480, 36(%rsp) # imm = 0x5000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6conv1dPiS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 40(%rsp), %rdi
movq (%rsp), %rsi
movl $81920, %edx # imm = 0x14000
movl $2, %ecx
callq hipMemcpy
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movl $20480, %esi # imm = 0x5000
movl $20, %edx
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6conv1dPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $80, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.local kernel
.comm kernel,80,16
.type _Z6conv1dPiS_i,@object # @_Z6conv1dPiS_i
.section .rodata,"a",@progbits
.globl _Z6conv1dPiS_i
.p2align 3, 0x0
_Z6conv1dPiS_i:
.quad _Z21__device_stub__conv1dPiS_i
.size _Z6conv1dPiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n"
.size .L.str.1, 71
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6conv1dPiS_i"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernel"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Start convolution"
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__conv1dPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym _Z6conv1dPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6conv1dPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0060*/ IADD3 R0, R8, 0x14, RZ ; /* 0x0000001408007810 */
/* 0x000fe40007ffe0ff */
/*0070*/ IADD3 R3, R2, c[0x0][0x0], RZ ; /* 0x0000000002037a10 */
/* 0x001fc80007ffe0ff */
/*0080*/ ISETP.GE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R6, c[0x0][0x0], R2 ; /* 0x0000000006007a24 */
/* 0x002fc800078e0202 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ @!P0 IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006068a24 */
/* 0x000fc800078e0203 */
/*00d0*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006068625 */
/* 0x000fcc00078e0207 */
/*00e0*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000406068981 */
/* 0x000ee2000c1e1900 */
/*00f0*/ SHF.L.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037819 */
/* 0x000fc800000006ff */
/*0100*/ @!P0 LEA R3, R8, R3, 0x2 ; /* 0x0000000308038211 */
/* 0x000fe200078e10ff */
/*0110*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x004fe80000004800 */
/*0120*/ @!P0 STS [R3], R6 ; /* 0x0000000603008388 */
/* 0x008fe80000000800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R8, [R2.X4] ; /* 0x0000000002087984 */
/* 0x000e280000004800 */
/*0150*/ LDS R9, [R2.X4+0x4] ; /* 0x0000040002097984 */
/* 0x000e680000004800 */
/*0160*/ LDS R11, [R2.X4+0x8] ; /* 0x00000800020b7984 */
/* 0x000ea80000004800 */
/*0170*/ LDS R13, [R2.X4+0xc] ; /* 0x00000c00020d7984 */
/* 0x000ee80000004800 */
/*0180*/ LDS R15, [R2.X4+0x10] ; /* 0x00001000020f7984 */
/* 0x000f280000004800 */
/*0190*/ LDS R7, [R2.X4+0x14] ; /* 0x0000140002077984 */
/* 0x000f680000004800 */
/*01a0*/ LDS R10, [R2.X4+0x18] ; /* 0x00001800020a7984 */
/* 0x000f680000004800 */
/*01b0*/ LDS R12, [R2.X4+0x1c] ; /* 0x00001c00020c7984 */
/* 0x000f680000004800 */
/*01c0*/ LDS R14, [R2.X4+0x20] ; /* 0x00002000020e7984 */
/* 0x000f680000004800 */
/*01d0*/ LDS R4, [R2.X4+0x24] ; /* 0x0000240002047984 */
/* 0x000f620000004800 */
/*01e0*/ IMAD R8, R8, c[0x3][0x48], RZ ; /* 0x00c0120008087a24 */
/* 0x001fc600078e02ff */
/*01f0*/ LDS R3, [R2.X4+0x28] ; /* 0x0000280002037984 */
/* 0x000e220000004800 */
/*0200*/ IMAD R8, R9, c[0x3][0x4c], R8 ; /* 0x00c0130009087a24 */
/* 0x002fc600078e0208 */
/*0210*/ LDS R5, [R2.X4+0x2c] ; /* 0x00002c0002057984 */
/* 0x000e620000004800 */
/*0220*/ IMAD R8, R11, c[0x3][0x50], R8 ; /* 0x00c014000b087a24 */
/* 0x004fc600078e0208 */
/*0230*/ LDS R9, [R2.X4+0x30] ; /* 0x0000300002097984 */
/* 0x000ea20000004800 */
/*0240*/ IMAD R8, R13, c[0x3][0x54], R8 ; /* 0x00c015000d087a24 */
/* 0x008fc600078e0208 */
/*0250*/ LDS R11, [R2.X4+0x34] ; /* 0x00003400020b7984 */
/* 0x000ee20000004800 */
/*0260*/ IMAD R8, R15, c[0x3][0x58], R8 ; /* 0x00c016000f087a24 */
/* 0x010fc600078e0208 */
/*0270*/ LDS R13, [R2.X4+0x38] ; /* 0x00003800020d7984 */
/* 0x000f220000004800 */
/*0280*/ IMAD R7, R7, c[0x3][0x5c], R8 ; /* 0x00c0170007077a24 */
/* 0x020fc600078e0208 */
/*0290*/ LDS R15, [R2.X4+0x3c] ; /* 0x00003c00020f7984 */
/* 0x000f620000004800 */
/*02a0*/ IMAD R7, R10, c[0x3][0x60], R7 ; /* 0x00c018000a077a24 */
/* 0x000fc600078e0207 */
/*02b0*/ LDS R17, [R2.X4+0x40] ; /* 0x0000400002117984 */
/* 0x000f620000004800 */
/*02c0*/ IMAD R7, R12, c[0x3][0x64], R7 ; /* 0x00c019000c077a24 */
/* 0x000fc600078e0207 */
/*02d0*/ LDS R19, [R2.X4+0x44] ; /* 0x0000440002137984 */
/* 0x000f620000004800 */
/*02e0*/ IMAD R7, R14, c[0x3][0x68], R7 ; /* 0x00c01a000e077a24 */
/* 0x000fc600078e0207 */
/*02f0*/ LDS R6, [R2.X4+0x48] ; /* 0x0000480002067984 */
/* 0x000f620000004800 */
/*0300*/ IMAD R4, R4, c[0x3][0x6c], R7 ; /* 0x00c01b0004047a24 */
/* 0x000fc600078e0207 */
/*0310*/ LDS R7, [R2.X4+0x4c] ; /* 0x00004c0002077984 */
/* 0x000f620000004800 */
/*0320*/ IMAD R4, R3, c[0x3][0x70], R4 ; /* 0x00c01c0003047a24 */
/* 0x001fc800078e0204 */
/*0330*/ IMAD R4, R5, c[0x3][0x74], R4 ; /* 0x00c01d0005047a24 */
/* 0x002fc800078e0204 */
/*0340*/ IMAD R4, R9, c[0x3][0x78], R4 ; /* 0x00c01e0009047a24 */
/* 0x004fc800078e0204 */
/*0350*/ IMAD R4, R11, c[0x3][0x7c], R4 ; /* 0x00c01f000b047a24 */
/* 0x008fc800078e0204 */
/*0360*/ IMAD R4, R13, c[0x3][0x80], R4 ; /* 0x00c020000d047a24 */
/* 0x010fc800078e0204 */
/*0370*/ IMAD R4, R15, c[0x3][0x84], R4 ; /* 0x00c021000f047a24 */
/* 0x020fc800078e0204 */
/*0380*/ IMAD R4, R17, c[0x3][0x88], R4 ; /* 0x00c0220011047a24 */
/* 0x000fc800078e0204 */
/*0390*/ IMAD R19, R19, c[0x3][0x8c], R4 ; /* 0x00c0230013137a24 */
/* 0x000fe200078e0204 */
/*03a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*03b0*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fe200078010ff */
/*03c0*/ IMAD R6, R6, c[0x3][0x90], R19 ; /* 0x00c0240006067a24 */
/* 0x000fc600078e0213 */
/*03d0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe200000f1403 */
/*03e0*/ IMAD R7, R7, c[0x3][0x94], R6 ; /* 0x00c0250007077a24 */
/* 0x000fca00078e0206 */
/*03f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6conv1dPiS_i
.globl _Z6conv1dPiS_i
.p2align 8
.type _Z6conv1dPiS_i,@function
_Z6conv1dPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_add_u32 v5, v0, 2, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3
v_cmpx_gt_u32_e32 20, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s15, v0
v_lshl_add_u32 v0, v0, 2, 0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_3:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, kernel@rel32@lo+4
s_addc_u32 s5, s5, kernel@rel32@hi+12
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
ds_load_b32 v6, v5
s_load_b32 s4, s[4:5], 0x0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x50
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s4, v6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v3 :: v_dual_add_nc_u32 v5, 4, v5
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6conv1dPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6conv1dPiS_i, .Lfunc_end0-_Z6conv1dPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected kernel
.type kernel,@object
.section .bss,"aw",@nobits
.globl kernel
.p2align 4, 0x0
kernel:
.zero 80
.size kernel, 80
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym kernel
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6conv1dPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6conv1dPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d0caf_00000000-6_share.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6conv1dPiS_iPiS_i
.type _Z28__device_stub__Z6conv1dPiS_iPiS_i, @function
_Z28__device_stub__Z6conv1dPiS_iPiS_i:
.LFB2296:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6conv1dPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z28__device_stub__Z6conv1dPiS_iPiS_i, .-_Z28__device_stub__Z6conv1dPiS_iPiS_i
.globl _Z6conv1dPiS_i
.type _Z6conv1dPiS_i, @function
_Z6conv1dPiS_i:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6conv1dPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z6conv1dPiS_i, .-_Z6conv1dPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Start convolution\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $82000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $82000, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $81920, %esi
call cudaMallocHost@PLT
movl $0, %ebx
movl $-10, %ebp
.L14:
cmpl $20479, %ebp
ja .L21
call rand@PLT
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rbx)
.L13:
addl $1, %ebp
addq $4, %rbx
cmpq $82000, %rbx
jne .L14
movl $0, %ebx
.L15:
call rand@PLT
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $80, %rbx
jne .L15
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $1, %ecx
movl $82000, %edx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movl $80, %edx
movq 16(%rsp), %rsi
leaq _ZL6kernel(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $80, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $1104, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movl $81920, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
movl $20, %ecx
movl $20480, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rax
movl $0, (%rax,%rbx)
jmp .L13
.L22:
movl $20480, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6conv1dPiS_iPiS_i
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6conv1dPiS_i"
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.LC14:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6conv1dPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $80, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6kernel
.comm _ZL6kernel,80,32
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "share.hip"
.globl _Z21__device_stub__conv1dPiS_i # -- Begin function _Z21__device_stub__conv1dPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__conv1dPiS_i,@function
_Z21__device_stub__conv1dPiS_i: # @_Z21__device_stub__conv1dPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6conv1dPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__conv1dPiS_i, .Lfunc_end0-_Z21__device_stub__conv1dPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $82000, %esi # imm = 0x14050
callq hipMalloc
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
movl $82000, %esi # imm = 0x14050
xorl %edx, %edx
callq hipHostMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movl $81920, %esi # imm = 0x14000
xorl %edx, %edx
callq hipHostMalloc
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $20500, %rbx # imm = 0x5014
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
leal -20490(%rbx), %ecx
movl $0, %eax
cmpl $-20480, %ecx # imm = 0xB000
jb .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
callq rand
jmp .LBB1_3
.LBB1_4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
callq rand
movq 16(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $20, %rbx
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
callq clock
movq %rax, %rbx
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movl $82000, %edx # imm = 0x14050
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $kernel, %edi
movl $80, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967376, %rdi # imm = 0x100000050
leaq 176(%rdi), %rdx
movl $1104, %r8d # imm = 0x450
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $20480, 36(%rsp) # imm = 0x5000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6conv1dPiS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 40(%rsp), %rdi
movq (%rsp), %rsi
movl $81920, %edx # imm = 0x14000
movl $2, %ecx
callq hipMemcpy
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movl $20480, %esi # imm = 0x5000
movl $20, %edx
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6conv1dPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $80, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.local kernel
.comm kernel,80,16
.type _Z6conv1dPiS_i,@object # @_Z6conv1dPiS_i
.section .rodata,"a",@progbits
.globl _Z6conv1dPiS_i
.p2align 3, 0x0
_Z6conv1dPiS_i:
.quad _Z21__device_stub__conv1dPiS_i
.size _Z6conv1dPiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Time consuming of 1D convolution of %d array with %d kernel is %f ms.\n"
.size .L.str.1, 71
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6conv1dPiS_i"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernel"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Start convolution"
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__conv1dPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym _Z6conv1dPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "complex.h"
extern "C" {
__device__
double2 fetch_initial_point(unsigned long i) {
return (double2){0.0, 0.0};
}
__device__
double2 iterate_point(double2 val, unsigned long i, double2 ipnt, unsigned long func_n) {
if (func_n < 42949673) {
func_n = 0;
} else if (func_n < 3693671875) {
func_n = 1;
} else if (func_n < 3994319586) {
func_n = 2;
} else {
func_n = 3;
}
switch (func_n) {
case 0:
return (double2){0.0, 0.16 * val.y};
case 1:
return (double2){0.85 * val.x + 0.04 * val.y, -0.04 * val.x + 0.85 * val.y + 1.6};
case 2:
return (double2){0.2 * val.x - 0.26 * val.y, 0.23 * val.x + 0.22 * val.y + 1.6};
case 3:
return (double2){-0.15 * val.x + 0.28 * val.y, 0.26 * val.x + 0.24 * val.y + 0.44};
}
return val;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "complex.h"
extern "C" {
__device__
double2 fetch_initial_point(unsigned long i) {
return (double2){0.0, 0.0};
}
__device__
double2 iterate_point(double2 val, unsigned long i, double2 ipnt, unsigned long func_n) {
if (func_n < 42949673) {
func_n = 0;
} else if (func_n < 3693671875) {
func_n = 1;
} else if (func_n < 3994319586) {
func_n = 2;
} else {
func_n = 3;
}
switch (func_n) {
case 0:
return (double2){0.0, 0.16 * val.y};
case 1:
return (double2){0.85 * val.x + 0.04 * val.y, -0.04 * val.x + 0.85 * val.y + 1.6};
case 2:
return (double2){0.2 * val.x - 0.26 * val.y, 0.23 * val.x + 0.22 * val.y + 1.6};
case 3:
return (double2){-0.15 * val.x + 0.28 * val.y, 0.26 * val.x + 0.24 * val.y + 0.44};
}
return val;
}
} | .file "tmpxft_000cdb2d_00000000-6_fern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3974:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3974:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl fetch_initial_point
.type fetch_initial_point, @function
fetch_initial_point:
.LFB3970:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3970:
.size fetch_initial_point, .-fetch_initial_point
.globl iterate_point
.type iterate_point, @function
iterate_point:
.LFB3971:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3971:
.size iterate_point, .-iterate_point
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3997:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3997:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "complex.h"
extern "C" {
__device__
double2 fetch_initial_point(unsigned long i) {
return (double2){0.0, 0.0};
}
__device__
double2 iterate_point(double2 val, unsigned long i, double2 ipnt, unsigned long func_n) {
if (func_n < 42949673) {
func_n = 0;
} else if (func_n < 3693671875) {
func_n = 1;
} else if (func_n < 3994319586) {
func_n = 2;
} else {
func_n = 3;
}
switch (func_n) {
case 0:
return (double2){0.0, 0.16 * val.y};
case 1:
return (double2){0.85 * val.x + 0.04 * val.y, -0.04 * val.x + 0.85 * val.y + 1.6};
case 2:
return (double2){0.2 * val.x - 0.26 * val.y, 0.23 * val.x + 0.22 * val.y + 1.6};
case 3:
return (double2){-0.15 * val.x + 0.28 * val.y, 0.26 * val.x + 0.24 * val.y + 0.44};
}
return val;
}
} | #include <hip/hip_runtime.h>
#include "complex.h"
extern "C" {
__device__
double2 fetch_initial_point(unsigned long i) {
return (double2){0.0, 0.0};
}
__device__
double2 iterate_point(double2 val, unsigned long i, double2 ipnt, unsigned long func_n) {
if (func_n < 42949673) {
func_n = 0;
} else if (func_n < 3693671875) {
func_n = 1;
} else if (func_n < 3994319586) {
func_n = 2;
} else {
func_n = 3;
}
switch (func_n) {
case 0:
return (double2){0.0, 0.16 * val.y};
case 1:
return (double2){0.85 * val.x + 0.04 * val.y, -0.04 * val.x + 0.85 * val.y + 1.6};
case 2:
return (double2){0.2 * val.x - 0.26 * val.y, 0.23 * val.x + 0.22 * val.y + 1.6};
case 3:
return (double2){-0.15 * val.x + 0.28 * val.y, 0.26 * val.x + 0.24 * val.y + 0.44};
}
return val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "complex.h"
extern "C" {
__device__
double2 fetch_initial_point(unsigned long i) {
return (double2){0.0, 0.0};
}
__device__
double2 iterate_point(double2 val, unsigned long i, double2 ipnt, unsigned long func_n) {
if (func_n < 42949673) {
func_n = 0;
} else if (func_n < 3693671875) {
func_n = 1;
} else if (func_n < 3994319586) {
func_n = 2;
} else {
func_n = 3;
}
switch (func_n) {
case 0:
return (double2){0.0, 0.16 * val.y};
case 1:
return (double2){0.85 * val.x + 0.04 * val.y, -0.04 * val.x + 0.85 * val.y + 1.6};
case 2:
return (double2){0.2 * val.x - 0.26 * val.y, 0.23 * val.x + 0.22 * val.y + 1.6};
case 3:
return (double2){-0.15 * val.x + 0.28 * val.y, 0.26 * val.x + 0.24 * val.y + 0.44};
}
return val;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "complex.h"
extern "C" {
__device__
double2 fetch_initial_point(unsigned long i) {
return (double2){0.0, 0.0};
}
__device__
double2 iterate_point(double2 val, unsigned long i, double2 ipnt, unsigned long func_n) {
if (func_n < 42949673) {
func_n = 0;
} else if (func_n < 3693671875) {
func_n = 1;
} else if (func_n < 3994319586) {
func_n = 2;
} else {
func_n = 3;
}
switch (func_n) {
case 0:
return (double2){0.0, 0.16 * val.y};
case 1:
return (double2){0.85 * val.x + 0.04 * val.y, -0.04 * val.x + 0.85 * val.y + 1.6};
case 2:
return (double2){0.2 * val.x - 0.26 * val.y, 0.23 * val.x + 0.22 * val.y + 1.6};
case 3:
return (double2){-0.15 * val.x + 0.28 * val.y, 0.26 * val.x + 0.24 * val.y + 0.44};
}
return val;
}
} | .text
.file "fern.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cdb2d_00000000-6_fern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3974:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3974:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl fetch_initial_point
.type fetch_initial_point, @function
fetch_initial_point:
.LFB3970:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3970:
.size fetch_initial_point, .-fetch_initial_point
.globl iterate_point
.type iterate_point, @function
iterate_point:
.LFB3971:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3971:
.size iterate_point, .-iterate_point
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3997:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3997:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fern.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cassert>
#include <cuda_runtime.h>
using namespace std;
__global__ void matrix_multiplication(const int *d_indices,
const int *d_matrix,
const int *d_vector,
int *d_output,
int n,
int t) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
return;
int result = 0;
for (int i = 0 ; i < t; i++) {
const int multiplierIndex = index + d_indices[i];
if (multiplierIndex < 0 || multiplierIndex > n)
continue;
const int elemIndex = n * i + index;
result += d_matrix[elemIndex] * d_vector[multiplierIndex];
}
d_output[index] = result;
}
#define cudaCheckErrors(EXPR) assert(EXPR == cudaSuccess)
/// Function for fast integer fetching
int fetch_int() {
int result = 0;
char c = 0;
// skip all other chars
while (c < '0' or c > '9') {
c = getchar_unlocked();
}
while ('0' <= c and c <= '9') {
result *= 10;
result += c - '0';
c = getchar_unlocked();
}
return result;
}
int main() {
int n = fetch_int();
int t = fetch_int();
int *h_fullInput;
// We need memory for n indices, n * t matrix elements and n elements of vector.
const int full = n * (t + 2);
cudaCheckErrors(cudaMallocHost((void**)&h_fullInput, sizeof(int) * full));
int *h_indices = h_fullInput;
int *h_matrix = h_fullInput + n;
int *h_vector = h_matrix + n * t;
for (int i = 0; i < t; i++) {
h_indices[i] = fetch_int();
for (int j = 0 ; j < n ; j++) {
int index = t * i + j;
h_matrix[index] = fetch_int();
}
}
for (int i = 0 ; i < n ; i++) {
h_vector[i] = fetch_int();
}
int *d_fullInput;
cudaCheckErrors(cudaMalloc((void**)&d_fullInput, sizeof(int) * full));
cudaMemcpy(d_fullInput, h_fullInput, sizeof(int) * full, cudaMemcpyHostToDevice);
const int *d_indices = d_fullInput;
const int *d_matrix = d_fullInput + n;
const int *d_vector = d_matrix + n * t;
int * d_output;
cudaCheckErrors(cudaMalloc((void**)&d_output, sizeof(int) * n));
const int blockSize = 512;
const int gridSize = (n + blockSize - 1) / blockSize;
matrix_multiplication<<<gridSize, blockSize>>>(d_indices, d_matrix, d_vector, d_output, n, t);
// write output into indices to save malloc call
int * h_output = h_indices;
cudaMemcpy(h_output, d_output, sizeof(int) * n, cudaMemcpyDeviceToHost);
for (int i = 0 ; i < n ; i++) {
printf("%d\n", d_output[i]);
}
cudaFree(d_fullInput);
cudaFree(h_fullInput);
cudaFree(d_output);
} | code for sm_80
Function : _Z21matrix_multiplicationPKiS0_S0_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R20, SR_TID.X ; /* 0x0000000000147919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R20 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0214 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff117624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x660 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R17.reuse, -0x1, RZ ; /* 0xffffffff11027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R17, R17, 0x3, RZ, 0xc0, !PT ; /* 0x0000000311117812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ ISETP.NE.AND P4, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f85270 */
/*0110*/ @!P0 BRA 0x500 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R20, R20, c[0x0][0x180], RZ ; /* 0x0000600014147a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R19, c[0x0][0x180] ; /* 0x0000600000137a02 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff187624 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R18, R17, -c[0x0][0x184], RZ ; /* 0x8000610011127a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R20, R3, c[0x0][0x0], R20 ; /* 0x0000000003147a24 */
/* 0x000fe200078e0214 */
/*0180*/ MOV R23, R0 ; /* 0x0000000000177202 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD R22, R19.reuse, 0x3, R0.reuse ; /* 0x0000000313167824 */
/* 0x140fe200078e0200 */
/*01a0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R19, 0x2, R0 ; /* 0x0000000213137824 */
/* 0x000fe400078e0200 */
/*01c0*/ MOV R2, R24 ; /* 0x0000001800027202 */
/* 0x000fca0000000f00 */
/*01d0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ee8000c1e1900 */
/*01f0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0200*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f62000c1e1900 */
/*0210*/ IMAD.IADD R5, R0.reuse, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x044fe200078e0205 */
/*0220*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x008fc80007ffe0ff */
/*0230*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe20003f04270 */
/*0240*/ IMAD.IADD R9, R0.reuse, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x050fe200078e0209 */
/*0250*/ ISETP.GT.AND P1, PT, R7, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x000fe40003f24270 */
/*0260*/ ISETP.LT.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fe40000701670 */
/*0270*/ ISETP.LT.OR P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f21670 */
/*0280*/ ISETP.GT.AND P2, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe40003f44270 */
/*0290*/ IADD3 R12, R0, R11, RZ ; /* 0x0000000b000c7210 */
/* 0x020fc40007ffe0ff */
/*02a0*/ ISETP.LT.OR P2, PT, R9, RZ, P2 ; /* 0x000000ff0900720c */
/* 0x000fe40001741670 */
/*02b0*/ ISETP.GT.AND P3, PT, R12, c[0x0][0x180], PT ; /* 0x000060000c007a0c */
/* 0x000fc60003f64270 */
/*02c0*/ @!P0 IMAD.MOV.U32 R26, RZ, RZ, 0x4 ; /* 0x00000004ff1a8424 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.LT.OR P3, PT, R12, RZ, P3 ; /* 0x000000ff0c00720c */
/* 0x000fe40001f61670 */
/*02e0*/ @!P1 MOV R6, 0x4 ; /* 0x0000000400069802 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P0 IMAD.WIDE R14, R5, R26, c[0x0][0x170] ; /* 0x00005c00050e8625 */
/* 0x000fc800078e021a */
/*0300*/ @!P0 IMAD.WIDE R26, R23, R26, c[0x0][0x168] ; /* 0x00005a00171a8625 */
/* 0x000fe200078e021a */
/*0310*/ @!P0 LDG.E R25, [R14.64] ; /* 0x000000040e198981 */
/* 0x0000a6000c1e1900 */
/*0320*/ @!P2 IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0aa424 */
/* 0x000fe200078e00ff */
/*0330*/ @!P0 LDG.E R24, [R26.64] ; /* 0x000000041a188981 */
/* 0x000ea2000c1e1900 */
/*0340*/ @!P1 IMAD.WIDE R4, R7, R6, c[0x0][0x170] ; /* 0x00005c0007049625 */
/* 0x000fe200078e0206 */
/*0350*/ @!P3 MOV R29, 0x4 ; /* 0x00000004001db802 */
/* 0x000fc60000000f00 */
/*0360*/ @!P1 IMAD.WIDE R6, R20, R6, c[0x0][0x168] ; /* 0x00005a0014069625 */
/* 0x000fe400078e0206 */
/*0370*/ @!P1 LDG.E R5, [R4.64] ; /* 0x0000000404059981 */
/* 0x0002e4000c1e1900 */
/*0380*/ @!P2 IMAD.WIDE R8, R9, R10.reuse, c[0x0][0x170] ; /* 0x00005c000908a625 */
/* 0x080fe400078e020a */
/*0390*/ @!P1 LDG.E R6, [R6.64] ; /* 0x0000000406069981 */
/* 0x000ee4000c1e1900 */
/*03a0*/ @!P2 IMAD.WIDE R10, R19, R10, c[0x0][0x168] ; /* 0x00005a00130aa625 */
/* 0x000fe400078e020a */
/*03b0*/ @!P2 LDG.E R9, [R8.64] ; /* 0x000000040809a981 */
/* 0x000f24000c1e1900 */
/*03c0*/ @!P3 IMAD.WIDE R12, R12, R29, c[0x0][0x170] ; /* 0x00005c000c0cb625 */
/* 0x000fc400078e021d */
/*03d0*/ @!P2 LDG.E R10, [R10.64] ; /* 0x000000040a0aa981 */
/* 0x000f24000c1e1900 */
/*03e0*/ @!P3 IMAD.WIDE R14, R22, R29, c[0x0][0x168] ; /* 0x00005a00160eb625 */
/* 0x001fe400078e021d */
/*03f0*/ @!P3 LDG.E R13, [R12.64] ; /* 0x000000040c0db981 */
/* 0x000f68000c1e1900 */
/*0400*/ @!P3 LDG.E R14, [R14.64] ; /* 0x000000040e0eb981 */
/* 0x000f62000c1e1900 */
/*0410*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*0420*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x002fc80000000f00 */
/*0430*/ LEA R23, R4.reuse, R23, 0x2 ; /* 0x0000001704177211 */
/* 0x040fe200078e10ff */
/*0440*/ IMAD R20, R4.reuse, 0x4, R20 ; /* 0x0000000404147824 */
/* 0x040fe200078e0214 */
/*0450*/ LEA R19, R4.reuse, R19, 0x2 ; /* 0x0000001304137211 */
/* 0x040fe200078e10ff */
/*0460*/ IMAD R22, R4, 0x4, R22 ; /* 0x0000000404167824 */
/* 0x000fe400078e0216 */
/*0470*/ @!P0 IMAD R16, R25, R24, R16 ; /* 0x0000001819108224 */
/* 0x004fe200078e0210 */
/*0480*/ IADD3 R24, P0, R2, 0x10, RZ ; /* 0x0000001002187810 */
/* 0x000fe20007f1e0ff */
/*0490*/ IMAD.IADD R2, R18, 0x1, R21 ; /* 0x0000000112027824 */
/* 0x000fc800078e0215 */
/*04a0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*04b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*04c0*/ @!P1 IMAD R16, R5, R6, R16 ; /* 0x0000000605109224 */
/* 0x008fc800078e0210 */
/*04d0*/ @!P2 IMAD R16, R9, R10, R16 ; /* 0x0000000a0910a224 */
/* 0x010fc800078e0210 */
/*04e0*/ @!P3 IMAD R16, R13, R14, R16 ; /* 0x0000000e0d10b224 */
/* 0x020fc800078e0210 */
/*04f0*/ @P0 BRA 0x1c0 ; /* 0xfffffcc000000947 */
/* 0x000fea000383ffff */
/*0500*/ @!P4 BRA 0x660 ; /* 0x000001500000c947 */
/* 0x000fea0003800000 */
/*0510*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0520*/ IMAD.WIDE R2, R21, R2, c[0x0][0x160] ; /* 0x0000580015027625 */
/* 0x000fc800078e0202 */
/*0530*/ IMAD R21, R21, c[0x0][0x180], R0 ; /* 0x0000600015157a24 */
/* 0x000fe200078e0200 */
/*0540*/ MOV R7, R3 ; /* 0x0000000300077202 */
/* 0x000fe20000000f00 */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0002 */
/*0560*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea4000c1e1900 */
/*0570*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x004fca00078e0203 */
/*0580*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fc80003f04270 */
/*0590*/ ISETP.LT.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000701670 */
/*05a0*/ @!P0 MOV R2, 0x4 ; /* 0x0000000400028802 */
/* 0x000fca0000000f00 */
/*05b0*/ @!P0 IMAD.WIDE R4, R3, R2, c[0x0][0x170] ; /* 0x00005c0003048625 */
/* 0x000fc800078e0202 */
/*05c0*/ @!P0 IMAD.WIDE R2, R21, R2, c[0x0][0x168] ; /* 0x00005a0015028625 */
/* 0x000fe400078e0202 */
/*05d0*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000404058981 */
/* 0x000ea8000c1e1900 */
/*05e0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ IADD3 R17, R17, -0x1, RZ ; /* 0xffffffff11117810 */
/* 0x000fe40007ffe0ff */
/*0600*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f5e0ff */
/*0610*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc40003f25270 */
/*0620*/ IADD3 R21, R21, c[0x0][0x180], RZ ; /* 0x0000600015157a10 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0640*/ @!P0 IMAD R16, R5, R2, R16 ; /* 0x0000000205108224 */
/* 0x004fd000078e0210 */
/*0650*/ @P1 BRA 0x560 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0660*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0670*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0203 */
/*0680*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cassert>
#include <cuda_runtime.h>
using namespace std;
__global__ void matrix_multiplication(const int *d_indices,
const int *d_matrix,
const int *d_vector,
int *d_output,
int n,
int t) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
return;
int result = 0;
for (int i = 0 ; i < t; i++) {
const int multiplierIndex = index + d_indices[i];
if (multiplierIndex < 0 || multiplierIndex > n)
continue;
const int elemIndex = n * i + index;
result += d_matrix[elemIndex] * d_vector[multiplierIndex];
}
d_output[index] = result;
}
#define cudaCheckErrors(EXPR) assert(EXPR == cudaSuccess)
/// Function for fast integer fetching
int fetch_int() {
int result = 0;
char c = 0;
// skip all other chars
while (c < '0' or c > '9') {
c = getchar_unlocked();
}
while ('0' <= c and c <= '9') {
result *= 10;
result += c - '0';
c = getchar_unlocked();
}
return result;
}
int main() {
int n = fetch_int();
int t = fetch_int();
int *h_fullInput;
// We need memory for n indices, n * t matrix elements and n elements of vector.
const int full = n * (t + 2);
cudaCheckErrors(cudaMallocHost((void**)&h_fullInput, sizeof(int) * full));
int *h_indices = h_fullInput;
int *h_matrix = h_fullInput + n;
int *h_vector = h_matrix + n * t;
for (int i = 0; i < t; i++) {
h_indices[i] = fetch_int();
for (int j = 0 ; j < n ; j++) {
int index = t * i + j;
h_matrix[index] = fetch_int();
}
}
for (int i = 0 ; i < n ; i++) {
h_vector[i] = fetch_int();
}
int *d_fullInput;
cudaCheckErrors(cudaMalloc((void**)&d_fullInput, sizeof(int) * full));
cudaMemcpy(d_fullInput, h_fullInput, sizeof(int) * full, cudaMemcpyHostToDevice);
const int *d_indices = d_fullInput;
const int *d_matrix = d_fullInput + n;
const int *d_vector = d_matrix + n * t;
int * d_output;
cudaCheckErrors(cudaMalloc((void**)&d_output, sizeof(int) * n));
const int blockSize = 512;
const int gridSize = (n + blockSize - 1) / blockSize;
matrix_multiplication<<<gridSize, blockSize>>>(d_indices, d_matrix, d_vector, d_output, n, t);
// write output into indices to save malloc call
int * h_output = h_indices;
cudaMemcpy(h_output, d_output, sizeof(int) * n, cudaMemcpyDeviceToHost);
for (int i = 0 ; i < n ; i++) {
printf("%d\n", d_output[i]);
}
cudaFree(d_fullInput);
cudaFree(h_fullInput);
cudaFree(d_output);
} | .file "tmpxft_00129167_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9fetch_intv
.type _Z9fetch_intv, @function
_Z9fetch_intv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
.L6:
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jnb .L13
leaq 1(%rax), %rdx
movq %rdx, 8(%rdi)
movzbl (%rax), %edx
.L5:
leal -48(%rdx), %eax
cmpb $9, %al
ja .L6
movl $0, %ebx
.L9:
leal (%rbx,%rbx,4), %eax
subl $48, %edx
movsbl %dl, %edx
leal (%rdx,%rax,2), %ebx
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jnb .L14
leaq 1(%rax), %rdx
movq %rdx, 8(%rdi)
movzbl (%rax), %eax
.L8:
movl %eax, %edx
subl $48, %eax
cmpb $9, %al
jbe .L9
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __uflow@PLT
movl %eax, %edx
jmp .L5
.L14:
call __uflow@PLT
jmp .L8
.cfi_endproc
.LFE2057:
.size _Z9fetch_intv, .-_Z9fetch_intv
.globl _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
.type _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii, @function
_Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21matrix_multiplicationPKiS0_S0_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii, .-_Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
.globl _Z21matrix_multiplicationPKiS0_S0_Piii
.type _Z21matrix_multiplicationPKiS0_S0_Piii, @function
_Z21matrix_multiplicationPKiS0_S0_Piii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z21matrix_multiplicationPKiS0_S0_Piii, .-_Z21matrix_multiplicationPKiS0_S0_Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
call _Z9fetch_intv
movl %eax, %r14d
call _Z9fetch_intv
movl %eax, %ecx
movl %eax, 40(%rsp)
leal 2(%rax), %eax
imull %r14d, %eax
movl %eax, 44(%rsp)
movslq %r14d, %rsi
movq %rsi, 8(%rsp)
leaq 0(,%rsi,4), %rdi
movq %rdi, 24(%rsp)
movq %rdi, %r15
leal (%r14,%r14), %edx
subl %edx, %eax
cltq
movq %rax, 32(%rsp)
testl %ecx, %ecx
jle .L24
movl $0, %r12d
movslq %ecx, %rax
salq $2, %rax
movq %rax, 16(%rsp)
movl $0, %r13d
.L27:
call _Z9fetch_intv
movl %eax, (%r12)
testl %r14d, %r14d
jle .L25
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rcx
addq %rcx, %rax
leaq (%r15,%rax,4), %rbp
.L26:
call _Z9fetch_intv
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
.L25:
addq $4, %r12
movl 40(%rsp), %eax
addl %eax, %r13d
movq 16(%rsp), %rax
cmpq %rax, %r12
jne .L27
.L24:
testl %r14d, %r14d
jle .L28
movq 32(%rsp), %rsi
leaq (%r15,%rsi,4), %rbx
movq 8(%rsp), %rax
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L29:
call _Z9fetch_intv
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
.L28:
movslq 44(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movl $0, %edi
movq %rdi, %rsi
call cudaMemcpy@PLT
movl $512, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L30:
movl $2, %ecx
movq 24(%rsp), %r15
movq %r15, %rdx
movl $0, %esi
movl $0, %edi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L31
movl $0, %esi
movq %rsi, %rbx
addq %rsi, %r15
movq %r15, %rbp
leaq .LC0(%rip), %r12
.L32:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
.L31:
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %esi
movq %rsi, %rdi
call cudaFree@PLT
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl $0, %edi
movq 24(%rsp), %rcx
leaq (%rdi,%rcx), %rax
movq 32(%rsp), %rsi
leaq (%rcx,%rsi,4), %rdx
movl 40(%rsp), %r9d
movl %r14d, %r8d
movl $0, %esi
movq %rsi, %rcx
movq %rax, %rsi
call _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
jmp .L30
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z21matrix_multiplicationPKiS0_S0_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21matrix_multiplicationPKiS0_S0_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cassert>
#include <cuda_runtime.h>
using namespace std;
__global__ void matrix_multiplication(const int *d_indices,
const int *d_matrix,
const int *d_vector,
int *d_output,
int n,
int t) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
return;
int result = 0;
for (int i = 0 ; i < t; i++) {
const int multiplierIndex = index + d_indices[i];
if (multiplierIndex < 0 || multiplierIndex > n)
continue;
const int elemIndex = n * i + index;
result += d_matrix[elemIndex] * d_vector[multiplierIndex];
}
d_output[index] = result;
}
#define cudaCheckErrors(EXPR) assert(EXPR == cudaSuccess)
/// Function for fast integer fetching
int fetch_int() {
int result = 0;
char c = 0;
// skip all other chars
while (c < '0' or c > '9') {
c = getchar_unlocked();
}
while ('0' <= c and c <= '9') {
result *= 10;
result += c - '0';
c = getchar_unlocked();
}
return result;
}
int main() {
int n = fetch_int();
int t = fetch_int();
int *h_fullInput;
// We need memory for n indices, n * t matrix elements and n elements of vector.
const int full = n * (t + 2);
cudaCheckErrors(cudaMallocHost((void**)&h_fullInput, sizeof(int) * full));
int *h_indices = h_fullInput;
int *h_matrix = h_fullInput + n;
int *h_vector = h_matrix + n * t;
for (int i = 0; i < t; i++) {
h_indices[i] = fetch_int();
for (int j = 0 ; j < n ; j++) {
int index = t * i + j;
h_matrix[index] = fetch_int();
}
}
for (int i = 0 ; i < n ; i++) {
h_vector[i] = fetch_int();
}
int *d_fullInput;
cudaCheckErrors(cudaMalloc((void**)&d_fullInput, sizeof(int) * full));
cudaMemcpy(d_fullInput, h_fullInput, sizeof(int) * full, cudaMemcpyHostToDevice);
const int *d_indices = d_fullInput;
const int *d_matrix = d_fullInput + n;
const int *d_vector = d_matrix + n * t;
int * d_output;
cudaCheckErrors(cudaMalloc((void**)&d_output, sizeof(int) * n));
const int blockSize = 512;
const int gridSize = (n + blockSize - 1) / blockSize;
matrix_multiplication<<<gridSize, blockSize>>>(d_indices, d_matrix, d_vector, d_output, n, t);
// write output into indices to save malloc call
int * h_output = h_indices;
cudaMemcpy(h_output, d_output, sizeof(int) * n, cudaMemcpyDeviceToHost);
for (int i = 0 ; i < n ; i++) {
printf("%d\n", d_output[i]);
}
cudaFree(d_fullInput);
cudaFree(h_fullInput);
cudaFree(d_output);
} | #include <cstdio>
#include <cassert>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void matrix_multiplication(const int *d_indices,
const int *d_matrix,
const int *d_vector,
int *d_output,
int n,
int t) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
return;
int result = 0;
for (int i = 0 ; i < t; i++) {
const int multiplierIndex = index + d_indices[i];
if (multiplierIndex < 0 || multiplierIndex > n)
continue;
const int elemIndex = n * i + index;
result += d_matrix[elemIndex] * d_vector[multiplierIndex];
}
d_output[index] = result;
}
#define cudaCheckErrors(EXPR) assert(EXPR == hipSuccess)
/// Function for fast integer fetching
int fetch_int() {
int result = 0;
char c = 0;
// skip all other chars
while (c < '0' or c > '9') {
c = getchar_unlocked();
}
while ('0' <= c and c <= '9') {
result *= 10;
result += c - '0';
c = getchar_unlocked();
}
return result;
}
int main() {
int n = fetch_int();
int t = fetch_int();
int *h_fullInput;
// We need memory for n indices, n * t matrix elements and n elements of vector.
const int full = n * (t + 2);
cudaCheckErrors(hipHostMalloc((void**)&h_fullInput, sizeof(int) * full, hipHostMallocDefault));
int *h_indices = h_fullInput;
int *h_matrix = h_fullInput + n;
int *h_vector = h_matrix + n * t;
for (int i = 0; i < t; i++) {
h_indices[i] = fetch_int();
for (int j = 0 ; j < n ; j++) {
int index = t * i + j;
h_matrix[index] = fetch_int();
}
}
for (int i = 0 ; i < n ; i++) {
h_vector[i] = fetch_int();
}
int *d_fullInput;
cudaCheckErrors(hipMalloc((void**)&d_fullInput, sizeof(int) * full));
hipMemcpy(d_fullInput, h_fullInput, sizeof(int) * full, hipMemcpyHostToDevice);
const int *d_indices = d_fullInput;
const int *d_matrix = d_fullInput + n;
const int *d_vector = d_matrix + n * t;
int * d_output;
cudaCheckErrors(hipMalloc((void**)&d_output, sizeof(int) * n));
const int blockSize = 512;
const int gridSize = (n + blockSize - 1) / blockSize;
matrix_multiplication<<<gridSize, blockSize>>>(d_indices, d_matrix, d_vector, d_output, n, t);
// write output into indices to save malloc call
int * h_output = h_indices;
hipMemcpy(h_output, d_output, sizeof(int) * n, hipMemcpyDeviceToHost);
for (int i = 0 ; i < n ; i++) {
printf("%d\n", d_output[i]);
}
hipFree(d_fullInput);
hipFree(h_fullInput);
hipFree(d_output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cstdio>
#include <cassert>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void matrix_multiplication(const int *d_indices,
const int *d_matrix,
const int *d_vector,
int *d_output,
int n,
int t) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
return;
int result = 0;
for (int i = 0 ; i < t; i++) {
const int multiplierIndex = index + d_indices[i];
if (multiplierIndex < 0 || multiplierIndex > n)
continue;
const int elemIndex = n * i + index;
result += d_matrix[elemIndex] * d_vector[multiplierIndex];
}
d_output[index] = result;
}
#define cudaCheckErrors(EXPR) assert(EXPR == hipSuccess)
/// Function for fast integer fetching
int fetch_int() {
int result = 0;
char c = 0;
// skip all other chars
while (c < '0' or c > '9') {
c = getchar_unlocked();
}
while ('0' <= c and c <= '9') {
result *= 10;
result += c - '0';
c = getchar_unlocked();
}
return result;
}
int main() {
int n = fetch_int();
int t = fetch_int();
int *h_fullInput;
// We need memory for n indices, n * t matrix elements and n elements of vector.
const int full = n * (t + 2);
cudaCheckErrors(hipHostMalloc((void**)&h_fullInput, sizeof(int) * full, hipHostMallocDefault));
int *h_indices = h_fullInput;
int *h_matrix = h_fullInput + n;
int *h_vector = h_matrix + n * t;
for (int i = 0; i < t; i++) {
h_indices[i] = fetch_int();
for (int j = 0 ; j < n ; j++) {
int index = t * i + j;
h_matrix[index] = fetch_int();
}
}
for (int i = 0 ; i < n ; i++) {
h_vector[i] = fetch_int();
}
int *d_fullInput;
cudaCheckErrors(hipMalloc((void**)&d_fullInput, sizeof(int) * full));
hipMemcpy(d_fullInput, h_fullInput, sizeof(int) * full, hipMemcpyHostToDevice);
const int *d_indices = d_fullInput;
const int *d_matrix = d_fullInput + n;
const int *d_vector = d_matrix + n * t;
int * d_output;
cudaCheckErrors(hipMalloc((void**)&d_output, sizeof(int) * n));
const int blockSize = 512;
const int gridSize = (n + blockSize - 1) / blockSize;
matrix_multiplication<<<gridSize, blockSize>>>(d_indices, d_matrix, d_vector, d_output, n, t);
// write output into indices to save malloc call
int * h_output = h_indices;
hipMemcpy(h_output, d_output, sizeof(int) * n, hipMemcpyDeviceToHost);
for (int i = 0 ; i < n ; i++) {
printf("%d\n", d_output[i]);
}
hipFree(d_fullInput);
hipFree(h_fullInput);
hipFree(d_output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21matrix_multiplicationPKiS0_S0_Piii
.globl _Z21matrix_multiplicationPKiS0_S0_Piii
.p2align 8
.type _Z21matrix_multiplicationPKiS0_S0_Piii,@function
_Z21matrix_multiplicationPKiS0_S0_Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b32 s10, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v1
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, s3, v4
s_add_i32 s10, s10, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_ge_i32_e64 s2, s3, v2
s_and_b32 s11, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
global_load_b32 v2, v[5:6], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v7, v2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v5
s_branch .LBB0_3
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21matrix_multiplicationPKiS0_S0_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21matrix_multiplicationPKiS0_S0_Piii, .Lfunc_end0-_Z21matrix_multiplicationPKiS0_S0_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21matrix_multiplicationPKiS0_S0_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21matrix_multiplicationPKiS0_S0_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cstdio>
#include <cassert>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void matrix_multiplication(const int *d_indices,
const int *d_matrix,
const int *d_vector,
int *d_output,
int n,
int t) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
return;
int result = 0;
for (int i = 0 ; i < t; i++) {
const int multiplierIndex = index + d_indices[i];
if (multiplierIndex < 0 || multiplierIndex > n)
continue;
const int elemIndex = n * i + index;
result += d_matrix[elemIndex] * d_vector[multiplierIndex];
}
d_output[index] = result;
}
#define cudaCheckErrors(EXPR) assert(EXPR == hipSuccess)
/// Function for fast integer fetching
int fetch_int() {
int result = 0;
char c = 0;
// skip all other chars
while (c < '0' or c > '9') {
c = getchar_unlocked();
}
while ('0' <= c and c <= '9') {
result *= 10;
result += c - '0';
c = getchar_unlocked();
}
return result;
}
int main() {
int n = fetch_int();
int t = fetch_int();
int *h_fullInput;
// We need memory for n indices, n * t matrix elements and n elements of vector.
const int full = n * (t + 2);
cudaCheckErrors(hipHostMalloc((void**)&h_fullInput, sizeof(int) * full, hipHostMallocDefault));
int *h_indices = h_fullInput;
int *h_matrix = h_fullInput + n;
int *h_vector = h_matrix + n * t;
for (int i = 0; i < t; i++) {
h_indices[i] = fetch_int();
for (int j = 0 ; j < n ; j++) {
int index = t * i + j;
h_matrix[index] = fetch_int();
}
}
for (int i = 0 ; i < n ; i++) {
h_vector[i] = fetch_int();
}
int *d_fullInput;
cudaCheckErrors(hipMalloc((void**)&d_fullInput, sizeof(int) * full));
hipMemcpy(d_fullInput, h_fullInput, sizeof(int) * full, hipMemcpyHostToDevice);
const int *d_indices = d_fullInput;
const int *d_matrix = d_fullInput + n;
const int *d_vector = d_matrix + n * t;
int * d_output;
cudaCheckErrors(hipMalloc((void**)&d_output, sizeof(int) * n));
const int blockSize = 512;
const int gridSize = (n + blockSize - 1) / blockSize;
matrix_multiplication<<<gridSize, blockSize>>>(d_indices, d_matrix, d_vector, d_output, n, t);
// write output into indices to save malloc call
int * h_output = h_indices;
hipMemcpy(h_output, d_output, sizeof(int) * n, hipMemcpyDeviceToHost);
for (int i = 0 ; i < n ; i++) {
printf("%d\n", d_output[i]);
}
hipFree(d_fullInput);
hipFree(h_fullInput);
hipFree(d_output);
} | .text
.file "main.hip"
.globl _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii # -- Begin function _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.p2align 4, 0x90
.type _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii,@function
_Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii: # @_Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21matrix_multiplicationPKiS0_S0_Piii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii, .Lfunc_end0-_Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.cfi_endproc
# -- End function
.globl _Z9fetch_intv # -- Begin function _Z9fetch_intv
.p2align 4, 0x90
.type _Z9fetch_intv,@function
_Z9fetch_intv: # @_Z9fetch_intv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB1_2
# %bb.7: # in Loop: Header=BB1_1 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %ebx
.LBB1_8: # %getchar_unlocked.exit
# in Loop: Header=BB1_1 Depth=1
leal -58(%rbx), %eax
cmpb $-10, %al
jb .LBB1_1
jmp .LBB1_3
.LBB1_2: # in Loop: Header=BB1_1 Depth=1
callq __uflow
movl %eax, %ebx
jmp .LBB1_8
.LBB1_3: # %.preheader
leal -48(%rbx), %eax
xorl %r14d, %r14d
cmpb $9, %al
ja .LBB1_11
# %bb.4: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB1_6
# %bb.9: # in Loop: Header=BB1_5 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %eax
.LBB1_10: # %getchar_unlocked.exit11
# in Loop: Header=BB1_5 Depth=1
movzbl %bl, %ecx
leal (%r14,%r14,4), %edx
leal (%rcx,%rdx,2), %r14d
addl $-48, %r14d
leal -48(%rax), %ecx
movl %eax, %ebx
cmpb $10, %cl
jb .LBB1_5
jmp .LBB1_11
.LBB1_6: # in Loop: Header=BB1_5 Depth=1
callq __uflow
# kill: def $eax killed $eax def $rax
jmp .LBB1_10
.LBB1_11: # %._crit_edge
movl %r14d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9fetch_intv, .Lfunc_end1-_Z9fetch_intv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_2
# %bb.7: # in Loop: Header=BB2_1 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %ebx
.LBB2_8: # %getchar_unlocked.exit.i
# in Loop: Header=BB2_1 Depth=1
leal -58(%rbx), %eax
cmpb $-10, %al
jb .LBB2_1
jmp .LBB2_3
.LBB2_2: # in Loop: Header=BB2_1 Depth=1
callq __uflow
movl %eax, %ebx
jmp .LBB2_8
.LBB2_3: # %.preheader.i
leal -48(%rbx), %eax
xorl %r14d, %r14d
cmpb $9, %al
ja .LBB2_11
# %bb.4: # %.lr.ph.i.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_6
# %bb.9: # in Loop: Header=BB2_5 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %eax
.LBB2_10: # %getchar_unlocked.exit11.i
# in Loop: Header=BB2_5 Depth=1
movzbl %bl, %ecx
leal (%r14,%r14,4), %edx
leal (%rcx,%rdx,2), %r14d
addl $-48, %r14d
leal -48(%rax), %ecx
movl %eax, %ebx
cmpb $10, %cl
jb .LBB2_5
jmp .LBB2_11
.LBB2_6: # in Loop: Header=BB2_5 Depth=1
callq __uflow
# kill: def $eax killed $eax def $rax
jmp .LBB2_10
.LBB2_12: # in Loop: Header=BB2_11 Depth=1
callq __uflow
movl %eax, %ebx
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_12
# %bb.17: # in Loop: Header=BB2_11 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %ebx
.LBB2_18: # %getchar_unlocked.exit.i63
# in Loop: Header=BB2_11 Depth=1
leal -58(%rbx), %eax
cmpb $-10, %al
jb .LBB2_11
# %bb.13: # %.preheader.i64
leal -48(%rbx), %eax
xorl %r15d, %r15d
cmpb $9, %al
ja .LBB2_21
# %bb.14: # %.lr.ph.i66.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_15: # %.lr.ph.i66
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_16
# %bb.19: # in Loop: Header=BB2_15 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %eax
.LBB2_20: # %getchar_unlocked.exit11.i70
# in Loop: Header=BB2_15 Depth=1
movzbl %bl, %ecx
leal (%r15,%r15,4), %edx
leal (%rcx,%rdx,2), %r15d
addl $-48, %r15d
leal -48(%rax), %ecx
movl %eax, %ebx
cmpb $10, %cl
jb .LBB2_15
jmp .LBB2_21
.LBB2_16: # in Loop: Header=BB2_15 Depth=1
callq __uflow
# kill: def $eax killed $eax def $rax
jmp .LBB2_20
.LBB2_21: # %_Z9fetch_intv.exit71
testl %r15d, %r15d
jg .LBB2_26
# %bb.22:
testl %r14d, %r14d
jg .LBB2_26
# %bb.23:
leal 2(%r15), %eax
imull %r14d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
leal 511(%r14), %eax
leal 1022(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_25
# %bb.24:
movl %r14d, 12(%rsp)
movl %r15d, 8(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 112(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21matrix_multiplicationPKiS0_S0_Piii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_25: # %._crit_edge
movslq %r14d, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipFree
callq hipFree
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_26:
.cfi_def_cfa_offset 176
callq _Z9fetch_intv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21matrix_multiplicationPKiS0_S0_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21matrix_multiplicationPKiS0_S0_Piii,@object # @_Z21matrix_multiplicationPKiS0_S0_Piii
.section .rodata,"a",@progbits
.globl _Z21matrix_multiplicationPKiS0_S0_Piii
.p2align 3, 0x0
_Z21matrix_multiplicationPKiS0_S0_Piii:
.quad _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.size _Z21matrix_multiplicationPKiS0_S0_Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21matrix_multiplicationPKiS0_S0_Piii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21matrix_multiplicationPKiS0_S0_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21matrix_multiplicationPKiS0_S0_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R20, SR_TID.X ; /* 0x0000000000147919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R20 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0214 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff117624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x660 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R17.reuse, -0x1, RZ ; /* 0xffffffff11027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R17, R17, 0x3, RZ, 0xc0, !PT ; /* 0x0000000311117812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ ISETP.NE.AND P4, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f85270 */
/*0110*/ @!P0 BRA 0x500 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R20, R20, c[0x0][0x180], RZ ; /* 0x0000600014147a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R19, c[0x0][0x180] ; /* 0x0000600000137a02 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff187624 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R18, R17, -c[0x0][0x184], RZ ; /* 0x8000610011127a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R20, R3, c[0x0][0x0], R20 ; /* 0x0000000003147a24 */
/* 0x000fe200078e0214 */
/*0180*/ MOV R23, R0 ; /* 0x0000000000177202 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD R22, R19.reuse, 0x3, R0.reuse ; /* 0x0000000313167824 */
/* 0x140fe200078e0200 */
/*01a0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R19, 0x2, R0 ; /* 0x0000000213137824 */
/* 0x000fe400078e0200 */
/*01c0*/ MOV R2, R24 ; /* 0x0000001800027202 */
/* 0x000fca0000000f00 */
/*01d0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ee8000c1e1900 */
/*01f0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0200*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f62000c1e1900 */
/*0210*/ IMAD.IADD R5, R0.reuse, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x044fe200078e0205 */
/*0220*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x008fc80007ffe0ff */
/*0230*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe20003f04270 */
/*0240*/ IMAD.IADD R9, R0.reuse, 0x1, R9 ; /* 0x0000000100097824 */
/* 0x050fe200078e0209 */
/*0250*/ ISETP.GT.AND P1, PT, R7, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x000fe40003f24270 */
/*0260*/ ISETP.LT.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fe40000701670 */
/*0270*/ ISETP.LT.OR P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f21670 */
/*0280*/ ISETP.GT.AND P2, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe40003f44270 */
/*0290*/ IADD3 R12, R0, R11, RZ ; /* 0x0000000b000c7210 */
/* 0x020fc40007ffe0ff */
/*02a0*/ ISETP.LT.OR P2, PT, R9, RZ, P2 ; /* 0x000000ff0900720c */
/* 0x000fe40001741670 */
/*02b0*/ ISETP.GT.AND P3, PT, R12, c[0x0][0x180], PT ; /* 0x000060000c007a0c */
/* 0x000fc60003f64270 */
/*02c0*/ @!P0 IMAD.MOV.U32 R26, RZ, RZ, 0x4 ; /* 0x00000004ff1a8424 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.LT.OR P3, PT, R12, RZ, P3 ; /* 0x000000ff0c00720c */
/* 0x000fe40001f61670 */
/*02e0*/ @!P1 MOV R6, 0x4 ; /* 0x0000000400069802 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P0 IMAD.WIDE R14, R5, R26, c[0x0][0x170] ; /* 0x00005c00050e8625 */
/* 0x000fc800078e021a */
/*0300*/ @!P0 IMAD.WIDE R26, R23, R26, c[0x0][0x168] ; /* 0x00005a00171a8625 */
/* 0x000fe200078e021a */
/*0310*/ @!P0 LDG.E R25, [R14.64] ; /* 0x000000040e198981 */
/* 0x0000a6000c1e1900 */
/*0320*/ @!P2 IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0aa424 */
/* 0x000fe200078e00ff */
/*0330*/ @!P0 LDG.E R24, [R26.64] ; /* 0x000000041a188981 */
/* 0x000ea2000c1e1900 */
/*0340*/ @!P1 IMAD.WIDE R4, R7, R6, c[0x0][0x170] ; /* 0x00005c0007049625 */
/* 0x000fe200078e0206 */
/*0350*/ @!P3 MOV R29, 0x4 ; /* 0x00000004001db802 */
/* 0x000fc60000000f00 */
/*0360*/ @!P1 IMAD.WIDE R6, R20, R6, c[0x0][0x168] ; /* 0x00005a0014069625 */
/* 0x000fe400078e0206 */
/*0370*/ @!P1 LDG.E R5, [R4.64] ; /* 0x0000000404059981 */
/* 0x0002e4000c1e1900 */
/*0380*/ @!P2 IMAD.WIDE R8, R9, R10.reuse, c[0x0][0x170] ; /* 0x00005c000908a625 */
/* 0x080fe400078e020a */
/*0390*/ @!P1 LDG.E R6, [R6.64] ; /* 0x0000000406069981 */
/* 0x000ee4000c1e1900 */
/*03a0*/ @!P2 IMAD.WIDE R10, R19, R10, c[0x0][0x168] ; /* 0x00005a00130aa625 */
/* 0x000fe400078e020a */
/*03b0*/ @!P2 LDG.E R9, [R8.64] ; /* 0x000000040809a981 */
/* 0x000f24000c1e1900 */
/*03c0*/ @!P3 IMAD.WIDE R12, R12, R29, c[0x0][0x170] ; /* 0x00005c000c0cb625 */
/* 0x000fc400078e021d */
/*03d0*/ @!P2 LDG.E R10, [R10.64] ; /* 0x000000040a0aa981 */
/* 0x000f24000c1e1900 */
/*03e0*/ @!P3 IMAD.WIDE R14, R22, R29, c[0x0][0x168] ; /* 0x00005a00160eb625 */
/* 0x001fe400078e021d */
/*03f0*/ @!P3 LDG.E R13, [R12.64] ; /* 0x000000040c0db981 */
/* 0x000f68000c1e1900 */
/*0400*/ @!P3 LDG.E R14, [R14.64] ; /* 0x000000040e0eb981 */
/* 0x000f62000c1e1900 */
/*0410*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe40007ffe0ff */
/*0420*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x002fc80000000f00 */
/*0430*/ LEA R23, R4.reuse, R23, 0x2 ; /* 0x0000001704177211 */
/* 0x040fe200078e10ff */
/*0440*/ IMAD R20, R4.reuse, 0x4, R20 ; /* 0x0000000404147824 */
/* 0x040fe200078e0214 */
/*0450*/ LEA R19, R4.reuse, R19, 0x2 ; /* 0x0000001304137211 */
/* 0x040fe200078e10ff */
/*0460*/ IMAD R22, R4, 0x4, R22 ; /* 0x0000000404167824 */
/* 0x000fe400078e0216 */
/*0470*/ @!P0 IMAD R16, R25, R24, R16 ; /* 0x0000001819108224 */
/* 0x004fe200078e0210 */
/*0480*/ IADD3 R24, P0, R2, 0x10, RZ ; /* 0x0000001002187810 */
/* 0x000fe20007f1e0ff */
/*0490*/ IMAD.IADD R2, R18, 0x1, R21 ; /* 0x0000000112027824 */
/* 0x000fc800078e0215 */
/*04a0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*04b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*04c0*/ @!P1 IMAD R16, R5, R6, R16 ; /* 0x0000000605109224 */
/* 0x008fc800078e0210 */
/*04d0*/ @!P2 IMAD R16, R9, R10, R16 ; /* 0x0000000a0910a224 */
/* 0x010fc800078e0210 */
/*04e0*/ @!P3 IMAD R16, R13, R14, R16 ; /* 0x0000000e0d10b224 */
/* 0x020fc800078e0210 */
/*04f0*/ @P0 BRA 0x1c0 ; /* 0xfffffcc000000947 */
/* 0x000fea000383ffff */
/*0500*/ @!P4 BRA 0x660 ; /* 0x000001500000c947 */
/* 0x000fea0003800000 */
/*0510*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0520*/ IMAD.WIDE R2, R21, R2, c[0x0][0x160] ; /* 0x0000580015027625 */
/* 0x000fc800078e0202 */
/*0530*/ IMAD R21, R21, c[0x0][0x180], R0 ; /* 0x0000600015157a24 */
/* 0x000fe200078e0200 */
/*0540*/ MOV R7, R3 ; /* 0x0000000300077202 */
/* 0x000fe20000000f00 */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0002 */
/*0560*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea4000c1e1900 */
/*0570*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x004fca00078e0203 */
/*0580*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fc80003f04270 */
/*0590*/ ISETP.LT.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000701670 */
/*05a0*/ @!P0 MOV R2, 0x4 ; /* 0x0000000400028802 */
/* 0x000fca0000000f00 */
/*05b0*/ @!P0 IMAD.WIDE R4, R3, R2, c[0x0][0x170] ; /* 0x00005c0003048625 */
/* 0x000fc800078e0202 */
/*05c0*/ @!P0 IMAD.WIDE R2, R21, R2, c[0x0][0x168] ; /* 0x00005a0015028625 */
/* 0x000fe400078e0202 */
/*05d0*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000404058981 */
/* 0x000ea8000c1e1900 */
/*05e0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ IADD3 R17, R17, -0x1, RZ ; /* 0xffffffff11117810 */
/* 0x000fe40007ffe0ff */
/*0600*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f5e0ff */
/*0610*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc40003f25270 */
/*0620*/ IADD3 R21, R21, c[0x0][0x180], RZ ; /* 0x0000600015157a10 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0640*/ @!P0 IMAD R16, R5, R2, R16 ; /* 0x0000000205108224 */
/* 0x004fd000078e0210 */
/*0650*/ @P1 BRA 0x560 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0660*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0670*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0203 */
/*0680*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21matrix_multiplicationPKiS0_S0_Piii
.globl _Z21matrix_multiplicationPKiS0_S0_Piii
.p2align 8
.type _Z21matrix_multiplicationPKiS0_S0_Piii,@function
_Z21matrix_multiplicationPKiS0_S0_Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b32 s10, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v1
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, s3, v4
s_add_i32 s10, s10, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_ge_i32_e64 s2, s3, v2
s_and_b32 s11, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
global_load_b32 v2, v[5:6], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v7, v2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v5
s_branch .LBB0_3
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21matrix_multiplicationPKiS0_S0_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21matrix_multiplicationPKiS0_S0_Piii, .Lfunc_end0-_Z21matrix_multiplicationPKiS0_S0_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21matrix_multiplicationPKiS0_S0_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21matrix_multiplicationPKiS0_S0_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00129167_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9fetch_intv
.type _Z9fetch_intv, @function
_Z9fetch_intv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
.L6:
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jnb .L13
leaq 1(%rax), %rdx
movq %rdx, 8(%rdi)
movzbl (%rax), %edx
.L5:
leal -48(%rdx), %eax
cmpb $9, %al
ja .L6
movl $0, %ebx
.L9:
leal (%rbx,%rbx,4), %eax
subl $48, %edx
movsbl %dl, %edx
leal (%rdx,%rax,2), %ebx
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jnb .L14
leaq 1(%rax), %rdx
movq %rdx, 8(%rdi)
movzbl (%rax), %eax
.L8:
movl %eax, %edx
subl $48, %eax
cmpb $9, %al
jbe .L9
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __uflow@PLT
movl %eax, %edx
jmp .L5
.L14:
call __uflow@PLT
jmp .L8
.cfi_endproc
.LFE2057:
.size _Z9fetch_intv, .-_Z9fetch_intv
.globl _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
.type _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii, @function
_Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21matrix_multiplicationPKiS0_S0_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii, .-_Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
.globl _Z21matrix_multiplicationPKiS0_S0_Piii
.type _Z21matrix_multiplicationPKiS0_S0_Piii, @function
_Z21matrix_multiplicationPKiS0_S0_Piii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z21matrix_multiplicationPKiS0_S0_Piii, .-_Z21matrix_multiplicationPKiS0_S0_Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
call _Z9fetch_intv
movl %eax, %r14d
call _Z9fetch_intv
movl %eax, %ecx
movl %eax, 40(%rsp)
leal 2(%rax), %eax
imull %r14d, %eax
movl %eax, 44(%rsp)
movslq %r14d, %rsi
movq %rsi, 8(%rsp)
leaq 0(,%rsi,4), %rdi
movq %rdi, 24(%rsp)
movq %rdi, %r15
leal (%r14,%r14), %edx
subl %edx, %eax
cltq
movq %rax, 32(%rsp)
testl %ecx, %ecx
jle .L24
movl $0, %r12d
movslq %ecx, %rax
salq $2, %rax
movq %rax, 16(%rsp)
movl $0, %r13d
.L27:
call _Z9fetch_intv
movl %eax, (%r12)
testl %r14d, %r14d
jle .L25
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rcx
addq %rcx, %rax
leaq (%r15,%rax,4), %rbp
.L26:
call _Z9fetch_intv
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
.L25:
addq $4, %r12
movl 40(%rsp), %eax
addl %eax, %r13d
movq 16(%rsp), %rax
cmpq %rax, %r12
jne .L27
.L24:
testl %r14d, %r14d
jle .L28
movq 32(%rsp), %rsi
leaq (%r15,%rsi,4), %rbx
movq 8(%rsp), %rax
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L29:
call _Z9fetch_intv
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
.L28:
movslq 44(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movl $0, %edi
movq %rdi, %rsi
call cudaMemcpy@PLT
movl $512, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L30:
movl $2, %ecx
movq 24(%rsp), %r15
movq %r15, %rdx
movl $0, %esi
movl $0, %edi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L31
movl $0, %esi
movq %rsi, %rbx
addq %rsi, %r15
movq %r15, %rbp
leaq .LC0(%rip), %r12
.L32:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
.L31:
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %esi
movq %rsi, %rdi
call cudaFree@PLT
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl $0, %edi
movq 24(%rsp), %rcx
leaq (%rdi,%rcx), %rax
movq 32(%rsp), %rsi
leaq (%rcx,%rsi,4), %rdx
movl 40(%rsp), %r9d
movl %r14d, %r8d
movl $0, %esi
movq %rsi, %rcx
movq %rax, %rsi
call _Z52__device_stub__Z21matrix_multiplicationPKiS0_S0_PiiiPKiS0_S0_Piii
jmp .L30
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z21matrix_multiplicationPKiS0_S0_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21matrix_multiplicationPKiS0_S0_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii # -- Begin function _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.p2align 4, 0x90
.type _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii,@function
_Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii: # @_Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21matrix_multiplicationPKiS0_S0_Piii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii, .Lfunc_end0-_Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.cfi_endproc
# -- End function
.globl _Z9fetch_intv # -- Begin function _Z9fetch_intv
.p2align 4, 0x90
.type _Z9fetch_intv,@function
_Z9fetch_intv: # @_Z9fetch_intv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB1_2
# %bb.7: # in Loop: Header=BB1_1 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %ebx
.LBB1_8: # %getchar_unlocked.exit
# in Loop: Header=BB1_1 Depth=1
leal -58(%rbx), %eax
cmpb $-10, %al
jb .LBB1_1
jmp .LBB1_3
.LBB1_2: # in Loop: Header=BB1_1 Depth=1
callq __uflow
movl %eax, %ebx
jmp .LBB1_8
.LBB1_3: # %.preheader
leal -48(%rbx), %eax
xorl %r14d, %r14d
cmpb $9, %al
ja .LBB1_11
# %bb.4: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB1_6
# %bb.9: # in Loop: Header=BB1_5 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %eax
.LBB1_10: # %getchar_unlocked.exit11
# in Loop: Header=BB1_5 Depth=1
movzbl %bl, %ecx
leal (%r14,%r14,4), %edx
leal (%rcx,%rdx,2), %r14d
addl $-48, %r14d
leal -48(%rax), %ecx
movl %eax, %ebx
cmpb $10, %cl
jb .LBB1_5
jmp .LBB1_11
.LBB1_6: # in Loop: Header=BB1_5 Depth=1
callq __uflow
# kill: def $eax killed $eax def $rax
jmp .LBB1_10
.LBB1_11: # %._crit_edge
movl %r14d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9fetch_intv, .Lfunc_end1-_Z9fetch_intv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_2
# %bb.7: # in Loop: Header=BB2_1 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %ebx
.LBB2_8: # %getchar_unlocked.exit.i
# in Loop: Header=BB2_1 Depth=1
leal -58(%rbx), %eax
cmpb $-10, %al
jb .LBB2_1
jmp .LBB2_3
.LBB2_2: # in Loop: Header=BB2_1 Depth=1
callq __uflow
movl %eax, %ebx
jmp .LBB2_8
.LBB2_3: # %.preheader.i
leal -48(%rbx), %eax
xorl %r14d, %r14d
cmpb $9, %al
ja .LBB2_11
# %bb.4: # %.lr.ph.i.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_6
# %bb.9: # in Loop: Header=BB2_5 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %eax
.LBB2_10: # %getchar_unlocked.exit11.i
# in Loop: Header=BB2_5 Depth=1
movzbl %bl, %ecx
leal (%r14,%r14,4), %edx
leal (%rcx,%rdx,2), %r14d
addl $-48, %r14d
leal -48(%rax), %ecx
movl %eax, %ebx
cmpb $10, %cl
jb .LBB2_5
jmp .LBB2_11
.LBB2_6: # in Loop: Header=BB2_5 Depth=1
callq __uflow
# kill: def $eax killed $eax def $rax
jmp .LBB2_10
.LBB2_12: # in Loop: Header=BB2_11 Depth=1
callq __uflow
movl %eax, %ebx
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_12
# %bb.17: # in Loop: Header=BB2_11 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %ebx
.LBB2_18: # %getchar_unlocked.exit.i63
# in Loop: Header=BB2_11 Depth=1
leal -58(%rbx), %eax
cmpb $-10, %al
jb .LBB2_11
# %bb.13: # %.preheader.i64
leal -48(%rbx), %eax
xorl %r15d, %r15d
cmpb $9, %al
ja .LBB2_21
# %bb.14: # %.lr.ph.i66.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_15: # %.lr.ph.i66
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
jae .LBB2_16
# %bb.19: # in Loop: Header=BB2_15 Depth=1
leaq 1(%rax), %rcx
movq %rcx, 8(%rdi)
movzbl (%rax), %eax
.LBB2_20: # %getchar_unlocked.exit11.i70
# in Loop: Header=BB2_15 Depth=1
movzbl %bl, %ecx
leal (%r15,%r15,4), %edx
leal (%rcx,%rdx,2), %r15d
addl $-48, %r15d
leal -48(%rax), %ecx
movl %eax, %ebx
cmpb $10, %cl
jb .LBB2_15
jmp .LBB2_21
.LBB2_16: # in Loop: Header=BB2_15 Depth=1
callq __uflow
# kill: def $eax killed $eax def $rax
jmp .LBB2_20
.LBB2_21: # %_Z9fetch_intv.exit71
testl %r15d, %r15d
jg .LBB2_26
# %bb.22:
testl %r14d, %r14d
jg .LBB2_26
# %bb.23:
leal 2(%r15), %eax
imull %r14d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
leal 511(%r14), %eax
leal 1022(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_25
# %bb.24:
movl %r14d, 12(%rsp)
movl %r15d, 8(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 112(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21matrix_multiplicationPKiS0_S0_Piii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_25: # %._crit_edge
movslq %r14d, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipFree
callq hipFree
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_26:
.cfi_def_cfa_offset 176
callq _Z9fetch_intv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21matrix_multiplicationPKiS0_S0_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21matrix_multiplicationPKiS0_S0_Piii,@object # @_Z21matrix_multiplicationPKiS0_S0_Piii
.section .rodata,"a",@progbits
.globl _Z21matrix_multiplicationPKiS0_S0_Piii
.p2align 3, 0x0
_Z21matrix_multiplicationPKiS0_S0_Piii:
.quad _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.size _Z21matrix_multiplicationPKiS0_S0_Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21matrix_multiplicationPKiS0_S0_Piii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__matrix_multiplicationPKiS0_S0_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21matrix_multiplicationPKiS0_S0_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void add(int n, float *a, float *sum)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<n)
{
for (int j = 0; j < n; j++)
{
sum[i] = sum[i] + a[i*n + j];
}
}
} | code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x160], !P0 ; /* 0x0000580007007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00d0*/ LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.WIDE R2, R7, R6, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fd400078e0206 */
/*00f0*/ @!P0 BRA 0x8a0 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R9, -R0, c[0x0][0x160], RZ ; /* 0x0000580000097a10 */
/* 0x000fe20007ffe1ff */
/*0110*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0120*/ IMAD R5, R7, c[0x0][0x160], RZ ; /* 0x0000580007057a24 */
/* 0x000fe200078e02ff */
/*0130*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0140*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*0150*/ IMAD.WIDE R4, R5, R6, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fd800078e0206 */
/*0160*/ @!P0 BRA 0x760 ; /* 0x000005f000008947 */
/* 0x001fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x530 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x02cfca0000000000 */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*01e0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*01f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0200*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0210*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0240*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0250*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0270*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e24000c1e1900 */
/*0280*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e64000c1e1900 */
/*02b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*02d0*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*02f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0300*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0310*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0320*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0330*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x000e24000c1e1900 */
/*0340*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0360*/ LDG.E R10, [R4.64+0x24] ; /* 0x00002404040a7981 */
/* 0x000e64000c1e1900 */
/*0370*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*0380*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*03b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R10, [R4.64+0x2c] ; /* 0x00002c04040a7981 */
/* 0x000ee4000c1e1900 */
/*03d0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*03e0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003004040a7981 */
/* 0x000ee4000c1e1900 */
/*0400*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */
/* 0x008fca0000000000 */
/*0410*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e8000c101904 */
/*0420*/ LDG.E R10, [R4.64+0x34] ; /* 0x00003404040a7981 */
/* 0x000e24000c1e1900 */
/*0430*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */
/* 0x001fca0000000000 */
/*0440*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0450*/ LDG.E R10, [R4.64+0x38] ; /* 0x00003804040a7981 */
/* 0x000e62000c1e1900 */
/*0460*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fe20007ffe0ff */
/*0470*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x002fca0000000000 */
/*0480*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0490*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c04040a7981 */
/* 0x000f22000c1e1900 */
/*04a0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*04b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */
/* 0x010fe20000000000 */
/*04d0*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x000fc80007f5e0ff */
/*04e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e2000c101904 */
/*04f0*/ IMAD.X R17, RZ, RZ, R5, P2 ; /* 0x000000ffff117224 */
/* 0x004fe200010e0605 */
/*0500*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc80000000f00 */
/*0510*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe20000000f00 */
/*0520*/ @P1 BRA 0x1b0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0530*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0540*/ @!P1 BRA 0x740 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0560*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x02cfca0000000000 */
/*0570*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0580*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*0590*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*05a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*05c0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*05d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea4000c1e1900 */
/*05f0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x004fca0000000000 */
/*0600*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*0610*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000ee4000c1e1900 */
/*0620*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */
/* 0x008fca0000000000 */
/*0630*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e8000c101904 */
/*0640*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e24000c1e1900 */
/*0650*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */
/* 0x001fca0000000000 */
/*0660*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0670*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000e64000c1e1900 */
/*0680*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x002fca0000000000 */
/*0690*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*06a0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f22000c1e1900 */
/*06b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*06c0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */
/* 0x010fe20000000000 */
/*06f0*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0700*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e2000c101904 */
/*0710*/ IMAD.X R17, RZ, RZ, R5, P1 ; /* 0x000000ffff117224 */
/* 0x004fe200008e0605 */
/*0720*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc80000000f00 */
/*0730*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe40000000f00 */
/*0740*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0750*/ @!P0 BRA 0x8a0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0770*/ FADD R13, R10, R11 ; /* 0x0000000b0a0d7221 */
/* 0x02cfca0000000000 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0790*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*07b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*07c0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x004fca0000000000 */
/*07f0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0800*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0810*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0820*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0830*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x004fe20000000000 */
/*0840*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f3e0ff */
/*0850*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e2000c101904 */
/*0860*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x001fe200008e0605 */
/*0870*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc80000000f00 */
/*0880*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe20000000f00 */
/*0890*/ @P0 BRA 0x760 ; /* 0xfffffec000000947 */
/* 0x002fea000383ffff */
/*08a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*08d0*/ IMAD R7, R7, c[0x0][0x160], R8 ; /* 0x0000580007077a24 */
/* 0x000fc800078e0208 */
/*08e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e0206 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0900*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x000fca0000000f00 */
/*0910*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0930*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0950*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0960*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x026fca0000000000 */
/*0970*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003ea000c101904 */
/*0980*/ @P0 BRA 0x8f0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void add(int n, float *a, float *sum)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<n)
{
for (int j = 0; j < n; j++)
{
sum[i] = sum[i] + a[i*n + j];
}
}
} | .file "tmpxft_0008ed0b_00000000-6_MatrixToVectorAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void add(int n, float *a, float *sum)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<n)
{
for (int j = 0; j < n; j++)
{
sum[i] = sum[i] + a[i*n + j];
}
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *a, float *sum)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<n)
{
for (int j = 0; j < n; j++)
{
sum[i] = sum[i] + a[i*n + j];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *a, float *sum)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<n)
{
for (int j = 0; j < n; j++)
{
sum[i] = sum[i] + a[i*n + j];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mul_lo_u32 v2, v2, s2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
global_load_b32 v4, v[0:1], off
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[0:1], v4, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *a, float *sum)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<n)
{
for (int j = 0; j < n; j++)
{
sum[i] = sum[i] + a[i*n + j];
}
}
} | .text
.file "MatrixToVectorAddition.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x160], !P0 ; /* 0x0000580007007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00d0*/ LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.WIDE R2, R7, R6, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fd400078e0206 */
/*00f0*/ @!P0 BRA 0x8a0 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R9, -R0, c[0x0][0x160], RZ ; /* 0x0000580000097a10 */
/* 0x000fe20007ffe1ff */
/*0110*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0120*/ IMAD R5, R7, c[0x0][0x160], RZ ; /* 0x0000580007057a24 */
/* 0x000fe200078e02ff */
/*0130*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0140*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f04270 */
/*0150*/ IMAD.WIDE R4, R5, R6, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fd800078e0206 */
/*0160*/ @!P0 BRA 0x760 ; /* 0x000005f000008947 */
/* 0x001fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x530 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x02cfca0000000000 */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*01e0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*01f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0200*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0210*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0240*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0250*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0270*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e24000c1e1900 */
/*0280*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e64000c1e1900 */
/*02b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*02d0*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*02f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0300*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0310*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0320*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0330*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x000e24000c1e1900 */
/*0340*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0360*/ LDG.E R10, [R4.64+0x24] ; /* 0x00002404040a7981 */
/* 0x000e64000c1e1900 */
/*0370*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*0380*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*03b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R10, [R4.64+0x2c] ; /* 0x00002c04040a7981 */
/* 0x000ee4000c1e1900 */
/*03d0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*03e0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003004040a7981 */
/* 0x000ee4000c1e1900 */
/*0400*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */
/* 0x008fca0000000000 */
/*0410*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e8000c101904 */
/*0420*/ LDG.E R10, [R4.64+0x34] ; /* 0x00003404040a7981 */
/* 0x000e24000c1e1900 */
/*0430*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */
/* 0x001fca0000000000 */
/*0440*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0450*/ LDG.E R10, [R4.64+0x38] ; /* 0x00003804040a7981 */
/* 0x000e62000c1e1900 */
/*0460*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fe20007ffe0ff */
/*0470*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x002fca0000000000 */
/*0480*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0490*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c04040a7981 */
/* 0x000f22000c1e1900 */
/*04a0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*04b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */
/* 0x010fe20000000000 */
/*04d0*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x000fc80007f5e0ff */
/*04e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e2000c101904 */
/*04f0*/ IMAD.X R17, RZ, RZ, R5, P2 ; /* 0x000000ffff117224 */
/* 0x004fe200010e0605 */
/*0500*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc80000000f00 */
/*0510*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe20000000f00 */
/*0520*/ @P1 BRA 0x1b0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0530*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0540*/ @!P1 BRA 0x740 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0560*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x02cfca0000000000 */
/*0570*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0580*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*0590*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*05a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*05c0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*05d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea4000c1e1900 */
/*05f0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x004fca0000000000 */
/*0600*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*0610*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000ee4000c1e1900 */
/*0620*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */
/* 0x008fca0000000000 */
/*0630*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e8000c101904 */
/*0640*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e24000c1e1900 */
/*0650*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */
/* 0x001fca0000000000 */
/*0660*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0670*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000e64000c1e1900 */
/*0680*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x002fca0000000000 */
/*0690*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*06a0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f22000c1e1900 */
/*06b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*06c0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */
/* 0x010fe20000000000 */
/*06f0*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0700*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e2000c101904 */
/*0710*/ IMAD.X R17, RZ, RZ, R5, P1 ; /* 0x000000ffff117224 */
/* 0x004fe200008e0605 */
/*0720*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc80000000f00 */
/*0730*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe40000000f00 */
/*0740*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0750*/ @!P0 BRA 0x8a0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0770*/ FADD R13, R10, R11 ; /* 0x0000000b0a0d7221 */
/* 0x02cfca0000000000 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0790*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*07b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*07c0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x004fca0000000000 */
/*07f0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0800*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0810*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0820*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0830*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x004fe20000000000 */
/*0840*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f3e0ff */
/*0850*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e2000c101904 */
/*0860*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x001fe200008e0605 */
/*0870*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc80000000f00 */
/*0880*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe20000000f00 */
/*0890*/ @P0 BRA 0x760 ; /* 0xfffffec000000947 */
/* 0x002fea000383ffff */
/*08a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*08d0*/ IMAD R7, R7, c[0x0][0x160], R8 ; /* 0x0000580007077a24 */
/* 0x000fc800078e0208 */
/*08e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e0206 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0900*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x000fca0000000f00 */
/*0910*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0930*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0950*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0960*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x026fca0000000000 */
/*0970*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003ea000c101904 */
/*0980*/ @P0 BRA 0x8f0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mul_lo_u32 v2, v2, s2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
global_load_b32 v4, v[0:1], off
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[0:1], v4, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008ed0b_00000000-6_MatrixToVectorAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixToVectorAddition.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__host__ __device__ int run_on_cpu_or_gpu() {
return 1;
}
__global__ void run_on_gpu() {
printf("run_on_cpu_or_gpu GPU: %d\n", run_on_cpu_or_gpu());
}
int main() {
printf("run_on_cpu_or_gpu CPU: %d\n", run_on_cpu_or_gpu());
run_on_gpu<<<1, 1>>>();
printf("will end\n");
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z10run_on_gpuv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100800 */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000640000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fcc00000e06ff */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__host__ __device__ int run_on_cpu_or_gpu() {
return 1;
}
__global__ void run_on_gpu() {
printf("run_on_cpu_or_gpu GPU: %d\n", run_on_cpu_or_gpu());
}
int main() {
printf("run_on_cpu_or_gpu CPU: %d\n", run_on_cpu_or_gpu());
run_on_gpu<<<1, 1>>>();
printf("will end\n");
cudaDeviceReset();
return 0;
} | .file "tmpxft_000dd35a_00000000-6_run_gpu_or_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17run_on_cpu_or_gpuv
.type _Z17run_on_cpu_or_gpuv, @function
_Z17run_on_cpu_or_gpuv:
.LFB2057:
.cfi_startproc
endbr64
movl $1, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z17run_on_cpu_or_gpuv, .-_Z17run_on_cpu_or_gpuv
.globl _Z29__device_stub__Z10run_on_gpuvv
.type _Z29__device_stub__Z10run_on_gpuvv, @function
_Z29__device_stub__Z10run_on_gpuvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10run_on_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z10run_on_gpuvv, .-_Z29__device_stub__Z10run_on_gpuvv
.globl _Z10run_on_gpuv
.type _Z10run_on_gpuv, @function
_Z10run_on_gpuv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10run_on_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10run_on_gpuv, .-_Z10run_on_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "run_on_cpu_or_gpu CPU: %d\n"
.LC1:
.string "will end\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L13:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z29__device_stub__Z10run_on_gpuvv
jmp .L13
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10run_on_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10run_on_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__host__ __device__ int run_on_cpu_or_gpu() {
return 1;
}
__global__ void run_on_gpu() {
printf("run_on_cpu_or_gpu GPU: %d\n", run_on_cpu_or_gpu());
}
int main() {
printf("run_on_cpu_or_gpu CPU: %d\n", run_on_cpu_or_gpu());
run_on_gpu<<<1, 1>>>();
printf("will end\n");
cudaDeviceReset();
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__host__ __device__ int run_on_cpu_or_gpu() {
return 1;
}
__global__ void run_on_gpu() {
printf("run_on_cpu_or_gpu GPU: %d\n", run_on_cpu_or_gpu());
}
int main() {
printf("run_on_cpu_or_gpu CPU: %d\n", run_on_cpu_or_gpu());
run_on_gpu<<<1, 1>>>();
printf("will end\n");
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__host__ __device__ int run_on_cpu_or_gpu() {
return 1;
}
__global__ void run_on_gpu() {
printf("run_on_cpu_or_gpu GPU: %d\n", run_on_cpu_or_gpu());
}
int main() {
printf("run_on_cpu_or_gpu CPU: %d\n", run_on_cpu_or_gpu());
run_on_gpu<<<1, 1>>>();
printf("will end\n");
hipDeviceReset();
return 0;
} | .text
.file "run_gpu_or_cpu.hip"
.globl _Z17run_on_cpu_or_gpuv # -- Begin function _Z17run_on_cpu_or_gpuv
.p2align 4, 0x90
.type _Z17run_on_cpu_or_gpuv,@function
_Z17run_on_cpu_or_gpuv: # @_Z17run_on_cpu_or_gpuv
.cfi_startproc
# %bb.0:
movl $1, %eax
retq
.Lfunc_end0:
.size _Z17run_on_cpu_or_gpuv, .Lfunc_end0-_Z17run_on_cpu_or_gpuv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__run_on_gpuv # -- Begin function _Z25__device_stub__run_on_gpuv
.p2align 4, 0x90
.type _Z25__device_stub__run_on_gpuv,@function
_Z25__device_stub__run_on_gpuv: # @_Z25__device_stub__run_on_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10run_on_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z25__device_stub__run_on_gpuv, .Lfunc_end1-_Z25__device_stub__run_on_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10run_on_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10run_on_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10run_on_gpuv,@object # @_Z10run_on_gpuv
.section .rodata,"a",@progbits
.globl _Z10run_on_gpuv
.p2align 3, 0x0
_Z10run_on_gpuv:
.quad _Z25__device_stub__run_on_gpuv
.size _Z10run_on_gpuv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "run_on_cpu_or_gpu CPU: %d\n"
.size .L.str, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10run_on_gpuv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "will end"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__run_on_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10run_on_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dd35a_00000000-6_run_gpu_or_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17run_on_cpu_or_gpuv
.type _Z17run_on_cpu_or_gpuv, @function
_Z17run_on_cpu_or_gpuv:
.LFB2057:
.cfi_startproc
endbr64
movl $1, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z17run_on_cpu_or_gpuv, .-_Z17run_on_cpu_or_gpuv
.globl _Z29__device_stub__Z10run_on_gpuvv
.type _Z29__device_stub__Z10run_on_gpuvv, @function
_Z29__device_stub__Z10run_on_gpuvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10run_on_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z10run_on_gpuvv, .-_Z29__device_stub__Z10run_on_gpuvv
.globl _Z10run_on_gpuv
.type _Z10run_on_gpuv, @function
_Z10run_on_gpuv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10run_on_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10run_on_gpuv, .-_Z10run_on_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "run_on_cpu_or_gpu CPU: %d\n"
.LC1:
.string "will end\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L13:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z29__device_stub__Z10run_on_gpuvv
jmp .L13
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10run_on_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10run_on_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "run_gpu_or_cpu.hip"
.globl _Z17run_on_cpu_or_gpuv # -- Begin function _Z17run_on_cpu_or_gpuv
.p2align 4, 0x90
.type _Z17run_on_cpu_or_gpuv,@function
_Z17run_on_cpu_or_gpuv: # @_Z17run_on_cpu_or_gpuv
.cfi_startproc
# %bb.0:
movl $1, %eax
retq
.Lfunc_end0:
.size _Z17run_on_cpu_or_gpuv, .Lfunc_end0-_Z17run_on_cpu_or_gpuv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__run_on_gpuv # -- Begin function _Z25__device_stub__run_on_gpuv
.p2align 4, 0x90
.type _Z25__device_stub__run_on_gpuv,@function
_Z25__device_stub__run_on_gpuv: # @_Z25__device_stub__run_on_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10run_on_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z25__device_stub__run_on_gpuv, .Lfunc_end1-_Z25__device_stub__run_on_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10run_on_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10run_on_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10run_on_gpuv,@object # @_Z10run_on_gpuv
.section .rodata,"a",@progbits
.globl _Z10run_on_gpuv
.p2align 3, 0x0
_Z10run_on_gpuv:
.quad _Z25__device_stub__run_on_gpuv
.size _Z10run_on_gpuv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "run_on_cpu_or_gpu CPU: %d\n"
.size .L.str, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10run_on_gpuv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "will end"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__run_on_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10run_on_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#ifdef _WIN32
# define IMPORT __declspec(dllimport)
#else
# define IMPORT
#endif
int static_cuda11_func(int);
IMPORT int shared_cuda11_func(int);
void test_functions()
{
static_cuda11_func(int(42));
shared_cuda11_func(int(42));
}
int main(int argc, char** argv)
{
test_functions();
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#ifdef _WIN32
# define IMPORT __declspec(dllimport)
#else
# define IMPORT
#endif
int static_cuda11_func(int);
IMPORT int shared_cuda11_func(int);
void test_functions()
{
static_cuda11_func(int(42));
shared_cuda11_func(int(42));
}
int main(int argc, char** argv)
{
test_functions();
return 0;
} | .file "tmpxft_0016fa6e_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14test_functionsv
.type _Z14test_functionsv, @function
_Z14test_functionsv:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $42, %edi
call _Z18static_cuda11_funci@PLT
movl $42, %edi
call _Z18shared_cuda11_funci@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z14test_functionsv, .-_Z14test_functionsv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z14test_functionsv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#ifdef _WIN32
# define IMPORT __declspec(dllimport)
#else
# define IMPORT
#endif
int static_cuda11_func(int);
IMPORT int shared_cuda11_func(int);
void test_functions()
{
static_cuda11_func(int(42));
shared_cuda11_func(int(42));
}
int main(int argc, char** argv)
{
test_functions();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#ifdef _WIN32
# define IMPORT __declspec(dllimport)
#else
# define IMPORT
#endif
int static_cuda11_func(int);
IMPORT int shared_cuda11_func(int);
void test_functions()
{
static_cuda11_func(int(42));
shared_cuda11_func(int(42));
}
int main(int argc, char** argv)
{
test_functions();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#ifdef _WIN32
# define IMPORT __declspec(dllimport)
#else
# define IMPORT
#endif
int static_cuda11_func(int);
IMPORT int shared_cuda11_func(int);
void test_functions()
{
static_cuda11_func(int(42));
shared_cuda11_func(int(42));
}
int main(int argc, char** argv)
{
test_functions();
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#ifdef _WIN32
# define IMPORT __declspec(dllimport)
#else
# define IMPORT
#endif
int static_cuda11_func(int);
IMPORT int shared_cuda11_func(int);
void test_functions()
{
static_cuda11_func(int(42));
shared_cuda11_func(int(42));
}
int main(int argc, char** argv)
{
test_functions();
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14test_functionsv # -- Begin function _Z14test_functionsv
.p2align 4, 0x90
.type _Z14test_functionsv,@function
_Z14test_functionsv: # @_Z14test_functionsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $42, %edi
callq _Z18static_cuda11_funci
movl $42, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp _Z18shared_cuda11_funci # TAILCALL
.Lfunc_end0:
.size _Z14test_functionsv, .Lfunc_end0-_Z14test_functionsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $42, %edi
callq _Z18static_cuda11_funci
movl $42, %edi
callq _Z18shared_cuda11_funci
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016fa6e_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14test_functionsv
.type _Z14test_functionsv, @function
_Z14test_functionsv:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $42, %edi
call _Z18static_cuda11_funci@PLT
movl $42, %edi
call _Z18shared_cuda11_funci@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z14test_functionsv, .-_Z14test_functionsv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z14test_functionsv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14test_functionsv # -- Begin function _Z14test_functionsv
.p2align 4, 0x90
.type _Z14test_functionsv,@function
_Z14test_functionsv: # @_Z14test_functionsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $42, %edi
callq _Z18static_cuda11_funci
movl $42, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp _Z18shared_cuda11_funci # TAILCALL
.Lfunc_end0:
.size _Z14test_functionsv, .Lfunc_end0-_Z14test_functionsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $42, %edi
callq _Z18static_cuda11_funci
movl $42, %edi
callq _Z18shared_cuda11_funci
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <stdlib.h>
#define N (1<<22)
#define BLOCK_SIZE 128
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
__global__ void reduxKernel(int* v, int n, int* res){
int tx = threadIdx.x;
int idx = blockIdx.x * (BLOCK_SIZE*2) + tx;
__shared__ int vs[BLOCK_SIZE*2];
// all threads execute the following, as the size of the shared memory is
// 2x the number of threads
int reg = idx < n ? v[idx] : 0;
if( idx + BLOCK_SIZE < n ){
reg += v[idx + BLOCK_SIZE];
}
//vs[tx] = v[idx] + v[idx + BLOCK_SIZE];
vs[tx] = reg;
__syncthreads();
if( BLOCK_SIZE >= 512 ){
if( tx < 256 ){ vs[tx] = reg = reg + vs[tx + 256]; __syncthreads(); }
}
if( BLOCK_SIZE >= 256 ){
if( tx < 128 ){ vs[tx] = reg = reg + vs[tx + 128]; __syncthreads(); }
}
if( BLOCK_SIZE >= 128 ){
if( tx < 64 ){ vs[tx] = reg = reg + vs[tx + 64]; __syncthreads(); }
}
// for( int bs = BLOCK_SIZE/2 ; bs > 32; bs >>= 1 ){
// if( tx < bs ){
// //accumulating on the register var "reg" saves a read
// //from shared memory. Instead of doing vs[tx] += vs[tx + bs],
// //we just accum on the reg and write it back to shared memory
// vs[tx] = reg = reg + vs[tx + bs];
// }
// __syncthreads();
// }
if( tx < 32 ){ //for the last wrap. Threads within a wrap don't need synchronize
volatile int* synchdShared = vs; //so that the compiler doesn't reorder
// in case the block size were less than 32 to begin with
if( BLOCK_SIZE >= 64 ){
// means we can "reach out" fully 32 positions to the right of the thread
// look at the general loop to work out why
synchdShared[tx] = reg = reg + synchdShared[tx + 32];
}
//and of course we are gonna fall-through
if( BLOCK_SIZE >= 32 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 16];
}
if( BLOCK_SIZE >= 16 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 8];
}
if( BLOCK_SIZE >= 8 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 4];
}
if( BLOCK_SIZE >= 4 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 2];
}
if( BLOCK_SIZE >= 2 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 1];
}
}
//interesting: without this if, the kernel execution takes 5x the time! Probably
//due the memory conflicts created by _ALL_ the threads trying to write to the same
//memory location "at once"
if(tx == 0){
res[blockIdx.x] = vs[0];
}
}
int hostRedux(int* v, int n){
int res = 0;
for(int i=0; i < n; i++){
res += v[i];
}
return res;
}
void deviceRedux(int* v, int n, int* res){
// reserve memory on device
int *vd;
int *resd;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float time;
const int numBlocks = (N/BLOCK_SIZE)/2;
HANDLE_ERROR( cudaMalloc((void**)&vd, n*sizeof(int)) );
HANDLE_ERROR( cudaMalloc((void**)&resd, numBlocks*sizeof(int)) );
cudaEventRecord( start, 0 );
// transfer v to vd
HANDLE_ERROR( cudaMemcpy(vd, v, n*sizeof(int), cudaMemcpyHostToDevice) );
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("memcpy in time: %f ms\n", time);
cudaEventRecord( start, 0 );
// invoke kernel
reduxKernel<<<numBlocks,BLOCK_SIZE>>>(vd,n,resd);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("kernel time: %f ms. ", time);
printf("Bandwidth: %f GB/s\n", (N*sizeof(int)/1e6)/time);
cudaEventRecord( start, 0 );
// copy results back to host
HANDLE_ERROR( cudaMemcpy(res, resd, numBlocks*sizeof(int), cudaMemcpyDeviceToHost) );
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("memcpy out time: %f ms\n", time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
//free vd
cudaFree(vd);
cudaFree(resd);
}
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
int
timeval_subtract (struct timeval* result, struct timeval*x, struct timeval*y)
{
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (x->tv_usec - y->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result->tv_sec = x->tv_sec - y->tv_sec;
result->tv_usec = x->tv_usec - y->tv_usec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
int main(){
int* v = (int*)malloc( sizeof(int) * N);
for(int i=0; i < N; i++){
v[i] = rand() % 10;
//v[i] = i;
}
int h;
struct timeval tv_start;
struct timeval tv_stop;
struct timeval tv_diff;
gettimeofday(&tv_start, 0);
h=hostRedux(v,N);
gettimeofday(&tv_stop, 0);
timeval_subtract(&tv_diff, &tv_stop, &tv_start);
printf("host: %d\n", h);
float msdiff = tv_diff.tv_sec*1000 + tv_diff.tv_usec/1000.0;
printf("CPU time: %.3f ms\n", msdiff);
const int numBlocks = (N/BLOCK_SIZE)/2;
int *res = (int*)malloc( sizeof(int) * numBlocks);
int d;
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord( start, 0 );
deviceRedux(v,N, res);
d=0;
for(int i=0; i < numBlocks; i++){
// printf("%d\n", res[i]);
d+=res[i];
}
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("CUDA time: %f ms\n", time);
printf("device: %d\n", d);
free(v);
free(res);
return !(h==d);
} | code for sm_80
Function : _Z11reduxKernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R6, 0x100, R9 ; /* 0x0000010006027824 */
/* 0x001fca00078e0209 */
/*0060*/ IADD3 R0, R2.reuse, 0x80, RZ ; /* 0x0000008002007810 */
/* 0x040fe40007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe20003f06270 */
/*0080*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e020b */
/*0090*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc60003f26270 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd000078e00ff */
/*00b0*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ @!P1 LDG.E R5, [R2.64+0x200] ; /* 0x0002000402059981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ISETP.GT.AND P0, PT, R9.reuse, 0x3f, PT ; /* 0x0000003f0900780c */
/* 0x040fe40003f04270 */
/*00e0*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*00f0*/ @!P1 IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100009824 */
/* 0x004fe200078e0205 */
/*0100*/ ISETP.GT.AND P1, PT, R9, 0x1f, PT ; /* 0x0000001f0900780c */
/* 0x000fc80003f24270 */
/*0110*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x000fe80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0140*/ BSSY B0, 0x2d0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0150*/ @!P0 LDS R5, [R9.X4+0x100] ; /* 0x0001000009058984 */
/* 0x000e240000004800 */
/*0160*/ @!P0 IADD3 R0, R0, R5, RZ ; /* 0x0000000500008210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P0 STS [R9.X4], R0 ; /* 0x0000000009008388 */
/* 0x0001e80000004800 */
/*0180*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0190*/ @P1 BRA 0x2c0 ; /* 0x0000012000001947 */
/* 0x000fea0003800000 */
/*01a0*/ LDS R3, [R9.X4+0x80] ; /* 0x0000800009037984 */
/* 0x001e240000004800 */
/*01b0*/ IMAD.IADD R3, R3, 0x1, R0 ; /* 0x0000000103037824 */
/* 0x001fca00078e0200 */
/*01c0*/ STS [R9.X4], R3 ; /* 0x0000000309007388 */
/* 0x000fe80000004800 */
/*01d0*/ LDS R0, [R9.X4+0x40] ; /* 0x0000400009007984 */
/* 0x000e240000004800 */
/*01e0*/ IADD3 R0, R3, R0, RZ ; /* 0x0000000003007210 */
/* 0x001fca0007ffe0ff */
/*01f0*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x000fe80000004800 */
/*0200*/ LDS R5, [R9.X4+0x20] ; /* 0x0000200009057984 */
/* 0x000e240000004800 */
/*0210*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x001fca00078e0205 */
/*0220*/ STS [R9.X4], R5 ; /* 0x0000000509007388 */
/* 0x000fe80000004800 */
/*0230*/ LDS R2, [R9.X4+0x10] ; /* 0x0000100009027984 */
/* 0x000e240000004800 */
/*0240*/ IADD3 R2, R5, R2, RZ ; /* 0x0000000205027210 */
/* 0x001fca0007ffe0ff */
/*0250*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x000fe80000004800 */
/*0260*/ LDS R7, [R9.X4+0x8] ; /* 0x0000080009077984 */
/* 0x000e240000004800 */
/*0270*/ IMAD.IADD R7, R2, 0x1, R7 ; /* 0x0000000102077824 */
/* 0x001fca00078e0207 */
/*0280*/ STS [R9.X4], R7 ; /* 0x0000000709007388 */
/* 0x000fe80000004800 */
/*0290*/ LDS R4, [R9.X4+0x4] ; /* 0x0000040009047984 */
/* 0x000e240000004800 */
/*02a0*/ IADD3 R4, R7, R4, RZ ; /* 0x0000000407047210 */
/* 0x001fca0007ffe0ff */
/*02b0*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0001e40000004800 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02d0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*02e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R11, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fe200078e000b */
/*0300*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0310*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <stdlib.h>
#define N (1<<22)
#define BLOCK_SIZE 128
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
__global__ void reduxKernel(int* v, int n, int* res){
int tx = threadIdx.x;
int idx = blockIdx.x * (BLOCK_SIZE*2) + tx;
__shared__ int vs[BLOCK_SIZE*2];
// all threads execute the following, as the size of the shared memory is
// 2x the number of threads
int reg = idx < n ? v[idx] : 0;
if( idx + BLOCK_SIZE < n ){
reg += v[idx + BLOCK_SIZE];
}
//vs[tx] = v[idx] + v[idx + BLOCK_SIZE];
vs[tx] = reg;
__syncthreads();
if( BLOCK_SIZE >= 512 ){
if( tx < 256 ){ vs[tx] = reg = reg + vs[tx + 256]; __syncthreads(); }
}
if( BLOCK_SIZE >= 256 ){
if( tx < 128 ){ vs[tx] = reg = reg + vs[tx + 128]; __syncthreads(); }
}
if( BLOCK_SIZE >= 128 ){
if( tx < 64 ){ vs[tx] = reg = reg + vs[tx + 64]; __syncthreads(); }
}
// for( int bs = BLOCK_SIZE/2 ; bs > 32; bs >>= 1 ){
// if( tx < bs ){
// //accumulating on the register var "reg" saves a read
// //from shared memory. Instead of doing vs[tx] += vs[tx + bs],
// //we just accum on the reg and write it back to shared memory
// vs[tx] = reg = reg + vs[tx + bs];
// }
// __syncthreads();
// }
if( tx < 32 ){ //for the last wrap. Threads within a wrap don't need synchronize
volatile int* synchdShared = vs; //so that the compiler doesn't reorder
// in case the block size were less than 32 to begin with
if( BLOCK_SIZE >= 64 ){
// means we can "reach out" fully 32 positions to the right of the thread
// look at the general loop to work out why
synchdShared[tx] = reg = reg + synchdShared[tx + 32];
}
//and of course we are gonna fall-through
if( BLOCK_SIZE >= 32 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 16];
}
if( BLOCK_SIZE >= 16 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 8];
}
if( BLOCK_SIZE >= 8 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 4];
}
if( BLOCK_SIZE >= 4 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 2];
}
if( BLOCK_SIZE >= 2 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 1];
}
}
//interesting: without this if, the kernel execution takes 5x the time! Probably
//due the memory conflicts created by _ALL_ the threads trying to write to the same
//memory location "at once"
if(tx == 0){
res[blockIdx.x] = vs[0];
}
}
int hostRedux(int* v, int n){
int res = 0;
for(int i=0; i < n; i++){
res += v[i];
}
return res;
}
void deviceRedux(int* v, int n, int* res){
// reserve memory on device
int *vd;
int *resd;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float time;
const int numBlocks = (N/BLOCK_SIZE)/2;
HANDLE_ERROR( cudaMalloc((void**)&vd, n*sizeof(int)) );
HANDLE_ERROR( cudaMalloc((void**)&resd, numBlocks*sizeof(int)) );
cudaEventRecord( start, 0 );
// transfer v to vd
HANDLE_ERROR( cudaMemcpy(vd, v, n*sizeof(int), cudaMemcpyHostToDevice) );
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("memcpy in time: %f ms\n", time);
cudaEventRecord( start, 0 );
// invoke kernel
reduxKernel<<<numBlocks,BLOCK_SIZE>>>(vd,n,resd);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("kernel time: %f ms. ", time);
printf("Bandwidth: %f GB/s\n", (N*sizeof(int)/1e6)/time);
cudaEventRecord( start, 0 );
// copy results back to host
HANDLE_ERROR( cudaMemcpy(res, resd, numBlocks*sizeof(int), cudaMemcpyDeviceToHost) );
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("memcpy out time: %f ms\n", time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
//free vd
cudaFree(vd);
cudaFree(resd);
}
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
int
timeval_subtract (struct timeval* result, struct timeval*x, struct timeval*y)
{
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (x->tv_usec - y->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result->tv_sec = x->tv_sec - y->tv_sec;
result->tv_usec = x->tv_usec - y->tv_usec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
int main(){
int* v = (int*)malloc( sizeof(int) * N);
for(int i=0; i < N; i++){
v[i] = rand() % 10;
//v[i] = i;
}
int h;
struct timeval tv_start;
struct timeval tv_stop;
struct timeval tv_diff;
gettimeofday(&tv_start, 0);
h=hostRedux(v,N);
gettimeofday(&tv_stop, 0);
timeval_subtract(&tv_diff, &tv_stop, &tv_start);
printf("host: %d\n", h);
float msdiff = tv_diff.tv_sec*1000 + tv_diff.tv_usec/1000.0;
printf("CPU time: %.3f ms\n", msdiff);
const int numBlocks = (N/BLOCK_SIZE)/2;
int *res = (int*)malloc( sizeof(int) * numBlocks);
int d;
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord( start, 0 );
deviceRedux(v,N, res);
d=0;
for(int i=0; i < numBlocks; i++){
// printf("%d\n", res[i]);
d+=res[i];
}
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("CUDA time: %f ms\n", time);
printf("device: %d\n", d);
free(v);
free(res);
return !(h==d);
} | .file "tmpxft_0009d90b_00000000-6_6.1.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9hostReduxPii
.type _Z9hostReduxPii, @function
_Z9hostReduxPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl $0, %edx
.L11:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L11
.L9:
movl %edx, %eax
ret
.L12:
movl $0, %edx
jmp .L9
.cfi_endproc
.LFE2058:
.size _Z9hostReduxPii, .-_Z9hostReduxPii
.globl _Z16timeval_subtractP7timevalS0_S0_
.type _Z16timeval_subtractP7timevalS0_S0_, @function
_Z16timeval_subtractP7timevalS0_S0_:
.LFB2060:
.cfi_startproc
endbr64
movq %rdi, %r8
movq %rdx, %rcx
movq 8(%rsi), %rax
movq 8(%rdx), %rdi
cmpq %rdi, %rax
jge .L15
movq %rdi, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
addl $1, %edx
imull $1000000, %edx, %eax
cltq
subq %rax, %rdi
movq %rdi, 8(%rcx)
movslq %edx, %rdx
addq %rdx, (%rcx)
.L15:
movq 8(%rcx), %r9
movq 8(%rsi), %rdi
subq %r9, %rdi
cmpq $1000000, %rdi
jle .L16
movabsq $4835703278458516699, %rdx
movq %rdi, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %rdi
subq %rdi, %rdx
imull $1000000, %edx, %eax
cltq
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rdx
subq %rdx, (%rcx)
.L16:
movq (%rsi), %rax
subq (%rcx), %rax
movq %rax, (%r8)
movq 8(%rsi), %rax
subq 8(%rcx), %rax
movq %rax, 8(%r8)
movq (%rcx), %rax
cmpq %rax, (%rsi)
setl %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z16timeval_subtractP7timevalS0_S0_, .-_Z16timeval_subtractP7timevalS0_S0_
.globl _Z34__device_stub__Z11reduxKernelPiiS_PiiS_
.type _Z34__device_stub__Z11reduxKernelPiiS_PiiS_, @function
_Z34__device_stub__Z11reduxKernelPiiS_PiiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11reduxKernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z11reduxKernelPiiS_PiiS_, .-_Z34__device_stub__Z11reduxKernelPiiS_PiiS_
.globl _Z11reduxKernelPiiS_
.type _Z11reduxKernelPiiS_, @function
_Z11reduxKernelPiiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11reduxKernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11reduxKernelPiiS_, .-_Z11reduxKernelPiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dgquintas/my-code-samples/master/cuda/ProgrammingMassivelyParallelProcessors/ch6/6.1.cu"
.section .rodata.str1.1
.LC2:
.string "memcpy in time: %f ms\n"
.LC3:
.string "kernel time: %f ms. "
.LC5:
.string "Bandwidth: %f GB/s\n"
.LC6:
.string "memcpy out time: %f ms\n"
.text
.globl _Z11deviceReduxPiiS_
.type _Z11deviceReduxPiiS_, @function
_Z11deviceReduxPiiS_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movl %esi, %ebp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebp, %rbx
salq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $117, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $118, %edx
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $122, %edx
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $16384, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L26:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rbx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
movsd .LC4(%rip), %xmm0
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $65536, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $144, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 24(%rsp), %rdx
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11reduxKernelPiiS_PiiS_
jmp .L26
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z11deviceReduxPiiS_, .-_Z11deviceReduxPiiS_
.section .rodata.str1.1
.LC7:
.string "host: %d\n"
.LC9:
.string "CPU time: %.3f ms\n"
.LC10:
.string "CUDA time: %f ms\n"
.LC11:
.string "device: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 16777216(%rax), %rbp
.L32:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
leaq 32(%rsp), %rbp
movl $0, %esi
movq %rbp, %rdi
call gettimeofday@PLT
movl $4194304, %esi
movq %r12, %rdi
call _Z9hostReduxPii
movl %eax, %r13d
leaq 48(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rdx
movq %rbx, %rsi
call _Z16timeval_subtractP7timevalS0_S0_
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imulq $1000, 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd .LC8(%rip), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $65536, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rdx
movl $4194304, %esi
movq %r12, %rdi
call _Z11deviceReduxPiiS_
movq %rbp, %rax
leaq 65536(%rbp), %rcx
movl $0, %edx
.L33:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L33
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
cmpl %ebx, %r13d
setne %al
movzbl %al, %eax
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11reduxKernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11reduxKernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1598689907
.long 1076938487
.align 8
.LC8:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#include <stdlib.h>
#define N (1<<22)
#define BLOCK_SIZE 128
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
__global__ void reduxKernel(int* v, int n, int* res){
int tx = threadIdx.x;
int idx = blockIdx.x * (BLOCK_SIZE*2) + tx;
__shared__ int vs[BLOCK_SIZE*2];
// all threads execute the following, as the size of the shared memory is
// 2x the number of threads
int reg = idx < n ? v[idx] : 0;
if( idx + BLOCK_SIZE < n ){
reg += v[idx + BLOCK_SIZE];
}
//vs[tx] = v[idx] + v[idx + BLOCK_SIZE];
vs[tx] = reg;
__syncthreads();
if( BLOCK_SIZE >= 512 ){
if( tx < 256 ){ vs[tx] = reg = reg + vs[tx + 256]; __syncthreads(); }
}
if( BLOCK_SIZE >= 256 ){
if( tx < 128 ){ vs[tx] = reg = reg + vs[tx + 128]; __syncthreads(); }
}
if( BLOCK_SIZE >= 128 ){
if( tx < 64 ){ vs[tx] = reg = reg + vs[tx + 64]; __syncthreads(); }
}
// for( int bs = BLOCK_SIZE/2 ; bs > 32; bs >>= 1 ){
// if( tx < bs ){
// //accumulating on the register var "reg" saves a read
// //from shared memory. Instead of doing vs[tx] += vs[tx + bs],
// //we just accum on the reg and write it back to shared memory
// vs[tx] = reg = reg + vs[tx + bs];
// }
// __syncthreads();
// }
if( tx < 32 ){ //for the last wrap. Threads within a wrap don't need synchronize
volatile int* synchdShared = vs; //so that the compiler doesn't reorder
// in case the block size were less than 32 to begin with
if( BLOCK_SIZE >= 64 ){
// means we can "reach out" fully 32 positions to the right of the thread
// look at the general loop to work out why
synchdShared[tx] = reg = reg + synchdShared[tx + 32];
}
//and of course we are gonna fall-through
if( BLOCK_SIZE >= 32 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 16];
}
if( BLOCK_SIZE >= 16 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 8];
}
if( BLOCK_SIZE >= 8 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 4];
}
if( BLOCK_SIZE >= 4 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 2];
}
if( BLOCK_SIZE >= 2 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 1];
}
}
//interesting: without this if, the kernel execution takes 5x the time! Probably
//due the memory conflicts created by _ALL_ the threads trying to write to the same
//memory location "at once"
if(tx == 0){
res[blockIdx.x] = vs[0];
}
}
int hostRedux(int* v, int n){
int res = 0;
for(int i=0; i < n; i++){
res += v[i];
}
return res;
}
void deviceRedux(int* v, int n, int* res){
// reserve memory on device
int *vd;
int *resd;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float time;
const int numBlocks = (N/BLOCK_SIZE)/2;
HANDLE_ERROR( cudaMalloc((void**)&vd, n*sizeof(int)) );
HANDLE_ERROR( cudaMalloc((void**)&resd, numBlocks*sizeof(int)) );
cudaEventRecord( start, 0 );
// transfer v to vd
HANDLE_ERROR( cudaMemcpy(vd, v, n*sizeof(int), cudaMemcpyHostToDevice) );
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("memcpy in time: %f ms\n", time);
cudaEventRecord( start, 0 );
// invoke kernel
reduxKernel<<<numBlocks,BLOCK_SIZE>>>(vd,n,resd);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("kernel time: %f ms. ", time);
printf("Bandwidth: %f GB/s\n", (N*sizeof(int)/1e6)/time);
cudaEventRecord( start, 0 );
// copy results back to host
HANDLE_ERROR( cudaMemcpy(res, resd, numBlocks*sizeof(int), cudaMemcpyDeviceToHost) );
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
printf("memcpy out time: %f ms\n", time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
//free vd
cudaFree(vd);
cudaFree(resd);
}
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
int
timeval_subtract (struct timeval* result, struct timeval*x, struct timeval*y)
{
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (x->tv_usec - y->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result->tv_sec = x->tv_sec - y->tv_sec;
result->tv_usec = x->tv_usec - y->tv_usec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
int main(){
int* v = (int*)malloc( sizeof(int) * N);
for(int i=0; i < N; i++){
v[i] = rand() % 10;
//v[i] = i;
}
int h;
struct timeval tv_start;
struct timeval tv_stop;
struct timeval tv_diff;
gettimeofday(&tv_start, 0);
h=hostRedux(v,N);
gettimeofday(&tv_stop, 0);
timeval_subtract(&tv_diff, &tv_stop, &tv_start);
printf("host: %d\n", h);
float msdiff = tv_diff.tv_sec*1000 + tv_diff.tv_usec/1000.0;
printf("CPU time: %.3f ms\n", msdiff);
const int numBlocks = (N/BLOCK_SIZE)/2;
int *res = (int*)malloc( sizeof(int) * numBlocks);
int d;
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord( start, 0 );
deviceRedux(v,N, res);
d=0;
for(int i=0; i < numBlocks; i++){
// printf("%d\n", res[i]);
d+=res[i];
}
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("CUDA time: %f ms\n", time);
printf("device: %d\n", d);
free(v);
free(res);
return !(h==d);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#include <stdlib.h>
#define N (1<<22)
#define BLOCK_SIZE 128
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
__global__ void reduxKernel(int* v, int n, int* res){
int tx = threadIdx.x;
int idx = blockIdx.x * (BLOCK_SIZE*2) + tx;
__shared__ int vs[BLOCK_SIZE*2];
// all threads execute the following, as the size of the shared memory is
// 2x the number of threads
int reg = idx < n ? v[idx] : 0;
if( idx + BLOCK_SIZE < n ){
reg += v[idx + BLOCK_SIZE];
}
//vs[tx] = v[idx] + v[idx + BLOCK_SIZE];
vs[tx] = reg;
__syncthreads();
if( BLOCK_SIZE >= 512 ){
if( tx < 256 ){ vs[tx] = reg = reg + vs[tx + 256]; __syncthreads(); }
}
if( BLOCK_SIZE >= 256 ){
if( tx < 128 ){ vs[tx] = reg = reg + vs[tx + 128]; __syncthreads(); }
}
if( BLOCK_SIZE >= 128 ){
if( tx < 64 ){ vs[tx] = reg = reg + vs[tx + 64]; __syncthreads(); }
}
// for( int bs = BLOCK_SIZE/2 ; bs > 32; bs >>= 1 ){
// if( tx < bs ){
// //accumulating on the register var "reg" saves a read
// //from shared memory. Instead of doing vs[tx] += vs[tx + bs],
// //we just accum on the reg and write it back to shared memory
// vs[tx] = reg = reg + vs[tx + bs];
// }
// __syncthreads();
// }
if( tx < 32 ){ //for the last wrap. Threads within a wrap don't need synchronize
volatile int* synchdShared = vs; //so that the compiler doesn't reorder
// in case the block size were less than 32 to begin with
if( BLOCK_SIZE >= 64 ){
// means we can "reach out" fully 32 positions to the right of the thread
// look at the general loop to work out why
synchdShared[tx] = reg = reg + synchdShared[tx + 32];
}
//and of course we are gonna fall-through
if( BLOCK_SIZE >= 32 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 16];
}
if( BLOCK_SIZE >= 16 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 8];
}
if( BLOCK_SIZE >= 8 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 4];
}
if( BLOCK_SIZE >= 4 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 2];
}
if( BLOCK_SIZE >= 2 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 1];
}
}
//interesting: without this if, the kernel execution takes 5x the time! Probably
//due the memory conflicts created by _ALL_ the threads trying to write to the same
//memory location "at once"
if(tx == 0){
res[blockIdx.x] = vs[0];
}
}
int hostRedux(int* v, int n){
int res = 0;
for(int i=0; i < n; i++){
res += v[i];
}
return res;
}
void deviceRedux(int* v, int n, int* res){
// reserve memory on device
int *vd;
int *resd;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float time;
const int numBlocks = (N/BLOCK_SIZE)/2;
HANDLE_ERROR( hipMalloc((void**)&vd, n*sizeof(int)) );
HANDLE_ERROR( hipMalloc((void**)&resd, numBlocks*sizeof(int)) );
hipEventRecord( start, 0 );
// transfer v to vd
HANDLE_ERROR( hipMemcpy(vd, v, n*sizeof(int), hipMemcpyHostToDevice) );
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("memcpy in time: %f ms\n", time);
hipEventRecord( start, 0 );
// invoke kernel
reduxKernel<<<numBlocks,BLOCK_SIZE>>>(vd,n,resd);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("kernel time: %f ms. ", time);
printf("Bandwidth: %f GB/s\n", (N*sizeof(int)/1e6)/time);
hipEventRecord( start, 0 );
// copy results back to host
HANDLE_ERROR( hipMemcpy(res, resd, numBlocks*sizeof(int), hipMemcpyDeviceToHost) );
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("memcpy out time: %f ms\n", time);
hipEventDestroy(start);
hipEventDestroy(stop);
//free vd
hipFree(vd);
hipFree(resd);
}
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
int
timeval_subtract (struct timeval* result, struct timeval*x, struct timeval*y)
{
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (x->tv_usec - y->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result->tv_sec = x->tv_sec - y->tv_sec;
result->tv_usec = x->tv_usec - y->tv_usec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
int main(){
int* v = (int*)malloc( sizeof(int) * N);
for(int i=0; i < N; i++){
v[i] = rand() % 10;
//v[i] = i;
}
int h;
struct timeval tv_start;
struct timeval tv_stop;
struct timeval tv_diff;
gettimeofday(&tv_start, 0);
h=hostRedux(v,N);
gettimeofday(&tv_stop, 0);
timeval_subtract(&tv_diff, &tv_stop, &tv_start);
printf("host: %d\n", h);
float msdiff = tv_diff.tv_sec*1000 + tv_diff.tv_usec/1000.0;
printf("CPU time: %.3f ms\n", msdiff);
const int numBlocks = (N/BLOCK_SIZE)/2;
int *res = (int*)malloc( sizeof(int) * numBlocks);
int d;
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord( start, 0 );
deviceRedux(v,N, res);
d=0;
for(int i=0; i < numBlocks; i++){
// printf("%d\n", res[i]);
d+=res[i];
}
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy(start);
hipEventDestroy(stop);
printf("CUDA time: %f ms\n", time);
printf("device: %d\n", d);
free(v);
free(res);
return !(h==d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#include <stdlib.h>
#define N (1<<22)
#define BLOCK_SIZE 128
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
__global__ void reduxKernel(int* v, int n, int* res){
int tx = threadIdx.x;
int idx = blockIdx.x * (BLOCK_SIZE*2) + tx;
__shared__ int vs[BLOCK_SIZE*2];
// all threads execute the following, as the size of the shared memory is
// 2x the number of threads
int reg = idx < n ? v[idx] : 0;
if( idx + BLOCK_SIZE < n ){
reg += v[idx + BLOCK_SIZE];
}
//vs[tx] = v[idx] + v[idx + BLOCK_SIZE];
vs[tx] = reg;
__syncthreads();
if( BLOCK_SIZE >= 512 ){
if( tx < 256 ){ vs[tx] = reg = reg + vs[tx + 256]; __syncthreads(); }
}
if( BLOCK_SIZE >= 256 ){
if( tx < 128 ){ vs[tx] = reg = reg + vs[tx + 128]; __syncthreads(); }
}
if( BLOCK_SIZE >= 128 ){
if( tx < 64 ){ vs[tx] = reg = reg + vs[tx + 64]; __syncthreads(); }
}
// for( int bs = BLOCK_SIZE/2 ; bs > 32; bs >>= 1 ){
// if( tx < bs ){
// //accumulating on the register var "reg" saves a read
// //from shared memory. Instead of doing vs[tx] += vs[tx + bs],
// //we just accum on the reg and write it back to shared memory
// vs[tx] = reg = reg + vs[tx + bs];
// }
// __syncthreads();
// }
if( tx < 32 ){ //for the last wrap. Threads within a wrap don't need synchronize
volatile int* synchdShared = vs; //so that the compiler doesn't reorder
// in case the block size were less than 32 to begin with
if( BLOCK_SIZE >= 64 ){
// means we can "reach out" fully 32 positions to the right of the thread
// look at the general loop to work out why
synchdShared[tx] = reg = reg + synchdShared[tx + 32];
}
//and of course we are gonna fall-through
if( BLOCK_SIZE >= 32 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 16];
}
if( BLOCK_SIZE >= 16 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 8];
}
if( BLOCK_SIZE >= 8 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 4];
}
if( BLOCK_SIZE >= 4 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 2];
}
if( BLOCK_SIZE >= 2 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 1];
}
}
//interesting: without this if, the kernel execution takes 5x the time! Probably
//due the memory conflicts created by _ALL_ the threads trying to write to the same
//memory location "at once"
if(tx == 0){
res[blockIdx.x] = vs[0];
}
}
int hostRedux(int* v, int n){
int res = 0;
for(int i=0; i < n; i++){
res += v[i];
}
return res;
}
void deviceRedux(int* v, int n, int* res){
// reserve memory on device
int *vd;
int *resd;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float time;
const int numBlocks = (N/BLOCK_SIZE)/2;
HANDLE_ERROR( hipMalloc((void**)&vd, n*sizeof(int)) );
HANDLE_ERROR( hipMalloc((void**)&resd, numBlocks*sizeof(int)) );
hipEventRecord( start, 0 );
// transfer v to vd
HANDLE_ERROR( hipMemcpy(vd, v, n*sizeof(int), hipMemcpyHostToDevice) );
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("memcpy in time: %f ms\n", time);
hipEventRecord( start, 0 );
// invoke kernel
reduxKernel<<<numBlocks,BLOCK_SIZE>>>(vd,n,resd);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("kernel time: %f ms. ", time);
printf("Bandwidth: %f GB/s\n", (N*sizeof(int)/1e6)/time);
hipEventRecord( start, 0 );
// copy results back to host
HANDLE_ERROR( hipMemcpy(res, resd, numBlocks*sizeof(int), hipMemcpyDeviceToHost) );
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("memcpy out time: %f ms\n", time);
hipEventDestroy(start);
hipEventDestroy(stop);
//free vd
hipFree(vd);
hipFree(resd);
}
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
int
timeval_subtract (struct timeval* result, struct timeval*x, struct timeval*y)
{
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (x->tv_usec - y->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result->tv_sec = x->tv_sec - y->tv_sec;
result->tv_usec = x->tv_usec - y->tv_usec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
int main(){
int* v = (int*)malloc( sizeof(int) * N);
for(int i=0; i < N; i++){
v[i] = rand() % 10;
//v[i] = i;
}
int h;
struct timeval tv_start;
struct timeval tv_stop;
struct timeval tv_diff;
gettimeofday(&tv_start, 0);
h=hostRedux(v,N);
gettimeofday(&tv_stop, 0);
timeval_subtract(&tv_diff, &tv_stop, &tv_start);
printf("host: %d\n", h);
float msdiff = tv_diff.tv_sec*1000 + tv_diff.tv_usec/1000.0;
printf("CPU time: %.3f ms\n", msdiff);
const int numBlocks = (N/BLOCK_SIZE)/2;
int *res = (int*)malloc( sizeof(int) * numBlocks);
int d;
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord( start, 0 );
deviceRedux(v,N, res);
d=0;
for(int i=0; i < numBlocks; i++){
// printf("%d\n", res[i]);
d+=res[i];
}
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy(start);
hipEventDestroy(stop);
printf("CUDA time: %f ms\n", time);
printf("device: %d\n", d);
free(v);
free(res);
return !(h==d);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11reduxKernelPiiS_
.globl _Z11reduxKernelPiiS_
.p2align 8
.type _Z11reduxKernelPiiS_,@function
_Z11reduxKernelPiiS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s4, 8, v0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, 0x80, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_6
ds_load_b32 v2, v1 offset:256
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v2, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v6, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0x80, v6
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
flat_load_b32 v5, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v6, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v5, v3
v_add_nc_u32_e32 v3, 32, v6
flat_store_b32 v[1:2], v7 dlc
s_waitcnt_vscnt null, 0x0
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v4, 64, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, -1, v4
v_cndmask_b32_e64 v4, 0, v4, s2
v_cndmask_b32_e64 v5, 0, s7, s2
flat_load_b32 v4, v[4:5] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v5, v4, v7
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 16, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v4, v5
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 8, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v4, v5
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 4, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v3, v5
v_cndmask_b32_e32 v3, 0, v4, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11reduxKernelPiiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11reduxKernelPiiS_, .Lfunc_end0-_Z11reduxKernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11reduxKernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11reduxKernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#include <stdlib.h>
#define N (1<<22)
#define BLOCK_SIZE 128
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
__global__ void reduxKernel(int* v, int n, int* res){
int tx = threadIdx.x;
int idx = blockIdx.x * (BLOCK_SIZE*2) + tx;
__shared__ int vs[BLOCK_SIZE*2];
// all threads execute the following, as the size of the shared memory is
// 2x the number of threads
int reg = idx < n ? v[idx] : 0;
if( idx + BLOCK_SIZE < n ){
reg += v[idx + BLOCK_SIZE];
}
//vs[tx] = v[idx] + v[idx + BLOCK_SIZE];
vs[tx] = reg;
__syncthreads();
if( BLOCK_SIZE >= 512 ){
if( tx < 256 ){ vs[tx] = reg = reg + vs[tx + 256]; __syncthreads(); }
}
if( BLOCK_SIZE >= 256 ){
if( tx < 128 ){ vs[tx] = reg = reg + vs[tx + 128]; __syncthreads(); }
}
if( BLOCK_SIZE >= 128 ){
if( tx < 64 ){ vs[tx] = reg = reg + vs[tx + 64]; __syncthreads(); }
}
// for( int bs = BLOCK_SIZE/2 ; bs > 32; bs >>= 1 ){
// if( tx < bs ){
// //accumulating on the register var "reg" saves a read
// //from shared memory. Instead of doing vs[tx] += vs[tx + bs],
// //we just accum on the reg and write it back to shared memory
// vs[tx] = reg = reg + vs[tx + bs];
// }
// __syncthreads();
// }
if( tx < 32 ){ //for the last wrap. Threads within a wrap don't need synchronize
volatile int* synchdShared = vs; //so that the compiler doesn't reorder
// in case the block size were less than 32 to begin with
if( BLOCK_SIZE >= 64 ){
// means we can "reach out" fully 32 positions to the right of the thread
// look at the general loop to work out why
synchdShared[tx] = reg = reg + synchdShared[tx + 32];
}
//and of course we are gonna fall-through
if( BLOCK_SIZE >= 32 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 16];
}
if( BLOCK_SIZE >= 16 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 8];
}
if( BLOCK_SIZE >= 8 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 4];
}
if( BLOCK_SIZE >= 4 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 2];
}
if( BLOCK_SIZE >= 2 ){
synchdShared[tx] = reg = reg + synchdShared[tx + 1];
}
}
//interesting: without this if, the kernel execution takes 5x the time! Probably
//due the memory conflicts created by _ALL_ the threads trying to write to the same
//memory location "at once"
if(tx == 0){
res[blockIdx.x] = vs[0];
}
}
int hostRedux(int* v, int n){
int res = 0;
for(int i=0; i < n; i++){
res += v[i];
}
return res;
}
void deviceRedux(int* v, int n, int* res){
// reserve memory on device
int *vd;
int *resd;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float time;
const int numBlocks = (N/BLOCK_SIZE)/2;
HANDLE_ERROR( hipMalloc((void**)&vd, n*sizeof(int)) );
HANDLE_ERROR( hipMalloc((void**)&resd, numBlocks*sizeof(int)) );
hipEventRecord( start, 0 );
// transfer v to vd
HANDLE_ERROR( hipMemcpy(vd, v, n*sizeof(int), hipMemcpyHostToDevice) );
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("memcpy in time: %f ms\n", time);
hipEventRecord( start, 0 );
// invoke kernel
reduxKernel<<<numBlocks,BLOCK_SIZE>>>(vd,n,resd);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("kernel time: %f ms. ", time);
printf("Bandwidth: %f GB/s\n", (N*sizeof(int)/1e6)/time);
hipEventRecord( start, 0 );
// copy results back to host
HANDLE_ERROR( hipMemcpy(res, resd, numBlocks*sizeof(int), hipMemcpyDeviceToHost) );
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
printf("memcpy out time: %f ms\n", time);
hipEventDestroy(start);
hipEventDestroy(stop);
//free vd
hipFree(vd);
hipFree(resd);
}
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
int
timeval_subtract (struct timeval* result, struct timeval*x, struct timeval*y)
{
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (x->tv_usec - y->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result->tv_sec = x->tv_sec - y->tv_sec;
result->tv_usec = x->tv_usec - y->tv_usec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
int main(){
int* v = (int*)malloc( sizeof(int) * N);
for(int i=0; i < N; i++){
v[i] = rand() % 10;
//v[i] = i;
}
int h;
struct timeval tv_start;
struct timeval tv_stop;
struct timeval tv_diff;
gettimeofday(&tv_start, 0);
h=hostRedux(v,N);
gettimeofday(&tv_stop, 0);
timeval_subtract(&tv_diff, &tv_stop, &tv_start);
printf("host: %d\n", h);
float msdiff = tv_diff.tv_sec*1000 + tv_diff.tv_usec/1000.0;
printf("CPU time: %.3f ms\n", msdiff);
const int numBlocks = (N/BLOCK_SIZE)/2;
int *res = (int*)malloc( sizeof(int) * numBlocks);
int d;
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord( start, 0 );
deviceRedux(v,N, res);
d=0;
for(int i=0; i < numBlocks; i++){
// printf("%d\n", res[i]);
d+=res[i];
}
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &time, start, stop );
hipEventDestroy(start);
hipEventDestroy(stop);
printf("CUDA time: %f ms\n", time);
printf("device: %d\n", d);
free(v);
free(res);
return !(h==d);
} | .text
.file "6.1.hip"
.globl _Z26__device_stub__reduxKernelPiiS_ # -- Begin function _Z26__device_stub__reduxKernelPiiS_
.p2align 4, 0x90
.type _Z26__device_stub__reduxKernelPiiS_,@function
_Z26__device_stub__reduxKernelPiiS_: # @_Z26__device_stub__reduxKernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11reduxKernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__reduxKernelPiiS_, .Lfunc_end0-_Z26__device_stub__reduxKernelPiiS_
.cfi_endproc
# -- End function
.globl _Z9hostReduxPii # -- Begin function _Z9hostReduxPii
.p2align 4, 0x90
.type _Z9hostReduxPii,@function
_Z9hostReduxPii: # @_Z9hostReduxPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %ecx
xorl %edx, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_4
# %bb.2: # %._crit_edge
retq
.LBB1_1:
xorl %eax, %eax
retq
.Lfunc_end1:
.size _Z9hostReduxPii, .Lfunc_end1-_Z9hostReduxPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11deviceReduxPiiS_
.LCPI2_0:
.quad 0x4030c6f7a0b5ed8d # double 16.777215999999999
.text
.globl _Z11deviceReduxPiiS_
.p2align 4, 0x90
.type _Z11deviceReduxPiiS_,@function
_Z11deviceReduxPiiS_: # @_Z11deviceReduxPiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r15
shlq $2, %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 24(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit7
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit9
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 16256(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 104(%rsp)
movl %ebp, 44(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 44(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11reduxKernelPiiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_ZL11HandleError10hipError_tPKci.exit11
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $119, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $120, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $124, %ecx
jmp .LBB2_2
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $146, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z11deviceReduxPiiS_, .Lfunc_end2-_Z11deviceReduxPiiS_
.cfi_endproc
# -- End function
.globl _Z16timeval_subtractP7timevalS0_S0_ # -- Begin function _Z16timeval_subtractP7timevalS0_S0_
.p2align 4, 0x90
.type _Z16timeval_subtractP7timevalS0_S0_,@function
_Z16timeval_subtractP7timevalS0_S0_: # @_Z16timeval_subtractP7timevalS0_S0_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movq 8(%rdx), %r9
movq %r9, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq 8(%rsi), %rax
jle .LBB3_2
# %bb.1:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %r9
movq %r9, 8(%rcx)
cltq
addq %rax, (%rcx)
.LBB3_2:
movq 8(%rsi), %rax
movq 8(%rcx), %r9
subq %r9, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB3_4
# %bb.3:
mulq %r8
shrq $18, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rax
subq %rax, (%rcx)
.LBB3_4:
movq (%rsi), %rax
subq (%rcx), %rax
movq %rax, (%rdi)
movq 8(%rsi), %rax
subq 8(%rcx), %rax
movq %rax, 8(%rdi)
movq (%rsi), %rdx
xorl %eax, %eax
cmpq (%rcx), %rdx
setl %al
retq
.Lfunc_end3:
.size _Z16timeval_subtractP7timevalS0_S0_, .Lfunc_end3-_Z16timeval_subtractP7timevalS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB4_1
# %bb.2:
xorl %r14d, %r14d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%r14,4), %ebp
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB4_3
# %bb.4: # %_Z9hostReduxPii.exit
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %r14
movq 24(%rsp), %rsi
movq %rsi, %rax
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
subq %r14, %rax
jle .LBB4_6
# %bb.5:
imulq %rcx
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %rsi
movq %rsi, 24(%rsp)
cltq
addq %rax, 16(%rsp)
.LBB4_6:
movq 24(%rsp), %rsi
movq %r14, %rax
subq %rsi, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB4_8
# %bb.7:
mulq %rcx
shrq $18, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %rsi, %rax
movq %rax, 24(%rsp)
movslq %edx, %rax
subq %rax, 16(%rsp)
.LBB4_8: # %_Z16timeval_subtractP7timevalS0_S0_.exit
movq 48(%rsp), %r15
subq 16(%rsp), %r15
subq 24(%rsp), %r14
xorl %r12d, %r12d
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
imulq $1000, %r15, %rax # imm = 0x3E8
cvtsi2sd %rax, %xmm0
cvtsi2sd %r14, %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r14
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movl $4194304, %esi # imm = 0x400000
movq %r14, %rdx
callq _Z11deviceReduxPiiS_
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
addl (%r14,%r12,4), %r15d
incq %r12
cmpq $16384, %r12 # imm = 0x4000
jne .LBB4_9
# %bb.10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.L.str.8, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
cmpl %r15d, %ebp
setne %al
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11reduxKernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11reduxKernelPiiS_,@object # @_Z11reduxKernelPiiS_
.section .rodata,"a",@progbits
.globl _Z11reduxKernelPiiS_
.p2align 3, 0x0
_Z11reduxKernelPiiS_:
.quad _Z26__device_stub__reduxKernelPiiS_
.size _Z11reduxKernelPiiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dgquintas/my-code-samples/master/cuda/ProgrammingMassivelyParallelProcessors/ch6/6.1.hip"
.size .L.str, 146
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy in time: %f ms\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel time: %f ms. "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Bandwidth: %f GB/s\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "memcpy out time: %f ms\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "host: %d\n"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU time: %.3f ms\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA time: %f ms\n"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "device: %d\n"
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%s in %s at line %d\n"
.size .L.str.9, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11reduxKernelPiiS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__reduxKernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11reduxKernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11reduxKernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R6, 0x100, R9 ; /* 0x0000010006027824 */
/* 0x001fca00078e0209 */
/*0060*/ IADD3 R0, R2.reuse, 0x80, RZ ; /* 0x0000008002007810 */
/* 0x040fe40007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe20003f06270 */
/*0080*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e020b */
/*0090*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc60003f26270 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd000078e00ff */
/*00b0*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ @!P1 LDG.E R5, [R2.64+0x200] ; /* 0x0002000402059981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ISETP.GT.AND P0, PT, R9.reuse, 0x3f, PT ; /* 0x0000003f0900780c */
/* 0x040fe40003f04270 */
/*00e0*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*00f0*/ @!P1 IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100009824 */
/* 0x004fe200078e0205 */
/*0100*/ ISETP.GT.AND P1, PT, R9, 0x1f, PT ; /* 0x0000001f0900780c */
/* 0x000fc80003f24270 */
/*0110*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x000fe80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0140*/ BSSY B0, 0x2d0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0150*/ @!P0 LDS R5, [R9.X4+0x100] ; /* 0x0001000009058984 */
/* 0x000e240000004800 */
/*0160*/ @!P0 IADD3 R0, R0, R5, RZ ; /* 0x0000000500008210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P0 STS [R9.X4], R0 ; /* 0x0000000009008388 */
/* 0x0001e80000004800 */
/*0180*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0190*/ @P1 BRA 0x2c0 ; /* 0x0000012000001947 */
/* 0x000fea0003800000 */
/*01a0*/ LDS R3, [R9.X4+0x80] ; /* 0x0000800009037984 */
/* 0x001e240000004800 */
/*01b0*/ IMAD.IADD R3, R3, 0x1, R0 ; /* 0x0000000103037824 */
/* 0x001fca00078e0200 */
/*01c0*/ STS [R9.X4], R3 ; /* 0x0000000309007388 */
/* 0x000fe80000004800 */
/*01d0*/ LDS R0, [R9.X4+0x40] ; /* 0x0000400009007984 */
/* 0x000e240000004800 */
/*01e0*/ IADD3 R0, R3, R0, RZ ; /* 0x0000000003007210 */
/* 0x001fca0007ffe0ff */
/*01f0*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x000fe80000004800 */
/*0200*/ LDS R5, [R9.X4+0x20] ; /* 0x0000200009057984 */
/* 0x000e240000004800 */
/*0210*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x001fca00078e0205 */
/*0220*/ STS [R9.X4], R5 ; /* 0x0000000509007388 */
/* 0x000fe80000004800 */
/*0230*/ LDS R2, [R9.X4+0x10] ; /* 0x0000100009027984 */
/* 0x000e240000004800 */
/*0240*/ IADD3 R2, R5, R2, RZ ; /* 0x0000000205027210 */
/* 0x001fca0007ffe0ff */
/*0250*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x000fe80000004800 */
/*0260*/ LDS R7, [R9.X4+0x8] ; /* 0x0000080009077984 */
/* 0x000e240000004800 */
/*0270*/ IMAD.IADD R7, R2, 0x1, R7 ; /* 0x0000000102077824 */
/* 0x001fca00078e0207 */
/*0280*/ STS [R9.X4], R7 ; /* 0x0000000709007388 */
/* 0x000fe80000004800 */
/*0290*/ LDS R4, [R9.X4+0x4] ; /* 0x0000040009047984 */
/* 0x000e240000004800 */
/*02a0*/ IADD3 R4, R7, R4, RZ ; /* 0x0000000407047210 */
/* 0x001fca0007ffe0ff */
/*02b0*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0001e40000004800 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02d0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*02e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R11, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fe200078e000b */
/*0300*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0310*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11reduxKernelPiiS_
.globl _Z11reduxKernelPiiS_
.p2align 8
.type _Z11reduxKernelPiiS_,@function
_Z11reduxKernelPiiS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s4, 8, v0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, 0x80, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_6
ds_load_b32 v2, v1 offset:256
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v2, v3
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v6, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0x80, v6
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
flat_load_b32 v5, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v6, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v5, v3
v_add_nc_u32_e32 v3, 32, v6
flat_store_b32 v[1:2], v7 dlc
s_waitcnt_vscnt null, 0x0
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v4, 64, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, -1, v4
v_cndmask_b32_e64 v4, 0, v4, s2
v_cndmask_b32_e64 v5, 0, s7, s2
flat_load_b32 v4, v[4:5] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v5, v4, v7
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 16, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v4, v5
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 8, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v4, v5
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 4, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v3, v5
v_cndmask_b32_e32 v3, 0, v4, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11reduxKernelPiiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11reduxKernelPiiS_, .Lfunc_end0-_Z11reduxKernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11reduxKernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11reduxKernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009d90b_00000000-6_6.1.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9hostReduxPii
.type _Z9hostReduxPii, @function
_Z9hostReduxPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl $0, %edx
.L11:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L11
.L9:
movl %edx, %eax
ret
.L12:
movl $0, %edx
jmp .L9
.cfi_endproc
.LFE2058:
.size _Z9hostReduxPii, .-_Z9hostReduxPii
.globl _Z16timeval_subtractP7timevalS0_S0_
.type _Z16timeval_subtractP7timevalS0_S0_, @function
_Z16timeval_subtractP7timevalS0_S0_:
.LFB2060:
.cfi_startproc
endbr64
movq %rdi, %r8
movq %rdx, %rcx
movq 8(%rsi), %rax
movq 8(%rdx), %rdi
cmpq %rdi, %rax
jge .L15
movq %rdi, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
addl $1, %edx
imull $1000000, %edx, %eax
cltq
subq %rax, %rdi
movq %rdi, 8(%rcx)
movslq %edx, %rdx
addq %rdx, (%rcx)
.L15:
movq 8(%rcx), %r9
movq 8(%rsi), %rdi
subq %r9, %rdi
cmpq $1000000, %rdi
jle .L16
movabsq $4835703278458516699, %rdx
movq %rdi, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %rdi
subq %rdi, %rdx
imull $1000000, %edx, %eax
cltq
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rdx
subq %rdx, (%rcx)
.L16:
movq (%rsi), %rax
subq (%rcx), %rax
movq %rax, (%r8)
movq 8(%rsi), %rax
subq 8(%rcx), %rax
movq %rax, 8(%r8)
movq (%rcx), %rax
cmpq %rax, (%rsi)
setl %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z16timeval_subtractP7timevalS0_S0_, .-_Z16timeval_subtractP7timevalS0_S0_
.globl _Z34__device_stub__Z11reduxKernelPiiS_PiiS_
.type _Z34__device_stub__Z11reduxKernelPiiS_PiiS_, @function
_Z34__device_stub__Z11reduxKernelPiiS_PiiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11reduxKernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z11reduxKernelPiiS_PiiS_, .-_Z34__device_stub__Z11reduxKernelPiiS_PiiS_
.globl _Z11reduxKernelPiiS_
.type _Z11reduxKernelPiiS_, @function
_Z11reduxKernelPiiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11reduxKernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11reduxKernelPiiS_, .-_Z11reduxKernelPiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dgquintas/my-code-samples/master/cuda/ProgrammingMassivelyParallelProcessors/ch6/6.1.cu"
.section .rodata.str1.1
.LC2:
.string "memcpy in time: %f ms\n"
.LC3:
.string "kernel time: %f ms. "
.LC5:
.string "Bandwidth: %f GB/s\n"
.LC6:
.string "memcpy out time: %f ms\n"
.text
.globl _Z11deviceReduxPiiS_
.type _Z11deviceReduxPiiS_, @function
_Z11deviceReduxPiiS_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movl %esi, %ebp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebp, %rbx
salq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $117, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $118, %edx
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $122, %edx
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $16384, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L26:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rbx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
movsd .LC4(%rip), %xmm0
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $65536, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $144, %edx
leaq .LC1(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 24(%rsp), %rdx
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11reduxKernelPiiS_PiiS_
jmp .L26
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z11deviceReduxPiiS_, .-_Z11deviceReduxPiiS_
.section .rodata.str1.1
.LC7:
.string "host: %d\n"
.LC9:
.string "CPU time: %.3f ms\n"
.LC10:
.string "CUDA time: %f ms\n"
.LC11:
.string "device: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 16777216(%rax), %rbp
.L32:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
leaq 32(%rsp), %rbp
movl $0, %esi
movq %rbp, %rdi
call gettimeofday@PLT
movl $4194304, %esi
movq %r12, %rdi
call _Z9hostReduxPii
movl %eax, %r13d
leaq 48(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rdx
movq %rbx, %rsi
call _Z16timeval_subtractP7timevalS0_S0_
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imulq $1000, 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd .LC8(%rip), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $65536, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rdx
movl $4194304, %esi
movq %r12, %rdi
call _Z11deviceReduxPiiS_
movq %rbp, %rax
leaq 65536(%rbp), %rcx
movl $0, %edx
.L33:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L33
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
cmpl %ebx, %r13d
setne %al
movzbl %al, %eax
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11reduxKernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11reduxKernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1598689907
.long 1076938487
.align 8
.LC8:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "6.1.hip"
.globl _Z26__device_stub__reduxKernelPiiS_ # -- Begin function _Z26__device_stub__reduxKernelPiiS_
.p2align 4, 0x90
.type _Z26__device_stub__reduxKernelPiiS_,@function
_Z26__device_stub__reduxKernelPiiS_: # @_Z26__device_stub__reduxKernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11reduxKernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__reduxKernelPiiS_, .Lfunc_end0-_Z26__device_stub__reduxKernelPiiS_
.cfi_endproc
# -- End function
.globl _Z9hostReduxPii # -- Begin function _Z9hostReduxPii
.p2align 4, 0x90
.type _Z9hostReduxPii,@function
_Z9hostReduxPii: # @_Z9hostReduxPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %ecx
xorl %edx, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_4
# %bb.2: # %._crit_edge
retq
.LBB1_1:
xorl %eax, %eax
retq
.Lfunc_end1:
.size _Z9hostReduxPii, .Lfunc_end1-_Z9hostReduxPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11deviceReduxPiiS_
.LCPI2_0:
.quad 0x4030c6f7a0b5ed8d # double 16.777215999999999
.text
.globl _Z11deviceReduxPiiS_
.p2align 4, 0x90
.type _Z11deviceReduxPiiS_,@function
_Z11deviceReduxPiiS_: # @_Z11deviceReduxPiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r15
shlq $2, %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 24(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit7
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit9
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 16256(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 104(%rsp)
movl %ebp, 44(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 44(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11reduxKernelPiiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_ZL11HandleError10hipError_tPKci.exit11
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $119, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $120, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $124, %ecx
jmp .LBB2_2
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $146, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z11deviceReduxPiiS_, .Lfunc_end2-_Z11deviceReduxPiiS_
.cfi_endproc
# -- End function
.globl _Z16timeval_subtractP7timevalS0_S0_ # -- Begin function _Z16timeval_subtractP7timevalS0_S0_
.p2align 4, 0x90
.type _Z16timeval_subtractP7timevalS0_S0_,@function
_Z16timeval_subtractP7timevalS0_S0_: # @_Z16timeval_subtractP7timevalS0_S0_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movq 8(%rdx), %r9
movq %r9, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq 8(%rsi), %rax
jle .LBB3_2
# %bb.1:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %r9
movq %r9, 8(%rcx)
cltq
addq %rax, (%rcx)
.LBB3_2:
movq 8(%rsi), %rax
movq 8(%rcx), %r9
subq %r9, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB3_4
# %bb.3:
mulq %r8
shrq $18, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rax
subq %rax, (%rcx)
.LBB3_4:
movq (%rsi), %rax
subq (%rcx), %rax
movq %rax, (%rdi)
movq 8(%rsi), %rax
subq 8(%rcx), %rax
movq %rax, 8(%rdi)
movq (%rsi), %rdx
xorl %eax, %eax
cmpq (%rcx), %rdx
setl %al
retq
.Lfunc_end3:
.size _Z16timeval_subtractP7timevalS0_S0_, .Lfunc_end3-_Z16timeval_subtractP7timevalS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB4_1
# %bb.2:
xorl %r14d, %r14d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%r14,4), %ebp
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB4_3
# %bb.4: # %_Z9hostReduxPii.exit
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %r14
movq 24(%rsp), %rsi
movq %rsi, %rax
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
subq %r14, %rax
jle .LBB4_6
# %bb.5:
imulq %rcx
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %rsi
movq %rsi, 24(%rsp)
cltq
addq %rax, 16(%rsp)
.LBB4_6:
movq 24(%rsp), %rsi
movq %r14, %rax
subq %rsi, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB4_8
# %bb.7:
mulq %rcx
shrq $18, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %rsi, %rax
movq %rax, 24(%rsp)
movslq %edx, %rax
subq %rax, 16(%rsp)
.LBB4_8: # %_Z16timeval_subtractP7timevalS0_S0_.exit
movq 48(%rsp), %r15
subq 16(%rsp), %r15
subq 24(%rsp), %r14
xorl %r12d, %r12d
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
imulq $1000, %r15, %rax # imm = 0x3E8
cvtsi2sd %rax, %xmm0
cvtsi2sd %r14, %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r14
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movl $4194304, %esi # imm = 0x400000
movq %r14, %rdx
callq _Z11deviceReduxPiiS_
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
addl (%r14,%r12,4), %r15d
incq %r12
cmpq $16384, %r12 # imm = 0x4000
jne .LBB4_9
# %bb.10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.L.str.8, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
cmpl %r15d, %ebp
setne %al
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11reduxKernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11reduxKernelPiiS_,@object # @_Z11reduxKernelPiiS_
.section .rodata,"a",@progbits
.globl _Z11reduxKernelPiiS_
.p2align 3, 0x0
_Z11reduxKernelPiiS_:
.quad _Z26__device_stub__reduxKernelPiiS_
.size _Z11reduxKernelPiiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dgquintas/my-code-samples/master/cuda/ProgrammingMassivelyParallelProcessors/ch6/6.1.hip"
.size .L.str, 146
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy in time: %f ms\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel time: %f ms. "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Bandwidth: %f GB/s\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "memcpy out time: %f ms\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "host: %d\n"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU time: %.3f ms\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA time: %f ms\n"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "device: %d\n"
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%s in %s at line %d\n"
.size .L.str.9, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11reduxKernelPiiS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__reduxKernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11reduxKernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
#include<sys/time.h>
#include<time.h>
//Macro for checking cuda errors following a cuda launch or api call
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
void initialize(int *a, int *b, int *c, int *d, int input_length) {
for (int i = 0; i < input_length; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
c[i] = 0;
d[i] = 0;
}
}
void validate(int *a, int *b, int length) {
for (int i = 0; i < length; ++i) {
if (a[i] != b[i]) {
printf("Different value detected at position: %d,"
"expected %d but get %d\n", i, a[i], b[i]);
break;
}
}
}
void vector_add(int *a, int *b, int *c, int size) {
for (int i = 0; i < size; i++) {
c[i] = a[i] + b[i];
}
}
__global__ void vector_add_kernel_coalesced_access(int *a_d, int *b_d, int *d_d, int work_per_thread, int input_length, int totalThreads) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = 0; i < work_per_thread && tid < input_length; i++, tid += totalThreads){
d_d[tid] = a_d[tid] + b_d[tid];
}
}
int main(int argc, char *argv[]) {
int input_length, block_size, work_per_thread;
struct timeval start, end;
if (argc != 2) {
printf("Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: ");
scanf("%d", &input_length);
printf("Type block_size: ");
scanf("%d", &block_size);
printf("Type work_per_thread: ");
scanf("%d", &work_per_thread);
} else{
input_length = atoi(argv[1]);
block_size = atoi(argv[2]);
work_per_thread = atoi(argv[3]);
}
// Arrays declaration
int *a_h, *b_h, *c_h, *d_h;
int *a_d, *b_d, *d_d;
// Allocation on Host
a_h = (int *) malloc(sizeof(int) * input_length);
b_h = (int *) malloc(sizeof(int) * input_length);
c_h = (int *) malloc(sizeof(int) * input_length);
d_h = (int *) malloc(sizeof(int) * input_length);
// Allocation on Device
CUDA_CHECK_RETURN(cudaMalloc((void **)&a_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(cudaMalloc((void **)&b_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(cudaMalloc((void **)&d_d, sizeof(int)*input_length));
// Initialization on host side
initialize(a_h, b_h, c_h, d_h, input_length);
// Run host code
gettimeofday(&start, NULL);
vector_add(a_h, b_h, c_h, input_length);
gettimeofday(&end, NULL);
double diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Host VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Run device code
int grid_size = (input_length - 1) / (block_size * work_per_thread) + 1;
dim3 grid_dime(grid_size, 1, 1);
dim3 block_dime(block_size, 1, 1);
int totalThreads = grid_size * block_size;
gettimeofday(&start, NULL);
// Copy input data to device
CUDA_CHECK_RETURN(cudaMemcpy(a_d, a_h, sizeof(int)*input_length, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(b_d, b_h, sizeof(int)*input_length, cudaMemcpyHostToDevice));
vector_add_kernel_coalesced_access<<< grid_dime, block_dime >>>(a_d, b_d, d_d, work_per_thread, input_length, totalThreads);
CUDA_CHECK_RETURN(cudaDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError());
//Copy back the result
CUDA_CHECK_RETURN(cudaMemcpy(d_h, d_d, sizeof(int)*input_length, cudaMemcpyDeviceToHost));
gettimeofday(&end, NULL);
diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Device VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Validation
validate(c_h, d_h, input_length);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(d_d);
return 0;
} | code for sm_80
Function : _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x17c], !P0 ; /* 0x00005f0000007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0100*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0110*/ IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fc40007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe40003f06270 */
/*0130*/ ISETP.LT.AND P1, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f21270 */
/*0140*/ IMAD.IADD R9, R4, 0x1, R3 ; /* 0x0000000104097824 */
/* 0x004fca00078e0203 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0160*/ @!P0 BRA P1, 0xa0 ; /* 0xffffff3000008947 */
/* 0x000fea000083ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
#include<sys/time.h>
#include<time.h>
//Macro for checking cuda errors following a cuda launch or api call
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
void initialize(int *a, int *b, int *c, int *d, int input_length) {
for (int i = 0; i < input_length; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
c[i] = 0;
d[i] = 0;
}
}
void validate(int *a, int *b, int length) {
for (int i = 0; i < length; ++i) {
if (a[i] != b[i]) {
printf("Different value detected at position: %d,"
"expected %d but get %d\n", i, a[i], b[i]);
break;
}
}
}
void vector_add(int *a, int *b, int *c, int size) {
for (int i = 0; i < size; i++) {
c[i] = a[i] + b[i];
}
}
__global__ void vector_add_kernel_coalesced_access(int *a_d, int *b_d, int *d_d, int work_per_thread, int input_length, int totalThreads) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = 0; i < work_per_thread && tid < input_length; i++, tid += totalThreads){
d_d[tid] = a_d[tid] + b_d[tid];
}
}
int main(int argc, char *argv[]) {
int input_length, block_size, work_per_thread;
struct timeval start, end;
if (argc != 2) {
printf("Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: ");
scanf("%d", &input_length);
printf("Type block_size: ");
scanf("%d", &block_size);
printf("Type work_per_thread: ");
scanf("%d", &work_per_thread);
} else{
input_length = atoi(argv[1]);
block_size = atoi(argv[2]);
work_per_thread = atoi(argv[3]);
}
// Arrays declaration
int *a_h, *b_h, *c_h, *d_h;
int *a_d, *b_d, *d_d;
// Allocation on Host
a_h = (int *) malloc(sizeof(int) * input_length);
b_h = (int *) malloc(sizeof(int) * input_length);
c_h = (int *) malloc(sizeof(int) * input_length);
d_h = (int *) malloc(sizeof(int) * input_length);
// Allocation on Device
CUDA_CHECK_RETURN(cudaMalloc((void **)&a_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(cudaMalloc((void **)&b_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(cudaMalloc((void **)&d_d, sizeof(int)*input_length));
// Initialization on host side
initialize(a_h, b_h, c_h, d_h, input_length);
// Run host code
gettimeofday(&start, NULL);
vector_add(a_h, b_h, c_h, input_length);
gettimeofday(&end, NULL);
double diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Host VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Run device code
int grid_size = (input_length - 1) / (block_size * work_per_thread) + 1;
dim3 grid_dime(grid_size, 1, 1);
dim3 block_dime(block_size, 1, 1);
int totalThreads = grid_size * block_size;
gettimeofday(&start, NULL);
// Copy input data to device
CUDA_CHECK_RETURN(cudaMemcpy(a_d, a_h, sizeof(int)*input_length, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(b_d, b_h, sizeof(int)*input_length, cudaMemcpyHostToDevice));
vector_add_kernel_coalesced_access<<< grid_dime, block_dime >>>(a_d, b_d, d_d, work_per_thread, input_length, totalThreads);
CUDA_CHECK_RETURN(cudaDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError());
//Copy back the result
CUDA_CHECK_RETURN(cudaMemcpy(d_h, d_d, sizeof(int)*input_length, cudaMemcpyDeviceToHost));
gettimeofday(&end, NULL);
diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Device VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Validation
validate(c_h, d_h, input_length);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(d_d);
return 0;
} | .file "tmpxft_0017aa82_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePiS_S_S_i
.type _Z10initializePiS_S_S_i, @function
_Z10initializePiS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L8
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movq %rcx, %r15
movslq %r8d, %r8
leaq 0(,%r8,4), %rbp
movl $0, %ebx
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
movl $0, (%r14,%rbx)
movl $0, (%r15,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z10initializePiS_S_S_i, .-_Z10initializePiS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Different value detected at position: %d,expected %d but get %d\n"
.text
.globl _Z8validatePiS_i
.type _Z8validatePiS_i, @function
_Z8validatePiS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L17
movslq %edx, %rax
movl $0, %edx
.L14:
movl (%rdi,%rdx,4), %ecx
movl (%rsi,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L20
addq $1, %rdx
cmpq %rax, %rdx
jne .L14
ret
.L20:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L17:
ret
.cfi_endproc
.LFE2058:
.size _Z8validatePiS_i, .-_Z8validatePiS_i
.globl _Z10vector_addPiS_S_i
.type _Z10vector_addPiS_S_i, @function
_Z10vector_addPiS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L21
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L23:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L23
.L21:
ret
.cfi_endproc
.LFE2059:
.size _Z10vector_addPiS_S_i, .-_Z10vector_addPiS_S_i
.globl _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
.type _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii, @function
_Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z34vector_add_kernel_coalesced_accessPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii, .-_Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
.globl _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.type _Z34vector_add_kernel_coalesced_accessPiS_S_iii, @function
_Z34vector_add_kernel_coalesced_accessPiS_S_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z34vector_add_kernel_coalesced_accessPiS_S_iii, .-_Z34vector_add_kernel_coalesced_accessPiS_S_iii
.section .rodata.str1.8
.align 8
.LC1:
.string "Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d"
.LC3:
.string "Type block_size: "
.LC4:
.string "Type work_per_thread: "
.section .rodata.str1.8
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/amirsojoodi/GPUProgrammingT.A.Class/master/7th/vectorAdd.cu"
.align 8
.LC6:
.string "Error %s at line %d in file %s\n"
.align 8
.LC9:
.string "Host VectorAdd time calculation duration: %8.5fms\n"
.align 8
.LC10:
.string "Device VectorAdd time calculation duration: %8.5fms\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L34
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC2(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
.L35:
movslq 20(%rsp), %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L48
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L49
movl 20(%rsp), %r8d
movq %r13, %rcx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10initializePiS_S_S_i
leaq 80(%rsp), %r15
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
movl 20(%rsp), %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10vector_addPiS_S_i
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 24(%rsp), %r14d
movl 20(%rsp), %eax
subl $1, %eax
movl %r14d, %ecx
imull 28(%rsp), %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 12(%rsp)
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl %r14d, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L51
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L41:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L53
call cudaGetLastError@PLT
testl %eax, %eax
jne .L54
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L55
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 20(%rsp), %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z8validatePiS_i
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 20(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 24(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
jmp .L35
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $80, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $81, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $82, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $108, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $109, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl 12(%rsp), %r9d
imull %r14d, %r9d
movl 20(%rsp), %r8d
movl 28(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
jmp .L41
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $112, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $113, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $116, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z34vector_add_kernel_coalesced_accessPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z34vector_add_kernel_coalesced_accessPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.align 8
.LC8:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
#include<sys/time.h>
#include<time.h>
//Macro for checking cuda errors following a cuda launch or api call
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
void initialize(int *a, int *b, int *c, int *d, int input_length) {
for (int i = 0; i < input_length; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
c[i] = 0;
d[i] = 0;
}
}
void validate(int *a, int *b, int length) {
for (int i = 0; i < length; ++i) {
if (a[i] != b[i]) {
printf("Different value detected at position: %d,"
"expected %d but get %d\n", i, a[i], b[i]);
break;
}
}
}
void vector_add(int *a, int *b, int *c, int size) {
for (int i = 0; i < size; i++) {
c[i] = a[i] + b[i];
}
}
__global__ void vector_add_kernel_coalesced_access(int *a_d, int *b_d, int *d_d, int work_per_thread, int input_length, int totalThreads) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = 0; i < work_per_thread && tid < input_length; i++, tid += totalThreads){
d_d[tid] = a_d[tid] + b_d[tid];
}
}
int main(int argc, char *argv[]) {
int input_length, block_size, work_per_thread;
struct timeval start, end;
if (argc != 2) {
printf("Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: ");
scanf("%d", &input_length);
printf("Type block_size: ");
scanf("%d", &block_size);
printf("Type work_per_thread: ");
scanf("%d", &work_per_thread);
} else{
input_length = atoi(argv[1]);
block_size = atoi(argv[2]);
work_per_thread = atoi(argv[3]);
}
// Arrays declaration
int *a_h, *b_h, *c_h, *d_h;
int *a_d, *b_d, *d_d;
// Allocation on Host
a_h = (int *) malloc(sizeof(int) * input_length);
b_h = (int *) malloc(sizeof(int) * input_length);
c_h = (int *) malloc(sizeof(int) * input_length);
d_h = (int *) malloc(sizeof(int) * input_length);
// Allocation on Device
CUDA_CHECK_RETURN(cudaMalloc((void **)&a_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(cudaMalloc((void **)&b_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(cudaMalloc((void **)&d_d, sizeof(int)*input_length));
// Initialization on host side
initialize(a_h, b_h, c_h, d_h, input_length);
// Run host code
gettimeofday(&start, NULL);
vector_add(a_h, b_h, c_h, input_length);
gettimeofday(&end, NULL);
double diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Host VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Run device code
int grid_size = (input_length - 1) / (block_size * work_per_thread) + 1;
dim3 grid_dime(grid_size, 1, 1);
dim3 block_dime(block_size, 1, 1);
int totalThreads = grid_size * block_size;
gettimeofday(&start, NULL);
// Copy input data to device
CUDA_CHECK_RETURN(cudaMemcpy(a_d, a_h, sizeof(int)*input_length, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(b_d, b_h, sizeof(int)*input_length, cudaMemcpyHostToDevice));
vector_add_kernel_coalesced_access<<< grid_dime, block_dime >>>(a_d, b_d, d_d, work_per_thread, input_length, totalThreads);
CUDA_CHECK_RETURN(cudaDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError());
//Copy back the result
CUDA_CHECK_RETURN(cudaMemcpy(d_h, d_d, sizeof(int)*input_length, cudaMemcpyDeviceToHost));
gettimeofday(&end, NULL);
diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Device VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Validation
validate(c_h, d_h, input_length);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(d_d);
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
#include<sys/time.h>
#include<time.h>
//Macro for checking cuda errors following a cuda launch or api call
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
void initialize(int *a, int *b, int *c, int *d, int input_length) {
for (int i = 0; i < input_length; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
c[i] = 0;
d[i] = 0;
}
}
void validate(int *a, int *b, int length) {
for (int i = 0; i < length; ++i) {
if (a[i] != b[i]) {
printf("Different value detected at position: %d,"
"expected %d but get %d\n", i, a[i], b[i]);
break;
}
}
}
void vector_add(int *a, int *b, int *c, int size) {
for (int i = 0; i < size; i++) {
c[i] = a[i] + b[i];
}
}
__global__ void vector_add_kernel_coalesced_access(int *a_d, int *b_d, int *d_d, int work_per_thread, int input_length, int totalThreads) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = 0; i < work_per_thread && tid < input_length; i++, tid += totalThreads){
d_d[tid] = a_d[tid] + b_d[tid];
}
}
int main(int argc, char *argv[]) {
int input_length, block_size, work_per_thread;
struct timeval start, end;
if (argc != 2) {
printf("Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: ");
scanf("%d", &input_length);
printf("Type block_size: ");
scanf("%d", &block_size);
printf("Type work_per_thread: ");
scanf("%d", &work_per_thread);
} else{
input_length = atoi(argv[1]);
block_size = atoi(argv[2]);
work_per_thread = atoi(argv[3]);
}
// Arrays declaration
int *a_h, *b_h, *c_h, *d_h;
int *a_d, *b_d, *d_d;
// Allocation on Host
a_h = (int *) malloc(sizeof(int) * input_length);
b_h = (int *) malloc(sizeof(int) * input_length);
c_h = (int *) malloc(sizeof(int) * input_length);
d_h = (int *) malloc(sizeof(int) * input_length);
// Allocation on Device
CUDA_CHECK_RETURN(hipMalloc((void **)&a_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(hipMalloc((void **)&b_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(hipMalloc((void **)&d_d, sizeof(int)*input_length));
// Initialization on host side
initialize(a_h, b_h, c_h, d_h, input_length);
// Run host code
gettimeofday(&start, NULL);
vector_add(a_h, b_h, c_h, input_length);
gettimeofday(&end, NULL);
double diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Host VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Run device code
int grid_size = (input_length - 1) / (block_size * work_per_thread) + 1;
dim3 grid_dime(grid_size, 1, 1);
dim3 block_dime(block_size, 1, 1);
int totalThreads = grid_size * block_size;
gettimeofday(&start, NULL);
// Copy input data to device
CUDA_CHECK_RETURN(hipMemcpy(a_d, a_h, sizeof(int)*input_length, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(b_d, b_h, sizeof(int)*input_length, hipMemcpyHostToDevice));
vector_add_kernel_coalesced_access<<< grid_dime, block_dime >>>(a_d, b_d, d_d, work_per_thread, input_length, totalThreads);
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError());
//Copy back the result
CUDA_CHECK_RETURN(hipMemcpy(d_h, d_d, sizeof(int)*input_length, hipMemcpyDeviceToHost));
gettimeofday(&end, NULL);
diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Device VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Validation
validate(c_h, d_h, input_length);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(d_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
#include<sys/time.h>
#include<time.h>
//Macro for checking cuda errors following a cuda launch or api call
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
void initialize(int *a, int *b, int *c, int *d, int input_length) {
for (int i = 0; i < input_length; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
c[i] = 0;
d[i] = 0;
}
}
void validate(int *a, int *b, int length) {
for (int i = 0; i < length; ++i) {
if (a[i] != b[i]) {
printf("Different value detected at position: %d,"
"expected %d but get %d\n", i, a[i], b[i]);
break;
}
}
}
void vector_add(int *a, int *b, int *c, int size) {
for (int i = 0; i < size; i++) {
c[i] = a[i] + b[i];
}
}
__global__ void vector_add_kernel_coalesced_access(int *a_d, int *b_d, int *d_d, int work_per_thread, int input_length, int totalThreads) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = 0; i < work_per_thread && tid < input_length; i++, tid += totalThreads){
d_d[tid] = a_d[tid] + b_d[tid];
}
}
int main(int argc, char *argv[]) {
int input_length, block_size, work_per_thread;
struct timeval start, end;
if (argc != 2) {
printf("Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: ");
scanf("%d", &input_length);
printf("Type block_size: ");
scanf("%d", &block_size);
printf("Type work_per_thread: ");
scanf("%d", &work_per_thread);
} else{
input_length = atoi(argv[1]);
block_size = atoi(argv[2]);
work_per_thread = atoi(argv[3]);
}
// Arrays declaration
int *a_h, *b_h, *c_h, *d_h;
int *a_d, *b_d, *d_d;
// Allocation on Host
a_h = (int *) malloc(sizeof(int) * input_length);
b_h = (int *) malloc(sizeof(int) * input_length);
c_h = (int *) malloc(sizeof(int) * input_length);
d_h = (int *) malloc(sizeof(int) * input_length);
// Allocation on Device
CUDA_CHECK_RETURN(hipMalloc((void **)&a_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(hipMalloc((void **)&b_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(hipMalloc((void **)&d_d, sizeof(int)*input_length));
// Initialization on host side
initialize(a_h, b_h, c_h, d_h, input_length);
// Run host code
gettimeofday(&start, NULL);
vector_add(a_h, b_h, c_h, input_length);
gettimeofday(&end, NULL);
double diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Host VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Run device code
int grid_size = (input_length - 1) / (block_size * work_per_thread) + 1;
dim3 grid_dime(grid_size, 1, 1);
dim3 block_dime(block_size, 1, 1);
int totalThreads = grid_size * block_size;
gettimeofday(&start, NULL);
// Copy input data to device
CUDA_CHECK_RETURN(hipMemcpy(a_d, a_h, sizeof(int)*input_length, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(b_d, b_h, sizeof(int)*input_length, hipMemcpyHostToDevice));
vector_add_kernel_coalesced_access<<< grid_dime, block_dime >>>(a_d, b_d, d_d, work_per_thread, input_length, totalThreads);
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError());
//Copy back the result
CUDA_CHECK_RETURN(hipMemcpy(d_h, d_d, sizeof(int)*input_length, hipMemcpyDeviceToHost));
gettimeofday(&end, NULL);
diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Device VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Validation
validate(c_h, d_h, input_length);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(d_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.globl _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.p2align 8
.type _Z34vector_add_kernel_coalesced_accessPiS_S_iii,@function
_Z34vector_add_kernel_coalesced_accessPiS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s2, 0
s_mul_i32 s15, s15, s4
s_cselect_b32 s4, -1, 0
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_b32 s4, s4, vcc_lo
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s8, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s15, s8, v0
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[12:13], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
s_cmp_ge_i32 s1, s2
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s3, v0
v_add_co_u32 v1, s0, v1, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s13, v2, s0
s_cselect_b32 s0, -1, 0
v_add_nc_u32_e32 v0, s8, v0
s_or_b32 s0, s0, vcc_lo
s_add_i32 s1, s1, 1
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s0, s14
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v5, v7
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34vector_add_kernel_coalesced_accessPiS_S_iii, .Lfunc_end0-_Z34vector_add_kernel_coalesced_accessPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z34vector_add_kernel_coalesced_accessPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
#include<sys/time.h>
#include<time.h>
//Macro for checking cuda errors following a cuda launch or api call
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
void initialize(int *a, int *b, int *c, int *d, int input_length) {
for (int i = 0; i < input_length; i++) {
a[i] = rand() % 100;
b[i] = rand() % 100;
c[i] = 0;
d[i] = 0;
}
}
void validate(int *a, int *b, int length) {
for (int i = 0; i < length; ++i) {
if (a[i] != b[i]) {
printf("Different value detected at position: %d,"
"expected %d but get %d\n", i, a[i], b[i]);
break;
}
}
}
void vector_add(int *a, int *b, int *c, int size) {
for (int i = 0; i < size; i++) {
c[i] = a[i] + b[i];
}
}
__global__ void vector_add_kernel_coalesced_access(int *a_d, int *b_d, int *d_d, int work_per_thread, int input_length, int totalThreads) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for(int i = 0; i < work_per_thread && tid < input_length; i++, tid += totalThreads){
d_d[tid] = a_d[tid] + b_d[tid];
}
}
int main(int argc, char *argv[]) {
int input_length, block_size, work_per_thread;
struct timeval start, end;
if (argc != 2) {
printf("Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: ");
scanf("%d", &input_length);
printf("Type block_size: ");
scanf("%d", &block_size);
printf("Type work_per_thread: ");
scanf("%d", &work_per_thread);
} else{
input_length = atoi(argv[1]);
block_size = atoi(argv[2]);
work_per_thread = atoi(argv[3]);
}
// Arrays declaration
int *a_h, *b_h, *c_h, *d_h;
int *a_d, *b_d, *d_d;
// Allocation on Host
a_h = (int *) malloc(sizeof(int) * input_length);
b_h = (int *) malloc(sizeof(int) * input_length);
c_h = (int *) malloc(sizeof(int) * input_length);
d_h = (int *) malloc(sizeof(int) * input_length);
// Allocation on Device
CUDA_CHECK_RETURN(hipMalloc((void **)&a_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(hipMalloc((void **)&b_d, sizeof(int)*input_length));
CUDA_CHECK_RETURN(hipMalloc((void **)&d_d, sizeof(int)*input_length));
// Initialization on host side
initialize(a_h, b_h, c_h, d_h, input_length);
// Run host code
gettimeofday(&start, NULL);
vector_add(a_h, b_h, c_h, input_length);
gettimeofday(&end, NULL);
double diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Host VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Run device code
int grid_size = (input_length - 1) / (block_size * work_per_thread) + 1;
dim3 grid_dime(grid_size, 1, 1);
dim3 block_dime(block_size, 1, 1);
int totalThreads = grid_size * block_size;
gettimeofday(&start, NULL);
// Copy input data to device
CUDA_CHECK_RETURN(hipMemcpy(a_d, a_h, sizeof(int)*input_length, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(b_d, b_h, sizeof(int)*input_length, hipMemcpyHostToDevice));
vector_add_kernel_coalesced_access<<< grid_dime, block_dime >>>(a_d, b_d, d_d, work_per_thread, input_length, totalThreads);
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError());
//Copy back the result
CUDA_CHECK_RETURN(hipMemcpy(d_h, d_d, sizeof(int)*input_length, hipMemcpyDeviceToHost));
gettimeofday(&end, NULL);
diff = (end.tv_sec - start.tv_sec) * 1000000.0 +
(end.tv_usec - start.tv_usec);
printf("Device VectorAdd time calculation duration: %8.5fms\n", diff / 1000);
// Validation
validate(c_h, d_h, input_length);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(d_d);
return 0;
} | .text
.file "vectorAdd.hip"
.globl _Z10initializePiS_S_S_i # -- Begin function _Z10initializePiS_S_S_i
.p2align 4, 0x90
.type _Z10initializePiS_S_S_i,@function
_Z10initializePiS_S_S_i: # @_Z10initializePiS_S_S_i
.cfi_startproc
# %bb.0:
testl %r8d, %r8d
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl %r8d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r12,%rbp,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%rbp,4)
movl $0, (%r14,%rbp,4)
movl $0, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB0_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initializePiS_S_S_i, .Lfunc_end0-_Z10initializePiS_S_S_i
.cfi_endproc
# -- End function
.globl _Z8validatePiS_i # -- Begin function _Z8validatePiS_i
.p2align 4, 0x90
.type _Z8validatePiS_i,@function
_Z8validatePiS_i: # @_Z8validatePiS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %edx
movl (%rsi,%rax,4), %ecx
cmpl %ecx, %edx
jne .LBB1_5
# %bb.3: # in Loop: Header=BB1_2 Depth=1
incq %rax
cmpq %rax, %r8
jne .LBB1_2
.LBB1_4: # %.loopexit
retq
.LBB1_5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end1:
.size _Z8validatePiS_i, .Lfunc_end1-_Z8validatePiS_i
.cfi_endproc
# -- End function
.globl _Z10vector_addPiS_S_i # -- Begin function _Z10vector_addPiS_S_i
.p2align 4, 0x90
.type _Z10vector_addPiS_S_i,@function
_Z10vector_addPiS_S_i: # @_Z10vector_addPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10vector_addPiS_S_i, .Lfunc_end2-_Z10vector_addPiS_S_i
.cfi_endproc
# -- End function
.globl _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii # -- Begin function _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.p2align 4, 0x90
.type _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii,@function
_Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii: # @_Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z34vector_add_kernel_coalesced_accessPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii, .Lfunc_end3-_Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB4_1
# %bb.2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%rsp)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 12(%rsp)
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 8(%rsp)
jmp .LBB4_3
.LBB4_1:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
.LBB4_3:
movslq 4(%rsp), %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_4
# %bb.6:
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_7
# %bb.8:
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_9
# %bb.10:
movl 4(%rsp), %r13d
testl %r13d, %r13d
jle .LBB4_13
# %bb.11: # %.lr.ph.preheader.i
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_12: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%rbp,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbp,4)
movl $0, (%r15,%rbp,4)
movl $0, (%r12,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB4_12
.LBB4_13: # %_Z10initializePiS_S_S_i.exit
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB4_16
# %bb.14: # %.lr.ph.preheader.i62
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_15: # %.lr.ph.i64
# =>This Inner Loop Header: Depth=1
movl (%r14,%rcx,4), %edx
addl (%rbx,%rcx,4), %edx
movl %edx, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_15
.LBB4_16: # %_Z10vector_addPiS_S_i.exit
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %rax
movq 64(%rsp), %rcx
subq 72(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 80(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl 4(%rsp), %eax
decl %eax
movl 12(%rsp), %ebp
movl 8(%rsp), %ecx
imull %ebp, %ecx
cltd
idivl %ecx
movl %eax, %r13d
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_17
# %bb.18:
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.20:
incl %r13d
movabsq $4294967296, %rax # imm = 0x100000000
leaq (%rax,%r13), %rdi
movq %rbp, %rdx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_22
# %bb.21:
imull %ebp, %r13d
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl 8(%rsp), %esi
movl 4(%rsp), %edi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %esi, 52(%rsp)
movl %edi, 48(%rsp)
movl %r13d, 44(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z34vector_add_kernel_coalesced_accessPiS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_22:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_23
# %bb.24:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_25
# %bb.26:
movq 16(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_27
# %bb.28:
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %rax
movq 64(%rsp), %rcx
subq 72(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 80(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB4_33
# %bb.29: # %.lr.ph.preheader.i68
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_30: # %.lr.ph.i70
# =>This Inner Loop Header: Depth=1
movl (%r15,%rsi,4), %edx
movl (%r12,%rsi,4), %ecx
cmpl %ecx, %edx
jne .LBB4_31
# %bb.32: # in Loop: Header=BB4_30 Depth=1
incq %rsi
cmpq %rsi, %rax
jne .LBB4_30
jmp .LBB4_33
.LBB4_31:
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB4_33: # %_Z8validatePiS_i.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_4:
.cfi_def_cfa_offset 272
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $80, %ecx
jmp .LBB4_5
.LBB4_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %ecx
jmp .LBB4_5
.LBB4_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %ecx
jmp .LBB4_5
.LBB4_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %ecx
jmp .LBB4_5
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %ecx
jmp .LBB4_5
.LBB4_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $112, %ecx
jmp .LBB4_5
.LBB4_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $113, %ecx
jmp .LBB4_5
.LBB4_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $116, %ecx
.LBB4_5:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34vector_add_kernel_coalesced_accessPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Different value detected at position: %d,expected %d but get %d\n"
.size .L.str, 65
.type _Z34vector_add_kernel_coalesced_accessPiS_S_iii,@object # @_Z34vector_add_kernel_coalesced_accessPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.p2align 3, 0x0
_Z34vector_add_kernel_coalesced_accessPiS_S_iii:
.quad _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.size _Z34vector_add_kernel_coalesced_accessPiS_S_iii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: "
.size .L.str.1, 93
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Type block_size: "
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Type work_per_thread: "
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/amirsojoodi/GPUProgrammingT.A.Class/master/7th/vectorAdd.hip"
.size .L.str.6, 118
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Host VectorAdd time calculation duration: %8.5fms\n"
.size .L.str.7, 51
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device VectorAdd time calculation duration: %8.5fms\n"
.size .L.str.8, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z34vector_add_kernel_coalesced_accessPiS_S_iii"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x17c], !P0 ; /* 0x00005f0000007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0100*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0110*/ IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fc40007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe40003f06270 */
/*0130*/ ISETP.LT.AND P1, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f21270 */
/*0140*/ IMAD.IADD R9, R4, 0x1, R3 ; /* 0x0000000104097824 */
/* 0x004fca00078e0203 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0160*/ @!P0 BRA P1, 0xa0 ; /* 0xffffff3000008947 */
/* 0x000fea000083ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.globl _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.p2align 8
.type _Z34vector_add_kernel_coalesced_accessPiS_S_iii,@function
_Z34vector_add_kernel_coalesced_accessPiS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s2, 0
s_mul_i32 s15, s15, s4
s_cselect_b32 s4, -1, 0
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_b32 s4, s4, vcc_lo
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s8, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s15, s8, v0
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[12:13], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
s_cmp_ge_i32 s1, s2
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s3, v0
v_add_co_u32 v1, s0, v1, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s13, v2, s0
s_cselect_b32 s0, -1, 0
v_add_nc_u32_e32 v0, s8, v0
s_or_b32 s0, s0, vcc_lo
s_add_i32 s1, s1, 1
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s0, s14
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v5, v7
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34vector_add_kernel_coalesced_accessPiS_S_iii, .Lfunc_end0-_Z34vector_add_kernel_coalesced_accessPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z34vector_add_kernel_coalesced_accessPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017aa82_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePiS_S_S_i
.type _Z10initializePiS_S_S_i, @function
_Z10initializePiS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L8
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movq %rcx, %r15
movslq %r8d, %r8
leaq 0(,%r8,4), %rbp
movl $0, %ebx
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
movl $0, (%r14,%rbx)
movl $0, (%r15,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z10initializePiS_S_S_i, .-_Z10initializePiS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Different value detected at position: %d,expected %d but get %d\n"
.text
.globl _Z8validatePiS_i
.type _Z8validatePiS_i, @function
_Z8validatePiS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L17
movslq %edx, %rax
movl $0, %edx
.L14:
movl (%rdi,%rdx,4), %ecx
movl (%rsi,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L20
addq $1, %rdx
cmpq %rax, %rdx
jne .L14
ret
.L20:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L17:
ret
.cfi_endproc
.LFE2058:
.size _Z8validatePiS_i, .-_Z8validatePiS_i
.globl _Z10vector_addPiS_S_i
.type _Z10vector_addPiS_S_i, @function
_Z10vector_addPiS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L21
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L23:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L23
.L21:
ret
.cfi_endproc
.LFE2059:
.size _Z10vector_addPiS_S_i, .-_Z10vector_addPiS_S_i
.globl _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
.type _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii, @function
_Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z34vector_add_kernel_coalesced_accessPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii, .-_Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
.globl _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.type _Z34vector_add_kernel_coalesced_accessPiS_S_iii, @function
_Z34vector_add_kernel_coalesced_accessPiS_S_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z34vector_add_kernel_coalesced_accessPiS_S_iii, .-_Z34vector_add_kernel_coalesced_accessPiS_S_iii
.section .rodata.str1.8
.align 8
.LC1:
.string "Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d"
.LC3:
.string "Type block_size: "
.LC4:
.string "Type work_per_thread: "
.section .rodata.str1.8
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/amirsojoodi/GPUProgrammingT.A.Class/master/7th/vectorAdd.cu"
.align 8
.LC6:
.string "Error %s at line %d in file %s\n"
.align 8
.LC9:
.string "Host VectorAdd time calculation duration: %8.5fms\n"
.align 8
.LC10:
.string "Device VectorAdd time calculation duration: %8.5fms\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L34
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC2(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
.L35:
movslq 20(%rsp), %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L48
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L49
movl 20(%rsp), %r8d
movq %r13, %rcx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10initializePiS_S_S_i
leaq 80(%rsp), %r15
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
movl 20(%rsp), %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10vector_addPiS_S_i
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 24(%rsp), %r14d
movl 20(%rsp), %eax
subl $1, %eax
movl %r14d, %ecx
imull 28(%rsp), %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 12(%rsp)
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl %r14d, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L51
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L41:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L53
call cudaGetLastError@PLT
testl %eax, %eax
jne .L54
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L55
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 20(%rsp), %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z8validatePiS_i
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 20(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 24(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
jmp .L35
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $80, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $81, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $82, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $108, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $109, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl 12(%rsp), %r9d
imull %r14d, %r9d
movl 20(%rsp), %r8d
movl 28(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z61__device_stub__Z34vector_add_kernel_coalesced_accessPiS_S_iiiPiS_S_iii
jmp .L41
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $112, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $113, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $116, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z34vector_add_kernel_coalesced_accessPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z34vector_add_kernel_coalesced_accessPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.align 8
.LC8:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.globl _Z10initializePiS_S_S_i # -- Begin function _Z10initializePiS_S_S_i
.p2align 4, 0x90
.type _Z10initializePiS_S_S_i,@function
_Z10initializePiS_S_S_i: # @_Z10initializePiS_S_S_i
.cfi_startproc
# %bb.0:
testl %r8d, %r8d
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl %r8d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r12,%rbp,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%rbp,4)
movl $0, (%r14,%rbp,4)
movl $0, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB0_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initializePiS_S_S_i, .Lfunc_end0-_Z10initializePiS_S_S_i
.cfi_endproc
# -- End function
.globl _Z8validatePiS_i # -- Begin function _Z8validatePiS_i
.p2align 4, 0x90
.type _Z8validatePiS_i,@function
_Z8validatePiS_i: # @_Z8validatePiS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %edx
movl (%rsi,%rax,4), %ecx
cmpl %ecx, %edx
jne .LBB1_5
# %bb.3: # in Loop: Header=BB1_2 Depth=1
incq %rax
cmpq %rax, %r8
jne .LBB1_2
.LBB1_4: # %.loopexit
retq
.LBB1_5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end1:
.size _Z8validatePiS_i, .Lfunc_end1-_Z8validatePiS_i
.cfi_endproc
# -- End function
.globl _Z10vector_addPiS_S_i # -- Begin function _Z10vector_addPiS_S_i
.p2align 4, 0x90
.type _Z10vector_addPiS_S_i,@function
_Z10vector_addPiS_S_i: # @_Z10vector_addPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10vector_addPiS_S_i, .Lfunc_end2-_Z10vector_addPiS_S_i
.cfi_endproc
# -- End function
.globl _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii # -- Begin function _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.p2align 4, 0x90
.type _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii,@function
_Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii: # @_Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z34vector_add_kernel_coalesced_accessPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii, .Lfunc_end3-_Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB4_1
# %bb.2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%rsp)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 12(%rsp)
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 8(%rsp)
jmp .LBB4_3
.LBB4_1:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
.LBB4_3:
movslq 4(%rsp), %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_4
# %bb.6:
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_7
# %bb.8:
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_9
# %bb.10:
movl 4(%rsp), %r13d
testl %r13d, %r13d
jle .LBB4_13
# %bb.11: # %.lr.ph.preheader.i
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_12: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%rbp,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbp,4)
movl $0, (%r15,%rbp,4)
movl $0, (%r12,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB4_12
.LBB4_13: # %_Z10initializePiS_S_S_i.exit
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB4_16
# %bb.14: # %.lr.ph.preheader.i62
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_15: # %.lr.ph.i64
# =>This Inner Loop Header: Depth=1
movl (%r14,%rcx,4), %edx
addl (%rbx,%rcx,4), %edx
movl %edx, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_15
.LBB4_16: # %_Z10vector_addPiS_S_i.exit
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %rax
movq 64(%rsp), %rcx
subq 72(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 80(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl 4(%rsp), %eax
decl %eax
movl 12(%rsp), %ebp
movl 8(%rsp), %ecx
imull %ebp, %ecx
cltd
idivl %ecx
movl %eax, %r13d
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_17
# %bb.18:
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.20:
incl %r13d
movabsq $4294967296, %rax # imm = 0x100000000
leaq (%rax,%r13), %rdi
movq %rbp, %rdx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_22
# %bb.21:
imull %ebp, %r13d
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl 8(%rsp), %esi
movl 4(%rsp), %edi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %esi, 52(%rsp)
movl %edi, 48(%rsp)
movl %r13d, 44(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z34vector_add_kernel_coalesced_accessPiS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_22:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_23
# %bb.24:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_25
# %bb.26:
movq 16(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_27
# %bb.28:
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %rax
movq 64(%rsp), %rcx
subq 72(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
subq 80(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB4_33
# %bb.29: # %.lr.ph.preheader.i68
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_30: # %.lr.ph.i70
# =>This Inner Loop Header: Depth=1
movl (%r15,%rsi,4), %edx
movl (%r12,%rsi,4), %ecx
cmpl %ecx, %edx
jne .LBB4_31
# %bb.32: # in Loop: Header=BB4_30 Depth=1
incq %rsi
cmpq %rsi, %rax
jne .LBB4_30
jmp .LBB4_33
.LBB4_31:
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB4_33: # %_Z8validatePiS_i.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_4:
.cfi_def_cfa_offset 272
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $80, %ecx
jmp .LBB4_5
.LBB4_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %ecx
jmp .LBB4_5
.LBB4_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %ecx
jmp .LBB4_5
.LBB4_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %ecx
jmp .LBB4_5
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %ecx
jmp .LBB4_5
.LBB4_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $112, %ecx
jmp .LBB4_5
.LBB4_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $113, %ecx
jmp .LBB4_5
.LBB4_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.6, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $116, %ecx
.LBB4_5:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34vector_add_kernel_coalesced_accessPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Different value detected at position: %d,expected %d but get %d\n"
.size .L.str, 65
.type _Z34vector_add_kernel_coalesced_accessPiS_S_iii,@object # @_Z34vector_add_kernel_coalesced_accessPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.p2align 3, 0x0
_Z34vector_add_kernel_coalesced_accessPiS_S_iii:
.quad _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.size _Z34vector_add_kernel_coalesced_accessPiS_S_iii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Usage is: VectorAddParallel input_length block_size work_per_thread\nNow, type input_length: "
.size .L.str.1, 93
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Type block_size: "
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Type work_per_thread: "
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/amirsojoodi/GPUProgrammingT.A.Class/master/7th/vectorAdd.hip"
.size .L.str.6, 118
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Host VectorAdd time calculation duration: %8.5fms\n"
.size .L.str.7, 51
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device VectorAdd time calculation duration: %8.5fms\n"
.size .L.str.8, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z34vector_add_kernel_coalesced_accessPiS_S_iii"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__vector_add_kernel_coalesced_accessPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34vector_add_kernel_coalesced_accessPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <ctime>
#define LOG_NUM_BANKS 5
#define NUM_BANKS 32
#define BLOCK_SIZE 64
#define DEBUG
#ifdef DEBUG
#define cudaCheckError(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "CUDA Error: %s at %s:%d\n",
cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#else
#define cudaCheckError(ans) ans
#endif
__device__ inline size_t NoConflictIndex(size_t index) {
return index;
// return index + (index >> LOG_NUM_BANKS);
}
__global__ void PrescanBlocks(float * out_data, const float * in_data, float * block_sums, const size_t data_size) {
// keeps all the in_data during processing
extern __shared__ float in_data_shared[];
size_t thread_id_local = threadIdx.x;
size_t offset = 1;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
in_data_shared[NoConflictIndex(2 * thread_id_local)] = in_data[2 * thread_id_global];
in_data_shared[NoConflictIndex(2 * thread_id_local + 1)] = in_data[2 * thread_id_global + 1];
for (size_t level_size = 2 * blockDim.x >> 1; level_size > 0; level_size >>= 1) {
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
in_data_shared[NoConflictIndex(parent_idx)] += in_data_shared[NoConflictIndex(left_son_idx)];
}
offset *= 2;
}
if (thread_id_local == 0) {
block_sums[blockIdx.x] = in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)];
in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)] = 0;
}
for (size_t level_size = 1; level_size < 2 * blockDim.x; level_size *= 2) {
offset >>= 1;
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
float left_son_value = in_data_shared[NoConflictIndex(left_son_idx)];
in_data_shared[NoConflictIndex(left_son_idx)] = in_data_shared[NoConflictIndex(parent_idx)];
in_data_shared[NoConflictIndex(parent_idx)] += left_son_value;
}
}
__syncthreads();
out_data[2 * thread_id_global] = in_data_shared[NoConflictIndex(2 * thread_id_local)];
out_data[2 * thread_id_global + 1] = in_data_shared[NoConflictIndex(2 * thread_id_local + 1)];
}
__global__ void AddBlockSums(float * data, const float * block_sums, const size_t data_size) {
__shared__ float this_block_sum;
size_t thread_id_local = threadIdx.x;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
if (thread_id_local == 0) {
this_block_sum = block_sums[blockIdx.x];
}
__syncthreads();
data[thread_id_global] += this_block_sum;
}
__host__ void PrescanBlockSums(float * block_sums, const size_t num_blocks) {
float sum = block_sums[0];
block_sums[0] = 0;
float keep;
for (size_t block_id = 1; block_id < num_blocks; ++block_id) {
keep = block_sums[block_id];
block_sums[block_id] = sum;
sum += keep;
}
}
void TotalPrescanGPU(const float * data, float * partial_sums, size_t data_size) {
float * d_data;
float * d_partial_sums;
float * d_block_sums;
float * block_sums;
size_t num_blocks = ((data_size + 2 * BLOCK_SIZE - 1) / (2 * BLOCK_SIZE));
size_t shared_size = ((2 * BLOCK_SIZE + NUM_BANKS - 1) / NUM_BANKS + BLOCK_SIZE) * 2 * sizeof(float);
block_sums = (float *) malloc(num_blocks * sizeof(float));
cudaCheckError( cudaMalloc(&d_data, data_size * sizeof(float)) );
cudaCheckError( cudaMalloc(&d_partial_sums, data_size * sizeof(float)) );
cudaCheckError( cudaMalloc(&d_block_sums, num_blocks * sizeof(float)) );
cudaMemcpy(d_data, data, data_size * sizeof(float), cudaMemcpyHostToDevice);
PrescanBlocks<<<num_blocks, BLOCK_SIZE, shared_size>>>(d_partial_sums, d_data, d_block_sums, data_size);
cudaMemcpy(block_sums, d_block_sums, num_blocks * sizeof(float), cudaMemcpyDeviceToHost);
PrescanBlockSums(block_sums, num_blocks);
cudaMemcpy(d_block_sums, block_sums, num_blocks * sizeof(float), cudaMemcpyHostToDevice);
AddBlockSums<<<num_blocks, 2 * BLOCK_SIZE>>>(d_partial_sums, d_block_sums, data_size);
cudaMemcpy(partial_sums, d_partial_sums, data_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_block_sums);
cudaFree(d_partial_sums);
cudaFree(d_data);
free(block_sums);
}
void TotalPrescanCPU(const float * data, float * partial_sums, size_t data_size) {
float sum = 0.0;
for (size_t idx = 0; idx < data_size; ++idx) {
partial_sums[idx] = sum;
sum += data[idx];
}
}
int main(int argc, char * argv[]) {
float * data;
float * partial_sums;
size_t logsize = atoi(argv[1]);
size_t num_elements = (1 << logsize);
data = (float *) malloc(num_elements * sizeof(float));
partial_sums = (float *) malloc(num_elements * sizeof(float));
for (size_t idx = 0; idx < num_elements; ++idx) {
data[idx] = 1.0 * idx;
}
size_t num_runs = 100;
float runtimes[100];
float gpu_mean = 0.0;
float gpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanGPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
gpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
gpu_std += (gpu_mean - runtimes[run]) * (gpu_mean - runtimes[run]) / num_runs;
}
gpu_std = sqrt(gpu_std);
/*
float true_answer = 0.0;
bool correct = true;
for (size_t idx = 0; idx < num_elements - 1; ++idx) {
true_answer += idx;
if (true_answer != partial_sums[idx + 1]) {
correct = false;
std::cout << idx << " " << partial_sums[idx + 1] << " " << true_answer << std::endl;
}
}
if (!correct) {
std::cout << "incorrect" << std::endl;
}
*/
float cpu_mean = 0.0;
float cpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanCPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
cpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
cpu_std += (cpu_mean - runtimes[run]) * (cpu_mean - runtimes[run]) / num_runs;
}
cpu_std = sqrt(cpu_std);
std::cout << num_elements << " " << gpu_mean << " " << gpu_std << " " << cpu_mean << " " << cpu_std << std::endl;
free(data);
free(partial_sums);
return 0;
} | code for sm_80
Function : _Z12AddBlockSumsPfPKfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R3, R2, c[0x0][0x0], RZ ; /* 0x0000000002037a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R3, P1, R3, R0, RZ ; /* 0x0000000003037210 */
/* 0x002fc80007f3e0ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06070 */
/*0060*/ IMAD.X R6, RZ, RZ, RZ, P1 ; /* 0x000000ffff067224 */
/* 0x000fca00008e06ff */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R6, c[0x0][0x174], PT, P0 ; /* 0x00005d0006007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LEA R4, P1, R3.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580003047a11 */
/* 0x040fe200078210ff */
/*00c0*/ BSSY B0, 0x140 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*00d0*/ LEA.HI.X R5, R3, c[0x0][0x164], R6, 0x2, P1 ; /* 0x0000590003057a11 */
/* 0x000fce00008f1406 */
/*00e0*/ @P0 BRA 0x130 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0003 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0120*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDS R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x000ea40000000800 */
/*0170*/ FADD R3, R0, R3 ; /* 0x0000000300037221 */
/* 0x004fca0000000000 */
/*0180*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13PrescanBlocksPfPKfS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R3, R11, c[0x0][0x0], RZ ; /* 0x000000000b037a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R0, P1, R3, R2, RZ ; /* 0x0000000203007210 */
/* 0x002fc80007f3e0ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0060*/ IMAD.X R3, RZ, RZ, RZ, P1 ; /* 0x000000ffff037224 */
/* 0x000fca00008e06ff */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ LEA R6, P0, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000067a11 */
/* 0x000fe200078018ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ LEA.HI.X R7, R0, c[0x0][0x16c], R3, 0x3, P0 ; /* 0x00005b0000077a11 */
/* 0x000fca00000f1c03 */
/*00c0*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040606097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.SHL.U32 R4, R2.reuse, 0x2, RZ ; /* 0x0000000202047824 */
/* 0x040fe200078e00ff */
/*00f0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0110*/ UMOV UR9, 0x1 ; /* 0x0000000100097882 */
/* 0x000fe20000000000 */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0130*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0140*/ LOP3.LUT R13, R4, 0x1, RZ, 0xfc, !PT ; /* 0x00000001040d7812 */
/* 0x000fc400078efcff */
/*0150*/ LOP3.LUT P0, R5, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05057812 */
/* 0x000fcc000780c0ff */
/*0160*/ @!P1 IMAD.SHL.U32 R10, R14, 0x8, RZ ; /* 0x000000080e0a9824 */
/* 0x000fe200078e00ff */
/*0170*/ STS.64 [R4.X4], R8 ; /* 0x0000000804007388 */
/* 0x0041ec0000004a00 */
/*0180*/ @!P0 BRA 0x2d0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*01a0*/ UMOV UR9, 0x1 ; /* 0x0000000100097882 */
/* 0x000fe20000000000 */
/*01b0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*01c0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R7.reuse, R2, PT ; /* 0x000000020700720c */
/* 0x040fe20003f04070 */
/*01f0*/ USHF.L.U64.HI UR5, UR9, 0x1, UR5 ; /* 0x0000000109057899 */
/* 0x000fe20008010205 */
/*0200*/ SHF.R.U64 R7, R7, 0x1, R12 ; /* 0x0000000107077819 */
/* 0x000fc4000000120c */
/*0210*/ ISETP.GT.U32.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe40003f04100 */
/*0220*/ SHF.R.U32.HI R12, RZ, 0x1, R12 ; /* 0x00000001ff0c7819 */
/* 0x000fd6000001160c */
/*0230*/ @P0 IMAD R6, R13, UR9, RZ ; /* 0x000000090d060c24 */
/* 0x000fca000f8e02ff */
/*0240*/ @P0 IADD3 R8, R6, UR9, RZ ; /* 0x0000000906080c10 */
/* 0x001fe2000fffe0ff */
/*0250*/ USHF.L.U32 UR9, UR9, 0x1, URZ ; /* 0x0000000109097899 */
/* 0x000fe2000800063f */
/*0260*/ @P0 LDS R6, [R6.X4+-0x4] ; /* 0xfffffc0006060984 */
/* 0x000fe80000004800 */
/*0270*/ @P0 LDS R5, [R8.X4+-0x4] ; /* 0xfffffc0008050984 */
/* 0x000e240000004800 */
/*0280*/ @P0 FADD R5, R5, R6 ; /* 0x0000000605050221 */
/* 0x001fca0000000000 */
/*0290*/ @P0 STS [R8.X4+-0x4], R5 ; /* 0xfffffc0508000388 */
/* 0x0001e20000004800 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05070 */
/*02b0*/ ISETP.NE.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05300 */
/*02c0*/ @P0 BRA 0x1d0 ; /* 0xffffff0000000947 */
/* 0x001fea000383ffff */
/*02d0*/ @!P1 LDS R5, [R10+-0x4] ; /* 0xfffffc000a059984 */
/* 0x000e620000000800 */
/*02e0*/ IMAD.SHL.U32 R8, R14, 0x2, RZ ; /* 0x000000020e087824 */
/* 0x001fe400078e00ff */
/*02f0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff069424 */
/* 0x000fe200078e00ff */
/*0300*/ @!P1 STS [R10+-0x4], RZ ; /* 0xfffffcff0a009388 */
/* 0x0001e40000000800 */
/*0310*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0320*/ @!P1 IMAD.WIDE.U32 R6, R11, R6, c[0x0][0x170] ; /* 0x00005c000b069625 */
/* 0x000fca00078e0006 */
/*0330*/ @!P1 STG.E [R6.64], R5 ; /* 0x0000000506009986 */
/* 0x0021ee000c101906 */
/*0340*/ @!P0 BRA 0x4b0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0350*/ UMOV UR8, 0x1 ; /* 0x0000000100087882 */
/* 0x000fe40000000000 */
/*0360*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0370*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x001fe2000f8e00ff */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.LT.U32.AND P0, PT, R2, UR8, PT ; /* 0x0000000802007c0c */
/* 0x000fe2000bf01070 */
/*03a0*/ USHF.R.U64 UR9, UR9, 0x1, UR5 ; /* 0x0000000109097899 */
/* 0x000fc40008001205 */
/*03b0*/ USHF.L.U64.HI UR4, UR8, 0x1, UR4 ; /* 0x0000000108047899 */
/* 0x000fe20008010204 */
/*03c0*/ ISETP.GT.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f04100 */
/*03d0*/ USHF.L.U32 UR8, UR8, 0x1, URZ ; /* 0x0000000108087899 */
/* 0x000fe4000800063f */
/*03e0*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011605 */
/*03f0*/ IMAD.U32 R9, RZ, RZ, UR4 ; /* 0x00000004ff097e24 */
/* 0x000fd0000f8e00ff */
/*0400*/ @P0 IMAD R7, R13, UR9, RZ ; /* 0x000000090d070c24 */
/* 0x000fca000f8e02ff */
/*0410*/ @P0 IADD3 R12, R7, UR9, RZ ; /* 0x00000009070c0c10 */
/* 0x000fe2000fffe0ff */
/*0420*/ @P0 LDS R5, [R7.X4+-0x4] ; /* 0xfffffc0007050984 */
/* 0x000fe80000004800 */
/*0430*/ @P0 LDS R6, [R12.X4+-0x4] ; /* 0xfffffc000c060984 */
/* 0x000e280000004800 */
/*0440*/ @P0 STS [R7.X4+-0x4], R6 ; /* 0xfffffc0607000388 */
/* 0x001fe80000004800 */
/*0450*/ @P0 LDS R10, [R12.X4+-0x4] ; /* 0xfffffc000c0a0984 */
/* 0x000e240000004800 */
/*0460*/ @P0 FADD R5, R5, R10 ; /* 0x0000000a05050221 */
/* 0x001fca0000000000 */
/*0470*/ @P0 STS [R12.X4+-0x4], R5 ; /* 0xfffffc050c000388 */
/* 0x0001e20000004800 */
/*0480*/ ISETP.LE.U32.AND P0, PT, R8, UR8, PT ; /* 0x0000000808007c0c */
/* 0x000fc8000bf03070 */
/*0490*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f06100 */
/*04a0*/ @!P0 BRA 0x370 ; /* 0xfffffec000008947 */
/* 0x001fea000383ffff */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x2, RZ ; /* 0x0000000200067824 */
/* 0x041fe200078e00ff */
/*04d0*/ SHF.L.U64.HI R3, R0, 0x1, R3 ; /* 0x0000000100037819 */
/* 0x000fc80000010203 */
/*04e0*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fc800078010ff */
/*04f0*/ LEA.HI.X R3, R6, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fe200000f1403 */
/*0500*/ LDS.64 R4, [R4.X4] ; /* 0x0000000004047984 */
/* 0x000e280000004a00 */
/*0510*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe8000c101906 */
/*0520*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101906 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <ctime>
#define LOG_NUM_BANKS 5
#define NUM_BANKS 32
#define BLOCK_SIZE 64
#define DEBUG
#ifdef DEBUG
#define cudaCheckError(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "CUDA Error: %s at %s:%d\n",
cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#else
#define cudaCheckError(ans) ans
#endif
__device__ inline size_t NoConflictIndex(size_t index) {
return index;
// return index + (index >> LOG_NUM_BANKS);
}
__global__ void PrescanBlocks(float * out_data, const float * in_data, float * block_sums, const size_t data_size) {
// keeps all the in_data during processing
extern __shared__ float in_data_shared[];
size_t thread_id_local = threadIdx.x;
size_t offset = 1;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
in_data_shared[NoConflictIndex(2 * thread_id_local)] = in_data[2 * thread_id_global];
in_data_shared[NoConflictIndex(2 * thread_id_local + 1)] = in_data[2 * thread_id_global + 1];
for (size_t level_size = 2 * blockDim.x >> 1; level_size > 0; level_size >>= 1) {
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
in_data_shared[NoConflictIndex(parent_idx)] += in_data_shared[NoConflictIndex(left_son_idx)];
}
offset *= 2;
}
if (thread_id_local == 0) {
block_sums[blockIdx.x] = in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)];
in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)] = 0;
}
for (size_t level_size = 1; level_size < 2 * blockDim.x; level_size *= 2) {
offset >>= 1;
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
float left_son_value = in_data_shared[NoConflictIndex(left_son_idx)];
in_data_shared[NoConflictIndex(left_son_idx)] = in_data_shared[NoConflictIndex(parent_idx)];
in_data_shared[NoConflictIndex(parent_idx)] += left_son_value;
}
}
__syncthreads();
out_data[2 * thread_id_global] = in_data_shared[NoConflictIndex(2 * thread_id_local)];
out_data[2 * thread_id_global + 1] = in_data_shared[NoConflictIndex(2 * thread_id_local + 1)];
}
__global__ void AddBlockSums(float * data, const float * block_sums, const size_t data_size) {
__shared__ float this_block_sum;
size_t thread_id_local = threadIdx.x;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
if (thread_id_local == 0) {
this_block_sum = block_sums[blockIdx.x];
}
__syncthreads();
data[thread_id_global] += this_block_sum;
}
__host__ void PrescanBlockSums(float * block_sums, const size_t num_blocks) {
float sum = block_sums[0];
block_sums[0] = 0;
float keep;
for (size_t block_id = 1; block_id < num_blocks; ++block_id) {
keep = block_sums[block_id];
block_sums[block_id] = sum;
sum += keep;
}
}
void TotalPrescanGPU(const float * data, float * partial_sums, size_t data_size) {
float * d_data;
float * d_partial_sums;
float * d_block_sums;
float * block_sums;
size_t num_blocks = ((data_size + 2 * BLOCK_SIZE - 1) / (2 * BLOCK_SIZE));
size_t shared_size = ((2 * BLOCK_SIZE + NUM_BANKS - 1) / NUM_BANKS + BLOCK_SIZE) * 2 * sizeof(float);
block_sums = (float *) malloc(num_blocks * sizeof(float));
cudaCheckError( cudaMalloc(&d_data, data_size * sizeof(float)) );
cudaCheckError( cudaMalloc(&d_partial_sums, data_size * sizeof(float)) );
cudaCheckError( cudaMalloc(&d_block_sums, num_blocks * sizeof(float)) );
cudaMemcpy(d_data, data, data_size * sizeof(float), cudaMemcpyHostToDevice);
PrescanBlocks<<<num_blocks, BLOCK_SIZE, shared_size>>>(d_partial_sums, d_data, d_block_sums, data_size);
cudaMemcpy(block_sums, d_block_sums, num_blocks * sizeof(float), cudaMemcpyDeviceToHost);
PrescanBlockSums(block_sums, num_blocks);
cudaMemcpy(d_block_sums, block_sums, num_blocks * sizeof(float), cudaMemcpyHostToDevice);
AddBlockSums<<<num_blocks, 2 * BLOCK_SIZE>>>(d_partial_sums, d_block_sums, data_size);
cudaMemcpy(partial_sums, d_partial_sums, data_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_block_sums);
cudaFree(d_partial_sums);
cudaFree(d_data);
free(block_sums);
}
void TotalPrescanCPU(const float * data, float * partial_sums, size_t data_size) {
float sum = 0.0;
for (size_t idx = 0; idx < data_size; ++idx) {
partial_sums[idx] = sum;
sum += data[idx];
}
}
int main(int argc, char * argv[]) {
float * data;
float * partial_sums;
size_t logsize = atoi(argv[1]);
size_t num_elements = (1 << logsize);
data = (float *) malloc(num_elements * sizeof(float));
partial_sums = (float *) malloc(num_elements * sizeof(float));
for (size_t idx = 0; idx < num_elements; ++idx) {
data[idx] = 1.0 * idx;
}
size_t num_runs = 100;
float runtimes[100];
float gpu_mean = 0.0;
float gpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanGPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
gpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
gpu_std += (gpu_mean - runtimes[run]) * (gpu_mean - runtimes[run]) / num_runs;
}
gpu_std = sqrt(gpu_std);
/*
float true_answer = 0.0;
bool correct = true;
for (size_t idx = 0; idx < num_elements - 1; ++idx) {
true_answer += idx;
if (true_answer != partial_sums[idx + 1]) {
correct = false;
std::cout << idx << " " << partial_sums[idx + 1] << " " << true_answer << std::endl;
}
}
if (!correct) {
std::cout << "incorrect" << std::endl;
}
*/
float cpu_mean = 0.0;
float cpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanCPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
cpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
cpu_std += (cpu_mean - runtimes[run]) * (cpu_mean - runtimes[run]) / num_runs;
}
cpu_std = sqrt(cpu_std);
std::cout << num_elements << " " << gpu_mean << " " << gpu_std << " " << cpu_mean << " " << cpu_std << std::endl;
free(data);
free(partial_sums);
return 0;
} | .file "tmpxft_0014e457_00000000-6_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16PrescanBlockSumsPfm
.type _Z16PrescanBlockSumsPfm, @function
_Z16PrescanBlockSumsPfm:
.LFB3671:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
movl $0x00000000, (%rdi)
cmpq $1, %rsi
jbe .L3
leaq 4(%rdi), %rax
leaq (%rdi,%rsi,4), %rdx
.L5:
movss (%rax), %xmm1
movss %xmm0, (%rax)
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3671:
.size _Z16PrescanBlockSumsPfm, .-_Z16PrescanBlockSumsPfm
.globl _Z15TotalPrescanCPUPKfPfm
.type _Z15TotalPrescanCPUPKfPfm, @function
_Z15TotalPrescanCPUPKfPfm:
.LFB3673:
.cfi_startproc
endbr64
testq %rdx, %rdx
je .L7
movl $0, %eax
pxor %xmm0, %xmm0
.L9:
movss %xmm0, (%rsi,%rax,4)
addss (%rdi,%rax,4), %xmm0
addq $1, %rax
cmpq %rax, %rdx
jne .L9
.L7:
ret
.cfi_endproc
.LFE3673:
.size _Z15TotalPrescanCPUPKfPfm, .-_Z15TotalPrescanCPUPKfPfm
.globl _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
.type _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m, @function
_Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13PrescanBlocksPfPKfS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m, .-_Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
.globl _Z13PrescanBlocksPfPKfS_m
.type _Z13PrescanBlocksPfPKfS_m, @function
_Z13PrescanBlocksPfPKfS_m:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z13PrescanBlocksPfPKfS_m, .-_Z13PrescanBlocksPfPKfS_m
.globl _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
.type _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm, @function
_Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm:
.LFB3701:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12AddBlockSumsPfPKfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm, .-_Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
.globl _Z12AddBlockSumsPfPKfm
.type _Z12AddBlockSumsPfPKfm, @function
_Z12AddBlockSumsPfPKfm:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z12AddBlockSumsPfPKfm, .-_Z12AddBlockSumsPfPKfm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SchattenGenie/CUDTBoost/master/src/scan.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CUDA Error: %s at %s:%d\n"
.text
.globl _Z15TotalPrescanGPUPKfPfm
.type _Z15TotalPrescanGPUPKfPfm, @function
_Z15TotalPrescanGPUPKfPfm:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 127(%rdx), %rbp
shrq $7, %rbp
leaq 0(,%rbp,4), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
leaq 0(,%rbx,4), %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L36
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L37
movl $1, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $544, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L31:
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %r13, %rdi
call _Z16PrescanBlockSumsPfm
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L32:
movl $2, %ecx
movq %r14, %rdx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $121, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $122, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $123, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L38:
movq %rbx, %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
jmp .L31
.L39:
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
jmp .L32
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z15TotalPrescanGPUPKfPfm, .-_Z15TotalPrescanGPUPKfPfm
.section .rodata.str1.1
.LC5:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $488, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %r13d
movl %eax, %ecx
sall %cl, %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %r13, %r13
je .L42
movl $0, %eax
jmp .L45
.L43:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L44:
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%rax,4)
addq $1, %rax
cmpq %rax, %r13
je .L42
.L45:
testq %rax, %rax
js .L43
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L44
.L42:
leaq 64(%rsp), %rbx
leaq 464(%rsp), %rbp
movq %rbx, %r12
movl $0x00000000, 40(%rsp)
leaq 48(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 24(%rsp)
.L46:
movq 8(%rsp), %rdi
call cudaEventCreate@PLT
movq 24(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %r15
movq %r13, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call _Z15TotalPrescanGPUPKfPfm
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
divss .LC4(%rip), %xmm0
addss 40(%rsp), %xmm0
movss %xmm0, 40(%rsp)
addq $4, %r12
cmpq %rbp, %r12
jne .L46
movq %rbx, %rax
pxor %xmm1, %xmm1
movss .LC4(%rip), %xmm2
.L47:
movss 40(%rsp), %xmm0
subss (%rax), %xmm0
mulss %xmm0, %xmm0
divss %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rbp, %rax
jne .L47
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L64
sqrtss %xmm1, %xmm1
movss %xmm1, 44(%rsp)
.L50:
movq %rbx, %r12
movl $0x00000000, 8(%rsp)
leaq 48(%rsp), %rax
movq %rax, 24(%rsp)
leaq 56(%rsp), %rax
movq %rax, 32(%rsp)
.L51:
movq 24(%rsp), %rdi
call cudaEventCreate@PLT
movq 32(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %r15
movq %r13, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call _Z15TotalPrescanCPUPKfPfm
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
divss .LC4(%rip), %xmm0
addss 8(%rsp), %xmm0
movss %xmm0, 8(%rsp)
addq $4, %r12
cmpq %rbp, %r12
jne .L51
pxor %xmm1, %xmm1
movss .LC4(%rip), %xmm2
.L52:
movss 8(%rsp), %xmm0
subss (%rbx), %xmm0
mulss %xmm0, %xmm0
divss %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L52
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L65
sqrtss %xmm1, %xmm1
movss %xmm1, 24(%rsp)
.L55:
movq %r13, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 40(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
movaps %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 44(%rsp)
jmp .L50
.L65:
movaps %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 24(%rsp)
jmp .L55
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12AddBlockSumsPfPKfm"
.LC7:
.string "_Z13PrescanBlocksPfPKfS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12AddBlockSumsPfPKfm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13PrescanBlocksPfPKfS_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1148846080
.align 4
.LC4:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <ctime>
#define LOG_NUM_BANKS 5
#define NUM_BANKS 32
#define BLOCK_SIZE 64
#define DEBUG
#ifdef DEBUG
#define cudaCheckError(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "CUDA Error: %s at %s:%d\n",
cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#else
#define cudaCheckError(ans) ans
#endif
__device__ inline size_t NoConflictIndex(size_t index) {
return index;
// return index + (index >> LOG_NUM_BANKS);
}
__global__ void PrescanBlocks(float * out_data, const float * in_data, float * block_sums, const size_t data_size) {
// keeps all the in_data during processing
extern __shared__ float in_data_shared[];
size_t thread_id_local = threadIdx.x;
size_t offset = 1;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
in_data_shared[NoConflictIndex(2 * thread_id_local)] = in_data[2 * thread_id_global];
in_data_shared[NoConflictIndex(2 * thread_id_local + 1)] = in_data[2 * thread_id_global + 1];
for (size_t level_size = 2 * blockDim.x >> 1; level_size > 0; level_size >>= 1) {
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
in_data_shared[NoConflictIndex(parent_idx)] += in_data_shared[NoConflictIndex(left_son_idx)];
}
offset *= 2;
}
if (thread_id_local == 0) {
block_sums[blockIdx.x] = in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)];
in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)] = 0;
}
for (size_t level_size = 1; level_size < 2 * blockDim.x; level_size *= 2) {
offset >>= 1;
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
float left_son_value = in_data_shared[NoConflictIndex(left_son_idx)];
in_data_shared[NoConflictIndex(left_son_idx)] = in_data_shared[NoConflictIndex(parent_idx)];
in_data_shared[NoConflictIndex(parent_idx)] += left_son_value;
}
}
__syncthreads();
out_data[2 * thread_id_global] = in_data_shared[NoConflictIndex(2 * thread_id_local)];
out_data[2 * thread_id_global + 1] = in_data_shared[NoConflictIndex(2 * thread_id_local + 1)];
}
__global__ void AddBlockSums(float * data, const float * block_sums, const size_t data_size) {
__shared__ float this_block_sum;
size_t thread_id_local = threadIdx.x;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
if (thread_id_local == 0) {
this_block_sum = block_sums[blockIdx.x];
}
__syncthreads();
data[thread_id_global] += this_block_sum;
}
__host__ void PrescanBlockSums(float * block_sums, const size_t num_blocks) {
float sum = block_sums[0];
block_sums[0] = 0;
float keep;
for (size_t block_id = 1; block_id < num_blocks; ++block_id) {
keep = block_sums[block_id];
block_sums[block_id] = sum;
sum += keep;
}
}
void TotalPrescanGPU(const float * data, float * partial_sums, size_t data_size) {
float * d_data;
float * d_partial_sums;
float * d_block_sums;
float * block_sums;
size_t num_blocks = ((data_size + 2 * BLOCK_SIZE - 1) / (2 * BLOCK_SIZE));
size_t shared_size = ((2 * BLOCK_SIZE + NUM_BANKS - 1) / NUM_BANKS + BLOCK_SIZE) * 2 * sizeof(float);
block_sums = (float *) malloc(num_blocks * sizeof(float));
cudaCheckError( cudaMalloc(&d_data, data_size * sizeof(float)) );
cudaCheckError( cudaMalloc(&d_partial_sums, data_size * sizeof(float)) );
cudaCheckError( cudaMalloc(&d_block_sums, num_blocks * sizeof(float)) );
cudaMemcpy(d_data, data, data_size * sizeof(float), cudaMemcpyHostToDevice);
PrescanBlocks<<<num_blocks, BLOCK_SIZE, shared_size>>>(d_partial_sums, d_data, d_block_sums, data_size);
cudaMemcpy(block_sums, d_block_sums, num_blocks * sizeof(float), cudaMemcpyDeviceToHost);
PrescanBlockSums(block_sums, num_blocks);
cudaMemcpy(d_block_sums, block_sums, num_blocks * sizeof(float), cudaMemcpyHostToDevice);
AddBlockSums<<<num_blocks, 2 * BLOCK_SIZE>>>(d_partial_sums, d_block_sums, data_size);
cudaMemcpy(partial_sums, d_partial_sums, data_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_block_sums);
cudaFree(d_partial_sums);
cudaFree(d_data);
free(block_sums);
}
void TotalPrescanCPU(const float * data, float * partial_sums, size_t data_size) {
float sum = 0.0;
for (size_t idx = 0; idx < data_size; ++idx) {
partial_sums[idx] = sum;
sum += data[idx];
}
}
int main(int argc, char * argv[]) {
float * data;
float * partial_sums;
size_t logsize = atoi(argv[1]);
size_t num_elements = (1 << logsize);
data = (float *) malloc(num_elements * sizeof(float));
partial_sums = (float *) malloc(num_elements * sizeof(float));
for (size_t idx = 0; idx < num_elements; ++idx) {
data[idx] = 1.0 * idx;
}
size_t num_runs = 100;
float runtimes[100];
float gpu_mean = 0.0;
float gpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanGPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
gpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
gpu_std += (gpu_mean - runtimes[run]) * (gpu_mean - runtimes[run]) / num_runs;
}
gpu_std = sqrt(gpu_std);
/*
float true_answer = 0.0;
bool correct = true;
for (size_t idx = 0; idx < num_elements - 1; ++idx) {
true_answer += idx;
if (true_answer != partial_sums[idx + 1]) {
correct = false;
std::cout << idx << " " << partial_sums[idx + 1] << " " << true_answer << std::endl;
}
}
if (!correct) {
std::cout << "incorrect" << std::endl;
}
*/
float cpu_mean = 0.0;
float cpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanCPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
cpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
cpu_std += (cpu_mean - runtimes[run]) * (cpu_mean - runtimes[run]) / num_runs;
}
cpu_std = sqrt(cpu_std);
std::cout << num_elements << " " << gpu_mean << " " << gpu_std << " " << cpu_mean << " " << cpu_std << std::endl;
free(data);
free(partial_sums);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <ctime>
#define LOG_NUM_BANKS 5
#define NUM_BANKS 32
#define BLOCK_SIZE 64
#define DEBUG
#ifdef DEBUG
#define cudaCheckError(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr, "CUDA Error: %s at %s:%d\n",
hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#else
#define cudaCheckError(ans) ans
#endif
__device__ inline size_t NoConflictIndex(size_t index) {
return index;
// return index + (index >> LOG_NUM_BANKS);
}
__global__ void PrescanBlocks(float * out_data, const float * in_data, float * block_sums, const size_t data_size) {
// keeps all the in_data during processing
extern __shared__ float in_data_shared[];
size_t thread_id_local = threadIdx.x;
size_t offset = 1;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
in_data_shared[NoConflictIndex(2 * thread_id_local)] = in_data[2 * thread_id_global];
in_data_shared[NoConflictIndex(2 * thread_id_local + 1)] = in_data[2 * thread_id_global + 1];
for (size_t level_size = 2 * blockDim.x >> 1; level_size > 0; level_size >>= 1) {
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
in_data_shared[NoConflictIndex(parent_idx)] += in_data_shared[NoConflictIndex(left_son_idx)];
}
offset *= 2;
}
if (thread_id_local == 0) {
block_sums[blockIdx.x] = in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)];
in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)] = 0;
}
for (size_t level_size = 1; level_size < 2 * blockDim.x; level_size *= 2) {
offset >>= 1;
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
float left_son_value = in_data_shared[NoConflictIndex(left_son_idx)];
in_data_shared[NoConflictIndex(left_son_idx)] = in_data_shared[NoConflictIndex(parent_idx)];
in_data_shared[NoConflictIndex(parent_idx)] += left_son_value;
}
}
__syncthreads();
out_data[2 * thread_id_global] = in_data_shared[NoConflictIndex(2 * thread_id_local)];
out_data[2 * thread_id_global + 1] = in_data_shared[NoConflictIndex(2 * thread_id_local + 1)];
}
__global__ void AddBlockSums(float * data, const float * block_sums, const size_t data_size) {
__shared__ float this_block_sum;
size_t thread_id_local = threadIdx.x;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
if (thread_id_local == 0) {
this_block_sum = block_sums[blockIdx.x];
}
__syncthreads();
data[thread_id_global] += this_block_sum;
}
__host__ void PrescanBlockSums(float * block_sums, const size_t num_blocks) {
float sum = block_sums[0];
block_sums[0] = 0;
float keep;
for (size_t block_id = 1; block_id < num_blocks; ++block_id) {
keep = block_sums[block_id];
block_sums[block_id] = sum;
sum += keep;
}
}
void TotalPrescanGPU(const float * data, float * partial_sums, size_t data_size) {
float * d_data;
float * d_partial_sums;
float * d_block_sums;
float * block_sums;
size_t num_blocks = ((data_size + 2 * BLOCK_SIZE - 1) / (2 * BLOCK_SIZE));
size_t shared_size = ((2 * BLOCK_SIZE + NUM_BANKS - 1) / NUM_BANKS + BLOCK_SIZE) * 2 * sizeof(float);
block_sums = (float *) malloc(num_blocks * sizeof(float));
cudaCheckError( hipMalloc(&d_data, data_size * sizeof(float)) );
cudaCheckError( hipMalloc(&d_partial_sums, data_size * sizeof(float)) );
cudaCheckError( hipMalloc(&d_block_sums, num_blocks * sizeof(float)) );
hipMemcpy(d_data, data, data_size * sizeof(float), hipMemcpyHostToDevice);
PrescanBlocks<<<num_blocks, BLOCK_SIZE, shared_size>>>(d_partial_sums, d_data, d_block_sums, data_size);
hipMemcpy(block_sums, d_block_sums, num_blocks * sizeof(float), hipMemcpyDeviceToHost);
PrescanBlockSums(block_sums, num_blocks);
hipMemcpy(d_block_sums, block_sums, num_blocks * sizeof(float), hipMemcpyHostToDevice);
AddBlockSums<<<num_blocks, 2 * BLOCK_SIZE>>>(d_partial_sums, d_block_sums, data_size);
hipMemcpy(partial_sums, d_partial_sums, data_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_block_sums);
hipFree(d_partial_sums);
hipFree(d_data);
free(block_sums);
}
void TotalPrescanCPU(const float * data, float * partial_sums, size_t data_size) {
float sum = 0.0;
for (size_t idx = 0; idx < data_size; ++idx) {
partial_sums[idx] = sum;
sum += data[idx];
}
}
int main(int argc, char * argv[]) {
float * data;
float * partial_sums;
size_t logsize = atoi(argv[1]);
size_t num_elements = (1 << logsize);
data = (float *) malloc(num_elements * sizeof(float));
partial_sums = (float *) malloc(num_elements * sizeof(float));
for (size_t idx = 0; idx < num_elements; ++idx) {
data[idx] = 1.0 * idx;
}
size_t num_runs = 100;
float runtimes[100];
float gpu_mean = 0.0;
float gpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanGPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
gpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
gpu_std += (gpu_mean - runtimes[run]) * (gpu_mean - runtimes[run]) / num_runs;
}
gpu_std = sqrt(gpu_std);
/*
float true_answer = 0.0;
bool correct = true;
for (size_t idx = 0; idx < num_elements - 1; ++idx) {
true_answer += idx;
if (true_answer != partial_sums[idx + 1]) {
correct = false;
std::cout << idx << " " << partial_sums[idx + 1] << " " << true_answer << std::endl;
}
}
if (!correct) {
std::cout << "incorrect" << std::endl;
}
*/
float cpu_mean = 0.0;
float cpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanCPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
cpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
cpu_std += (cpu_mean - runtimes[run]) * (cpu_mean - runtimes[run]) / num_runs;
}
cpu_std = sqrt(cpu_std);
std::cout << num_elements << " " << gpu_mean << " " << gpu_std << " " << cpu_mean << " " << cpu_std << std::endl;
free(data);
free(partial_sums);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <ctime>
#define LOG_NUM_BANKS 5
#define NUM_BANKS 32
#define BLOCK_SIZE 64
#define DEBUG
#ifdef DEBUG
#define cudaCheckError(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr, "CUDA Error: %s at %s:%d\n",
hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#else
#define cudaCheckError(ans) ans
#endif
__device__ inline size_t NoConflictIndex(size_t index) {
return index;
// return index + (index >> LOG_NUM_BANKS);
}
__global__ void PrescanBlocks(float * out_data, const float * in_data, float * block_sums, const size_t data_size) {
// keeps all the in_data during processing
extern __shared__ float in_data_shared[];
size_t thread_id_local = threadIdx.x;
size_t offset = 1;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
in_data_shared[NoConflictIndex(2 * thread_id_local)] = in_data[2 * thread_id_global];
in_data_shared[NoConflictIndex(2 * thread_id_local + 1)] = in_data[2 * thread_id_global + 1];
for (size_t level_size = 2 * blockDim.x >> 1; level_size > 0; level_size >>= 1) {
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
in_data_shared[NoConflictIndex(parent_idx)] += in_data_shared[NoConflictIndex(left_son_idx)];
}
offset *= 2;
}
if (thread_id_local == 0) {
block_sums[blockIdx.x] = in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)];
in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)] = 0;
}
for (size_t level_size = 1; level_size < 2 * blockDim.x; level_size *= 2) {
offset >>= 1;
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
float left_son_value = in_data_shared[NoConflictIndex(left_son_idx)];
in_data_shared[NoConflictIndex(left_son_idx)] = in_data_shared[NoConflictIndex(parent_idx)];
in_data_shared[NoConflictIndex(parent_idx)] += left_son_value;
}
}
__syncthreads();
out_data[2 * thread_id_global] = in_data_shared[NoConflictIndex(2 * thread_id_local)];
out_data[2 * thread_id_global + 1] = in_data_shared[NoConflictIndex(2 * thread_id_local + 1)];
}
__global__ void AddBlockSums(float * data, const float * block_sums, const size_t data_size) {
__shared__ float this_block_sum;
size_t thread_id_local = threadIdx.x;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
if (thread_id_local == 0) {
this_block_sum = block_sums[blockIdx.x];
}
__syncthreads();
data[thread_id_global] += this_block_sum;
}
__host__ void PrescanBlockSums(float * block_sums, const size_t num_blocks) {
float sum = block_sums[0];
block_sums[0] = 0;
float keep;
for (size_t block_id = 1; block_id < num_blocks; ++block_id) {
keep = block_sums[block_id];
block_sums[block_id] = sum;
sum += keep;
}
}
void TotalPrescanGPU(const float * data, float * partial_sums, size_t data_size) {
float * d_data;
float * d_partial_sums;
float * d_block_sums;
float * block_sums;
size_t num_blocks = ((data_size + 2 * BLOCK_SIZE - 1) / (2 * BLOCK_SIZE));
size_t shared_size = ((2 * BLOCK_SIZE + NUM_BANKS - 1) / NUM_BANKS + BLOCK_SIZE) * 2 * sizeof(float);
block_sums = (float *) malloc(num_blocks * sizeof(float));
cudaCheckError( hipMalloc(&d_data, data_size * sizeof(float)) );
cudaCheckError( hipMalloc(&d_partial_sums, data_size * sizeof(float)) );
cudaCheckError( hipMalloc(&d_block_sums, num_blocks * sizeof(float)) );
hipMemcpy(d_data, data, data_size * sizeof(float), hipMemcpyHostToDevice);
PrescanBlocks<<<num_blocks, BLOCK_SIZE, shared_size>>>(d_partial_sums, d_data, d_block_sums, data_size);
hipMemcpy(block_sums, d_block_sums, num_blocks * sizeof(float), hipMemcpyDeviceToHost);
PrescanBlockSums(block_sums, num_blocks);
hipMemcpy(d_block_sums, block_sums, num_blocks * sizeof(float), hipMemcpyHostToDevice);
AddBlockSums<<<num_blocks, 2 * BLOCK_SIZE>>>(d_partial_sums, d_block_sums, data_size);
hipMemcpy(partial_sums, d_partial_sums, data_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_block_sums);
hipFree(d_partial_sums);
hipFree(d_data);
free(block_sums);
}
void TotalPrescanCPU(const float * data, float * partial_sums, size_t data_size) {
float sum = 0.0;
for (size_t idx = 0; idx < data_size; ++idx) {
partial_sums[idx] = sum;
sum += data[idx];
}
}
int main(int argc, char * argv[]) {
float * data;
float * partial_sums;
size_t logsize = atoi(argv[1]);
size_t num_elements = (1 << logsize);
data = (float *) malloc(num_elements * sizeof(float));
partial_sums = (float *) malloc(num_elements * sizeof(float));
for (size_t idx = 0; idx < num_elements; ++idx) {
data[idx] = 1.0 * idx;
}
size_t num_runs = 100;
float runtimes[100];
float gpu_mean = 0.0;
float gpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanGPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
gpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
gpu_std += (gpu_mean - runtimes[run]) * (gpu_mean - runtimes[run]) / num_runs;
}
gpu_std = sqrt(gpu_std);
/*
float true_answer = 0.0;
bool correct = true;
for (size_t idx = 0; idx < num_elements - 1; ++idx) {
true_answer += idx;
if (true_answer != partial_sums[idx + 1]) {
correct = false;
std::cout << idx << " " << partial_sums[idx + 1] << " " << true_answer << std::endl;
}
}
if (!correct) {
std::cout << "incorrect" << std::endl;
}
*/
float cpu_mean = 0.0;
float cpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanCPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
cpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
cpu_std += (cpu_mean - runtimes[run]) * (cpu_mean - runtimes[run]) / num_runs;
}
cpu_std = sqrt(cpu_std);
std::cout << num_elements << " " << gpu_mean << " " << gpu_std << " " << cpu_mean << " " << cpu_std << std::endl;
free(data);
free(partial_sums);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13PrescanBlocksPfPKfS_m
.globl _Z13PrescanBlocksPfPKfS_m
.p2align 8
.type _Z13PrescanBlocksPfPKfS_m,@function
_Z13PrescanBlocksPfPKfS_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s2
v_add_co_u32 v6, s7, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, null, 0, 0, s7
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[6:7]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_15
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 1, v[6:7]
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_cmp_eq_u16_e64 s3, s3, 0
s_mov_b32 s6, s15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, 1, v2
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_and_b32 vcc_lo, exec_lo, s3
s_clause 0x1
global_load_b32 v10, v[6:7], off
global_load_b32 v11, v[8:9], off
v_lshlrev_b32_e32 v9, 1, v0
v_lshl_add_u32 v7, v0, 3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v8, 1, v9
v_lshl_add_u32 v6, v8, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_cbranch_vccnz .LBB0_6
v_add_co_u32 v10, null, v9, 2
s_mov_b32 s3, 0
s_mov_b64 s[4:5], 1
s_mov_b64 s[8:9], s[2:3]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_u64_e64 s3, s[8:9], 2
s_lshl_b64 s[4:5], s[4:5], 1
s_lshr_b64 s[8:9], s[8:9], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_7
.LBB0_4:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u64_e64 s[8:9], v[0:1]
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v11, s4, v8
v_mul_lo_u32 v12, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v11, 2, v11
v_lshlrev_b32_e32 v12, 2, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v11, v11, 0, -4
v_add3_u32 v12, v12, 0, -4
ds_load_b32 v11, v11
ds_load_b32 v13, v12
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v11, v11, v13
ds_store_b32 v12, v11
s_branch .LBB0_3
.LBB0_6:
s_mov_b64 s[4:5], 1
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s7, 0
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_lshl_b32 s8, s2, 3
s_lshl_b64 s[6:7], s[6:7], 2
s_add_i32 s8, s8, 0
v_mov_b32_e32 v12, 0
s_add_i32 s8, s8, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v10, s8
s_load_b64 s[8:9], s[0:1], 0x10
ds_load_b32 v11, v10
ds_store_b32 v10, v12
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s8, s6
s_addc_u32 s7, s9, s7
global_store_b32 v12, v11, s[6:7]
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_14
v_add_co_u32 v9, null, v9, 2
s_lshl_b32 s2, s2, 1
s_mov_b32 s3, 0
s_mov_b64 s[6:7], 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
s_lshl_b64 s[6:7], s[6:7], 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s8, s[6:7], s[2:3]
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_14
.LBB0_12:
s_lshr_b64 s[4:5], s[4:5], 1
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_11
v_mul_lo_u32 v10, s4, v9
v_mul_lo_u32 v12, s4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v10, 2, v10
v_lshlrev_b32_e32 v12, 2, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v10, v10, 0, -4
v_add3_u32 v12, v12, 0, -4
ds_load_b32 v11, v10
ds_load_b32 v13, v12
s_waitcnt lgkmcnt(1)
ds_store_b32 v12, v11
ds_load_b32 v11, v10
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v11, v13, v11
ds_store_b32 v10, v11
s_branch .LBB0_11
.LBB0_14:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v7, v7
ds_load_b32 v6, v6
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt lgkmcnt(1)
global_store_b32 v[0:1], v7, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v6, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13PrescanBlocksPfPKfS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13PrescanBlocksPfPKfS_m, .Lfunc_end0-_Z13PrescanBlocksPfPKfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12AddBlockSumsPfPKfm
.globl _Z12AddBlockSumsPfPKfm
.p2align 8
.type _Z12AddBlockSumsPfPKfm,@function
_Z12AddBlockSumsPfPKfm:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s15, s3
v_add_co_u32 v1, s3, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, 0, 0, s3
s_mov_b32 s3, exec_lo
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB1_4
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s2
ds_store_b32 v0, v3
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v3, 0
ds_load_b32 v3, v3
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12AddBlockSumsPfPKfm
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12AddBlockSumsPfPKfm, .Lfunc_end1-_Z12AddBlockSumsPfPKfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13PrescanBlocksPfPKfS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13PrescanBlocksPfPKfS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12AddBlockSumsPfPKfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12AddBlockSumsPfPKfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <ctime>
#define LOG_NUM_BANKS 5
#define NUM_BANKS 32
#define BLOCK_SIZE 64
#define DEBUG
#ifdef DEBUG
#define cudaCheckError(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr, "CUDA Error: %s at %s:%d\n",
hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#else
#define cudaCheckError(ans) ans
#endif
__device__ inline size_t NoConflictIndex(size_t index) {
return index;
// return index + (index >> LOG_NUM_BANKS);
}
__global__ void PrescanBlocks(float * out_data, const float * in_data, float * block_sums, const size_t data_size) {
// keeps all the in_data during processing
extern __shared__ float in_data_shared[];
size_t thread_id_local = threadIdx.x;
size_t offset = 1;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
in_data_shared[NoConflictIndex(2 * thread_id_local)] = in_data[2 * thread_id_global];
in_data_shared[NoConflictIndex(2 * thread_id_local + 1)] = in_data[2 * thread_id_global + 1];
for (size_t level_size = 2 * blockDim.x >> 1; level_size > 0; level_size >>= 1) {
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
in_data_shared[NoConflictIndex(parent_idx)] += in_data_shared[NoConflictIndex(left_son_idx)];
}
offset *= 2;
}
if (thread_id_local == 0) {
block_sums[blockIdx.x] = in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)];
in_data_shared[NoConflictIndex(blockDim.x * 2 - 1)] = 0;
}
for (size_t level_size = 1; level_size < 2 * blockDim.x; level_size *= 2) {
offset >>= 1;
__syncthreads();
if (thread_id_local < level_size) {
size_t left_son_idx = offset * (2 * thread_id_local + 1) - 1;
size_t parent_idx = offset * (2 * thread_id_local + 2) - 1;
float left_son_value = in_data_shared[NoConflictIndex(left_son_idx)];
in_data_shared[NoConflictIndex(left_son_idx)] = in_data_shared[NoConflictIndex(parent_idx)];
in_data_shared[NoConflictIndex(parent_idx)] += left_son_value;
}
}
__syncthreads();
out_data[2 * thread_id_global] = in_data_shared[NoConflictIndex(2 * thread_id_local)];
out_data[2 * thread_id_global + 1] = in_data_shared[NoConflictIndex(2 * thread_id_local + 1)];
}
__global__ void AddBlockSums(float * data, const float * block_sums, const size_t data_size) {
__shared__ float this_block_sum;
size_t thread_id_local = threadIdx.x;
size_t thread_id_global = blockIdx.x * blockDim.x + thread_id_local;
if (thread_id_global >= data_size) {
return;
}
if (thread_id_local == 0) {
this_block_sum = block_sums[blockIdx.x];
}
__syncthreads();
data[thread_id_global] += this_block_sum;
}
__host__ void PrescanBlockSums(float * block_sums, const size_t num_blocks) {
float sum = block_sums[0];
block_sums[0] = 0;
float keep;
for (size_t block_id = 1; block_id < num_blocks; ++block_id) {
keep = block_sums[block_id];
block_sums[block_id] = sum;
sum += keep;
}
}
void TotalPrescanGPU(const float * data, float * partial_sums, size_t data_size) {
float * d_data;
float * d_partial_sums;
float * d_block_sums;
float * block_sums;
size_t num_blocks = ((data_size + 2 * BLOCK_SIZE - 1) / (2 * BLOCK_SIZE));
size_t shared_size = ((2 * BLOCK_SIZE + NUM_BANKS - 1) / NUM_BANKS + BLOCK_SIZE) * 2 * sizeof(float);
block_sums = (float *) malloc(num_blocks * sizeof(float));
cudaCheckError( hipMalloc(&d_data, data_size * sizeof(float)) );
cudaCheckError( hipMalloc(&d_partial_sums, data_size * sizeof(float)) );
cudaCheckError( hipMalloc(&d_block_sums, num_blocks * sizeof(float)) );
hipMemcpy(d_data, data, data_size * sizeof(float), hipMemcpyHostToDevice);
PrescanBlocks<<<num_blocks, BLOCK_SIZE, shared_size>>>(d_partial_sums, d_data, d_block_sums, data_size);
hipMemcpy(block_sums, d_block_sums, num_blocks * sizeof(float), hipMemcpyDeviceToHost);
PrescanBlockSums(block_sums, num_blocks);
hipMemcpy(d_block_sums, block_sums, num_blocks * sizeof(float), hipMemcpyHostToDevice);
AddBlockSums<<<num_blocks, 2 * BLOCK_SIZE>>>(d_partial_sums, d_block_sums, data_size);
hipMemcpy(partial_sums, d_partial_sums, data_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_block_sums);
hipFree(d_partial_sums);
hipFree(d_data);
free(block_sums);
}
void TotalPrescanCPU(const float * data, float * partial_sums, size_t data_size) {
float sum = 0.0;
for (size_t idx = 0; idx < data_size; ++idx) {
partial_sums[idx] = sum;
sum += data[idx];
}
}
int main(int argc, char * argv[]) {
float * data;
float * partial_sums;
size_t logsize = atoi(argv[1]);
size_t num_elements = (1 << logsize);
data = (float *) malloc(num_elements * sizeof(float));
partial_sums = (float *) malloc(num_elements * sizeof(float));
for (size_t idx = 0; idx < num_elements; ++idx) {
data[idx] = 1.0 * idx;
}
size_t num_runs = 100;
float runtimes[100];
float gpu_mean = 0.0;
float gpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanGPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
gpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
gpu_std += (gpu_mean - runtimes[run]) * (gpu_mean - runtimes[run]) / num_runs;
}
gpu_std = sqrt(gpu_std);
/*
float true_answer = 0.0;
bool correct = true;
for (size_t idx = 0; idx < num_elements - 1; ++idx) {
true_answer += idx;
if (true_answer != partial_sums[idx + 1]) {
correct = false;
std::cout << idx << " " << partial_sums[idx + 1] << " " << true_answer << std::endl;
}
}
if (!correct) {
std::cout << "incorrect" << std::endl;
}
*/
float cpu_mean = 0.0;
float cpu_std = 0.0;
for (size_t run = 0; run < num_runs; ++run) {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// cudaEventRecord(start);
const clock_t begin_time = clock();
TotalPrescanCPU(data, partial_sums, num_elements);
float milliseconds = float(clock () - begin_time) / 1000;
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// float milliseconds = 0;
// cudaEventElapsedTime(&milliseconds, start, stop);
// std::cout << "GPU run took " << milliseconds << " ms" << std::endl;
runtimes[run] = milliseconds;
cpu_mean += milliseconds / num_runs;
}
for (size_t run = 0; run < num_runs; ++run) {
cpu_std += (cpu_mean - runtimes[run]) * (cpu_mean - runtimes[run]) / num_runs;
}
cpu_std = sqrt(cpu_std);
std::cout << num_elements << " " << gpu_mean << " " << gpu_std << " " << cpu_mean << " " << cpu_std << std::endl;
free(data);
free(partial_sums);
return 0;
} | .text
.file "scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__PrescanBlocksPfPKfS_m # -- Begin function _Z28__device_stub__PrescanBlocksPfPKfS_m
.p2align 4, 0x90
.type _Z28__device_stub__PrescanBlocksPfPKfS_m,@function
_Z28__device_stub__PrescanBlocksPfPKfS_m: # @_Z28__device_stub__PrescanBlocksPfPKfS_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13PrescanBlocksPfPKfS_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__PrescanBlocksPfPKfS_m, .Lfunc_end0-_Z28__device_stub__PrescanBlocksPfPKfS_m
.cfi_endproc
# -- End function
.globl _Z27__device_stub__AddBlockSumsPfPKfm # -- Begin function _Z27__device_stub__AddBlockSumsPfPKfm
.p2align 4, 0x90
.type _Z27__device_stub__AddBlockSumsPfPKfm,@function
_Z27__device_stub__AddBlockSumsPfPKfm: # @_Z27__device_stub__AddBlockSumsPfPKfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12AddBlockSumsPfPKfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__AddBlockSumsPfPKfm, .Lfunc_end1-_Z27__device_stub__AddBlockSumsPfPKfm
.cfi_endproc
# -- End function
.globl _Z16PrescanBlockSumsPfm # -- Begin function _Z16PrescanBlockSumsPfm
.p2align 4, 0x90
.type _Z16PrescanBlockSumsPfm,@function
_Z16PrescanBlockSumsPfm: # @_Z16PrescanBlockSumsPfm
.cfi_startproc
# %bb.0:
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $0, (%rdi)
cmpq $2, %rsi
jb .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl $1, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm0, (%rdi,%rax,4)
incq %rax
movaps %xmm1, %xmm0
cmpq %rax, %rsi
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z16PrescanBlockSumsPfm, .Lfunc_end2-_Z16PrescanBlockSumsPfm
.cfi_endproc
# -- End function
.globl _Z15TotalPrescanGPUPKfPfm # -- Begin function _Z15TotalPrescanGPUPKfPfm
.p2align 4, 0x90
.type _Z15TotalPrescanGPUPKfPfm,@function
_Z15TotalPrescanGPUPKfPfm: # @_Z15TotalPrescanGPUPKfPfm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movq %rsi, %rbp
movq %rdi, %r14
leaq 127(%rdx), %r12
movq %r12, 152(%rsp) # 8-byte Spill
shrq $7, %r12
leaq (,%r12,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r15, 104(%rsp) # 8-byte Spill
leaq (,%r15,4), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_Z10cudaAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_Z10cudaAssert10hipError_tPKcib.exit28
movq %rbp, 144(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z10cudaAssert10hipError_tPKcib.exit30
movabsq $4294967296, %rbp # imm = 0x100000000
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %r14d
orq %rbp, %r14
leaq 64(%rbp), %rdx
movl $544, %r8d # imm = 0x220
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movq %rax, 40(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13PrescanBlocksPfPKfS_m, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $0, (%rbx)
cmpq $256, 152(%rsp) # 8-byte Folded Reload
# imm = 0x100
jb .LBB3_12
# %bb.10: # %.lr.ph.i.preheader
movl $1, %eax
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm0, (%rbx,%rax,4)
incq %rax
movaps %xmm1, %xmm0
cmpq %rax, %r12
jne .LBB3_11
.LBB3_12: # %_Z16PrescanBlockSumsPfm.exit
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
subq $-128, %rbp
movq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12AddBlockSumsPfPKfm, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
movq 16(%rsp), %rsi
movq 144(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size _Z15TotalPrescanGPUPKfPfm, .Lfunc_end3-_Z15TotalPrescanGPUPKfPfm
.cfi_endproc
# -- End function
.globl _Z15TotalPrescanCPUPKfPfm # -- Begin function _Z15TotalPrescanCPUPKfPfm
.p2align 4, 0x90
.type _Z15TotalPrescanCPUPKfPfm,@function
_Z15TotalPrescanCPUPKfPfm: # @_Z15TotalPrescanCPUPKfPfm
.cfi_startproc
# %bb.0:
testq %rdx, %rdx
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rsi,%rax,4)
addss (%rdi,%rax,4), %xmm0
incq %rax
cmpq %rax, %rdx
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z15TotalPrescanCPUPKfPfm, .Lfunc_end4-_Z15TotalPrescanCPUPKfPfm
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI5_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI5_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_2:
.long 0x447a0000 # float 1000
.LCPI5_3:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $1, %edx
movl %eax, %ecx
shll %cl, %edx
movslq %edx, %r15
leaq (,%r15,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
movdqa .LCPI5_0(%rip), %xmm0 # xmm0 = [1127219200,1160773632,0,0]
movapd .LCPI5_1(%rip), %xmm1 # xmm1 = [4.503599627370496E+15,1.9342813113834067E+25]
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movq %r12, %xmm2
punpckldq %xmm0, %xmm2 # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
subpd %xmm1, %xmm2
movapd %xmm2, %xmm3
unpckhpd %xmm2, %xmm3 # xmm3 = xmm3[1],xmm2[1]
addsd %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtsd2ss %xmm3, %xmm2
movss %xmm2, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB5_1
# %bb.2:
xorps %xmm2, %xmm2
xorl %r12d, %r12d
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movss %xmm2, 4(%rsp) # 4-byte Spill
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r13, %rdi
callq hipEventCreate
callq clock
movq %rax, %rbp
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z15TotalPrescanGPUPKfPfm
callq clock
movss .LCPI5_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI5_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss 4(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, 32(%rsp,%r12,4)
divss %xmm3, %xmm0
addss %xmm0, %xmm2
incq %r12
cmpq $100, %r12
jne .LBB5_3
# %bb.4: # %.preheader70.preheader
pxor %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_5: # %.preheader70
# =>This Inner Loop Header: Depth=1
movaps %xmm2, %xmm1
subss 32(%rsp,%rax,4), %xmm1
mulss %xmm1, %xmm1
divss %xmm3, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $100, %rax
jne .LBB5_5
# %bb.6:
xorps %xmm3, %xmm3
ucomiss %xmm3, %xmm0
movss %xmm2, 4(%rsp) # 4-byte Spill
jb .LBB5_8
# %bb.7:
sqrtss %xmm0, %xmm0
jmp .LBB5_9
.LBB5_8: # %call.sqrt
callq sqrtf@PLT
xorps %xmm3, %xmm3
.LBB5_9: # %.split
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %r12d, %r12d
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB5_10: # =>This Loop Header: Depth=1
# Child Loop BB5_11 Depth 2
movss %xmm3, (%rsp) # 4-byte Spill
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r13, %rdi
callq hipEventCreate
callq clock
xorps %xmm0, %xmm0
movq %rax, %rbp
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_11: # %.lr.ph.i
# Parent Loop BB5_10 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%r14,%rax,4)
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq %rax, %r15
jne .LBB5_11
# %bb.12: # %_Z15TotalPrescanCPUPKfPfm.exit
# in Loop: Header=BB5_10 Depth=1
callq clock
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_2(%rip), %xmm0
movss %xmm0, 32(%rsp,%r12,4)
movss .LCPI5_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm2, %xmm0
movss (%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
incq %r12
cmpq $100, %r12
jne .LBB5_10
# %bb.13: # %.preheader.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movaps %xmm3, %xmm1
subss 32(%rsp,%rax,4), %xmm1
mulss %xmm1, %xmm1
divss %xmm2, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $100, %rax
jne .LBB5_14
# %bb.15:
movss %xmm3, (%rsp) # 4-byte Spill
xorpd %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB5_17
# %bb.16:
sqrtss %xmm0, %xmm0
jmp .LBB5_18
.LBB5_17: # %call.sqrt102
callq sqrtf@PLT
.LBB5_18: # %.split101
movss %xmm0, 8(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB5_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB5_21
# %bb.20:
movzbl 67(%r15), %ecx
jmp .LBB5_22
.LBB5_21:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB5_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_23:
.cfi_def_cfa_offset 496
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13PrescanBlocksPfPKfS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12AddBlockSumsPfPKfm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13PrescanBlocksPfPKfS_m,@object # @_Z13PrescanBlocksPfPKfS_m
.section .rodata,"a",@progbits
.globl _Z13PrescanBlocksPfPKfS_m
.p2align 3, 0x0
_Z13PrescanBlocksPfPKfS_m:
.quad _Z28__device_stub__PrescanBlocksPfPKfS_m
.size _Z13PrescanBlocksPfPKfS_m, 8
.type _Z12AddBlockSumsPfPKfm,@object # @_Z12AddBlockSumsPfPKfm
.globl _Z12AddBlockSumsPfPKfm
.p2align 3, 0x0
_Z12AddBlockSumsPfPKfm:
.quad _Z27__device_stub__AddBlockSumsPfPKfm
.size _Z12AddBlockSumsPfPKfm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SchattenGenie/CUDTBoost/master/src/scan.hip"
.size .L.str, 101
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA Error: %s at %s:%d\n"
.size .L.str.2, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13PrescanBlocksPfPKfS_m"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12AddBlockSumsPfPKfm"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__PrescanBlocksPfPKfS_m
.addrsig_sym _Z27__device_stub__AddBlockSumsPfPKfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13PrescanBlocksPfPKfS_m
.addrsig_sym _Z12AddBlockSumsPfPKfm
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12AddBlockSumsPfPKfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R3, R2, c[0x0][0x0], RZ ; /* 0x0000000002037a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R3, P1, R3, R0, RZ ; /* 0x0000000003037210 */
/* 0x002fc80007f3e0ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06070 */
/*0060*/ IMAD.X R6, RZ, RZ, RZ, P1 ; /* 0x000000ffff067224 */
/* 0x000fca00008e06ff */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R6, c[0x0][0x174], PT, P0 ; /* 0x00005d0006007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LEA R4, P1, R3.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580003047a11 */
/* 0x040fe200078210ff */
/*00c0*/ BSSY B0, 0x140 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*00d0*/ LEA.HI.X R5, R3, c[0x0][0x164], R6, 0x2, P1 ; /* 0x0000590003057a11 */
/* 0x000fce00008f1406 */
/*00e0*/ @P0 BRA 0x130 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0003 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0120*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e40000000800 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDS R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x000ea40000000800 */
/*0170*/ FADD R3, R0, R3 ; /* 0x0000000300037221 */
/* 0x004fca0000000000 */
/*0180*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13PrescanBlocksPfPKfS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R3, R11, c[0x0][0x0], RZ ; /* 0x000000000b037a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R0, P1, R3, R2, RZ ; /* 0x0000000203007210 */
/* 0x002fc80007f3e0ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0060*/ IMAD.X R3, RZ, RZ, RZ, P1 ; /* 0x000000ffff037224 */
/* 0x000fca00008e06ff */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ LEA R6, P0, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000067a11 */
/* 0x000fe200078018ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ LEA.HI.X R7, R0, c[0x0][0x16c], R3, 0x3, P0 ; /* 0x00005b0000077a11 */
/* 0x000fca00000f1c03 */
/*00c0*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040606097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.SHL.U32 R4, R2.reuse, 0x2, RZ ; /* 0x0000000202047824 */
/* 0x040fe200078e00ff */
/*00f0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0110*/ UMOV UR9, 0x1 ; /* 0x0000000100097882 */
/* 0x000fe20000000000 */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0130*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0140*/ LOP3.LUT R13, R4, 0x1, RZ, 0xfc, !PT ; /* 0x00000001040d7812 */
/* 0x000fc400078efcff */
/*0150*/ LOP3.LUT P0, R5, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05057812 */
/* 0x000fcc000780c0ff */
/*0160*/ @!P1 IMAD.SHL.U32 R10, R14, 0x8, RZ ; /* 0x000000080e0a9824 */
/* 0x000fe200078e00ff */
/*0170*/ STS.64 [R4.X4], R8 ; /* 0x0000000804007388 */
/* 0x0041ec0000004a00 */
/*0180*/ @!P0 BRA 0x2d0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*01a0*/ UMOV UR9, 0x1 ; /* 0x0000000100097882 */
/* 0x000fe20000000000 */
/*01b0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*01c0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R7.reuse, R2, PT ; /* 0x000000020700720c */
/* 0x040fe20003f04070 */
/*01f0*/ USHF.L.U64.HI UR5, UR9, 0x1, UR5 ; /* 0x0000000109057899 */
/* 0x000fe20008010205 */
/*0200*/ SHF.R.U64 R7, R7, 0x1, R12 ; /* 0x0000000107077819 */
/* 0x000fc4000000120c */
/*0210*/ ISETP.GT.U32.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe40003f04100 */
/*0220*/ SHF.R.U32.HI R12, RZ, 0x1, R12 ; /* 0x00000001ff0c7819 */
/* 0x000fd6000001160c */
/*0230*/ @P0 IMAD R6, R13, UR9, RZ ; /* 0x000000090d060c24 */
/* 0x000fca000f8e02ff */
/*0240*/ @P0 IADD3 R8, R6, UR9, RZ ; /* 0x0000000906080c10 */
/* 0x001fe2000fffe0ff */
/*0250*/ USHF.L.U32 UR9, UR9, 0x1, URZ ; /* 0x0000000109097899 */
/* 0x000fe2000800063f */
/*0260*/ @P0 LDS R6, [R6.X4+-0x4] ; /* 0xfffffc0006060984 */
/* 0x000fe80000004800 */
/*0270*/ @P0 LDS R5, [R8.X4+-0x4] ; /* 0xfffffc0008050984 */
/* 0x000e240000004800 */
/*0280*/ @P0 FADD R5, R5, R6 ; /* 0x0000000605050221 */
/* 0x001fca0000000000 */
/*0290*/ @P0 STS [R8.X4+-0x4], R5 ; /* 0xfffffc0508000388 */
/* 0x0001e20000004800 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05070 */
/*02b0*/ ISETP.NE.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05300 */
/*02c0*/ @P0 BRA 0x1d0 ; /* 0xffffff0000000947 */
/* 0x001fea000383ffff */
/*02d0*/ @!P1 LDS R5, [R10+-0x4] ; /* 0xfffffc000a059984 */
/* 0x000e620000000800 */
/*02e0*/ IMAD.SHL.U32 R8, R14, 0x2, RZ ; /* 0x000000020e087824 */
/* 0x001fe400078e00ff */
/*02f0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff069424 */
/* 0x000fe200078e00ff */
/*0300*/ @!P1 STS [R10+-0x4], RZ ; /* 0xfffffcff0a009388 */
/* 0x0001e40000000800 */
/*0310*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0320*/ @!P1 IMAD.WIDE.U32 R6, R11, R6, c[0x0][0x170] ; /* 0x00005c000b069625 */
/* 0x000fca00078e0006 */
/*0330*/ @!P1 STG.E [R6.64], R5 ; /* 0x0000000506009986 */
/* 0x0021ee000c101906 */
/*0340*/ @!P0 BRA 0x4b0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0350*/ UMOV UR8, 0x1 ; /* 0x0000000100087882 */
/* 0x000fe40000000000 */
/*0360*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0370*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x001fe2000f8e00ff */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.LT.U32.AND P0, PT, R2, UR8, PT ; /* 0x0000000802007c0c */
/* 0x000fe2000bf01070 */
/*03a0*/ USHF.R.U64 UR9, UR9, 0x1, UR5 ; /* 0x0000000109097899 */
/* 0x000fc40008001205 */
/*03b0*/ USHF.L.U64.HI UR4, UR8, 0x1, UR4 ; /* 0x0000000108047899 */
/* 0x000fe20008010204 */
/*03c0*/ ISETP.GT.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f04100 */
/*03d0*/ USHF.L.U32 UR8, UR8, 0x1, URZ ; /* 0x0000000108087899 */
/* 0x000fe4000800063f */
/*03e0*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011605 */
/*03f0*/ IMAD.U32 R9, RZ, RZ, UR4 ; /* 0x00000004ff097e24 */
/* 0x000fd0000f8e00ff */
/*0400*/ @P0 IMAD R7, R13, UR9, RZ ; /* 0x000000090d070c24 */
/* 0x000fca000f8e02ff */
/*0410*/ @P0 IADD3 R12, R7, UR9, RZ ; /* 0x00000009070c0c10 */
/* 0x000fe2000fffe0ff */
/*0420*/ @P0 LDS R5, [R7.X4+-0x4] ; /* 0xfffffc0007050984 */
/* 0x000fe80000004800 */
/*0430*/ @P0 LDS R6, [R12.X4+-0x4] ; /* 0xfffffc000c060984 */
/* 0x000e280000004800 */
/*0440*/ @P0 STS [R7.X4+-0x4], R6 ; /* 0xfffffc0607000388 */
/* 0x001fe80000004800 */
/*0450*/ @P0 LDS R10, [R12.X4+-0x4] ; /* 0xfffffc000c0a0984 */
/* 0x000e240000004800 */
/*0460*/ @P0 FADD R5, R5, R10 ; /* 0x0000000a05050221 */
/* 0x001fca0000000000 */
/*0470*/ @P0 STS [R12.X4+-0x4], R5 ; /* 0xfffffc050c000388 */
/* 0x0001e20000004800 */
/*0480*/ ISETP.LE.U32.AND P0, PT, R8, UR8, PT ; /* 0x0000000808007c0c */
/* 0x000fc8000bf03070 */
/*0490*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f06100 */
/*04a0*/ @!P0 BRA 0x370 ; /* 0xfffffec000008947 */
/* 0x001fea000383ffff */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x2, RZ ; /* 0x0000000200067824 */
/* 0x041fe200078e00ff */
/*04d0*/ SHF.L.U64.HI R3, R0, 0x1, R3 ; /* 0x0000000100037819 */
/* 0x000fc80000010203 */
/*04e0*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fc800078010ff */
/*04f0*/ LEA.HI.X R3, R6, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fe200000f1403 */
/*0500*/ LDS.64 R4, [R4.X4] ; /* 0x0000000004047984 */
/* 0x000e280000004a00 */
/*0510*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe8000c101906 */
/*0520*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101906 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13PrescanBlocksPfPKfS_m
.globl _Z13PrescanBlocksPfPKfS_m
.p2align 8
.type _Z13PrescanBlocksPfPKfS_m,@function
_Z13PrescanBlocksPfPKfS_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s2
v_add_co_u32 v6, s7, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, null, 0, 0, s7
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[6:7]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_15
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 1, v[6:7]
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_cmp_eq_u16_e64 s3, s3, 0
s_mov_b32 s6, s15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, 1, v2
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_and_b32 vcc_lo, exec_lo, s3
s_clause 0x1
global_load_b32 v10, v[6:7], off
global_load_b32 v11, v[8:9], off
v_lshlrev_b32_e32 v9, 1, v0
v_lshl_add_u32 v7, v0, 3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v8, 1, v9
v_lshl_add_u32 v6, v8, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_cbranch_vccnz .LBB0_6
v_add_co_u32 v10, null, v9, 2
s_mov_b32 s3, 0
s_mov_b64 s[4:5], 1
s_mov_b64 s[8:9], s[2:3]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_u64_e64 s3, s[8:9], 2
s_lshl_b64 s[4:5], s[4:5], 1
s_lshr_b64 s[8:9], s[8:9], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_7
.LBB0_4:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u64_e64 s[8:9], v[0:1]
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v11, s4, v8
v_mul_lo_u32 v12, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v11, 2, v11
v_lshlrev_b32_e32 v12, 2, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v11, v11, 0, -4
v_add3_u32 v12, v12, 0, -4
ds_load_b32 v11, v11
ds_load_b32 v13, v12
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v11, v11, v13
ds_store_b32 v12, v11
s_branch .LBB0_3
.LBB0_6:
s_mov_b64 s[4:5], 1
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s7, 0
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_lshl_b32 s8, s2, 3
s_lshl_b64 s[6:7], s[6:7], 2
s_add_i32 s8, s8, 0
v_mov_b32_e32 v12, 0
s_add_i32 s8, s8, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v10, s8
s_load_b64 s[8:9], s[0:1], 0x10
ds_load_b32 v11, v10
ds_store_b32 v10, v12
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s8, s6
s_addc_u32 s7, s9, s7
global_store_b32 v12, v11, s[6:7]
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_14
v_add_co_u32 v9, null, v9, 2
s_lshl_b32 s2, s2, 1
s_mov_b32 s3, 0
s_mov_b64 s[6:7], 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
s_lshl_b64 s[6:7], s[6:7], 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s8, s[6:7], s[2:3]
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_14
.LBB0_12:
s_lshr_b64 s[4:5], s[4:5], 1
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_11
v_mul_lo_u32 v10, s4, v9
v_mul_lo_u32 v12, s4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v10, 2, v10
v_lshlrev_b32_e32 v12, 2, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v10, v10, 0, -4
v_add3_u32 v12, v12, 0, -4
ds_load_b32 v11, v10
ds_load_b32 v13, v12
s_waitcnt lgkmcnt(1)
ds_store_b32 v12, v11
ds_load_b32 v11, v10
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v11, v13, v11
ds_store_b32 v10, v11
s_branch .LBB0_11
.LBB0_14:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v7, v7
ds_load_b32 v6, v6
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt lgkmcnt(1)
global_store_b32 v[0:1], v7, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v6, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13PrescanBlocksPfPKfS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13PrescanBlocksPfPKfS_m, .Lfunc_end0-_Z13PrescanBlocksPfPKfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12AddBlockSumsPfPKfm
.globl _Z12AddBlockSumsPfPKfm
.p2align 8
.type _Z12AddBlockSumsPfPKfm,@function
_Z12AddBlockSumsPfPKfm:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s15, s3
v_add_co_u32 v1, s3, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, 0, 0, s3
s_mov_b32 s3, exec_lo
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB1_4
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s2
ds_store_b32 v0, v3
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v3, 0
ds_load_b32 v3, v3
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12AddBlockSumsPfPKfm
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12AddBlockSumsPfPKfm, .Lfunc_end1-_Z12AddBlockSumsPfPKfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13PrescanBlocksPfPKfS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13PrescanBlocksPfPKfS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12AddBlockSumsPfPKfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12AddBlockSumsPfPKfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014e457_00000000-6_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16PrescanBlockSumsPfm
.type _Z16PrescanBlockSumsPfm, @function
_Z16PrescanBlockSumsPfm:
.LFB3671:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
movl $0x00000000, (%rdi)
cmpq $1, %rsi
jbe .L3
leaq 4(%rdi), %rax
leaq (%rdi,%rsi,4), %rdx
.L5:
movss (%rax), %xmm1
movss %xmm0, (%rax)
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3671:
.size _Z16PrescanBlockSumsPfm, .-_Z16PrescanBlockSumsPfm
.globl _Z15TotalPrescanCPUPKfPfm
.type _Z15TotalPrescanCPUPKfPfm, @function
_Z15TotalPrescanCPUPKfPfm:
.LFB3673:
.cfi_startproc
endbr64
testq %rdx, %rdx
je .L7
movl $0, %eax
pxor %xmm0, %xmm0
.L9:
movss %xmm0, (%rsi,%rax,4)
addss (%rdi,%rax,4), %xmm0
addq $1, %rax
cmpq %rax, %rdx
jne .L9
.L7:
ret
.cfi_endproc
.LFE3673:
.size _Z15TotalPrescanCPUPKfPfm, .-_Z15TotalPrescanCPUPKfPfm
.globl _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
.type _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m, @function
_Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13PrescanBlocksPfPKfS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m, .-_Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
.globl _Z13PrescanBlocksPfPKfS_m
.type _Z13PrescanBlocksPfPKfS_m, @function
_Z13PrescanBlocksPfPKfS_m:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z13PrescanBlocksPfPKfS_m, .-_Z13PrescanBlocksPfPKfS_m
.globl _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
.type _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm, @function
_Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm:
.LFB3701:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12AddBlockSumsPfPKfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm, .-_Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
.globl _Z12AddBlockSumsPfPKfm
.type _Z12AddBlockSumsPfPKfm, @function
_Z12AddBlockSumsPfPKfm:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z12AddBlockSumsPfPKfm, .-_Z12AddBlockSumsPfPKfm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SchattenGenie/CUDTBoost/master/src/scan.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CUDA Error: %s at %s:%d\n"
.text
.globl _Z15TotalPrescanGPUPKfPfm
.type _Z15TotalPrescanGPUPKfPfm, @function
_Z15TotalPrescanGPUPKfPfm:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 127(%rdx), %rbp
shrq $7, %rbp
leaq 0(,%rbp,4), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
leaq 0(,%rbx,4), %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L36
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L37
movl $1, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $544, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L31:
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %r13, %rdi
call _Z16PrescanBlockSumsPfm
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L32:
movl $2, %ecx
movq %r14, %rdx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $121, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $122, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $123, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L38:
movq %rbx, %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z13PrescanBlocksPfPKfS_mPfPKfS_m
jmp .L31
.L39:
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z36__device_stub__Z12AddBlockSumsPfPKfmPfPKfm
jmp .L32
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z15TotalPrescanGPUPKfPfm, .-_Z15TotalPrescanGPUPKfPfm
.section .rodata.str1.1
.LC5:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $488, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %r13d
movl %eax, %ecx
sall %cl, %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %r13, %r13
je .L42
movl $0, %eax
jmp .L45
.L43:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L44:
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%rax,4)
addq $1, %rax
cmpq %rax, %r13
je .L42
.L45:
testq %rax, %rax
js .L43
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L44
.L42:
leaq 64(%rsp), %rbx
leaq 464(%rsp), %rbp
movq %rbx, %r12
movl $0x00000000, 40(%rsp)
leaq 48(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 24(%rsp)
.L46:
movq 8(%rsp), %rdi
call cudaEventCreate@PLT
movq 24(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %r15
movq %r13, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call _Z15TotalPrescanGPUPKfPfm
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
divss .LC4(%rip), %xmm0
addss 40(%rsp), %xmm0
movss %xmm0, 40(%rsp)
addq $4, %r12
cmpq %rbp, %r12
jne .L46
movq %rbx, %rax
pxor %xmm1, %xmm1
movss .LC4(%rip), %xmm2
.L47:
movss 40(%rsp), %xmm0
subss (%rax), %xmm0
mulss %xmm0, %xmm0
divss %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rbp, %rax
jne .L47
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L64
sqrtss %xmm1, %xmm1
movss %xmm1, 44(%rsp)
.L50:
movq %rbx, %r12
movl $0x00000000, 8(%rsp)
leaq 48(%rsp), %rax
movq %rax, 24(%rsp)
leaq 56(%rsp), %rax
movq %rax, 32(%rsp)
.L51:
movq 24(%rsp), %rdi
call cudaEventCreate@PLT
movq 32(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %r15
movq %r13, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call _Z15TotalPrescanCPUPKfPfm
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC3(%rip), %xmm0
movss %xmm0, (%r12)
divss .LC4(%rip), %xmm0
addss 8(%rsp), %xmm0
movss %xmm0, 8(%rsp)
addq $4, %r12
cmpq %rbp, %r12
jne .L51
pxor %xmm1, %xmm1
movss .LC4(%rip), %xmm2
.L52:
movss 8(%rsp), %xmm0
subss (%rbx), %xmm0
mulss %xmm0, %xmm0
divss %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L52
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L65
sqrtss %xmm1, %xmm1
movss %xmm1, 24(%rsp)
.L55:
movq %r13, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 40(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
movaps %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 44(%rsp)
jmp .L50
.L65:
movaps %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 24(%rsp)
jmp .L55
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12AddBlockSumsPfPKfm"
.LC7:
.string "_Z13PrescanBlocksPfPKfS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12AddBlockSumsPfPKfm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13PrescanBlocksPfPKfS_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1148846080
.align 4
.LC4:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__PrescanBlocksPfPKfS_m # -- Begin function _Z28__device_stub__PrescanBlocksPfPKfS_m
.p2align 4, 0x90
.type _Z28__device_stub__PrescanBlocksPfPKfS_m,@function
_Z28__device_stub__PrescanBlocksPfPKfS_m: # @_Z28__device_stub__PrescanBlocksPfPKfS_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13PrescanBlocksPfPKfS_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__PrescanBlocksPfPKfS_m, .Lfunc_end0-_Z28__device_stub__PrescanBlocksPfPKfS_m
.cfi_endproc
# -- End function
.globl _Z27__device_stub__AddBlockSumsPfPKfm # -- Begin function _Z27__device_stub__AddBlockSumsPfPKfm
.p2align 4, 0x90
.type _Z27__device_stub__AddBlockSumsPfPKfm,@function
_Z27__device_stub__AddBlockSumsPfPKfm: # @_Z27__device_stub__AddBlockSumsPfPKfm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12AddBlockSumsPfPKfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__AddBlockSumsPfPKfm, .Lfunc_end1-_Z27__device_stub__AddBlockSumsPfPKfm
.cfi_endproc
# -- End function
.globl _Z16PrescanBlockSumsPfm # -- Begin function _Z16PrescanBlockSumsPfm
.p2align 4, 0x90
.type _Z16PrescanBlockSumsPfm,@function
_Z16PrescanBlockSumsPfm: # @_Z16PrescanBlockSumsPfm
.cfi_startproc
# %bb.0:
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $0, (%rdi)
cmpq $2, %rsi
jb .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl $1, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm0, (%rdi,%rax,4)
incq %rax
movaps %xmm1, %xmm0
cmpq %rax, %rsi
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z16PrescanBlockSumsPfm, .Lfunc_end2-_Z16PrescanBlockSumsPfm
.cfi_endproc
# -- End function
.globl _Z15TotalPrescanGPUPKfPfm # -- Begin function _Z15TotalPrescanGPUPKfPfm
.p2align 4, 0x90
.type _Z15TotalPrescanGPUPKfPfm,@function
_Z15TotalPrescanGPUPKfPfm: # @_Z15TotalPrescanGPUPKfPfm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movq %rsi, %rbp
movq %rdi, %r14
leaq 127(%rdx), %r12
movq %r12, 152(%rsp) # 8-byte Spill
shrq $7, %r12
leaq (,%r12,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r15, 104(%rsp) # 8-byte Spill
leaq (,%r15,4), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_Z10cudaAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_Z10cudaAssert10hipError_tPKcib.exit28
movq %rbp, 144(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z10cudaAssert10hipError_tPKcib.exit30
movabsq $4294967296, %rbp # imm = 0x100000000
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %r14d
orq %rbp, %r14
leaq 64(%rbp), %rdx
movl $544, %r8d # imm = 0x220
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movq %rax, 40(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13PrescanBlocksPfPKfS_m, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $0, (%rbx)
cmpq $256, 152(%rsp) # 8-byte Folded Reload
# imm = 0x100
jb .LBB3_12
# %bb.10: # %.lr.ph.i.preheader
movl $1, %eax
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm0, (%rbx,%rax,4)
incq %rax
movaps %xmm1, %xmm0
cmpq %rax, %r12
jne .LBB3_11
.LBB3_12: # %_Z16PrescanBlockSumsPfm.exit
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
subq $-128, %rbp
movq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12AddBlockSumsPfPKfm, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
movq 16(%rsp), %rsi
movq 144(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size _Z15TotalPrescanGPUPKfPfm, .Lfunc_end3-_Z15TotalPrescanGPUPKfPfm
.cfi_endproc
# -- End function
.globl _Z15TotalPrescanCPUPKfPfm # -- Begin function _Z15TotalPrescanCPUPKfPfm
.p2align 4, 0x90
.type _Z15TotalPrescanCPUPKfPfm,@function
_Z15TotalPrescanCPUPKfPfm: # @_Z15TotalPrescanCPUPKfPfm
.cfi_startproc
# %bb.0:
testq %rdx, %rdx
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rsi,%rax,4)
addss (%rdi,%rax,4), %xmm0
incq %rax
cmpq %rax, %rdx
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z15TotalPrescanCPUPKfPfm, .Lfunc_end4-_Z15TotalPrescanCPUPKfPfm
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI5_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI5_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_2:
.long 0x447a0000 # float 1000
.LCPI5_3:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $1, %edx
movl %eax, %ecx
shll %cl, %edx
movslq %edx, %r15
leaq (,%r15,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
movdqa .LCPI5_0(%rip), %xmm0 # xmm0 = [1127219200,1160773632,0,0]
movapd .LCPI5_1(%rip), %xmm1 # xmm1 = [4.503599627370496E+15,1.9342813113834067E+25]
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movq %r12, %xmm2
punpckldq %xmm0, %xmm2 # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
subpd %xmm1, %xmm2
movapd %xmm2, %xmm3
unpckhpd %xmm2, %xmm3 # xmm3 = xmm3[1],xmm2[1]
addsd %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtsd2ss %xmm3, %xmm2
movss %xmm2, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB5_1
# %bb.2:
xorps %xmm2, %xmm2
xorl %r12d, %r12d
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movss %xmm2, 4(%rsp) # 4-byte Spill
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r13, %rdi
callq hipEventCreate
callq clock
movq %rax, %rbp
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z15TotalPrescanGPUPKfPfm
callq clock
movss .LCPI5_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI5_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss 4(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, 32(%rsp,%r12,4)
divss %xmm3, %xmm0
addss %xmm0, %xmm2
incq %r12
cmpq $100, %r12
jne .LBB5_3
# %bb.4: # %.preheader70.preheader
pxor %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_5: # %.preheader70
# =>This Inner Loop Header: Depth=1
movaps %xmm2, %xmm1
subss 32(%rsp,%rax,4), %xmm1
mulss %xmm1, %xmm1
divss %xmm3, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $100, %rax
jne .LBB5_5
# %bb.6:
xorps %xmm3, %xmm3
ucomiss %xmm3, %xmm0
movss %xmm2, 4(%rsp) # 4-byte Spill
jb .LBB5_8
# %bb.7:
sqrtss %xmm0, %xmm0
jmp .LBB5_9
.LBB5_8: # %call.sqrt
callq sqrtf@PLT
xorps %xmm3, %xmm3
.LBB5_9: # %.split
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %r12d, %r12d
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB5_10: # =>This Loop Header: Depth=1
# Child Loop BB5_11 Depth 2
movss %xmm3, (%rsp) # 4-byte Spill
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %r13, %rdi
callq hipEventCreate
callq clock
xorps %xmm0, %xmm0
movq %rax, %rbp
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_11: # %.lr.ph.i
# Parent Loop BB5_10 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%r14,%rax,4)
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq %rax, %r15
jne .LBB5_11
# %bb.12: # %_Z15TotalPrescanCPUPKfPfm.exit
# in Loop: Header=BB5_10 Depth=1
callq clock
subq %rbp, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_2(%rip), %xmm0
movss %xmm0, 32(%rsp,%r12,4)
movss .LCPI5_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm2, %xmm0
movss (%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
incq %r12
cmpq $100, %r12
jne .LBB5_10
# %bb.13: # %.preheader.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movaps %xmm3, %xmm1
subss 32(%rsp,%rax,4), %xmm1
mulss %xmm1, %xmm1
divss %xmm2, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $100, %rax
jne .LBB5_14
# %bb.15:
movss %xmm3, (%rsp) # 4-byte Spill
xorpd %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB5_17
# %bb.16:
sqrtss %xmm0, %xmm0
jmp .LBB5_18
.LBB5_17: # %call.sqrt102
callq sqrtf@PLT
.LBB5_18: # %.split101
movss %xmm0, 8(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB5_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB5_21
# %bb.20:
movzbl 67(%r15), %ecx
jmp .LBB5_22
.LBB5_21:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB5_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_23:
.cfi_def_cfa_offset 496
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13PrescanBlocksPfPKfS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12AddBlockSumsPfPKfm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13PrescanBlocksPfPKfS_m,@object # @_Z13PrescanBlocksPfPKfS_m
.section .rodata,"a",@progbits
.globl _Z13PrescanBlocksPfPKfS_m
.p2align 3, 0x0
_Z13PrescanBlocksPfPKfS_m:
.quad _Z28__device_stub__PrescanBlocksPfPKfS_m
.size _Z13PrescanBlocksPfPKfS_m, 8
.type _Z12AddBlockSumsPfPKfm,@object # @_Z12AddBlockSumsPfPKfm
.globl _Z12AddBlockSumsPfPKfm
.p2align 3, 0x0
_Z12AddBlockSumsPfPKfm:
.quad _Z27__device_stub__AddBlockSumsPfPKfm
.size _Z12AddBlockSumsPfPKfm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SchattenGenie/CUDTBoost/master/src/scan.hip"
.size .L.str, 101
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA Error: %s at %s:%d\n"
.size .L.str.2, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13PrescanBlocksPfPKfS_m"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12AddBlockSumsPfPKfm"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__PrescanBlocksPfPKfS_m
.addrsig_sym _Z27__device_stub__AddBlockSumsPfPKfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13PrescanBlocksPfPKfS_m
.addrsig_sym _Z12AddBlockSumsPfPKfm
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <algorithm>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/adjacent_difference.h>
#include <thrust/generate.h>
#include <thrust/unique.h>
#include <thrust/scan.h>
#include <thrust/transform_reduce.h>
#include <thrust/transform.h>
#include <thrust/binary_search.h>
#include <thrust/functional.h>
#include <thrust/inner_product.h>
#define SITES 10
#define MAX_MEASUREMENT 8
unsigned int TotalRain ( thrust::device_vector<unsigned int>& M) {
// Sum up all elements
return thrust::reduce ( M.begin(), M.end() );
}
unsigned int TotalDaysRainInSite ( thrust::device_vector<unsigned int>& S,
const unsigned int Site) {
// Count occurrences of Site in S
return thrust::count ( S.begin(), S.end(), Site );
}
unsigned int TotalSites ( thrust::device_vector<unsigned int>& S) {
// Sort by Sites
thrust::sort ( S.begin(), S.end() );
// Count unique elements in S
return thrust::distance( S.begin(), thrust::unique ( S.begin(), S.end() ) );
}
struct find_rain_by_site {
const unsigned int site;
find_rain_by_site(int _site) : site(_site) {}
__host__ __device__
int operator()(const int& sites, const int& measurements) const {
if (sites == site) return measurements; else return 0;
}
};
unsigned int TotalRainIN ( thrust::device_vector<unsigned int>& S,
thrust::device_vector<unsigned int>& M,
const unsigned int St) {
// if (S(i) != St) M(i)=0;
thrust::transform(S.begin(), S.end(), M.begin(), M.begin(), find_rain_by_site(St));
// Reduce
return thrust::reduce(M.begin(), M.end());
}
struct find_rain_by_days {
const int start, end;
find_rain_by_days(int _start, int _end) : start(_start), end(_end) {}
__host__ __device__
int operator()(const int& day, const int& measurement) const {
if ((start<=day) && (day<=end)) return measurement; else return 0;
}
};
unsigned int TotalRainBetween ( thrust::device_vector<unsigned int>& D,
thrust::device_vector<unsigned int>& M,
const unsigned int Start, const unsigned int End) {
// if !(Start < D(i) < End) M(i)=0;
thrust::transform(D.begin(), D.end(), M.begin(), M.begin(), find_rain_by_days(Start, End));
// Reduce
return thrust::reduce(M.begin(), M.end());
}
unsigned int TotalDaysWithRain ( thrust::device_vector<unsigned int>& D) {
// Count unique elements in D
return thrust::distance( D.begin(), thrust::unique ( D.begin(), D.end() ) );
}
struct greater_than_ten {
__host__ __device__
bool operator () ( const int x ) {
return x > 10;
}
};
unsigned int TotalDaysRainHigher( thrust::device_vector<unsigned int>& D,
thrust::device_vector<unsigned int>& M,
const unsigned int Min) {
// Merges elements in M using D as key. If values in D identical, merge.
// Example
// D = 1 1 2 3 3 4
// M = 2 7 4 9 12 3
// D* = 1 2 3 4
// M* = 9 4 21 3
thrust::pair<thrust::device_vector<unsigned int>::iterator, thrust::device_vector<unsigned int>::iterator> new_end = thrust::reduce_by_key(D.begin(), D.end(), M.begin(), D.begin(), M.begin());
if(Min == 10) {
// Count elements in D* that are greater than ten
return thrust::count_if(M.begin(), new_end.second, greater_than_ten());
} else {
// ...
}
return 0;
}
bool Option ( char o, thrust::device_vector<unsigned int>& Days,
thrust::device_vector<unsigned int>& Sites,
thrust::device_vector<unsigned int>& Measurements)
{
switch (o) {
case '0': std::cout << "Total Rainfall is " << TotalRain( Measurements ) << std::endl; break;
case '1': std::cout << "Total number of Days with any Rainfall in Site 3: "
<< TotalDaysRainInSite ( Sites, 3 ) << std::endl; break;
case '2': std::cout << "Total Sites with rain: " << TotalSites ( Sites ) << std::endl; break;
case '3': std::cout << "Total Rainfall in Site 7 is " << TotalRainIN ( Sites, Measurements, 7 )
<< std::endl; break;
case '4': std::cout << "Total Rainfall between days 7 and 77 is "
<< TotalRainBetween ( Days, Measurements, 7, 77 ) << std::endl; break;
case '5': std::cout << "Total number of Days with any rainfall: "
<< TotalDaysWithRain ( Days ) << std::endl; break;
case '6': std::cout << "Number of Days where Rainfall exceeded 10 is "
<< TotalDaysRainHigher ( Days, Measurements, 10 ) << std::endl; break;
default: return false;
}
return true;
}
struct rand_modulus {
unsigned int N;
rand_modulus(unsigned int _NN) : N(_NN) {}
__host__ __device__
unsigned int operator()() const {
return rand() % N;
}
};
struct is_equal {
__host__ __device__
unsigned int operator() ( const unsigned int& d, const unsigned int& s ) {
return d==s? 1: 0;
}
};
struct get_site {
__host__ __device__
unsigned int operator() ( const unsigned int& v ) {
return v % SITES;
}
};
struct get_day {
__host__ __device__
unsigned int operator() ( const unsigned int& v ) {
return v / SITES;
}
};
unsigned int rand_mes() {
return (unsigned int) pow( 2.0, ((double) (rand() % 100000)) / (100000 / MAX_MEASUREMENT) );
}
int main (int argc, char **argv)
{
unsigned int N=20;
char o= '1';
int Dup = -1;
if (argc>1) { o = argv[1][0]; }
if (argc>2) { N = atoi(argv[2]); }
if (o == 'H' || o == 'h') {
std::cout << "Arguments: (H|1|2|3|4|5|6) N " << std::endl;
exit(0);
}
// use this host vector to generate random input data
thrust::host_vector<unsigned int> HDay(N);
thrust::host_vector<unsigned int> HMes(N);
srand(0); // init random generation seed: same random numbers generated in each execution
// Generate Information sorted by (increasing) day and site, and with no duplicates (day, site)
thrust::generate ( HDay.begin(), HDay.end(), rand_modulus(N*SITES) );
thrust::generate ( HMes.begin(), HMes.end(), rand_mes );
// Create Device vectors and copy data from host vectors
thrust::device_vector<unsigned int> Days = HDay;
thrust::device_vector<unsigned int> Measurements= HMes;
thrust::device_vector<unsigned int> Sites(N);
// Sort data and modify to avoid duplicates ( only works fine if SITES=10 )
thrust::sort ( Days.begin(), Days.end() );
do {
Dup++;
thrust::transform ( Days.begin(), Days.end()-1, Days.begin()+1, Sites.begin(), is_equal() );
thrust::transform ( Days.begin()+1, Days.end(), Sites.begin(), Days.begin()+1, thrust::plus<unsigned int>() );
} while (thrust::reduce ( Sites.begin(), Sites.end()-1 ) > 0);
thrust::transform ( Days.begin(), Days.end(), Sites.begin(), get_site() );
thrust::transform ( Days.begin(), Days.end(), Days.begin(), get_day() );
if (Dup >0)
std::cout << "Phases to extract duplicates during generation: " << Dup << std::endl << std::endl;
if ( N<=20 ) { // for small cases: print contains of input vectors
std::cout << "Days: ";
thrust::copy( Days.begin(), Days.end(), std::ostream_iterator<unsigned int>( std::cout, ", " ));
std::cout << std::endl << "Sites: ";
thrust::copy( Sites.begin(), Sites.end(), std::ostream_iterator<unsigned int>( std::cout, ", " ));
std::cout << std::endl << "Measurements: ";
thrust::copy( HMes.begin(), HMes.end(), std::ostream_iterator<unsigned int>( std::cout, ", " ));
std::cout << std::endl;
}
// create device vectors and copy data from host vectors
Option ( o, Days, Sites, Measurements);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <algorithm>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/adjacent_difference.h>
#include <thrust/generate.h>
#include <thrust/unique.h>
#include <thrust/scan.h>
#include <thrust/transform_reduce.h>
#include <thrust/transform.h>
#include <thrust/binary_search.h>
#include <thrust/functional.h>
#include <thrust/inner_product.h>
#define SITES 10
#define MAX_MEASUREMENT 8
unsigned int TotalRain ( thrust::device_vector<unsigned int>& M) {
// Sum up all elements
return thrust::reduce ( M.begin(), M.end() );
}
unsigned int TotalDaysRainInSite ( thrust::device_vector<unsigned int>& S,
const unsigned int Site) {
// Count occurrences of Site in S
return thrust::count ( S.begin(), S.end(), Site );
}
unsigned int TotalSites ( thrust::device_vector<unsigned int>& S) {
// Sort by Sites
thrust::sort ( S.begin(), S.end() );
// Count unique elements in S
return thrust::distance( S.begin(), thrust::unique ( S.begin(), S.end() ) );
}
struct find_rain_by_site {
const unsigned int site;
find_rain_by_site(int _site) : site(_site) {}
__host__ __device__
int operator()(const int& sites, const int& measurements) const {
if (sites == site) return measurements; else return 0;
}
};
unsigned int TotalRainIN ( thrust::device_vector<unsigned int>& S,
thrust::device_vector<unsigned int>& M,
const unsigned int St) {
// if (S(i) != St) M(i)=0;
thrust::transform(S.begin(), S.end(), M.begin(), M.begin(), find_rain_by_site(St));
// Reduce
return thrust::reduce(M.begin(), M.end());
}
struct find_rain_by_days {
const int start, end;
find_rain_by_days(int _start, int _end) : start(_start), end(_end) {}
__host__ __device__
int operator()(const int& day, const int& measurement) const {
if ((start<=day) && (day<=end)) return measurement; else return 0;
}
};
unsigned int TotalRainBetween ( thrust::device_vector<unsigned int>& D,
thrust::device_vector<unsigned int>& M,
const unsigned int Start, const unsigned int End) {
// if !(Start < D(i) < End) M(i)=0;
thrust::transform(D.begin(), D.end(), M.begin(), M.begin(), find_rain_by_days(Start, End));
// Reduce
return thrust::reduce(M.begin(), M.end());
}
unsigned int TotalDaysWithRain ( thrust::device_vector<unsigned int>& D) {
// Count unique elements in D
return thrust::distance( D.begin(), thrust::unique ( D.begin(), D.end() ) );
}
struct greater_than_ten {
__host__ __device__
bool operator () ( const int x ) {
return x > 10;
}
};
unsigned int TotalDaysRainHigher( thrust::device_vector<unsigned int>& D,
thrust::device_vector<unsigned int>& M,
const unsigned int Min) {
// Merges elements in M using D as key. If values in D identical, merge.
// Example
// D = 1 1 2 3 3 4
// M = 2 7 4 9 12 3
// D* = 1 2 3 4
// M* = 9 4 21 3
thrust::pair<thrust::device_vector<unsigned int>::iterator, thrust::device_vector<unsigned int>::iterator> new_end = thrust::reduce_by_key(D.begin(), D.end(), M.begin(), D.begin(), M.begin());
if(Min == 10) {
// Count elements in D* that are greater than ten
return thrust::count_if(M.begin(), new_end.second, greater_than_ten());
} else {
// ...
}
return 0;
}
bool Option ( char o, thrust::device_vector<unsigned int>& Days,
thrust::device_vector<unsigned int>& Sites,
thrust::device_vector<unsigned int>& Measurements)
{
switch (o) {
case '0': std::cout << "Total Rainfall is " << TotalRain( Measurements ) << std::endl; break;
case '1': std::cout << "Total number of Days with any Rainfall in Site 3: "
<< TotalDaysRainInSite ( Sites, 3 ) << std::endl; break;
case '2': std::cout << "Total Sites with rain: " << TotalSites ( Sites ) << std::endl; break;
case '3': std::cout << "Total Rainfall in Site 7 is " << TotalRainIN ( Sites, Measurements, 7 )
<< std::endl; break;
case '4': std::cout << "Total Rainfall between days 7 and 77 is "
<< TotalRainBetween ( Days, Measurements, 7, 77 ) << std::endl; break;
case '5': std::cout << "Total number of Days with any rainfall: "
<< TotalDaysWithRain ( Days ) << std::endl; break;
case '6': std::cout << "Number of Days where Rainfall exceeded 10 is "
<< TotalDaysRainHigher ( Days, Measurements, 10 ) << std::endl; break;
default: return false;
}
return true;
}
struct rand_modulus {
unsigned int N;
rand_modulus(unsigned int _NN) : N(_NN) {}
__host__ __device__
unsigned int operator()() const {
return rand() % N;
}
};
struct is_equal {
__host__ __device__
unsigned int operator() ( const unsigned int& d, const unsigned int& s ) {
return d==s? 1: 0;
}
};
struct get_site {
__host__ __device__
unsigned int operator() ( const unsigned int& v ) {
return v % SITES;
}
};
struct get_day {
__host__ __device__
unsigned int operator() ( const unsigned int& v ) {
return v / SITES;
}
};
unsigned int rand_mes() {
return (unsigned int) pow( 2.0, ((double) (rand() % 100000)) / (100000 / MAX_MEASUREMENT) );
}
int main (int argc, char **argv)
{
unsigned int N=20;
char o= '1';
int Dup = -1;
if (argc>1) { o = argv[1][0]; }
if (argc>2) { N = atoi(argv[2]); }
if (o == 'H' || o == 'h') {
std::cout << "Arguments: (H|1|2|3|4|5|6) N " << std::endl;
exit(0);
}
// use this host vector to generate random input data
thrust::host_vector<unsigned int> HDay(N);
thrust::host_vector<unsigned int> HMes(N);
srand(0); // init random generation seed: same random numbers generated in each execution
// Generate Information sorted by (increasing) day and site, and with no duplicates (day, site)
thrust::generate ( HDay.begin(), HDay.end(), rand_modulus(N*SITES) );
thrust::generate ( HMes.begin(), HMes.end(), rand_mes );
// Create Device vectors and copy data from host vectors
thrust::device_vector<unsigned int> Days = HDay;
thrust::device_vector<unsigned int> Measurements= HMes;
thrust::device_vector<unsigned int> Sites(N);
// Sort data and modify to avoid duplicates ( only works fine if SITES=10 )
thrust::sort ( Days.begin(), Days.end() );
do {
Dup++;
thrust::transform ( Days.begin(), Days.end()-1, Days.begin()+1, Sites.begin(), is_equal() );
thrust::transform ( Days.begin()+1, Days.end(), Sites.begin(), Days.begin()+1, thrust::plus<unsigned int>() );
} while (thrust::reduce ( Sites.begin(), Sites.end()-1 ) > 0);
thrust::transform ( Days.begin(), Days.end(), Sites.begin(), get_site() );
thrust::transform ( Days.begin(), Days.end(), Days.begin(), get_day() );
if (Dup >0)
std::cout << "Phases to extract duplicates during generation: " << Dup << std::endl << std::endl;
if ( N<=20 ) { // for small cases: print contains of input vectors
std::cout << "Days: ";
thrust::copy( Days.begin(), Days.end(), std::ostream_iterator<unsigned int>( std::cout, ", " ));
std::cout << std::endl << "Sites: ";
thrust::copy( Sites.begin(), Sites.end(), std::ostream_iterator<unsigned int>( std::cout, ", " ));
std::cout << std::endl << "Measurements: ";
thrust::copy( HMes.begin(), HMes.end(), std::ostream_iterator<unsigned int>( std::cout, ", " ));
std::cout << std::endl;
}
// create device vectors and copy data from host vectors
Option ( o, Days, Sites, Measurements);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ void add ( float *a, float *b, float *c,int n ){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) c[ind] = a[ind] + b[ind];
}
__global__ void vecAdd ( float *a, float *b, float *c,int n ){
add( a, b, c, n);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
float *d_a, *d_b, *d_c;
cudaMalloc( &d_a, n * sizeof(float) );
cudaMalloc( &d_b, n * sizeof(float) );
cudaMalloc( &d_c, n * sizeof(float) );
cudaMemcpy( d_a, a, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy( d_b, b, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy( d_c, c, n * sizeof(float), cudaMemcpyHostToDevice);
//Device Blocka allocation
dim3 block = dim3(64, 1, 1); //64 threads
// allocate blocks in grid
dim3 grid = dim3( (n + block.x - 1 ) / block.x, 1, 1);
vecAdd <<< grid, block >>> (d_a, d_b, d_c, n);
cudaMemcpy ( c, d_c, n * sizeof(float), cudaMemcpyDeviceToHost );
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ void add ( float *a, float *b, float *c,int n ){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) c[ind] = a[ind] + b[ind];
}
__global__ void vecAdd ( float *a, float *b, float *c,int n ){
add( a, b, c, n);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
float *d_a, *d_b, *d_c;
cudaMalloc( &d_a, n * sizeof(float) );
cudaMalloc( &d_b, n * sizeof(float) );
cudaMalloc( &d_c, n * sizeof(float) );
cudaMemcpy( d_a, a, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy( d_b, b, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy( d_c, c, n * sizeof(float), cudaMemcpyHostToDevice);
//Device Blocka allocation
dim3 block = dim3(64, 1, 1); //64 threads
// allocate blocks in grid
dim3 grid = dim3( (n + block.x - 1 ) / block.x, 1, 1);
vecAdd <<< grid, block >>> (d_a, d_b, d_c, n);
cudaMemcpy ( c, d_c, n * sizeof(float), cudaMemcpyDeviceToHost );
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | .file "tmpxft_0005886e_00000000-6_addArrays.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1
.LC5:
.string "CPU:"
.LC6:
.string " + "
.LC7:
.string " = "
.LC8:
.string "GPU:"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
movl %eax, %edx
subl %ecx, %edx
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r14,%rax,4)
movl $0x00000000, 0(%r13,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L18
movl $0, %eax
.L19:
movss (%r15,%rax), %xmm0
addss (%r14,%rax), %xmm0
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $80, %rax
jne .L19
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L24
.L41:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
call _ZSt16__throw_bad_castv@PLT
.L39:
call __stack_chk_fail@PLT
.L22:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L40
.L24:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L41
cmpb $0, 56(%r12)
je .L22
movzbl 67(%r12), %esi
jmp .L23
.L40:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rax
leaq 80(%r13), %rdx
.L25:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L25
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $64, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L26:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L31
.L42:
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L26
.L45:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L29:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L44
.L31:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L45
cmpb $0, 56(%r12)
je .L29
movzbl 67(%r12), %esi
jmp .L30
.L44:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ void add ( float *a, float *b, float *c,int n ){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) c[ind] = a[ind] + b[ind];
}
__global__ void vecAdd ( float *a, float *b, float *c,int n ){
add( a, b, c, n);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
float *d_a, *d_b, *d_c;
cudaMalloc( &d_a, n * sizeof(float) );
cudaMalloc( &d_b, n * sizeof(float) );
cudaMalloc( &d_c, n * sizeof(float) );
cudaMemcpy( d_a, a, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy( d_b, b, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy( d_c, c, n * sizeof(float), cudaMemcpyHostToDevice);
//Device Blocka allocation
dim3 block = dim3(64, 1, 1); //64 threads
// allocate blocks in grid
dim3 grid = dim3( (n + block.x - 1 ) / block.x, 1, 1);
vecAdd <<< grid, block >>> (d_a, d_b, d_c, n);
cudaMemcpy ( c, d_c, n * sizeof(float), cudaMemcpyDeviceToHost );
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ void add ( float *a, float *b, float *c,int n ){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) c[ind] = a[ind] + b[ind];
}
__global__ void vecAdd ( float *a, float *b, float *c,int n ){
add( a, b, c, n);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
float *d_a, *d_b, *d_c;
hipMalloc( &d_a, n * sizeof(float) );
hipMalloc( &d_b, n * sizeof(float) );
hipMalloc( &d_c, n * sizeof(float) );
hipMemcpy( d_a, a, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy( d_b, b, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy( d_c, c, n * sizeof(float), hipMemcpyHostToDevice);
//Device Blocka allocation
dim3 block = dim3(64, 1, 1); //64 threads
// allocate blocks in grid
dim3 grid = dim3( (n + block.x - 1 ) / block.x, 1, 1);
vecAdd <<< grid, block >>> (d_a, d_b, d_c, n);
hipMemcpy ( c, d_c, n * sizeof(float), hipMemcpyDeviceToHost );
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ void add ( float *a, float *b, float *c,int n ){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) c[ind] = a[ind] + b[ind];
}
__global__ void vecAdd ( float *a, float *b, float *c,int n ){
add( a, b, c, n);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
float *d_a, *d_b, *d_c;
hipMalloc( &d_a, n * sizeof(float) );
hipMalloc( &d_b, n * sizeof(float) );
hipMalloc( &d_c, n * sizeof(float) );
hipMemcpy( d_a, a, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy( d_b, b, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy( d_c, c, n * sizeof(float), hipMemcpyHostToDevice);
//Device Blocka allocation
dim3 block = dim3(64, 1, 1); //64 threads
// allocate blocks in grid
dim3 grid = dim3( (n + block.x - 1 ) / block.x, 1, 1);
vecAdd <<< grid, block >>> (d_a, d_b, d_c, n);
hipMemcpy ( c, d_c, n * sizeof(float), hipMemcpyDeviceToHost );
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2015/2016, March 15 - April 15
// ###
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ void add ( float *a, float *b, float *c,int n ){
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if (ind < n) c[ind] = a[ind] + b[ind];
}
__global__ void vecAdd ( float *a, float *b, float *c,int n ){
add( a, b, c, n);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
float *d_a, *d_b, *d_c;
hipMalloc( &d_a, n * sizeof(float) );
hipMalloc( &d_b, n * sizeof(float) );
hipMalloc( &d_c, n * sizeof(float) );
hipMemcpy( d_a, a, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy( d_b, b, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy( d_c, c, n * sizeof(float), hipMemcpyHostToDevice);
//Device Blocka allocation
dim3 block = dim3(64, 1, 1); //64 threads
// allocate blocks in grid
dim3 grid = dim3( (n + block.x - 1 ) / block.x, 1, 1);
vecAdd <<< grid, block >>> (d_a, d_b, d_c, n);
hipMemcpy ( c, d_c, n * sizeof(float), hipMemcpyDeviceToHost );
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | .text
.file "addArrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end1-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $80, %edi
callq _Znam
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
xorl %eax, %eax
movl $3435973837, %ecx # imm = 0xCCCCCCCD
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, %edx
imulq %rcx, %rdx
shrq $34, %rdx
leal (%rdx,%rdx,4), %edx
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
negl %edx
addl %eax, %edx
incl %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm0, (%rbx,%rax,4)
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB2_8
.LBB2_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_9 Depth=1
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit83
# in Loop: Header=BB2_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.5, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB2_35
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i80
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r13)
je .LBB2_21
# %bb.11: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB2_22
.LBB2_12:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i75
cmpb $0, 56(%r12)
je .LBB2_15
# %bb.14:
movzbl 67(%r12), %eax
jmp .LBB2_16
.LBB2_15:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit78
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
movups %xmm0, (%r15)
movups %xmm0, 16(%r15)
movups %xmm0, 32(%r15)
movups %xmm0, 48(%r15)
movups %xmm0, 64(%r15)
leaq 24(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.17:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_18:
movq 8(%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i85
cmpb $0, 56(%r12)
je .LBB2_23
# %bb.20:
movzbl 67(%r12), %eax
jmp .LBB2_24
.LBB2_23:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit88
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB2_25
.p2align 4, 0x90
.LBB2_33: # in Loop: Header=BB2_25 Depth=1
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98
# in Loop: Header=BB2_25 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
je .LBB2_28
.LBB2_25: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.5, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB2_35
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
# in Loop: Header=BB2_25 Depth=1
cmpb $0, 56(%r13)
je .LBB2_33
# %bb.27: # in Loop: Header=BB2_25 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB2_34
.LBB2_28:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i90
cmpb $0, 56(%r12)
je .LBB2_31
# %bb.30:
movzbl 67(%r12), %eax
jmp .LBB2_32
.LBB2_31:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit93
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_35:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " + "
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " = "
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU:"
.size .L.str.7, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005886e_00000000-6_addArrays.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1
.LC5:
.string "CPU:"
.LC6:
.string " + "
.LC7:
.string " = "
.LC8:
.string "GPU:"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
movl %eax, %edx
subl %ecx, %edx
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r14,%rax,4)
movl $0x00000000, 0(%r13,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L18
movl $0, %eax
.L19:
movss (%r15,%rax), %xmm0
addss (%r14,%rax), %xmm0
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $80, %rax
jne .L19
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L24
.L41:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
call _ZSt16__throw_bad_castv@PLT
.L39:
call __stack_chk_fail@PLT
.L22:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L40
.L24:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L41
cmpb $0, 56(%r12)
je .L22
movzbl 67(%r12), %esi
jmp .L23
.L40:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rax
leaq 80(%r13), %rdx
.L25:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L25
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $64, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L26:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L31
.L42:
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L26
.L45:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L29:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L44
.L31:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L45
cmpb $0, 56(%r12)
je .L29
movzbl 67(%r12), %esi
jmp .L30
.L44:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addArrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end1-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $80, %edi
callq _Znam
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
xorl %eax, %eax
movl $3435973837, %ecx # imm = 0xCCCCCCCD
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, %edx
imulq %rcx, %rdx
shrq $34, %rdx
leal (%rdx,%rdx,4), %edx
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
negl %edx
addl %eax, %edx
incl %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm0, (%rbx,%rax,4)
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB2_8
.LBB2_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_9 Depth=1
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit83
# in Loop: Header=BB2_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.5, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB2_35
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i80
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r13)
je .LBB2_21
# %bb.11: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB2_22
.LBB2_12:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i75
cmpb $0, 56(%r12)
je .LBB2_15
# %bb.14:
movzbl 67(%r12), %eax
jmp .LBB2_16
.LBB2_15:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit78
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
movups %xmm0, (%r15)
movups %xmm0, 16(%r15)
movups %xmm0, 32(%r15)
movups %xmm0, 48(%r15)
movups %xmm0, 64(%r15)
leaq 24(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.17:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_18:
movq 8(%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i85
cmpb $0, 56(%r12)
je .LBB2_23
# %bb.20:
movzbl 67(%r12), %eax
jmp .LBB2_24
.LBB2_23:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit88
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB2_25
.p2align 4, 0x90
.LBB2_33: # in Loop: Header=BB2_25 Depth=1
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98
# in Loop: Header=BB2_25 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
je .LBB2_28
.LBB2_25: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.5, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB2_35
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
# in Loop: Header=BB2_25 Depth=1
cmpb $0, 56(%r13)
je .LBB2_33
# %bb.27: # in Loop: Header=BB2_25 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB2_34
.LBB2_28:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_35
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i90
cmpb $0, 56(%r12)
je .LBB2_31
# %bb.30:
movzbl 67(%r12), %eax
jmp .LBB2_32
.LBB2_31:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit93
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_35:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " + "
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " = "
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU:"
.size .L.str.7, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdbool.h>
#include <math.h>
#define M_PI 3.14159265359
#define MIN(a,b) (((a)<(b))?(a):(b))
typedef struct
{
float *matrix;
int n_landmarks;
int n_measurements;
} dist_matrix;
typedef struct
{
int *assignment;
bool *assigned_measurements;
} assignment;
typedef struct
{
float (*measurements)[2];
int n_measurements;
float *measurement_cov;
} landmark_measurements;
__device__ float* get_particle(float *particles, int i) {
int max_landmarks = (int)particles[4];
return (particles + (6 + 6*max_landmarks)*i);
}
__device__ float* get_mean(float *particle, int i)
{
return (particle + 6 + 2*i);
}
__device__ float* get_cov(float *particle, int i)
{
int max_landmarks = (int)particle[4];
return (particle + 6 + 2*max_landmarks + 4*i);
}
__device__ int get_n_landmarks(float *particle)
{
return (int)particle[5];
}
__device__ void add_landmark(float *particle, float mean[2], float *cov)
{
int n_landmarks = (int)particle[5];
particle[5] = (float)(n_landmarks + 1);
float *new_mean = get_mean(particle, n_landmarks);
float *new_cov = get_cov(particle, n_landmarks);
new_mean[0] = mean[0];
new_mean[1] = mean[1];
new_cov[0] = cov[0];
new_cov[1] = cov[1];
new_cov[2] = cov[2];
new_cov[3] = cov[3];
}
__device__ void add_unassigned_measurements_as_landmarks(float *particle, bool *assigned_measurements, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
if(!assigned_measurements[i]) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
}
__device__ void add_measurements_as_landmarks(float *particle, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
__device__ void insertion_sort(float arr[], int lm[], int me[], int n)
{
int i, lm_key, me_key, j;
float key;
for (i = 1; i < n; i++) {
key = arr[i];
lm_key = lm[i];
me_key = me[i];
j = i - 1;
while (j >= 0 && arr[j] < key) {
arr[j + 1] = arr[j];
lm[j + 1] = lm[j];
me[j + 1] = me[j];
j = j - 1;
}
arr[j + 1] = key;
lm[j + 1] = lm_key;
me[j + 1] = me_key;
}
}
__device__ void vecmul(float *A, float *u, float *v)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = u[0];
float f = v[1];
v[0] = a*e + b*f;
v[1] = c*e + d*f;
}
__device__ void matmul(float *A, float *B, float *C)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = B[0];
float f = B[1];
float g = B[2];
float h = B[3];
C[0] = a*e + b*g;
C[1] = a*f + b*h;
C[2] = c*e + d*g;
C[3] = c*f + d*h;
}
__device__ void pinv(float *A, float *B)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
B[0] = e_i*a + f_i*b;
B[1] = e_i*c + f_i*d;
B[2] = g_i*a + h_i*b;
B[3] = g_i*c + h_i*d;
}
__device__ float pdf(float *x, float *mean, float* cov)
{
float a = cov[0];
float b = cov[1];
float logdet = log(a*a - b*b);
float root = sqrt(2.0)/2.0;
float e = root * (1.0/sqrt(a-b));
float f = root * (1.0/sqrt(a+b));
float m = x[0] - mean[0];
float n = x[1] - mean[1];
float maha = 2*(m*m*e*e + n*n*f*f);
float log2pi = log(2 * M_PI);
return exp(-0.5 * (2*log2pi + maha + logdet));
}
__device__ void compute_dist_matrix(float *particle, landmark_measurements *measurements, dist_matrix *matrix)
{
float *measurement_cov = measurements->measurement_cov;
float pos[] = { particle[0], particle[1] };
float *landmarks_cov = get_cov(particle, 0);
for(int i = 0; i < matrix->n_landmarks; i++) {
float *landmark = get_mean(particle, i);
for(int j = 0; j < matrix->n_measurements; j++) {
float measurement_predicted[] = {
landmark[0] - pos[0], landmark[1] - pos[1]
};
float cov[4] = {
landmarks_cov[4*i] + measurement_cov[0],
landmarks_cov[4*i+1] + measurement_cov[1],
landmarks_cov[4*i+2] + measurement_cov[2],
landmarks_cov[4*i+3] + measurement_cov[3]
};
matrix->matrix[i * matrix->n_measurements + j] = pdf(measurement_predicted, measurements->measurements[j], cov);
}
}
}
__device__ void assign(dist_matrix *matrix, int *data_assoc_memory, assignment *assignment, float threshold) {
int n_landmarks = matrix->n_landmarks;
int n_measurements = matrix->n_measurements;
int *landmark_idx = data_assoc_memory;
int *measurement_idx = landmark_idx + (n_landmarks * n_measurements);
int k = 0;
for(int i = 0; i < n_landmarks; i++) {
for(int j = 0; j < n_measurements; j++) {
// only take values > threshold
if(matrix->matrix[i * n_measurements + j] > threshold) {
landmark_idx[k] = i;
measurement_idx[k] = j;
matrix->matrix[k] = matrix->matrix[i * n_measurements + j];
k++;
}
}
}
insertion_sort(matrix->matrix, landmark_idx, measurement_idx, k);
int iterations = MIN(n_landmarks, k);
for(int i = 0; i < iterations; i++) {
int a = landmark_idx[i];
int b = measurement_idx[i];
if(assignment->assignment[a] != -1){
continue;
}
assignment->assignment[a] = b;
assignment->assigned_measurements[b] = true;
}
}
__device__ void associate_landmarks_measurements(float *particle, float *m, int *data_assoc_memory, landmark_measurements *measurements, int n_landmarks, assignment *assignment, float threshold) {
int n_measurements = measurements->n_measurements;
dist_matrix matrix;
matrix.matrix = m;
matrix.n_landmarks = n_landmarks;
matrix.n_measurements = n_measurements;
compute_dist_matrix(particle, measurements, &matrix);
assign(&matrix, data_assoc_memory, assignment, threshold);
}
__device__ void update_landmark(float *particle, landmark_measurements *measurements, assignment *assignment)
{
float *measurement_cov = measurements->measurement_cov;
float x = particle[0];
float y = particle[1];
int n_landmarks = get_n_landmarks(particle);
for(int i = 0; i < n_landmarks; i++) {
int j = assignment->assignment[i];
if(j == -1) {
continue;
}
float *mean = get_mean(particle, i);
float mean_x = mean[0];
float mean_y = mean[1];
float measurement_predicted[2] = { mean_x - x, mean_y - y };
float residual[2] = {
measurements->measurements[j][0] - measurement_predicted[0],
measurements->measurements[j][1] - measurement_predicted[1]
};
float *cov = get_cov(particle, i);
float Q[4] = {
cov[0] + measurement_cov[0],
cov[1] + measurement_cov[1],
cov[2] + measurement_cov[2],
cov[3] + measurement_cov[3]
};
float K[4] = { 0, 0, 0, 0 };
float Q_inv[4] = { 0, 0, 0, 0 };
pinv(Q, Q_inv);
matmul(cov, Q_inv, K);
float K_residual[] = { 0, 0 };
vecmul(K, residual, K_residual);
mean[0] += K_residual[0];
mean[1] += K_residual[1];
float new_cov[] = { 1 - K[0], K[1], K[2], 1 - K[3] };
matmul(new_cov, cov, new_cov);
cov[0] = new_cov[0];
cov[1] = new_cov[1];
cov[2] = new_cov[2];
cov[3] = new_cov[3];
particle[3] *= pdf(measurements->measurements[j], measurement_predicted, Q);
}
}
__device__ int get_max_landmarks_in_block(float *particles, int block_size, int thread_id, int n_particles) {
int max_landmarks = 0;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
break;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks > max_landmarks) {
max_landmarks = n_landmarks;
}
}
return max_landmarks;
}
__global__ void update(
float *particles, int block_size, float measurements_array[][2], int n_particles, int n_measurements,
float *measurement_cov, float threshold/*, int *scratchpad_memory, int size*/)
{
// int i = threadIdx.x + blockIdx.x * blockDim.x;
if(n_measurements == 0) {
return;
}
int block_id = blockIdx.x+ blockIdx.y * gridDim.x;
int thread_id = block_id * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
int max_landmarks = get_max_landmarks_in_block(particles, block_size, thread_id, n_particles);
int scratchpad_size = (max_landmarks + n_measurements + (3 * max_landmarks * n_measurements)) * sizeof(int);
int *scratchpad;
int *assignment_memory;
int *data_assoc_memory;
float *matrix_memory;
if(scratchpad_size > 0) {
scratchpad = (int *)malloc(scratchpad_size);
assignment_memory = scratchpad;
data_assoc_memory = assignment_memory + (max_landmarks + n_measurements);
matrix_memory = (float *)(data_assoc_memory + (2 * max_landmarks * n_measurements));
}
landmark_measurements measurements;
measurements.n_measurements = n_measurements;
measurements.measurement_cov = measurement_cov;
measurements.measurements = measurements_array;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
return;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks == 0) {
add_measurements_as_landmarks(particle, &measurements);
continue;
}
bool *assigned_measurements = (bool *)(assignment_memory);
int *assignment_lm = (int *)(assignment_memory + n_measurements);
for(int i = 0; i < n_measurements; i++) {
assigned_measurements[i] = false;
}
for(int i = 0; i < n_landmarks; i++) {
assignment_lm[i] = -1;
}
assignment assignmentx;
assignmentx.assignment = assignment_lm;
assignmentx.assigned_measurements = assigned_measurements;
associate_landmarks_measurements(
particle, matrix_memory, data_assoc_memory, &measurements,
n_landmarks, &assignmentx,
threshold
);
update_landmark(particle, &measurements, &assignmentx);
add_unassigned_measurements_as_landmarks(particle, assignmentx.assigned_measurements, &measurements);
}
if(scratchpad_size > 0) {
free(scratchpad);
}
} | .file "tmpxft_0013cecf_00000000-6_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2046:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2046:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12get_particlePfi
.type _Z12get_particlePfi, @function
_Z12get_particlePfi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12get_particlePfi, .-_Z12get_particlePfi
.globl _Z8get_meanPfi
.type _Z8get_meanPfi, @function
_Z8get_meanPfi:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z8get_meanPfi, .-_Z8get_meanPfi
.globl _Z7get_covPfi
.type _Z7get_covPfi, @function
_Z7get_covPfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z7get_covPfi, .-_Z7get_covPfi
.globl _Z15get_n_landmarksPf
.type _Z15get_n_landmarksPf, @function
_Z15get_n_landmarksPf:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z15get_n_landmarksPf, .-_Z15get_n_landmarksPf
.globl _Z12add_landmarkPfS_S_
.type _Z12add_landmarkPfS_S_, @function
_Z12add_landmarkPfS_S_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z12add_landmarkPfS_S_, .-_Z12add_landmarkPfS_S_
.globl _Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements
.type _Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements, @function
_Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements, .-_Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements
.globl _Z29add_measurements_as_landmarksPfP21landmark_measurements
.type _Z29add_measurements_as_landmarksPfP21landmark_measurements, @function
_Z29add_measurements_as_landmarksPfP21landmark_measurements:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z29add_measurements_as_landmarksPfP21landmark_measurements, .-_Z29add_measurements_as_landmarksPfP21landmark_measurements
.globl _Z14insertion_sortPfPiS0_i
.type _Z14insertion_sortPfPiS0_i, @function
_Z14insertion_sortPfPiS0_i:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z14insertion_sortPfPiS0_i, .-_Z14insertion_sortPfPiS0_i
.globl _Z6vecmulPfS_S_
.type _Z6vecmulPfS_S_, @function
_Z6vecmulPfS_S_:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z6vecmulPfS_S_, .-_Z6vecmulPfS_S_
.globl _Z6matmulPfS_S_
.type _Z6matmulPfS_S_, @function
_Z6matmulPfS_S_:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z6matmulPfS_S_, .-_Z6matmulPfS_S_
.globl _Z4pinvPfS_
.type _Z4pinvPfS_, @function
_Z4pinvPfS_:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z4pinvPfS_, .-_Z4pinvPfS_
.globl _Z3pdfPfS_S_
.type _Z3pdfPfS_S_, @function
_Z3pdfPfS_S_:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Z3pdfPfS_S_, .-_Z3pdfPfS_S_
.globl _Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix
.type _Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix, @function
_Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix:
.LFB2039:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2039:
.size _Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix, .-_Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix
.globl _Z6assignP11dist_matrixPiP10assignmentf
.type _Z6assignP11dist_matrixPiP10assignmentf, @function
_Z6assignP11dist_matrixPiP10assignmentf:
.LFB2040:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2040:
.size _Z6assignP11dist_matrixPiP10assignmentf, .-_Z6assignP11dist_matrixPiP10assignmentf
.globl _Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf
.type _Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf, @function
_Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf:
.LFB2041:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2041:
.size _Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf, .-_Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf
.globl _Z15update_landmarkPfP21landmark_measurementsP10assignment
.type _Z15update_landmarkPfP21landmark_measurementsP10assignment, @function
_Z15update_landmarkPfP21landmark_measurementsP10assignment:
.LFB2042:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2042:
.size _Z15update_landmarkPfP21landmark_measurementsP10assignment, .-_Z15update_landmarkPfP21landmark_measurementsP10assignment
.globl _Z26get_max_landmarks_in_blockPfiii
.type _Z26get_max_landmarks_in_blockPfiii, @function
_Z26get_max_landmarks_in_blockPfiii:
.LFB2043:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2043:
.size _Z26get_max_landmarks_in_blockPfiii, .-_Z26get_max_landmarks_in_blockPfiii
.globl _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f
.type _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f, @function
_Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f:
.LFB2068:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movss %xmm0, 16(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6updatePfiPA2_fiiS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f, .-_Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f
.globl _Z6updatePfiPA2_fiiS_f
.type _Z6updatePfiPA2_fiiS_f, @function
_Z6updatePfiPA2_fiiS_f:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _Z6updatePfiPA2_fiiS_f, .-_Z6updatePfiPA2_fiiS_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updatePfiPA2_fiiS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfiPA2_fiiS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdbool.h>
#include <math.h>
#define M_PI 3.14159265359
#define MIN(a,b) (((a)<(b))?(a):(b))
typedef struct
{
float *matrix;
int n_landmarks;
int n_measurements;
} dist_matrix;
typedef struct
{
int *assignment;
bool *assigned_measurements;
} assignment;
typedef struct
{
float (*measurements)[2];
int n_measurements;
float *measurement_cov;
} landmark_measurements;
__device__ float* get_particle(float *particles, int i) {
int max_landmarks = (int)particles[4];
return (particles + (6 + 6*max_landmarks)*i);
}
__device__ float* get_mean(float *particle, int i)
{
return (particle + 6 + 2*i);
}
__device__ float* get_cov(float *particle, int i)
{
int max_landmarks = (int)particle[4];
return (particle + 6 + 2*max_landmarks + 4*i);
}
__device__ int get_n_landmarks(float *particle)
{
return (int)particle[5];
}
__device__ void add_landmark(float *particle, float mean[2], float *cov)
{
int n_landmarks = (int)particle[5];
particle[5] = (float)(n_landmarks + 1);
float *new_mean = get_mean(particle, n_landmarks);
float *new_cov = get_cov(particle, n_landmarks);
new_mean[0] = mean[0];
new_mean[1] = mean[1];
new_cov[0] = cov[0];
new_cov[1] = cov[1];
new_cov[2] = cov[2];
new_cov[3] = cov[3];
}
__device__ void add_unassigned_measurements_as_landmarks(float *particle, bool *assigned_measurements, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
if(!assigned_measurements[i]) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
}
__device__ void add_measurements_as_landmarks(float *particle, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
__device__ void insertion_sort(float arr[], int lm[], int me[], int n)
{
int i, lm_key, me_key, j;
float key;
for (i = 1; i < n; i++) {
key = arr[i];
lm_key = lm[i];
me_key = me[i];
j = i - 1;
while (j >= 0 && arr[j] < key) {
arr[j + 1] = arr[j];
lm[j + 1] = lm[j];
me[j + 1] = me[j];
j = j - 1;
}
arr[j + 1] = key;
lm[j + 1] = lm_key;
me[j + 1] = me_key;
}
}
__device__ void vecmul(float *A, float *u, float *v)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = u[0];
float f = v[1];
v[0] = a*e + b*f;
v[1] = c*e + d*f;
}
__device__ void matmul(float *A, float *B, float *C)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = B[0];
float f = B[1];
float g = B[2];
float h = B[3];
C[0] = a*e + b*g;
C[1] = a*f + b*h;
C[2] = c*e + d*g;
C[3] = c*f + d*h;
}
__device__ void pinv(float *A, float *B)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
B[0] = e_i*a + f_i*b;
B[1] = e_i*c + f_i*d;
B[2] = g_i*a + h_i*b;
B[3] = g_i*c + h_i*d;
}
__device__ float pdf(float *x, float *mean, float* cov)
{
float a = cov[0];
float b = cov[1];
float logdet = log(a*a - b*b);
float root = sqrt(2.0)/2.0;
float e = root * (1.0/sqrt(a-b));
float f = root * (1.0/sqrt(a+b));
float m = x[0] - mean[0];
float n = x[1] - mean[1];
float maha = 2*(m*m*e*e + n*n*f*f);
float log2pi = log(2 * M_PI);
return exp(-0.5 * (2*log2pi + maha + logdet));
}
__device__ void compute_dist_matrix(float *particle, landmark_measurements *measurements, dist_matrix *matrix)
{
float *measurement_cov = measurements->measurement_cov;
float pos[] = { particle[0], particle[1] };
float *landmarks_cov = get_cov(particle, 0);
for(int i = 0; i < matrix->n_landmarks; i++) {
float *landmark = get_mean(particle, i);
for(int j = 0; j < matrix->n_measurements; j++) {
float measurement_predicted[] = {
landmark[0] - pos[0], landmark[1] - pos[1]
};
float cov[4] = {
landmarks_cov[4*i] + measurement_cov[0],
landmarks_cov[4*i+1] + measurement_cov[1],
landmarks_cov[4*i+2] + measurement_cov[2],
landmarks_cov[4*i+3] + measurement_cov[3]
};
matrix->matrix[i * matrix->n_measurements + j] = pdf(measurement_predicted, measurements->measurements[j], cov);
}
}
}
__device__ void assign(dist_matrix *matrix, int *data_assoc_memory, assignment *assignment, float threshold) {
int n_landmarks = matrix->n_landmarks;
int n_measurements = matrix->n_measurements;
int *landmark_idx = data_assoc_memory;
int *measurement_idx = landmark_idx + (n_landmarks * n_measurements);
int k = 0;
for(int i = 0; i < n_landmarks; i++) {
for(int j = 0; j < n_measurements; j++) {
// only take values > threshold
if(matrix->matrix[i * n_measurements + j] > threshold) {
landmark_idx[k] = i;
measurement_idx[k] = j;
matrix->matrix[k] = matrix->matrix[i * n_measurements + j];
k++;
}
}
}
insertion_sort(matrix->matrix, landmark_idx, measurement_idx, k);
int iterations = MIN(n_landmarks, k);
for(int i = 0; i < iterations; i++) {
int a = landmark_idx[i];
int b = measurement_idx[i];
if(assignment->assignment[a] != -1){
continue;
}
assignment->assignment[a] = b;
assignment->assigned_measurements[b] = true;
}
}
__device__ void associate_landmarks_measurements(float *particle, float *m, int *data_assoc_memory, landmark_measurements *measurements, int n_landmarks, assignment *assignment, float threshold) {
int n_measurements = measurements->n_measurements;
dist_matrix matrix;
matrix.matrix = m;
matrix.n_landmarks = n_landmarks;
matrix.n_measurements = n_measurements;
compute_dist_matrix(particle, measurements, &matrix);
assign(&matrix, data_assoc_memory, assignment, threshold);
}
__device__ void update_landmark(float *particle, landmark_measurements *measurements, assignment *assignment)
{
float *measurement_cov = measurements->measurement_cov;
float x = particle[0];
float y = particle[1];
int n_landmarks = get_n_landmarks(particle);
for(int i = 0; i < n_landmarks; i++) {
int j = assignment->assignment[i];
if(j == -1) {
continue;
}
float *mean = get_mean(particle, i);
float mean_x = mean[0];
float mean_y = mean[1];
float measurement_predicted[2] = { mean_x - x, mean_y - y };
float residual[2] = {
measurements->measurements[j][0] - measurement_predicted[0],
measurements->measurements[j][1] - measurement_predicted[1]
};
float *cov = get_cov(particle, i);
float Q[4] = {
cov[0] + measurement_cov[0],
cov[1] + measurement_cov[1],
cov[2] + measurement_cov[2],
cov[3] + measurement_cov[3]
};
float K[4] = { 0, 0, 0, 0 };
float Q_inv[4] = { 0, 0, 0, 0 };
pinv(Q, Q_inv);
matmul(cov, Q_inv, K);
float K_residual[] = { 0, 0 };
vecmul(K, residual, K_residual);
mean[0] += K_residual[0];
mean[1] += K_residual[1];
float new_cov[] = { 1 - K[0], K[1], K[2], 1 - K[3] };
matmul(new_cov, cov, new_cov);
cov[0] = new_cov[0];
cov[1] = new_cov[1];
cov[2] = new_cov[2];
cov[3] = new_cov[3];
particle[3] *= pdf(measurements->measurements[j], measurement_predicted, Q);
}
}
__device__ int get_max_landmarks_in_block(float *particles, int block_size, int thread_id, int n_particles) {
int max_landmarks = 0;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
break;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks > max_landmarks) {
max_landmarks = n_landmarks;
}
}
return max_landmarks;
}
__global__ void update(
float *particles, int block_size, float measurements_array[][2], int n_particles, int n_measurements,
float *measurement_cov, float threshold/*, int *scratchpad_memory, int size*/)
{
// int i = threadIdx.x + blockIdx.x * blockDim.x;
if(n_measurements == 0) {
return;
}
int block_id = blockIdx.x+ blockIdx.y * gridDim.x;
int thread_id = block_id * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
int max_landmarks = get_max_landmarks_in_block(particles, block_size, thread_id, n_particles);
int scratchpad_size = (max_landmarks + n_measurements + (3 * max_landmarks * n_measurements)) * sizeof(int);
int *scratchpad;
int *assignment_memory;
int *data_assoc_memory;
float *matrix_memory;
if(scratchpad_size > 0) {
scratchpad = (int *)malloc(scratchpad_size);
assignment_memory = scratchpad;
data_assoc_memory = assignment_memory + (max_landmarks + n_measurements);
matrix_memory = (float *)(data_assoc_memory + (2 * max_landmarks * n_measurements));
}
landmark_measurements measurements;
measurements.n_measurements = n_measurements;
measurements.measurement_cov = measurement_cov;
measurements.measurements = measurements_array;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
return;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks == 0) {
add_measurements_as_landmarks(particle, &measurements);
continue;
}
bool *assigned_measurements = (bool *)(assignment_memory);
int *assignment_lm = (int *)(assignment_memory + n_measurements);
for(int i = 0; i < n_measurements; i++) {
assigned_measurements[i] = false;
}
for(int i = 0; i < n_landmarks; i++) {
assignment_lm[i] = -1;
}
assignment assignmentx;
assignmentx.assignment = assignment_lm;
assignmentx.assigned_measurements = assigned_measurements;
associate_landmarks_measurements(
particle, matrix_memory, data_assoc_memory, &measurements,
n_landmarks, &assignmentx,
threshold
);
update_landmark(particle, &measurements, &assignmentx);
add_unassigned_measurements_as_landmarks(particle, assignmentx.assigned_measurements, &measurements);
}
if(scratchpad_size > 0) {
free(scratchpad);
}
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdbool.h>
#include <math.h>
#define M_PI 3.14159265359
#define MIN(a,b) (((a)<(b))?(a):(b))
typedef struct
{
float *matrix;
int n_landmarks;
int n_measurements;
} dist_matrix;
typedef struct
{
int *assignment;
bool *assigned_measurements;
} assignment;
typedef struct
{
float (*measurements)[2];
int n_measurements;
float *measurement_cov;
} landmark_measurements;
__device__ float* get_particle(float *particles, int i) {
int max_landmarks = (int)particles[4];
return (particles + (6 + 6*max_landmarks)*i);
}
__device__ float* get_mean(float *particle, int i)
{
return (particle + 6 + 2*i);
}
__device__ float* get_cov(float *particle, int i)
{
int max_landmarks = (int)particle[4];
return (particle + 6 + 2*max_landmarks + 4*i);
}
__device__ int get_n_landmarks(float *particle)
{
return (int)particle[5];
}
__device__ void add_landmark(float *particle, float mean[2], float *cov)
{
int n_landmarks = (int)particle[5];
particle[5] = (float)(n_landmarks + 1);
float *new_mean = get_mean(particle, n_landmarks);
float *new_cov = get_cov(particle, n_landmarks);
new_mean[0] = mean[0];
new_mean[1] = mean[1];
new_cov[0] = cov[0];
new_cov[1] = cov[1];
new_cov[2] = cov[2];
new_cov[3] = cov[3];
}
__device__ void add_unassigned_measurements_as_landmarks(float *particle, bool *assigned_measurements, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
if(!assigned_measurements[i]) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
}
__device__ void add_measurements_as_landmarks(float *particle, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
__device__ void insertion_sort(float arr[], int lm[], int me[], int n)
{
int i, lm_key, me_key, j;
float key;
for (i = 1; i < n; i++) {
key = arr[i];
lm_key = lm[i];
me_key = me[i];
j = i - 1;
while (j >= 0 && arr[j] < key) {
arr[j + 1] = arr[j];
lm[j + 1] = lm[j];
me[j + 1] = me[j];
j = j - 1;
}
arr[j + 1] = key;
lm[j + 1] = lm_key;
me[j + 1] = me_key;
}
}
__device__ void vecmul(float *A, float *u, float *v)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = u[0];
float f = v[1];
v[0] = a*e + b*f;
v[1] = c*e + d*f;
}
__device__ void matmul(float *A, float *B, float *C)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = B[0];
float f = B[1];
float g = B[2];
float h = B[3];
C[0] = a*e + b*g;
C[1] = a*f + b*h;
C[2] = c*e + d*g;
C[3] = c*f + d*h;
}
__device__ void pinv(float *A, float *B)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
B[0] = e_i*a + f_i*b;
B[1] = e_i*c + f_i*d;
B[2] = g_i*a + h_i*b;
B[3] = g_i*c + h_i*d;
}
__device__ float pdf(float *x, float *mean, float* cov)
{
float a = cov[0];
float b = cov[1];
float logdet = log(a*a - b*b);
float root = sqrt(2.0)/2.0;
float e = root * (1.0/sqrt(a-b));
float f = root * (1.0/sqrt(a+b));
float m = x[0] - mean[0];
float n = x[1] - mean[1];
float maha = 2*(m*m*e*e + n*n*f*f);
float log2pi = log(2 * M_PI);
return exp(-0.5 * (2*log2pi + maha + logdet));
}
__device__ void compute_dist_matrix(float *particle, landmark_measurements *measurements, dist_matrix *matrix)
{
float *measurement_cov = measurements->measurement_cov;
float pos[] = { particle[0], particle[1] };
float *landmarks_cov = get_cov(particle, 0);
for(int i = 0; i < matrix->n_landmarks; i++) {
float *landmark = get_mean(particle, i);
for(int j = 0; j < matrix->n_measurements; j++) {
float measurement_predicted[] = {
landmark[0] - pos[0], landmark[1] - pos[1]
};
float cov[4] = {
landmarks_cov[4*i] + measurement_cov[0],
landmarks_cov[4*i+1] + measurement_cov[1],
landmarks_cov[4*i+2] + measurement_cov[2],
landmarks_cov[4*i+3] + measurement_cov[3]
};
matrix->matrix[i * matrix->n_measurements + j] = pdf(measurement_predicted, measurements->measurements[j], cov);
}
}
}
__device__ void assign(dist_matrix *matrix, int *data_assoc_memory, assignment *assignment, float threshold) {
int n_landmarks = matrix->n_landmarks;
int n_measurements = matrix->n_measurements;
int *landmark_idx = data_assoc_memory;
int *measurement_idx = landmark_idx + (n_landmarks * n_measurements);
int k = 0;
for(int i = 0; i < n_landmarks; i++) {
for(int j = 0; j < n_measurements; j++) {
// only take values > threshold
if(matrix->matrix[i * n_measurements + j] > threshold) {
landmark_idx[k] = i;
measurement_idx[k] = j;
matrix->matrix[k] = matrix->matrix[i * n_measurements + j];
k++;
}
}
}
insertion_sort(matrix->matrix, landmark_idx, measurement_idx, k);
int iterations = MIN(n_landmarks, k);
for(int i = 0; i < iterations; i++) {
int a = landmark_idx[i];
int b = measurement_idx[i];
if(assignment->assignment[a] != -1){
continue;
}
assignment->assignment[a] = b;
assignment->assigned_measurements[b] = true;
}
}
__device__ void associate_landmarks_measurements(float *particle, float *m, int *data_assoc_memory, landmark_measurements *measurements, int n_landmarks, assignment *assignment, float threshold) {
int n_measurements = measurements->n_measurements;
dist_matrix matrix;
matrix.matrix = m;
matrix.n_landmarks = n_landmarks;
matrix.n_measurements = n_measurements;
compute_dist_matrix(particle, measurements, &matrix);
assign(&matrix, data_assoc_memory, assignment, threshold);
}
__device__ void update_landmark(float *particle, landmark_measurements *measurements, assignment *assignment)
{
float *measurement_cov = measurements->measurement_cov;
float x = particle[0];
float y = particle[1];
int n_landmarks = get_n_landmarks(particle);
for(int i = 0; i < n_landmarks; i++) {
int j = assignment->assignment[i];
if(j == -1) {
continue;
}
float *mean = get_mean(particle, i);
float mean_x = mean[0];
float mean_y = mean[1];
float measurement_predicted[2] = { mean_x - x, mean_y - y };
float residual[2] = {
measurements->measurements[j][0] - measurement_predicted[0],
measurements->measurements[j][1] - measurement_predicted[1]
};
float *cov = get_cov(particle, i);
float Q[4] = {
cov[0] + measurement_cov[0],
cov[1] + measurement_cov[1],
cov[2] + measurement_cov[2],
cov[3] + measurement_cov[3]
};
float K[4] = { 0, 0, 0, 0 };
float Q_inv[4] = { 0, 0, 0, 0 };
pinv(Q, Q_inv);
matmul(cov, Q_inv, K);
float K_residual[] = { 0, 0 };
vecmul(K, residual, K_residual);
mean[0] += K_residual[0];
mean[1] += K_residual[1];
float new_cov[] = { 1 - K[0], K[1], K[2], 1 - K[3] };
matmul(new_cov, cov, new_cov);
cov[0] = new_cov[0];
cov[1] = new_cov[1];
cov[2] = new_cov[2];
cov[3] = new_cov[3];
particle[3] *= pdf(measurements->measurements[j], measurement_predicted, Q);
}
}
__device__ int get_max_landmarks_in_block(float *particles, int block_size, int thread_id, int n_particles) {
int max_landmarks = 0;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
break;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks > max_landmarks) {
max_landmarks = n_landmarks;
}
}
return max_landmarks;
}
__global__ void update(
float *particles, int block_size, float measurements_array[][2], int n_particles, int n_measurements,
float *measurement_cov, float threshold/*, int *scratchpad_memory, int size*/)
{
// int i = threadIdx.x + blockIdx.x * blockDim.x;
if(n_measurements == 0) {
return;
}
int block_id = blockIdx.x+ blockIdx.y * gridDim.x;
int thread_id = block_id * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
int max_landmarks = get_max_landmarks_in_block(particles, block_size, thread_id, n_particles);
int scratchpad_size = (max_landmarks + n_measurements + (3 * max_landmarks * n_measurements)) * sizeof(int);
int *scratchpad;
int *assignment_memory;
int *data_assoc_memory;
float *matrix_memory;
if(scratchpad_size > 0) {
scratchpad = (int *)malloc(scratchpad_size);
assignment_memory = scratchpad;
data_assoc_memory = assignment_memory + (max_landmarks + n_measurements);
matrix_memory = (float *)(data_assoc_memory + (2 * max_landmarks * n_measurements));
}
landmark_measurements measurements;
measurements.n_measurements = n_measurements;
measurements.measurement_cov = measurement_cov;
measurements.measurements = measurements_array;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
return;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks == 0) {
add_measurements_as_landmarks(particle, &measurements);
continue;
}
bool *assigned_measurements = (bool *)(assignment_memory);
int *assignment_lm = (int *)(assignment_memory + n_measurements);
for(int i = 0; i < n_measurements; i++) {
assigned_measurements[i] = false;
}
for(int i = 0; i < n_landmarks; i++) {
assignment_lm[i] = -1;
}
assignment assignmentx;
assignmentx.assignment = assignment_lm;
assignmentx.assigned_measurements = assigned_measurements;
associate_landmarks_measurements(
particle, matrix_memory, data_assoc_memory, &measurements,
n_landmarks, &assignmentx,
threshold
);
update_landmark(particle, &measurements, &assignmentx);
add_unassigned_measurements_as_landmarks(particle, assignmentx.assigned_measurements, &measurements);
}
if(scratchpad_size > 0) {
free(scratchpad);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdbool.h>
#include <math.h>
#define M_PI 3.14159265359
#define MIN(a,b) (((a)<(b))?(a):(b))
typedef struct
{
float *matrix;
int n_landmarks;
int n_measurements;
} dist_matrix;
typedef struct
{
int *assignment;
bool *assigned_measurements;
} assignment;
typedef struct
{
float (*measurements)[2];
int n_measurements;
float *measurement_cov;
} landmark_measurements;
__device__ float* get_particle(float *particles, int i) {
int max_landmarks = (int)particles[4];
return (particles + (6 + 6*max_landmarks)*i);
}
__device__ float* get_mean(float *particle, int i)
{
return (particle + 6 + 2*i);
}
__device__ float* get_cov(float *particle, int i)
{
int max_landmarks = (int)particle[4];
return (particle + 6 + 2*max_landmarks + 4*i);
}
__device__ int get_n_landmarks(float *particle)
{
return (int)particle[5];
}
__device__ void add_landmark(float *particle, float mean[2], float *cov)
{
int n_landmarks = (int)particle[5];
particle[5] = (float)(n_landmarks + 1);
float *new_mean = get_mean(particle, n_landmarks);
float *new_cov = get_cov(particle, n_landmarks);
new_mean[0] = mean[0];
new_mean[1] = mean[1];
new_cov[0] = cov[0];
new_cov[1] = cov[1];
new_cov[2] = cov[2];
new_cov[3] = cov[3];
}
__device__ void add_unassigned_measurements_as_landmarks(float *particle, bool *assigned_measurements, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
if(!assigned_measurements[i]) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
}
__device__ void add_measurements_as_landmarks(float *particle, landmark_measurements *measurements)
{
int n_measurements = measurements->n_measurements;
float *measurement_cov = measurements->measurement_cov;
for(int i = 0; i < n_measurements; i++) {
float x = particle[0];
float y = particle[1];
float measurement[] = {
x + measurements->measurements[i][0],
y + measurements->measurements[i][1]
};
add_landmark(particle, measurement, measurement_cov);
}
}
__device__ void insertion_sort(float arr[], int lm[], int me[], int n)
{
int i, lm_key, me_key, j;
float key;
for (i = 1; i < n; i++) {
key = arr[i];
lm_key = lm[i];
me_key = me[i];
j = i - 1;
while (j >= 0 && arr[j] < key) {
arr[j + 1] = arr[j];
lm[j + 1] = lm[j];
me[j + 1] = me[j];
j = j - 1;
}
arr[j + 1] = key;
lm[j + 1] = lm_key;
me[j + 1] = me_key;
}
}
__device__ void vecmul(float *A, float *u, float *v)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = u[0];
float f = v[1];
v[0] = a*e + b*f;
v[1] = c*e + d*f;
}
__device__ void matmul(float *A, float *B, float *C)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = B[0];
float f = B[1];
float g = B[2];
float h = B[3];
C[0] = a*e + b*g;
C[1] = a*f + b*h;
C[2] = c*e + d*g;
C[3] = c*f + d*h;
}
__device__ void pinv(float *A, float *B)
{
float a = A[0];
float b = A[1];
float c = A[2];
float d = A[3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
B[0] = e_i*a + f_i*b;
B[1] = e_i*c + f_i*d;
B[2] = g_i*a + h_i*b;
B[3] = g_i*c + h_i*d;
}
__device__ float pdf(float *x, float *mean, float* cov)
{
float a = cov[0];
float b = cov[1];
float logdet = log(a*a - b*b);
float root = sqrt(2.0)/2.0;
float e = root * (1.0/sqrt(a-b));
float f = root * (1.0/sqrt(a+b));
float m = x[0] - mean[0];
float n = x[1] - mean[1];
float maha = 2*(m*m*e*e + n*n*f*f);
float log2pi = log(2 * M_PI);
return exp(-0.5 * (2*log2pi + maha + logdet));
}
__device__ void compute_dist_matrix(float *particle, landmark_measurements *measurements, dist_matrix *matrix)
{
float *measurement_cov = measurements->measurement_cov;
float pos[] = { particle[0], particle[1] };
float *landmarks_cov = get_cov(particle, 0);
for(int i = 0; i < matrix->n_landmarks; i++) {
float *landmark = get_mean(particle, i);
for(int j = 0; j < matrix->n_measurements; j++) {
float measurement_predicted[] = {
landmark[0] - pos[0], landmark[1] - pos[1]
};
float cov[4] = {
landmarks_cov[4*i] + measurement_cov[0],
landmarks_cov[4*i+1] + measurement_cov[1],
landmarks_cov[4*i+2] + measurement_cov[2],
landmarks_cov[4*i+3] + measurement_cov[3]
};
matrix->matrix[i * matrix->n_measurements + j] = pdf(measurement_predicted, measurements->measurements[j], cov);
}
}
}
__device__ void assign(dist_matrix *matrix, int *data_assoc_memory, assignment *assignment, float threshold) {
int n_landmarks = matrix->n_landmarks;
int n_measurements = matrix->n_measurements;
int *landmark_idx = data_assoc_memory;
int *measurement_idx = landmark_idx + (n_landmarks * n_measurements);
int k = 0;
for(int i = 0; i < n_landmarks; i++) {
for(int j = 0; j < n_measurements; j++) {
// only take values > threshold
if(matrix->matrix[i * n_measurements + j] > threshold) {
landmark_idx[k] = i;
measurement_idx[k] = j;
matrix->matrix[k] = matrix->matrix[i * n_measurements + j];
k++;
}
}
}
insertion_sort(matrix->matrix, landmark_idx, measurement_idx, k);
int iterations = MIN(n_landmarks, k);
for(int i = 0; i < iterations; i++) {
int a = landmark_idx[i];
int b = measurement_idx[i];
if(assignment->assignment[a] != -1){
continue;
}
assignment->assignment[a] = b;
assignment->assigned_measurements[b] = true;
}
}
__device__ void associate_landmarks_measurements(float *particle, float *m, int *data_assoc_memory, landmark_measurements *measurements, int n_landmarks, assignment *assignment, float threshold) {
int n_measurements = measurements->n_measurements;
dist_matrix matrix;
matrix.matrix = m;
matrix.n_landmarks = n_landmarks;
matrix.n_measurements = n_measurements;
compute_dist_matrix(particle, measurements, &matrix);
assign(&matrix, data_assoc_memory, assignment, threshold);
}
__device__ void update_landmark(float *particle, landmark_measurements *measurements, assignment *assignment)
{
float *measurement_cov = measurements->measurement_cov;
float x = particle[0];
float y = particle[1];
int n_landmarks = get_n_landmarks(particle);
for(int i = 0; i < n_landmarks; i++) {
int j = assignment->assignment[i];
if(j == -1) {
continue;
}
float *mean = get_mean(particle, i);
float mean_x = mean[0];
float mean_y = mean[1];
float measurement_predicted[2] = { mean_x - x, mean_y - y };
float residual[2] = {
measurements->measurements[j][0] - measurement_predicted[0],
measurements->measurements[j][1] - measurement_predicted[1]
};
float *cov = get_cov(particle, i);
float Q[4] = {
cov[0] + measurement_cov[0],
cov[1] + measurement_cov[1],
cov[2] + measurement_cov[2],
cov[3] + measurement_cov[3]
};
float K[4] = { 0, 0, 0, 0 };
float Q_inv[4] = { 0, 0, 0, 0 };
pinv(Q, Q_inv);
matmul(cov, Q_inv, K);
float K_residual[] = { 0, 0 };
vecmul(K, residual, K_residual);
mean[0] += K_residual[0];
mean[1] += K_residual[1];
float new_cov[] = { 1 - K[0], K[1], K[2], 1 - K[3] };
matmul(new_cov, cov, new_cov);
cov[0] = new_cov[0];
cov[1] = new_cov[1];
cov[2] = new_cov[2];
cov[3] = new_cov[3];
particle[3] *= pdf(measurements->measurements[j], measurement_predicted, Q);
}
}
__device__ int get_max_landmarks_in_block(float *particles, int block_size, int thread_id, int n_particles) {
int max_landmarks = 0;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
break;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks > max_landmarks) {
max_landmarks = n_landmarks;
}
}
return max_landmarks;
}
__global__ void update(
float *particles, int block_size, float measurements_array[][2], int n_particles, int n_measurements,
float *measurement_cov, float threshold/*, int *scratchpad_memory, int size*/)
{
// int i = threadIdx.x + blockIdx.x * blockDim.x;
if(n_measurements == 0) {
return;
}
int block_id = blockIdx.x+ blockIdx.y * gridDim.x;
int thread_id = block_id * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
int max_landmarks = get_max_landmarks_in_block(particles, block_size, thread_id, n_particles);
int scratchpad_size = (max_landmarks + n_measurements + (3 * max_landmarks * n_measurements)) * sizeof(int);
int *scratchpad;
int *assignment_memory;
int *data_assoc_memory;
float *matrix_memory;
if(scratchpad_size > 0) {
scratchpad = (int *)malloc(scratchpad_size);
assignment_memory = scratchpad;
data_assoc_memory = assignment_memory + (max_landmarks + n_measurements);
matrix_memory = (float *)(data_assoc_memory + (2 * max_landmarks * n_measurements));
}
landmark_measurements measurements;
measurements.n_measurements = n_measurements;
measurements.measurement_cov = measurement_cov;
measurements.measurements = measurements_array;
for(int k = 0; k < block_size; k++) {
int particle_id = thread_id*block_size + k;
if(particle_id >= n_particles) {
return;
}
float *particle = get_particle(particles, particle_id);
int n_landmarks = get_n_landmarks(particle);
if(n_landmarks == 0) {
add_measurements_as_landmarks(particle, &measurements);
continue;
}
bool *assigned_measurements = (bool *)(assignment_memory);
int *assignment_lm = (int *)(assignment_memory + n_measurements);
for(int i = 0; i < n_measurements; i++) {
assigned_measurements[i] = false;
}
for(int i = 0; i < n_landmarks; i++) {
assignment_lm[i] = -1;
}
assignment assignmentx;
assignmentx.assignment = assignment_lm;
assignmentx.assigned_measurements = assigned_measurements;
associate_landmarks_measurements(
particle, matrix_memory, data_assoc_memory, &measurements,
n_landmarks, &assignmentx,
threshold
);
update_landmark(particle, &measurements, &assignmentx);
add_unassigned_measurements_as_landmarks(particle, assignmentx.assigned_measurements, &measurements);
}
if(scratchpad_size > 0) {
free(scratchpad);
}
} | .text
.file "update.hip"
.globl _Z21__device_stub__updatePfiPA2_fiiS_f # -- Begin function _Z21__device_stub__updatePfiPA2_fiiS_f
.p2align 4, 0x90
.type _Z21__device_stub__updatePfiPA2_fiiS_f,@function
_Z21__device_stub__updatePfiPA2_fiiS_f: # @_Z21__device_stub__updatePfiPA2_fiiS_f
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
movss %xmm0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6updatePfiPA2_fiiS_f, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__updatePfiPA2_fiiS_f, .Lfunc_end0-_Z21__device_stub__updatePfiPA2_fiiS_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfiPA2_fiiS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6updatePfiPA2_fiiS_f,@object # @_Z6updatePfiPA2_fiiS_f
.section .rodata,"a",@progbits
.globl _Z6updatePfiPA2_fiiS_f
.p2align 3, 0x0
_Z6updatePfiPA2_fiiS_f:
.quad _Z21__device_stub__updatePfiPA2_fiiS_f
.size _Z6updatePfiPA2_fiiS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updatePfiPA2_fiiS_f"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updatePfiPA2_fiiS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6updatePfiPA2_fiiS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013cecf_00000000-6_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2046:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2046:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12get_particlePfi
.type _Z12get_particlePfi, @function
_Z12get_particlePfi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12get_particlePfi, .-_Z12get_particlePfi
.globl _Z8get_meanPfi
.type _Z8get_meanPfi, @function
_Z8get_meanPfi:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z8get_meanPfi, .-_Z8get_meanPfi
.globl _Z7get_covPfi
.type _Z7get_covPfi, @function
_Z7get_covPfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z7get_covPfi, .-_Z7get_covPfi
.globl _Z15get_n_landmarksPf
.type _Z15get_n_landmarksPf, @function
_Z15get_n_landmarksPf:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z15get_n_landmarksPf, .-_Z15get_n_landmarksPf
.globl _Z12add_landmarkPfS_S_
.type _Z12add_landmarkPfS_S_, @function
_Z12add_landmarkPfS_S_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z12add_landmarkPfS_S_, .-_Z12add_landmarkPfS_S_
.globl _Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements
.type _Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements, @function
_Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements, .-_Z40add_unassigned_measurements_as_landmarksPfPbP21landmark_measurements
.globl _Z29add_measurements_as_landmarksPfP21landmark_measurements
.type _Z29add_measurements_as_landmarksPfP21landmark_measurements, @function
_Z29add_measurements_as_landmarksPfP21landmark_measurements:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z29add_measurements_as_landmarksPfP21landmark_measurements, .-_Z29add_measurements_as_landmarksPfP21landmark_measurements
.globl _Z14insertion_sortPfPiS0_i
.type _Z14insertion_sortPfPiS0_i, @function
_Z14insertion_sortPfPiS0_i:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z14insertion_sortPfPiS0_i, .-_Z14insertion_sortPfPiS0_i
.globl _Z6vecmulPfS_S_
.type _Z6vecmulPfS_S_, @function
_Z6vecmulPfS_S_:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z6vecmulPfS_S_, .-_Z6vecmulPfS_S_
.globl _Z6matmulPfS_S_
.type _Z6matmulPfS_S_, @function
_Z6matmulPfS_S_:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z6matmulPfS_S_, .-_Z6matmulPfS_S_
.globl _Z4pinvPfS_
.type _Z4pinvPfS_, @function
_Z4pinvPfS_:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z4pinvPfS_, .-_Z4pinvPfS_
.globl _Z3pdfPfS_S_
.type _Z3pdfPfS_S_, @function
_Z3pdfPfS_S_:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Z3pdfPfS_S_, .-_Z3pdfPfS_S_
.globl _Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix
.type _Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix, @function
_Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix:
.LFB2039:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2039:
.size _Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix, .-_Z19compute_dist_matrixPfP21landmark_measurementsP11dist_matrix
.globl _Z6assignP11dist_matrixPiP10assignmentf
.type _Z6assignP11dist_matrixPiP10assignmentf, @function
_Z6assignP11dist_matrixPiP10assignmentf:
.LFB2040:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2040:
.size _Z6assignP11dist_matrixPiP10assignmentf, .-_Z6assignP11dist_matrixPiP10assignmentf
.globl _Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf
.type _Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf, @function
_Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf:
.LFB2041:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2041:
.size _Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf, .-_Z32associate_landmarks_measurementsPfS_PiP21landmark_measurementsiP10assignmentf
.globl _Z15update_landmarkPfP21landmark_measurementsP10assignment
.type _Z15update_landmarkPfP21landmark_measurementsP10assignment, @function
_Z15update_landmarkPfP21landmark_measurementsP10assignment:
.LFB2042:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2042:
.size _Z15update_landmarkPfP21landmark_measurementsP10assignment, .-_Z15update_landmarkPfP21landmark_measurementsP10assignment
.globl _Z26get_max_landmarks_in_blockPfiii
.type _Z26get_max_landmarks_in_blockPfiii, @function
_Z26get_max_landmarks_in_blockPfiii:
.LFB2043:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2043:
.size _Z26get_max_landmarks_in_blockPfiii, .-_Z26get_max_landmarks_in_blockPfiii
.globl _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f
.type _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f, @function
_Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f:
.LFB2068:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movss %xmm0, 16(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6updatePfiPA2_fiiS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f, .-_Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f
.globl _Z6updatePfiPA2_fiiS_f
.type _Z6updatePfiPA2_fiiS_f, @function
_Z6updatePfiPA2_fiiS_f:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6updatePfiPA2_fiiS_fPfiPA2_fiiS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _Z6updatePfiPA2_fiiS_f, .-_Z6updatePfiPA2_fiiS_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updatePfiPA2_fiiS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfiPA2_fiiS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update.hip"
.globl _Z21__device_stub__updatePfiPA2_fiiS_f # -- Begin function _Z21__device_stub__updatePfiPA2_fiiS_f
.p2align 4, 0x90
.type _Z21__device_stub__updatePfiPA2_fiiS_f,@function
_Z21__device_stub__updatePfiPA2_fiiS_f: # @_Z21__device_stub__updatePfiPA2_fiiS_f
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
movss %xmm0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6updatePfiPA2_fiiS_f, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__updatePfiPA2_fiiS_f, .Lfunc_end0-_Z21__device_stub__updatePfiPA2_fiiS_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfiPA2_fiiS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6updatePfiPA2_fiiS_f,@object # @_Z6updatePfiPA2_fiiS_f
.section .rodata,"a",@progbits
.globl _Z6updatePfiPA2_fiiS_f
.p2align 3, 0x0
_Z6updatePfiPA2_fiiS_f:
.quad _Z21__device_stub__updatePfiPA2_fiiS_f
.size _Z6updatePfiPA2_fiiS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updatePfiPA2_fiiS_f"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updatePfiPA2_fiiS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6updatePfiPA2_fiiS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#define NROWS 2048
#define NCOLS 1024
#define NUM_THREADS 32
// Matrix addition kernel
void __global__ matrixAdd(float *A, float *B, float *C, int numRows, int numCols)
{
unsigned int index;
// Some checks
if (blockIdx.y * blockDim.y + threadIdx.y >= numRows)
return;
if (blockIdx.x * blockDim.x + threadIdx.x >= numCols)
return;
index = (blockIdx.y * blockDim.y + threadIdx.y) * numCols +
blockIdx.x * blockDim.x + threadIdx.x;
C[index] = A[index] + B[index];
}
int main()
{
unsigned i, j;
// Check if matrix is large enough
if (NROWS < NUM_THREADS || NCOLS < NUM_THREADS)
{
printf("%d or %d < %d\n", NROWS, NCOLS, NUM_THREADS);
exit(0);
}
// Allocate memory on CPU
float *A, *B, *C;
A = (float *) malloc(NROWS * NCOLS * sizeof(float));
B = (float *) malloc(NROWS * NCOLS * sizeof(float));
C = (float *) malloc(NROWS * NCOLS * sizeof(float));
// Allocate memory on GPU
float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, NROWS * NCOLS * sizeof(float));
cudaMalloc((void **) &d_B, NROWS * NCOLS * sizeof(float));
cudaMalloc((void **) &d_C, NROWS * NCOLS * sizeof(float));
// Initliase data
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
A[i * NCOLS + j] = B[i * NCOLS + j] = j;
// Allocate CUDA event
cudaEvent_t event_start, event_stop;
float timestamp;
cudaEventCreate(&event_start);
cudaEventCreate(&event_stop);
// Copy data to GPU
cudaEventRecord(event_start, 0);
cudaMemcpy(d_A, A, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied data to GPU in: %lf ms\n", timestamp);
// Configure and launch kernel
cudaEventRecord(event_start, 0);
dim3 numThreads(NUM_THREADS, NUM_THREADS);
dim3 blockSize(ceil(NCOLS / ((float) NUM_THREADS)), ceil(NROWS / ((float) NUM_THREADS)));
printf("Num threads: %d, blocks: (%d, %d)\n", NUM_THREADS, blockSize.x, blockSize.y);
matrixAdd<<<blockSize, numThreads>>>(d_A, d_B, d_C, NROWS, NCOLS);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Performed matrix addition in: %lf ms\n", timestamp);
// Wait for kernel
cudaThreadSynchronize();
// Get result
cudaEventRecord(event_start, 0);
cudaMemcpy(C, d_C, NROWS * NCOLS * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied results from GPU in: %lf ms\n", timestamp);
// Check result
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
if (C[i * NCOLS + j] != A[i * NCOLS + j] + B[i * NCOLS + j])
{
printf("ERROR: %d %d (%f != %f)\n", i, j, A[i * NCOLS + j] + B[i * NCOLS + j], C[i * NCOLS + j]);
// exit(0);
}
printf("Success!\n");
} | code for sm_80
Function : _Z9matrixAddPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06070 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*00f0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*0130*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#define NROWS 2048
#define NCOLS 1024
#define NUM_THREADS 32
// Matrix addition kernel
void __global__ matrixAdd(float *A, float *B, float *C, int numRows, int numCols)
{
unsigned int index;
// Some checks
if (blockIdx.y * blockDim.y + threadIdx.y >= numRows)
return;
if (blockIdx.x * blockDim.x + threadIdx.x >= numCols)
return;
index = (blockIdx.y * blockDim.y + threadIdx.y) * numCols +
blockIdx.x * blockDim.x + threadIdx.x;
C[index] = A[index] + B[index];
}
int main()
{
unsigned i, j;
// Check if matrix is large enough
if (NROWS < NUM_THREADS || NCOLS < NUM_THREADS)
{
printf("%d or %d < %d\n", NROWS, NCOLS, NUM_THREADS);
exit(0);
}
// Allocate memory on CPU
float *A, *B, *C;
A = (float *) malloc(NROWS * NCOLS * sizeof(float));
B = (float *) malloc(NROWS * NCOLS * sizeof(float));
C = (float *) malloc(NROWS * NCOLS * sizeof(float));
// Allocate memory on GPU
float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, NROWS * NCOLS * sizeof(float));
cudaMalloc((void **) &d_B, NROWS * NCOLS * sizeof(float));
cudaMalloc((void **) &d_C, NROWS * NCOLS * sizeof(float));
// Initliase data
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
A[i * NCOLS + j] = B[i * NCOLS + j] = j;
// Allocate CUDA event
cudaEvent_t event_start, event_stop;
float timestamp;
cudaEventCreate(&event_start);
cudaEventCreate(&event_stop);
// Copy data to GPU
cudaEventRecord(event_start, 0);
cudaMemcpy(d_A, A, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied data to GPU in: %lf ms\n", timestamp);
// Configure and launch kernel
cudaEventRecord(event_start, 0);
dim3 numThreads(NUM_THREADS, NUM_THREADS);
dim3 blockSize(ceil(NCOLS / ((float) NUM_THREADS)), ceil(NROWS / ((float) NUM_THREADS)));
printf("Num threads: %d, blocks: (%d, %d)\n", NUM_THREADS, blockSize.x, blockSize.y);
matrixAdd<<<blockSize, numThreads>>>(d_A, d_B, d_C, NROWS, NCOLS);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Performed matrix addition in: %lf ms\n", timestamp);
// Wait for kernel
cudaThreadSynchronize();
// Get result
cudaEventRecord(event_start, 0);
cudaMemcpy(C, d_C, NROWS * NCOLS * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied results from GPU in: %lf ms\n", timestamp);
// Check result
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
if (C[i * NCOLS + j] != A[i * NCOLS + j] + B[i * NCOLS + j])
{
printf("ERROR: %d %d (%f != %f)\n", i, j, A[i * NCOLS + j] + B[i * NCOLS + j], C[i * NCOLS + j]);
// exit(0);
}
printf("Success!\n");
} | .file "tmpxft_00185435_00000000-6_matrixAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
.type _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii, @function
_Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii, .-_Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
.globl _Z9matrixAddPfS_S_ii
.type _Z9matrixAddPfS_S_ii, @function
_Z9matrixAddPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9matrixAddPfS_S_ii, .-_Z9matrixAddPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Copied data to GPU in: %lf ms\n"
.align 8
.LC1:
.string "Num threads: %d, blocks: (%d, %d)\n"
.align 8
.LC2:
.string "Performed matrix addition in: %lf ms\n"
.align 8
.LC3:
.string "Copied results from GPU in: %lf ms\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "ERROR: %d %d (%f != %f)\n"
.LC5:
.string "Success!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call malloc@PLT
movq %rax, %r14
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movq %rbx, %r13
movq %r14, %r12
leaq 8388608(%rbx), %rdi
movq %r14, %rsi
movq %rbx, %rcx
.L12:
movl $0, %eax
.L15:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, (%rcx,%rax,4)
movss %xmm0, (%rsi,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L15
addq $4096, %rcx
addq $4096, %rsi
cmpq %rdi, %rcx
jne .L12
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 68(%rsp)
movl $64, %r8d
movl $32, %ecx
movl $32, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, 60(%rsp)
movl $64, 64(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rbx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC4(%rip), %r15
jmp .L18
.L28:
movl $1024, %r8d
movl $2048, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
jmp .L17
.L24:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L19:
addq $1, %rbx
cmpq $1024, %rbx
je .L29
.L21:
movss 0(%rbp,%rbx,4), %xmm1
movss (%r12,%rbx,4), %xmm0
addss 0(%r13,%rbx,4), %xmm0
ucomiss %xmm0, %xmm1
jp .L24
je .L19
jmp .L24
.L29:
addl $1, %r14d
addq $4096, %rbp
addq $4096, %r12
addq $4096, %r13
cmpl $2048, %r14d
je .L22
.L18:
movl $0, %ebx
jmp .L21
.L22:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9matrixAddPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#define NROWS 2048
#define NCOLS 1024
#define NUM_THREADS 32
// Matrix addition kernel
void __global__ matrixAdd(float *A, float *B, float *C, int numRows, int numCols)
{
unsigned int index;
// Some checks
if (blockIdx.y * blockDim.y + threadIdx.y >= numRows)
return;
if (blockIdx.x * blockDim.x + threadIdx.x >= numCols)
return;
index = (blockIdx.y * blockDim.y + threadIdx.y) * numCols +
blockIdx.x * blockDim.x + threadIdx.x;
C[index] = A[index] + B[index];
}
int main()
{
unsigned i, j;
// Check if matrix is large enough
if (NROWS < NUM_THREADS || NCOLS < NUM_THREADS)
{
printf("%d or %d < %d\n", NROWS, NCOLS, NUM_THREADS);
exit(0);
}
// Allocate memory on CPU
float *A, *B, *C;
A = (float *) malloc(NROWS * NCOLS * sizeof(float));
B = (float *) malloc(NROWS * NCOLS * sizeof(float));
C = (float *) malloc(NROWS * NCOLS * sizeof(float));
// Allocate memory on GPU
float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, NROWS * NCOLS * sizeof(float));
cudaMalloc((void **) &d_B, NROWS * NCOLS * sizeof(float));
cudaMalloc((void **) &d_C, NROWS * NCOLS * sizeof(float));
// Initliase data
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
A[i * NCOLS + j] = B[i * NCOLS + j] = j;
// Allocate CUDA event
cudaEvent_t event_start, event_stop;
float timestamp;
cudaEventCreate(&event_start);
cudaEventCreate(&event_stop);
// Copy data to GPU
cudaEventRecord(event_start, 0);
cudaMemcpy(d_A, A, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, NROWS * NCOLS * sizeof(float), cudaMemcpyHostToDevice);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied data to GPU in: %lf ms\n", timestamp);
// Configure and launch kernel
cudaEventRecord(event_start, 0);
dim3 numThreads(NUM_THREADS, NUM_THREADS);
dim3 blockSize(ceil(NCOLS / ((float) NUM_THREADS)), ceil(NROWS / ((float) NUM_THREADS)));
printf("Num threads: %d, blocks: (%d, %d)\n", NUM_THREADS, blockSize.x, blockSize.y);
matrixAdd<<<blockSize, numThreads>>>(d_A, d_B, d_C, NROWS, NCOLS);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Performed matrix addition in: %lf ms\n", timestamp);
// Wait for kernel
cudaThreadSynchronize();
// Get result
cudaEventRecord(event_start, 0);
cudaMemcpy(C, d_C, NROWS * NCOLS * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(event_stop, 0);
cudaEventSynchronize(event_stop);
cudaEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied results from GPU in: %lf ms\n", timestamp);
// Check result
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
if (C[i * NCOLS + j] != A[i * NCOLS + j] + B[i * NCOLS + j])
{
printf("ERROR: %d %d (%f != %f)\n", i, j, A[i * NCOLS + j] + B[i * NCOLS + j], C[i * NCOLS + j]);
// exit(0);
}
printf("Success!\n");
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#define NROWS 2048
#define NCOLS 1024
#define NUM_THREADS 32
// Matrix addition kernel
void __global__ matrixAdd(float *A, float *B, float *C, int numRows, int numCols)
{
unsigned int index;
// Some checks
if (blockIdx.y * blockDim.y + threadIdx.y >= numRows)
return;
if (blockIdx.x * blockDim.x + threadIdx.x >= numCols)
return;
index = (blockIdx.y * blockDim.y + threadIdx.y) * numCols +
blockIdx.x * blockDim.x + threadIdx.x;
C[index] = A[index] + B[index];
}
int main()
{
unsigned i, j;
// Check if matrix is large enough
if (NROWS < NUM_THREADS || NCOLS < NUM_THREADS)
{
printf("%d or %d < %d\n", NROWS, NCOLS, NUM_THREADS);
exit(0);
}
// Allocate memory on CPU
float *A, *B, *C;
A = (float *) malloc(NROWS * NCOLS * sizeof(float));
B = (float *) malloc(NROWS * NCOLS * sizeof(float));
C = (float *) malloc(NROWS * NCOLS * sizeof(float));
// Allocate memory on GPU
float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, NROWS * NCOLS * sizeof(float));
hipMalloc((void **) &d_B, NROWS * NCOLS * sizeof(float));
hipMalloc((void **) &d_C, NROWS * NCOLS * sizeof(float));
// Initliase data
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
A[i * NCOLS + j] = B[i * NCOLS + j] = j;
// Allocate CUDA event
hipEvent_t event_start, event_stop;
float timestamp;
hipEventCreate(&event_start);
hipEventCreate(&event_stop);
// Copy data to GPU
hipEventRecord(event_start, 0);
hipMemcpy(d_A, A, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied data to GPU in: %lf ms\n", timestamp);
// Configure and launch kernel
hipEventRecord(event_start, 0);
dim3 numThreads(NUM_THREADS, NUM_THREADS);
dim3 blockSize(ceil(NCOLS / ((float) NUM_THREADS)), ceil(NROWS / ((float) NUM_THREADS)));
printf("Num threads: %d, blocks: (%d, %d)\n", NUM_THREADS, blockSize.x, blockSize.y);
matrixAdd<<<blockSize, numThreads>>>(d_A, d_B, d_C, NROWS, NCOLS);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Performed matrix addition in: %lf ms\n", timestamp);
// Wait for kernel
hipDeviceSynchronize();
// Get result
hipEventRecord(event_start, 0);
hipMemcpy(C, d_C, NROWS * NCOLS * sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied results from GPU in: %lf ms\n", timestamp);
// Check result
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
if (C[i * NCOLS + j] != A[i * NCOLS + j] + B[i * NCOLS + j])
{
printf("ERROR: %d %d (%f != %f)\n", i, j, A[i * NCOLS + j] + B[i * NCOLS + j], C[i * NCOLS + j]);
// exit(0);
}
printf("Success!\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#define NROWS 2048
#define NCOLS 1024
#define NUM_THREADS 32
// Matrix addition kernel
void __global__ matrixAdd(float *A, float *B, float *C, int numRows, int numCols)
{
unsigned int index;
// Some checks
if (blockIdx.y * blockDim.y + threadIdx.y >= numRows)
return;
if (blockIdx.x * blockDim.x + threadIdx.x >= numCols)
return;
index = (blockIdx.y * blockDim.y + threadIdx.y) * numCols +
blockIdx.x * blockDim.x + threadIdx.x;
C[index] = A[index] + B[index];
}
int main()
{
unsigned i, j;
// Check if matrix is large enough
if (NROWS < NUM_THREADS || NCOLS < NUM_THREADS)
{
printf("%d or %d < %d\n", NROWS, NCOLS, NUM_THREADS);
exit(0);
}
// Allocate memory on CPU
float *A, *B, *C;
A = (float *) malloc(NROWS * NCOLS * sizeof(float));
B = (float *) malloc(NROWS * NCOLS * sizeof(float));
C = (float *) malloc(NROWS * NCOLS * sizeof(float));
// Allocate memory on GPU
float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, NROWS * NCOLS * sizeof(float));
hipMalloc((void **) &d_B, NROWS * NCOLS * sizeof(float));
hipMalloc((void **) &d_C, NROWS * NCOLS * sizeof(float));
// Initliase data
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
A[i * NCOLS + j] = B[i * NCOLS + j] = j;
// Allocate CUDA event
hipEvent_t event_start, event_stop;
float timestamp;
hipEventCreate(&event_start);
hipEventCreate(&event_stop);
// Copy data to GPU
hipEventRecord(event_start, 0);
hipMemcpy(d_A, A, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied data to GPU in: %lf ms\n", timestamp);
// Configure and launch kernel
hipEventRecord(event_start, 0);
dim3 numThreads(NUM_THREADS, NUM_THREADS);
dim3 blockSize(ceil(NCOLS / ((float) NUM_THREADS)), ceil(NROWS / ((float) NUM_THREADS)));
printf("Num threads: %d, blocks: (%d, %d)\n", NUM_THREADS, blockSize.x, blockSize.y);
matrixAdd<<<blockSize, numThreads>>>(d_A, d_B, d_C, NROWS, NCOLS);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Performed matrix addition in: %lf ms\n", timestamp);
// Wait for kernel
hipDeviceSynchronize();
// Get result
hipEventRecord(event_start, 0);
hipMemcpy(C, d_C, NROWS * NCOLS * sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied results from GPU in: %lf ms\n", timestamp);
// Check result
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
if (C[i * NCOLS + j] != A[i * NCOLS + j] + B[i * NCOLS + j])
{
printf("ERROR: %d %d (%f != %f)\n", i, j, A[i * NCOLS + j] + B[i * NCOLS + j], C[i * NCOLS + j]);
// exit(0);
}
printf("Success!\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPfS_S_ii
.globl _Z9matrixAddPfS_S_ii
.p2align 8
.type _Z9matrixAddPfS_S_ii,@function
_Z9matrixAddPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[2:3], 0xc
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s14, s14, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s14, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v2, v0, s14
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPfS_S_ii, .Lfunc_end0-_Z9matrixAddPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#define NROWS 2048
#define NCOLS 1024
#define NUM_THREADS 32
// Matrix addition kernel
void __global__ matrixAdd(float *A, float *B, float *C, int numRows, int numCols)
{
unsigned int index;
// Some checks
if (blockIdx.y * blockDim.y + threadIdx.y >= numRows)
return;
if (blockIdx.x * blockDim.x + threadIdx.x >= numCols)
return;
index = (blockIdx.y * blockDim.y + threadIdx.y) * numCols +
blockIdx.x * blockDim.x + threadIdx.x;
C[index] = A[index] + B[index];
}
int main()
{
unsigned i, j;
// Check if matrix is large enough
if (NROWS < NUM_THREADS || NCOLS < NUM_THREADS)
{
printf("%d or %d < %d\n", NROWS, NCOLS, NUM_THREADS);
exit(0);
}
// Allocate memory on CPU
float *A, *B, *C;
A = (float *) malloc(NROWS * NCOLS * sizeof(float));
B = (float *) malloc(NROWS * NCOLS * sizeof(float));
C = (float *) malloc(NROWS * NCOLS * sizeof(float));
// Allocate memory on GPU
float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, NROWS * NCOLS * sizeof(float));
hipMalloc((void **) &d_B, NROWS * NCOLS * sizeof(float));
hipMalloc((void **) &d_C, NROWS * NCOLS * sizeof(float));
// Initliase data
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
A[i * NCOLS + j] = B[i * NCOLS + j] = j;
// Allocate CUDA event
hipEvent_t event_start, event_stop;
float timestamp;
hipEventCreate(&event_start);
hipEventCreate(&event_stop);
// Copy data to GPU
hipEventRecord(event_start, 0);
hipMemcpy(d_A, A, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, NROWS * NCOLS * sizeof(float), hipMemcpyHostToDevice);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied data to GPU in: %lf ms\n", timestamp);
// Configure and launch kernel
hipEventRecord(event_start, 0);
dim3 numThreads(NUM_THREADS, NUM_THREADS);
dim3 blockSize(ceil(NCOLS / ((float) NUM_THREADS)), ceil(NROWS / ((float) NUM_THREADS)));
printf("Num threads: %d, blocks: (%d, %d)\n", NUM_THREADS, blockSize.x, blockSize.y);
matrixAdd<<<blockSize, numThreads>>>(d_A, d_B, d_C, NROWS, NCOLS);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Performed matrix addition in: %lf ms\n", timestamp);
// Wait for kernel
hipDeviceSynchronize();
// Get result
hipEventRecord(event_start, 0);
hipMemcpy(C, d_C, NROWS * NCOLS * sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(event_stop, 0);
hipEventSynchronize(event_stop);
hipEventElapsedTime(×tamp, event_start, event_stop);
printf("Copied results from GPU in: %lf ms\n", timestamp);
// Check result
for (i = 0; i < NROWS; i++)
for (j = 0; j < NCOLS; j++)
if (C[i * NCOLS + j] != A[i * NCOLS + j] + B[i * NCOLS + j])
{
printf("ERROR: %d %d (%f != %f)\n", i, j, A[i * NCOLS + j] + B[i * NCOLS + j], C[i * NCOLS + j]);
// exit(0);
}
printf("Success!\n");
} | .text
.file "matrixAddition.hip"
.globl _Z24__device_stub__matrixAddPfS_S_ii # -- Begin function _Z24__device_stub__matrixAddPfS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPfS_S_ii,@function
_Z24__device_stub__matrixAddPfS_S_ii: # @_Z24__device_stub__matrixAddPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPfS_S_ii, .Lfunc_end0-_Z24__device_stub__matrixAddPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader51
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, %edi
xorps %xmm0, %xmm0
cvtsi2ss %rdi, %xmm0
movss %xmm0, (%rdx,%rsi,4)
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.1, %edi
movl $32, %esi
movl $32, %edx
movl $64, %ecx
xorl %eax, %eax
callq printf
movabsq $274877906976, %rdi # imm = 0x4000000020
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2048, 36(%rsp) # imm = 0x800
movl $1024, 32(%rsp) # imm = 0x400
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9matrixAddPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_7 Depth=1
incq %r12
addq $4096, %r15 # imm = 0x1000
addq $4096, %rbx # imm = 0x1000
addq $4096, %r14 # imm = 0x1000
cmpq $2048, %r12 # imm = 0x800
je .LBB1_12
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_8 Depth=2
incq %r13
cmpq $1024, %r13 # imm = 0x400
je .LBB1_11
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%r13,4), %xmm0
ucomiss %xmm0, %xmm1
jne .LBB1_9
jnp .LBB1_10
.LBB1_9: # in Loop: Header=BB1_8 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %edi
movl %r12d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB1_10
.LBB1_12:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPfS_S_ii,@object # @_Z9matrixAddPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z9matrixAddPfS_S_ii
.p2align 3, 0x0
_Z9matrixAddPfS_S_ii:
.quad _Z24__device_stub__matrixAddPfS_S_ii
.size _Z9matrixAddPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Copied data to GPU in: %lf ms\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Num threads: %d, blocks: (%d, %d)\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Performed matrix addition in: %lf ms\n"
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Copied results from GPU in: %lf ms\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "ERROR: %d %d (%f != %f)\n"
.size .L.str.4, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPfS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixAddPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06070 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*00f0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*0130*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPfS_S_ii
.globl _Z9matrixAddPfS_S_ii
.p2align 8
.type _Z9matrixAddPfS_S_ii,@function
_Z9matrixAddPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[2:3], 0xc
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s14, s14, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s14, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v2, v0, s14
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPfS_S_ii, .Lfunc_end0-_Z9matrixAddPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00185435_00000000-6_matrixAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
.type _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii, @function
_Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii, .-_Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
.globl _Z9matrixAddPfS_S_ii
.type _Z9matrixAddPfS_S_ii, @function
_Z9matrixAddPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9matrixAddPfS_S_ii, .-_Z9matrixAddPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Copied data to GPU in: %lf ms\n"
.align 8
.LC1:
.string "Num threads: %d, blocks: (%d, %d)\n"
.align 8
.LC2:
.string "Performed matrix addition in: %lf ms\n"
.align 8
.LC3:
.string "Copied results from GPU in: %lf ms\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "ERROR: %d %d (%f != %f)\n"
.LC5:
.string "Success!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call malloc@PLT
movq %rax, %r14
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movq %rbx, %r13
movq %r14, %r12
leaq 8388608(%rbx), %rdi
movq %r14, %rsi
movq %rbx, %rcx
.L12:
movl $0, %eax
.L15:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, (%rcx,%rax,4)
movss %xmm0, (%rsi,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L15
addq $4096, %rcx
addq $4096, %rsi
cmpq %rdi, %rcx
jne .L12
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 68(%rsp)
movl $64, %r8d
movl $32, %ecx
movl $32, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, 60(%rsp)
movl $64, 64(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rbx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC4(%rip), %r15
jmp .L18
.L28:
movl $1024, %r8d
movl $2048, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z9matrixAddPfS_S_iiPfS_S_ii
jmp .L17
.L24:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L19:
addq $1, %rbx
cmpq $1024, %rbx
je .L29
.L21:
movss 0(%rbp,%rbx,4), %xmm1
movss (%r12,%rbx,4), %xmm0
addss 0(%r13,%rbx,4), %xmm0
ucomiss %xmm0, %xmm1
jp .L24
je .L19
jmp .L24
.L29:
addl $1, %r14d
addq $4096, %rbp
addq $4096, %r12
addq $4096, %r13
cmpl $2048, %r14d
je .L22
.L18:
movl $0, %ebx
jmp .L21
.L22:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9matrixAddPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAddition.hip"
.globl _Z24__device_stub__matrixAddPfS_S_ii # -- Begin function _Z24__device_stub__matrixAddPfS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPfS_S_ii,@function
_Z24__device_stub__matrixAddPfS_S_ii: # @_Z24__device_stub__matrixAddPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPfS_S_ii, .Lfunc_end0-_Z24__device_stub__matrixAddPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader51
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, %edi
xorps %xmm0, %xmm0
cvtsi2ss %rdi, %xmm0
movss %xmm0, (%rdx,%rsi,4)
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $.L.str.1, %edi
movl $32, %esi
movl $32, %edx
movl $64, %ecx
xorl %eax, %eax
callq printf
movabsq $274877906976, %rdi # imm = 0x4000000020
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2048, 36(%rsp) # imm = 0x800
movl $1024, 32(%rsp) # imm = 0x400
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9matrixAddPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_7 Depth=1
incq %r12
addq $4096, %r15 # imm = 0x1000
addq $4096, %rbx # imm = 0x1000
addq $4096, %r14 # imm = 0x1000
cmpq $2048, %r12 # imm = 0x800
je .LBB1_12
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_8 Depth=2
incq %r13
cmpq $1024, %r13 # imm = 0x400
je .LBB1_11
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%r13,4), %xmm0
ucomiss %xmm0, %xmm1
jne .LBB1_9
jnp .LBB1_10
.LBB1_9: # in Loop: Header=BB1_8 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %edi
movl %r12d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB1_10
.LBB1_12:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPfS_S_ii,@object # @_Z9matrixAddPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z9matrixAddPfS_S_ii
.p2align 3, 0x0
_Z9matrixAddPfS_S_ii:
.quad _Z24__device_stub__matrixAddPfS_S_ii
.size _Z9matrixAddPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Copied data to GPU in: %lf ms\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Num threads: %d, blocks: (%d, %d)\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Performed matrix addition in: %lf ms\n"
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Copied results from GPU in: %lf ms\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "ERROR: %d %d (%f != %f)\n"
.size .L.str.4, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPfS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void xMinDeltaIntegralFracKernel( const float *intData, float *tmpArray, const int nWindows, const int h, const int w, const float *xMin, const float *yMin, const float *yMax, const float *inData, const int inDataStrideRow) {
int id = BLOCK_SIZE * BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = id % w + 1; id /= w; // 1-indexed
const int x = id % h + 1; id /= h; // 1-indexed
const int & windowIdx = id;
if (windowIdx < nWindows and x <= h and y <= w) {
tmpArray += windowIdx * h * w;
const int rem = windowIdx % 4;
if (rem == 0) {
tmpArray[(x-1)*w + (y-1)] = 0;
} else {
const float xMinStretched = rem == 0 ? -h :
xMin[3*(windowIdx/4) + (rem > 0 ? (rem-1) : rem)];
// const float xMaxStretched = rem == 1 ? h :
// xMax[3*(windowIdx/4) + (rem > 1 ? (rem-1) : rem)];
const float yMinStretched = rem == 2 ? -w :
yMin[3*(windowIdx/4) + (rem > 2 ? (rem-1) : rem)];
const float yMaxStretched = rem == 3 ? w :
yMax[3*(windowIdx/4) + (rem > 3 ? (rem-1) : rem)];
const int xMinInt = (int)ceil(xMinStretched-1);
// const float xMinFrac = xMinInt-xMinStretched+1;
const int yMinInt = (int)ceil(yMinStretched-1);
const float yMinFrac = yMinInt-yMinStretched+1;
// const int xMaxInt = (int)floor(xMaxStretched);
// const float xMaxFrac = xMaxStretched-xMaxInt;
const int yMaxInt = (int)floor(yMaxStretched);
const float yMaxFrac = yMaxStretched-yMaxInt;
const float tlCorner = y+yMinInt < 1 or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMinInt-1))];
// const float blCorner = y+yMinInt < 1 or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMinInt-1))];
const float trCorner = y+yMaxInt >= w or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMaxInt ))];
// const float brCorner = y+yMaxInt >= w or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMaxInt ))];
float delta = 0;
delta += trCorner * (y+yMaxInt < 1 ? 1.0f : yMaxFrac);
delta += tlCorner * (y+yMinInt >= w ? 1.0f : yMinFrac);
delta +=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta +=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta *= (x+xMinInt >= 1 and x+xMinInt < h);
tmpArray[(x-1)*w + (y-1)] *= -delta;
}
}
} | code for sm_80
Function : _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x178] ; /* 0x00005e0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0030*/ IABS R11, c[0x0][0x174] ; /* 0x00005d00000b7a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0070*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe40000000800 */
/*0080*/ ULOP3.LUT UR4, UR7, UR4, URZ, 0xfc, !UPT ; /* 0x0000000407047292 */
/* 0x000fc8000f8efc3f */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*00a0*/ IMAD R5, R5, 0x10, R4 ; /* 0x0000001005057824 */
/* 0x001fce00078e0204 */
/*00b0*/ I2F.RP R4, R11 ; /* 0x0000000b00047306 */
/* 0x000e220000209400 */
/*00c0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fce0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002b0000021f000 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x002fe400078e00ff */
/*0100*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x004fc800078e0a03 */
/*0110*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0120*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fc60000000000 */
/*0130*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fc60007ffe0ff */
/*0160*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a00 */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0180*/ IMAD R2, R7, R2, R6 ; /* 0x0000000207027224 */
/* 0x000fca00078e0206 */
/*0190*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*01a0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*01b0*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*01e0*/ LOP3.LUT R2, R5, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0005027a12 */
/* 0x000fc800078e3cff */
/*01f0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0210*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0000 */
/*0230*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x001fe400078e0a03 */
/*0240*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0250*/ @!P1 LOP3.LUT R9, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff099a12 */
/* 0x000fe200078e33ff */
/*0260*/ IMAD R7, R0, R11, RZ ; /* 0x0000000b00077224 */
/* 0x000fc600078e02ff */
/*0270*/ IABS R0, R9 ; /* 0x0000000900007213 */
/* 0x000fe20000000000 */
/*0280*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0290*/ IMAD.HI.U32 R2, R2, R0, RZ ; /* 0x0000000002027227 */
/* 0x000fc800078e00ff */
/*02a0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*02b0*/ IMAD R0, R11, R3, R0 ; /* 0x000000030b007224 */
/* 0x000fca00078e0200 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fda0003f24070 */
/*02d0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R11 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a0b */
/*02e0*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25270 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fe40003f06070 */
/*0310*/ LOP3.LUT R0, R9, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0009007a12 */
/* 0x000fc800078e3cff */
/*0320*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*0330*/ IADD3 R0, -R9, RZ, RZ ; /* 0x000000ff09007210 */
/* 0x000fca0007ffe1ff */
/*0340*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD R5, R0, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x000fc800078e0205 */
/*0360*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0002 */
/*0370*/ @!P2 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0ba224 */
/* 0x000fe200078e0a0b */
/*0380*/ @!P1 LOP3.LUT R11, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff0b9a12 */
/* 0x000fc800078e33ff */
/*0390*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fe20003f06270 */
/*03a0*/ IMAD.MOV R4, RZ, RZ, -R11 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0a0b */
/*03b0*/ ISETP.GT.OR P0, PT, RZ, UR4, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda0008704670 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*03e0*/ SHF.R.S32.HI R0, RZ, 0x1f, R11 ; /* 0x0000001fff007819 */
/* 0x000fe2000001140b */
/*03f0*/ UIMAD UR4, UR7, UR4, URZ ; /* 0x00000004070472a4 */
/* 0x000fe2000f8e023f */
/*0400*/ IMAD R4, R4, c[0x0][0x174], R9 ; /* 0x00005d0004047a24 */
/* 0x000fe200078e0209 */
/*0410*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0420*/ LEA.HI R6, R0, R11, RZ, 0x2 ; /* 0x0000000b00067211 */
/* 0x000fe400078f10ff */
/*0430*/ IMAD R3, R4, c[0x0][0x178], R5 ; /* 0x00005e0004037a24 */
/* 0x000fe400078e0205 */
/*0440*/ IMAD R0, R11, UR4, RZ ; /* 0x000000040b007c24 */
/* 0x000fe2000f8e02ff */
/*0450*/ LOP3.LUT R2, R6, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc06027812 */
/* 0x000fc400078ec0ff */
/*0460*/ SHF.R.S32.HI R7, RZ, 0x1f, R3 ; /* 0x0000001fff077819 */
/* 0x000fe40000011403 */
/*0470*/ IADD3 R3, P0, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe20007f1e0ff */
/*0480*/ IMAD.IADD R11, R11, 0x1, -R2 ; /* 0x000000010b0b7824 */
/* 0x000fc600078e0a02 */
/*0490*/ LEA.HI.X.SX32 R0, R0, R7, 0x1, P0 ; /* 0x0000000700007211 */
/* 0x000fe400000f0eff */
/*04a0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*04b0*/ LEA R2, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003027a11 */
/* 0x000fc800078210ff */
/*04c0*/ LEA.HI.X R3, R3, c[0x0][0x16c], R0, 0x2, P1 ; /* 0x00005b0003037a11 */
/* 0x000fce00008f1400 */
/*04d0*/ @!P0 BRA 0xb10 ; /* 0x0000063000008947 */
/* 0x000fea0003800000 */
/*04e0*/ ISETP.NE.AND P1, PT, R11.reuse, 0x2, PT ; /* 0x000000020b00780c */
/* 0x040fe20003f25270 */
/*04f0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ; /* 0x00000004ff0e7424 */
/* 0x000fe200078e00ff */
/*0500*/ SHF.R.S32.HI R0, RZ, 0x2, R6 ; /* 0x00000002ff007819 */
/* 0x000fe40000011406 */
/*0510*/ ISETP.GT.OR P3, PT, R11.reuse, 0x2, !P1 ; /* 0x000000020b00780c */
/* 0x040fe40004f64670 */
/*0520*/ ISETP.NE.AND P2, PT, R11.reuse, 0x3, PT ; /* 0x000000030b00780c */
/* 0x040fe20003f45270 */
/*0530*/ IMAD R13, R0, 0x3, R11 ; /* 0x00000003000d7824 */
/* 0x000fe200078e020b */
/*0540*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f04270 */
/*0550*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fca0007ffe0ff */
/*0560*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R7 ; /* 0x000000ffff001224 */
/* 0x000fe400078e0007 */
/*0570*/ @!P3 IMAD.MOV R0, RZ, RZ, R13 ; /* 0x000000ffff00b224 */
/* 0x000fe400078e020d */
/*0580*/ @P2 IMAD.WIDE R8, R13, R14, c[0x0][0x190] ; /* 0x000064000d082625 */
/* 0x000fc800078e020e */
/*0590*/ @P1 IMAD.WIDE R10, R14.reuse, R0, c[0x0][0x188] ; /* 0x000062000e0a1625 */
/* 0x040fe200078e0200 */
/*05a0*/ @P2 LDG.E R12, [R8.64] ; /* 0x00000008080c2981 */
/* 0x0000a6000c1e1900 */
/*05b0*/ @!P0 IMAD.MOV R7, RZ, RZ, R13 ; /* 0x000000ffff078224 */
/* 0x000fe400078e020d */
/*05c0*/ @P1 LDG.E R13, [R10.64] ; /* 0x000000080a0d1981 */
/* 0x000e24000c1e1900 */
/*05d0*/ IMAD.WIDE R6, R14, R7, c[0x0][0x180] ; /* 0x000060000e067625 */
/* 0x000fcc00078e0207 */
/*05e0*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee2000c1e1900 */
/*05f0*/ @!P1 IMAD.MOV R16, RZ, RZ, -c[0x0][0x178] ; /* 0x80005e00ff109624 */
/* 0x000fe200078e02ff */
/*0600*/ IADD3 R17, R5, 0x1, RZ ; /* 0x0000000105117810 */
/* 0x000fe20007ffe0ff */
/*0610*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0620*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*0630*/ UIADD3 UR6, UR7, -0x1, URZ ; /* 0xffffffff07067890 */
/* 0x000fe4000fffe03f */
/*0640*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe4000fffe13f */
/*0650*/ UIADD3 UR5, UR7, 0x1, URZ ; /* 0x0000000107057890 */
/* 0x000fe2000fffe03f */
/*0660*/ @!P2 I2F R12, c[0x0][0x178] ; /* 0x00005e00000cab06 */
/* 0x000ff00000201400 */
/*0670*/ @!P1 I2F R13, R16 ; /* 0x00000010000d9306 */
/* 0x000e220000201400 */
/*0680*/ FADD R15, R6, -1 ; /* 0xbf800000060f7421 */
/* 0x008fce0000000000 */
/*0690*/ F2I.CEIL.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e62000020b100 */
/*06a0*/ FADD R8, R13, -1 ; /* 0xbf8000000d087421 */
/* 0x001fce0000000000 */
/*06b0*/ F2I.FLOOR.NTZ R0, R12 ; /* 0x0000000c00007305 */
/* 0x004e300000207100 */
/*06c0*/ F2I.CEIL.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000ea2000020b100 */
/*06d0*/ IADD3 R9, R4, 0x1, R15 ; /* 0x0000000104097810 */
/* 0x002fc80007ffe00f */
/*06e0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f06270 */
/*06f0*/ IADD3 R11, R17, R0, RZ ; /* 0x00000000110b7210 */
/* 0x001fc80007ffe0ff */
/*0700*/ ISETP.GE.OR P1, PT, R11, c[0x0][0x178], !P0 ; /* 0x00005e000b007a0c */
/* 0x000fe20004726670 */
/*0710*/ IMAD.IADD R10, R17, 0x1, R8 ; /* 0x00000001110a7824 */
/* 0x004fe400078e0208 */
/*0720*/ IMAD.IADD R6, R4, 0x1, R15 ; /* 0x0000000104067824 */
/* 0x000fc600078e020f */
/*0730*/ ISETP.LT.OR P0, PT, R10, 0x1, !P0 ; /* 0x000000010a00780c */
/* 0x000fce0004701670 */
/*0740*/ @!P1 IMNMX R7, R6, UR4, PT ; /* 0x0000000406079c17 */
/* 0x000fe4000b800200 */
/*0750*/ @!P1 IMNMX R4, R11, UR6, PT ; /* 0x000000060b049c17 */
/* 0x000fe4000b800200 */
/*0760*/ @!P1 IMNMX R7, RZ, R7, !PT ; /* 0x00000007ff079217 */
/* 0x000fe40007800200 */
/*0770*/ @!P1 IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff049217 */
/* 0x000fe20007800200 */
/*0780*/ @!P0 IMAD.IADD R5, R5, 0x1, R8 ; /* 0x0000000105058824 */
/* 0x000fc800078e0208 */
/*0790*/ @!P1 IMAD R15, R7, c[0x0][0x1a0], R4 ; /* 0x00006800070f9a24 */
/* 0x000fe200078e0204 */
/*07a0*/ @!P0 IMNMX R4, R6.reuse, UR4, PT ; /* 0x0000000406048c17 */
/* 0x040fe4000b800200 */
/*07b0*/ @!P0 IMNMX R5, R5, UR6, PT ; /* 0x0000000605058c17 */
/* 0x000fe4000b800200 */
/*07c0*/ IMNMX R18, R11, c[0x0][0x178], PT ; /* 0x00005e000b127a17 */
/* 0x000fe40003800200 */
/*07d0*/ IMNMX R17, R9, c[0x0][0x174], PT ; /* 0x00005d0009117a17 */
/* 0x000fe40003800200 */
/*07e0*/ @!P0 IMNMX R7, RZ, R4, !PT ; /* 0x00000004ff078217 */
/* 0x000fe40007800200 */
/*07f0*/ @!P0 IMNMX R16, RZ, R5, !PT ; /* 0x00000005ff108217 */
/* 0x000fe20007800200 */
/*0800*/ @!P1 IMAD.WIDE R4, R15, R14, c[0x0][0x198] ; /* 0x000066000f049625 */
/* 0x000fe200078e020e */
/*0810*/ IMNMX R6, R6, c[0x0][0x174], PT ; /* 0x00005d0006067a17 */
/* 0x000fc40003800200 */
/*0820*/ IMNMX R22, RZ, R18, !PT ; /* 0x00000012ff167217 */
/* 0x000fe40007800200 */
/*0830*/ IMNMX R15, RZ, R17, !PT ; /* 0x00000011ff0f7217 */
/* 0x000fe20007800200 */
/*0840*/ @!P0 IMAD R7, R7, c[0x0][0x1a0], R16 ; /* 0x0000680007078a24 */
/* 0x000fe200078e0210 */
/*0850*/ IMNMX R23, RZ, R6, !PT ; /* 0x00000006ff177217 */
/* 0x000fe20007800200 */
/*0860*/ @!P1 LDG.E R16, [R4.64] ; /* 0x0000000804109981 */
/* 0x0000a2000c1e1900 */
/*0870*/ IMNMX R6, R10, c[0x0][0x178], PT ; /* 0x00005e000a067a17 */
/* 0x000fe20003800200 */
/*0880*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe400078e00ff */
/*0890*/ IMAD R19, R15, UR5, R22 ; /* 0x000000050f137c24 */
/* 0x000fe4000f8e0216 */
/*08a0*/ @!P0 IMAD.WIDE R20, R7, R14, c[0x0][0x198] ; /* 0x0000660007148625 */
/* 0x000fc800078e020e */
/*08b0*/ IMAD R7, R23, UR5, R22 ; /* 0x0000000517077c24 */
/* 0x000fe2000f8e0216 */
/*08c0*/ IMNMX R22, RZ, R6, !PT ; /* 0x00000006ff167217 */
/* 0x000fe20007800200 */
/*08d0*/ IMAD.WIDE R18, R19, R14.reuse, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x080fe200078e020e */
/*08e0*/ @!P0 LDG.E R17, [R20.64] ; /* 0x0000000814118981 */
/* 0x0002e6000c1e1900 */
/*08f0*/ IMAD.WIDE R6, R7, R14, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe400078e020e */
/*0900*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000f24000c1e1900 */
/*0910*/ IMAD R5, R15, UR5, R22 ; /* 0x000000050f057c24 */
/* 0x001fc4000f8e0216 */
/*0920*/ IMAD R15, R23, UR5, R22 ; /* 0x00000005170f7c24 */
/* 0x000fe2000f8e0216 */
/*0930*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000162000c1e1900 */
/*0940*/ IMAD.WIDE R4, R5, R14, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc600078e020e */
/*0950*/ LDG.E R22, [R2.64] ; /* 0x0000000802167981 */
/* 0x000f62000c1e1900 */
/*0960*/ IMAD.WIDE R14, R15, R14, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc600078e020e */
/*0970*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f68000c1e1900 */
/*0980*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000f62000c1e1900 */
/*0990*/ I2F R21, R0 ; /* 0x0000000000157306 */
/* 0x002e700000201400 */
/*09a0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e220000201400 */
/*09b0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*09c0*/ FADD R21, -R21, R12 ; /* 0x0000000c15157221 */
/* 0x002fe20000000100 */
/*09d0*/ ISETP.GE.AND P2, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fc80003f46270 */
/*09e0*/ FSEL R21, R21, 1, P0 ; /* 0x3f80000015157808 */
/* 0x000fe20000000000 */
/*09f0*/ FADD R13, R8, -R13 ; /* 0x8000000d080d7221 */
/* 0x001fe20000000000 */
/*0a00*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x000fc60003f06270 */
/*0a10*/ FADD R7, R13, 1 ; /* 0x3f8000000d077421 */
/* 0x000fe20000000000 */
/*0a20*/ ISETP.GT.AND P0, PT, R9, RZ, !P0 ; /* 0x000000ff0900720c */
/* 0x000fc80004704270 */
/*0a30*/ FSEL R7, R7, 1, !P2 ; /* 0x3f80000007077808 */
/* 0x000fe40005000000 */
/*0a40*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */
/* 0x000fcc0004000000 */
/*0a50*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000e220000201000 */
/*0a60*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff101224 */
/* 0x000fc800078e00ff */
/*0a70*/ FFMA R16, R21, R16, RZ ; /* 0x0000001015107223 */
/* 0x004fc800000000ff */
/*0a80*/ FFMA R7, R7, R17, R16 ; /* 0x0000001107077223 */
/* 0x008fc80000000010 */
/*0a90*/ FADD R7, R7, R18 ; /* 0x0000001207077221 */
/* 0x010fc80000000000 */
/*0aa0*/ FADD R7, R7, -R6 ; /* 0x8000000607077221 */
/* 0x020fc80000000000 */
/*0ab0*/ FADD R7, R7, -R4 ; /* 0x8000000407077221 */
/* 0x000fc80000000000 */
/*0ac0*/ FADD R7, R7, R14 ; /* 0x0000000e07077221 */
/* 0x000fc80000000000 */
/*0ad0*/ FMUL R7, R7, R0 ; /* 0x0000000007077220 */
/* 0x001fc80000400000 */
/*0ae0*/ FFMA R7, -R7, R22, -RZ ; /* 0x0000001607077223 */
/* 0x000fca00000009ff */
/*0af0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101908 */
/*0b00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b10*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void xMinDeltaIntegralFracKernel( const float *intData, float *tmpArray, const int nWindows, const int h, const int w, const float *xMin, const float *yMin, const float *yMax, const float *inData, const int inDataStrideRow) {
int id = BLOCK_SIZE * BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = id % w + 1; id /= w; // 1-indexed
const int x = id % h + 1; id /= h; // 1-indexed
const int & windowIdx = id;
if (windowIdx < nWindows and x <= h and y <= w) {
tmpArray += windowIdx * h * w;
const int rem = windowIdx % 4;
if (rem == 0) {
tmpArray[(x-1)*w + (y-1)] = 0;
} else {
const float xMinStretched = rem == 0 ? -h :
xMin[3*(windowIdx/4) + (rem > 0 ? (rem-1) : rem)];
// const float xMaxStretched = rem == 1 ? h :
// xMax[3*(windowIdx/4) + (rem > 1 ? (rem-1) : rem)];
const float yMinStretched = rem == 2 ? -w :
yMin[3*(windowIdx/4) + (rem > 2 ? (rem-1) : rem)];
const float yMaxStretched = rem == 3 ? w :
yMax[3*(windowIdx/4) + (rem > 3 ? (rem-1) : rem)];
const int xMinInt = (int)ceil(xMinStretched-1);
// const float xMinFrac = xMinInt-xMinStretched+1;
const int yMinInt = (int)ceil(yMinStretched-1);
const float yMinFrac = yMinInt-yMinStretched+1;
// const int xMaxInt = (int)floor(xMaxStretched);
// const float xMaxFrac = xMaxStretched-xMaxInt;
const int yMaxInt = (int)floor(yMaxStretched);
const float yMaxFrac = yMaxStretched-yMaxInt;
const float tlCorner = y+yMinInt < 1 or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMinInt-1))];
// const float blCorner = y+yMinInt < 1 or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMinInt-1))];
const float trCorner = y+yMaxInt >= w or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMaxInt ))];
// const float brCorner = y+yMaxInt >= w or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMaxInt ))];
float delta = 0;
delta += trCorner * (y+yMaxInt < 1 ? 1.0f : yMaxFrac);
delta += tlCorner * (y+yMinInt >= w ? 1.0f : yMinFrac);
delta +=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta +=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta *= (x+xMinInt >= 1 and x+xMinInt < h);
tmpArray[(x-1)*w + (y-1)] *= -delta;
}
}
} | .file "tmpxft_000f169f_00000000-6_xMinDeltaIntegralFracKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i
.type _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i, @function
_Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq 256(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i, .-_Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i
.globl _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.type _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, @function
_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, .-_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void xMinDeltaIntegralFracKernel( const float *intData, float *tmpArray, const int nWindows, const int h, const int w, const float *xMin, const float *yMin, const float *yMax, const float *inData, const int inDataStrideRow) {
int id = BLOCK_SIZE * BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = id % w + 1; id /= w; // 1-indexed
const int x = id % h + 1; id /= h; // 1-indexed
const int & windowIdx = id;
if (windowIdx < nWindows and x <= h and y <= w) {
tmpArray += windowIdx * h * w;
const int rem = windowIdx % 4;
if (rem == 0) {
tmpArray[(x-1)*w + (y-1)] = 0;
} else {
const float xMinStretched = rem == 0 ? -h :
xMin[3*(windowIdx/4) + (rem > 0 ? (rem-1) : rem)];
// const float xMaxStretched = rem == 1 ? h :
// xMax[3*(windowIdx/4) + (rem > 1 ? (rem-1) : rem)];
const float yMinStretched = rem == 2 ? -w :
yMin[3*(windowIdx/4) + (rem > 2 ? (rem-1) : rem)];
const float yMaxStretched = rem == 3 ? w :
yMax[3*(windowIdx/4) + (rem > 3 ? (rem-1) : rem)];
const int xMinInt = (int)ceil(xMinStretched-1);
// const float xMinFrac = xMinInt-xMinStretched+1;
const int yMinInt = (int)ceil(yMinStretched-1);
const float yMinFrac = yMinInt-yMinStretched+1;
// const int xMaxInt = (int)floor(xMaxStretched);
// const float xMaxFrac = xMaxStretched-xMaxInt;
const int yMaxInt = (int)floor(yMaxStretched);
const float yMaxFrac = yMaxStretched-yMaxInt;
const float tlCorner = y+yMinInt < 1 or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMinInt-1))];
// const float blCorner = y+yMinInt < 1 or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMinInt-1))];
const float trCorner = y+yMaxInt >= w or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMaxInt ))];
// const float brCorner = y+yMaxInt >= w or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMaxInt ))];
float delta = 0;
delta += trCorner * (y+yMaxInt < 1 ? 1.0f : yMaxFrac);
delta += tlCorner * (y+yMinInt >= w ? 1.0f : yMinFrac);
delta +=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta +=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta *= (x+xMinInt >= 1 and x+xMinInt < h);
tmpArray[(x-1)*w + (y-1)] *= -delta;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void xMinDeltaIntegralFracKernel( const float *intData, float *tmpArray, const int nWindows, const int h, const int w, const float *xMin, const float *yMin, const float *yMax, const float *inData, const int inDataStrideRow) {
int id = BLOCK_SIZE * BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = id % w + 1; id /= w; // 1-indexed
const int x = id % h + 1; id /= h; // 1-indexed
const int & windowIdx = id;
if (windowIdx < nWindows and x <= h and y <= w) {
tmpArray += windowIdx * h * w;
const int rem = windowIdx % 4;
if (rem == 0) {
tmpArray[(x-1)*w + (y-1)] = 0;
} else {
const float xMinStretched = rem == 0 ? -h :
xMin[3*(windowIdx/4) + (rem > 0 ? (rem-1) : rem)];
// const float xMaxStretched = rem == 1 ? h :
// xMax[3*(windowIdx/4) + (rem > 1 ? (rem-1) : rem)];
const float yMinStretched = rem == 2 ? -w :
yMin[3*(windowIdx/4) + (rem > 2 ? (rem-1) : rem)];
const float yMaxStretched = rem == 3 ? w :
yMax[3*(windowIdx/4) + (rem > 3 ? (rem-1) : rem)];
const int xMinInt = (int)ceil(xMinStretched-1);
// const float xMinFrac = xMinInt-xMinStretched+1;
const int yMinInt = (int)ceil(yMinStretched-1);
const float yMinFrac = yMinInt-yMinStretched+1;
// const int xMaxInt = (int)floor(xMaxStretched);
// const float xMaxFrac = xMaxStretched-xMaxInt;
const int yMaxInt = (int)floor(yMaxStretched);
const float yMaxFrac = yMaxStretched-yMaxInt;
const float tlCorner = y+yMinInt < 1 or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMinInt-1))];
// const float blCorner = y+yMinInt < 1 or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMinInt-1))];
const float trCorner = y+yMaxInt >= w or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMaxInt ))];
// const float brCorner = y+yMaxInt >= w or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMaxInt ))];
float delta = 0;
delta += trCorner * (y+yMaxInt < 1 ? 1.0f : yMaxFrac);
delta += tlCorner * (y+yMinInt >= w ? 1.0f : yMinFrac);
delta +=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta +=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta *= (x+xMinInt >= 1 and x+xMinInt < h);
tmpArray[(x-1)*w + (y-1)] *= -delta;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void xMinDeltaIntegralFracKernel( const float *intData, float *tmpArray, const int nWindows, const int h, const int w, const float *xMin, const float *yMin, const float *yMax, const float *inData, const int inDataStrideRow) {
int id = BLOCK_SIZE * BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = id % w + 1; id /= w; // 1-indexed
const int x = id % h + 1; id /= h; // 1-indexed
const int & windowIdx = id;
if (windowIdx < nWindows and x <= h and y <= w) {
tmpArray += windowIdx * h * w;
const int rem = windowIdx % 4;
if (rem == 0) {
tmpArray[(x-1)*w + (y-1)] = 0;
} else {
const float xMinStretched = rem == 0 ? -h :
xMin[3*(windowIdx/4) + (rem > 0 ? (rem-1) : rem)];
// const float xMaxStretched = rem == 1 ? h :
// xMax[3*(windowIdx/4) + (rem > 1 ? (rem-1) : rem)];
const float yMinStretched = rem == 2 ? -w :
yMin[3*(windowIdx/4) + (rem > 2 ? (rem-1) : rem)];
const float yMaxStretched = rem == 3 ? w :
yMax[3*(windowIdx/4) + (rem > 3 ? (rem-1) : rem)];
const int xMinInt = (int)ceil(xMinStretched-1);
// const float xMinFrac = xMinInt-xMinStretched+1;
const int yMinInt = (int)ceil(yMinStretched-1);
const float yMinFrac = yMinInt-yMinStretched+1;
// const int xMaxInt = (int)floor(xMaxStretched);
// const float xMaxFrac = xMaxStretched-xMaxInt;
const int yMaxInt = (int)floor(yMaxStretched);
const float yMaxFrac = yMaxStretched-yMaxInt;
const float tlCorner = y+yMinInt < 1 or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMinInt-1))];
// const float blCorner = y+yMinInt < 1 or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMinInt-1))];
const float trCorner = y+yMaxInt >= w or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMaxInt ))];
// const float brCorner = y+yMaxInt >= w or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMaxInt ))];
float delta = 0;
delta += trCorner * (y+yMaxInt < 1 ? 1.0f : yMaxFrac);
delta += tlCorner * (y+yMinInt >= w ? 1.0f : yMinFrac);
delta +=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta +=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta *= (x+xMinInt >= 1 and x+xMinInt < h);
tmpArray[(x-1)*w + (y-1)] *= -delta;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.globl _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.p2align 8
.type _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i,@function
_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i:
s_load_b32 s6, s[0:1], 0x18
v_lshl_add_u32 v0, s15, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v0
v_add_nc_u32_e32 v4, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s6, 31
s_add_i32 s2, s6, s4
v_xor_b32_e32 v3, s4, v3
s_xor_b32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s2, 0, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s2, v1
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s3, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_hi_u32 v1, v4, v1
s_add_i32 s8, s3, s7
s_xor_b32 s8, s8, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v5, s8
s_sub_i32 s4, 0, s8
v_mul_lo_u32 v2, v1, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_subrev_nc_u32_e32 v6, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v6
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cvt_u32_f32_e32 v2, v5
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, s4, v2
s_or_b32 s4, s6, s3
s_cmp_gt_i32 s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v1, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v5, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v5, v3
v_xor_b32_e32 v3, s7, v3
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s8
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s8, v4
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v2
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_cselect_b32 s2, -1, 0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_17
v_ashrrev_i32_e32 v4, 31, v2
s_mul_i32 s2, s6, s3
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v3, s2, v2
v_mul_lo_u32 v5, v1, s6
v_lshrrev_b32_e32 v4, 30, v4
v_mul_lo_u32 v7, v2, s3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v2, v4
v_ashrrev_i32_e32 v4, 31, v3
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v5, v1, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v8, -4, v6
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmpx_ne_u32_e32 0, v2
s_xor_b32 s7, exec_lo, s2
s_cbranch_execz .LBB0_15
v_ashrrev_i32_e32 v1, 2, v6
v_cmp_lt_i32_e32 vcc_lo, 0, v2
s_load_b64 s[4:5], s[0:1], 0x20
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 1, v1
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v1, vcc_lo
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v7, v[6:7], off
v_cmpx_ne_u32_e32 2, v2
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_cmp_lt_i32_e32 vcc_lo, 2, v2
s_load_b64 s[4:5], s[0:1], 0x28
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v6, v[8:9], off
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_6
s_sub_i32 s4, 0, s6
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v6, s4
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_ne_u32_e32 vcc_lo, 3, v2
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_8:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_10
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, s6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, -1.0, v7
v_add_f32_e32 v7, -1.0, v6
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x38
s_load_b32 s8, s[0:1], 0x40
v_add_nc_u32_e32 v11, 1, v0
v_mov_b32_e32 v9, 0
v_ceil_f32_e32 v1, v1
v_ceil_f32_e32 v7, v7
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v10, v1
v_cvt_i32_f32_e32 v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v1, v5, v10, 1
v_add_nc_u32_e32 v7, v11, v8
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
v_min_i32_e32 v12, v7, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v12
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v10, v0, v8
s_add_i32 s2, s3, -1
s_add_i32 s10, s6, -1
v_minmax_i32 v12, s2, v13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_minmax_i32 v10, s10, v10, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[14:15], null, v12, s8, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s2, s4, v14
v_add_co_ci_u32_e64 v15, s2, s5, v15, s2
global_load_b32 v10, v[14:15], off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s9
v_floor_f32_e32 v12, v2
s_xor_b32 s9, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v12, v12
v_add_nc_u32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v11
s_and_b32 s9, s2, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_14
s_add_i32 s9, s3, -1
s_add_i32 s10, s6, -1
v_minmax_i32 v16, s9, v13, 0
v_minmax_i32 v9, s10, v11, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, v16, s8, v[9:10]
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_add_co_u32 v14, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
global_load_b32 v9, v[14:15], off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
v_minmax_i32 v14, v1, s3, 0
v_minmax_i32 v13, v13, s3, 0
s_load_b64 s[0:1], s[0:1], 0x0
v_minmax_i32 v20, v7, s6, 0
v_cvt_f32_i32_e32 v12, v12
v_mad_u64_u32 v[15:16], null, v14, s6, v[14:15]
v_minmax_i32 v14, v11, s6, 0
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v2, v2, v12
v_mad_u64_u32 v[16:17], null, v13, s6, v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_dual_sub_f32 v6, v8, v6 :: v_dual_add_nc_u32 v13, v14, v15
v_add_nc_u32_e32 v15, v20, v15
v_mad_u64_u32 v[17:18], null, v5, s6, v[0:1]
v_add_nc_u32_e32 v19, v14, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v14, 31, v13
v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_nc_u32 v21, v20, v16
v_ashrrev_i32_e32 v16, 31, v15
v_ashrrev_i32_e32 v20, 31, v19
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_ashrrev_i32_e32 v22, 31, v21
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_lshlrev_b64 v[19:20], 2, v[19:20]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v19, vcc_lo, s0, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v20, vcc_lo
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_clause 0x1
global_load_b32 v0, v[13:14], off
global_load_b32 v5, v[19:20], off
v_add_co_u32 v13, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s0, v21
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v22, vcc_lo
global_load_b32 v19, v[13:14], off
v_cmp_gt_i32_e64 s0, s3, v1
global_load_b32 v15, v[15:16], off
v_lshlrev_b64 v[13:14], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v13
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v14, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v11
global_load_b32 v13, v[3:4], off
v_cndmask_b32_e32 v2, 1.0, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s6, v7
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, v9, 0
v_cndmask_b32_e32 v6, 1.0, v6, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_fmac_f32_e32 v2, v6, v10
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, 1.0, s0
s_waitcnt vmcnt(4)
v_add_f32_e32 v0, v0, v2
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v5
s_waitcnt vmcnt(2)
v_sub_f32_e32 v0, v0, v19
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v15, v0
v_mul_f32_e64 v0, v1, -v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v0, v13, v0
global_store_b32 v[3:4], v0, off
.LBB0_15:
s_and_not1_saveexec_b32 s0, s7
s_cbranch_execz .LBB0_17
v_mad_u64_u32 v[1:2], null, v5, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v3, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 68
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, .Lfunc_end0-_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 68
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void xMinDeltaIntegralFracKernel( const float *intData, float *tmpArray, const int nWindows, const int h, const int w, const float *xMin, const float *yMin, const float *yMax, const float *inData, const int inDataStrideRow) {
int id = BLOCK_SIZE * BLOCK_SIZE * blockIdx.x + threadIdx.x;
const int y = id % w + 1; id /= w; // 1-indexed
const int x = id % h + 1; id /= h; // 1-indexed
const int & windowIdx = id;
if (windowIdx < nWindows and x <= h and y <= w) {
tmpArray += windowIdx * h * w;
const int rem = windowIdx % 4;
if (rem == 0) {
tmpArray[(x-1)*w + (y-1)] = 0;
} else {
const float xMinStretched = rem == 0 ? -h :
xMin[3*(windowIdx/4) + (rem > 0 ? (rem-1) : rem)];
// const float xMaxStretched = rem == 1 ? h :
// xMax[3*(windowIdx/4) + (rem > 1 ? (rem-1) : rem)];
const float yMinStretched = rem == 2 ? -w :
yMin[3*(windowIdx/4) + (rem > 2 ? (rem-1) : rem)];
const float yMaxStretched = rem == 3 ? w :
yMax[3*(windowIdx/4) + (rem > 3 ? (rem-1) : rem)];
const int xMinInt = (int)ceil(xMinStretched-1);
// const float xMinFrac = xMinInt-xMinStretched+1;
const int yMinInt = (int)ceil(yMinStretched-1);
const float yMinFrac = yMinInt-yMinStretched+1;
// const int xMaxInt = (int)floor(xMaxStretched);
// const float xMaxFrac = xMaxStretched-xMaxInt;
const int yMaxInt = (int)floor(yMaxStretched);
const float yMaxFrac = yMaxStretched-yMaxInt;
const float tlCorner = y+yMinInt < 1 or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMinInt-1))];
// const float blCorner = y+yMinInt < 1 or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMinInt-1))];
const float trCorner = y+yMaxInt >= w or x+xMinInt < 1 ? 0 :
inData[
max(0,min(h-1,x+xMinInt-1)) * inDataStrideRow +
max(0,min(w-1,y+yMaxInt ))];
// const float brCorner = y+yMaxInt >= w or x+xMaxInt >= h ? 0 :
// inData[
// max(0,min(h-1,x+xMaxInt )) * inDataStrideRow +
// max(0,min(w-1,y+yMaxInt ))];
float delta = 0;
delta += trCorner * (y+yMaxInt < 1 ? 1.0f : yMaxFrac);
delta += tlCorner * (y+yMinInt >= w ? 1.0f : yMinFrac);
delta +=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMaxInt, w))];
delta -=
intData[max(0,min(x+xMinInt , h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta +=
intData[max(0,min(x+xMinInt-1, h))*(w+1)
+ max(0,min(y+yMinInt, w))];
delta *= (x+xMinInt >= 1 and x+xMinInt < h);
tmpArray[(x-1)*w + (y-1)] *= -delta;
}
}
} | .text
.file "xMinDeltaIntegralFracKernel.hip"
.globl _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i # -- Begin function _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.p2align 4, 0x90
.type _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i,@function
_Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i: # @_Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, .Lfunc_end0-_Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i,@object # @_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.section .rodata,"a",@progbits
.globl _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.p2align 3, 0x0
_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i:
.quad _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.size _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x178] ; /* 0x00005e0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0030*/ IABS R11, c[0x0][0x174] ; /* 0x00005d00000b7a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0070*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe40000000800 */
/*0080*/ ULOP3.LUT UR4, UR7, UR4, URZ, 0xfc, !UPT ; /* 0x0000000407047292 */
/* 0x000fc8000f8efc3f */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*00a0*/ IMAD R5, R5, 0x10, R4 ; /* 0x0000001005057824 */
/* 0x001fce00078e0204 */
/*00b0*/ I2F.RP R4, R11 ; /* 0x0000000b00047306 */
/* 0x000e220000209400 */
/*00c0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fce0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002b0000021f000 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x002fe400078e00ff */
/*0100*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x004fc800078e0a03 */
/*0110*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0120*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fc60000000000 */
/*0130*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fc60007ffe0ff */
/*0160*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a00 */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0180*/ IMAD R2, R7, R2, R6 ; /* 0x0000000207027224 */
/* 0x000fca00078e0206 */
/*0190*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*01a0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*01b0*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*01e0*/ LOP3.LUT R2, R5, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0005027a12 */
/* 0x000fc800078e3cff */
/*01f0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0210*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0000 */
/*0230*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x001fe400078e0a03 */
/*0240*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0250*/ @!P1 LOP3.LUT R9, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff099a12 */
/* 0x000fe200078e33ff */
/*0260*/ IMAD R7, R0, R11, RZ ; /* 0x0000000b00077224 */
/* 0x000fc600078e02ff */
/*0270*/ IABS R0, R9 ; /* 0x0000000900007213 */
/* 0x000fe20000000000 */
/*0280*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fcc00078e0002 */
/*0290*/ IMAD.HI.U32 R2, R2, R0, RZ ; /* 0x0000000002027227 */
/* 0x000fc800078e00ff */
/*02a0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*02b0*/ IMAD R0, R11, R3, R0 ; /* 0x000000030b007224 */
/* 0x000fca00078e0200 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fda0003f24070 */
/*02d0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R11 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a0b */
/*02e0*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25270 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fe40003f06070 */
/*0310*/ LOP3.LUT R0, R9, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0009007a12 */
/* 0x000fc800078e3cff */
/*0320*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*0330*/ IADD3 R0, -R9, RZ, RZ ; /* 0x000000ff09007210 */
/* 0x000fca0007ffe1ff */
/*0340*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD R5, R0, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x000fc800078e0205 */
/*0360*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0002 */
/*0370*/ @!P2 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0ba224 */
/* 0x000fe200078e0a0b */
/*0380*/ @!P1 LOP3.LUT R11, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff0b9a12 */
/* 0x000fc800078e33ff */
/*0390*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fe20003f06270 */
/*03a0*/ IMAD.MOV R4, RZ, RZ, -R11 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0a0b */
/*03b0*/ ISETP.GT.OR P0, PT, RZ, UR4, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda0008704670 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*03e0*/ SHF.R.S32.HI R0, RZ, 0x1f, R11 ; /* 0x0000001fff007819 */
/* 0x000fe2000001140b */
/*03f0*/ UIMAD UR4, UR7, UR4, URZ ; /* 0x00000004070472a4 */
/* 0x000fe2000f8e023f */
/*0400*/ IMAD R4, R4, c[0x0][0x174], R9 ; /* 0x00005d0004047a24 */
/* 0x000fe200078e0209 */
/*0410*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0420*/ LEA.HI R6, R0, R11, RZ, 0x2 ; /* 0x0000000b00067211 */
/* 0x000fe400078f10ff */
/*0430*/ IMAD R3, R4, c[0x0][0x178], R5 ; /* 0x00005e0004037a24 */
/* 0x000fe400078e0205 */
/*0440*/ IMAD R0, R11, UR4, RZ ; /* 0x000000040b007c24 */
/* 0x000fe2000f8e02ff */
/*0450*/ LOP3.LUT R2, R6, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc06027812 */
/* 0x000fc400078ec0ff */
/*0460*/ SHF.R.S32.HI R7, RZ, 0x1f, R3 ; /* 0x0000001fff077819 */
/* 0x000fe40000011403 */
/*0470*/ IADD3 R3, P0, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe20007f1e0ff */
/*0480*/ IMAD.IADD R11, R11, 0x1, -R2 ; /* 0x000000010b0b7824 */
/* 0x000fc600078e0a02 */
/*0490*/ LEA.HI.X.SX32 R0, R0, R7, 0x1, P0 ; /* 0x0000000700007211 */
/* 0x000fe400000f0eff */
/*04a0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*04b0*/ LEA R2, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003027a11 */
/* 0x000fc800078210ff */
/*04c0*/ LEA.HI.X R3, R3, c[0x0][0x16c], R0, 0x2, P1 ; /* 0x00005b0003037a11 */
/* 0x000fce00008f1400 */
/*04d0*/ @!P0 BRA 0xb10 ; /* 0x0000063000008947 */
/* 0x000fea0003800000 */
/*04e0*/ ISETP.NE.AND P1, PT, R11.reuse, 0x2, PT ; /* 0x000000020b00780c */
/* 0x040fe20003f25270 */
/*04f0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ; /* 0x00000004ff0e7424 */
/* 0x000fe200078e00ff */
/*0500*/ SHF.R.S32.HI R0, RZ, 0x2, R6 ; /* 0x00000002ff007819 */
/* 0x000fe40000011406 */
/*0510*/ ISETP.GT.OR P3, PT, R11.reuse, 0x2, !P1 ; /* 0x000000020b00780c */
/* 0x040fe40004f64670 */
/*0520*/ ISETP.NE.AND P2, PT, R11.reuse, 0x3, PT ; /* 0x000000030b00780c */
/* 0x040fe20003f45270 */
/*0530*/ IMAD R13, R0, 0x3, R11 ; /* 0x00000003000d7824 */
/* 0x000fe200078e020b */
/*0540*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f04270 */
/*0550*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fca0007ffe0ff */
/*0560*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R7 ; /* 0x000000ffff001224 */
/* 0x000fe400078e0007 */
/*0570*/ @!P3 IMAD.MOV R0, RZ, RZ, R13 ; /* 0x000000ffff00b224 */
/* 0x000fe400078e020d */
/*0580*/ @P2 IMAD.WIDE R8, R13, R14, c[0x0][0x190] ; /* 0x000064000d082625 */
/* 0x000fc800078e020e */
/*0590*/ @P1 IMAD.WIDE R10, R14.reuse, R0, c[0x0][0x188] ; /* 0x000062000e0a1625 */
/* 0x040fe200078e0200 */
/*05a0*/ @P2 LDG.E R12, [R8.64] ; /* 0x00000008080c2981 */
/* 0x0000a6000c1e1900 */
/*05b0*/ @!P0 IMAD.MOV R7, RZ, RZ, R13 ; /* 0x000000ffff078224 */
/* 0x000fe400078e020d */
/*05c0*/ @P1 LDG.E R13, [R10.64] ; /* 0x000000080a0d1981 */
/* 0x000e24000c1e1900 */
/*05d0*/ IMAD.WIDE R6, R14, R7, c[0x0][0x180] ; /* 0x000060000e067625 */
/* 0x000fcc00078e0207 */
/*05e0*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee2000c1e1900 */
/*05f0*/ @!P1 IMAD.MOV R16, RZ, RZ, -c[0x0][0x178] ; /* 0x80005e00ff109624 */
/* 0x000fe200078e02ff */
/*0600*/ IADD3 R17, R5, 0x1, RZ ; /* 0x0000000105117810 */
/* 0x000fe20007ffe0ff */
/*0610*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0620*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*0630*/ UIADD3 UR6, UR7, -0x1, URZ ; /* 0xffffffff07067890 */
/* 0x000fe4000fffe03f */
/*0640*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe4000fffe13f */
/*0650*/ UIADD3 UR5, UR7, 0x1, URZ ; /* 0x0000000107057890 */
/* 0x000fe2000fffe03f */
/*0660*/ @!P2 I2F R12, c[0x0][0x178] ; /* 0x00005e00000cab06 */
/* 0x000ff00000201400 */
/*0670*/ @!P1 I2F R13, R16 ; /* 0x00000010000d9306 */
/* 0x000e220000201400 */
/*0680*/ FADD R15, R6, -1 ; /* 0xbf800000060f7421 */
/* 0x008fce0000000000 */
/*0690*/ F2I.CEIL.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e62000020b100 */
/*06a0*/ FADD R8, R13, -1 ; /* 0xbf8000000d087421 */
/* 0x001fce0000000000 */
/*06b0*/ F2I.FLOOR.NTZ R0, R12 ; /* 0x0000000c00007305 */
/* 0x004e300000207100 */
/*06c0*/ F2I.CEIL.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000ea2000020b100 */
/*06d0*/ IADD3 R9, R4, 0x1, R15 ; /* 0x0000000104097810 */
/* 0x002fc80007ffe00f */
/*06e0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f06270 */
/*06f0*/ IADD3 R11, R17, R0, RZ ; /* 0x00000000110b7210 */
/* 0x001fc80007ffe0ff */
/*0700*/ ISETP.GE.OR P1, PT, R11, c[0x0][0x178], !P0 ; /* 0x00005e000b007a0c */
/* 0x000fe20004726670 */
/*0710*/ IMAD.IADD R10, R17, 0x1, R8 ; /* 0x00000001110a7824 */
/* 0x004fe400078e0208 */
/*0720*/ IMAD.IADD R6, R4, 0x1, R15 ; /* 0x0000000104067824 */
/* 0x000fc600078e020f */
/*0730*/ ISETP.LT.OR P0, PT, R10, 0x1, !P0 ; /* 0x000000010a00780c */
/* 0x000fce0004701670 */
/*0740*/ @!P1 IMNMX R7, R6, UR4, PT ; /* 0x0000000406079c17 */
/* 0x000fe4000b800200 */
/*0750*/ @!P1 IMNMX R4, R11, UR6, PT ; /* 0x000000060b049c17 */
/* 0x000fe4000b800200 */
/*0760*/ @!P1 IMNMX R7, RZ, R7, !PT ; /* 0x00000007ff079217 */
/* 0x000fe40007800200 */
/*0770*/ @!P1 IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff049217 */
/* 0x000fe20007800200 */
/*0780*/ @!P0 IMAD.IADD R5, R5, 0x1, R8 ; /* 0x0000000105058824 */
/* 0x000fc800078e0208 */
/*0790*/ @!P1 IMAD R15, R7, c[0x0][0x1a0], R4 ; /* 0x00006800070f9a24 */
/* 0x000fe200078e0204 */
/*07a0*/ @!P0 IMNMX R4, R6.reuse, UR4, PT ; /* 0x0000000406048c17 */
/* 0x040fe4000b800200 */
/*07b0*/ @!P0 IMNMX R5, R5, UR6, PT ; /* 0x0000000605058c17 */
/* 0x000fe4000b800200 */
/*07c0*/ IMNMX R18, R11, c[0x0][0x178], PT ; /* 0x00005e000b127a17 */
/* 0x000fe40003800200 */
/*07d0*/ IMNMX R17, R9, c[0x0][0x174], PT ; /* 0x00005d0009117a17 */
/* 0x000fe40003800200 */
/*07e0*/ @!P0 IMNMX R7, RZ, R4, !PT ; /* 0x00000004ff078217 */
/* 0x000fe40007800200 */
/*07f0*/ @!P0 IMNMX R16, RZ, R5, !PT ; /* 0x00000005ff108217 */
/* 0x000fe20007800200 */
/*0800*/ @!P1 IMAD.WIDE R4, R15, R14, c[0x0][0x198] ; /* 0x000066000f049625 */
/* 0x000fe200078e020e */
/*0810*/ IMNMX R6, R6, c[0x0][0x174], PT ; /* 0x00005d0006067a17 */
/* 0x000fc40003800200 */
/*0820*/ IMNMX R22, RZ, R18, !PT ; /* 0x00000012ff167217 */
/* 0x000fe40007800200 */
/*0830*/ IMNMX R15, RZ, R17, !PT ; /* 0x00000011ff0f7217 */
/* 0x000fe20007800200 */
/*0840*/ @!P0 IMAD R7, R7, c[0x0][0x1a0], R16 ; /* 0x0000680007078a24 */
/* 0x000fe200078e0210 */
/*0850*/ IMNMX R23, RZ, R6, !PT ; /* 0x00000006ff177217 */
/* 0x000fe20007800200 */
/*0860*/ @!P1 LDG.E R16, [R4.64] ; /* 0x0000000804109981 */
/* 0x0000a2000c1e1900 */
/*0870*/ IMNMX R6, R10, c[0x0][0x178], PT ; /* 0x00005e000a067a17 */
/* 0x000fe20003800200 */
/*0880*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe400078e00ff */
/*0890*/ IMAD R19, R15, UR5, R22 ; /* 0x000000050f137c24 */
/* 0x000fe4000f8e0216 */
/*08a0*/ @!P0 IMAD.WIDE R20, R7, R14, c[0x0][0x198] ; /* 0x0000660007148625 */
/* 0x000fc800078e020e */
/*08b0*/ IMAD R7, R23, UR5, R22 ; /* 0x0000000517077c24 */
/* 0x000fe2000f8e0216 */
/*08c0*/ IMNMX R22, RZ, R6, !PT ; /* 0x00000006ff167217 */
/* 0x000fe20007800200 */
/*08d0*/ IMAD.WIDE R18, R19, R14.reuse, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x080fe200078e020e */
/*08e0*/ @!P0 LDG.E R17, [R20.64] ; /* 0x0000000814118981 */
/* 0x0002e6000c1e1900 */
/*08f0*/ IMAD.WIDE R6, R7, R14, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe400078e020e */
/*0900*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000f24000c1e1900 */
/*0910*/ IMAD R5, R15, UR5, R22 ; /* 0x000000050f057c24 */
/* 0x001fc4000f8e0216 */
/*0920*/ IMAD R15, R23, UR5, R22 ; /* 0x00000005170f7c24 */
/* 0x000fe2000f8e0216 */
/*0930*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000162000c1e1900 */
/*0940*/ IMAD.WIDE R4, R5, R14, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc600078e020e */
/*0950*/ LDG.E R22, [R2.64] ; /* 0x0000000802167981 */
/* 0x000f62000c1e1900 */
/*0960*/ IMAD.WIDE R14, R15, R14, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc600078e020e */
/*0970*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f68000c1e1900 */
/*0980*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000f62000c1e1900 */
/*0990*/ I2F R21, R0 ; /* 0x0000000000157306 */
/* 0x002e700000201400 */
/*09a0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e220000201400 */
/*09b0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe20003f06270 */
/*09c0*/ FADD R21, -R21, R12 ; /* 0x0000000c15157221 */
/* 0x002fe20000000100 */
/*09d0*/ ISETP.GE.AND P2, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fc80003f46270 */
/*09e0*/ FSEL R21, R21, 1, P0 ; /* 0x3f80000015157808 */
/* 0x000fe20000000000 */
/*09f0*/ FADD R13, R8, -R13 ; /* 0x8000000d080d7221 */
/* 0x001fe20000000000 */
/*0a00*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x000fc60003f06270 */
/*0a10*/ FADD R7, R13, 1 ; /* 0x3f8000000d077421 */
/* 0x000fe20000000000 */
/*0a20*/ ISETP.GT.AND P0, PT, R9, RZ, !P0 ; /* 0x000000ff0900720c */
/* 0x000fc80004704270 */
/*0a30*/ FSEL R7, R7, 1, !P2 ; /* 0x3f80000007077808 */
/* 0x000fe40005000000 */
/*0a40*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */
/* 0x000fcc0004000000 */
/*0a50*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000e220000201000 */
/*0a60*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff101224 */
/* 0x000fc800078e00ff */
/*0a70*/ FFMA R16, R21, R16, RZ ; /* 0x0000001015107223 */
/* 0x004fc800000000ff */
/*0a80*/ FFMA R7, R7, R17, R16 ; /* 0x0000001107077223 */
/* 0x008fc80000000010 */
/*0a90*/ FADD R7, R7, R18 ; /* 0x0000001207077221 */
/* 0x010fc80000000000 */
/*0aa0*/ FADD R7, R7, -R6 ; /* 0x8000000607077221 */
/* 0x020fc80000000000 */
/*0ab0*/ FADD R7, R7, -R4 ; /* 0x8000000407077221 */
/* 0x000fc80000000000 */
/*0ac0*/ FADD R7, R7, R14 ; /* 0x0000000e07077221 */
/* 0x000fc80000000000 */
/*0ad0*/ FMUL R7, R7, R0 ; /* 0x0000000007077220 */
/* 0x001fc80000400000 */
/*0ae0*/ FFMA R7, -R7, R22, -RZ ; /* 0x0000001607077223 */
/* 0x000fca00000009ff */
/*0af0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101908 */
/*0b00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b10*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.globl _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.p2align 8
.type _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i,@function
_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i:
s_load_b32 s6, s[0:1], 0x18
v_lshl_add_u32 v0, s15, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v0
v_add_nc_u32_e32 v4, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s6, 31
s_add_i32 s2, s6, s4
v_xor_b32_e32 v3, s4, v3
s_xor_b32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s2, 0, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s2, v1
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s3, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_hi_u32 v1, v4, v1
s_add_i32 s8, s3, s7
s_xor_b32 s8, s8, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v5, s8
s_sub_i32 s4, 0, s8
v_mul_lo_u32 v2, v1, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_subrev_nc_u32_e32 v6, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v6
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cvt_u32_f32_e32 v2, v5
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, s4, v2
s_or_b32 s4, s6, s3
s_cmp_gt_i32 s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v1, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v5, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v5, v3
v_xor_b32_e32 v3, s7, v3
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s8
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s8, v4
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v2
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_cselect_b32 s2, -1, 0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_17
v_ashrrev_i32_e32 v4, 31, v2
s_mul_i32 s2, s6, s3
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v3, s2, v2
v_mul_lo_u32 v5, v1, s6
v_lshrrev_b32_e32 v4, 30, v4
v_mul_lo_u32 v7, v2, s3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v2, v4
v_ashrrev_i32_e32 v4, 31, v3
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v5, v1, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v8, -4, v6
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmpx_ne_u32_e32 0, v2
s_xor_b32 s7, exec_lo, s2
s_cbranch_execz .LBB0_15
v_ashrrev_i32_e32 v1, 2, v6
v_cmp_lt_i32_e32 vcc_lo, 0, v2
s_load_b64 s[4:5], s[0:1], 0x20
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 1, v1
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v1, vcc_lo
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v7, v[6:7], off
v_cmpx_ne_u32_e32 2, v2
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_cmp_lt_i32_e32 vcc_lo, 2, v2
s_load_b64 s[4:5], s[0:1], 0x28
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v6, v[8:9], off
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_6
s_sub_i32 s4, 0, s6
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v6, s4
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_ne_u32_e32 vcc_lo, 3, v2
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_8:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_10
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, s6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, -1.0, v7
v_add_f32_e32 v7, -1.0, v6
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x38
s_load_b32 s8, s[0:1], 0x40
v_add_nc_u32_e32 v11, 1, v0
v_mov_b32_e32 v9, 0
v_ceil_f32_e32 v1, v1
v_ceil_f32_e32 v7, v7
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v10, v1
v_cvt_i32_f32_e32 v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v1, v5, v10, 1
v_add_nc_u32_e32 v7, v11, v8
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
v_min_i32_e32 v12, v7, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v12
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v10, v0, v8
s_add_i32 s2, s3, -1
s_add_i32 s10, s6, -1
v_minmax_i32 v12, s2, v13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_minmax_i32 v10, s10, v10, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[14:15], null, v12, s8, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s2, s4, v14
v_add_co_ci_u32_e64 v15, s2, s5, v15, s2
global_load_b32 v10, v[14:15], off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s9
v_floor_f32_e32 v12, v2
s_xor_b32 s9, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v12, v12
v_add_nc_u32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v11
s_and_b32 s9, s2, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_14
s_add_i32 s9, s3, -1
s_add_i32 s10, s6, -1
v_minmax_i32 v16, s9, v13, 0
v_minmax_i32 v9, s10, v11, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, v16, s8, v[9:10]
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_add_co_u32 v14, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
global_load_b32 v9, v[14:15], off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
v_minmax_i32 v14, v1, s3, 0
v_minmax_i32 v13, v13, s3, 0
s_load_b64 s[0:1], s[0:1], 0x0
v_minmax_i32 v20, v7, s6, 0
v_cvt_f32_i32_e32 v12, v12
v_mad_u64_u32 v[15:16], null, v14, s6, v[14:15]
v_minmax_i32 v14, v11, s6, 0
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v2, v2, v12
v_mad_u64_u32 v[16:17], null, v13, s6, v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_dual_sub_f32 v6, v8, v6 :: v_dual_add_nc_u32 v13, v14, v15
v_add_nc_u32_e32 v15, v20, v15
v_mad_u64_u32 v[17:18], null, v5, s6, v[0:1]
v_add_nc_u32_e32 v19, v14, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v14, 31, v13
v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_nc_u32 v21, v20, v16
v_ashrrev_i32_e32 v16, 31, v15
v_ashrrev_i32_e32 v20, 31, v19
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_ashrrev_i32_e32 v22, 31, v21
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_lshlrev_b64 v[19:20], 2, v[19:20]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v19, vcc_lo, s0, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v20, vcc_lo
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_clause 0x1
global_load_b32 v0, v[13:14], off
global_load_b32 v5, v[19:20], off
v_add_co_u32 v13, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s0, v21
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v22, vcc_lo
global_load_b32 v19, v[13:14], off
v_cmp_gt_i32_e64 s0, s3, v1
global_load_b32 v15, v[15:16], off
v_lshlrev_b64 v[13:14], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v13
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v14, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v11
global_load_b32 v13, v[3:4], off
v_cndmask_b32_e32 v2, 1.0, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s6, v7
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, v9, 0
v_cndmask_b32_e32 v6, 1.0, v6, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_fmac_f32_e32 v2, v6, v10
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, 1.0, s0
s_waitcnt vmcnt(4)
v_add_f32_e32 v0, v0, v2
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v5
s_waitcnt vmcnt(2)
v_sub_f32_e32 v0, v0, v19
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v15, v0
v_mul_f32_e64 v0, v1, -v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v0, v13, v0
global_store_b32 v[3:4], v0, off
.LBB0_15:
s_and_not1_saveexec_b32 s0, s7
s_cbranch_execz .LBB0_17
v_mad_u64_u32 v[1:2], null, v5, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v3, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 68
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, .Lfunc_end0-_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 68
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f169f_00000000-6_xMinDeltaIntegralFracKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i
.type _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i, @function
_Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq 256(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i, .-_Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i
.globl _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.type _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, @function
_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z66__device_stub__Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_iPKfPfiiiS0_S0_S0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, .-_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "xMinDeltaIntegralFracKernel.hip"
.globl _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i # -- Begin function _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.p2align 4, 0x90
.type _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i,@function
_Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i: # @_Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, .Lfunc_end0-_Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i,@object # @_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.section .rodata,"a",@progbits
.globl _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.p2align 3, 0x0
_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i:
.quad _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.size _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27xMinDeltaIntegralFracKernelPKfPfiiiS0_S0_S0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <string>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define AND 0
#define OR 1
#define NAND 2
#define NOR 3
#define XOR 4
#define NXOR 5
/*
* Evaluates logical expression.
*/
char evaluateLogicGate(int ops[]) {
int result=0;
switch (ops[2]) {
case NOR:
result = !(ops[0] | ops[1]);
break;
case XOR:
result = ops[0] ^ ops[1];
break;
case NAND:
result = !(ops[0] & ops[1]);
break;
case AND:
result = ops[0] & ops[1];
break;
case OR:
result = ops[0] | ops[1];
break;
case NXOR:
result = !(ops[0] ^ ops[1]);
break;
}
char output = result + '0';
return output;
}
/*
* Sequential computation of list of logical expressions.
* Takes input file, file length and output file name as arguments.
*/
int main(int argc, char* argv[]) {
if (argc != 4) {
printf("Error: Please enter the input file path, input file length and output file path when running.\n");
return 1;
}
char line[10];
char* inputFileName = argv[1];
int inputLength = atoi(argv[2]);
char* outputFileName = argv[3];
FILE* inputFile = fopen(inputFileName, "r");
FILE* outputFile = fopen(outputFileName, "w");
if (inputFile == NULL) {
fprintf(stderr, "Error opening file.\n");
return 1;
}
clock_t start = clock();
int operands[3] = { 0 };
char result = NULL;
while (fgets(line, 10, inputFile)) {
operands[0] = atoi(line);
operands[1] = atoi(line + 2);
operands[2] = atoi(line + 4);
result = evaluateLogicGate(operands);
fprintf(outputFile, "%c\n", result);
}
clock_t end = clock();
int duration = ((end - start) * 1000) / CLOCKS_PER_SEC;
fclose(outputFile);
fclose(inputFile);
printf("Completed\nTime: %ds %dms\n", duration / 1000, duration % 1000);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <string>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define AND 0
#define OR 1
#define NAND 2
#define NOR 3
#define XOR 4
#define NXOR 5
/*
* Evaluates logical expression.
*/
char evaluateLogicGate(int ops[]) {
int result=0;
switch (ops[2]) {
case NOR:
result = !(ops[0] | ops[1]);
break;
case XOR:
result = ops[0] ^ ops[1];
break;
case NAND:
result = !(ops[0] & ops[1]);
break;
case AND:
result = ops[0] & ops[1];
break;
case OR:
result = ops[0] | ops[1];
break;
case NXOR:
result = !(ops[0] ^ ops[1]);
break;
}
char output = result + '0';
return output;
}
/*
* Sequential computation of list of logical expressions.
* Takes input file, file length and output file name as arguments.
*/
int main(int argc, char* argv[]) {
if (argc != 4) {
printf("Error: Please enter the input file path, input file length and output file path when running.\n");
return 1;
}
char line[10];
char* inputFileName = argv[1];
int inputLength = atoi(argv[2]);
char* outputFileName = argv[3];
FILE* inputFile = fopen(inputFileName, "r");
FILE* outputFile = fopen(outputFileName, "w");
if (inputFile == NULL) {
fprintf(stderr, "Error opening file.\n");
return 1;
}
clock_t start = clock();
int operands[3] = { 0 };
char result = NULL;
while (fgets(line, 10, inputFile)) {
operands[0] = atoi(line);
operands[1] = atoi(line + 2);
operands[2] = atoi(line + 4);
result = evaluateLogicGate(operands);
fprintf(outputFile, "%c\n", result);
}
clock_t end = clock();
int duration = ((end - start) * 1000) / CLOCKS_PER_SEC;
fclose(outputFile);
fclose(inputFile);
printf("Completed\nTime: %ds %dms\n", duration / 1000, duration % 1000);
return 0;
} | .file "tmpxft_001361da_00000000-6_sequential.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17evaluateLogicGatePi
.type _Z17evaluateLogicGatePi, @function
_Z17evaluateLogicGatePi:
.LFB3056:
.cfi_startproc
endbr64
cmpl $5, 8(%rdi)
ja .L12
movl 8(%rdi), %eax
leaq .L6(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L6:
.long .L11-.L6
.long .L10-.L6
.long .L9-.L6
.long .L8-.L6
.long .L7-.L6
.long .L5-.L6
.text
.L8:
movl (%rdi), %eax
orl 4(%rdi), %eax
sete %al
movzbl %al, %eax
.L4:
addl $48, %eax
ret
.L7:
movl (%rdi), %eax
xorl 4(%rdi), %eax
jmp .L4
.L9:
movl (%rdi), %eax
andl 4(%rdi), %eax
sete %al
movzbl %al, %eax
jmp .L4
.L11:
movl (%rdi), %eax
andl 4(%rdi), %eax
jmp .L4
.L10:
movl (%rdi), %eax
orl 4(%rdi), %eax
jmp .L4
.L5:
movl 4(%rdi), %eax
cmpl %eax, (%rdi)
sete %al
movzbl %al, %eax
jmp .L4
.L12:
movl $0, %eax
jmp .L4
.cfi_endproc
.LFE3056:
.size _Z17evaluateLogicGatePi, .-_Z17evaluateLogicGatePi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: Please enter the input file path, input file length and output file path when running.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "w"
.LC3:
.string "Error opening file.\n"
.LC4:
.string "%c\n"
.LC5:
.string "Completed\nTime: %ds %dms\n"
.text
.globl main
.type main, @function
main:
.LFB3057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
cmpl $4, %edi
je .L14
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L13:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %r12
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rbx), %rbp
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbp
testq %rbx, %rbx
je .L22
call clock@PLT
movq %rax, %r13
movq $0, (%rsp)
movl $0, 8(%rsp)
leaq .LC4(%rip), %r12
jmp .L17
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L13
.L18:
leaq 14(%rsp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%rsp)
leaq 16(%rsp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
leaq 18(%rsp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
movq %rsp, %rdi
call _Z17evaluateLogicGatePi
movsbl %al, %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L17:
leaq 14(%rsp), %rdi
movq %rbx, %rcx
movl $10, %edx
movl $10, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L18
call clock@PLT
subq %r13, %rax
movl $1000, %ecx
cqto
idivq %rcx
movq %rax, %r12
movq %rbp, %rdi
call fclose@PLT
movq %rbx, %rdi
call fclose@PLT
movl $1000, %esi
movl %r12d, %eax
cltd
idivl %esi
movl %edx, %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L13
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <string>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define AND 0
#define OR 1
#define NAND 2
#define NOR 3
#define XOR 4
#define NXOR 5
/*
* Evaluates logical expression.
*/
char evaluateLogicGate(int ops[]) {
int result=0;
switch (ops[2]) {
case NOR:
result = !(ops[0] | ops[1]);
break;
case XOR:
result = ops[0] ^ ops[1];
break;
case NAND:
result = !(ops[0] & ops[1]);
break;
case AND:
result = ops[0] & ops[1];
break;
case OR:
result = ops[0] | ops[1];
break;
case NXOR:
result = !(ops[0] ^ ops[1]);
break;
}
char output = result + '0';
return output;
}
/*
* Sequential computation of list of logical expressions.
* Takes input file, file length and output file name as arguments.
*/
int main(int argc, char* argv[]) {
if (argc != 4) {
printf("Error: Please enter the input file path, input file length and output file path when running.\n");
return 1;
}
char line[10];
char* inputFileName = argv[1];
int inputLength = atoi(argv[2]);
char* outputFileName = argv[3];
FILE* inputFile = fopen(inputFileName, "r");
FILE* outputFile = fopen(outputFileName, "w");
if (inputFile == NULL) {
fprintf(stderr, "Error opening file.\n");
return 1;
}
clock_t start = clock();
int operands[3] = { 0 };
char result = NULL;
while (fgets(line, 10, inputFile)) {
operands[0] = atoi(line);
operands[1] = atoi(line + 2);
operands[2] = atoi(line + 4);
result = evaluateLogicGate(operands);
fprintf(outputFile, "%c\n", result);
}
clock_t end = clock();
int duration = ((end - start) * 1000) / CLOCKS_PER_SEC;
fclose(outputFile);
fclose(inputFile);
printf("Completed\nTime: %ds %dms\n", duration / 1000, duration % 1000);
return 0;
} | #include <hip/hip_runtime.h>
#include <string>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define AND 0
#define OR 1
#define NAND 2
#define NOR 3
#define XOR 4
#define NXOR 5
/*
* Evaluates logical expression.
*/
char evaluateLogicGate(int ops[]) {
int result=0;
switch (ops[2]) {
case NOR:
result = !(ops[0] | ops[1]);
break;
case XOR:
result = ops[0] ^ ops[1];
break;
case NAND:
result = !(ops[0] & ops[1]);
break;
case AND:
result = ops[0] & ops[1];
break;
case OR:
result = ops[0] | ops[1];
break;
case NXOR:
result = !(ops[0] ^ ops[1]);
break;
}
char output = result + '0';
return output;
}
/*
* Sequential computation of list of logical expressions.
* Takes input file, file length and output file name as arguments.
*/
int main(int argc, char* argv[]) {
if (argc != 4) {
printf("Error: Please enter the input file path, input file length and output file path when running.\n");
return 1;
}
char line[10];
char* inputFileName = argv[1];
int inputLength = atoi(argv[2]);
char* outputFileName = argv[3];
FILE* inputFile = fopen(inputFileName, "r");
FILE* outputFile = fopen(outputFileName, "w");
if (inputFile == NULL) {
fprintf(stderr, "Error opening file.\n");
return 1;
}
clock_t start = clock();
int operands[3] = { 0 };
char result = NULL;
while (fgets(line, 10, inputFile)) {
operands[0] = atoi(line);
operands[1] = atoi(line + 2);
operands[2] = atoi(line + 4);
result = evaluateLogicGate(operands);
fprintf(outputFile, "%c\n", result);
}
clock_t end = clock();
int duration = ((end - start) * 1000) / CLOCKS_PER_SEC;
fclose(outputFile);
fclose(inputFile);
printf("Completed\nTime: %ds %dms\n", duration / 1000, duration % 1000);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <string>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define AND 0
#define OR 1
#define NAND 2
#define NOR 3
#define XOR 4
#define NXOR 5
/*
* Evaluates logical expression.
*/
char evaluateLogicGate(int ops[]) {
int result=0;
switch (ops[2]) {
case NOR:
result = !(ops[0] | ops[1]);
break;
case XOR:
result = ops[0] ^ ops[1];
break;
case NAND:
result = !(ops[0] & ops[1]);
break;
case AND:
result = ops[0] & ops[1];
break;
case OR:
result = ops[0] | ops[1];
break;
case NXOR:
result = !(ops[0] ^ ops[1]);
break;
}
char output = result + '0';
return output;
}
/*
* Sequential computation of list of logical expressions.
* Takes input file, file length and output file name as arguments.
*/
int main(int argc, char* argv[]) {
if (argc != 4) {
printf("Error: Please enter the input file path, input file length and output file path when running.\n");
return 1;
}
char line[10];
char* inputFileName = argv[1];
int inputLength = atoi(argv[2]);
char* outputFileName = argv[3];
FILE* inputFile = fopen(inputFileName, "r");
FILE* outputFile = fopen(outputFileName, "w");
if (inputFile == NULL) {
fprintf(stderr, "Error opening file.\n");
return 1;
}
clock_t start = clock();
int operands[3] = { 0 };
char result = NULL;
while (fgets(line, 10, inputFile)) {
operands[0] = atoi(line);
operands[1] = atoi(line + 2);
operands[2] = atoi(line + 4);
result = evaluateLogicGate(operands);
fprintf(outputFile, "%c\n", result);
}
clock_t end = clock();
int duration = ((end - start) * 1000) / CLOCKS_PER_SEC;
fclose(outputFile);
fclose(inputFile);
printf("Completed\nTime: %ds %dms\n", duration / 1000, duration % 1000);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <string>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define AND 0
#define OR 1
#define NAND 2
#define NOR 3
#define XOR 4
#define NXOR 5
/*
* Evaluates logical expression.
*/
char evaluateLogicGate(int ops[]) {
int result=0;
switch (ops[2]) {
case NOR:
result = !(ops[0] | ops[1]);
break;
case XOR:
result = ops[0] ^ ops[1];
break;
case NAND:
result = !(ops[0] & ops[1]);
break;
case AND:
result = ops[0] & ops[1];
break;
case OR:
result = ops[0] | ops[1];
break;
case NXOR:
result = !(ops[0] ^ ops[1]);
break;
}
char output = result + '0';
return output;
}
/*
* Sequential computation of list of logical expressions.
* Takes input file, file length and output file name as arguments.
*/
int main(int argc, char* argv[]) {
if (argc != 4) {
printf("Error: Please enter the input file path, input file length and output file path when running.\n");
return 1;
}
char line[10];
char* inputFileName = argv[1];
int inputLength = atoi(argv[2]);
char* outputFileName = argv[3];
FILE* inputFile = fopen(inputFileName, "r");
FILE* outputFile = fopen(outputFileName, "w");
if (inputFile == NULL) {
fprintf(stderr, "Error opening file.\n");
return 1;
}
clock_t start = clock();
int operands[3] = { 0 };
char result = NULL;
while (fgets(line, 10, inputFile)) {
operands[0] = atoi(line);
operands[1] = atoi(line + 2);
operands[2] = atoi(line + 4);
result = evaluateLogicGate(operands);
fprintf(outputFile, "%c\n", result);
}
clock_t end = clock();
int duration = ((end - start) * 1000) / CLOCKS_PER_SEC;
fclose(outputFile);
fclose(inputFile);
printf("Completed\nTime: %ds %dms\n", duration / 1000, duration % 1000);
return 0;
} | .text
.file "sequential.hip"
.globl _Z17evaluateLogicGatePi # -- Begin function _Z17evaluateLogicGatePi
.p2align 4, 0x90
.type _Z17evaluateLogicGatePi,@function
_Z17evaluateLogicGatePi: # @_Z17evaluateLogicGatePi
.cfi_startproc
# %bb.0:
movl 8(%rdi), %eax
cmpq $5, %rax
ja .LBB0_9
# %bb.1:
jmpq *.LJTI0_0(,%rax,8)
.LBB0_2:
movl 4(%rdi), %eax
andl (%rdi), %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_3:
movl 4(%rdi), %eax
xorl (%rdi), %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_4:
movl 4(%rdi), %ecx
xorl %eax, %eax
testl %ecx, (%rdi)
jmp .LBB0_8
.LBB0_5:
movl 4(%rdi), %ecx
xorl %eax, %eax
orl (%rdi), %ecx
jmp .LBB0_8
.LBB0_6:
movl 4(%rdi), %eax
orl (%rdi), %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_7:
movl (%rdi), %ecx
xorl %eax, %eax
cmpl 4(%rdi), %ecx
.LBB0_8:
sete %al
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_9:
xorl %eax, %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.Lfunc_end0:
.size _Z17evaluateLogicGatePi, .Lfunc_end0-_Z17evaluateLogicGatePi
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_2
.quad .LBB0_6
.quad .LBB0_4
.quad .LBB0_5
.quad .LBB0_3
.quad .LBB0_7
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
jne .LBB1_1
# %bb.2:
movq 8(%rsi), %rdi
movq 24(%rsi), %r14
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
testq %rbx, %rbx
je .LBB1_3
# %bb.4:
movq %rax, %r14
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
leaq 6(%rsp), %rdi
movl $10, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB1_16
# %bb.5: # %.lr.ph
leaq 10(%rsp), %r13
leaq 6(%rsp), %rbp
jmp .LBB1_6
.LBB1_10: # in Loop: Header=BB1_6 Depth=1
xorl %ecx, %ecx
testl %r15d, %r12d
.LBB1_14: # %_Z17evaluateLogicGatePi.exit
# in Loop: Header=BB1_6 Depth=1
sete %cl
.LBB1_15: # %_Z17evaluateLogicGatePi.exit
# in Loop: Header=BB1_6 Depth=1
addb $48, %cl
movsbl %cl, %edx
movl $.L.str.4, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
movq %rbp, %rdi
movl $10, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB1_16
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %rbp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leaq 8(%rsp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq %r13, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $0, %ecx
cmpl $5, %eax
ja .LBB1_15
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movl %eax, %eax
jmpq *.LJTI1_0(,%rax,8)
.LBB1_11: # in Loop: Header=BB1_6 Depth=1
andl %r15d, %r12d
movl %r12d, %ecx
jmp .LBB1_15
.LBB1_9: # in Loop: Header=BB1_6 Depth=1
xorl %r15d, %r12d
movl %r12d, %ecx
jmp .LBB1_15
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
xorl %ecx, %ecx
orl %r15d, %r12d
jmp .LBB1_14
.LBB1_12: # in Loop: Header=BB1_6 Depth=1
orl %r15d, %r12d
movl %r12d, %ecx
jmp .LBB1_15
.LBB1_13: # in Loop: Header=BB1_6 Depth=1
xorl %ecx, %ecx
cmpl %r12d, %r15d
jmp .LBB1_14
.LBB1_1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
jmp .LBB1_17
.LBB1_16: # %._crit_edge
callq clock
subq 16(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r15
movq %rdx, %rax
shrq $63, %rax
sarq $7, %r15
addq %rax, %r15
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq fclose
movslq %r15d, %rdx
imulq $274877907, %rdx, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
imull $1000, %esi, %eax # imm = 0x3E8
subl %eax, %edx
xorl %ebx, %ebx
movl $.L.str.5, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB1_17:
movl %ebx, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB1_17
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI1_0:
.quad .LBB1_11
.quad .LBB1_12
.quad .LBB1_10
.quad .LBB1_8
.quad .LBB1_9
.quad .LBB1_13
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error opening file.\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%c\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Completed\nTime: %ds %dms\n"
.size .L.str.5, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: Please enter the input file path, input file length and output file path when running."
.size .Lstr, 94
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001361da_00000000-6_sequential.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17evaluateLogicGatePi
.type _Z17evaluateLogicGatePi, @function
_Z17evaluateLogicGatePi:
.LFB3056:
.cfi_startproc
endbr64
cmpl $5, 8(%rdi)
ja .L12
movl 8(%rdi), %eax
leaq .L6(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L6:
.long .L11-.L6
.long .L10-.L6
.long .L9-.L6
.long .L8-.L6
.long .L7-.L6
.long .L5-.L6
.text
.L8:
movl (%rdi), %eax
orl 4(%rdi), %eax
sete %al
movzbl %al, %eax
.L4:
addl $48, %eax
ret
.L7:
movl (%rdi), %eax
xorl 4(%rdi), %eax
jmp .L4
.L9:
movl (%rdi), %eax
andl 4(%rdi), %eax
sete %al
movzbl %al, %eax
jmp .L4
.L11:
movl (%rdi), %eax
andl 4(%rdi), %eax
jmp .L4
.L10:
movl (%rdi), %eax
orl 4(%rdi), %eax
jmp .L4
.L5:
movl 4(%rdi), %eax
cmpl %eax, (%rdi)
sete %al
movzbl %al, %eax
jmp .L4
.L12:
movl $0, %eax
jmp .L4
.cfi_endproc
.LFE3056:
.size _Z17evaluateLogicGatePi, .-_Z17evaluateLogicGatePi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: Please enter the input file path, input file length and output file path when running.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "w"
.LC3:
.string "Error opening file.\n"
.LC4:
.string "%c\n"
.LC5:
.string "Completed\nTime: %ds %dms\n"
.text
.globl main
.type main, @function
main:
.LFB3057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
cmpl $4, %edi
je .L14
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L13:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %r12
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rbx), %rbp
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbp
testq %rbx, %rbx
je .L22
call clock@PLT
movq %rax, %r13
movq $0, (%rsp)
movl $0, 8(%rsp)
leaq .LC4(%rip), %r12
jmp .L17
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L13
.L18:
leaq 14(%rsp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%rsp)
leaq 16(%rsp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
leaq 18(%rsp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
movq %rsp, %rdi
call _Z17evaluateLogicGatePi
movsbl %al, %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L17:
leaq 14(%rsp), %rdi
movq %rbx, %rcx
movl $10, %edx
movl $10, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L18
call clock@PLT
subq %r13, %rax
movl $1000, %ecx
cqto
idivq %rcx
movq %rax, %r12
movq %rbp, %rdi
call fclose@PLT
movq %rbx, %rdi
call fclose@PLT
movl $1000, %esi
movl %r12d, %eax
cltd
idivl %esi
movl %edx, %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L13
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sequential.hip"
.globl _Z17evaluateLogicGatePi # -- Begin function _Z17evaluateLogicGatePi
.p2align 4, 0x90
.type _Z17evaluateLogicGatePi,@function
_Z17evaluateLogicGatePi: # @_Z17evaluateLogicGatePi
.cfi_startproc
# %bb.0:
movl 8(%rdi), %eax
cmpq $5, %rax
ja .LBB0_9
# %bb.1:
jmpq *.LJTI0_0(,%rax,8)
.LBB0_2:
movl 4(%rdi), %eax
andl (%rdi), %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_3:
movl 4(%rdi), %eax
xorl (%rdi), %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_4:
movl 4(%rdi), %ecx
xorl %eax, %eax
testl %ecx, (%rdi)
jmp .LBB0_8
.LBB0_5:
movl 4(%rdi), %ecx
xorl %eax, %eax
orl (%rdi), %ecx
jmp .LBB0_8
.LBB0_6:
movl 4(%rdi), %eax
orl (%rdi), %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_7:
movl (%rdi), %ecx
xorl %eax, %eax
cmpl 4(%rdi), %ecx
.LBB0_8:
sete %al
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.LBB0_9:
xorl %eax, %eax
addb $48, %al
# kill: def $al killed $al killed $eax
retq
.Lfunc_end0:
.size _Z17evaluateLogicGatePi, .Lfunc_end0-_Z17evaluateLogicGatePi
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_2
.quad .LBB0_6
.quad .LBB0_4
.quad .LBB0_5
.quad .LBB0_3
.quad .LBB0_7
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
jne .LBB1_1
# %bb.2:
movq 8(%rsi), %rdi
movq 24(%rsi), %r14
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
testq %rbx, %rbx
je .LBB1_3
# %bb.4:
movq %rax, %r14
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
leaq 6(%rsp), %rdi
movl $10, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB1_16
# %bb.5: # %.lr.ph
leaq 10(%rsp), %r13
leaq 6(%rsp), %rbp
jmp .LBB1_6
.LBB1_10: # in Loop: Header=BB1_6 Depth=1
xorl %ecx, %ecx
testl %r15d, %r12d
.LBB1_14: # %_Z17evaluateLogicGatePi.exit
# in Loop: Header=BB1_6 Depth=1
sete %cl
.LBB1_15: # %_Z17evaluateLogicGatePi.exit
# in Loop: Header=BB1_6 Depth=1
addb $48, %cl
movsbl %cl, %edx
movl $.L.str.4, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
movq %rbp, %rdi
movl $10, %esi
movq %rbx, %rdx
callq fgets
testq %rax, %rax
je .LBB1_16
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %rbp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leaq 8(%rsp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq %r13, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $0, %ecx
cmpl $5, %eax
ja .LBB1_15
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movl %eax, %eax
jmpq *.LJTI1_0(,%rax,8)
.LBB1_11: # in Loop: Header=BB1_6 Depth=1
andl %r15d, %r12d
movl %r12d, %ecx
jmp .LBB1_15
.LBB1_9: # in Loop: Header=BB1_6 Depth=1
xorl %r15d, %r12d
movl %r12d, %ecx
jmp .LBB1_15
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
xorl %ecx, %ecx
orl %r15d, %r12d
jmp .LBB1_14
.LBB1_12: # in Loop: Header=BB1_6 Depth=1
orl %r15d, %r12d
movl %r12d, %ecx
jmp .LBB1_15
.LBB1_13: # in Loop: Header=BB1_6 Depth=1
xorl %ecx, %ecx
cmpl %r12d, %r15d
jmp .LBB1_14
.LBB1_1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
jmp .LBB1_17
.LBB1_16: # %._crit_edge
callq clock
subq 16(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r15
movq %rdx, %rax
shrq $63, %rax
sarq $7, %r15
addq %rax, %r15
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
callq fclose
movslq %r15d, %rdx
imulq $274877907, %rdx, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
imull $1000, %esi, %eax # imm = 0x3E8
subl %eax, %edx
xorl %ebx, %ebx
movl $.L.str.5, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB1_17:
movl %ebx, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB1_17
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI1_0:
.quad .LBB1_11
.quad .LBB1_12
.quad .LBB1_10
.quad .LBB1_8
.quad .LBB1_9
.quad .LBB1_13
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error opening file.\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%c\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Completed\nTime: %ds %dms\n"
.size .L.str.5, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: Please enter the input file path, input file length and output file path when running."
.size .Lstr, 94
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
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