system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan(float * input, float * output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float sh_input[2048];
int tx = threadIdx.x;
int tx2= tx + blockDim.x;
int bdimx = blockDim.x;
int i = 2*blockIdx.x*blockDim.x + tx;
int ... | .text
.file "scan.hip"
.globl _Z19__device_stub__scanPfS_i # -- Begin function _Z19__device_stub__scanPfS_i
.p2align 4, 0x90
.type _Z19__device_stub__scanPfS_i,@function
_Z19__device_stub__scanPfS_i: # @_Z19__device_stub__scanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4scanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e2200000025... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPfS_i
.globl _Z4scanPfS_i
.p2align 8
.type _Z4scanPfS_i,@function
_Z4scanPfS_i:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000df603_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "scan.hip"
.globl _Z19__device_stub__scanPfS_i # -- Begin function _Z19__device_stub__scanPfS_i
.p2align 4, 0x90
.type _Z19__device_stub__scanPfS_i,@function
_Z19__device_stub__scanPfS_i: # @_Z19__device_stub__scanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(... | code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e22000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(... | .file "tmpxft_00178551_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(... | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 5... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 5... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_dual_mov_b32 v3, 0 ::... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 5... | .text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_off... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e22000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_dual_mov_b32 v3, 0 ::... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00178551_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_off... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z12hello_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e2200000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0015df80_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
.globl _Z27__device_stub__hello_kernelv # -- Begin function _Z27__device_stub__hello_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__hello_kernelv,@function
_Z27__device_stub__hello_kernelv: # @_Z27__device_stub__hello_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015df80_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "hello.hip"
.globl _Z27__device_stub__hello_kernelv # -- Begin function _Z27__device_stub__hello_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__hello_kernelv,@function
_Z27__device_stub__hello_kernelv: # @_Z27__device_stub__hello_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x )... | code for sm_80
Function : _Z28RunLengthEncodingComputationPcPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x00000000000079... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x )... | .file "tmpxft_000d5518_00000000-6_RunLengthEncoding.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
cal... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x )... | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28RunLengthEncodingComputationPcPii
.globl _Z28RunLengthEncodingComputationPcPii
.p2align 8
.type _Z28RunLengthEncodingComputationPcPii,@function
_Z28RunLengthEncodingComputationPcPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x ... | .text
.file "RunLengthEncoding.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z43__device_stub__RunLengthEncodingComputationPcPii # -- Begin function _Z43__device_stu... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28RunLengthEncodingComputationPcPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x00000000000079... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28RunLengthEncodingComputationPcPii
.globl _Z28RunLengthEncodingComputationPcPii
.p2align 8
.type _Z28RunLengthEncodingComputationPcPii,@function
_Z28RunLengthEncodingComputationPcPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing r... | .file "tmpxft_000f3e36_00000000-6_stats.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing r... | #include <hip/hip_runtime.h>
__global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the p... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the p... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21sorted_mean_per_slicePjS_PdjS0_
.globl _Z21sorted_mean_per_slicePjS_PdjS0_
.p2align 8
.type _Z21sorted_mean_per_slicePjS_PdjS0_,@function
_Z21sorted_mean_per_slicePjS_PdjS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x18
s_add... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the p... | .text
.file "stats.hip"
.globl _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_ # -- Begin function _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.p2align 4, 0x90
.type _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_,@function
_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_: # @_Z36__device_stub__sorted_me... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f3e36_00000000-6_stats.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "stats.hip"
.globl _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_ # -- Begin function _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.p2align 4, 0x90
.type _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_,@function
_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_: # @_Z36__device_stub__sorted_me... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matrices */
float A[N*N], B[N*N];
/... | .file "tmpxft_000bdffa_00000000-6_matrixNormCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matrices */
float A[N*N], B[N*N];
/... | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matric... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matric... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixNormPfS_i
.globl _Z10matrixNormPfS_i
.p2align 8
.type _Z10matrixNormPfS_i,@function
_Z10matrixNormPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matric... | .text
.file "matrixNormCuda.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI0_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bdffa_00000000-6_matrixNormCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "matrixNormCuda.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI0_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j;
float depth_point = depth[ ... | .file "tmpxft_001612d6_00000000-6_to3d_point.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j;
float depth_point = depth[ ... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10to3d_pointPfS_
.globl _Z10to3d_pointPfS_
.p2align 8
.type _Z10to3d_pointPfS_,@function
_Z10to3d_pointPfS_:
v_and_b32_e32 v13, 0x3ff, v0
s_lshl_b32 s12, s14, 5
s_load_b32 s13, s[0:1], 0x10
s_mov_b32 s9, 0x400921fb
s_mov_b32 s8, 0... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j... | .text
.file "to3d_point.hip"
.globl _Z25__device_stub__to3d_pointPfS_ # -- Begin function _Z25__device_stub__to3d_pointPfS_
.p2align 4, 0x90
.type _Z25__device_stub__to3d_pointPfS_,@function
_Z25__device_stub__to3d_pointPfS_: # @_Z25__device_stub__to3d_pointPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001612d6_00000000-6_to3d_point.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "to3d_point.hip"
.globl _Z25__device_stub__to3d_pointPfS_ # -- Begin function _Z25__device_stub__to3d_pointPfS_
.p2align 4, 0x90
.type _Z25__device_stub__to3d_pointPfS_,@function
_Z25__device_stub__to3d_pointPfS_: # @_Z25__device_stub__to3d_pointPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __managed__ int block_optimal_pat... | .file "tmpxft_001bb513_00000000-6_tsp_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10871:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cuda... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __managed__ int block_optimal_pat... | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __ma... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __ma... | .text
.file "tsp_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6randomii # -- Begin function _Z6randomii
.p2align 4, 0x90
.type _Z6randomii... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomn... | code for sm_80
Function : _Z6kernelPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomn... | .file "tmpxft_0012b45c_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomn... | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiPf
.globl _Z6kernelPiPf
.p2align 8
.type _Z6kernelPiPf,@function
_Z6kernelPiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0x3fe55555
s_mov_b32 s0, 0x55555555
s_mov_b3... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (... | .text
.file "cuda.hip"
.globl _Z21__device_stub__kernelPiPf # -- Begin function _Z21__device_stub__kernelPiPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiPf,@function
_Z21__device_stub__kernelPiPf: # @_Z21__device_stub__kernelPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi,... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012b45c_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "cuda.hip"
.globl _Z21__device_stub__kernelPiPf # -- Begin function _Z21__device_stub__kernelPiPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiPf,@function
_Z21__device_stub__kernelPiPf: # @_Z21__device_stub__kernelPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi,... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#d... | code for sm_80
Function : _Z11sgemmKernelPfS_S_iiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#d... | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#define NUM_OF_GPU_THREADS 2
#define ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#define NUM_OF_GPU_THREADS 2
#define ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sgemmKernelPfS_S_iiiff
.globl _Z11sgemmKernelPfS_S_iiiff
.p2align 8
.type _Z11sgemmKernelPfS_S_iiiff,@function
_Z11sgemmKernelPfS_S_iiiff:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11sgemmKernelPfS_S_iiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sgemmKernelPfS_S_iiiff
.globl _Z11sgemmKernelPfS_S_iiiff
.p2align 8
.type _Z11sgemmKernelPfS_S_iiiff,@function
_Z11sgemmKernelPfS_S_iiiff:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weig... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weig... | .file "tmpxft_001151a9_00000000-6_inner_product_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
ad... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weig... | #include <hip/hip_runtime.h>
//#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(fa... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(fa... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(fa... | .text
.file "inner_product_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/l... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001151a9_00000000-6_inner_product_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
ad... | .text
.file "inner_product_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/l... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | code for sm_80
Function : _Z1fPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | .file "tmpxft_00045e9a_00000000-6_new_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | #include <hip/hip_runtime.h>
__global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1fPiS_
.globl _Z1fPiS_
.p2align 8
.type _Z1fPiS_,@function
_Z1fPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_sub_u32 s4, s2, s0
s_subb_u32 s5, s3, s1
s_delay_alu insti... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | .text
.file "new_test.hip"
.globl _Z16__device_stub__fPiS_ # -- Begin function _Z16__device_stub__fPiS_
.p2align 4, 0x90
.type _Z16__device_stub__fPiS_,@function
_Z16__device_stub__fPiS_: # @_Z16__device_stub__fPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
m... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1fPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1fPiS_
.globl _Z1fPiS_
.p2align 8
.type _Z1fPiS_,@function
_Z1fPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_sub_u32 s4, s2, s0
s_subb_u32 s5, s3, s1
s_delay_alu insti... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045e9a_00000000-6_new_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "new_test.hip"
.globl _Z16__device_stub__fPiS_ # -- Begin function _Z16__device_stub__fPiS_
.p2align 4, 0x90
.type _Z16__device_stub__fPiS_,@function
_Z16__device_stub__fPiS_: # @_Z16__device_stub__fPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
m... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | code for sm_80
Function : _Z13computeSquarePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | .file "tmpxft_001b0173_00000000-6_computeSquare.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13computeSquarePiS_
.globl _Z13computeSquarePiS_
.p2align 8
.type _Z13computeSquarePiS_,@function
_Z13computeSquarePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_w... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | .text
.file "computeSquare.hip"
.globl _Z28__device_stub__computeSquarePiS_ # -- Begin function _Z28__device_stub__computeSquarePiS_
.p2align 4, 0x90
.type _Z28__device_stub__computeSquarePiS_,@function
_Z28__device_stub__computeSquarePiS_: # @_Z28__device_stub__computeSquarePiS_
.cfi_startproc
# %bb.0:
subq $88, %rs... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13computeSquarePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13computeSquarePiS_
.globl _Z13computeSquarePiS_
.p2align 8
.type _Z13computeSquarePiS_,@function
_Z13computeSquarePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_w... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b0173_00000000-6_computeSquare.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... | .text
.file "computeSquare.hip"
.globl _Z28__device_stub__computeSquarePiS_ # -- Begin function _Z28__device_stub__computeSquarePiS_
.p2align 4, 0x90
.type _Z28__device_stub__computeSquarePiS_,@function
_Z28__device_stub__computeSquarePiS_: # @_Z28__device_stub__computeSquarePiS_
.cfi_startproc
# %bb.0:
subq $88, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shar... | code for sm_80
Function : _Z24Pixel_Shared_ConvolutionPiS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shar... | .file "tmpxft_001510bc_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shar... | #include <hip/hip_runtime.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24Pixel_Shared_ConvolutionPiS_mm
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.p2align 8
.type _Z24Pixel_Shared_ConvolutionPiS_mm,@function
_Z24Pixel_Shared_ConvolutionPiS_mm:
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e64 s2, s[8:... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void... | .text
.file "cuda.hip"
.globl _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm # -- Begin function _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.p2align 4, 0x90
.type _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm,@function
_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm: # @_Z39__device_stub__Pixel_Shared_C... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24Pixel_Shared_ConvolutionPiS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24Pixel_Shared_ConvolutionPiS_mm
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.p2align 8
.type _Z24Pixel_Shared_ConvolutionPiS_mm,@function
_Z24Pixel_Shared_ConvolutionPiS_mm:
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e64 s2, s[8:... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001510bc_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "cuda.hip"
.globl _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm # -- Begin function _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.p2align 4, 0x90
.type _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm,@function
_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm: # @_Z39__device_stub__Pixel_Shared_C... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated docume... | .file "tmpxft_0014b71e_00000000-6_sort16.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated docume... | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated docume... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated docume... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13nvidiaBatcherPi
.globl _Z13nvidiaBatcherPi
.p2align 8
.type _Z13nvidiaBatcherPi,@function
_Z13nvidiaBatcherPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v1, s15, 9, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
v_lsh... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated docume... | .text
.file "sort16.hip"
.globl _Z7initGPUv # -- Begin function _Z7initGPUv
.p2align 4, 0x90
.type _Z7initGPUv,@function
_Z7initGPUv: # @_Z7initGPUv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl deviceNum(%rip), %edi
callq hipSetDevice
movslq dataSize(%rip... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b71e_00000000-6_sort16.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "sort16.hip"
.globl _Z7initGPUv # -- Begin function _Z7initGPUv
.p2align 4, 0x90
.type _Z7initGPUv,@function
_Z7initGPUv: # @_Z7initGPUv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl deviceNum(%rip), %edi
callq hipSetDevice
movslq dataSize(%rip... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#in... | code for sm_80
Function : _Z10initializePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2200... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#in... | .file "tmpxft_001a55f0_00000000-6_Multi_GPU_Test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#in... | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#in... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#in... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePdS_
.globl _Z10initializePdS_
.p2align 8
.type _Z10initializePdS_,@function
_Z10initializePdS_:
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_waitcnt l... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#in... | .text
.file "Multi_GPU_Test.hip"
.globl _Z5divUpii # -- Begin function _Z5divUpii
.p2align 4, 0x90
.type _Z5divUpii,@function
_Z5divUpii: # @_Z5divUpii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10initializePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2200... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePdS_
.globl _Z10initializePdS_
.p2align 8
.type _Z10initializePdS_,@function
_Z10initializePdS_:
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_waitcnt l... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a55f0_00000000-6_Multi_GPU_Test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "Multi_GPU_Test.hip"
.globl _Z5divUpii # -- Begin function _Z5divUpii
.p2align 4, 0x90
.type _Z5divUpii,@function
_Z5divUpii: # @_Z5divUpii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, d... | code for sm_80
Function : _Z9matrixMulPdS_S_ll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e28... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, d... | .file "tmpxft_0012c2cb_00000000-6_gpu_mul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUn... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, d... | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, d... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, d... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_ll
.globl _Z9matrixMulPdS_S_ll
.p2align 8
.type _Z9matrixMulPdS_S_ll,@function
_Z9matrixMulPdS_S_ll:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xfff... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, d... | .text
.file "gpu_mul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matrixMulPdS_S_ll # -- Begin function _Z24__device_stub__matrixMulPdS_S_ll
.p2al... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPdS_S_ll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e28... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_ll
.globl _Z9matrixMulPdS_S_ll
.p2align 8
.type _Z9matrixMulPdS_S_ll,@function
_Z9matrixMulPdS_S_ll:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xfff... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c2cb_00000000-6_gpu_mul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUn... | .text
.file "gpu_mul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matrixMulPdS_S_ll # -- Begin function _Z24__device_stub__matrixMulPdS_S_ll
.p2al... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCal... | code for sm_80
Function : _Z10evolve_GPUPdS_S_S_idddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCal... | .file "tmpxft_00062ed2_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCal... | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafe... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafe... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10evolve_GPUPdS_S_S_idddi
.globl _Z10evolve_GPUPdS_S_S_idddi
.p2align 8
.type _Z10evolve_GPUPdS_S_S_idddi,@function
_Z10evolve_GPUPdS_S_S_idddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s10, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b3... |
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