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You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//#pragma comment (lib, "cublas.lib")
//#include "stdio.h"
//#include <cuda.h>
//using namespace std;
//#include <ctime>
//#include "cuda_runtime.h"
//#include "curand_kernel.h"
//#include "device_launch_parameters.h"
//#include <stdio.h>
//#include <stdlib.h>
//
//#include <string>
//#include <iomanip>
//#include <time.h>
//#include <iostream>
//#include <cmath>
//#include <math.h>
//
//#define TRAIN_NUM 60000
//#define TEST_NUM 10000
//#define ROW 28
//#define COL 28
//#define CONV_SIZE 24
//#define POOL_SIZE 12
//#define FC1_SIZE 5
//#define FC2_SIZE 10
//#define CONV_W_SIZE 5
//#define CONV_W_NUM 6
//
//int correct_cnt;
//float avg_error;
//float max_acc;
//
//float alpha = 0.2;
//int epochs = 5;
//int minibatch = 1;
//
//float train_image[TRAIN_NUM][ROW][COL];
//int train_label[TRAIN_NUM];
//float test_image[TEST_NUM][ROW][COL];
//int test_label[TEST_NUM];
//
//float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_b[CONV_W_NUM];
//float fc1_b[FC1_SIZE];
//float fc1_w[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_b[FC2_SIZE];
//float fc2_w[FC2_SIZE][FC1_SIZE];
//
//float input[ROW][COL];
//float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//float conv_a[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//int pool_pos[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float pool[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc1_z[FC1_SIZE];
//float fc1_a[FC1_SIZE];
//float fc2_z[FC2_SIZE];
//float fc2_a[FC2_SIZE];
//float output[FC2_SIZE];
//int answer[FC2_SIZE];
//
//float conv_dw[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_db[CONV_W_NUM];
//float fc1_db[FC1_SIZE];
//float fc1_dw[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_db[FC2_SIZE];
//float fc2_dw[FC2_SIZE][FC1_SIZE];
//float C[FC2_SIZE];
//float fc2_delta[FC2_SIZE];
//float fc1_delta[FC1_SIZE];
//float conv_sigma_delta[CONV_W_NUM];
//float conv_delta[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//
//int swap_endian(int val)
//{
// unsigned char c1, c2, c3, c4;
// c1 = val & 255;
// c2 = (val >> 8) & 255;
// c3 = (val >> 16) & 255;
// c4 = (val >> 24) & 255;
// return ((int)c1 << 24) + ((int)c2 << 16) + ((int)c3 << 8) + c4;
//}
//void load_data()
//{
// FILE* f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-images.idx3-ubyte", "rb");
// FILE* f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-labels.idx1-ubyte", "rb");
//
// int tmp;
//
// int magic_num;
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// // printf("debug:%d\n",swap_endian(magic_num));
//
// int train_size;
// fread(&train_size, sizeof(int), 1, f_images);
// fread(&train_size, sizeof(int), 1, f_labels);
// train_size = swap_endian(train_size);
//
// // printf("debug:%d\n",swap_endian(train_size));
//
// int rows, cols;
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// // printf("debug:%d\n",swap_endian(rows));
// // printf("debug:%d\n",swap_endian(cols));
//
// for (int i = 0;i < train_size;i++)
// {
// fread(&train_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Training labels : Already read %5d labels\r", i);
// // printf("%d:debug:%d\r",i,train_label[i]);
// // system("pause");
// }
// printf("Training labels : Already read %5d labels\n", train_size);
//
// for (int i = 0;i < train_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// train_image[i][j][k] = tmp;
// train_image[i][j][k] /= 255;
// // printf("%d %d %d debug: %f\n",i,j,k,train_image[i][j][k]);
// // system("pause");
// }
// if (i % 1000 == 0)
// printf("Training images : Already read %5d images\r", i);
// }
// printf("Training images : Already read %5d images\n", train_size);
//
// fclose(f_images);
// fclose(f_labels);
//
// f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-images.idx3-ubyte", "rb");
// f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-labels.idx1-ubyte", "rb");
//
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// int test_size;
// fread(&test_size, sizeof(int), 1, f_images);
// fread(&test_size, sizeof(int), 1, f_labels);
// test_size = swap_endian(test_size);
//
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// for (int i = 0;i < test_size;i++)
// {
// fread(&test_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Testing labels : Already read %5d labels\r", i);
// }
// printf("Testing labels : Already read %5d labels\n", test_size);
//
// for (int i = 0;i < test_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// test_image[i][j][k] = tmp;
// test_image[i][j][k] /= 255;
// }
// if (i % 1000 == 0)
// printf("Testing images : Already read %5d images\r", i);
// }
// printf("Testing images : Already read %5d images\n\n", test_size);
//
// fclose(f_images);
// fclose(f_labels);
//}
//
//float sigmoid(float x)
//{
// return (1 / (1 + exp(-1 * x)));
//}
//
//void set_input(int idx, float image[TRAIN_NUM][ROW][COL])
//{
// for (int i = 0;i < ROW;i++)
// for (int j = 0;j < COL;j++)
// input[i][j] = image[idx][i][j];
//}
//
//void input_conv()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_SIZE;j++)
// for (int k = 0;k < CONV_SIZE;k++)
// {
// conv_z[i][j][k] = 0;
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// conv_z[i][j][k] += input[j + l][k + m] * conv_w[i][l][m];
// conv_z[i][j][k] += conv_b[i];
// conv_a[i][j][k] = sigmoid(conv_z[i][j][k]);
// }
//}
//
//void conv_pool()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float _max = conv_a[i][j * 2][k * 2];
// pool_pos[i][j][k] = 0;
// if (conv_a[i][j * 2][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2][k * 2 + 1];
// pool_pos[i][j][k] = 1;
// }
// if (conv_a[i][j * 2 + 1][k * 2] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2];
// pool_pos[i][j][k] = 2;
// }
// if (conv_a[i][j * 2 + 1][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2 + 1];
// pool_pos[i][j][k] = 3;
// }
// pool[i][j][k] = _max;
// }
//}
//
//void pool_fc1()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_z[i] = 0;
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_z[i] += pool[j][k][l] * fc1_w[i][j][k][l];
// fc1_z[i] += fc1_b[i];
// fc1_a[i] = sigmoid(fc1_z[i]);
// }
//}
//
//void fc1_fc2()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_z[i] = 0;
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_z[i] += fc1_a[j] * fc2_w[i][j];
// fc2_z[i] += fc2_b[i];
// fc2_a[i] = sigmoid(fc2_z[i]);
// }
//}
//
//void set_answer(int idx, int label[TRAIN_NUM])
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// output[i] = fc2_a[i];
// answer[i] = (label[idx] == i) ? 1 : 0;
// }
//}
//
//void check_answer(int& correct_cnt)
//{
// float _max = output[0];
// int max_pos = 0;
// for (int i = 0;i < FC2_SIZE;i++)
// {
// if (_max < output[i])
// {
// _max = output[i];
// max_pos = i;
// }
// }
// if (answer[max_pos])
// correct_cnt++;
//}
//
//void get_error(float& avg_error)
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// C[i] = output[i] - answer[i];
// avg_error += C[i] * C[i] * 0.5;
// }
//}
//
//
//void update_fc2_b()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_delta[i] = alpha * C[i] * (fc2_a[i] * (1.0 - fc2_a[i]));
// fc2_db[i] += fc2_delta[i];
// }
//}
//
//void update_fc2_w()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_dw[i][j] += fc2_delta[i] * fc1_a[j];
//}
//
//void update_fc1_b()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// float error = 0;
// for (int j = 0;j < FC2_SIZE;j++)
// error += fc2_delta[j] * fc2_w[j][i];
// fc1_delta[i] = error * (fc1_a[i] * (1.0 - fc1_a[i]));
// fc1_db[i] += fc1_delta[i];
// }
//}
//
//void update_fc1_w()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_dw[i][j][k][l] += fc1_delta[i] * pool[j][k][l];
//}
//
//void update_conv_b()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_sigma_delta[i] = 0;
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float error = 0;
// conv_delta[i][j][k] = 0;
// for (int l = 0;l < FC1_SIZE;l++)
// error += fc1_delta[l] * fc1_w[l][i][j][k];
// conv_delta[i][j][k] = error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// conv_sigma_delta[i] += error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// }
// conv_db[i] += conv_sigma_delta[i];
// }
//}
//
//void update_conv_w()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// {
// float error = 0;
// for (int m = 0;m < POOL_SIZE;m++)
// for (int n = 0;n < POOL_SIZE;n++)
// {
// int x = pool_pos[i][m][n] / 2;
// int y = pool_pos[i][m][n] % 2;
// error += conv_delta[i][m][n] * input[2 * m + j + x][2 * n + k + y];
// }
// conv_dw[i][j][k] += error;
// }
//}
//
//void assign_grads()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_b[i] -= (fc2_db[i] / minibatch);
// fc2_db[i] = 0;
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// {
// fc2_w[i][j] -= (fc2_dw[i][j] / minibatch);
// fc2_dw[i][j] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_b[i] -= (fc1_db[i] / minibatch);
// fc1_db[i] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// {
// fc1_w[i][j][k][l] -= (fc1_dw[i][j][k][l] / minibatch);
// fc1_dw[i][j][k][l] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_b[i] -= (conv_db[i] / minibatch);
// conv_db[i] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// {
// conv_w[i][l][m] -= (conv_dw[i][l][m] / minibatch);
// conv_dw[i][l][m] = 0;
// }
//}
//
//float get_rand(float fan_in)
//{
// float sum = 0;
// for (int i = 0;i < 12;i++)
// sum += (float)rand() / RAND_MAX;
// sum -= 6;
// sum *= 1 / sqrt(fan_in);
// return sum;
//}
//void init_params()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// conv_w[i][j][k] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// conv_b[i] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_w[i][j][k][l] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// fc1_b[i] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// {
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_w[i][j] = get_rand(FC1_SIZE);
// fc2_b[i] = get_rand(FC1_SIZE);
// }
//}
//int main() {
//
// load_data();
// clock_t t = clock();
// init_params();
//
// for (int i = 1;i <= epochs;i++)
// {
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TRAIN_NUM;j++)
// {
// set_input(j, train_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, train_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// update_fc2_b();
// update_fc2_w();
// update_fc1_b();
// update_fc1_w();
// update_conv_b();
// update_conv_w();
// if ((j + 1) % minibatch == 0)
// assign_grads();
//
// if (j && j % 100 == 0)
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100, i);
// }
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TRAIN_NUM, ((float)correct_cnt / TRAIN_NUM) * 100, (avg_error / TRAIN_NUM) * 100, i);
//
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TEST_NUM;j++)
// {
// set_input(j, test_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, test_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// if (j && j % 100 == 0)
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100);
// }
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TEST_NUM, ((float)correct_cnt / TEST_NUM) * 100, (avg_error / TEST_NUM) * 100);
//
// if ((float)correct_cnt / TEST_NUM * 100 > max_acc)
// {
// max_acc = (float)correct_cnt / TEST_NUM * 100;
// //export_params();
// printf("The new model has been exported.Accuracy has reached to %0.5f%%\n\n", max_acc);
// }
// else
// {
// alpha = alpha - (alpha / 3);
// printf("Learning rate has been reduced to %f\n\n", alpha);
// }
// }
//
//
//
// //float train_image[ROW][COL] = {
// //{ 3, 1, 2, 4, 3, 3 },
// //{ 2, 4, 3, 1, 1, 4 },
// //{ 1, 5, 2, 3, 2, 5 },
// //{ 2, 3, 4, 1, 4, 1 },
// //{ 1, 4, 2, 1, 2, 3 },
// //{ 2, 3, 6, 5, 4, 1 }, };
// //float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE] = { {
// //{1, 2, 3},
// //{4, 3, 1},
// //{1, 2, 4}},
// //{{4, 2, 5},
// //{2, 3, 1},
// //{1, 2, 3}} };
//
// ////float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
// //float conv_z[2][2][2];
// //float train_label[2] = { 3,2 };
//
// //cudaMemcpyToSymbol(_train_image, train_image, ROW * COL * sizeof(float));
// //cudaMemcpyToSymbol(_conv_w, conv_w, CONV_W_NUM * CONV_W_SIZE * CONV_W_SIZE * sizeof(float));
// ////cudaMemcpy(_train_label, train_label, 2 * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_train_image, train_image, ROW * COL * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_conv_w, conv_w, CONV_W_NUM*CONV_W_SIZE*CONV_W_SIZE*sizeof(float), cudaMemcpyHostToDevice);
// //dim3 grid2(2, 4, 4);
//
// ////_input_conv << <1, grid2>> > ((float (*)[4])_train_image, (float (*)[3][3])_conv_w, (float (*)[2][2])_conv_z);
// //_input_conv << <1, grid2 >> > ();
// //_conv_pool << <1, grid2 >> > ();
// ////cudaMemcpyFromSymbol(&conv_z, _pool, CONV_W_NUM * CONV_SIZE * CONV_SIZE * sizeof(float));
// //cudaMemcpyFromSymbol(&conv_z, _pool, 8 * sizeof(float));
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j <2;j++) {
// // cout << conv_z[0][i][j] << " ";
// // }
// // cout << endl;
// //}
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j < 2;j++) {
// // cout << conv_z[1][i][j] << " ";
// // }
// // cout << endl;
// //}
// return 0;
//}
|
.file "tmpxft_000d62e8_00000000-6_MyCNNCpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//#pragma comment (lib, "cublas.lib")
//#include "stdio.h"
//#include <cuda.h>
//using namespace std;
//#include <ctime>
//#include "cuda_runtime.h"
//#include "curand_kernel.h"
//#include "device_launch_parameters.h"
//#include <stdio.h>
//#include <stdlib.h>
//
//#include <string>
//#include <iomanip>
//#include <time.h>
//#include <iostream>
//#include <cmath>
//#include <math.h>
//
//#define TRAIN_NUM 60000
//#define TEST_NUM 10000
//#define ROW 28
//#define COL 28
//#define CONV_SIZE 24
//#define POOL_SIZE 12
//#define FC1_SIZE 5
//#define FC2_SIZE 10
//#define CONV_W_SIZE 5
//#define CONV_W_NUM 6
//
//int correct_cnt;
//float avg_error;
//float max_acc;
//
//float alpha = 0.2;
//int epochs = 5;
//int minibatch = 1;
//
//float train_image[TRAIN_NUM][ROW][COL];
//int train_label[TRAIN_NUM];
//float test_image[TEST_NUM][ROW][COL];
//int test_label[TEST_NUM];
//
//float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_b[CONV_W_NUM];
//float fc1_b[FC1_SIZE];
//float fc1_w[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_b[FC2_SIZE];
//float fc2_w[FC2_SIZE][FC1_SIZE];
//
//float input[ROW][COL];
//float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//float conv_a[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//int pool_pos[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float pool[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc1_z[FC1_SIZE];
//float fc1_a[FC1_SIZE];
//float fc2_z[FC2_SIZE];
//float fc2_a[FC2_SIZE];
//float output[FC2_SIZE];
//int answer[FC2_SIZE];
//
//float conv_dw[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_db[CONV_W_NUM];
//float fc1_db[FC1_SIZE];
//float fc1_dw[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_db[FC2_SIZE];
//float fc2_dw[FC2_SIZE][FC1_SIZE];
//float C[FC2_SIZE];
//float fc2_delta[FC2_SIZE];
//float fc1_delta[FC1_SIZE];
//float conv_sigma_delta[CONV_W_NUM];
//float conv_delta[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//
//int swap_endian(int val)
//{
// unsigned char c1, c2, c3, c4;
// c1 = val & 255;
// c2 = (val >> 8) & 255;
// c3 = (val >> 16) & 255;
// c4 = (val >> 24) & 255;
// return ((int)c1 << 24) + ((int)c2 << 16) + ((int)c3 << 8) + c4;
//}
//void load_data()
//{
// FILE* f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-images.idx3-ubyte", "rb");
// FILE* f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-labels.idx1-ubyte", "rb");
//
// int tmp;
//
// int magic_num;
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// // printf("debug:%d\n",swap_endian(magic_num));
//
// int train_size;
// fread(&train_size, sizeof(int), 1, f_images);
// fread(&train_size, sizeof(int), 1, f_labels);
// train_size = swap_endian(train_size);
//
// // printf("debug:%d\n",swap_endian(train_size));
//
// int rows, cols;
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// // printf("debug:%d\n",swap_endian(rows));
// // printf("debug:%d\n",swap_endian(cols));
//
// for (int i = 0;i < train_size;i++)
// {
// fread(&train_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Training labels : Already read %5d labels\r", i);
// // printf("%d:debug:%d\r",i,train_label[i]);
// // system("pause");
// }
// printf("Training labels : Already read %5d labels\n", train_size);
//
// for (int i = 0;i < train_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// train_image[i][j][k] = tmp;
// train_image[i][j][k] /= 255;
// // printf("%d %d %d debug: %f\n",i,j,k,train_image[i][j][k]);
// // system("pause");
// }
// if (i % 1000 == 0)
// printf("Training images : Already read %5d images\r", i);
// }
// printf("Training images : Already read %5d images\n", train_size);
//
// fclose(f_images);
// fclose(f_labels);
//
// f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-images.idx3-ubyte", "rb");
// f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-labels.idx1-ubyte", "rb");
//
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// int test_size;
// fread(&test_size, sizeof(int), 1, f_images);
// fread(&test_size, sizeof(int), 1, f_labels);
// test_size = swap_endian(test_size);
//
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// for (int i = 0;i < test_size;i++)
// {
// fread(&test_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Testing labels : Already read %5d labels\r", i);
// }
// printf("Testing labels : Already read %5d labels\n", test_size);
//
// for (int i = 0;i < test_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// test_image[i][j][k] = tmp;
// test_image[i][j][k] /= 255;
// }
// if (i % 1000 == 0)
// printf("Testing images : Already read %5d images\r", i);
// }
// printf("Testing images : Already read %5d images\n\n", test_size);
//
// fclose(f_images);
// fclose(f_labels);
//}
//
//float sigmoid(float x)
//{
// return (1 / (1 + exp(-1 * x)));
//}
//
//void set_input(int idx, float image[TRAIN_NUM][ROW][COL])
//{
// for (int i = 0;i < ROW;i++)
// for (int j = 0;j < COL;j++)
// input[i][j] = image[idx][i][j];
//}
//
//void input_conv()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_SIZE;j++)
// for (int k = 0;k < CONV_SIZE;k++)
// {
// conv_z[i][j][k] = 0;
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// conv_z[i][j][k] += input[j + l][k + m] * conv_w[i][l][m];
// conv_z[i][j][k] += conv_b[i];
// conv_a[i][j][k] = sigmoid(conv_z[i][j][k]);
// }
//}
//
//void conv_pool()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float _max = conv_a[i][j * 2][k * 2];
// pool_pos[i][j][k] = 0;
// if (conv_a[i][j * 2][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2][k * 2 + 1];
// pool_pos[i][j][k] = 1;
// }
// if (conv_a[i][j * 2 + 1][k * 2] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2];
// pool_pos[i][j][k] = 2;
// }
// if (conv_a[i][j * 2 + 1][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2 + 1];
// pool_pos[i][j][k] = 3;
// }
// pool[i][j][k] = _max;
// }
//}
//
//void pool_fc1()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_z[i] = 0;
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_z[i] += pool[j][k][l] * fc1_w[i][j][k][l];
// fc1_z[i] += fc1_b[i];
// fc1_a[i] = sigmoid(fc1_z[i]);
// }
//}
//
//void fc1_fc2()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_z[i] = 0;
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_z[i] += fc1_a[j] * fc2_w[i][j];
// fc2_z[i] += fc2_b[i];
// fc2_a[i] = sigmoid(fc2_z[i]);
// }
//}
//
//void set_answer(int idx, int label[TRAIN_NUM])
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// output[i] = fc2_a[i];
// answer[i] = (label[idx] == i) ? 1 : 0;
// }
//}
//
//void check_answer(int& correct_cnt)
//{
// float _max = output[0];
// int max_pos = 0;
// for (int i = 0;i < FC2_SIZE;i++)
// {
// if (_max < output[i])
// {
// _max = output[i];
// max_pos = i;
// }
// }
// if (answer[max_pos])
// correct_cnt++;
//}
//
//void get_error(float& avg_error)
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// C[i] = output[i] - answer[i];
// avg_error += C[i] * C[i] * 0.5;
// }
//}
//
//
//void update_fc2_b()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_delta[i] = alpha * C[i] * (fc2_a[i] * (1.0 - fc2_a[i]));
// fc2_db[i] += fc2_delta[i];
// }
//}
//
//void update_fc2_w()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_dw[i][j] += fc2_delta[i] * fc1_a[j];
//}
//
//void update_fc1_b()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// float error = 0;
// for (int j = 0;j < FC2_SIZE;j++)
// error += fc2_delta[j] * fc2_w[j][i];
// fc1_delta[i] = error * (fc1_a[i] * (1.0 - fc1_a[i]));
// fc1_db[i] += fc1_delta[i];
// }
//}
//
//void update_fc1_w()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_dw[i][j][k][l] += fc1_delta[i] * pool[j][k][l];
//}
//
//void update_conv_b()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_sigma_delta[i] = 0;
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float error = 0;
// conv_delta[i][j][k] = 0;
// for (int l = 0;l < FC1_SIZE;l++)
// error += fc1_delta[l] * fc1_w[l][i][j][k];
// conv_delta[i][j][k] = error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// conv_sigma_delta[i] += error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// }
// conv_db[i] += conv_sigma_delta[i];
// }
//}
//
//void update_conv_w()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// {
// float error = 0;
// for (int m = 0;m < POOL_SIZE;m++)
// for (int n = 0;n < POOL_SIZE;n++)
// {
// int x = pool_pos[i][m][n] / 2;
// int y = pool_pos[i][m][n] % 2;
// error += conv_delta[i][m][n] * input[2 * m + j + x][2 * n + k + y];
// }
// conv_dw[i][j][k] += error;
// }
//}
//
//void assign_grads()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_b[i] -= (fc2_db[i] / minibatch);
// fc2_db[i] = 0;
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// {
// fc2_w[i][j] -= (fc2_dw[i][j] / minibatch);
// fc2_dw[i][j] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_b[i] -= (fc1_db[i] / minibatch);
// fc1_db[i] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// {
// fc1_w[i][j][k][l] -= (fc1_dw[i][j][k][l] / minibatch);
// fc1_dw[i][j][k][l] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_b[i] -= (conv_db[i] / minibatch);
// conv_db[i] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// {
// conv_w[i][l][m] -= (conv_dw[i][l][m] / minibatch);
// conv_dw[i][l][m] = 0;
// }
//}
//
//float get_rand(float fan_in)
//{
// float sum = 0;
// for (int i = 0;i < 12;i++)
// sum += (float)rand() / RAND_MAX;
// sum -= 6;
// sum *= 1 / sqrt(fan_in);
// return sum;
//}
//void init_params()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// conv_w[i][j][k] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// conv_b[i] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_w[i][j][k][l] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// fc1_b[i] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// {
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_w[i][j] = get_rand(FC1_SIZE);
// fc2_b[i] = get_rand(FC1_SIZE);
// }
//}
//int main() {
//
// load_data();
// clock_t t = clock();
// init_params();
//
// for (int i = 1;i <= epochs;i++)
// {
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TRAIN_NUM;j++)
// {
// set_input(j, train_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, train_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// update_fc2_b();
// update_fc2_w();
// update_fc1_b();
// update_fc1_w();
// update_conv_b();
// update_conv_w();
// if ((j + 1) % minibatch == 0)
// assign_grads();
//
// if (j && j % 100 == 0)
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100, i);
// }
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TRAIN_NUM, ((float)correct_cnt / TRAIN_NUM) * 100, (avg_error / TRAIN_NUM) * 100, i);
//
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TEST_NUM;j++)
// {
// set_input(j, test_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, test_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// if (j && j % 100 == 0)
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100);
// }
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TEST_NUM, ((float)correct_cnt / TEST_NUM) * 100, (avg_error / TEST_NUM) * 100);
//
// if ((float)correct_cnt / TEST_NUM * 100 > max_acc)
// {
// max_acc = (float)correct_cnt / TEST_NUM * 100;
// //export_params();
// printf("The new model has been exported.Accuracy has reached to %0.5f%%\n\n", max_acc);
// }
// else
// {
// alpha = alpha - (alpha / 3);
// printf("Learning rate has been reduced to %f\n\n", alpha);
// }
// }
//
//
//
// //float train_image[ROW][COL] = {
// //{ 3, 1, 2, 4, 3, 3 },
// //{ 2, 4, 3, 1, 1, 4 },
// //{ 1, 5, 2, 3, 2, 5 },
// //{ 2, 3, 4, 1, 4, 1 },
// //{ 1, 4, 2, 1, 2, 3 },
// //{ 2, 3, 6, 5, 4, 1 }, };
// //float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE] = { {
// //{1, 2, 3},
// //{4, 3, 1},
// //{1, 2, 4}},
// //{{4, 2, 5},
// //{2, 3, 1},
// //{1, 2, 3}} };
//
// ////float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
// //float conv_z[2][2][2];
// //float train_label[2] = { 3,2 };
//
// //cudaMemcpyToSymbol(_train_image, train_image, ROW * COL * sizeof(float));
// //cudaMemcpyToSymbol(_conv_w, conv_w, CONV_W_NUM * CONV_W_SIZE * CONV_W_SIZE * sizeof(float));
// ////cudaMemcpy(_train_label, train_label, 2 * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_train_image, train_image, ROW * COL * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_conv_w, conv_w, CONV_W_NUM*CONV_W_SIZE*CONV_W_SIZE*sizeof(float), cudaMemcpyHostToDevice);
// //dim3 grid2(2, 4, 4);
//
// ////_input_conv << <1, grid2>> > ((float (*)[4])_train_image, (float (*)[3][3])_conv_w, (float (*)[2][2])_conv_z);
// //_input_conv << <1, grid2 >> > ();
// //_conv_pool << <1, grid2 >> > ();
// ////cudaMemcpyFromSymbol(&conv_z, _pool, CONV_W_NUM * CONV_SIZE * CONV_SIZE * sizeof(float));
// //cudaMemcpyFromSymbol(&conv_z, _pool, 8 * sizeof(float));
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j <2;j++) {
// // cout << conv_z[0][i][j] << " ";
// // }
// // cout << endl;
// //}
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j < 2;j++) {
// // cout << conv_z[1][i][j] << " ";
// // }
// // cout << endl;
// //}
// return 0;
//}
|
#include <hip/hip_runtime.h>
//#pragma comment (lib, "cublas.lib")
//#include "stdio.h"
//#include <cuda.h>
//using namespace std;
//#include <ctime>
//#include "cuda_runtime.h"
//#include "curand_kernel.h"
//#include "device_launch_parameters.h"
//#include <stdio.h>
//#include <stdlib.h>
//
//#include <string>
//#include <iomanip>
//#include <time.h>
//#include <iostream>
//#include <cmath>
//#include <math.h>
//
//#define TRAIN_NUM 60000
//#define TEST_NUM 10000
//#define ROW 28
//#define COL 28
//#define CONV_SIZE 24
//#define POOL_SIZE 12
//#define FC1_SIZE 5
//#define FC2_SIZE 10
//#define CONV_W_SIZE 5
//#define CONV_W_NUM 6
//
//int correct_cnt;
//float avg_error;
//float max_acc;
//
//float alpha = 0.2;
//int epochs = 5;
//int minibatch = 1;
//
//float train_image[TRAIN_NUM][ROW][COL];
//int train_label[TRAIN_NUM];
//float test_image[TEST_NUM][ROW][COL];
//int test_label[TEST_NUM];
//
//float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_b[CONV_W_NUM];
//float fc1_b[FC1_SIZE];
//float fc1_w[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_b[FC2_SIZE];
//float fc2_w[FC2_SIZE][FC1_SIZE];
//
//float input[ROW][COL];
//float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//float conv_a[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//int pool_pos[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float pool[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc1_z[FC1_SIZE];
//float fc1_a[FC1_SIZE];
//float fc2_z[FC2_SIZE];
//float fc2_a[FC2_SIZE];
//float output[FC2_SIZE];
//int answer[FC2_SIZE];
//
//float conv_dw[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_db[CONV_W_NUM];
//float fc1_db[FC1_SIZE];
//float fc1_dw[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_db[FC2_SIZE];
//float fc2_dw[FC2_SIZE][FC1_SIZE];
//float C[FC2_SIZE];
//float fc2_delta[FC2_SIZE];
//float fc1_delta[FC1_SIZE];
//float conv_sigma_delta[CONV_W_NUM];
//float conv_delta[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//
//int swap_endian(int val)
//{
// unsigned char c1, c2, c3, c4;
// c1 = val & 255;
// c2 = (val >> 8) & 255;
// c3 = (val >> 16) & 255;
// c4 = (val >> 24) & 255;
// return ((int)c1 << 24) + ((int)c2 << 16) + ((int)c3 << 8) + c4;
//}
//void load_data()
//{
// FILE* f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-images.idx3-ubyte", "rb");
// FILE* f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-labels.idx1-ubyte", "rb");
//
// int tmp;
//
// int magic_num;
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// // printf("debug:%d\n",swap_endian(magic_num));
//
// int train_size;
// fread(&train_size, sizeof(int), 1, f_images);
// fread(&train_size, sizeof(int), 1, f_labels);
// train_size = swap_endian(train_size);
//
// // printf("debug:%d\n",swap_endian(train_size));
//
// int rows, cols;
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// // printf("debug:%d\n",swap_endian(rows));
// // printf("debug:%d\n",swap_endian(cols));
//
// for (int i = 0;i < train_size;i++)
// {
// fread(&train_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Training labels : Already read %5d labels\r", i);
// // printf("%d:debug:%d\r",i,train_label[i]);
// // system("pause");
// }
// printf("Training labels : Already read %5d labels\n", train_size);
//
// for (int i = 0;i < train_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// train_image[i][j][k] = tmp;
// train_image[i][j][k] /= 255;
// // printf("%d %d %d debug: %f\n",i,j,k,train_image[i][j][k]);
// // system("pause");
// }
// if (i % 1000 == 0)
// printf("Training images : Already read %5d images\r", i);
// }
// printf("Training images : Already read %5d images\n", train_size);
//
// fclose(f_images);
// fclose(f_labels);
//
// f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-images.idx3-ubyte", "rb");
// f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-labels.idx1-ubyte", "rb");
//
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// int test_size;
// fread(&test_size, sizeof(int), 1, f_images);
// fread(&test_size, sizeof(int), 1, f_labels);
// test_size = swap_endian(test_size);
//
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// for (int i = 0;i < test_size;i++)
// {
// fread(&test_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Testing labels : Already read %5d labels\r", i);
// }
// printf("Testing labels : Already read %5d labels\n", test_size);
//
// for (int i = 0;i < test_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// test_image[i][j][k] = tmp;
// test_image[i][j][k] /= 255;
// }
// if (i % 1000 == 0)
// printf("Testing images : Already read %5d images\r", i);
// }
// printf("Testing images : Already read %5d images\n\n", test_size);
//
// fclose(f_images);
// fclose(f_labels);
//}
//
//float sigmoid(float x)
//{
// return (1 / (1 + exp(-1 * x)));
//}
//
//void set_input(int idx, float image[TRAIN_NUM][ROW][COL])
//{
// for (int i = 0;i < ROW;i++)
// for (int j = 0;j < COL;j++)
// input[i][j] = image[idx][i][j];
//}
//
//void input_conv()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_SIZE;j++)
// for (int k = 0;k < CONV_SIZE;k++)
// {
// conv_z[i][j][k] = 0;
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// conv_z[i][j][k] += input[j + l][k + m] * conv_w[i][l][m];
// conv_z[i][j][k] += conv_b[i];
// conv_a[i][j][k] = sigmoid(conv_z[i][j][k]);
// }
//}
//
//void conv_pool()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float _max = conv_a[i][j * 2][k * 2];
// pool_pos[i][j][k] = 0;
// if (conv_a[i][j * 2][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2][k * 2 + 1];
// pool_pos[i][j][k] = 1;
// }
// if (conv_a[i][j * 2 + 1][k * 2] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2];
// pool_pos[i][j][k] = 2;
// }
// if (conv_a[i][j * 2 + 1][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2 + 1];
// pool_pos[i][j][k] = 3;
// }
// pool[i][j][k] = _max;
// }
//}
//
//void pool_fc1()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_z[i] = 0;
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_z[i] += pool[j][k][l] * fc1_w[i][j][k][l];
// fc1_z[i] += fc1_b[i];
// fc1_a[i] = sigmoid(fc1_z[i]);
// }
//}
//
//void fc1_fc2()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_z[i] = 0;
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_z[i] += fc1_a[j] * fc2_w[i][j];
// fc2_z[i] += fc2_b[i];
// fc2_a[i] = sigmoid(fc2_z[i]);
// }
//}
//
//void set_answer(int idx, int label[TRAIN_NUM])
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// output[i] = fc2_a[i];
// answer[i] = (label[idx] == i) ? 1 : 0;
// }
//}
//
//void check_answer(int& correct_cnt)
//{
// float _max = output[0];
// int max_pos = 0;
// for (int i = 0;i < FC2_SIZE;i++)
// {
// if (_max < output[i])
// {
// _max = output[i];
// max_pos = i;
// }
// }
// if (answer[max_pos])
// correct_cnt++;
//}
//
//void get_error(float& avg_error)
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// C[i] = output[i] - answer[i];
// avg_error += C[i] * C[i] * 0.5;
// }
//}
//
//
//void update_fc2_b()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_delta[i] = alpha * C[i] * (fc2_a[i] * (1.0 - fc2_a[i]));
// fc2_db[i] += fc2_delta[i];
// }
//}
//
//void update_fc2_w()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_dw[i][j] += fc2_delta[i] * fc1_a[j];
//}
//
//void update_fc1_b()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// float error = 0;
// for (int j = 0;j < FC2_SIZE;j++)
// error += fc2_delta[j] * fc2_w[j][i];
// fc1_delta[i] = error * (fc1_a[i] * (1.0 - fc1_a[i]));
// fc1_db[i] += fc1_delta[i];
// }
//}
//
//void update_fc1_w()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_dw[i][j][k][l] += fc1_delta[i] * pool[j][k][l];
//}
//
//void update_conv_b()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_sigma_delta[i] = 0;
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float error = 0;
// conv_delta[i][j][k] = 0;
// for (int l = 0;l < FC1_SIZE;l++)
// error += fc1_delta[l] * fc1_w[l][i][j][k];
// conv_delta[i][j][k] = error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// conv_sigma_delta[i] += error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// }
// conv_db[i] += conv_sigma_delta[i];
// }
//}
//
//void update_conv_w()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// {
// float error = 0;
// for (int m = 0;m < POOL_SIZE;m++)
// for (int n = 0;n < POOL_SIZE;n++)
// {
// int x = pool_pos[i][m][n] / 2;
// int y = pool_pos[i][m][n] % 2;
// error += conv_delta[i][m][n] * input[2 * m + j + x][2 * n + k + y];
// }
// conv_dw[i][j][k] += error;
// }
//}
//
//void assign_grads()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_b[i] -= (fc2_db[i] / minibatch);
// fc2_db[i] = 0;
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// {
// fc2_w[i][j] -= (fc2_dw[i][j] / minibatch);
// fc2_dw[i][j] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_b[i] -= (fc1_db[i] / minibatch);
// fc1_db[i] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// {
// fc1_w[i][j][k][l] -= (fc1_dw[i][j][k][l] / minibatch);
// fc1_dw[i][j][k][l] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_b[i] -= (conv_db[i] / minibatch);
// conv_db[i] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// {
// conv_w[i][l][m] -= (conv_dw[i][l][m] / minibatch);
// conv_dw[i][l][m] = 0;
// }
//}
//
//float get_rand(float fan_in)
//{
// float sum = 0;
// for (int i = 0;i < 12;i++)
// sum += (float)rand() / RAND_MAX;
// sum -= 6;
// sum *= 1 / sqrt(fan_in);
// return sum;
//}
//void init_params()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// conv_w[i][j][k] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// conv_b[i] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_w[i][j][k][l] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// fc1_b[i] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// {
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_w[i][j] = get_rand(FC1_SIZE);
// fc2_b[i] = get_rand(FC1_SIZE);
// }
//}
//int main() {
//
// load_data();
// clock_t t = clock();
// init_params();
//
// for (int i = 1;i <= epochs;i++)
// {
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TRAIN_NUM;j++)
// {
// set_input(j, train_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, train_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// update_fc2_b();
// update_fc2_w();
// update_fc1_b();
// update_fc1_w();
// update_conv_b();
// update_conv_w();
// if ((j + 1) % minibatch == 0)
// assign_grads();
//
// if (j && j % 100 == 0)
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100, i);
// }
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TRAIN_NUM, ((float)correct_cnt / TRAIN_NUM) * 100, (avg_error / TRAIN_NUM) * 100, i);
//
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TEST_NUM;j++)
// {
// set_input(j, test_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, test_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// if (j && j % 100 == 0)
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100);
// }
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TEST_NUM, ((float)correct_cnt / TEST_NUM) * 100, (avg_error / TEST_NUM) * 100);
//
// if ((float)correct_cnt / TEST_NUM * 100 > max_acc)
// {
// max_acc = (float)correct_cnt / TEST_NUM * 100;
// //export_params();
// printf("The new model has been exported.Accuracy has reached to %0.5f%%\n\n", max_acc);
// }
// else
// {
// alpha = alpha - (alpha / 3);
// printf("Learning rate has been reduced to %f\n\n", alpha);
// }
// }
//
//
//
// //float train_image[ROW][COL] = {
// //{ 3, 1, 2, 4, 3, 3 },
// //{ 2, 4, 3, 1, 1, 4 },
// //{ 1, 5, 2, 3, 2, 5 },
// //{ 2, 3, 4, 1, 4, 1 },
// //{ 1, 4, 2, 1, 2, 3 },
// //{ 2, 3, 6, 5, 4, 1 }, };
// //float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE] = { {
// //{1, 2, 3},
// //{4, 3, 1},
// //{1, 2, 4}},
// //{{4, 2, 5},
// //{2, 3, 1},
// //{1, 2, 3}} };
//
// ////float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
// //float conv_z[2][2][2];
// //float train_label[2] = { 3,2 };
//
// //cudaMemcpyToSymbol(_train_image, train_image, ROW * COL * sizeof(float));
// //cudaMemcpyToSymbol(_conv_w, conv_w, CONV_W_NUM * CONV_W_SIZE * CONV_W_SIZE * sizeof(float));
// ////cudaMemcpy(_train_label, train_label, 2 * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_train_image, train_image, ROW * COL * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_conv_w, conv_w, CONV_W_NUM*CONV_W_SIZE*CONV_W_SIZE*sizeof(float), cudaMemcpyHostToDevice);
// //dim3 grid2(2, 4, 4);
//
// ////_input_conv << <1, grid2>> > ((float (*)[4])_train_image, (float (*)[3][3])_conv_w, (float (*)[2][2])_conv_z);
// //_input_conv << <1, grid2 >> > ();
// //_conv_pool << <1, grid2 >> > ();
// ////cudaMemcpyFromSymbol(&conv_z, _pool, CONV_W_NUM * CONV_SIZE * CONV_SIZE * sizeof(float));
// //cudaMemcpyFromSymbol(&conv_z, _pool, 8 * sizeof(float));
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j <2;j++) {
// // cout << conv_z[0][i][j] << " ";
// // }
// // cout << endl;
// //}
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j < 2;j++) {
// // cout << conv_z[1][i][j] << " ";
// // }
// // cout << endl;
// //}
// return 0;
//}
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You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
//#pragma comment (lib, "cublas.lib")
//#include "stdio.h"
//#include <cuda.h>
//using namespace std;
//#include <ctime>
//#include "cuda_runtime.h"
//#include "curand_kernel.h"
//#include "device_launch_parameters.h"
//#include <stdio.h>
//#include <stdlib.h>
//
//#include <string>
//#include <iomanip>
//#include <time.h>
//#include <iostream>
//#include <cmath>
//#include <math.h>
//
//#define TRAIN_NUM 60000
//#define TEST_NUM 10000
//#define ROW 28
//#define COL 28
//#define CONV_SIZE 24
//#define POOL_SIZE 12
//#define FC1_SIZE 5
//#define FC2_SIZE 10
//#define CONV_W_SIZE 5
//#define CONV_W_NUM 6
//
//int correct_cnt;
//float avg_error;
//float max_acc;
//
//float alpha = 0.2;
//int epochs = 5;
//int minibatch = 1;
//
//float train_image[TRAIN_NUM][ROW][COL];
//int train_label[TRAIN_NUM];
//float test_image[TEST_NUM][ROW][COL];
//int test_label[TEST_NUM];
//
//float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_b[CONV_W_NUM];
//float fc1_b[FC1_SIZE];
//float fc1_w[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_b[FC2_SIZE];
//float fc2_w[FC2_SIZE][FC1_SIZE];
//
//float input[ROW][COL];
//float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//float conv_a[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//int pool_pos[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float pool[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc1_z[FC1_SIZE];
//float fc1_a[FC1_SIZE];
//float fc2_z[FC2_SIZE];
//float fc2_a[FC2_SIZE];
//float output[FC2_SIZE];
//int answer[FC2_SIZE];
//
//float conv_dw[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_db[CONV_W_NUM];
//float fc1_db[FC1_SIZE];
//float fc1_dw[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_db[FC2_SIZE];
//float fc2_dw[FC2_SIZE][FC1_SIZE];
//float C[FC2_SIZE];
//float fc2_delta[FC2_SIZE];
//float fc1_delta[FC1_SIZE];
//float conv_sigma_delta[CONV_W_NUM];
//float conv_delta[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//
//int swap_endian(int val)
//{
// unsigned char c1, c2, c3, c4;
// c1 = val & 255;
// c2 = (val >> 8) & 255;
// c3 = (val >> 16) & 255;
// c4 = (val >> 24) & 255;
// return ((int)c1 << 24) + ((int)c2 << 16) + ((int)c3 << 8) + c4;
//}
//void load_data()
//{
// FILE* f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-images.idx3-ubyte", "rb");
// FILE* f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-labels.idx1-ubyte", "rb");
//
// int tmp;
//
// int magic_num;
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// // printf("debug:%d\n",swap_endian(magic_num));
//
// int train_size;
// fread(&train_size, sizeof(int), 1, f_images);
// fread(&train_size, sizeof(int), 1, f_labels);
// train_size = swap_endian(train_size);
//
// // printf("debug:%d\n",swap_endian(train_size));
//
// int rows, cols;
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// // printf("debug:%d\n",swap_endian(rows));
// // printf("debug:%d\n",swap_endian(cols));
//
// for (int i = 0;i < train_size;i++)
// {
// fread(&train_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Training labels : Already read %5d labels\r", i);
// // printf("%d:debug:%d\r",i,train_label[i]);
// // system("pause");
// }
// printf("Training labels : Already read %5d labels\n", train_size);
//
// for (int i = 0;i < train_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// train_image[i][j][k] = tmp;
// train_image[i][j][k] /= 255;
// // printf("%d %d %d debug: %f\n",i,j,k,train_image[i][j][k]);
// // system("pause");
// }
// if (i % 1000 == 0)
// printf("Training images : Already read %5d images\r", i);
// }
// printf("Training images : Already read %5d images\n", train_size);
//
// fclose(f_images);
// fclose(f_labels);
//
// f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-images.idx3-ubyte", "rb");
// f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-labels.idx1-ubyte", "rb");
//
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// int test_size;
// fread(&test_size, sizeof(int), 1, f_images);
// fread(&test_size, sizeof(int), 1, f_labels);
// test_size = swap_endian(test_size);
//
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// for (int i = 0;i < test_size;i++)
// {
// fread(&test_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Testing labels : Already read %5d labels\r", i);
// }
// printf("Testing labels : Already read %5d labels\n", test_size);
//
// for (int i = 0;i < test_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// test_image[i][j][k] = tmp;
// test_image[i][j][k] /= 255;
// }
// if (i % 1000 == 0)
// printf("Testing images : Already read %5d images\r", i);
// }
// printf("Testing images : Already read %5d images\n\n", test_size);
//
// fclose(f_images);
// fclose(f_labels);
//}
//
//float sigmoid(float x)
//{
// return (1 / (1 + exp(-1 * x)));
//}
//
//void set_input(int idx, float image[TRAIN_NUM][ROW][COL])
//{
// for (int i = 0;i < ROW;i++)
// for (int j = 0;j < COL;j++)
// input[i][j] = image[idx][i][j];
//}
//
//void input_conv()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_SIZE;j++)
// for (int k = 0;k < CONV_SIZE;k++)
// {
// conv_z[i][j][k] = 0;
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// conv_z[i][j][k] += input[j + l][k + m] * conv_w[i][l][m];
// conv_z[i][j][k] += conv_b[i];
// conv_a[i][j][k] = sigmoid(conv_z[i][j][k]);
// }
//}
//
//void conv_pool()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float _max = conv_a[i][j * 2][k * 2];
// pool_pos[i][j][k] = 0;
// if (conv_a[i][j * 2][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2][k * 2 + 1];
// pool_pos[i][j][k] = 1;
// }
// if (conv_a[i][j * 2 + 1][k * 2] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2];
// pool_pos[i][j][k] = 2;
// }
// if (conv_a[i][j * 2 + 1][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2 + 1];
// pool_pos[i][j][k] = 3;
// }
// pool[i][j][k] = _max;
// }
//}
//
//void pool_fc1()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_z[i] = 0;
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_z[i] += pool[j][k][l] * fc1_w[i][j][k][l];
// fc1_z[i] += fc1_b[i];
// fc1_a[i] = sigmoid(fc1_z[i]);
// }
//}
//
//void fc1_fc2()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_z[i] = 0;
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_z[i] += fc1_a[j] * fc2_w[i][j];
// fc2_z[i] += fc2_b[i];
// fc2_a[i] = sigmoid(fc2_z[i]);
// }
//}
//
//void set_answer(int idx, int label[TRAIN_NUM])
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// output[i] = fc2_a[i];
// answer[i] = (label[idx] == i) ? 1 : 0;
// }
//}
//
//void check_answer(int& correct_cnt)
//{
// float _max = output[0];
// int max_pos = 0;
// for (int i = 0;i < FC2_SIZE;i++)
// {
// if (_max < output[i])
// {
// _max = output[i];
// max_pos = i;
// }
// }
// if (answer[max_pos])
// correct_cnt++;
//}
//
//void get_error(float& avg_error)
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// C[i] = output[i] - answer[i];
// avg_error += C[i] * C[i] * 0.5;
// }
//}
//
//
//void update_fc2_b()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_delta[i] = alpha * C[i] * (fc2_a[i] * (1.0 - fc2_a[i]));
// fc2_db[i] += fc2_delta[i];
// }
//}
//
//void update_fc2_w()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_dw[i][j] += fc2_delta[i] * fc1_a[j];
//}
//
//void update_fc1_b()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// float error = 0;
// for (int j = 0;j < FC2_SIZE;j++)
// error += fc2_delta[j] * fc2_w[j][i];
// fc1_delta[i] = error * (fc1_a[i] * (1.0 - fc1_a[i]));
// fc1_db[i] += fc1_delta[i];
// }
//}
//
//void update_fc1_w()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_dw[i][j][k][l] += fc1_delta[i] * pool[j][k][l];
//}
//
//void update_conv_b()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_sigma_delta[i] = 0;
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float error = 0;
// conv_delta[i][j][k] = 0;
// for (int l = 0;l < FC1_SIZE;l++)
// error += fc1_delta[l] * fc1_w[l][i][j][k];
// conv_delta[i][j][k] = error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// conv_sigma_delta[i] += error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// }
// conv_db[i] += conv_sigma_delta[i];
// }
//}
//
//void update_conv_w()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// {
// float error = 0;
// for (int m = 0;m < POOL_SIZE;m++)
// for (int n = 0;n < POOL_SIZE;n++)
// {
// int x = pool_pos[i][m][n] / 2;
// int y = pool_pos[i][m][n] % 2;
// error += conv_delta[i][m][n] * input[2 * m + j + x][2 * n + k + y];
// }
// conv_dw[i][j][k] += error;
// }
//}
//
//void assign_grads()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_b[i] -= (fc2_db[i] / minibatch);
// fc2_db[i] = 0;
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// {
// fc2_w[i][j] -= (fc2_dw[i][j] / minibatch);
// fc2_dw[i][j] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_b[i] -= (fc1_db[i] / minibatch);
// fc1_db[i] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// {
// fc1_w[i][j][k][l] -= (fc1_dw[i][j][k][l] / minibatch);
// fc1_dw[i][j][k][l] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_b[i] -= (conv_db[i] / minibatch);
// conv_db[i] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// {
// conv_w[i][l][m] -= (conv_dw[i][l][m] / minibatch);
// conv_dw[i][l][m] = 0;
// }
//}
//
//float get_rand(float fan_in)
//{
// float sum = 0;
// for (int i = 0;i < 12;i++)
// sum += (float)rand() / RAND_MAX;
// sum -= 6;
// sum *= 1 / sqrt(fan_in);
// return sum;
//}
//void init_params()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// conv_w[i][j][k] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// conv_b[i] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_w[i][j][k][l] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// fc1_b[i] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// {
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_w[i][j] = get_rand(FC1_SIZE);
// fc2_b[i] = get_rand(FC1_SIZE);
// }
//}
//int main() {
//
// load_data();
// clock_t t = clock();
// init_params();
//
// for (int i = 1;i <= epochs;i++)
// {
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TRAIN_NUM;j++)
// {
// set_input(j, train_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, train_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// update_fc2_b();
// update_fc2_w();
// update_fc1_b();
// update_fc1_w();
// update_conv_b();
// update_conv_w();
// if ((j + 1) % minibatch == 0)
// assign_grads();
//
// if (j && j % 100 == 0)
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100, i);
// }
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TRAIN_NUM, ((float)correct_cnt / TRAIN_NUM) * 100, (avg_error / TRAIN_NUM) * 100, i);
//
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TEST_NUM;j++)
// {
// set_input(j, test_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, test_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// if (j && j % 100 == 0)
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100);
// }
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TEST_NUM, ((float)correct_cnt / TEST_NUM) * 100, (avg_error / TEST_NUM) * 100);
//
// if ((float)correct_cnt / TEST_NUM * 100 > max_acc)
// {
// max_acc = (float)correct_cnt / TEST_NUM * 100;
// //export_params();
// printf("The new model has been exported.Accuracy has reached to %0.5f%%\n\n", max_acc);
// }
// else
// {
// alpha = alpha - (alpha / 3);
// printf("Learning rate has been reduced to %f\n\n", alpha);
// }
// }
//
//
//
// //float train_image[ROW][COL] = {
// //{ 3, 1, 2, 4, 3, 3 },
// //{ 2, 4, 3, 1, 1, 4 },
// //{ 1, 5, 2, 3, 2, 5 },
// //{ 2, 3, 4, 1, 4, 1 },
// //{ 1, 4, 2, 1, 2, 3 },
// //{ 2, 3, 6, 5, 4, 1 }, };
// //float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE] = { {
// //{1, 2, 3},
// //{4, 3, 1},
// //{1, 2, 4}},
// //{{4, 2, 5},
// //{2, 3, 1},
// //{1, 2, 3}} };
//
// ////float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
// //float conv_z[2][2][2];
// //float train_label[2] = { 3,2 };
//
// //cudaMemcpyToSymbol(_train_image, train_image, ROW * COL * sizeof(float));
// //cudaMemcpyToSymbol(_conv_w, conv_w, CONV_W_NUM * CONV_W_SIZE * CONV_W_SIZE * sizeof(float));
// ////cudaMemcpy(_train_label, train_label, 2 * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_train_image, train_image, ROW * COL * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_conv_w, conv_w, CONV_W_NUM*CONV_W_SIZE*CONV_W_SIZE*sizeof(float), cudaMemcpyHostToDevice);
// //dim3 grid2(2, 4, 4);
//
// ////_input_conv << <1, grid2>> > ((float (*)[4])_train_image, (float (*)[3][3])_conv_w, (float (*)[2][2])_conv_z);
// //_input_conv << <1, grid2 >> > ();
// //_conv_pool << <1, grid2 >> > ();
// ////cudaMemcpyFromSymbol(&conv_z, _pool, CONV_W_NUM * CONV_SIZE * CONV_SIZE * sizeof(float));
// //cudaMemcpyFromSymbol(&conv_z, _pool, 8 * sizeof(float));
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j <2;j++) {
// // cout << conv_z[0][i][j] << " ";
// // }
// // cout << endl;
// //}
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j < 2;j++) {
// // cout << conv_z[1][i][j] << " ";
// // }
// // cout << endl;
// //}
// return 0;
//}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
//#pragma comment (lib, "cublas.lib")
//#include "stdio.h"
//#include <cuda.h>
//using namespace std;
//#include <ctime>
//#include "cuda_runtime.h"
//#include "curand_kernel.h"
//#include "device_launch_parameters.h"
//#include <stdio.h>
//#include <stdlib.h>
//
//#include <string>
//#include <iomanip>
//#include <time.h>
//#include <iostream>
//#include <cmath>
//#include <math.h>
//
//#define TRAIN_NUM 60000
//#define TEST_NUM 10000
//#define ROW 28
//#define COL 28
//#define CONV_SIZE 24
//#define POOL_SIZE 12
//#define FC1_SIZE 5
//#define FC2_SIZE 10
//#define CONV_W_SIZE 5
//#define CONV_W_NUM 6
//
//int correct_cnt;
//float avg_error;
//float max_acc;
//
//float alpha = 0.2;
//int epochs = 5;
//int minibatch = 1;
//
//float train_image[TRAIN_NUM][ROW][COL];
//int train_label[TRAIN_NUM];
//float test_image[TEST_NUM][ROW][COL];
//int test_label[TEST_NUM];
//
//float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_b[CONV_W_NUM];
//float fc1_b[FC1_SIZE];
//float fc1_w[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_b[FC2_SIZE];
//float fc2_w[FC2_SIZE][FC1_SIZE];
//
//float input[ROW][COL];
//float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//float conv_a[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
//int pool_pos[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float pool[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc1_z[FC1_SIZE];
//float fc1_a[FC1_SIZE];
//float fc2_z[FC2_SIZE];
//float fc2_a[FC2_SIZE];
//float output[FC2_SIZE];
//int answer[FC2_SIZE];
//
//float conv_dw[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE];
//float conv_db[CONV_W_NUM];
//float fc1_db[FC1_SIZE];
//float fc1_dw[FC1_SIZE][CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//float fc2_db[FC2_SIZE];
//float fc2_dw[FC2_SIZE][FC1_SIZE];
//float C[FC2_SIZE];
//float fc2_delta[FC2_SIZE];
//float fc1_delta[FC1_SIZE];
//float conv_sigma_delta[CONV_W_NUM];
//float conv_delta[CONV_W_NUM][POOL_SIZE][POOL_SIZE];
//
//int swap_endian(int val)
//{
// unsigned char c1, c2, c3, c4;
// c1 = val & 255;
// c2 = (val >> 8) & 255;
// c3 = (val >> 16) & 255;
// c4 = (val >> 24) & 255;
// return ((int)c1 << 24) + ((int)c2 << 16) + ((int)c3 << 8) + c4;
//}
//void load_data()
//{
// FILE* f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-images.idx3-ubyte", "rb");
// FILE* f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\train-labels.idx1-ubyte", "rb");
//
// int tmp;
//
// int magic_num;
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// // printf("debug:%d\n",swap_endian(magic_num));
//
// int train_size;
// fread(&train_size, sizeof(int), 1, f_images);
// fread(&train_size, sizeof(int), 1, f_labels);
// train_size = swap_endian(train_size);
//
// // printf("debug:%d\n",swap_endian(train_size));
//
// int rows, cols;
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// // printf("debug:%d\n",swap_endian(rows));
// // printf("debug:%d\n",swap_endian(cols));
//
// for (int i = 0;i < train_size;i++)
// {
// fread(&train_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Training labels : Already read %5d labels\r", i);
// // printf("%d:debug:%d\r",i,train_label[i]);
// // system("pause");
// }
// printf("Training labels : Already read %5d labels\n", train_size);
//
// for (int i = 0;i < train_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// train_image[i][j][k] = tmp;
// train_image[i][j][k] /= 255;
// // printf("%d %d %d debug: %f\n",i,j,k,train_image[i][j][k]);
// // system("pause");
// }
// if (i % 1000 == 0)
// printf("Training images : Already read %5d images\r", i);
// }
// printf("Training images : Already read %5d images\n", train_size);
//
// fclose(f_images);
// fclose(f_labels);
//
// f_images = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-images.idx3-ubyte", "rb");
// f_labels = fopen("D:\\\\Zufar\\\\CUDA-CNN\\\\CudaCNN2\\\\CudaCNN2\\\\data\\\\t10k-labels.idx1-ubyte", "rb");
//
// fread(&magic_num, sizeof(int), 1, f_images);
// fread(&magic_num, sizeof(int), 1, f_labels);
//
// int test_size;
// fread(&test_size, sizeof(int), 1, f_images);
// fread(&test_size, sizeof(int), 1, f_labels);
// test_size = swap_endian(test_size);
//
// fread(&rows, sizeof(int), 1, f_images);
// fread(&cols, sizeof(int), 1, f_images);
// rows = swap_endian(rows);
// cols = swap_endian(cols);
//
// for (int i = 0;i < test_size;i++)
// {
// fread(&test_label[i], 1, 1, f_labels);
// if (i % 1000 == 0)
// printf("Testing labels : Already read %5d labels\r", i);
// }
// printf("Testing labels : Already read %5d labels\n", test_size);
//
// for (int i = 0;i < test_size;i++)
// {
// for (int j = 0;j < rows;j++)
// for (int k = 0;k < cols;k++)
// {
// tmp = 0;
// fread(&tmp, 1, 1, f_images);
// test_image[i][j][k] = tmp;
// test_image[i][j][k] /= 255;
// }
// if (i % 1000 == 0)
// printf("Testing images : Already read %5d images\r", i);
// }
// printf("Testing images : Already read %5d images\n\n", test_size);
//
// fclose(f_images);
// fclose(f_labels);
//}
//
//float sigmoid(float x)
//{
// return (1 / (1 + exp(-1 * x)));
//}
//
//void set_input(int idx, float image[TRAIN_NUM][ROW][COL])
//{
// for (int i = 0;i < ROW;i++)
// for (int j = 0;j < COL;j++)
// input[i][j] = image[idx][i][j];
//}
//
//void input_conv()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_SIZE;j++)
// for (int k = 0;k < CONV_SIZE;k++)
// {
// conv_z[i][j][k] = 0;
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// conv_z[i][j][k] += input[j + l][k + m] * conv_w[i][l][m];
// conv_z[i][j][k] += conv_b[i];
// conv_a[i][j][k] = sigmoid(conv_z[i][j][k]);
// }
//}
//
//void conv_pool()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float _max = conv_a[i][j * 2][k * 2];
// pool_pos[i][j][k] = 0;
// if (conv_a[i][j * 2][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2][k * 2 + 1];
// pool_pos[i][j][k] = 1;
// }
// if (conv_a[i][j * 2 + 1][k * 2] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2];
// pool_pos[i][j][k] = 2;
// }
// if (conv_a[i][j * 2 + 1][k * 2 + 1] > _max)
// {
// _max = conv_a[i][j * 2 + 1][k * 2 + 1];
// pool_pos[i][j][k] = 3;
// }
// pool[i][j][k] = _max;
// }
//}
//
//void pool_fc1()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_z[i] = 0;
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_z[i] += pool[j][k][l] * fc1_w[i][j][k][l];
// fc1_z[i] += fc1_b[i];
// fc1_a[i] = sigmoid(fc1_z[i]);
// }
//}
//
//void fc1_fc2()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_z[i] = 0;
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_z[i] += fc1_a[j] * fc2_w[i][j];
// fc2_z[i] += fc2_b[i];
// fc2_a[i] = sigmoid(fc2_z[i]);
// }
//}
//
//void set_answer(int idx, int label[TRAIN_NUM])
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// output[i] = fc2_a[i];
// answer[i] = (label[idx] == i) ? 1 : 0;
// }
//}
//
//void check_answer(int& correct_cnt)
//{
// float _max = output[0];
// int max_pos = 0;
// for (int i = 0;i < FC2_SIZE;i++)
// {
// if (_max < output[i])
// {
// _max = output[i];
// max_pos = i;
// }
// }
// if (answer[max_pos])
// correct_cnt++;
//}
//
//void get_error(float& avg_error)
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// C[i] = output[i] - answer[i];
// avg_error += C[i] * C[i] * 0.5;
// }
//}
//
//
//void update_fc2_b()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_delta[i] = alpha * C[i] * (fc2_a[i] * (1.0 - fc2_a[i]));
// fc2_db[i] += fc2_delta[i];
// }
//}
//
//void update_fc2_w()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_dw[i][j] += fc2_delta[i] * fc1_a[j];
//}
//
//void update_fc1_b()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// {
// float error = 0;
// for (int j = 0;j < FC2_SIZE;j++)
// error += fc2_delta[j] * fc2_w[j][i];
// fc1_delta[i] = error * (fc1_a[i] * (1.0 - fc1_a[i]));
// fc1_db[i] += fc1_delta[i];
// }
//}
//
//void update_fc1_w()
//{
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_dw[i][j][k][l] += fc1_delta[i] * pool[j][k][l];
//}
//
//void update_conv_b()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_sigma_delta[i] = 0;
// for (int j = 0;j < POOL_SIZE;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// {
// float error = 0;
// conv_delta[i][j][k] = 0;
// for (int l = 0;l < FC1_SIZE;l++)
// error += fc1_delta[l] * fc1_w[l][i][j][k];
// conv_delta[i][j][k] = error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// conv_sigma_delta[i] += error * (pool[i][j][k] * (1.0 - pool[i][j][k]));
// }
// conv_db[i] += conv_sigma_delta[i];
// }
//}
//
//void update_conv_w()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// {
// float error = 0;
// for (int m = 0;m < POOL_SIZE;m++)
// for (int n = 0;n < POOL_SIZE;n++)
// {
// int x = pool_pos[i][m][n] / 2;
// int y = pool_pos[i][m][n] % 2;
// error += conv_delta[i][m][n] * input[2 * m + j + x][2 * n + k + y];
// }
// conv_dw[i][j][k] += error;
// }
//}
//
//void assign_grads()
//{
// for (int i = 0;i < FC2_SIZE;i++)
// {
// fc2_b[i] -= (fc2_db[i] / minibatch);
// fc2_db[i] = 0;
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// for (int j = 0;j < FC1_SIZE;j++)
// {
// fc2_w[i][j] -= (fc2_dw[i][j] / minibatch);
// fc2_dw[i][j] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// fc1_b[i] -= (fc1_db[i] / minibatch);
// fc1_db[i] = 0;
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// {
// fc1_w[i][j][k][l] -= (fc1_dw[i][j][k][l] / minibatch);
// fc1_dw[i][j][k][l] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// conv_b[i] -= (conv_db[i] / minibatch);
// conv_db[i] = 0;
// }
//
// for (int i = 0;i < CONV_W_NUM;i++)
// for (int l = 0;l < CONV_W_SIZE;l++)
// for (int m = 0;m < CONV_W_SIZE;m++)
// {
// conv_w[i][l][m] -= (conv_dw[i][l][m] / minibatch);
// conv_dw[i][l][m] = 0;
// }
//}
//
//float get_rand(float fan_in)
//{
// float sum = 0;
// for (int i = 0;i < 12;i++)
// sum += (float)rand() / RAND_MAX;
// sum -= 6;
// sum *= 1 / sqrt(fan_in);
// return sum;
//}
//void init_params()
//{
// for (int i = 0;i < CONV_W_NUM;i++)
// {
// for (int j = 0;j < CONV_W_SIZE;j++)
// for (int k = 0;k < CONV_W_SIZE;k++)
// conv_w[i][j][k] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// conv_b[i] = get_rand(CONV_W_SIZE * CONV_W_SIZE);
// }
//
// for (int i = 0;i < FC1_SIZE;i++)
// {
// for (int j = 0;j < CONV_W_NUM;j++)
// for (int k = 0;k < POOL_SIZE;k++)
// for (int l = 0;l < POOL_SIZE;l++)
// fc1_w[i][j][k][l] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// fc1_b[i] = get_rand(POOL_SIZE * POOL_SIZE * CONV_W_NUM);
// }
//
// for (int i = 0;i < FC2_SIZE;i++)
// {
// for (int j = 0;j < FC1_SIZE;j++)
// fc2_w[i][j] = get_rand(FC1_SIZE);
// fc2_b[i] = get_rand(FC1_SIZE);
// }
//}
//int main() {
//
// load_data();
// clock_t t = clock();
// init_params();
//
// for (int i = 1;i <= epochs;i++)
// {
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TRAIN_NUM;j++)
// {
// set_input(j, train_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, train_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// update_fc2_b();
// update_fc2_w();
// update_fc1_b();
// update_fc1_w();
// update_conv_b();
// update_conv_w();
// if ((j + 1) % minibatch == 0)
// assign_grads();
//
// if (j && j % 100 == 0)
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100, i);
// }
// printf("Training Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% Epoch : %d \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TRAIN_NUM, ((float)correct_cnt / TRAIN_NUM) * 100, (avg_error / TRAIN_NUM) * 100, i);
//
// correct_cnt = 0;
// avg_error = 0;
//
// for (int j = 0;j < TEST_NUM;j++)
// {
// set_input(j, test_image);
// input_conv();
// conv_pool();
// pool_fc1();
// fc1_fc2();
// set_answer(j, test_label);
// check_answer(correct_cnt);
// get_error(avg_error);
//
// if (j && j % 100 == 0)
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \r", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), j, ((float)correct_cnt / j) * 100, (avg_error / j) * 100);
// }
// printf("Testing Time spent : %.0fs Image count : %d Accuracy : %0.4f%% Error : %0.4f%% \n", floor(((float)(clock() - t)) / CLOCKS_PER_SEC), TEST_NUM, ((float)correct_cnt / TEST_NUM) * 100, (avg_error / TEST_NUM) * 100);
//
// if ((float)correct_cnt / TEST_NUM * 100 > max_acc)
// {
// max_acc = (float)correct_cnt / TEST_NUM * 100;
// //export_params();
// printf("The new model has been exported.Accuracy has reached to %0.5f%%\n\n", max_acc);
// }
// else
// {
// alpha = alpha - (alpha / 3);
// printf("Learning rate has been reduced to %f\n\n", alpha);
// }
// }
//
//
//
// //float train_image[ROW][COL] = {
// //{ 3, 1, 2, 4, 3, 3 },
// //{ 2, 4, 3, 1, 1, 4 },
// //{ 1, 5, 2, 3, 2, 5 },
// //{ 2, 3, 4, 1, 4, 1 },
// //{ 1, 4, 2, 1, 2, 3 },
// //{ 2, 3, 6, 5, 4, 1 }, };
// //float conv_w[CONV_W_NUM][CONV_W_SIZE][CONV_W_SIZE] = { {
// //{1, 2, 3},
// //{4, 3, 1},
// //{1, 2, 4}},
// //{{4, 2, 5},
// //{2, 3, 1},
// //{1, 2, 3}} };
//
// ////float conv_z[CONV_W_NUM][CONV_SIZE][CONV_SIZE];
// //float conv_z[2][2][2];
// //float train_label[2] = { 3,2 };
//
// //cudaMemcpyToSymbol(_train_image, train_image, ROW * COL * sizeof(float));
// //cudaMemcpyToSymbol(_conv_w, conv_w, CONV_W_NUM * CONV_W_SIZE * CONV_W_SIZE * sizeof(float));
// ////cudaMemcpy(_train_label, train_label, 2 * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_train_image, train_image, ROW * COL * sizeof(float), cudaMemcpyHostToDevice);
// ////cudaMemcpy(_conv_w, conv_w, CONV_W_NUM*CONV_W_SIZE*CONV_W_SIZE*sizeof(float), cudaMemcpyHostToDevice);
// //dim3 grid2(2, 4, 4);
//
// ////_input_conv << <1, grid2>> > ((float (*)[4])_train_image, (float (*)[3][3])_conv_w, (float (*)[2][2])_conv_z);
// //_input_conv << <1, grid2 >> > ();
// //_conv_pool << <1, grid2 >> > ();
// ////cudaMemcpyFromSymbol(&conv_z, _pool, CONV_W_NUM * CONV_SIZE * CONV_SIZE * sizeof(float));
// //cudaMemcpyFromSymbol(&conv_z, _pool, 8 * sizeof(float));
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j <2;j++) {
// // cout << conv_z[0][i][j] << " ";
// // }
// // cout << endl;
// //}
// //for (int i = 0;i < 2;i++) {
// // for (int j = 0;j < 2;j++) {
// // cout << conv_z[1][i][j] << " ";
// // }
// // cout << endl;
// //}
// return 0;
//}
|
.text
.file "MyCNNCpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d62e8_00000000-6_MyCNNCpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "MyCNNCpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <float.h>
__global__ void vector_sub(double *out, const double *a, double c, int m, int n) {
int tid =threadIdx.x;
if (tid >= m && tid < n) {
out[tid] -= a[tid] * c;
}
}
void printMatrix(double **matrix, const int *SIZE) {
for (int i = 0; i < *SIZE; ++i) {
for (int j = 0; j < *SIZE; ++j) {
printf("%f ", matrix[i][j]);
}
printf("\n");
}
printf("\n");
}
double diagonalMultiplication(double **matrix, const int *SIZE) {
double rez = 1;
for (int i = 0; i < *SIZE; ++i) rez *= matrix[i][i];
return rez;
}
int zeroesCheck(const double *range, const int *SIZE) {
int count = 0, flag = 1;
for (int i = 0; i < *SIZE; ++i)
if (range[i] == 0 && flag) {
count++;
} else flag = 0;
return count;
}
int power(int a, int b) {
int rez = 1;
for (int i = 0; i < b; ++i) rez *= a;
return rez;
}
int sort(double **matrix, int *SIZE) {
int i, j, count = 0;
double *temp;
for (i = 0; i < *SIZE - 1; i++)
for (j = 0; j < *SIZE - i - 1; j++) {
if (zeroesCheck(matrix[j], SIZE) > zeroesCheck(matrix[j + 1], SIZE)) {
count++;
temp = matrix[j];
matrix[j] = matrix[j + 1];
matrix[j + 1] = temp;
}
}
return power(-1, count);
}
double gaussianDeterminant(double **matrix, int* SIZE) {
int size = *SIZE;
double first, factor;
double *d_a, *d_out;
cudaMalloc((void **) &d_a, sizeof(double) * *SIZE);
cudaMalloc((void **) &d_out, sizeof(double) * *SIZE);
while (size > 1) {
if (matrix[*SIZE - size][*SIZE - size] == 0) return 0;
first = matrix[*SIZE - size][*SIZE - size];
for (int i = *SIZE - size + 1; i < *SIZE; ++i) {
factor = matrix[i][*SIZE - size] / first;
cudaMemcpy(d_out, matrix[i], sizeof(double) * *SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_a, matrix[*SIZE - size], sizeof(double) * *SIZE, cudaMemcpyHostToDevice);
vector_sub <<< 1, *SIZE >>>(d_out, d_a, factor, *SIZE - size, *SIZE);
cudaMemcpy(matrix[i], d_out, sizeof(double) * *SIZE, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
}
size--;
}
cudaFree(d_a);
cudaFree(d_out);
return diagonalMultiplication(matrix, SIZE);
}
void init() {
FILE *fp1, *fp2;
if ((fp1 = fopen("read.txt", "r")) == nullptr) {
printf("Can't open file 'read.txt'\n");
exit(-1);
}
if ((fp2 = fopen("write.txt", "w")) == nullptr) {
printf("Can't open file 'write.txt'\n");
exit(-1);
}
double **matrix;
double determinant;
int SIZE, sign;
clock_t time_start, time_finish;
while (fscanf(fp1, "%d", &SIZE) == 1) {
matrix = (double **) malloc(SIZE * sizeof(double *));
for (int i = 0; i < SIZE; ++i) {
matrix[i] = (double *) malloc(SIZE * sizeof(double));
for (int j = 0; j < SIZE; ++j) {
fscanf(fp1, "%lf", &matrix[i][j]);
}
}
time_start = clock();
sign = sort(matrix, &SIZE);
determinant = gaussianDeterminant(matrix, &SIZE) * (double) sign;
time_finish = clock();
fprintf(fp2, "%ld %f\n", time_finish - time_start, determinant);
for (int i = 0; i < SIZE; ++i) free(matrix[i]);
free(matrix);
if (determinant > DBL_MAX) exit(-2);
}
fclose(fp1);
fclose(fp2);
}
int main() {
init();
return 0;
}
|
code for sm_80
Function : _Z10vector_subPdPKddii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x001fc80003f06270 */
/*0030*/ ISETP.LT.OR P0, PT, R4, c[0x0][0x178], P0 ; /* 0x00005e0004007a0c */
/* 0x000fda0000701670 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ DFMA R6, -R2, c[0x0][0x170], R6 ; /* 0x00005c0002067a2b */
/* 0x004e0e0000000106 */
/*00c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <float.h>
__global__ void vector_sub(double *out, const double *a, double c, int m, int n) {
int tid =threadIdx.x;
if (tid >= m && tid < n) {
out[tid] -= a[tid] * c;
}
}
void printMatrix(double **matrix, const int *SIZE) {
for (int i = 0; i < *SIZE; ++i) {
for (int j = 0; j < *SIZE; ++j) {
printf("%f ", matrix[i][j]);
}
printf("\n");
}
printf("\n");
}
double diagonalMultiplication(double **matrix, const int *SIZE) {
double rez = 1;
for (int i = 0; i < *SIZE; ++i) rez *= matrix[i][i];
return rez;
}
int zeroesCheck(const double *range, const int *SIZE) {
int count = 0, flag = 1;
for (int i = 0; i < *SIZE; ++i)
if (range[i] == 0 && flag) {
count++;
} else flag = 0;
return count;
}
int power(int a, int b) {
int rez = 1;
for (int i = 0; i < b; ++i) rez *= a;
return rez;
}
int sort(double **matrix, int *SIZE) {
int i, j, count = 0;
double *temp;
for (i = 0; i < *SIZE - 1; i++)
for (j = 0; j < *SIZE - i - 1; j++) {
if (zeroesCheck(matrix[j], SIZE) > zeroesCheck(matrix[j + 1], SIZE)) {
count++;
temp = matrix[j];
matrix[j] = matrix[j + 1];
matrix[j + 1] = temp;
}
}
return power(-1, count);
}
double gaussianDeterminant(double **matrix, int* SIZE) {
int size = *SIZE;
double first, factor;
double *d_a, *d_out;
cudaMalloc((void **) &d_a, sizeof(double) * *SIZE);
cudaMalloc((void **) &d_out, sizeof(double) * *SIZE);
while (size > 1) {
if (matrix[*SIZE - size][*SIZE - size] == 0) return 0;
first = matrix[*SIZE - size][*SIZE - size];
for (int i = *SIZE - size + 1; i < *SIZE; ++i) {
factor = matrix[i][*SIZE - size] / first;
cudaMemcpy(d_out, matrix[i], sizeof(double) * *SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_a, matrix[*SIZE - size], sizeof(double) * *SIZE, cudaMemcpyHostToDevice);
vector_sub <<< 1, *SIZE >>>(d_out, d_a, factor, *SIZE - size, *SIZE);
cudaMemcpy(matrix[i], d_out, sizeof(double) * *SIZE, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
}
size--;
}
cudaFree(d_a);
cudaFree(d_out);
return diagonalMultiplication(matrix, SIZE);
}
void init() {
FILE *fp1, *fp2;
if ((fp1 = fopen("read.txt", "r")) == nullptr) {
printf("Can't open file 'read.txt'\n");
exit(-1);
}
if ((fp2 = fopen("write.txt", "w")) == nullptr) {
printf("Can't open file 'write.txt'\n");
exit(-1);
}
double **matrix;
double determinant;
int SIZE, sign;
clock_t time_start, time_finish;
while (fscanf(fp1, "%d", &SIZE) == 1) {
matrix = (double **) malloc(SIZE * sizeof(double *));
for (int i = 0; i < SIZE; ++i) {
matrix[i] = (double *) malloc(SIZE * sizeof(double));
for (int j = 0; j < SIZE; ++j) {
fscanf(fp1, "%lf", &matrix[i][j]);
}
}
time_start = clock();
sign = sort(matrix, &SIZE);
determinant = gaussianDeterminant(matrix, &SIZE) * (double) sign;
time_finish = clock();
fprintf(fp2, "%ld %f\n", time_finish - time_start, determinant);
for (int i = 0; i < SIZE; ++i) free(matrix[i]);
free(matrix);
if (determinant > DBL_MAX) exit(-2);
}
fclose(fp1);
fclose(fp2);
}
int main() {
init();
return 0;
}
|
.file "tmpxft_0011dbcc_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.text
.globl _Z11printMatrixPPdPKi
.type _Z11printMatrixPPdPKi, @function
_Z11printMatrixPPdPKi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
cmpl $0, (%rsi)
jle .L4
movq %rsi, %r12
movq %rdi, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L5
.L6:
movq 0(%rbp), %rax
movsd (%rax,%rbx,8), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, (%r12)
jg .L6
.L7:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq $8, %rbp
cmpl %r14d, (%r12)
jle .L4
.L5:
movl $0, %ebx
cmpl $0, (%r12)
jg .L6
jmp .L7
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPPdPKi, .-_Z11printMatrixPPdPKi
.globl _Z22diagonalMultiplicationPPdPKi
.type _Z22diagonalMultiplicationPPdPKi, @function
_Z22diagonalMultiplicationPPdPKi:
.LFB2058:
.cfi_startproc
endbr64
movl (%rsi), %ecx
testl %ecx, %ecx
jle .L15
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
movsd .LC2(%rip), %xmm0
.L14:
movq (%rdi,%rax), %rdx
mulsd (%rdx,%rax), %xmm0
addq $8, %rax
cmpq %rcx, %rax
jne .L14
ret
.L15:
movsd .LC2(%rip), %xmm0
ret
.cfi_endproc
.LFE2058:
.size _Z22diagonalMultiplicationPPdPKi, .-_Z22diagonalMultiplicationPPdPKi
.globl _Z11zeroesCheckPKdPKi
.type _Z11zeroesCheckPKdPKi, @function
_Z11zeroesCheckPKdPKi:
.LFB2059:
.cfi_startproc
endbr64
movl (%rsi), %edx
testl %edx, %edx
jle .L21
movq %rdi, %rax
movslq %edx, %rdx
leaq (%rdi,%rdx,8), %rdi
movl $1, %ecx
movl $0, %r9d
pxor %xmm0, %xmm0
movl $0, %esi
movl $0, %r8d
jmp .L20
.L22:
movl %r8d, %ecx
.L19:
addq $8, %rax
cmpq %rdi, %rax
je .L17
.L20:
ucomisd (%rax), %xmm0
setnp %dl
cmovne %esi, %edx
testb %dl, %dl
je .L22
testl %ecx, %ecx
je .L22
addl $1, %r9d
jmp .L19
.L21:
movl $0, %r9d
.L17:
movl %r9d, %eax
ret
.cfi_endproc
.LFE2059:
.size _Z11zeroesCheckPKdPKi, .-_Z11zeroesCheckPKdPKi
.globl _Z5powerii
.type _Z5powerii, @function
_Z5powerii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L27
movl $0, %eax
movl $1, %edx
.L26:
imull %edi, %edx
addl $1, %eax
cmpl %eax, %esi
jne .L26
.L24:
movl %edx, %eax
ret
.L27:
movl $1, %edx
jmp .L24
.cfi_endproc
.LFE2060:
.size _Z5powerii, .-_Z5powerii
.globl _Z4sortPPdPi
.type _Z4sortPPdPi, @function
_Z4sortPPdPi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %rbp
movl $0, 4(%rsp)
movl $0, %r15d
movl $1, %edx
cmpl $1, (%rsi)
jg .L30
jmp .L29
.L32:
addq $1, %rbx
movl %r15d, %eax
notl %eax
addl 0(%rbp), %eax
cmpl %ebx, %eax
jle .L35
.L33:
movq (%r12,%rbx,8), %r13
movq %rbp, %rsi
movq %r13, %rdi
call _Z11zeroesCheckPKdPKi
movl %eax, (%rsp)
movq 8(%r12,%rbx,8), %r14
movq %rbp, %rsi
movq %r14, %rdi
call _Z11zeroesCheckPKdPKi
cmpl %eax, (%rsp)
jle .L32
addl $1, 4(%rsp)
movq %r14, (%r12,%rbx,8)
movq %r13, 8(%r12,%rbx,8)
jmp .L32
.L35:
addl $1, %r15d
movl 0(%rbp), %eax
subl $1, %eax
cmpl %r15d, %eax
jle .L34
.L30:
movl 0(%rbp), %eax
subl %r15d, %eax
movl $0, %ebx
cmpl $1, %eax
jg .L33
jmp .L35
.L34:
cmpl $0, 4(%rsp)
jle .L39
movl $0, %eax
movl $1, %edx
.L36:
negl %edx
addl $1, %eax
movl 4(%rsp), %ecx
cmpl %ecx, %eax
jne .L36
.L29:
movl %edx, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $1, %edx
jmp .L29
.cfi_endproc
.LFE2061:
.size _Z4sortPPdPi, .-_Z4sortPPdPi
.globl _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
.type _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii, @function
_Z36__device_stub__Z10vector_subPdPKddiiPdPKddii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_subPdPKddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii, .-_Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
.globl _Z10vector_subPdPKddii
.type _Z10vector_subPdPKddii, @function
_Z10vector_subPdPKddii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z10vector_subPdPKddii, .-_Z10vector_subPdPKddii
.globl _Z19gaussianDeterminantPPdPi
.type _Z19gaussianDeterminantPPdPi, @function
_Z19gaussianDeterminantPPdPi:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl (%rsi), %r13d
movslq %r13d, %rsi
salq $3, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movslq 0(%rbp), %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
cmpl $1, %r13d
jg .L60
.L54:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rsi
movq %r12, %rdi
call _Z22diagonalMultiplicationPPdPKi
.L53:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movslq 0(%rbp), %rdx
salq $3, %rdx
movq (%r12,%rbx,8), %rdi
movl $2, %ecx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl 0(%rbp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jle .L57
.L59:
movq (%r12,%rbx,8), %rsi
movl %edx, %eax
subl %r13d, %eax
cltq
movq (%rsi,%rax,8), %r14
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %eax
movslq %eax, %rdx
salq $3, %rdx
subl %r13d, %eax
cltq
movq (%r12,%rax,8), %rsi
movl $1, %ecx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L58
movl 0(%rbp), %ecx
movl %ecx, %edx
subl %r13d, %edx
movq %r14, %xmm0
movq %r15, %xmm1
divsd %xmm1, %xmm0
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
jmp .L58
.L57:
subl $1, %r13d
cmpl $1, %r13d
je .L54
.L60:
movl 0(%rbp), %edx
movl %edx, %ebx
subl %r13d, %ebx
movslq %ebx, %rax
movq (%r12,%rax,8), %rcx
movq (%rcx,%rax,8), %r15
movq %r15, %xmm2
pxor %xmm3, %xmm3
ucomisd %xmm3, %xmm2
jp .L63
je .L62
.L63:
addl $1, %ebx
cmpl %ebx, %edx
jle .L57
movslq %ebx, %rbx
jmp .L59
.L62:
pxor %xmm0, %xmm0
jmp .L53
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z19gaussianDeterminantPPdPi, .-_Z19gaussianDeterminantPPdPi
.section .rodata.str1.1
.LC4:
.string "r"
.LC5:
.string "read.txt"
.LC6:
.string "Can't open file 'read.txt'\n"
.LC7:
.string "w"
.LC8:
.string "write.txt"
.LC9:
.string "Can't open file 'write.txt'\n"
.LC10:
.string "%lf"
.LC11:
.string "%ld %f\n"
.LC13:
.string "%d"
.text
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L87
movq %rax, %r12
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L85
leaq .LC10(%rip), %r13
jmp .L70
.L87:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L85:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L75:
movq %r15, %rdi
call free@PLT
movq %rbp, %xmm2
comisd .LC12(%rip), %xmm2
ja .L88
.L70:
leaq 20(%rsp), %rdx
leaq .LC13(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L89
movl 20(%rsp), %ebx
movslq %ebx, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L71
movl $0, %r14d
.L74:
movslq %ebx, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%r15,%r14,8)
cmpl $0, 20(%rsp)
jle .L72
movl $0, %ebp
.L73:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
addq $8, %rbx
cmpl %ebp, 20(%rsp)
jg .L73
.L72:
movl 20(%rsp), %ebx
addq $1, %r14
cmpl %r14d, %ebx
jg .L74
.L71:
call clock@PLT
movq %rax, %rbx
leaq 20(%rsp), %rbp
movq %rbp, %rsi
movq %r15, %rdi
call _Z4sortPPdPi
movl %eax, %r14d
movq %rbp, %rsi
movq %r15, %rdi
call _Z19gaussianDeterminantPPdPi
pxor %xmm1, %xmm1
cvtsi2sdl %r14d, %xmm1
mulsd %xmm0, %xmm1
movq %xmm1, %rbp
call clock@PLT
subq %rbx, %rax
movq %rax, %rcx
movq %rbp, %xmm0
leaq .LC11(%rip), %rdx
movl $2, %esi
movq 8(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
cmpl $0, 20(%rsp)
jle .L75
movl $0, %ebx
.L76:
movq (%r15,%rbx,8), %rdi
call free@PLT
addq $1, %rbx
cmpl %ebx, 20(%rsp)
jg .L76
jmp .L75
.L88:
movl $-2, %edi
call exit@PLT
.L89:
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L90
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z4initv, .-_Z4initv
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z4initv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10vector_subPdPKddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_subPdPKddii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC12:
.long -1
.long 2146435071
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <float.h>
__global__ void vector_sub(double *out, const double *a, double c, int m, int n) {
int tid =threadIdx.x;
if (tid >= m && tid < n) {
out[tid] -= a[tid] * c;
}
}
void printMatrix(double **matrix, const int *SIZE) {
for (int i = 0; i < *SIZE; ++i) {
for (int j = 0; j < *SIZE; ++j) {
printf("%f ", matrix[i][j]);
}
printf("\n");
}
printf("\n");
}
double diagonalMultiplication(double **matrix, const int *SIZE) {
double rez = 1;
for (int i = 0; i < *SIZE; ++i) rez *= matrix[i][i];
return rez;
}
int zeroesCheck(const double *range, const int *SIZE) {
int count = 0, flag = 1;
for (int i = 0; i < *SIZE; ++i)
if (range[i] == 0 && flag) {
count++;
} else flag = 0;
return count;
}
int power(int a, int b) {
int rez = 1;
for (int i = 0; i < b; ++i) rez *= a;
return rez;
}
int sort(double **matrix, int *SIZE) {
int i, j, count = 0;
double *temp;
for (i = 0; i < *SIZE - 1; i++)
for (j = 0; j < *SIZE - i - 1; j++) {
if (zeroesCheck(matrix[j], SIZE) > zeroesCheck(matrix[j + 1], SIZE)) {
count++;
temp = matrix[j];
matrix[j] = matrix[j + 1];
matrix[j + 1] = temp;
}
}
return power(-1, count);
}
double gaussianDeterminant(double **matrix, int* SIZE) {
int size = *SIZE;
double first, factor;
double *d_a, *d_out;
cudaMalloc((void **) &d_a, sizeof(double) * *SIZE);
cudaMalloc((void **) &d_out, sizeof(double) * *SIZE);
while (size > 1) {
if (matrix[*SIZE - size][*SIZE - size] == 0) return 0;
first = matrix[*SIZE - size][*SIZE - size];
for (int i = *SIZE - size + 1; i < *SIZE; ++i) {
factor = matrix[i][*SIZE - size] / first;
cudaMemcpy(d_out, matrix[i], sizeof(double) * *SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_a, matrix[*SIZE - size], sizeof(double) * *SIZE, cudaMemcpyHostToDevice);
vector_sub <<< 1, *SIZE >>>(d_out, d_a, factor, *SIZE - size, *SIZE);
cudaMemcpy(matrix[i], d_out, sizeof(double) * *SIZE, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
}
size--;
}
cudaFree(d_a);
cudaFree(d_out);
return diagonalMultiplication(matrix, SIZE);
}
void init() {
FILE *fp1, *fp2;
if ((fp1 = fopen("read.txt", "r")) == nullptr) {
printf("Can't open file 'read.txt'\n");
exit(-1);
}
if ((fp2 = fopen("write.txt", "w")) == nullptr) {
printf("Can't open file 'write.txt'\n");
exit(-1);
}
double **matrix;
double determinant;
int SIZE, sign;
clock_t time_start, time_finish;
while (fscanf(fp1, "%d", &SIZE) == 1) {
matrix = (double **) malloc(SIZE * sizeof(double *));
for (int i = 0; i < SIZE; ++i) {
matrix[i] = (double *) malloc(SIZE * sizeof(double));
for (int j = 0; j < SIZE; ++j) {
fscanf(fp1, "%lf", &matrix[i][j]);
}
}
time_start = clock();
sign = sort(matrix, &SIZE);
determinant = gaussianDeterminant(matrix, &SIZE) * (double) sign;
time_finish = clock();
fprintf(fp2, "%ld %f\n", time_finish - time_start, determinant);
for (int i = 0; i < SIZE; ++i) free(matrix[i]);
free(matrix);
if (determinant > DBL_MAX) exit(-2);
}
fclose(fp1);
fclose(fp2);
}
int main() {
init();
return 0;
}
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <float.h>
__global__ void vector_sub(double *out, const double *a, double c, int m, int n) {
int tid =threadIdx.x;
if (tid >= m && tid < n) {
out[tid] -= a[tid] * c;
}
}
void printMatrix(double **matrix, const int *SIZE) {
for (int i = 0; i < *SIZE; ++i) {
for (int j = 0; j < *SIZE; ++j) {
printf("%f ", matrix[i][j]);
}
printf("\n");
}
printf("\n");
}
double diagonalMultiplication(double **matrix, const int *SIZE) {
double rez = 1;
for (int i = 0; i < *SIZE; ++i) rez *= matrix[i][i];
return rez;
}
int zeroesCheck(const double *range, const int *SIZE) {
int count = 0, flag = 1;
for (int i = 0; i < *SIZE; ++i)
if (range[i] == 0 && flag) {
count++;
} else flag = 0;
return count;
}
int power(int a, int b) {
int rez = 1;
for (int i = 0; i < b; ++i) rez *= a;
return rez;
}
int sort(double **matrix, int *SIZE) {
int i, j, count = 0;
double *temp;
for (i = 0; i < *SIZE - 1; i++)
for (j = 0; j < *SIZE - i - 1; j++) {
if (zeroesCheck(matrix[j], SIZE) > zeroesCheck(matrix[j + 1], SIZE)) {
count++;
temp = matrix[j];
matrix[j] = matrix[j + 1];
matrix[j + 1] = temp;
}
}
return power(-1, count);
}
double gaussianDeterminant(double **matrix, int* SIZE) {
int size = *SIZE;
double first, factor;
double *d_a, *d_out;
hipMalloc((void **) &d_a, sizeof(double) * *SIZE);
hipMalloc((void **) &d_out, sizeof(double) * *SIZE);
while (size > 1) {
if (matrix[*SIZE - size][*SIZE - size] == 0) return 0;
first = matrix[*SIZE - size][*SIZE - size];
for (int i = *SIZE - size + 1; i < *SIZE; ++i) {
factor = matrix[i][*SIZE - size] / first;
hipMemcpy(d_out, matrix[i], sizeof(double) * *SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_a, matrix[*SIZE - size], sizeof(double) * *SIZE, hipMemcpyHostToDevice);
vector_sub <<< 1, *SIZE >>>(d_out, d_a, factor, *SIZE - size, *SIZE);
hipMemcpy(matrix[i], d_out, sizeof(double) * *SIZE, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
}
size--;
}
hipFree(d_a);
hipFree(d_out);
return diagonalMultiplication(matrix, SIZE);
}
void init() {
FILE *fp1, *fp2;
if ((fp1 = fopen("read.txt", "r")) == nullptr) {
printf("Can't open file 'read.txt'\n");
exit(-1);
}
if ((fp2 = fopen("write.txt", "w")) == nullptr) {
printf("Can't open file 'write.txt'\n");
exit(-1);
}
double **matrix;
double determinant;
int SIZE, sign;
clock_t time_start, time_finish;
while (fscanf(fp1, "%d", &SIZE) == 1) {
matrix = (double **) malloc(SIZE * sizeof(double *));
for (int i = 0; i < SIZE; ++i) {
matrix[i] = (double *) malloc(SIZE * sizeof(double));
for (int j = 0; j < SIZE; ++j) {
fscanf(fp1, "%lf", &matrix[i][j]);
}
}
time_start = clock();
sign = sort(matrix, &SIZE);
determinant = gaussianDeterminant(matrix, &SIZE) * (double) sign;
time_finish = clock();
fprintf(fp2, "%ld %f\n", time_finish - time_start, determinant);
for (int i = 0; i < SIZE; ++i) free(matrix[i]);
free(matrix);
if (determinant > DBL_MAX) exit(-2);
}
fclose(fp1);
fclose(fp2);
}
int main() {
init();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <float.h>
__global__ void vector_sub(double *out, const double *a, double c, int m, int n) {
int tid =threadIdx.x;
if (tid >= m && tid < n) {
out[tid] -= a[tid] * c;
}
}
void printMatrix(double **matrix, const int *SIZE) {
for (int i = 0; i < *SIZE; ++i) {
for (int j = 0; j < *SIZE; ++j) {
printf("%f ", matrix[i][j]);
}
printf("\n");
}
printf("\n");
}
double diagonalMultiplication(double **matrix, const int *SIZE) {
double rez = 1;
for (int i = 0; i < *SIZE; ++i) rez *= matrix[i][i];
return rez;
}
int zeroesCheck(const double *range, const int *SIZE) {
int count = 0, flag = 1;
for (int i = 0; i < *SIZE; ++i)
if (range[i] == 0 && flag) {
count++;
} else flag = 0;
return count;
}
int power(int a, int b) {
int rez = 1;
for (int i = 0; i < b; ++i) rez *= a;
return rez;
}
int sort(double **matrix, int *SIZE) {
int i, j, count = 0;
double *temp;
for (i = 0; i < *SIZE - 1; i++)
for (j = 0; j < *SIZE - i - 1; j++) {
if (zeroesCheck(matrix[j], SIZE) > zeroesCheck(matrix[j + 1], SIZE)) {
count++;
temp = matrix[j];
matrix[j] = matrix[j + 1];
matrix[j + 1] = temp;
}
}
return power(-1, count);
}
double gaussianDeterminant(double **matrix, int* SIZE) {
int size = *SIZE;
double first, factor;
double *d_a, *d_out;
hipMalloc((void **) &d_a, sizeof(double) * *SIZE);
hipMalloc((void **) &d_out, sizeof(double) * *SIZE);
while (size > 1) {
if (matrix[*SIZE - size][*SIZE - size] == 0) return 0;
first = matrix[*SIZE - size][*SIZE - size];
for (int i = *SIZE - size + 1; i < *SIZE; ++i) {
factor = matrix[i][*SIZE - size] / first;
hipMemcpy(d_out, matrix[i], sizeof(double) * *SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_a, matrix[*SIZE - size], sizeof(double) * *SIZE, hipMemcpyHostToDevice);
vector_sub <<< 1, *SIZE >>>(d_out, d_a, factor, *SIZE - size, *SIZE);
hipMemcpy(matrix[i], d_out, sizeof(double) * *SIZE, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
}
size--;
}
hipFree(d_a);
hipFree(d_out);
return diagonalMultiplication(matrix, SIZE);
}
void init() {
FILE *fp1, *fp2;
if ((fp1 = fopen("read.txt", "r")) == nullptr) {
printf("Can't open file 'read.txt'\n");
exit(-1);
}
if ((fp2 = fopen("write.txt", "w")) == nullptr) {
printf("Can't open file 'write.txt'\n");
exit(-1);
}
double **matrix;
double determinant;
int SIZE, sign;
clock_t time_start, time_finish;
while (fscanf(fp1, "%d", &SIZE) == 1) {
matrix = (double **) malloc(SIZE * sizeof(double *));
for (int i = 0; i < SIZE; ++i) {
matrix[i] = (double *) malloc(SIZE * sizeof(double));
for (int j = 0; j < SIZE; ++j) {
fscanf(fp1, "%lf", &matrix[i][j]);
}
}
time_start = clock();
sign = sort(matrix, &SIZE);
determinant = gaussianDeterminant(matrix, &SIZE) * (double) sign;
time_finish = clock();
fprintf(fp2, "%ld %f\n", time_finish - time_start, determinant);
for (int i = 0; i < SIZE; ++i) free(matrix[i]);
free(matrix);
if (determinant > DBL_MAX) exit(-2);
}
fclose(fp1);
fclose(fp2);
}
int main() {
init();
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_subPdPKddii
.globl _Z10vector_subPdPKddii
.p2align 8
.type _Z10vector_subPdPKddii,@function
_Z10vector_subPdPKddii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[6:7]
global_load_b64 v[2:3], v4, s[4:5]
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], -v[0:1], s[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_subPdPKddii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_subPdPKddii, .Lfunc_end0-_Z10vector_subPdPKddii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_subPdPKddii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10vector_subPdPKddii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <float.h>
__global__ void vector_sub(double *out, const double *a, double c, int m, int n) {
int tid =threadIdx.x;
if (tid >= m && tid < n) {
out[tid] -= a[tid] * c;
}
}
void printMatrix(double **matrix, const int *SIZE) {
for (int i = 0; i < *SIZE; ++i) {
for (int j = 0; j < *SIZE; ++j) {
printf("%f ", matrix[i][j]);
}
printf("\n");
}
printf("\n");
}
double diagonalMultiplication(double **matrix, const int *SIZE) {
double rez = 1;
for (int i = 0; i < *SIZE; ++i) rez *= matrix[i][i];
return rez;
}
int zeroesCheck(const double *range, const int *SIZE) {
int count = 0, flag = 1;
for (int i = 0; i < *SIZE; ++i)
if (range[i] == 0 && flag) {
count++;
} else flag = 0;
return count;
}
int power(int a, int b) {
int rez = 1;
for (int i = 0; i < b; ++i) rez *= a;
return rez;
}
int sort(double **matrix, int *SIZE) {
int i, j, count = 0;
double *temp;
for (i = 0; i < *SIZE - 1; i++)
for (j = 0; j < *SIZE - i - 1; j++) {
if (zeroesCheck(matrix[j], SIZE) > zeroesCheck(matrix[j + 1], SIZE)) {
count++;
temp = matrix[j];
matrix[j] = matrix[j + 1];
matrix[j + 1] = temp;
}
}
return power(-1, count);
}
double gaussianDeterminant(double **matrix, int* SIZE) {
int size = *SIZE;
double first, factor;
double *d_a, *d_out;
hipMalloc((void **) &d_a, sizeof(double) * *SIZE);
hipMalloc((void **) &d_out, sizeof(double) * *SIZE);
while (size > 1) {
if (matrix[*SIZE - size][*SIZE - size] == 0) return 0;
first = matrix[*SIZE - size][*SIZE - size];
for (int i = *SIZE - size + 1; i < *SIZE; ++i) {
factor = matrix[i][*SIZE - size] / first;
hipMemcpy(d_out, matrix[i], sizeof(double) * *SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_a, matrix[*SIZE - size], sizeof(double) * *SIZE, hipMemcpyHostToDevice);
vector_sub <<< 1, *SIZE >>>(d_out, d_a, factor, *SIZE - size, *SIZE);
hipMemcpy(matrix[i], d_out, sizeof(double) * *SIZE, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
}
size--;
}
hipFree(d_a);
hipFree(d_out);
return diagonalMultiplication(matrix, SIZE);
}
void init() {
FILE *fp1, *fp2;
if ((fp1 = fopen("read.txt", "r")) == nullptr) {
printf("Can't open file 'read.txt'\n");
exit(-1);
}
if ((fp2 = fopen("write.txt", "w")) == nullptr) {
printf("Can't open file 'write.txt'\n");
exit(-1);
}
double **matrix;
double determinant;
int SIZE, sign;
clock_t time_start, time_finish;
while (fscanf(fp1, "%d", &SIZE) == 1) {
matrix = (double **) malloc(SIZE * sizeof(double *));
for (int i = 0; i < SIZE; ++i) {
matrix[i] = (double *) malloc(SIZE * sizeof(double));
for (int j = 0; j < SIZE; ++j) {
fscanf(fp1, "%lf", &matrix[i][j]);
}
}
time_start = clock();
sign = sort(matrix, &SIZE);
determinant = gaussianDeterminant(matrix, &SIZE) * (double) sign;
time_finish = clock();
fprintf(fp2, "%ld %f\n", time_finish - time_start, determinant);
for (int i = 0; i < SIZE; ++i) free(matrix[i]);
free(matrix);
if (determinant > DBL_MAX) exit(-2);
}
fclose(fp1);
fclose(fp2);
}
int main() {
init();
return 0;
}
|
.text
.file "main.hip"
.globl _Z25__device_stub__vector_subPdPKddii # -- Begin function _Z25__device_stub__vector_subPdPKddii
.p2align 4, 0x90
.type _Z25__device_stub__vector_subPdPKddii,@function
_Z25__device_stub__vector_subPdPKddii: # @_Z25__device_stub__vector_subPdPKddii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_subPdPKddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_subPdPKddii, .Lfunc_end0-_Z25__device_stub__vector_subPdPKddii
.cfi_endproc
# -- End function
.globl _Z11printMatrixPPdPKi # -- Begin function _Z11printMatrixPPdPKi
.p2align 4, 0x90
.type _Z11printMatrixPPdPKi,@function
_Z11printMatrixPPdPKi: # @_Z11printMatrixPPdPKi
.cfi_startproc
# %bb.0:
cmpl $0, (%rsi)
jle .LBB1_7
# %bb.1: # %.preheader.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
movslq (%rbx), %rax
cmpq %rax, %r15
jge .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, (%rbx)
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rax
movsd (%rax,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
movslq (%rbx), %rax
cmpq %rax, %r12
jl .LBB1_4
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_7: # %._crit_edge12
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11printMatrixPPdPKi, .Lfunc_end1-_Z11printMatrixPPdPKi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22diagonalMultiplicationPPdPKi
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z22diagonalMultiplicationPPdPKi
.p2align 4, 0x90
.type _Z22diagonalMultiplicationPPdPKi,@function
_Z22diagonalMultiplicationPPdPKi: # @_Z22diagonalMultiplicationPPdPKi
.cfi_startproc
# %bb.0:
movl (%rsi), %eax
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rcx,8), %rdx
mulsd (%rdx,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z22diagonalMultiplicationPPdPKi, .Lfunc_end2-_Z22diagonalMultiplicationPPdPKi
.cfi_endproc
# -- End function
.globl _Z11zeroesCheckPKdPKi # -- Begin function _Z11zeroesCheckPKdPKi
.p2align 4, 0x90
.type _Z11zeroesCheckPKdPKi,@function
_Z11zeroesCheckPKdPKi: # @_Z11zeroesCheckPKdPKi
.cfi_startproc
# %bb.0:
movl (%rsi), %ecx
testl %ecx, %ecx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
xorl %edx, %edx
movb $1, %sil
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
ucomisd (%rdi,%rdx,8), %xmm0
setnp %r8b
sete %r9b
andb %r8b, %r9b
andb %r9b, %sil
movzbl %sil, %r8d
addl %r8d, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_4
# %bb.2: # %._crit_edge
retq
.LBB3_1:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z11zeroesCheckPKdPKi, .Lfunc_end3-_Z11zeroesCheckPKdPKi
.cfi_endproc
# -- End function
.globl _Z5powerii # -- Begin function _Z5powerii
.p2align 4, 0x90
.type _Z5powerii,@function
_Z5powerii: # @_Z5powerii
.cfi_startproc
# %bb.0:
movl $1, %eax
testl %esi, %esi
jle .LBB4_2
.p2align 4, 0x90
.LBB4_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
imull %edi, %eax
decl %esi
jne .LBB4_1
.LBB4_2: # %._crit_edge
retq
.Lfunc_end4:
.size _Z5powerii, .Lfunc_end4-_Z5powerii
.cfi_endproc
# -- End function
.globl _Z4sortPPdPi # -- Begin function _Z4sortPPdPi
.p2align 4, 0x90
.type _Z4sortPPdPi,@function
_Z4sortPPdPi: # @_Z4sortPPdPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl (%rsi), %eax
xorl %ecx, %ecx
cmpl $2, %eax
jl .LBB5_12
# %bb.1: # %.preheader.lr.ph
leal -1(%rax), %ecx
xorl %esi, %esi
xorpd %xmm0, %xmm0
movl %ecx, -8(%rsp) # 4-byte Spill
movl %ecx, %edx
xorl %ecx, %ecx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_11: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incl %esi
movl -4(%rsp), %edx # 4-byte Reload
decl %edx
cmpl -8(%rsp), %esi # 4-byte Folded Reload
je .LBB5_12
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_5 Depth 3
# Child Loop BB5_7 Depth 3
movl %esi, %r9d
subl %eax, %r9d
cmpl $-2, %r9d
movl %edx, -4(%rsp) # 4-byte Spill
jg .LBB5_11
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB5_2 Depth=1
movl %edx, %r9d
xorl %r14d, %r14d
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_10: # in Loop: Header=BB5_4 Depth=2
cmpq %r9, %r14
je .LBB5_11
.LBB5_4: # %.lr.ph
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_5 Depth 3
# Child Loop BB5_7 Depth 3
movq %r14, %r10
movq (%rdi,%r14,8), %r11
xorl %r14d, %r14d
movb $1, %bpl
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i
# Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
ucomisd (%r11,%r14,8), %xmm0
setnp %r15b
sete %r12b
andb %r15b, %r12b
andb %r12b, %bpl
movzbl %bpl, %r15d
addl %r15d, %ebx
incq %r14
cmpq %r14, %rax
jne .LBB5_5
# %bb.6: # %_Z11zeroesCheckPKdPKi.exit
# in Loop: Header=BB5_4 Depth=2
leaq 1(%r10), %r14
movq 8(%rdi,%r10,8), %r15
xorl %r12d, %r12d
movb $1, %bpl
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_7: # %.lr.ph.i28
# Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
ucomisd (%r15,%r12,8), %xmm0
setnp %dl
sete %r8b
andb %dl, %r8b
andb %r8b, %bpl
movzbl %bpl, %edx
addl %edx, %r13d
incq %r12
cmpq %r12, %rax
jne .LBB5_7
# %bb.8: # %_Z11zeroesCheckPKdPKi.exit36
# in Loop: Header=BB5_4 Depth=2
cmpl %r13d, %ebx
jbe .LBB5_10
# %bb.9: # in Loop: Header=BB5_4 Depth=2
incl %ecx
movq %r15, (%rdi,%r10,8)
movq %r11, (%rdi,%r14,8)
jmp .LBB5_10
.LBB5_12: # %._crit_edge43
testl %ecx, %ecx
jle .LBB5_13
# %bb.14: # %.lr.ph.i37.preheader
movl $1, %edx
movl $-1, %esi
.p2align 4, 0x90
.LBB5_15: # %.lr.ph.i37
# =>This Inner Loop Header: Depth=1
movl %esi, %eax
movl %edx, %esi
movl %eax, %edx
decl %ecx
jne .LBB5_15
jmp .LBB5_16
.LBB5_13:
movl $1, %eax
.LBB5_16: # %_Z5powerii.exit
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z4sortPPdPi, .Lfunc_end5-_Z4sortPPdPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19gaussianDeterminantPPdPi
.LCPI6_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z19gaussianDeterminantPPdPi
.p2align 4, 0x90
.type _Z19gaussianDeterminantPPdPi,@function
_Z19gaussianDeterminantPPdPi: # @_Z19gaussianDeterminantPPdPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
movslq (%rsi), %rbp
leaq (,%rbp,8), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq (%r14), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
cmpq $2, %rbp
jl .LBB6_9
# %bb.1: # %.lr.ph56
movabsq $4294967296, %rax # imm = 0x100000000
movl $1, %ecx
subl %ebp, %ecx
movl %ecx, 12(%rsp) # 4-byte Spill
leaq 1(%rax), %r15
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_8: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
leal -1(%rbp), %eax
incl 12(%rsp) # 4-byte Folded Spill
cmpl $2, %ebp
movl %eax, %ebp
jle .LBB6_9
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
movl (%r14), %ecx
movl %ecx, %edx
subl %ebp, %edx
movslq %edx, %rax
movq (%rbx,%rax,8), %rsi
movsd (%rsi,%rax,8), %xmm1 # xmm1 = mem[0],zero
xorpd %xmm0, %xmm0
movsd %xmm1, 40(%rsp) # 8-byte Spill
ucomisd %xmm0, %xmm1
jne .LBB6_3
jnp .LBB6_12
.LBB6_3: # %.preheader
# in Loop: Header=BB6_2 Depth=1
incl %edx
movl (%r14), %eax
cmpl %eax, %edx
jge .LBB6_8
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB6_2 Depth=1
addl 12(%rsp), %ecx # 4-byte Folded Reload
movslq %ecx, %r13
movslq %ebp, %r12
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_7: # in Loop: Header=BB6_5 Depth=2
movq (%rbx,%r13,8), %rdi
movq 16(%rsp), %rsi
movslq (%r14), %rdx
shlq $3, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
incq %r13
movslq (%r14), %rax
cmpq %rax, %r13
jge .LBB6_8
.LBB6_5: # %.lr.ph
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r13,8), %rsi
movslq %eax, %rdx
subl %ebp, %eax
cltq
movsd (%rsi,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq (%r14), %rdx
movq %rdx, %rax
subq %r12, %rax
movq (%rbx,%rax,8), %rsi
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movl (%r14), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_7
# %bb.6: # in Loop: Header=BB6_5 Depth=2
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movl (%r14), %edx
movl %edx, 32(%rsp)
subl %ebp, %edx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movsd %xmm0, 104(%rsp)
movl %edx, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z10vector_subPdPKddii, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_7
.LBB6_9: # %._crit_edge57
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl (%r14), %eax
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %eax, %eax
jle .LBB6_12
# %bb.10: # %.lr.ph.preheader.i
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq (%rbx,%rcx,8), %rdx
mulsd (%rdx,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB6_11
.LBB6_12: # %_Z22diagonalMultiplicationPPdPKi.exit
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z19gaussianDeterminantPPdPi, .Lfunc_end6-_Z19gaussianDeterminantPPdPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4initv
.LCPI7_0:
.quad 0x7fefffffffffffff # double 1.7976931348623157E+308
.text
.globl _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
testq %rax, %rax
je .LBB7_1
# %bb.3:
movq %rax, %rbx
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, 24(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB7_4
# %bb.5:
leaq 4(%rsp), %r15
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_32: # %._crit_edge38
# in Loop: Header=BB7_6 Depth=1
movq %r12, %rdi
callq free
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd .LCPI7_0(%rip), %xmm0
ja .LBB7_33
.LBB7_6: # =>This Loop Header: Depth=1
# Child Loop BB7_9 Depth 2
# Child Loop BB7_11 Depth 3
# Child Loop BB7_15 Depth 2
# Child Loop BB7_17 Depth 3
# Child Loop BB7_18 Depth 4
# Child Loop BB7_20 Depth 4
# Child Loop BB7_28 Depth 2
# Child Loop BB7_31 Depth 2
movl $.L.str.8, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB7_34
# %bb.7: # in Loop: Header=BB7_6 Depth=1
movslq 4(%rsp), %r14
leaq (,%r14,8), %rdi
callq malloc
movq %rax, %r12
testq %r14, %r14
jle .LBB7_13
# %bb.8: # %.lr.ph34.preheader
# in Loop: Header=BB7_6 Depth=1
xorl %ebp, %ebp
jmp .LBB7_9
.p2align 4, 0x90
.LBB7_12: # %._crit_edge
# in Loop: Header=BB7_9 Depth=2
incq %rbp
movslq 4(%rsp), %r14
cmpq %r14, %rbp
jge .LBB7_13
.LBB7_9: # %.lr.ph34
# Parent Loop BB7_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_11 Depth 3
movslq %r14d, %rdi
shlq $3, %rdi
callq malloc
movq %rax, (%r12,%rbp,8)
cmpl $0, 4(%rsp)
jle .LBB7_12
# %bb.10: # %.lr.ph.preheader
# in Loop: Header=BB7_9 Depth=2
movq %rax, %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_11: # %.lr.ph
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_9 Depth=2
# => This Inner Loop Header: Depth=3
movl $.L.str.9, %esi
movq %rbx, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r14
movslq 4(%rsp), %rax
addq $8, %r13
cmpq %rax, %r14
jl .LBB7_11
jmp .LBB7_12
.p2align 4, 0x90
.LBB7_13: # %._crit_edge35
# in Loop: Header=BB7_6 Depth=1
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
movl 4(%rsp), %ecx
xorl %eax, %eax
cmpl $2, %ecx
xorpd %xmm0, %xmm0
jl .LBB7_25
# %bb.14: # %.preheader.lr.ph.i
# in Loop: Header=BB7_6 Depth=1
leal -1(%rcx), %eax
xorl %edx, %edx
movl %eax, 16(%rsp) # 4-byte Spill
movl %eax, %esi
xorl %eax, %eax
jmp .LBB7_15
.p2align 4, 0x90
.LBB7_24: # %._crit_edge.i
# in Loop: Header=BB7_15 Depth=2
movl 8(%rsp), %edx # 4-byte Reload
incl %edx
movl 20(%rsp), %esi # 4-byte Reload
decl %esi
cmpl 16(%rsp), %edx # 4-byte Folded Reload
je .LBB7_25
.LBB7_15: # %.preheader.i
# Parent Loop BB7_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_17 Depth 3
# Child Loop BB7_18 Depth 4
# Child Loop BB7_20 Depth 4
movl %edx, 8(%rsp) # 4-byte Spill
subl %ecx, %edx
cmpl $-2, %edx
movl %esi, 20(%rsp) # 4-byte Spill
jg .LBB7_24
# %bb.16: # %.lr.ph.preheader.i
# in Loop: Header=BB7_15 Depth=2
movl %esi, %r8d
xorl %ebp, %ebp
jmp .LBB7_17
.p2align 4, 0x90
.LBB7_23: # in Loop: Header=BB7_17 Depth=3
cmpq %r8, %rbp
je .LBB7_24
.LBB7_17: # %.lr.ph.i
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_15 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB7_18 Depth 4
# Child Loop BB7_20 Depth 4
movq %rbp, %r9
movq (%r12,%rbp,8), %r10
xorl %r15d, %r15d
movb $1, %bpl
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB7_18: # %.lr.ph.i.i
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_15 Depth=2
# Parent Loop BB7_17 Depth=3
# => This Inner Loop Header: Depth=4
ucomisd (%r10,%r15,8), %xmm0
setnp %dl
sete %r14b
andb %dl, %r14b
andb %r14b, %bpl
movzbl %bpl, %edx
addl %edx, %r11d
incq %r15
cmpq %r15, %rcx
jne .LBB7_18
# %bb.19: # %_Z11zeroesCheckPKdPKi.exit.i
# in Loop: Header=BB7_17 Depth=3
leaq 1(%r9), %rbp
movq 8(%r12,%r9,8), %r15
xorl %r14d, %r14d
movb $1, %r13b
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_20: # %.lr.ph.i28.i
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_15 Depth=2
# Parent Loop BB7_17 Depth=3
# => This Inner Loop Header: Depth=4
ucomisd (%r15,%r14,8), %xmm0
setnp %dil
sete %sil
andb %dil, %sil
andb %sil, %r13b
movzbl %r13b, %esi
addl %esi, %edx
incq %r14
cmpq %r14, %rcx
jne .LBB7_20
# %bb.21: # %_Z11zeroesCheckPKdPKi.exit36.i
# in Loop: Header=BB7_17 Depth=3
cmpl %edx, %r11d
jbe .LBB7_23
# %bb.22: # in Loop: Header=BB7_17 Depth=3
incl %eax
movq %r15, (%r12,%r9,8)
movq %r10, (%r12,%rbp,8)
jmp .LBB7_23
.p2align 4, 0x90
.LBB7_25: # %._crit_edge43.i
# in Loop: Header=BB7_6 Depth=1
testl %eax, %eax
leaq 4(%rsp), %r15
jle .LBB7_26
# %bb.27: # %.lr.ph.i37.i.preheader
# in Loop: Header=BB7_6 Depth=1
movl $1, %ecx
movl $-1, %edx
.p2align 4, 0x90
.LBB7_28: # %.lr.ph.i37.i
# Parent Loop BB7_6 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %ebp
movl %ecx, %edx
movl %ebp, %ecx
decl %eax
jne .LBB7_28
jmp .LBB7_29
.p2align 4, 0x90
.LBB7_26: # in Loop: Header=BB7_6 Depth=1
movl $1, %ebp
.LBB7_29: # %_Z4sortPPdPi.exit
# in Loop: Header=BB7_6 Depth=1
movq %r12, %rdi
movq %r15, %rsi
callq _Z19gaussianDeterminantPPdPi
xorps %xmm1, %xmm1
cvtsi2sd %ebp, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
movl $.L.str.10, %esi
movq 24(%rsp), %rdi # 8-byte Reload
movq %rax, %rdx
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
cmpl $0, 4(%rsp)
jle .LBB7_32
# %bb.30: # %.lr.ph37.preheader
# in Loop: Header=BB7_6 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_31: # %.lr.ph37
# Parent Loop BB7_6 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%r14,8), %rdi
callq free
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB7_31
jmp .LBB7_32
.LBB7_34:
movq %rbx, %rdi
callq fclose
movq 24(%rsp), %rdi # 8-byte Reload
callq fclose
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_33:
.cfi_def_cfa_offset 96
movl $-2, %edi
callq exit
.LBB7_1:
movl $.Lstr.1, %edi
jmp .LBB7_2
.LBB7_4:
movl $.Lstr, %edi
.LBB7_2:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end7:
.size _Z4initv, .Lfunc_end7-_Z4initv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z4initv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_subPdPKddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_subPdPKddii,@object # @_Z10vector_subPdPKddii
.section .rodata,"a",@progbits
.globl _Z10vector_subPdPKddii
.p2align 3, 0x0
_Z10vector_subPdPKddii:
.quad _Z25__device_stub__vector_subPdPKddii
.size _Z10vector_subPdPKddii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "read.txt"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "write.txt"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%lf"
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%ld %f\n"
.size .L.str.10, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_subPdPKddii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Can't open file 'write.txt'"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Can't open file 'read.txt'"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_subPdPKddii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_subPdPKddii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10vector_subPdPKddii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x001fc80003f06270 */
/*0030*/ ISETP.LT.OR P0, PT, R4, c[0x0][0x178], P0 ; /* 0x00005e0004007a0c */
/* 0x000fda0000701670 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ DFMA R6, -R2, c[0x0][0x170], R6 ; /* 0x00005c0002067a2b */
/* 0x004e0e0000000106 */
/*00c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_subPdPKddii
.globl _Z10vector_subPdPKddii
.p2align 8
.type _Z10vector_subPdPKddii,@function
_Z10vector_subPdPKddii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[6:7]
global_load_b64 v[2:3], v4, s[4:5]
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], -v[0:1], s[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_subPdPKddii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_subPdPKddii, .Lfunc_end0-_Z10vector_subPdPKddii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_subPdPKddii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10vector_subPdPKddii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0011dbcc_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.text
.globl _Z11printMatrixPPdPKi
.type _Z11printMatrixPPdPKi, @function
_Z11printMatrixPPdPKi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
cmpl $0, (%rsi)
jle .L4
movq %rsi, %r12
movq %rdi, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L5
.L6:
movq 0(%rbp), %rax
movsd (%rax,%rbx,8), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, (%r12)
jg .L6
.L7:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq $8, %rbp
cmpl %r14d, (%r12)
jle .L4
.L5:
movl $0, %ebx
cmpl $0, (%r12)
jg .L6
jmp .L7
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPPdPKi, .-_Z11printMatrixPPdPKi
.globl _Z22diagonalMultiplicationPPdPKi
.type _Z22diagonalMultiplicationPPdPKi, @function
_Z22diagonalMultiplicationPPdPKi:
.LFB2058:
.cfi_startproc
endbr64
movl (%rsi), %ecx
testl %ecx, %ecx
jle .L15
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
movsd .LC2(%rip), %xmm0
.L14:
movq (%rdi,%rax), %rdx
mulsd (%rdx,%rax), %xmm0
addq $8, %rax
cmpq %rcx, %rax
jne .L14
ret
.L15:
movsd .LC2(%rip), %xmm0
ret
.cfi_endproc
.LFE2058:
.size _Z22diagonalMultiplicationPPdPKi, .-_Z22diagonalMultiplicationPPdPKi
.globl _Z11zeroesCheckPKdPKi
.type _Z11zeroesCheckPKdPKi, @function
_Z11zeroesCheckPKdPKi:
.LFB2059:
.cfi_startproc
endbr64
movl (%rsi), %edx
testl %edx, %edx
jle .L21
movq %rdi, %rax
movslq %edx, %rdx
leaq (%rdi,%rdx,8), %rdi
movl $1, %ecx
movl $0, %r9d
pxor %xmm0, %xmm0
movl $0, %esi
movl $0, %r8d
jmp .L20
.L22:
movl %r8d, %ecx
.L19:
addq $8, %rax
cmpq %rdi, %rax
je .L17
.L20:
ucomisd (%rax), %xmm0
setnp %dl
cmovne %esi, %edx
testb %dl, %dl
je .L22
testl %ecx, %ecx
je .L22
addl $1, %r9d
jmp .L19
.L21:
movl $0, %r9d
.L17:
movl %r9d, %eax
ret
.cfi_endproc
.LFE2059:
.size _Z11zeroesCheckPKdPKi, .-_Z11zeroesCheckPKdPKi
.globl _Z5powerii
.type _Z5powerii, @function
_Z5powerii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L27
movl $0, %eax
movl $1, %edx
.L26:
imull %edi, %edx
addl $1, %eax
cmpl %eax, %esi
jne .L26
.L24:
movl %edx, %eax
ret
.L27:
movl $1, %edx
jmp .L24
.cfi_endproc
.LFE2060:
.size _Z5powerii, .-_Z5powerii
.globl _Z4sortPPdPi
.type _Z4sortPPdPi, @function
_Z4sortPPdPi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %rbp
movl $0, 4(%rsp)
movl $0, %r15d
movl $1, %edx
cmpl $1, (%rsi)
jg .L30
jmp .L29
.L32:
addq $1, %rbx
movl %r15d, %eax
notl %eax
addl 0(%rbp), %eax
cmpl %ebx, %eax
jle .L35
.L33:
movq (%r12,%rbx,8), %r13
movq %rbp, %rsi
movq %r13, %rdi
call _Z11zeroesCheckPKdPKi
movl %eax, (%rsp)
movq 8(%r12,%rbx,8), %r14
movq %rbp, %rsi
movq %r14, %rdi
call _Z11zeroesCheckPKdPKi
cmpl %eax, (%rsp)
jle .L32
addl $1, 4(%rsp)
movq %r14, (%r12,%rbx,8)
movq %r13, 8(%r12,%rbx,8)
jmp .L32
.L35:
addl $1, %r15d
movl 0(%rbp), %eax
subl $1, %eax
cmpl %r15d, %eax
jle .L34
.L30:
movl 0(%rbp), %eax
subl %r15d, %eax
movl $0, %ebx
cmpl $1, %eax
jg .L33
jmp .L35
.L34:
cmpl $0, 4(%rsp)
jle .L39
movl $0, %eax
movl $1, %edx
.L36:
negl %edx
addl $1, %eax
movl 4(%rsp), %ecx
cmpl %ecx, %eax
jne .L36
.L29:
movl %edx, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $1, %edx
jmp .L29
.cfi_endproc
.LFE2061:
.size _Z4sortPPdPi, .-_Z4sortPPdPi
.globl _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
.type _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii, @function
_Z36__device_stub__Z10vector_subPdPKddiiPdPKddii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_subPdPKddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii, .-_Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
.globl _Z10vector_subPdPKddii
.type _Z10vector_subPdPKddii, @function
_Z10vector_subPdPKddii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z10vector_subPdPKddii, .-_Z10vector_subPdPKddii
.globl _Z19gaussianDeterminantPPdPi
.type _Z19gaussianDeterminantPPdPi, @function
_Z19gaussianDeterminantPPdPi:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl (%rsi), %r13d
movslq %r13d, %rsi
salq $3, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movslq 0(%rbp), %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
cmpl $1, %r13d
jg .L60
.L54:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rsi
movq %r12, %rdi
call _Z22diagonalMultiplicationPPdPKi
.L53:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movslq 0(%rbp), %rdx
salq $3, %rdx
movq (%r12,%rbx,8), %rdi
movl $2, %ecx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl 0(%rbp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jle .L57
.L59:
movq (%r12,%rbx,8), %rsi
movl %edx, %eax
subl %r13d, %eax
cltq
movq (%rsi,%rax,8), %r14
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %eax
movslq %eax, %rdx
salq $3, %rdx
subl %r13d, %eax
cltq
movq (%r12,%rax,8), %rsi
movl $1, %ecx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L58
movl 0(%rbp), %ecx
movl %ecx, %edx
subl %r13d, %edx
movq %r14, %xmm0
movq %r15, %xmm1
divsd %xmm1, %xmm0
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z10vector_subPdPKddiiPdPKddii
jmp .L58
.L57:
subl $1, %r13d
cmpl $1, %r13d
je .L54
.L60:
movl 0(%rbp), %edx
movl %edx, %ebx
subl %r13d, %ebx
movslq %ebx, %rax
movq (%r12,%rax,8), %rcx
movq (%rcx,%rax,8), %r15
movq %r15, %xmm2
pxor %xmm3, %xmm3
ucomisd %xmm3, %xmm2
jp .L63
je .L62
.L63:
addl $1, %ebx
cmpl %ebx, %edx
jle .L57
movslq %ebx, %rbx
jmp .L59
.L62:
pxor %xmm0, %xmm0
jmp .L53
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z19gaussianDeterminantPPdPi, .-_Z19gaussianDeterminantPPdPi
.section .rodata.str1.1
.LC4:
.string "r"
.LC5:
.string "read.txt"
.LC6:
.string "Can't open file 'read.txt'\n"
.LC7:
.string "w"
.LC8:
.string "write.txt"
.LC9:
.string "Can't open file 'write.txt'\n"
.LC10:
.string "%lf"
.LC11:
.string "%ld %f\n"
.LC13:
.string "%d"
.text
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L87
movq %rax, %r12
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L85
leaq .LC10(%rip), %r13
jmp .L70
.L87:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L85:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L75:
movq %r15, %rdi
call free@PLT
movq %rbp, %xmm2
comisd .LC12(%rip), %xmm2
ja .L88
.L70:
leaq 20(%rsp), %rdx
leaq .LC13(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L89
movl 20(%rsp), %ebx
movslq %ebx, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L71
movl $0, %r14d
.L74:
movslq %ebx, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%r15,%r14,8)
cmpl $0, 20(%rsp)
jle .L72
movl $0, %ebp
.L73:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
addq $8, %rbx
cmpl %ebp, 20(%rsp)
jg .L73
.L72:
movl 20(%rsp), %ebx
addq $1, %r14
cmpl %r14d, %ebx
jg .L74
.L71:
call clock@PLT
movq %rax, %rbx
leaq 20(%rsp), %rbp
movq %rbp, %rsi
movq %r15, %rdi
call _Z4sortPPdPi
movl %eax, %r14d
movq %rbp, %rsi
movq %r15, %rdi
call _Z19gaussianDeterminantPPdPi
pxor %xmm1, %xmm1
cvtsi2sdl %r14d, %xmm1
mulsd %xmm0, %xmm1
movq %xmm1, %rbp
call clock@PLT
subq %rbx, %rax
movq %rax, %rcx
movq %rbp, %xmm0
leaq .LC11(%rip), %rdx
movl $2, %esi
movq 8(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
cmpl $0, 20(%rsp)
jle .L75
movl $0, %ebx
.L76:
movq (%r15,%rbx,8), %rdi
call free@PLT
addq $1, %rbx
cmpl %ebx, 20(%rsp)
jg .L76
jmp .L75
.L88:
movl $-2, %edi
call exit@PLT
.L89:
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L90
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z4initv, .-_Z4initv
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z4initv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10vector_subPdPKddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_subPdPKddii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC12:
.long -1
.long 2146435071
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.globl _Z25__device_stub__vector_subPdPKddii # -- Begin function _Z25__device_stub__vector_subPdPKddii
.p2align 4, 0x90
.type _Z25__device_stub__vector_subPdPKddii,@function
_Z25__device_stub__vector_subPdPKddii: # @_Z25__device_stub__vector_subPdPKddii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_subPdPKddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_subPdPKddii, .Lfunc_end0-_Z25__device_stub__vector_subPdPKddii
.cfi_endproc
# -- End function
.globl _Z11printMatrixPPdPKi # -- Begin function _Z11printMatrixPPdPKi
.p2align 4, 0x90
.type _Z11printMatrixPPdPKi,@function
_Z11printMatrixPPdPKi: # @_Z11printMatrixPPdPKi
.cfi_startproc
# %bb.0:
cmpl $0, (%rsi)
jle .LBB1_7
# %bb.1: # %.preheader.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
movslq (%rbx), %rax
cmpq %rax, %r15
jge .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, (%rbx)
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r15,8), %rax
movsd (%rax,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
movslq (%rbx), %rax
cmpq %rax, %r12
jl .LBB1_4
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_7: # %._crit_edge12
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11printMatrixPPdPKi, .Lfunc_end1-_Z11printMatrixPPdPKi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22diagonalMultiplicationPPdPKi
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z22diagonalMultiplicationPPdPKi
.p2align 4, 0x90
.type _Z22diagonalMultiplicationPPdPKi,@function
_Z22diagonalMultiplicationPPdPKi: # @_Z22diagonalMultiplicationPPdPKi
.cfi_startproc
# %bb.0:
movl (%rsi), %eax
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rcx,8), %rdx
mulsd (%rdx,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z22diagonalMultiplicationPPdPKi, .Lfunc_end2-_Z22diagonalMultiplicationPPdPKi
.cfi_endproc
# -- End function
.globl _Z11zeroesCheckPKdPKi # -- Begin function _Z11zeroesCheckPKdPKi
.p2align 4, 0x90
.type _Z11zeroesCheckPKdPKi,@function
_Z11zeroesCheckPKdPKi: # @_Z11zeroesCheckPKdPKi
.cfi_startproc
# %bb.0:
movl (%rsi), %ecx
testl %ecx, %ecx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
xorl %edx, %edx
movb $1, %sil
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
ucomisd (%rdi,%rdx,8), %xmm0
setnp %r8b
sete %r9b
andb %r8b, %r9b
andb %r9b, %sil
movzbl %sil, %r8d
addl %r8d, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_4
# %bb.2: # %._crit_edge
retq
.LBB3_1:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z11zeroesCheckPKdPKi, .Lfunc_end3-_Z11zeroesCheckPKdPKi
.cfi_endproc
# -- End function
.globl _Z5powerii # -- Begin function _Z5powerii
.p2align 4, 0x90
.type _Z5powerii,@function
_Z5powerii: # @_Z5powerii
.cfi_startproc
# %bb.0:
movl $1, %eax
testl %esi, %esi
jle .LBB4_2
.p2align 4, 0x90
.LBB4_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
imull %edi, %eax
decl %esi
jne .LBB4_1
.LBB4_2: # %._crit_edge
retq
.Lfunc_end4:
.size _Z5powerii, .Lfunc_end4-_Z5powerii
.cfi_endproc
# -- End function
.globl _Z4sortPPdPi # -- Begin function _Z4sortPPdPi
.p2align 4, 0x90
.type _Z4sortPPdPi,@function
_Z4sortPPdPi: # @_Z4sortPPdPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl (%rsi), %eax
xorl %ecx, %ecx
cmpl $2, %eax
jl .LBB5_12
# %bb.1: # %.preheader.lr.ph
leal -1(%rax), %ecx
xorl %esi, %esi
xorpd %xmm0, %xmm0
movl %ecx, -8(%rsp) # 4-byte Spill
movl %ecx, %edx
xorl %ecx, %ecx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_11: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incl %esi
movl -4(%rsp), %edx # 4-byte Reload
decl %edx
cmpl -8(%rsp), %esi # 4-byte Folded Reload
je .LBB5_12
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_5 Depth 3
# Child Loop BB5_7 Depth 3
movl %esi, %r9d
subl %eax, %r9d
cmpl $-2, %r9d
movl %edx, -4(%rsp) # 4-byte Spill
jg .LBB5_11
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB5_2 Depth=1
movl %edx, %r9d
xorl %r14d, %r14d
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_10: # in Loop: Header=BB5_4 Depth=2
cmpq %r9, %r14
je .LBB5_11
.LBB5_4: # %.lr.ph
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_5 Depth 3
# Child Loop BB5_7 Depth 3
movq %r14, %r10
movq (%rdi,%r14,8), %r11
xorl %r14d, %r14d
movb $1, %bpl
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i
# Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
ucomisd (%r11,%r14,8), %xmm0
setnp %r15b
sete %r12b
andb %r15b, %r12b
andb %r12b, %bpl
movzbl %bpl, %r15d
addl %r15d, %ebx
incq %r14
cmpq %r14, %rax
jne .LBB5_5
# %bb.6: # %_Z11zeroesCheckPKdPKi.exit
# in Loop: Header=BB5_4 Depth=2
leaq 1(%r10), %r14
movq 8(%rdi,%r10,8), %r15
xorl %r12d, %r12d
movb $1, %bpl
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_7: # %.lr.ph.i28
# Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
ucomisd (%r15,%r12,8), %xmm0
setnp %dl
sete %r8b
andb %dl, %r8b
andb %r8b, %bpl
movzbl %bpl, %edx
addl %edx, %r13d
incq %r12
cmpq %r12, %rax
jne .LBB5_7
# %bb.8: # %_Z11zeroesCheckPKdPKi.exit36
# in Loop: Header=BB5_4 Depth=2
cmpl %r13d, %ebx
jbe .LBB5_10
# %bb.9: # in Loop: Header=BB5_4 Depth=2
incl %ecx
movq %r15, (%rdi,%r10,8)
movq %r11, (%rdi,%r14,8)
jmp .LBB5_10
.LBB5_12: # %._crit_edge43
testl %ecx, %ecx
jle .LBB5_13
# %bb.14: # %.lr.ph.i37.preheader
movl $1, %edx
movl $-1, %esi
.p2align 4, 0x90
.LBB5_15: # %.lr.ph.i37
# =>This Inner Loop Header: Depth=1
movl %esi, %eax
movl %edx, %esi
movl %eax, %edx
decl %ecx
jne .LBB5_15
jmp .LBB5_16
.LBB5_13:
movl $1, %eax
.LBB5_16: # %_Z5powerii.exit
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z4sortPPdPi, .Lfunc_end5-_Z4sortPPdPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19gaussianDeterminantPPdPi
.LCPI6_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z19gaussianDeterminantPPdPi
.p2align 4, 0x90
.type _Z19gaussianDeterminantPPdPi,@function
_Z19gaussianDeterminantPPdPi: # @_Z19gaussianDeterminantPPdPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
movslq (%rsi), %rbp
leaq (,%rbp,8), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq (%r14), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
cmpq $2, %rbp
jl .LBB6_9
# %bb.1: # %.lr.ph56
movabsq $4294967296, %rax # imm = 0x100000000
movl $1, %ecx
subl %ebp, %ecx
movl %ecx, 12(%rsp) # 4-byte Spill
leaq 1(%rax), %r15
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_8: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
leal -1(%rbp), %eax
incl 12(%rsp) # 4-byte Folded Spill
cmpl $2, %ebp
movl %eax, %ebp
jle .LBB6_9
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
movl (%r14), %ecx
movl %ecx, %edx
subl %ebp, %edx
movslq %edx, %rax
movq (%rbx,%rax,8), %rsi
movsd (%rsi,%rax,8), %xmm1 # xmm1 = mem[0],zero
xorpd %xmm0, %xmm0
movsd %xmm1, 40(%rsp) # 8-byte Spill
ucomisd %xmm0, %xmm1
jne .LBB6_3
jnp .LBB6_12
.LBB6_3: # %.preheader
# in Loop: Header=BB6_2 Depth=1
incl %edx
movl (%r14), %eax
cmpl %eax, %edx
jge .LBB6_8
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB6_2 Depth=1
addl 12(%rsp), %ecx # 4-byte Folded Reload
movslq %ecx, %r13
movslq %ebp, %r12
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_7: # in Loop: Header=BB6_5 Depth=2
movq (%rbx,%r13,8), %rdi
movq 16(%rsp), %rsi
movslq (%r14), %rdx
shlq $3, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
incq %r13
movslq (%r14), %rax
cmpq %rax, %r13
jge .LBB6_8
.LBB6_5: # %.lr.ph
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r13,8), %rsi
movslq %eax, %rdx
subl %ebp, %eax
cltq
movsd (%rsi,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq (%r14), %rdx
movq %rdx, %rax
subq %r12, %rax
movq (%rbx,%rax,8), %rsi
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movl (%r14), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_7
# %bb.6: # in Loop: Header=BB6_5 Depth=2
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movl (%r14), %edx
movl %edx, 32(%rsp)
subl %ebp, %edx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movsd %xmm0, 104(%rsp)
movl %edx, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z10vector_subPdPKddii, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_7
.LBB6_9: # %._crit_edge57
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl (%r14), %eax
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %eax, %eax
jle .LBB6_12
# %bb.10: # %.lr.ph.preheader.i
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq (%rbx,%rcx,8), %rdx
mulsd (%rdx,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB6_11
.LBB6_12: # %_Z22diagonalMultiplicationPPdPKi.exit
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z19gaussianDeterminantPPdPi, .Lfunc_end6-_Z19gaussianDeterminantPPdPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4initv
.LCPI7_0:
.quad 0x7fefffffffffffff # double 1.7976931348623157E+308
.text
.globl _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
testq %rax, %rax
je .LBB7_1
# %bb.3:
movq %rax, %rbx
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, 24(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB7_4
# %bb.5:
leaq 4(%rsp), %r15
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_32: # %._crit_edge38
# in Loop: Header=BB7_6 Depth=1
movq %r12, %rdi
callq free
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd .LCPI7_0(%rip), %xmm0
ja .LBB7_33
.LBB7_6: # =>This Loop Header: Depth=1
# Child Loop BB7_9 Depth 2
# Child Loop BB7_11 Depth 3
# Child Loop BB7_15 Depth 2
# Child Loop BB7_17 Depth 3
# Child Loop BB7_18 Depth 4
# Child Loop BB7_20 Depth 4
# Child Loop BB7_28 Depth 2
# Child Loop BB7_31 Depth 2
movl $.L.str.8, %esi
movq %rbx, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB7_34
# %bb.7: # in Loop: Header=BB7_6 Depth=1
movslq 4(%rsp), %r14
leaq (,%r14,8), %rdi
callq malloc
movq %rax, %r12
testq %r14, %r14
jle .LBB7_13
# %bb.8: # %.lr.ph34.preheader
# in Loop: Header=BB7_6 Depth=1
xorl %ebp, %ebp
jmp .LBB7_9
.p2align 4, 0x90
.LBB7_12: # %._crit_edge
# in Loop: Header=BB7_9 Depth=2
incq %rbp
movslq 4(%rsp), %r14
cmpq %r14, %rbp
jge .LBB7_13
.LBB7_9: # %.lr.ph34
# Parent Loop BB7_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_11 Depth 3
movslq %r14d, %rdi
shlq $3, %rdi
callq malloc
movq %rax, (%r12,%rbp,8)
cmpl $0, 4(%rsp)
jle .LBB7_12
# %bb.10: # %.lr.ph.preheader
# in Loop: Header=BB7_9 Depth=2
movq %rax, %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_11: # %.lr.ph
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_9 Depth=2
# => This Inner Loop Header: Depth=3
movl $.L.str.9, %esi
movq %rbx, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r14
movslq 4(%rsp), %rax
addq $8, %r13
cmpq %rax, %r14
jl .LBB7_11
jmp .LBB7_12
.p2align 4, 0x90
.LBB7_13: # %._crit_edge35
# in Loop: Header=BB7_6 Depth=1
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
movl 4(%rsp), %ecx
xorl %eax, %eax
cmpl $2, %ecx
xorpd %xmm0, %xmm0
jl .LBB7_25
# %bb.14: # %.preheader.lr.ph.i
# in Loop: Header=BB7_6 Depth=1
leal -1(%rcx), %eax
xorl %edx, %edx
movl %eax, 16(%rsp) # 4-byte Spill
movl %eax, %esi
xorl %eax, %eax
jmp .LBB7_15
.p2align 4, 0x90
.LBB7_24: # %._crit_edge.i
# in Loop: Header=BB7_15 Depth=2
movl 8(%rsp), %edx # 4-byte Reload
incl %edx
movl 20(%rsp), %esi # 4-byte Reload
decl %esi
cmpl 16(%rsp), %edx # 4-byte Folded Reload
je .LBB7_25
.LBB7_15: # %.preheader.i
# Parent Loop BB7_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_17 Depth 3
# Child Loop BB7_18 Depth 4
# Child Loop BB7_20 Depth 4
movl %edx, 8(%rsp) # 4-byte Spill
subl %ecx, %edx
cmpl $-2, %edx
movl %esi, 20(%rsp) # 4-byte Spill
jg .LBB7_24
# %bb.16: # %.lr.ph.preheader.i
# in Loop: Header=BB7_15 Depth=2
movl %esi, %r8d
xorl %ebp, %ebp
jmp .LBB7_17
.p2align 4, 0x90
.LBB7_23: # in Loop: Header=BB7_17 Depth=3
cmpq %r8, %rbp
je .LBB7_24
.LBB7_17: # %.lr.ph.i
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_15 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB7_18 Depth 4
# Child Loop BB7_20 Depth 4
movq %rbp, %r9
movq (%r12,%rbp,8), %r10
xorl %r15d, %r15d
movb $1, %bpl
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB7_18: # %.lr.ph.i.i
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_15 Depth=2
# Parent Loop BB7_17 Depth=3
# => This Inner Loop Header: Depth=4
ucomisd (%r10,%r15,8), %xmm0
setnp %dl
sete %r14b
andb %dl, %r14b
andb %r14b, %bpl
movzbl %bpl, %edx
addl %edx, %r11d
incq %r15
cmpq %r15, %rcx
jne .LBB7_18
# %bb.19: # %_Z11zeroesCheckPKdPKi.exit.i
# in Loop: Header=BB7_17 Depth=3
leaq 1(%r9), %rbp
movq 8(%r12,%r9,8), %r15
xorl %r14d, %r14d
movb $1, %r13b
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_20: # %.lr.ph.i28.i
# Parent Loop BB7_6 Depth=1
# Parent Loop BB7_15 Depth=2
# Parent Loop BB7_17 Depth=3
# => This Inner Loop Header: Depth=4
ucomisd (%r15,%r14,8), %xmm0
setnp %dil
sete %sil
andb %dil, %sil
andb %sil, %r13b
movzbl %r13b, %esi
addl %esi, %edx
incq %r14
cmpq %r14, %rcx
jne .LBB7_20
# %bb.21: # %_Z11zeroesCheckPKdPKi.exit36.i
# in Loop: Header=BB7_17 Depth=3
cmpl %edx, %r11d
jbe .LBB7_23
# %bb.22: # in Loop: Header=BB7_17 Depth=3
incl %eax
movq %r15, (%r12,%r9,8)
movq %r10, (%r12,%rbp,8)
jmp .LBB7_23
.p2align 4, 0x90
.LBB7_25: # %._crit_edge43.i
# in Loop: Header=BB7_6 Depth=1
testl %eax, %eax
leaq 4(%rsp), %r15
jle .LBB7_26
# %bb.27: # %.lr.ph.i37.i.preheader
# in Loop: Header=BB7_6 Depth=1
movl $1, %ecx
movl $-1, %edx
.p2align 4, 0x90
.LBB7_28: # %.lr.ph.i37.i
# Parent Loop BB7_6 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %ebp
movl %ecx, %edx
movl %ebp, %ecx
decl %eax
jne .LBB7_28
jmp .LBB7_29
.p2align 4, 0x90
.LBB7_26: # in Loop: Header=BB7_6 Depth=1
movl $1, %ebp
.LBB7_29: # %_Z4sortPPdPi.exit
# in Loop: Header=BB7_6 Depth=1
movq %r12, %rdi
movq %r15, %rsi
callq _Z19gaussianDeterminantPPdPi
xorps %xmm1, %xmm1
cvtsi2sd %ebp, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
movl $.L.str.10, %esi
movq 24(%rsp), %rdi # 8-byte Reload
movq %rax, %rdx
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
cmpl $0, 4(%rsp)
jle .LBB7_32
# %bb.30: # %.lr.ph37.preheader
# in Loop: Header=BB7_6 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_31: # %.lr.ph37
# Parent Loop BB7_6 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%r14,8), %rdi
callq free
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB7_31
jmp .LBB7_32
.LBB7_34:
movq %rbx, %rdi
callq fclose
movq 24(%rsp), %rdi # 8-byte Reload
callq fclose
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_33:
.cfi_def_cfa_offset 96
movl $-2, %edi
callq exit
.LBB7_1:
movl $.Lstr.1, %edi
jmp .LBB7_2
.LBB7_4:
movl $.Lstr, %edi
.LBB7_2:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end7:
.size _Z4initv, .Lfunc_end7-_Z4initv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z4initv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_subPdPKddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_subPdPKddii,@object # @_Z10vector_subPdPKddii
.section .rodata,"a",@progbits
.globl _Z10vector_subPdPKddii
.p2align 3, 0x0
_Z10vector_subPdPKddii:
.quad _Z25__device_stub__vector_subPdPKddii
.size _Z10vector_subPdPKddii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "read.txt"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "write.txt"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%lf"
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%ld %f\n"
.size .L.str.10, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_subPdPKddii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Can't open file 'write.txt'"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Can't open file 'read.txt'"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_subPdPKddii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_subPdPKddii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cassert>
#include <cmath>
#include <cstddef>
#include <cstdint>
#include <cstdlib>
#include <iostream>
#include <limits>
#include <random>
#include <vector>
#include <cuda_runtime_api.h>
#include <cuda.h>
/* Define the kernel function: */
__global__ void add_vec_kernel(
double const* __restrict__ x, double const* __restrict__ y,
double* __restrict__ z, int const n )
{
/* blockIdx, blockDim and threadIdx are variables describing the
* dimensions of the "grid" which are automatically provided by the
* Cuda runtime */
int const gid = blockIdx.x * blockDim.x + threadIdx.x;
if( gid < n )
{
z[ gid ] = x[ gid ] + y[ gid ];
}
return;
}
int main( void )
{
/* ---------------------------------------------------------------------- */
/* prepare the host vectors: */
int32_t const N = int32_t{ 10000 };
std::vector< double > x( N, double{ 0.0 } );
std::vector< double > y( N, double{ 0.0 } );
std::vector< double > z( N, double{ 0.0 } );
std::mt19937_64 prng( 20181205u );
std::uniform_real_distribution< double >
dist( double{ -10. }, double{ +10. } );
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
x[ ii ] = dist( prng );
y[ ii ] = dist( prng );
}
cudaError_t cu_err;
/* --------------------------------------------------------------------- */
/* use the "default" / "first" Cuda device for the program: */
int device = int{ 0 };
::cudaGetDevice( &device );
cu_err = ::cudaDeviceSynchronize();
assert( cu_err == ::cudaSuccess );
/* --------------------------------------------------------------------- */
/* Allocate the buffers on the device */
/* x_arg, y_arg, z_arg ... handles on the host side managing buffers in *
* the device memory */
double* x_arg = nullptr;
double* y_arg = nullptr;
double* z_arg = nullptr;
::cudaMalloc( &x_arg, sizeof( double ) * N );
::cudaMalloc( &y_arg, sizeof( double ) * N );
::cudaMalloc( &z_arg, sizeof( double ) * N );
/* --------------------------------------------------------------------- */
/* Transfer x and y from host to device */
::cudaMemcpy( x_arg, x.data(), sizeof( double ) * N, cudaMemcpyHostToDevice );
::cudaMemcpy( y_arg, y.data(), sizeof( double ) * N, cudaMemcpyHostToDevice );
/* --------------------------------------------------------------------- */
/* execute kernel on the device */
int32_t const threads_per_block = int32_t{ 128 };
int32_t const num_blocks =
( N + threads_per_block - int32_t{ 1 } ) / threads_per_block;
add_vec_kernel<<< num_blocks, threads_per_block >>>( x_arg, y_arg, z_arg, N );
cu_err = ::cudaPeekAtLastError();
assert( cu_err == ::cudaSuccess );
/* -------------------------------------------------------------------- */
/* transfer the result from the device buffer to the host buffer */
::cudaMemcpy( z.data(), z_arg, sizeof( double ) * N, cudaMemcpyDeviceToHost );
/* ------------------------------------------------------------------- */
/* verify that the result is correct */
bool success = true;
double const EPS = std::numeric_limits< double >::epsilon();
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
if( std::fabs( ( x[ ii ] + y[ ii ] ) - z[ ii ] ) > EPS )
{
success = false;
break;
}
}
std::cout << "Success: " << std::boolalpha << success << std::endl;
/* -------------------------------------------------------------------- */
/* Clean-up */
::cudaFree( x_arg );
::cudaFree( y_arg );
::cudaFree( z_arg );
return 0;
}
/* end: */
|
code for sm_80
Function : _Z14add_vec_kernelPKdS0_Pdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64.CONSTANT R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e9b00 */
/*00b0*/ LDG.E.64.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e9b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cassert>
#include <cmath>
#include <cstddef>
#include <cstdint>
#include <cstdlib>
#include <iostream>
#include <limits>
#include <random>
#include <vector>
#include <cuda_runtime_api.h>
#include <cuda.h>
/* Define the kernel function: */
__global__ void add_vec_kernel(
double const* __restrict__ x, double const* __restrict__ y,
double* __restrict__ z, int const n )
{
/* blockIdx, blockDim and threadIdx are variables describing the
* dimensions of the "grid" which are automatically provided by the
* Cuda runtime */
int const gid = blockIdx.x * blockDim.x + threadIdx.x;
if( gid < n )
{
z[ gid ] = x[ gid ] + y[ gid ];
}
return;
}
int main( void )
{
/* ---------------------------------------------------------------------- */
/* prepare the host vectors: */
int32_t const N = int32_t{ 10000 };
std::vector< double > x( N, double{ 0.0 } );
std::vector< double > y( N, double{ 0.0 } );
std::vector< double > z( N, double{ 0.0 } );
std::mt19937_64 prng( 20181205u );
std::uniform_real_distribution< double >
dist( double{ -10. }, double{ +10. } );
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
x[ ii ] = dist( prng );
y[ ii ] = dist( prng );
}
cudaError_t cu_err;
/* --------------------------------------------------------------------- */
/* use the "default" / "first" Cuda device for the program: */
int device = int{ 0 };
::cudaGetDevice( &device );
cu_err = ::cudaDeviceSynchronize();
assert( cu_err == ::cudaSuccess );
/* --------------------------------------------------------------------- */
/* Allocate the buffers on the device */
/* x_arg, y_arg, z_arg ... handles on the host side managing buffers in *
* the device memory */
double* x_arg = nullptr;
double* y_arg = nullptr;
double* z_arg = nullptr;
::cudaMalloc( &x_arg, sizeof( double ) * N );
::cudaMalloc( &y_arg, sizeof( double ) * N );
::cudaMalloc( &z_arg, sizeof( double ) * N );
/* --------------------------------------------------------------------- */
/* Transfer x and y from host to device */
::cudaMemcpy( x_arg, x.data(), sizeof( double ) * N, cudaMemcpyHostToDevice );
::cudaMemcpy( y_arg, y.data(), sizeof( double ) * N, cudaMemcpyHostToDevice );
/* --------------------------------------------------------------------- */
/* execute kernel on the device */
int32_t const threads_per_block = int32_t{ 128 };
int32_t const num_blocks =
( N + threads_per_block - int32_t{ 1 } ) / threads_per_block;
add_vec_kernel<<< num_blocks, threads_per_block >>>( x_arg, y_arg, z_arg, N );
cu_err = ::cudaPeekAtLastError();
assert( cu_err == ::cudaSuccess );
/* -------------------------------------------------------------------- */
/* transfer the result from the device buffer to the host buffer */
::cudaMemcpy( z.data(), z_arg, sizeof( double ) * N, cudaMemcpyDeviceToHost );
/* ------------------------------------------------------------------- */
/* verify that the result is correct */
bool success = true;
double const EPS = std::numeric_limits< double >::epsilon();
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
if( std::fabs( ( x[ ii ] + y[ ii ] ) - z[ ii ] ) > EPS )
{
success = false;
break;
}
}
std::cout << "Success: " << std::boolalpha << success << std::endl;
/* -------------------------------------------------------------------- */
/* Clean-up */
::cudaFree( x_arg );
::cudaFree( y_arg );
::cudaFree( z_arg );
return 0;
}
/* end: */
|
.file "tmpxft_0014d66f_00000000-6_vec_add_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4756:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4756:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14add_vec_kernelPKdS0_PdiPKdS0_Pdi
.type _Z41__device_stub__Z14add_vec_kernelPKdS0_PdiPKdS0_Pdi, @function
_Z41__device_stub__Z14add_vec_kernelPKdS0_PdiPKdS0_Pdi:
.LFB4778:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14add_vec_kernelPKdS0_Pdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4778:
.size _Z41__device_stub__Z14add_vec_kernelPKdS0_PdiPKdS0_Pdi, .-_Z41__device_stub__Z14add_vec_kernelPKdS0_PdiPKdS0_Pdi
.globl _Z14add_vec_kernelPKdS0_Pdi
.type _Z14add_vec_kernelPKdS0_Pdi, @function
_Z14add_vec_kernelPKdS0_Pdi:
.LFB4779:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14add_vec_kernelPKdS0_PdiPKdS0_Pdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4779:
.size _Z14add_vec_kernelPKdS0_Pdi, .-_Z14add_vec_kernelPKdS0_Pdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14add_vec_kernelPKdS0_Pdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4781:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14add_vec_kernelPKdS0_Pdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4781:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB5107:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE5107:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv:
.LFB5536:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1248(%rdi), %r9
movq %rdi, %rcx
movabsq $-5403634167711393303, %r8
.L21:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 1248(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L21
leaq 1240(%rdi), %r8
movabsq $-5403634167711393303, %rsi
.L23:
movq 1248(%rdx), %rax
andq $-2147483648, %rax
movq 1256(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1248(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L23
movq 2488(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 1240(%rdi), %rdx
andl $1, %eax
movabsq $-5403634167711393303, %rcx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 2488(%rdi)
movq $0, 2496(%rdi)
ret
.cfi_endproc
.LFE5536:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.section .text._ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_,"axG",@progbits,_ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_,comdat
.weak _ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
.type _ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_, @function
_ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_:
.LFB5495:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $311, 2496(%rdi)
ja .L34
.L28:
movq 2496(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 2496(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $29, %rdx
movabsq $6148914691236517205, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
salq $17, %rdx
movabsq $8202884508482404352, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
salq $37, %rdx
movabsq $-2270628950310912, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
shrq $43, %rdx
xorq %rdx, %rax
js .L29
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L30:
pxor %xmm1, %xmm1
addsd %xmm1, %xmm0
mulsd .LC3(%rip), %xmm0
comisd .LC4(%rip), %xmm0
jnb .L35
.L27:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
jmp .L28
.L29:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L30
.L35:
movsd .LC1(%rip), %xmm0
jmp .L27
.cfi_endproc
.LFE5495:
.size _ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_, .-_ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
.section .rodata.str1.1
.LC9:
.string "Success: "
.text
.globl main
.type main, @function
main:
.LFB4753:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4753
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $2672, %rsp
.cfi_def_cfa_offset 2720
movq %fs:40, %rax
movq %rax, 2664(%rsp)
xorl %eax, %eax
movl $80000, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 64(%rsp)
leaq 80000(%rax), %rdx
movq %rdx, 80(%rsp)
.L37:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L37
movq %rdx, 72(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $80000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbp
movq %rax, 96(%rsp)
leaq 80000(%rax), %rdx
movq %rdx, 112(%rsp)
.L38:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L38
movq %rdx, 104(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movl $80000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %r12
movq %rax, 128(%rsp)
leaq 80000(%rax), %rdx
movq %rdx, 144(%rsp)
.L39:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L39
movq %rdx, 136(%rsp)
movq $20181205, 160(%rsp)
movl $1, %ecx
movabsq $6364136223846793005, %r8
movabsq $945986875574848801, %rdi
.L40:
movq 152(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $62, %rdx
xorq %rdx, %rax
imulq %r8, %rax
movq %rax, %rsi
movq %rcx, %rdx
shrq $3, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $312, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addq %rsi, %rax
movq %rax, 160(%rsp,%rcx,8)
addq $1, %rcx
cmpq $312, %rcx
jne .L40
movq $312, 2656(%rsp)
movl $0, %r13d
leaq 160(%rsp), %r14
.L41:
movq %r14, %rdi
call _ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
mulsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, (%rbx,%r13)
movq %r14, %rdi
call _ZSt18generate_canonicalIdLm53ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
mulsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 0(%rbp,%r13)
addq $8, %r13
cmpq $80000, %r13
jne .L41
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
.LEHB3:
call cudaGetDevice@PLT
call cudaDeviceSynchronize@PLT
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
leaq 16(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $79, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movl $10000, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z41__device_stub__Z14add_vec_kernelPKdS0_PdiPKdS0_Pdi
.L42:
call cudaPeekAtLastError@PLT
movl $2, %ecx
movl $80000, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %eax
movq .LC7(%rip), %xmm2
movsd .LC8(%rip), %xmm1
.L44:
movsd (%rbx,%rax), %xmm0
addsd 0(%rbp,%rax), %xmm0
subsd (%r12,%rax), %xmm0
andpd %xmm2, %xmm0
comisd %xmm1, %xmm0
ja .L50
addq $8, %rax
cmpq $80000, %rax
jne .L44
movl $1, %ebx
jmp .L43
.L50:
movl $0, %ebx
.L43:
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq %rdi, %rsi
addq -24(%rax), %rsi
orl $1, 24(%rsi)
movzbl %bl, %esi
call _ZNSo9_M_insertIbEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 128(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 2664(%rsp), %rax
subq %fs:40, %rax
jne .L62
movl $0, %eax
addq $2672, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 128(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L46:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L47:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 2664(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L52:
endbr64
movq %rax, %rbx
jmp .L46
.L51:
endbr64
movq %rax, %rbx
jmp .L47
.L48:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4753:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4753:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4753-.LLSDACSB4753
.LLSDACSB4753:
.uleb128 .LEHB0-.LFB4753
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4753
.uleb128 .LEHE1-.LEHB1
.uleb128 .L51-.LFB4753
.uleb128 0
.uleb128 .LEHB2-.LFB4753
.uleb128 .LEHE2-.LEHB2
.uleb128 .L52-.LFB4753
.uleb128 0
.uleb128 .LEHB3-.LFB4753
.uleb128 .LEHE3-.LEHB3
.uleb128 .L53-.LFB4753
.uleb128 0
.uleb128 .LEHB4-.LFB4753
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4753:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1
.long 1072693247
.align 8
.LC3:
.long 0
.long 1005584384
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long 0
.long 1077149696
.align 8
.LC6:
.long 0
.long 1076101120
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC8:
.long 0
.long 1018167296
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cassert>
#include <cmath>
#include <cstddef>
#include <cstdint>
#include <cstdlib>
#include <iostream>
#include <limits>
#include <random>
#include <vector>
#include <cuda_runtime_api.h>
#include <cuda.h>
/* Define the kernel function: */
__global__ void add_vec_kernel(
double const* __restrict__ x, double const* __restrict__ y,
double* __restrict__ z, int const n )
{
/* blockIdx, blockDim and threadIdx are variables describing the
* dimensions of the "grid" which are automatically provided by the
* Cuda runtime */
int const gid = blockIdx.x * blockDim.x + threadIdx.x;
if( gid < n )
{
z[ gid ] = x[ gid ] + y[ gid ];
}
return;
}
int main( void )
{
/* ---------------------------------------------------------------------- */
/* prepare the host vectors: */
int32_t const N = int32_t{ 10000 };
std::vector< double > x( N, double{ 0.0 } );
std::vector< double > y( N, double{ 0.0 } );
std::vector< double > z( N, double{ 0.0 } );
std::mt19937_64 prng( 20181205u );
std::uniform_real_distribution< double >
dist( double{ -10. }, double{ +10. } );
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
x[ ii ] = dist( prng );
y[ ii ] = dist( prng );
}
cudaError_t cu_err;
/* --------------------------------------------------------------------- */
/* use the "default" / "first" Cuda device for the program: */
int device = int{ 0 };
::cudaGetDevice( &device );
cu_err = ::cudaDeviceSynchronize();
assert( cu_err == ::cudaSuccess );
/* --------------------------------------------------------------------- */
/* Allocate the buffers on the device */
/* x_arg, y_arg, z_arg ... handles on the host side managing buffers in *
* the device memory */
double* x_arg = nullptr;
double* y_arg = nullptr;
double* z_arg = nullptr;
::cudaMalloc( &x_arg, sizeof( double ) * N );
::cudaMalloc( &y_arg, sizeof( double ) * N );
::cudaMalloc( &z_arg, sizeof( double ) * N );
/* --------------------------------------------------------------------- */
/* Transfer x and y from host to device */
::cudaMemcpy( x_arg, x.data(), sizeof( double ) * N, cudaMemcpyHostToDevice );
::cudaMemcpy( y_arg, y.data(), sizeof( double ) * N, cudaMemcpyHostToDevice );
/* --------------------------------------------------------------------- */
/* execute kernel on the device */
int32_t const threads_per_block = int32_t{ 128 };
int32_t const num_blocks =
( N + threads_per_block - int32_t{ 1 } ) / threads_per_block;
add_vec_kernel<<< num_blocks, threads_per_block >>>( x_arg, y_arg, z_arg, N );
cu_err = ::cudaPeekAtLastError();
assert( cu_err == ::cudaSuccess );
/* -------------------------------------------------------------------- */
/* transfer the result from the device buffer to the host buffer */
::cudaMemcpy( z.data(), z_arg, sizeof( double ) * N, cudaMemcpyDeviceToHost );
/* ------------------------------------------------------------------- */
/* verify that the result is correct */
bool success = true;
double const EPS = std::numeric_limits< double >::epsilon();
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
if( std::fabs( ( x[ ii ] + y[ ii ] ) - z[ ii ] ) > EPS )
{
success = false;
break;
}
}
std::cout << "Success: " << std::boolalpha << success << std::endl;
/* -------------------------------------------------------------------- */
/* Clean-up */
::cudaFree( x_arg );
::cudaFree( y_arg );
::cudaFree( z_arg );
return 0;
}
/* end: */
|
#include <cassert>
#include <cmath>
#include <cstddef>
#include <cstdint>
#include <cstdlib>
#include <iostream>
#include <limits>
#include <random>
#include <vector>
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
/* Define the kernel function: */
__global__ void add_vec_kernel(
double const* __restrict__ x, double const* __restrict__ y,
double* __restrict__ z, int const n )
{
/* blockIdx, blockDim and threadIdx are variables describing the
* dimensions of the "grid" which are automatically provided by the
* Cuda runtime */
int const gid = blockIdx.x * blockDim.x + threadIdx.x;
if( gid < n )
{
z[ gid ] = x[ gid ] + y[ gid ];
}
return;
}
int main( void )
{
/* ---------------------------------------------------------------------- */
/* prepare the host vectors: */
int32_t const N = int32_t{ 10000 };
std::vector< double > x( N, double{ 0.0 } );
std::vector< double > y( N, double{ 0.0 } );
std::vector< double > z( N, double{ 0.0 } );
std::mt19937_64 prng( 20181205u );
std::uniform_real_distribution< double >
dist( double{ -10. }, double{ +10. } );
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
x[ ii ] = dist( prng );
y[ ii ] = dist( prng );
}
hipError_t cu_err;
/* --------------------------------------------------------------------- */
/* use the "default" / "first" Cuda device for the program: */
int device = int{ 0 };
::hipGetDevice( &device );
cu_err = ::hipDeviceSynchronize();
assert( cu_err == ::hipSuccess );
/* --------------------------------------------------------------------- */
/* Allocate the buffers on the device */
/* x_arg, y_arg, z_arg ... handles on the host side managing buffers in *
* the device memory */
double* x_arg = nullptr;
double* y_arg = nullptr;
double* z_arg = nullptr;
::hipMalloc( &x_arg, sizeof( double ) * N );
::hipMalloc( &y_arg, sizeof( double ) * N );
::hipMalloc( &z_arg, sizeof( double ) * N );
/* --------------------------------------------------------------------- */
/* Transfer x and y from host to device */
::hipMemcpy( x_arg, x.data(), sizeof( double ) * N, hipMemcpyHostToDevice );
::hipMemcpy( y_arg, y.data(), sizeof( double ) * N, hipMemcpyHostToDevice );
/* --------------------------------------------------------------------- */
/* execute kernel on the device */
int32_t const threads_per_block = int32_t{ 128 };
int32_t const num_blocks =
( N + threads_per_block - int32_t{ 1 } ) / threads_per_block;
add_vec_kernel<<< num_blocks, threads_per_block >>>( x_arg, y_arg, z_arg, N );
cu_err = ::hipPeekAtLastError();
assert( cu_err == ::hipSuccess );
/* -------------------------------------------------------------------- */
/* transfer the result from the device buffer to the host buffer */
::hipMemcpy( z.data(), z_arg, sizeof( double ) * N, hipMemcpyDeviceToHost );
/* ------------------------------------------------------------------- */
/* verify that the result is correct */
bool success = true;
double const EPS = std::numeric_limits< double >::epsilon();
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
if( std::fabs( ( x[ ii ] + y[ ii ] ) - z[ ii ] ) > EPS )
{
success = false;
break;
}
}
std::cout << "Success: " << std::boolalpha << success << std::endl;
/* -------------------------------------------------------------------- */
/* Clean-up */
::hipFree( x_arg );
::hipFree( y_arg );
::hipFree( z_arg );
return 0;
}
/* end: */
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <cassert>
#include <cmath>
#include <cstddef>
#include <cstdint>
#include <cstdlib>
#include <iostream>
#include <limits>
#include <random>
#include <vector>
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
/* Define the kernel function: */
__global__ void add_vec_kernel(
double const* __restrict__ x, double const* __restrict__ y,
double* __restrict__ z, int const n )
{
/* blockIdx, blockDim and threadIdx are variables describing the
* dimensions of the "grid" which are automatically provided by the
* Cuda runtime */
int const gid = blockIdx.x * blockDim.x + threadIdx.x;
if( gid < n )
{
z[ gid ] = x[ gid ] + y[ gid ];
}
return;
}
int main( void )
{
/* ---------------------------------------------------------------------- */
/* prepare the host vectors: */
int32_t const N = int32_t{ 10000 };
std::vector< double > x( N, double{ 0.0 } );
std::vector< double > y( N, double{ 0.0 } );
std::vector< double > z( N, double{ 0.0 } );
std::mt19937_64 prng( 20181205u );
std::uniform_real_distribution< double >
dist( double{ -10. }, double{ +10. } );
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
x[ ii ] = dist( prng );
y[ ii ] = dist( prng );
}
hipError_t cu_err;
/* --------------------------------------------------------------------- */
/* use the "default" / "first" Cuda device for the program: */
int device = int{ 0 };
::hipGetDevice( &device );
cu_err = ::hipDeviceSynchronize();
assert( cu_err == ::hipSuccess );
/* --------------------------------------------------------------------- */
/* Allocate the buffers on the device */
/* x_arg, y_arg, z_arg ... handles on the host side managing buffers in *
* the device memory */
double* x_arg = nullptr;
double* y_arg = nullptr;
double* z_arg = nullptr;
::hipMalloc( &x_arg, sizeof( double ) * N );
::hipMalloc( &y_arg, sizeof( double ) * N );
::hipMalloc( &z_arg, sizeof( double ) * N );
/* --------------------------------------------------------------------- */
/* Transfer x and y from host to device */
::hipMemcpy( x_arg, x.data(), sizeof( double ) * N, hipMemcpyHostToDevice );
::hipMemcpy( y_arg, y.data(), sizeof( double ) * N, hipMemcpyHostToDevice );
/* --------------------------------------------------------------------- */
/* execute kernel on the device */
int32_t const threads_per_block = int32_t{ 128 };
int32_t const num_blocks =
( N + threads_per_block - int32_t{ 1 } ) / threads_per_block;
add_vec_kernel<<< num_blocks, threads_per_block >>>( x_arg, y_arg, z_arg, N );
cu_err = ::hipPeekAtLastError();
assert( cu_err == ::hipSuccess );
/* -------------------------------------------------------------------- */
/* transfer the result from the device buffer to the host buffer */
::hipMemcpy( z.data(), z_arg, sizeof( double ) * N, hipMemcpyDeviceToHost );
/* ------------------------------------------------------------------- */
/* verify that the result is correct */
bool success = true;
double const EPS = std::numeric_limits< double >::epsilon();
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
if( std::fabs( ( x[ ii ] + y[ ii ] ) - z[ ii ] ) > EPS )
{
success = false;
break;
}
}
std::cout << "Success: " << std::boolalpha << success << std::endl;
/* -------------------------------------------------------------------- */
/* Clean-up */
::hipFree( x_arg );
::hipFree( y_arg );
::hipFree( z_arg );
return 0;
}
/* end: */
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14add_vec_kernelPKdS0_Pdi
.globl _Z14add_vec_kernelPKdS0_Pdi
.p2align 8
.type _Z14add_vec_kernelPKdS0_Pdi,@function
_Z14add_vec_kernelPKdS0_Pdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14add_vec_kernelPKdS0_Pdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14add_vec_kernelPKdS0_Pdi, .Lfunc_end0-_Z14add_vec_kernelPKdS0_Pdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14add_vec_kernelPKdS0_Pdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14add_vec_kernelPKdS0_Pdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <cassert>
#include <cmath>
#include <cstddef>
#include <cstdint>
#include <cstdlib>
#include <iostream>
#include <limits>
#include <random>
#include <vector>
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
/* Define the kernel function: */
__global__ void add_vec_kernel(
double const* __restrict__ x, double const* __restrict__ y,
double* __restrict__ z, int const n )
{
/* blockIdx, blockDim and threadIdx are variables describing the
* dimensions of the "grid" which are automatically provided by the
* Cuda runtime */
int const gid = blockIdx.x * blockDim.x + threadIdx.x;
if( gid < n )
{
z[ gid ] = x[ gid ] + y[ gid ];
}
return;
}
int main( void )
{
/* ---------------------------------------------------------------------- */
/* prepare the host vectors: */
int32_t const N = int32_t{ 10000 };
std::vector< double > x( N, double{ 0.0 } );
std::vector< double > y( N, double{ 0.0 } );
std::vector< double > z( N, double{ 0.0 } );
std::mt19937_64 prng( 20181205u );
std::uniform_real_distribution< double >
dist( double{ -10. }, double{ +10. } );
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
x[ ii ] = dist( prng );
y[ ii ] = dist( prng );
}
hipError_t cu_err;
/* --------------------------------------------------------------------- */
/* use the "default" / "first" Cuda device for the program: */
int device = int{ 0 };
::hipGetDevice( &device );
cu_err = ::hipDeviceSynchronize();
assert( cu_err == ::hipSuccess );
/* --------------------------------------------------------------------- */
/* Allocate the buffers on the device */
/* x_arg, y_arg, z_arg ... handles on the host side managing buffers in *
* the device memory */
double* x_arg = nullptr;
double* y_arg = nullptr;
double* z_arg = nullptr;
::hipMalloc( &x_arg, sizeof( double ) * N );
::hipMalloc( &y_arg, sizeof( double ) * N );
::hipMalloc( &z_arg, sizeof( double ) * N );
/* --------------------------------------------------------------------- */
/* Transfer x and y from host to device */
::hipMemcpy( x_arg, x.data(), sizeof( double ) * N, hipMemcpyHostToDevice );
::hipMemcpy( y_arg, y.data(), sizeof( double ) * N, hipMemcpyHostToDevice );
/* --------------------------------------------------------------------- */
/* execute kernel on the device */
int32_t const threads_per_block = int32_t{ 128 };
int32_t const num_blocks =
( N + threads_per_block - int32_t{ 1 } ) / threads_per_block;
add_vec_kernel<<< num_blocks, threads_per_block >>>( x_arg, y_arg, z_arg, N );
cu_err = ::hipPeekAtLastError();
assert( cu_err == ::hipSuccess );
/* -------------------------------------------------------------------- */
/* transfer the result from the device buffer to the host buffer */
::hipMemcpy( z.data(), z_arg, sizeof( double ) * N, hipMemcpyDeviceToHost );
/* ------------------------------------------------------------------- */
/* verify that the result is correct */
bool success = true;
double const EPS = std::numeric_limits< double >::epsilon();
for( int32_t ii = int32_t{ 0 } ; ii < N ; ++ii )
{
if( std::fabs( ( x[ ii ] + y[ ii ] ) - z[ ii ] ) > EPS )
{
success = false;
break;
}
}
std::cout << "Success: " << std::boolalpha << success << std::endl;
/* -------------------------------------------------------------------- */
/* Clean-up */
::hipFree( x_arg );
::hipFree( y_arg );
::hipFree( z_arg );
return 0;
}
/* end: */
|
.text
.file "vec_add_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__add_vec_kernelPKdS0_Pdi # -- Begin function _Z29__device_stub__add_vec_kernelPKdS0_Pdi
.p2align 4, 0x90
.type _Z29__device_stub__add_vec_kernelPKdS0_Pdi,@function
_Z29__device_stub__add_vec_kernelPKdS0_Pdi: # @_Z29__device_stub__add_vec_kernelPKdS0_Pdi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14add_vec_kernelPKdS0_Pdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__add_vec_kernelPKdS0_Pdi, .Lfunc_end0-_Z29__device_stub__add_vec_kernelPKdS0_Pdi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x5f800000 # float 1.84467441E+19
.LCPI1_1:
.long 0x40000000 # float 2
.LCPI1_2:
.long 0x5f000000 # float 9.22337203E+18
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x3ff0000000000000 # double 1
.LCPI1_6:
.quad 0x4034000000000000 # double 20
.LCPI1_7:
.quad 0xc024000000000000 # double -10
.LCPI1_9:
.quad 0x3cb0000000000000 # double 2.2204460492503131E-16
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_4:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_5:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.LCPI1_8:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2744, %rsp # imm = 0xAB8
.cfi_def_cfa_offset 2800
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80000, %edi # imm = 0x13880
callq _Znwm
movq %rax, %rbx
movl $80000, %edx # imm = 0x13880
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
movl $80000, %edi # imm = 0x13880
callq _Znwm
.Ltmp1:
# %bb.1: # %.lr.ph.i.i.i.i.i.i.i.i.i34.preheader
movq %rax, %r14
movl $80000, %edx # imm = 0x13880
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp3:
movl $80000, %edi # imm = 0x13880
callq _Znwm
.Ltmp4:
# %bb.2: # %.lr.ph.i.i.i.i.i.i.i.i.i39.preheader
movq %rax, %r15
movl $80000, %edx # imm = 0x13880
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq $20181205, 240(%rsp) # imm = 0x133F0D5
movl $1, %eax
movl $20181205, %esi # imm = 0x133F0D5
movabsq $6364136223846793005, %rcx # imm = 0x5851F42D4C957F2D
movq %rsi, %rdx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
shrq $62, %rdx
xorq %rsi, %rdx
imulq %rcx, %rdx
addq %rax, %rdx
movq %rdx, 240(%rsp,%rax,8)
incq %rax
movq %rdx, %rsi
cmpq $312, %rax # imm = 0x138
jne .LBB1_3
# %bb.4: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEC2Em.exit
movq $312, 2736(%rsp) # imm = 0x138
xorl %ebp, %ebp
leaq 240(%rsp), %r12
.p2align 4, 0x90
.LBB1_5: # =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_11 Depth 2
flds .LCPI1_0(%rip)
fstpt (%rsp)
callq logl
fstpt 24(%rsp) # 10-byte Folded Spill
flds .LCPI1_1(%rip)
fstpt (%rsp)
callq logl
fldt 24(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI1_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 22(%rsp)
movzwl 22(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 54(%rsp)
fldcw 54(%rsp)
fistpll 128(%rsp)
fldcw 22(%rsp)
shlq $63, %rcx
xorq 128(%rsp), %rcx
leaq 52(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %r13
cmpq $1, %rax
adcq $0, %r13
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp6:
movq %r12, %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp7:
# %bb.7: # %.noexc44
# in Loop: Header=BB1_6 Depth=2
movq %rax, %xmm0
punpckldq .LCPI1_4(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_5(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm0, 120(%rsp)
fldl 120(%rsp)
fmuls .LCPI1_0(%rip)
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
fstpl 112(%rsp)
movsd 112(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
decq %r13
jne .LBB1_6
# %bb.8: # in Loop: Header=BB1_5 Depth=1
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd 40(%rsp), %xmm1 # 8-byte Folded Reload
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm0, %xmm1
jae .LBB1_9
.LBB1_10: # %_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEEEdRT_.exit
# in Loop: Header=BB1_5 Depth=1
mulsd .LCPI1_6(%rip), %xmm1
addsd .LCPI1_7(%rip), %xmm1
movsd %xmm1, (%rbx,%rbp,8)
flds .LCPI1_0(%rip)
fstpt (%rsp)
callq logl
fstpt 24(%rsp) # 10-byte Folded Spill
flds .LCPI1_1(%rip)
fstpt (%rsp)
callq logl
fldt 24(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI1_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 20(%rsp)
movzwl 20(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 52(%rsp)
fldcw 52(%rsp)
fistpll 104(%rsp)
fldcw 20(%rsp)
shlq $63, %rcx
xorq 104(%rsp), %rcx
leaq 52(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %r13
cmpq $1, %rax
adcq $0, %r13
xorpd %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp9:
movq %r12, %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp10:
# %bb.12: # %.noexc51
# in Loop: Header=BB1_11 Depth=2
movq %rax, %xmm0
punpckldq .LCPI1_4(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_5(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm0, 96(%rsp)
fldl 96(%rsp)
fmuls .LCPI1_0(%rip)
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
fstpl 88(%rsp)
movsd 88(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
decq %r13
jne .LBB1_11
# %bb.13: # in Loop: Header=BB1_5 Depth=1
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
ucomisd .LCPI1_3(%rip), %xmm0
jae .LBB1_14
.LBB1_15: # %_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEEEdRT_.exit52
# in Loop: Header=BB1_5 Depth=1
mulsd .LCPI1_6(%rip), %xmm0
addsd .LCPI1_7(%rip), %xmm0
movsd %xmm0, (%r14,%rbp,8)
incq %rbp
cmpq $10000, %rbp # imm = 0x2710
jne .LBB1_5
jmp .LBB1_16
.LBB1_9: # in Loop: Header=BB1_5 Depth=1
xorpd %xmm1, %xmm1
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
callq nextafter
movapd %xmm0, %xmm1
jmp .LBB1_10
.LBB1_14: # in Loop: Header=BB1_5 Depth=1
xorpd %xmm1, %xmm1
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
callq nextafter
jmp .LBB1_15
.LBB1_16:
movl $0, 80(%rsp)
.Ltmp12:
leaq 80(%rsp), %rdi
callq hipGetDevice
.Ltmp13:
# %bb.17:
.Ltmp14:
callq hipDeviceSynchronize
.Ltmp15:
# %bb.18:
movq $0, 72(%rsp)
movq $0, 64(%rsp)
movq $0, 56(%rsp)
.Ltmp17:
leaq 72(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
.Ltmp18:
# %bb.19: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
.Ltmp19:
leaq 64(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
.Ltmp20:
# %bb.20: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit55
.Ltmp21:
leaq 56(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
.Ltmp22:
# %bb.21: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit57
movq 72(%rsp), %rdi
.Ltmp23:
movl $80000, %edx # imm = 0x13880
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp24:
# %bb.22:
movq 64(%rsp), %rdi
.Ltmp25:
movl $80000, %edx # imm = 0x13880
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp26:
# %bb.23:
.Ltmp28:
movabsq $4294967375, %rdi # imm = 0x10000004F
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp29:
# %bb.24:
testl %eax, %eax
jne .LBB1_27
# %bb.25:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movl $10000, 84(%rsp) # imm = 0x2710
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 84(%rsp), %rax
movq %rax, 232(%rsp)
.Ltmp30:
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp31:
# %bb.26: # %.noexc58
movq 144(%rsp), %rax
movq 136(%rsp), %rdi
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
.Ltmp32:
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 208(%rsp), %r9
movl $_Z14add_vec_kernelPKdS0_Pdi, %edi
callq hipLaunchKernel
.Ltmp33:
.LBB1_27:
.Ltmp34:
callq hipPeekAtLastError
.Ltmp35:
# %bb.28:
movq 56(%rsp), %rsi
.Ltmp36:
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp37:
# %bb.29: # %.preheader.preheader
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
addsd (%r14), %xmm0
subsd (%r15), %xmm0
andpd .LCPI1_8(%rip), %xmm0
ucomisd .LCPI1_9(%rip), %xmm0
jbe .LBB1_38
# %bb.30:
xorl %ebp, %ebp
jmp .LBB1_42
.LBB1_38: # %.lr.ph.preheader
xorl %ecx, %ecx
movapd .LCPI1_8(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI1_9(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_39: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rcx, %rax
cmpq $9999, %rcx # imm = 0x270F
je .LBB1_41
# %bb.40: # %.preheader
# in Loop: Header=BB1_39 Depth=1
movsd 8(%rbx,%rax,8), %xmm2 # xmm2 = mem[0],zero
addsd 8(%r14,%rax,8), %xmm2
subsd 8(%r15,%rax,8), %xmm2
andpd %xmm0, %xmm2
leaq 1(%rax), %rcx
ucomisd %xmm1, %xmm2
jbe .LBB1_39
.LBB1_41: # %.preheader._crit_edge.loopexit
cmpq $9999, %rax # imm = 0x270F
setae %bpl
.LBB1_42: # %.preheader._crit_edge
.Ltmp39:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp40:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
orl $1, _ZSt4cout+24(%rax)
.Ltmp41:
movzbl %bpl, %esi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIbEERSoT_
.Ltmp42:
# %bb.44: # %_ZNSolsEb.exit
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_45
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_49
# %bb.48:
movzbl 67(%r13), %eax
jmp .LBB1_51
.LBB1_49:
.Ltmp43:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp44:
# %bb.50: # %.noexc76
movq (%r13), %rax
.Ltmp45:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp46:
.LBB1_51: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp47:
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp48:
# %bb.52: # %.noexc78
.Ltmp49:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp50:
# %bb.53: # %_ZNSolsEPFRSoS_E.exit
movq 72(%rsp), %rdi
.Ltmp51:
callq hipFree
.Ltmp52:
# %bb.54:
movq 64(%rsp), %rdi
.Ltmp53:
callq hipFree
.Ltmp54:
# %bb.55:
movq 56(%rsp), %rdi
.Ltmp55:
callq hipFree
.Ltmp56:
# %bb.56: # %_ZNSt6vectorIdSaIdEED2Ev.exit
movq %r15, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $2744, %rsp # imm = 0xAB8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_45:
.cfi_def_cfa_offset 2800
.Ltmp57:
callq _ZSt16__throw_bad_castv
.Ltmp58:
# %bb.46: # %.noexc75
.LBB1_32:
.Ltmp5:
movq %rax, %r12
jmp .LBB1_59
.LBB1_31:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_60
.LBB1_35:
.Ltmp16:
jmp .LBB1_58
.LBB1_37:
.Ltmp38:
jmp .LBB1_58
.LBB1_36:
.Ltmp27:
jmp .LBB1_58
.LBB1_57:
.Ltmp59:
jmp .LBB1_58
.LBB1_33: # %.loopexit
.Ltmp11:
jmp .LBB1_58
.LBB1_34: # %.loopexit.split-lp
.Ltmp8:
.LBB1_58:
movq %rax, %r12
movq %r15, %rdi
callq _ZdlPv
.LBB1_59: # %_ZNSt6vectorIdSaIdEED2Ev.exit71
movq %r14, %rdi
callq _ZdlPv
.LBB1_60: # %_ZNSt6vectorIdSaIdEED2Ev.exit73
movq %rbx, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp15-.Ltmp12 # Call between .Ltmp12 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp26-.Ltmp17 # Call between .Ltmp17 and .Ltmp26
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp37-.Ltmp28 # Call between .Ltmp28 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp58-.Ltmp39 # Call between .Ltmp39 and .Ltmp58
.uleb128 .Ltmp59-.Lfunc_begin0 # jumps to .Ltmp59
.byte 0 # On action: cleanup
.uleb128 .Ltmp58-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp58 # Call between .Ltmp58 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,@function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv: # @_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_startproc
# %bb.0:
cmpq $312, 2496(%rdi) # imm = 0x138
jb .LBB2_6
# %bb.1: # %.preheader.preheader
movabsq $-5403634167711393303, %rax # imm = 0xB5026F5AA96619E9
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 1248(%rdi,%rdx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $156, %rsi
jne .LBB2_2
# %bb.3: # %.preheader.i.preheader
movl $157, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB2_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1256(%rdi,%rcx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $312, %rcx # imm = 0x138
jne .LBB2_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 2488(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 1240(%rdi), %rsi
andl $1, %edx
negq %rdx
andq %rax, %rdx
xorq %rsi, %rdx
movq %rdx, 2488(%rdi)
movq $0, 2496(%rdi)
.LBB2_6:
movq 2496(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 2496(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $29, %rcx
movabsq $22906492245, %rdx # imm = 0x555555555
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
shlq $17, %rax
movabsq $8202884508482404352, %rcx # imm = 0x71D67FFFEDA60000
andq %rax, %rcx
xorq %rdx, %rcx
movl %ecx, %edx
andl $134201207, %edx # imm = 0x7FFBF77
shlq $37, %rdx
xorq %rcx, %rdx
movq %rdx, %rax
shrq $43, %rax
xorq %rdx, %rax
retq
.Lfunc_end2:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, .Lfunc_end2-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14add_vec_kernelPKdS0_Pdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14add_vec_kernelPKdS0_Pdi,@object # @_Z14add_vec_kernelPKdS0_Pdi
.section .rodata,"a",@progbits
.globl _Z14add_vec_kernelPKdS0_Pdi
.p2align 3, 0x0
_Z14add_vec_kernelPKdS0_Pdi:
.quad _Z29__device_stub__add_vec_kernelPKdS0_Pdi
.size _Z14add_vec_kernelPKdS0_Pdi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Success: "
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14add_vec_kernelPKdS0_Pdi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__add_vec_kernelPKdS0_Pdi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z14add_vec_kernelPKdS0_Pdi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z14add_vec_kernelPKdS0_Pdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64.CONSTANT R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e9b00 */
/*00b0*/ LDG.E.64.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e9b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14add_vec_kernelPKdS0_Pdi
.globl _Z14add_vec_kernelPKdS0_Pdi
.p2align 8
.type _Z14add_vec_kernelPKdS0_Pdi,@function
_Z14add_vec_kernelPKdS0_Pdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14add_vec_kernelPKdS0_Pdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14add_vec_kernelPKdS0_Pdi, .Lfunc_end0-_Z14add_vec_kernelPKdS0_Pdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14add_vec_kernelPKdS0_Pdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14add_vec_kernelPKdS0_Pdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "conv2d-transpose-input-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DTransposeInputGrad::Conv2DTransposeInputGrad(Op* y, Op* kernel,
const int strides[], const int input_size[])
: Op("conv2d_transpose_input_grad",
Shape({input_size[0], input_size[1],
input_size[2], input_size[3]}),
{y, kernel})
, m_strides(strides)
{
m_input_size[0] = input_size[0];
m_input_size[1] = input_size[1];
m_input_size[2] = input_size[2];
m_input_size[3] = input_size[3];
}
void Conv2DTransposeInputGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& ckernel = g.compiled(preds()[1]);
Shape out_shape({m_input_size[0], m_input_size[1], m_input_size[2], m_input_size[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int y_size[4] = { cy.out_shape[0], cy.out_shape[1],
cy.out_shape[2], cy.out_shape[3]};
int kernel_size[4] = { ckernel.out_shape[0], ckernel.out_shape[1],
ckernel.out_shape[2], ckernel.out_shape[3]};
auto out_node = rt::Node::op_conv2d_transpose_input_grad(cy.out_data, ckernel.out_data,
m_strides, out_data, y_size,
kernel_size, m_input_size,
{cy.out_node, ckernel.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "conv2d-transpose-input-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DTransposeInputGrad::Conv2DTransposeInputGrad(Op* y, Op* kernel,
const int strides[], const int input_size[])
: Op("conv2d_transpose_input_grad",
Shape({input_size[0], input_size[1],
input_size[2], input_size[3]}),
{y, kernel})
, m_strides(strides)
{
m_input_size[0] = input_size[0];
m_input_size[1] = input_size[1];
m_input_size[2] = input_size[2];
m_input_size[3] = input_size[3];
}
void Conv2DTransposeInputGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& ckernel = g.compiled(preds()[1]);
Shape out_shape({m_input_size[0], m_input_size[1], m_input_size[2], m_input_size[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int y_size[4] = { cy.out_shape[0], cy.out_shape[1],
cy.out_shape[2], cy.out_shape[3]};
int kernel_size[4] = { ckernel.out_shape[0], ckernel.out_shape[1],
ckernel.out_shape[2], ckernel.out_shape[3]};
auto out_node = rt::Node::op_conv2d_transpose_input_grad(cy.out_data, ckernel.out_data,
m_strides, out_data, y_size,
kernel_size, m_input_size,
{cy.out_node, ckernel.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
}
|
.file "tmpxft_00084ede_00000000-6_conv2d-transpose-input-grad.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops24Conv2DTransposeInputGradD2Ev,"axG",@progbits,_ZN3ops24Conv2DTransposeInputGradD5Ev,comdat
.align 2
.weak _ZN3ops24Conv2DTransposeInputGradD2Ev
.type _ZN3ops24Conv2DTransposeInputGradD2Ev, @function
_ZN3ops24Conv2DTransposeInputGradD2Ev:
.LFB5662:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5662:
.size _ZN3ops24Conv2DTransposeInputGradD2Ev, .-_ZN3ops24Conv2DTransposeInputGradD2Ev
.weak _ZN3ops24Conv2DTransposeInputGradD1Ev
.set _ZN3ops24Conv2DTransposeInputGradD1Ev,_ZN3ops24Conv2DTransposeInputGradD2Ev
.section .text._ZN3ops24Conv2DTransposeInputGradD0Ev,"axG",@progbits,_ZN3ops24Conv2DTransposeInputGradD5Ev,comdat
.align 2
.weak _ZN3ops24Conv2DTransposeInputGradD0Ev
.type _ZN3ops24Conv2DTransposeInputGradD0Ev, @function
_ZN3ops24Conv2DTransposeInputGradD0Ev:
.LFB5664:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $136, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5664:
.size _ZN3ops24Conv2DTransposeInputGradD0Ev, .-_ZN3ops24Conv2DTransposeInputGradD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4959:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4959:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4993:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE4993:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5173:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L38
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L38:
ret
.cfi_endproc
.LFE5173:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt12_Vector_baseIiSaIiEED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIiSaIiEED2Ev
.type _ZNSt12_Vector_baseIiSaIiEED2Ev, @function
_ZNSt12_Vector_baseIiSaIiEED2Ev:
.LFB5207:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L44
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L44:
ret
.cfi_endproc
.LFE5207:
.size _ZNSt12_Vector_baseIiSaIiEED2Ev, .-_ZNSt12_Vector_baseIiSaIiEED2Ev
.weak _ZNSt12_Vector_baseIiSaIiEED1Ev
.set _ZNSt12_Vector_baseIiSaIiEED1Ev,_ZNSt12_Vector_baseIiSaIiEED2Ev
.text
.align 2
.globl _ZN3ops24Conv2DTransposeInputGrad7compileEv
.type _ZN3ops24Conv2DTransposeInputGrad7compileEv, @function
_ZN3ops24Conv2DTransposeInputGrad7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB0:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %r14
movq %rax, -200(%rbp)
leaq -128(%rbp), %rdi
movq %rbx, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE0:
movq -128(%rbp), %rax
movq (%rax), %rsi
movq %r14, %rdi
.LEHB1:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE1:
movq %rax, %r12
movq -128(%rbp), %rdi
testq %rdi, %rdi
je .L48
movq -112(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L48:
leaq -128(%rbp), %rdi
movq %rbx, %rsi
.LEHB2:
call _ZN3ops2Op5predsEv@PLT
.LEHE2:
movq -128(%rbp), %rax
movq 8(%rax), %rsi
movq -200(%rbp), %rdi
.LEHB3:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE3:
movq %rax, %r13
movq -128(%rbp), %rdi
testq %rdi, %rdi
je .L49
movq -112(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L49:
movl 124(%rbx), %eax
salq $32, %rax
movl 120(%rbx), %r15d
orq %rax, %r15
movl 132(%rbx), %eax
salq $32, %rax
movl 128(%rbx), %r14d
orq %rax, %r14
movq $0, -128(%rbp)
movq $0, -120(%rbp)
movq $0, -112(%rbp)
movl $16, %edi
.LEHB4:
call _Znwm@PLT
.LEHE4:
movq %rax, -128(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -112(%rbp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rdx, -120(%rbp)
leaq -128(%rbp), %rsi
leaq -192(%rbp), %rdi
.LEHB5:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE5:
jmp .L93
.L84:
endbr64
movq %rax, %rbx
leaq -128(%rbp), %rdi
call _ZNSt12_Vector_baseIiSaIiEED2Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L52:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L93:
movq -128(%rbp), %rdi
testq %rdi, %rdi
je .L53
movq -112(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L53:
leaq -192(%rbp), %rdi
.LEHB7:
call _ZNK3ops5Shape5totalEv@PLT
movslq %eax, %rdi
call _Z12tensor_allocm@PLT
movq %rax, %r14
leaq 64(%r12), %r15
movl $0, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -96(%rbp)
movl $1, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -92(%rbp)
movl $2, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -88(%rbp)
movl $3, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -84(%rbp)
leaq 64(%r13), %r15
movl $0, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -80(%rbp)
movl $1, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -76(%rbp)
movl $2, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -72(%rbp)
movl $3, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
.LEHE7:
movl %eax, -68(%rbp)
movq 56(%r12), %r15
movq 56(%r13), %rax
movq %rax, -208(%rbp)
movq $0, -128(%rbp)
movq $0, -120(%rbp)
movq $0, -112(%rbp)
movl $16, %edi
.LEHB8:
call _Znwm@PLT
.LEHE8:
movq %rax, -128(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -112(%rbp)
movq %r15, (%rax)
movq -208(%rbp), %rcx
movq %rcx, 8(%rax)
movq %rdx, -120(%rbp)
movq 112(%rbx), %rdx
movq 88(%r13), %rsi
movq 88(%r12), %rdi
leaq -128(%rbp), %rax
pushq %rax
leaq 120(%rbx), %rax
pushq %rax
leaq -80(%rbp), %r9
leaq -96(%rbp), %r8
movq %r14, %rcx
.LEHB9:
.cfi_escape 0x2e,0x10
call _ZN2rt4Node30op_conv2d_transpose_input_gradEPKfS2_PKiPfS4_S4_S4_RKSt6vectorIPS0_SaIS7_EE@PLT
.LEHE9:
movq %rax, %r12
addq $16, %rsp
movq -128(%rbp), %rdi
testq %rdi, %rdi
je .L57
movq -112(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L57:
movq $0, -128(%rbp)
movq $0, -120(%rbp)
movq $0, -112(%rbp)
movl $8, %edi
.LEHB10:
.cfi_escape 0x2e,0
call _Znwm@PLT
.LEHE10:
jmp .L94
.L85:
endbr64
movq %rax, %rbx
leaq -128(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L56:
leaq -192(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L76
call __stack_chk_fail@PLT
.L94:
movq %rax, -128(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -112(%rbp)
movq %r14, (%rax)
movq %rdx, -120(%rbp)
movq $0, -160(%rbp)
movq $0, -152(%rbp)
movq $0, -144(%rbp)
movl $8, %edi
.LEHB11:
call _Znwm@PLT
.LEHE11:
movq %rax, -160(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -144(%rbp)
movq %r12, (%rax)
movq %rdx, -152(%rbp)
leaq -128(%rbp), %rcx
leaq -160(%rbp), %rdx
subq $8, %rsp
pushq %r14
leaq -192(%rbp), %r9
movq %r12, %r8
movq %rbx, %rsi
movq -200(%rbp), %rdi
.LEHB12:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE12:
jmp .L95
.L86:
endbr64
movq %rax, %rbx
movq -128(%rbp), %rdi
movq -112(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L56
call _ZdlPvm@PLT
jmp .L56
.L95:
addq $16, %rsp
movq -160(%rbp), %rdi
testq %rdi, %rdi
je .L64
movq -144(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L64:
movq -128(%rbp), %rdi
testq %rdi, %rdi
je .L65
movq -112(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L65:
movq -192(%rbp), %rdi
testq %rdi, %rdi
je .L47
movq -176(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L47:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L96
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L87:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -160(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L63:
movq -128(%rbp), %rdi
movq -112(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L56
call _ZdlPvm@PLT
jmp .L56
.L78:
endbr64
movq %rax, %rbx
leaq -128(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L68
call __stack_chk_fail@PLT
.L68:
movq %rbx, %rdi
.LEHB13:
call _Unwind_Resume@PLT
.L79:
endbr64
movq %rax, %rbx
leaq -128(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L70
call __stack_chk_fail@PLT
.L70:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L80:
endbr64
movq %rax, %rbx
leaq -128(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L72
call __stack_chk_fail@PLT
.L72:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L82:
endbr64
movq %rax, %rbx
leaq -128(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L56
.L83:
endbr64
movq %rax, %rbx
leaq -160(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L63
.L81:
endbr64
movq %rax, %rbx
jmp .L56
.L76:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE13:
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB0-.LFB4617
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4617
.uleb128 .LEHE1-.LEHB1
.uleb128 .L78-.LFB4617
.uleb128 0
.uleb128 .LEHB2-.LFB4617
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4617
.uleb128 .LEHE3-.LEHB3
.uleb128 .L79-.LFB4617
.uleb128 0
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 .L84-.LFB4617
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L80-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L81-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 .L85-.LFB4617
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L82-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 .L86-.LFB4617
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 .L87-.LFB4617
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 .L83-.LFB4617
.uleb128 0
.uleb128 .LEHB13-.LFB4617
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops24Conv2DTransposeInputGrad7compileEv, .-_ZN3ops24Conv2DTransposeInputGrad7compileEv
.align 2
.globl _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.type _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_, @function
_ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $192, %rsp
.cfi_def_cfa_offset 240
movq %rdi, %rbp
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %r14
movq %r8, %rbx
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $16, %edi
.LEHB14:
call _Znwm@PLT
.LEHE14:
movq %rax, 80(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 96(%rsp)
movq %r13, (%rax)
movq %r12, 8(%rax)
movq %rdx, 88(%rsp)
movl 4(%rbx), %eax
salq $32, %rax
movl (%rbx), %r13d
orq %rax, %r13
movl 12(%rbx), %eax
salq $32, %rax
movl 8(%rbx), %r12d
orq %rax, %r12
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $16, %edi
.LEHB15:
call _Znwm@PLT
.LEHE15:
movq %rax, 48(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 64(%rsp)
movq %r13, (%rax)
movq %r12, 8(%rax)
movq %rdx, 56(%rsp)
leaq 48(%rsp), %rsi
leaq 16(%rsp), %rdi
.LEHB16:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE16:
jmp .L123
.L118:
endbr64
movq %rax, %rbx
movq 80(%rsp), %rdi
movq 96(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L101
call _ZdlPvm@PLT
.L101:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L113
call __stack_chk_fail@PLT
.L119:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt12_Vector_baseIiSaIiEED2Ev
.L104:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L101
.L123:
leaq 144(%rsp), %rdi
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $27, 8(%rsp)
leaq 8(%rsp), %rsi
movl $0, %edx
.LEHB17:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE17:
movq %rax, 144(%rsp)
movq 8(%rsp), %rdx
movq %rdx, 160(%rsp)
movabsq $8385531199085244259, %rsi
movabsq $7310309148916081010, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movabsq $7955995106059710579, %rsi
movabsq $7233188264842392944, %rdi
movq %rsi, 11(%rax)
movq %rdi, 19(%rax)
movq %rdx, 152(%rsp)
movq 144(%rsp), %rax
movb $0, (%rax,%rdx)
leaq 80(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 112(%rsp), %r8
movq %rbp, %rdi
.LEHB18:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE18:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L105
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L105:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L106
movq 32(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L106:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L107
movq 64(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L107:
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .L108
movq 96(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L108:
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .L109
movq 128(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L109:
leaq 16+_ZTVN3ops24Conv2DTransposeInputGradE(%rip), %rax
movq %rax, 0(%rbp)
movq %r14, 112(%rbp)
movl (%rbx), %eax
movl %eax, 120(%rbp)
movl 4(%rbx), %eax
movl %eax, 124(%rbp)
movl 8(%rbx), %eax
movl %eax, 128(%rbp)
movl 12(%rbx), %eax
movl %eax, 132(%rbp)
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L124
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L117:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L111:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L112:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
jmp .L104
.L116:
endbr64
movq %rax, %rbx
jmp .L111
.L115:
endbr64
movq %rax, %rbx
jmp .L112
.L113:
movq %rbx, %rdi
.LEHB19:
call _Unwind_Resume@PLT
.LEHE19:
.L124:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.section .gcc_except_table
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB14-.LFB4615
.uleb128 .LEHE14-.LEHB14
.uleb128 .L118-.LFB4615
.uleb128 0
.uleb128 .LEHB15-.LFB4615
.uleb128 .LEHE15-.LEHB15
.uleb128 .L119-.LFB4615
.uleb128 0
.uleb128 .LEHB16-.LFB4615
.uleb128 .LEHE16-.LEHB16
.uleb128 .L115-.LFB4615
.uleb128 0
.uleb128 .LEHB17-.LFB4615
.uleb128 .LEHE17-.LEHB17
.uleb128 .L116-.LFB4615
.uleb128 0
.uleb128 .LEHB18-.LFB4615
.uleb128 .LEHE18-.LEHB18
.uleb128 .L117-.LFB4615
.uleb128 0
.uleb128 .LEHB19-.LFB4615
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_, .-_ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.globl _ZN3ops24Conv2DTransposeInputGradC1EPNS_2OpES2_PKiS4_
.set _ZN3ops24Conv2DTransposeInputGradC1EPNS_2OpES2_PKiS4_,_ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.weak _ZTSN3ops24Conv2DTransposeInputGradE
.section .rodata._ZTSN3ops24Conv2DTransposeInputGradE,"aG",@progbits,_ZTSN3ops24Conv2DTransposeInputGradE,comdat
.align 32
.type _ZTSN3ops24Conv2DTransposeInputGradE, @object
.size _ZTSN3ops24Conv2DTransposeInputGradE, 33
_ZTSN3ops24Conv2DTransposeInputGradE:
.string "N3ops24Conv2DTransposeInputGradE"
.weak _ZTIN3ops24Conv2DTransposeInputGradE
.section .data.rel.ro._ZTIN3ops24Conv2DTransposeInputGradE,"awG",@progbits,_ZTIN3ops24Conv2DTransposeInputGradE,comdat
.align 8
.type _ZTIN3ops24Conv2DTransposeInputGradE, @object
.size _ZTIN3ops24Conv2DTransposeInputGradE, 24
_ZTIN3ops24Conv2DTransposeInputGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops24Conv2DTransposeInputGradE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops24Conv2DTransposeInputGradE
.section .data.rel.ro._ZTVN3ops24Conv2DTransposeInputGradE,"awG",@progbits,_ZTVN3ops24Conv2DTransposeInputGradE,comdat
.align 8
.type _ZTVN3ops24Conv2DTransposeInputGradE, @object
.size _ZTVN3ops24Conv2DTransposeInputGradE, 48
_ZTVN3ops24Conv2DTransposeInputGradE:
.quad 0
.quad _ZTIN3ops24Conv2DTransposeInputGradE
.quad _ZN3ops24Conv2DTransposeInputGradD1Ev
.quad _ZN3ops24Conv2DTransposeInputGradD0Ev
.quad _ZN3ops24Conv2DTransposeInputGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "conv2d-transpose-input-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DTransposeInputGrad::Conv2DTransposeInputGrad(Op* y, Op* kernel,
const int strides[], const int input_size[])
: Op("conv2d_transpose_input_grad",
Shape({input_size[0], input_size[1],
input_size[2], input_size[3]}),
{y, kernel})
, m_strides(strides)
{
m_input_size[0] = input_size[0];
m_input_size[1] = input_size[1];
m_input_size[2] = input_size[2];
m_input_size[3] = input_size[3];
}
void Conv2DTransposeInputGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& ckernel = g.compiled(preds()[1]);
Shape out_shape({m_input_size[0], m_input_size[1], m_input_size[2], m_input_size[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int y_size[4] = { cy.out_shape[0], cy.out_shape[1],
cy.out_shape[2], cy.out_shape[3]};
int kernel_size[4] = { ckernel.out_shape[0], ckernel.out_shape[1],
ckernel.out_shape[2], ckernel.out_shape[3]};
auto out_node = rt::Node::op_conv2d_transpose_input_grad(cy.out_data, ckernel.out_data,
m_strides, out_data, y_size,
kernel_size, m_input_size,
{cy.out_node, ckernel.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
}
|
#include <hip/hip_runtime.h>
#include "conv2d-transpose-input-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DTransposeInputGrad::Conv2DTransposeInputGrad(Op* y, Op* kernel,
const int strides[], const int input_size[])
: Op("conv2d_transpose_input_grad",
Shape({input_size[0], input_size[1],
input_size[2], input_size[3]}),
{y, kernel})
, m_strides(strides)
{
m_input_size[0] = input_size[0];
m_input_size[1] = input_size[1];
m_input_size[2] = input_size[2];
m_input_size[3] = input_size[3];
}
void Conv2DTransposeInputGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& ckernel = g.compiled(preds()[1]);
Shape out_shape({m_input_size[0], m_input_size[1], m_input_size[2], m_input_size[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int y_size[4] = { cy.out_shape[0], cy.out_shape[1],
cy.out_shape[2], cy.out_shape[3]};
int kernel_size[4] = { ckernel.out_shape[0], ckernel.out_shape[1],
ckernel.out_shape[2], ckernel.out_shape[3]};
auto out_node = rt::Node::op_conv2d_transpose_input_grad(cy.out_data, ckernel.out_data,
m_strides, out_data, y_size,
kernel_size, m_input_size,
{cy.out_node, ckernel.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "conv2d-transpose-input-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DTransposeInputGrad::Conv2DTransposeInputGrad(Op* y, Op* kernel,
const int strides[], const int input_size[])
: Op("conv2d_transpose_input_grad",
Shape({input_size[0], input_size[1],
input_size[2], input_size[3]}),
{y, kernel})
, m_strides(strides)
{
m_input_size[0] = input_size[0];
m_input_size[1] = input_size[1];
m_input_size[2] = input_size[2];
m_input_size[3] = input_size[3];
}
void Conv2DTransposeInputGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& ckernel = g.compiled(preds()[1]);
Shape out_shape({m_input_size[0], m_input_size[1], m_input_size[2], m_input_size[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int y_size[4] = { cy.out_shape[0], cy.out_shape[1],
cy.out_shape[2], cy.out_shape[3]};
int kernel_size[4] = { ckernel.out_shape[0], ckernel.out_shape[1],
ckernel.out_shape[2], ckernel.out_shape[3]};
auto out_node = rt::Node::op_conv2d_transpose_input_grad(cy.out_data, ckernel.out_data,
m_strides, out_data, y_size,
kernel_size, m_input_size,
{cy.out_node, ckernel.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "conv2d-transpose-input-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DTransposeInputGrad::Conv2DTransposeInputGrad(Op* y, Op* kernel,
const int strides[], const int input_size[])
: Op("conv2d_transpose_input_grad",
Shape({input_size[0], input_size[1],
input_size[2], input_size[3]}),
{y, kernel})
, m_strides(strides)
{
m_input_size[0] = input_size[0];
m_input_size[1] = input_size[1];
m_input_size[2] = input_size[2];
m_input_size[3] = input_size[3];
}
void Conv2DTransposeInputGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& ckernel = g.compiled(preds()[1]);
Shape out_shape({m_input_size[0], m_input_size[1], m_input_size[2], m_input_size[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int y_size[4] = { cy.out_shape[0], cy.out_shape[1],
cy.out_shape[2], cy.out_shape[3]};
int kernel_size[4] = { ckernel.out_shape[0], ckernel.out_shape[1],
ckernel.out_shape[2], ckernel.out_shape[3]};
auto out_node = rt::Node::op_conv2d_transpose_input_grad(cy.out_data, ckernel.out_data,
m_strides, out_data, y_size,
kernel_size, m_input_size,
{cy.out_node, ckernel.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
}
|
.text
.file "conv2d-transpose-input-grad.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.p2align 4, 0x90
.type _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_,@function
_ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_: # @_ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, 88(%rsp) # 8-byte Spill
movq %rdx, 104(%rsp) # 8-byte Spill
movq %rsi, 96(%rsp) # 8-byte Spill
movq %rdi, %r14
leaq 72(%rsp), %rax
movq %rax, 56(%rsp)
movl $28, %edi
callq _Znwm
movq %rax, 56(%rsp)
movq $27, 72(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str+11(%rip), %xmm0
movups %xmm0, 11(%rax)
movq $27, 64(%rsp)
movb $0, 27(%rax)
movl (%rbx), %ebp
movl 4(%rbx), %r15d
movl 8(%rbx), %r12d
movl 12(%rbx), %r13d
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
.Ltmp0:
movl $16, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, 32(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 48(%rsp)
movl %ebp, (%rax)
movl %r15d, 4(%rax)
movl %r12d, 8(%rax)
movl %r13d, 12(%rax)
movq %rcx, 40(%rsp)
.Ltmp3:
leaq 144(%rsp), %rdi
leaq 32(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp4:
# %bb.2:
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp6:
movl $16, %edi
callq _Znwm
.Ltmp7:
# %bb.3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq 96(%rsp), %rdx # 8-byte Reload
movq %rdx, (%rax)
movq 104(%rsp), %rdx # 8-byte Reload
movq %rdx, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
.Ltmp9:
leaq 56(%rsp), %rsi
leaq 144(%rsp), %rdx
movq %rsp, %rcx
leaq 112(%rsp), %r8
movq %r14, %rdi
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp10:
# %bb.4:
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_6
# %bb.5:
callq _ZdlPv
.LBB0_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_8
# %bb.7:
callq _ZdlPv
.LBB0_8: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit31
movq 144(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_10
# %bb.9:
callq _ZdlPv
.LBB0_10: # %_ZN3ops5ShapeD2Ev.exit
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_12
# %bb.11:
callq _ZdlPv
.LBB0_12: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq 56(%rsp), %rdi
leaq 72(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_14
# %bb.13: # %.critedge.i.i
callq _ZdlPv
.LBB0_14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops24Conv2DTransposeInputGradE+16, (%r14)
movq 88(%rsp), %rax # 8-byte Reload
movq %rax, 112(%r14)
movl (%rbx), %eax
movl %eax, 120(%r14)
movl 4(%rbx), %eax
movl %eax, 124(%r14)
movl 8(%rbx), %eax
movl %eax, 128(%r14)
movl 12(%rbx), %eax
movl %eax, 132(%r14)
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_15:
.cfi_def_cfa_offset 224
.Ltmp11:
movq %rax, %rbx
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_18
# %bb.16:
callq _ZdlPv
jmp .LBB0_18
.LBB0_17:
.Ltmp8:
movq %rax, %rbx
.LBB0_18: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit36
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_20
# %bb.19: # %.body26.sink.split
callq _ZdlPv
.LBB0_20: # %.body26
movq 144(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_25
# %bb.21:
callq _ZdlPv
jmp .LBB0_25
.LBB0_22:
.Ltmp5:
jmp .LBB0_24
.LBB0_23:
.Ltmp2:
.LBB0_24: # %_ZN3ops5ShapeD2Ev.exit41
movq %rax, %rbx
.LBB0_25: # %_ZN3ops5ShapeD2Ev.exit41
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_27
# %bb.26: # %.body.sink.split
callq _ZdlPv
.LBB0_27: # %.body
movq 56(%rsp), %rdi
leaq 72(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_29
# %bb.28: # %.critedge.i.i45
callq _ZdlPv
.LBB0_29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit47
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_, .Lfunc_end0-_ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops24Conv2DTransposeInputGrad7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops24Conv2DTransposeInputGrad7compileEv
.p2align 4, 0x90
.type _ZN3ops24Conv2DTransposeInputGrad7compileEv,@function
_ZN3ops24Conv2DTransposeInputGrad7compileEv: # @_ZN3ops24Conv2DTransposeInputGrad7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
.cfi_escape 0x2e, 0x00
callq _ZN3ops5Graph8instanceEv
movq %rax, %r14
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
movq 24(%rsp), %rax
movq (%rax), %rsi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.1:
movq %rax, %r13
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
movq 24(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp15:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
movq %rax, 160(%rsp) # 8-byte Spill
.Ltmp16:
# %bb.4:
movq %r14, 152(%rsp) # 8-byte Spill
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit53
movl 120(%rbx), %ebp
movl 124(%rbx), %r14d
movl 128(%rbx), %r15d
movl 132(%rbx), %r12d
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
movl $16, %edi
callq _Znwm
.Ltmp19:
# %bb.7: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movl %ebp, (%rax)
movl %r14d, 4(%rax)
movl %r15d, 8(%rax)
movl %r12d, 12(%rax)
movq %rcx, 8(%rsp)
.Ltmp21:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %rsp, %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp22:
# %bb.8:
movq (%rsp), %rdi
testq %rdi, %rdi
movq %r13, %r12
je .LBB1_10
# %bb.9:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_10: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq _ZNK3ops5Shape5totalEv
.Ltmp25:
movq 160(%rsp), %r13 # 8-byte Reload
# %bb.11:
movslq %eax, %rdi
.Ltmp26:
.cfi_escape 0x2e, 0x00
callq _Z12tensor_allocm
.Ltmp27:
# %bb.12:
movq %rax, %r14
leaq 64(%r12), %rbp
.Ltmp29:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
.Ltmp30:
# %bb.13:
movl %eax, 128(%rsp)
.Ltmp31:
.cfi_escape 0x2e, 0x00
movl $1, %esi
movq %rbp, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp32:
# %bb.14:
movl %eax, 132(%rsp)
.Ltmp33:
.cfi_escape 0x2e, 0x00
movl $2, %esi
movq %rbp, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp34:
# %bb.15:
movl %eax, 136(%rsp)
.Ltmp35:
.cfi_escape 0x2e, 0x00
movl $3, %esi
movq %rbp, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp36:
# %bb.16:
movq %r14, 144(%rsp) # 8-byte Spill
movl %eax, 140(%rsp)
leaq 64(%r13), %rbp
.Ltmp38:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
.Ltmp39:
# %bb.17:
movl %eax, 112(%rsp)
.Ltmp40:
.cfi_escape 0x2e, 0x00
movl $1, %esi
movq %rbp, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp41:
# %bb.18:
movl %eax, 116(%rsp)
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl $2, %esi
movq %rbp, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp43:
# %bb.19:
movl %eax, 120(%rsp)
.Ltmp44:
.cfi_escape 0x2e, 0x00
movl $3, %esi
movq %rbp, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp45:
# %bb.20:
movl %eax, 124(%rsp)
movq 88(%r12), %rbp
movq 88(%r13), %r14
movq 112(%rbx), %r15
movq 56(%r12), %r12
movq 56(%r13), %r13
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp47:
.cfi_escape 0x2e, 0x00
movl $16, %edi
callq _Znwm
.Ltmp48:
# %bb.21: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
leaq 120(%rbx), %r10
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r12, (%rax)
movq %r13, 8(%rax)
movq %rcx, 8(%rsp)
.Ltmp50:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r8
leaq 112(%rsp), %r9
movq %rbp, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq 144(%rsp), %r14 # 8-byte Reload
movq %r14, %rcx
movq %rsp, %rax
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
callq _ZN2rt4Node30op_conv2d_transpose_input_gradEPKfS2_PKiPfS4_S4_S4_RKSt6vectorIPS0_SaIS7_EE
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp51:
# %bb.22:
movq %rax, %r15
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB1_24
# %bb.23:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp53:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq _Znwm
.Ltmp54:
# %bb.25: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit65
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %r15, (%rax)
movq %rcx, 88(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp56:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq _Znwm
.Ltmp57:
# %bb.26: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r14, (%rax)
movq %rcx, 56(%rsp)
.Ltmp59:
.cfi_escape 0x2e, 0x10
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 88(%rsp), %rdx
leaq 56(%rsp), %rcx
leaq 32(%rsp), %r9
movq 160(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r15, %r8
pushq %r14
.cfi_adjust_cfa_offset 8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp60:
# %bb.27:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_29
# %bb.28:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_29: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_31
# %bb.30:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_31: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit73
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_33
# %bb.32:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_33: # %_ZN3ops5ShapeD2Ev.exit
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_34:
.cfi_def_cfa_offset 224
.Ltmp61:
jmp .LBB1_36
.LBB1_35:
.Ltmp58:
.LBB1_36:
movq %rax, %rbx
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_38
# %bb.37: # %.body67.sink.split
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_38: # %.body67
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_59
# %bb.39:
.cfi_escape 0x2e, 0x00
jmp .LBB1_46
.LBB1_40:
.Ltmp55:
movq %rax, %rbx
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_59
# %bb.41:
.cfi_escape 0x2e, 0x00
jmp .LBB1_46
.LBB1_42:
.Ltmp52:
jmp .LBB1_44
.LBB1_43:
.Ltmp49:
.LBB1_44:
movq %rax, %rbx
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB1_59
# %bb.45: # %.body57.sink.split
.cfi_escape 0x2e, 0x00
.LBB1_46: # %.body63
callq _ZdlPv
jmp .LBB1_59
.LBB1_47:
.Ltmp23:
jmp .LBB1_49
.LBB1_48:
.Ltmp20:
.LBB1_49:
movq %rax, %rbx
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB1_62
# %bb.50: # %.body.sink.split
.cfi_escape 0x2e, 0x00
jmp .LBB1_61
.LBB1_51:
.Ltmp17:
movq %rax, %rbx
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_62
# %bb.52:
.cfi_escape 0x2e, 0x00
jmp .LBB1_61
.LBB1_53:
.Ltmp14:
movq %rax, %rbx
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_62
# %bb.54:
.cfi_escape 0x2e, 0x00
jmp .LBB1_61
.LBB1_55:
.Ltmp28:
jmp .LBB1_58
.LBB1_56:
.Ltmp46:
jmp .LBB1_58
.LBB1_57:
.Ltmp37:
.LBB1_58:
movq %rax, %rbx
.LBB1_59:
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_62
# %bb.60:
.cfi_escape 0x2e, 0x00
.LBB1_61:
callq _ZdlPv
.LBB1_62:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops24Conv2DTransposeInputGrad7compileEv, .Lfunc_end1-_ZN3ops24Conv2DTransposeInputGrad7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp12-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp27-.Ltmp24 # Call between .Ltmp24 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp36-.Ltmp29 # Call between .Ltmp29 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin1 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp45-.Ltmp38 # Call between .Ltmp38 and .Ltmp45
.uleb128 .Ltmp46-.Lfunc_begin1 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp48-.Ltmp47 # Call between .Ltmp47 and .Ltmp48
.uleb128 .Ltmp49-.Lfunc_begin1 # jumps to .Ltmp49
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp51-.Ltmp50 # Call between .Ltmp50 and .Ltmp51
.uleb128 .Ltmp52-.Lfunc_begin1 # jumps to .Ltmp52
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Ltmp54-.Ltmp53 # Call between .Ltmp53 and .Ltmp54
.uleb128 .Ltmp55-.Lfunc_begin1 # jumps to .Ltmp55
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin1 # >> Call Site 13 <<
.uleb128 .Ltmp57-.Ltmp56 # Call between .Ltmp56 and .Ltmp57
.uleb128 .Ltmp58-.Lfunc_begin1 # jumps to .Ltmp58
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin1 # >> Call Site 14 <<
.uleb128 .Ltmp60-.Ltmp59 # Call between .Ltmp59 and .Ltmp60
.uleb128 .Ltmp61-.Lfunc_begin1 # jumps to .Ltmp61
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin1 # >> Call Site 15 <<
.uleb128 .Lfunc_end1-.Ltmp60 # Call between .Ltmp60 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops24Conv2DTransposeInputGradD0Ev,"axG",@progbits,_ZN3ops24Conv2DTransposeInputGradD0Ev,comdat
.weak _ZN3ops24Conv2DTransposeInputGradD0Ev # -- Begin function _ZN3ops24Conv2DTransposeInputGradD0Ev
.p2align 4, 0x90
.type _ZN3ops24Conv2DTransposeInputGradD0Ev,@function
_ZN3ops24Conv2DTransposeInputGradD0Ev: # @_ZN3ops24Conv2DTransposeInputGradD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops24Conv2DTransposeInputGradD0Ev, .Lfunc_end3-_ZN3ops24Conv2DTransposeInputGradD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "conv2d_transpose_input_grad"
.size .L.str, 28
.type _ZTVN3ops24Conv2DTransposeInputGradE,@object # @_ZTVN3ops24Conv2DTransposeInputGradE
.section .rodata,"a",@progbits
.globl _ZTVN3ops24Conv2DTransposeInputGradE
.p2align 3, 0x0
_ZTVN3ops24Conv2DTransposeInputGradE:
.quad 0
.quad _ZTIN3ops24Conv2DTransposeInputGradE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops24Conv2DTransposeInputGradD0Ev
.quad _ZN3ops24Conv2DTransposeInputGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops24Conv2DTransposeInputGradE, 48
.type _ZTSN3ops24Conv2DTransposeInputGradE,@object # @_ZTSN3ops24Conv2DTransposeInputGradE
.globl _ZTSN3ops24Conv2DTransposeInputGradE
_ZTSN3ops24Conv2DTransposeInputGradE:
.asciz "N3ops24Conv2DTransposeInputGradE"
.size _ZTSN3ops24Conv2DTransposeInputGradE, 33
.type _ZTIN3ops24Conv2DTransposeInputGradE,@object # @_ZTIN3ops24Conv2DTransposeInputGradE
.globl _ZTIN3ops24Conv2DTransposeInputGradE
.p2align 3, 0x0
_ZTIN3ops24Conv2DTransposeInputGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops24Conv2DTransposeInputGradE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops24Conv2DTransposeInputGradE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops24Conv2DTransposeInputGradC1EPNS_2OpES2_PKiS4_
.type _ZN3ops24Conv2DTransposeInputGradC1EPNS_2OpES2_PKiS4_,@function
.set _ZN3ops24Conv2DTransposeInputGradC1EPNS_2OpES2_PKiS4_, _ZN3ops24Conv2DTransposeInputGradC2EPNS_2OpES2_PKiS4_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops24Conv2DTransposeInputGradE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops24Conv2DTransposeInputGradE
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void gain(int width, int height, float rGain, float gGain, float bGain, float* input, float* output)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x < width) && (y < height))
{
int index = (y * width + x) * 4;
output[index + 0] = input[index + 0] * rGain;
output[index + 1] = input[index + 1] * gGain;
output[index + 2] = input[index + 2] * bGain;
output[index + 3] = input[index + 3];
}
}
|
code for sm_80
Function : _Z4gainiifffPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fcc00000006ff */
/*00e0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fc800078e0205 */
/*0110*/ FMUL R7, R6, c[0x0][0x168] ; /* 0x00005a0006077a20 */
/* 0x004fca0000400000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0130*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FMUL R9, R0, c[0x0][0x16c] ; /* 0x00005b0000097a20 */
/* 0x004fca0000400000 */
/*0150*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c101904 */
/*0160*/ LDG.E R0, [R2.64+0x8] ; /* 0x0000080402007981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FMUL R11, R0, c[0x0][0x170] ; /* 0x00005c00000b7a20 */
/* 0x004fca0000400000 */
/*0180*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c101904 */
/*0190*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void gain(int width, int height, float rGain, float gGain, float bGain, float* input, float* output)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x < width) && (y < height))
{
int index = (y * width + x) * 4;
output[index + 0] = input[index + 0] * rGain;
output[index + 1] = input[index + 1] * gGain;
output[index + 2] = input[index + 2] * bGain;
output[index + 3] = input[index + 3];
}
}
|
.file "tmpxft_000d60a2_00000000-6_gain.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4gainiifffPfS_iifffPfS_
.type _Z30__device_stub__Z4gainiifffPfS_iifffPfS_, @function
_Z30__device_stub__Z4gainiifffPfS_iifffPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4gainiifffPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z4gainiifffPfS_iifffPfS_, .-_Z30__device_stub__Z4gainiifffPfS_iifffPfS_
.globl _Z4gainiifffPfS_
.type _Z4gainiifffPfS_, @function
_Z4gainiifffPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4gainiifffPfS_iifffPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4gainiifffPfS_, .-_Z4gainiifffPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4gainiifffPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gainiifffPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void gain(int width, int height, float rGain, float gGain, float bGain, float* input, float* output)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x < width) && (y < height))
{
int index = (y * width + x) * 4;
output[index + 0] = input[index + 0] * rGain;
output[index + 1] = input[index + 1] * gGain;
output[index + 2] = input[index + 2] * bGain;
output[index + 3] = input[index + 3];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gain(int width, int height, float rGain, float gGain, float bGain, float* input, float* output)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x < width) && (y < height))
{
int index = (y * width + x) * 4;
output[index + 0] = input[index + 0] * rGain;
output[index + 1] = input[index + 1] * gGain;
output[index + 2] = input[index + 2] * bGain;
output[index + 3] = input[index + 3];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gain(int width, int height, float rGain, float gGain, float bGain, float* input, float* output)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x < width) && (y < height))
{
int index = (y * width + x) * 4;
output[index + 0] = input[index + 0] * rGain;
output[index + 1] = input[index + 1] * gGain;
output[index + 2] = input[index + 2] * bGain;
output[index + 3] = input[index + 3];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gainiifffPfS_
.globl _Z4gainiifffPfS_
.p2align 8
.type _Z4gainiifffPfS_,@function
_Z4gainiifffPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v1, v1, s4
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v0, v1, v0, 2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v5, v[3:4], off
v_or_b32_e32 v3, 1, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, s2, v5
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[1:2], v7, off
v_or_b32_e32 v1, 2, v0
v_add_co_u32 v3, vcc_lo, s6, v3
global_load_b32 v5, v[5:6], off
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, s3, v5
v_add_co_u32 v5, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[3:4], v7, off
v_or_b32_e32 v3, 3, v0
v_add_co_u32 v0, vcc_lo, s6, v1
global_load_b32 v5, v[5:6], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v5
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, s6, v3
global_load_b32 v2, v[5:6], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gainiifffPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gainiifffPfS_, .Lfunc_end0-_Z4gainiifffPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gainiifffPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gainiifffPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gain(int width, int height, float rGain, float gGain, float bGain, float* input, float* output)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x < width) && (y < height))
{
int index = (y * width + x) * 4;
output[index + 0] = input[index + 0] * rGain;
output[index + 1] = input[index + 1] * gGain;
output[index + 2] = input[index + 2] * bGain;
output[index + 3] = input[index + 3];
}
}
|
.text
.file "gain.hip"
.globl _Z19__device_stub__gainiifffPfS_ # -- Begin function _Z19__device_stub__gainiifffPfS_
.p2align 4, 0x90
.type _Z19__device_stub__gainiifffPfS_,@function
_Z19__device_stub__gainiifffPfS_: # @_Z19__device_stub__gainiifffPfS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4gainiifffPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__gainiifffPfS_, .Lfunc_end0-_Z19__device_stub__gainiifffPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gainiifffPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4gainiifffPfS_,@object # @_Z4gainiifffPfS_
.section .rodata,"a",@progbits
.globl _Z4gainiifffPfS_
.p2align 3, 0x0
_Z4gainiifffPfS_:
.quad _Z19__device_stub__gainiifffPfS_
.size _Z4gainiifffPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4gainiifffPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gainiifffPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gainiifffPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4gainiifffPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fcc00000006ff */
/*00e0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00f0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fc800078e0205 */
/*0110*/ FMUL R7, R6, c[0x0][0x168] ; /* 0x00005a0006077a20 */
/* 0x004fca0000400000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0130*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FMUL R9, R0, c[0x0][0x16c] ; /* 0x00005b0000097a20 */
/* 0x004fca0000400000 */
/*0150*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c101904 */
/*0160*/ LDG.E R0, [R2.64+0x8] ; /* 0x0000080402007981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FMUL R11, R0, c[0x0][0x170] ; /* 0x00005c00000b7a20 */
/* 0x004fca0000400000 */
/*0180*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c101904 */
/*0190*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gainiifffPfS_
.globl _Z4gainiifffPfS_
.p2align 8
.type _Z4gainiifffPfS_,@function
_Z4gainiifffPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v1, v1, s4
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v0, v1, v0, 2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v5, v[3:4], off
v_or_b32_e32 v3, 1, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, s2, v5
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[1:2], v7, off
v_or_b32_e32 v1, 2, v0
v_add_co_u32 v3, vcc_lo, s6, v3
global_load_b32 v5, v[5:6], off
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, s3, v5
v_add_co_u32 v5, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[3:4], v7, off
v_or_b32_e32 v3, 3, v0
v_add_co_u32 v0, vcc_lo, s6, v1
global_load_b32 v5, v[5:6], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v5
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, s6, v3
global_load_b32 v2, v[5:6], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gainiifffPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gainiifffPfS_, .Lfunc_end0-_Z4gainiifffPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gainiifffPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gainiifffPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d60a2_00000000-6_gain.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4gainiifffPfS_iifffPfS_
.type _Z30__device_stub__Z4gainiifffPfS_iifffPfS_, @function
_Z30__device_stub__Z4gainiifffPfS_iifffPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4gainiifffPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z4gainiifffPfS_iifffPfS_, .-_Z30__device_stub__Z4gainiifffPfS_iifffPfS_
.globl _Z4gainiifffPfS_
.type _Z4gainiifffPfS_, @function
_Z4gainiifffPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4gainiifffPfS_iifffPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4gainiifffPfS_, .-_Z4gainiifffPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4gainiifffPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gainiifffPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "gain.hip"
.globl _Z19__device_stub__gainiifffPfS_ # -- Begin function _Z19__device_stub__gainiifffPfS_
.p2align 4, 0x90
.type _Z19__device_stub__gainiifffPfS_,@function
_Z19__device_stub__gainiifffPfS_: # @_Z19__device_stub__gainiifffPfS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4gainiifffPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__gainiifffPfS_, .Lfunc_end0-_Z19__device_stub__gainiifffPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gainiifffPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4gainiifffPfS_,@object # @_Z4gainiifffPfS_
.section .rodata,"a",@progbits
.globl _Z4gainiifffPfS_
.p2align 3, 0x0
_Z4gainiifffPfS_:
.quad _Z19__device_stub__gainiifffPfS_
.size _Z4gainiifffPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4gainiifffPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gainiifffPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gainiifffPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cstdio>
__global__ void my_kernel() {
printf("Hello from block %i of %i and thread %i \n ", blockIdx.x, blockDim.x, threadIdx.x);
}
int main() {
my_kernel <<<16, 16 >>> ();
cudaError_t cuda_err = cudaDeviceSynchronize();
if (cuda_err != cudaSuccess)
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cuda_err));
return 0;
}
|
code for sm_80
Function : _Z9my_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0004e20000000a00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0015e80000100a00 */
/*00c0*/ STL [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0025e60000100800 */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x004fe40000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x008fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cstdio>
__global__ void my_kernel() {
printf("Hello from block %i of %i and thread %i \n ", blockIdx.x, blockDim.x, threadIdx.x);
}
int main() {
my_kernel <<<16, 16 >>> ();
cudaError_t cuda_err = cudaDeviceSynchronize();
if (cuda_err != cudaSuccess)
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cuda_err));
return 0;
}
|
.file "tmpxft_000fa27f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9my_kernelvv
.type _Z27__device_stub__Z9my_kernelvv, @function
_Z27__device_stub__Z9my_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9my_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9my_kernelvv, .-_Z27__device_stub__Z9my_kernelvv
.globl _Z9my_kernelv
.type _Z9my_kernelv, @function
_Z9my_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9my_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9my_kernelv, .-_Z9my_kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "kernel launch failed with error \"%s\".\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L16
.L13:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z27__device_stub__Z9my_kernelvv
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9my_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cstdio>
__global__ void my_kernel() {
printf("Hello from block %i of %i and thread %i \n ", blockIdx.x, blockDim.x, threadIdx.x);
}
int main() {
my_kernel <<<16, 16 >>> ();
cudaError_t cuda_err = cudaDeviceSynchronize();
if (cuda_err != cudaSuccess)
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cuda_err));
return 0;
}
|
#include <hip/hip_runtime.h>
#include <cstdio>
__global__ void my_kernel() {
printf("Hello from block %i of %i and thread %i \n ", blockIdx.x, blockDim.x, threadIdx.x);
}
int main() {
my_kernel <<<16, 16 >>> ();
hipError_t cuda_err = hipDeviceSynchronize();
if (cuda_err != hipSuccess)
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cuda_err));
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <cstdio>
__global__ void my_kernel() {
printf("Hello from block %i of %i and thread %i \n ", blockIdx.x, blockDim.x, threadIdx.x);
}
int main() {
my_kernel <<<16, 16 >>> ();
hipError_t cuda_err = hipDeviceSynchronize();
if (cuda_err != hipSuccess)
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cuda_err));
return 0;
}
|
.text
.file "main.hip"
.globl _Z24__device_stub__my_kernelv # -- Begin function _Z24__device_stub__my_kernelv
.p2align 4, 0x90
.type _Z24__device_stub__my_kernelv,@function
_Z24__device_stub__my_kernelv: # @_Z24__device_stub__my_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9my_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__my_kernelv, .Lfunc_end0-_Z24__device_stub__my_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9my_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9my_kernelv,@object # @_Z9my_kernelv
.section .rodata,"a",@progbits
.globl _Z9my_kernelv
.p2align 3, 0x0
_Z9my_kernelv:
.quad _Z24__device_stub__my_kernelv
.size _Z9my_kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_kernelv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9my_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000fa27f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9my_kernelvv
.type _Z27__device_stub__Z9my_kernelvv, @function
_Z27__device_stub__Z9my_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9my_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9my_kernelvv, .-_Z27__device_stub__Z9my_kernelvv
.globl _Z9my_kernelv
.type _Z9my_kernelv, @function
_Z9my_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9my_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9my_kernelv, .-_Z9my_kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "kernel launch failed with error \"%s\".\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L16
.L13:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z27__device_stub__Z9my_kernelvv
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9my_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.globl _Z24__device_stub__my_kernelv # -- Begin function _Z24__device_stub__my_kernelv
.p2align 4, 0x90
.type _Z24__device_stub__my_kernelv,@function
_Z24__device_stub__my_kernelv: # @_Z24__device_stub__my_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9my_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__my_kernelv, .Lfunc_end0-_Z24__device_stub__my_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9my_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9my_kernelv,@object # @_Z9my_kernelv
.section .rodata,"a",@progbits
.globl _Z9my_kernelv
.p2align 3, 0x0
_Z9my_kernelv:
.quad _Z24__device_stub__my_kernelv
.size _Z9my_kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_kernelv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9my_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void naiveGmem(float *out, float *in, const int nx, const int ny)
{
// matrix coordinate (ix,iy)
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y;
// transpose with boundary test
if (ix < nx && iy < ny)
{
out[ix * ny + iy] = in[iy * nx + ix];
}
}
|
code for sm_80
Function : _Z9naiveGmemPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void naiveGmem(float *out, float *in, const int nx, const int ny)
{
// matrix coordinate (ix,iy)
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y;
// transpose with boundary test
if (ix < nx && iy < ny)
{
out[ix * ny + iy] = in[iy * nx + ix];
}
}
|
.file "tmpxft_00194cfa_00000000-6_naiveGmem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii
.type _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii, @function
_Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9naiveGmemPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii, .-_Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii
.globl _Z9naiveGmemPfS_ii
.type _Z9naiveGmemPfS_ii, @function
_Z9naiveGmemPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9naiveGmemPfS_ii, .-_Z9naiveGmemPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9naiveGmemPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9naiveGmemPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void naiveGmem(float *out, float *in, const int nx, const int ny)
{
// matrix coordinate (ix,iy)
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y;
// transpose with boundary test
if (ix < nx && iy < ny)
{
out[ix * ny + iy] = in[iy * nx + ix];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveGmem(float *out, float *in, const int nx, const int ny)
{
// matrix coordinate (ix,iy)
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y;
// transpose with boundary test
if (ix < nx && iy < ny)
{
out[ix * ny + iy] = in[iy * nx + ix];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveGmem(float *out, float *in, const int nx, const int ny)
{
// matrix coordinate (ix,iy)
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y;
// transpose with boundary test
if (ix < nx && iy < ny)
{
out[ix * ny + iy] = in[iy * nx + ix];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9naiveGmemPfS_ii
.globl _Z9naiveGmemPfS_ii
.p2align 8
.type _Z9naiveGmemPfS_ii,@function
_Z9naiveGmemPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9naiveGmemPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9naiveGmemPfS_ii, .Lfunc_end0-_Z9naiveGmemPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9naiveGmemPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9naiveGmemPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveGmem(float *out, float *in, const int nx, const int ny)
{
// matrix coordinate (ix,iy)
unsigned int ix = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int iy = blockIdx.y * blockDim.y + threadIdx.y;
// transpose with boundary test
if (ix < nx && iy < ny)
{
out[ix * ny + iy] = in[iy * nx + ix];
}
}
|
.text
.file "naiveGmem.hip"
.globl _Z24__device_stub__naiveGmemPfS_ii # -- Begin function _Z24__device_stub__naiveGmemPfS_ii
.p2align 4, 0x90
.type _Z24__device_stub__naiveGmemPfS_ii,@function
_Z24__device_stub__naiveGmemPfS_ii: # @_Z24__device_stub__naiveGmemPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9naiveGmemPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__naiveGmemPfS_ii, .Lfunc_end0-_Z24__device_stub__naiveGmemPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9naiveGmemPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9naiveGmemPfS_ii,@object # @_Z9naiveGmemPfS_ii
.section .rodata,"a",@progbits
.globl _Z9naiveGmemPfS_ii
.p2align 3, 0x0
_Z9naiveGmemPfS_ii:
.quad _Z24__device_stub__naiveGmemPfS_ii
.size _Z9naiveGmemPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9naiveGmemPfS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__naiveGmemPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9naiveGmemPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9naiveGmemPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9naiveGmemPfS_ii
.globl _Z9naiveGmemPfS_ii
.p2align 8
.type _Z9naiveGmemPfS_ii,@function
_Z9naiveGmemPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9naiveGmemPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9naiveGmemPfS_ii, .Lfunc_end0-_Z9naiveGmemPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9naiveGmemPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9naiveGmemPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00194cfa_00000000-6_naiveGmem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii
.type _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii, @function
_Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9naiveGmemPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii, .-_Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii
.globl _Z9naiveGmemPfS_ii
.type _Z9naiveGmemPfS_ii, @function
_Z9naiveGmemPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9naiveGmemPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9naiveGmemPfS_ii, .-_Z9naiveGmemPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9naiveGmemPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9naiveGmemPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "naiveGmem.hip"
.globl _Z24__device_stub__naiveGmemPfS_ii # -- Begin function _Z24__device_stub__naiveGmemPfS_ii
.p2align 4, 0x90
.type _Z24__device_stub__naiveGmemPfS_ii,@function
_Z24__device_stub__naiveGmemPfS_ii: # @_Z24__device_stub__naiveGmemPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9naiveGmemPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__naiveGmemPfS_ii, .Lfunc_end0-_Z24__device_stub__naiveGmemPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9naiveGmemPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9naiveGmemPfS_ii,@object # @_Z9naiveGmemPfS_ii
.section .rodata,"a",@progbits
.globl _Z9naiveGmemPfS_ii
.p2align 3, 0x0
_Z9naiveGmemPfS_ii:
.quad _Z24__device_stub__naiveGmemPfS_ii
.size _Z9naiveGmemPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9naiveGmemPfS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__naiveGmemPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9naiveGmemPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// author: yohanes.gultom@gmail.com
// partial source: https://gist.github.com/wh5a/4313739
#include <stdio.h>
#include <time.h>
#define TILE_WIDTH 20
// create random matrix row-major-format
float* create_flat_matrix_rand(int row, int col, int max)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
float val = (max > 0) ? (float)(rand() % max) : 0.0f;
m[col * i + j] = val;
}
}
return m;
}
float* create_flat_matrix(int row, int col, float val)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
m[col * i + j] = val;
}
}
return m;
}
// print matrix row-major-format
void print_flat_matrix(float *m, int row, int col)
{
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
printf("%.2f ", m[col * i + j]);
}
printf("\n");
}
}
__global__ void mmul_d(float *first, int m, int p, float *second, int q, float *multiply)
{
int c, d, k = 0;
float sum = .0f;
for (c = 0; c < m; c++) {
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
}
__global__ void mmul_d_thread(float *first, int m, int p, float *second, int q, float *multiply)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int d, k = 0;
float sum = .0f;
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
// Compute C = A * B
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * TILE_WIDTH + ty,
Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) {
if (Row < numARows && m*TILE_WIDTH+tx < numAColumns)
ds_M[ty][tx] = A[Row*numAColumns + m*TILE_WIDTH+tx];
else
ds_M[ty][tx] = 0;
if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows)
ds_N[ty][tx] = B[(m*TILE_WIDTH+ty)*numBColumns+Col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += ds_M[ty][k] * ds_N[k][tx];
__syncthreads();
}
if (Row < numCRows && Col < numCColumns)
C[Row*numCColumns+Col] = Pvalue;
}
int main(int argc, char** argv)
{
if (argc < 6) {
printf("insufficient args. for A x B = C, required args: [row num A] [col num A/row num B] [col num B] [cuda block size] [reps] [optimized] [compare]\n");
return EXIT_FAILURE;
}
int m, n, p, q = 0;
m = atoi(argv[1]);
n = atoi(argv[2]);
p = n;
q = atoi(argv[3]);
int blockSize = atoi(argv[4]);
int nBlocks = (blockSize > 0) ? (m * n) / blockSize + ((m * n) % blockSize == 0 ? 0 : 1) : 0;
int reps = atoi(argv[5]);
// optimized = ignore blockSize and nBlocks
int optimized = (argc >= 7) ? atoi(argv[6]):0;
int compare = (argc >= 8) ? atoi(argv[7]):0;
//@@ Initialize the optimized grid and block dimensions here
dim3 dimGrid((q-1)/TILE_WIDTH+1, (m-1)/TILE_WIDTH+1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
float *first_d, *second_d, *multiply_d;
float *first, *second, *multiply;
int i = 0;
double total_time = 0.0f;
for (i = 0; i < reps; i++) {
double exec_time = ((double) clock()) * -1;
first = create_flat_matrix(m, n, 1);
second = create_flat_matrix(p, q, 2);
multiply = create_flat_matrix(m, q, 0);
cudaMalloc((void **) &first_d, m * n * sizeof(float));
cudaMalloc((void **) &second_d, p * q * sizeof(float));
cudaMalloc((void **) &multiply_d, m * q * sizeof(float));
cudaMemcpy(first_d, first, m * n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(second_d, second, p * q * sizeof(float), cudaMemcpyHostToDevice);
if (optimized == 1) {
matrixMultiply<<<dimGrid, dimBlock>>>(first_d, second_d, multiply_d, m, n, p, q, m, q);
} else {
mmul_d_thread <<< nBlocks, blockSize >>> (first_d, m, n, second_d, q, multiply_d);
}
cudaMemcpy(multiply, multiply_d, m * q * sizeof(float), cudaMemcpyDeviceToHost);
if (compare == 1) {
printf("first:\n");
print_flat_matrix(first, m, n);
printf("second:\n");
print_flat_matrix(second, p, q);
printf("multiply:\n");
print_flat_matrix(multiply, m, q);
}
free(multiply); free(second); free(first);
cudaFree(first_d); cudaFree(second_d); cudaFree(multiply_d);
total_time = total_time + ((exec_time + ((double)clock())) / CLOCKS_PER_SEC);
// printf("%d: %.6f\n", i, ((exec_time + ((double)clock())) / CLOCKS_PER_SEC));
}
printf("%d\t%d\t%d\t%d\t%d\t%.6f\n", m, n, q, blockSize, reps, (total_time / reps));
return EXIT_SUCCESS;
}
|
.file "tmpxft_00121a34_00000000-6_mmul_cuda_20.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23create_flat_matrix_randiii
.type _Z23create_flat_matrix_randiii, @function
_Z23create_flat_matrix_randiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %edi, 20(%rsp)
movl %esi, %r15d
movl %edx, %ebp
imull %esi, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L3
movl $0, %r14d
movl $0, %r13d
movslq %r15d, %rax
movq %rax, 24(%rsp)
jmp .L5
.L6:
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
je .L9
.L7:
pxor %xmm0, %xmm0
testl %ebp, %ebp
jle .L6
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
jmp .L6
.L9:
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 20(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jle .L9
movslq %r14d, %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %r12
jmp .L7
.L3:
movq 8(%rsp), %rax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z23create_flat_matrix_randiii, .-_Z23create_flat_matrix_randiii
.globl _Z18create_flat_matrixiif
.type _Z18create_flat_matrixiif, @function
_Z18create_flat_matrixiif:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %r12d
movl %esi, %ebp
movd %xmm0, %ebx
imull %esi, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
testl %r12d, %r12d
jle .L13
movl $0, %edi
movl $0, %esi
movslq %ebp, %r8
jmp .L15
.L17:
movslq %edi, %rcx
leaq (%rax,%rcx,4), %rdx
addq %r8, %rcx
leaq (%rax,%rcx,4), %rcx
.L16:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L16
.L18:
addl $1, %esi
addl %ebp, %edi
cmpl %esi, %r12d
je .L13
.L15:
testl %ebp, %ebp
jg .L17
jmp .L18
.L13:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z18create_flat_matrixiif, .-_Z18create_flat_matrixiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%.2f "
.LC2:
.string "\n"
.text
.globl _Z17print_flat_matrixPfii
.type _Z17print_flat_matrixPfii, @function
_Z17print_flat_matrixPfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L21
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC1(%rip), %r12
jmp .L23
.L25:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
.L26:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L21
.L23:
testl %r15d, %r15d
jg .L25
jmp .L26
.L21:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z17print_flat_matrixPfii, .-_Z17print_flat_matrixPfii
.globl _Z32__device_stub__Z6mmul_dPfiiS_iS_PfiiS_iS_
.type _Z32__device_stub__Z6mmul_dPfiiS_iS_PfiiS_iS_, @function
_Z32__device_stub__Z6mmul_dPfiiS_iS_PfiiS_iS_:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6mmul_dPfiiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z6mmul_dPfiiS_iS_PfiiS_iS_, .-_Z32__device_stub__Z6mmul_dPfiiS_iS_PfiiS_iS_
.globl _Z6mmul_dPfiiS_iS_
.type _Z6mmul_dPfiiS_iS_, @function
_Z6mmul_dPfiiS_iS_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6mmul_dPfiiS_iS_PfiiS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z6mmul_dPfiiS_iS_, .-_Z6mmul_dPfiiS_iS_
.globl _Z40__device_stub__Z13mmul_d_threadPfiiS_iS_PfiiS_iS_
.type _Z40__device_stub__Z13mmul_d_threadPfiiS_iS_PfiiS_iS_, @function
_Z40__device_stub__Z13mmul_d_threadPfiiS_iS_PfiiS_iS_:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13mmul_d_threadPfiiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z13mmul_d_threadPfiiS_iS_PfiiS_iS_, .-_Z40__device_stub__Z13mmul_d_threadPfiiS_iS_PfiiS_iS_
.globl _Z13mmul_d_threadPfiiS_iS_
.type _Z13mmul_d_threadPfiiS_iS_, @function
_Z13mmul_d_threadPfiiS_iS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13mmul_d_threadPfiiS_iS_PfiiS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z13mmul_d_threadPfiiS_iS_, .-_Z13mmul_d_threadPfiiS_iS_
.globl _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.type _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2089:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, .-_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.type _Z14matrixMultiplyPfS_S_iiiiii, @function
_Z14matrixMultiplyPfS_S_iiiiii:
.LFB2090:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z14matrixMultiplyPfS_S_iiiiii, .-_Z14matrixMultiplyPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "insufficient args. for A x B = C, required args: [row num A] [col num A/row num B] [col num B] [cuda block size] [reps] [optimized] [compare]\n"
.section .rodata.str1.1
.LC7:
.string "first:\n"
.LC8:
.string "second:\n"
.LC9:
.string "multiply:\n"
.LC11:
.string "%d\t%d\t%d\t%d\t%d\t%.6f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jle .L71
movl %edi, %r13d
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 92(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 72(%rsp)
movl %eax, (%rsp)
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 64(%rsp)
movl %eax, %ecx
movl $0, 88(%rsp)
testl %eax, %eax
jle .L56
movl %ebx, %eax
imull %r12d, %eax
cltd
idivl %ecx
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, 88(%rsp)
.L56:
movq 40(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 80(%rsp)
movl %eax, 56(%rsp)
cmpl $6, %r13d
jg .L72
movl $0, 60(%rsp)
movl $0, 52(%rsp)
.L57:
movq 72(%rsp), %rsi
movl %esi, %eax
subl $1, %eax
movl $20, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 120(%rsp)
leal -1(%rbx), %eax
cltd
idivl %ecx
addl $1, %eax
movl %eax, 124(%rsp)
movl $1, 128(%rsp)
movl $20, 132(%rsp)
movl $20, 136(%rsp)
movl $1, 140(%rsp)
cmpl $0, 80(%rsp)
jle .L68
movl %ebx, %r15d
imull %r12d, %r15d
movslq %r15d, %r15
salq $2, %r15
imull %esi, %r12d
movslq %r12d, %r12
salq $2, %r12
imull %esi, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq $0x000000000, 8(%rsp)
movl $0, %r13d
movq %r15, 16(%rsp)
movq %r12, 24(%rsp)
movq %rbx, 32(%rsp)
movl (%rsp), %r15d
movl 92(%rsp), %ebx
jmp .L63
.L71:
leaq .LC4(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L53
.L72:
movq 48(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 60(%rsp)
movl $0, 52(%rsp)
cmpl $7, %r13d
jle .L57
movq 56(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 52(%rsp)
jmp .L57
.L75:
movl 140(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movq 120(%rsp), %rdi
movl 128(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L60:
movl $2, %ecx
movq 32(%rsp), %rdx
movq 112(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpl $1, 52(%rsp)
je .L74
.L62:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 40(%rsp), %xmm0
divsd .LC10(%rip), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addl $1, %r13d
movl 56(%rsp), %eax
cmpl %eax, %r13d
je .L58
.L63:
call clock@PLT
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movsd %xmm2, 40(%rsp)
movss .LC5(%rip), %xmm0
movl %ebx, %esi
movl %r14d, %edi
call _Z18create_flat_matrixiif
movq %rax, (%rsp)
movss .LC6(%rip), %xmm0
movl %r15d, %esi
movl %ebx, %edi
call _Z18create_flat_matrixiif
movq %rax, %rbp
pxor %xmm0, %xmm0
movl %r15d, %esi
movl %r14d, %edi
call _Z18create_flat_matrixiif
movq %rax, %r12
leaq 96(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq 24(%rsp), %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq 32(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 16(%rsp), %rdx
movq (%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 24(%rsp), %rdx
movq %rbp, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, 60(%rsp)
je .L75
movl 64(%rsp), %eax
movl %eax, 156(%rsp)
movl $1, 160(%rsp)
movl 88(%rsp), %eax
movl %eax, 144(%rsp)
movl $1, 148(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L60
movq 112(%rsp), %r9
movl %r15d, %r8d
movq 104(%rsp), %rcx
movl %ebx, %edx
movl %r14d, %esi
movq 96(%rsp), %rdi
call _Z40__device_stub__Z13mmul_d_threadPfiiS_iS_PfiiS_iS_
jmp .L60
.L73:
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq %r15
.cfi_def_cfa_offset 256
pushq %r14
.cfi_def_cfa_offset 264
pushq %r15
.cfi_def_cfa_offset 272
movl %ebx, %r9d
movl %ebx, %r8d
movl %r14d, %ecx
movq 144(%rsp), %rdx
movq 136(%rsp), %rsi
movq 128(%rsp), %rdi
call _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
addq $32, %rsp
.cfi_def_cfa_offset 240
jmp .L60
.L74:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %r14d, %esi
movq (%rsp), %rdi
call _Z17print_flat_matrixPfii
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
movl %ebx, %esi
movq %rbp, %rdi
call _Z17print_flat_matrixPfii
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
movl %r14d, %esi
movq %r12, %rdi
call _Z17print_flat_matrixPfii
jmp .L62
.L68:
movq $0x000000000, 8(%rsp)
.L58:
movq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq %rax
.cfi_def_cfa_offset 256
movl 80(%rsp), %r9d
movl 88(%rsp), %r8d
movl 108(%rsp), %ecx
movl %r14d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
movl $0, %eax
.L53:
movq 168(%rsp), %rdx
subq %fs:40, %rdx
jne .L76
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z14matrixMultiplyPfS_S_iiiiii"
.section .rodata.str1.1
.LC13:
.string "_Z13mmul_d_threadPfiiS_iS_"
.LC14:
.string "_Z6mmul_dPfiiS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mmul_d_threadPfiiS_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mmul_dPfiiS_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1065353216
.align 4
.LC6:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// author: yohanes.gultom@gmail.com
// partial source: https://gist.github.com/wh5a/4313739
#include <stdio.h>
#include <time.h>
#define TILE_WIDTH 20
// create random matrix row-major-format
float* create_flat_matrix_rand(int row, int col, int max)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
float val = (max > 0) ? (float)(rand() % max) : 0.0f;
m[col * i + j] = val;
}
}
return m;
}
float* create_flat_matrix(int row, int col, float val)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
m[col * i + j] = val;
}
}
return m;
}
// print matrix row-major-format
void print_flat_matrix(float *m, int row, int col)
{
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
printf("%.2f ", m[col * i + j]);
}
printf("\n");
}
}
__global__ void mmul_d(float *first, int m, int p, float *second, int q, float *multiply)
{
int c, d, k = 0;
float sum = .0f;
for (c = 0; c < m; c++) {
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
}
__global__ void mmul_d_thread(float *first, int m, int p, float *second, int q, float *multiply)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int d, k = 0;
float sum = .0f;
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
// Compute C = A * B
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * TILE_WIDTH + ty,
Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) {
if (Row < numARows && m*TILE_WIDTH+tx < numAColumns)
ds_M[ty][tx] = A[Row*numAColumns + m*TILE_WIDTH+tx];
else
ds_M[ty][tx] = 0;
if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows)
ds_N[ty][tx] = B[(m*TILE_WIDTH+ty)*numBColumns+Col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += ds_M[ty][k] * ds_N[k][tx];
__syncthreads();
}
if (Row < numCRows && Col < numCColumns)
C[Row*numCColumns+Col] = Pvalue;
}
int main(int argc, char** argv)
{
if (argc < 6) {
printf("insufficient args. for A x B = C, required args: [row num A] [col num A/row num B] [col num B] [cuda block size] [reps] [optimized] [compare]\n");
return EXIT_FAILURE;
}
int m, n, p, q = 0;
m = atoi(argv[1]);
n = atoi(argv[2]);
p = n;
q = atoi(argv[3]);
int blockSize = atoi(argv[4]);
int nBlocks = (blockSize > 0) ? (m * n) / blockSize + ((m * n) % blockSize == 0 ? 0 : 1) : 0;
int reps = atoi(argv[5]);
// optimized = ignore blockSize and nBlocks
int optimized = (argc >= 7) ? atoi(argv[6]):0;
int compare = (argc >= 8) ? atoi(argv[7]):0;
//@@ Initialize the optimized grid and block dimensions here
dim3 dimGrid((q-1)/TILE_WIDTH+1, (m-1)/TILE_WIDTH+1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
float *first_d, *second_d, *multiply_d;
float *first, *second, *multiply;
int i = 0;
double total_time = 0.0f;
for (i = 0; i < reps; i++) {
double exec_time = ((double) clock()) * -1;
first = create_flat_matrix(m, n, 1);
second = create_flat_matrix(p, q, 2);
multiply = create_flat_matrix(m, q, 0);
cudaMalloc((void **) &first_d, m * n * sizeof(float));
cudaMalloc((void **) &second_d, p * q * sizeof(float));
cudaMalloc((void **) &multiply_d, m * q * sizeof(float));
cudaMemcpy(first_d, first, m * n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(second_d, second, p * q * sizeof(float), cudaMemcpyHostToDevice);
if (optimized == 1) {
matrixMultiply<<<dimGrid, dimBlock>>>(first_d, second_d, multiply_d, m, n, p, q, m, q);
} else {
mmul_d_thread <<< nBlocks, blockSize >>> (first_d, m, n, second_d, q, multiply_d);
}
cudaMemcpy(multiply, multiply_d, m * q * sizeof(float), cudaMemcpyDeviceToHost);
if (compare == 1) {
printf("first:\n");
print_flat_matrix(first, m, n);
printf("second:\n");
print_flat_matrix(second, p, q);
printf("multiply:\n");
print_flat_matrix(multiply, m, q);
}
free(multiply); free(second); free(first);
cudaFree(first_d); cudaFree(second_d); cudaFree(multiply_d);
total_time = total_time + ((exec_time + ((double)clock())) / CLOCKS_PER_SEC);
// printf("%d: %.6f\n", i, ((exec_time + ((double)clock())) / CLOCKS_PER_SEC));
}
printf("%d\t%d\t%d\t%d\t%d\t%.6f\n", m, n, q, blockSize, reps, (total_time / reps));
return EXIT_SUCCESS;
}
|
// author: yohanes.gultom@gmail.com
// partial source: https://gist.github.com/wh5a/4313739
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define TILE_WIDTH 20
// create random matrix row-major-format
float* create_flat_matrix_rand(int row, int col, int max)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
float val = (max > 0) ? (float)(rand() % max) : 0.0f;
m[col * i + j] = val;
}
}
return m;
}
float* create_flat_matrix(int row, int col, float val)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
m[col * i + j] = val;
}
}
return m;
}
// print matrix row-major-format
void print_flat_matrix(float *m, int row, int col)
{
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
printf("%.2f ", m[col * i + j]);
}
printf("\n");
}
}
__global__ void mmul_d(float *first, int m, int p, float *second, int q, float *multiply)
{
int c, d, k = 0;
float sum = .0f;
for (c = 0; c < m; c++) {
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
}
__global__ void mmul_d_thread(float *first, int m, int p, float *second, int q, float *multiply)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int d, k = 0;
float sum = .0f;
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
// Compute C = A * B
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * TILE_WIDTH + ty,
Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) {
if (Row < numARows && m*TILE_WIDTH+tx < numAColumns)
ds_M[ty][tx] = A[Row*numAColumns + m*TILE_WIDTH+tx];
else
ds_M[ty][tx] = 0;
if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows)
ds_N[ty][tx] = B[(m*TILE_WIDTH+ty)*numBColumns+Col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += ds_M[ty][k] * ds_N[k][tx];
__syncthreads();
}
if (Row < numCRows && Col < numCColumns)
C[Row*numCColumns+Col] = Pvalue;
}
int main(int argc, char** argv)
{
if (argc < 6) {
printf("insufficient args. for A x B = C, required args: [row num A] [col num A/row num B] [col num B] [cuda block size] [reps] [optimized] [compare]\n");
return EXIT_FAILURE;
}
int m, n, p, q = 0;
m = atoi(argv[1]);
n = atoi(argv[2]);
p = n;
q = atoi(argv[3]);
int blockSize = atoi(argv[4]);
int nBlocks = (blockSize > 0) ? (m * n) / blockSize + ((m * n) % blockSize == 0 ? 0 : 1) : 0;
int reps = atoi(argv[5]);
// optimized = ignore blockSize and nBlocks
int optimized = (argc >= 7) ? atoi(argv[6]):0;
int compare = (argc >= 8) ? atoi(argv[7]):0;
//@@ Initialize the optimized grid and block dimensions here
dim3 dimGrid((q-1)/TILE_WIDTH+1, (m-1)/TILE_WIDTH+1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
float *first_d, *second_d, *multiply_d;
float *first, *second, *multiply;
int i = 0;
double total_time = 0.0f;
for (i = 0; i < reps; i++) {
double exec_time = ((double) clock()) * -1;
first = create_flat_matrix(m, n, 1);
second = create_flat_matrix(p, q, 2);
multiply = create_flat_matrix(m, q, 0);
hipMalloc((void **) &first_d, m * n * sizeof(float));
hipMalloc((void **) &second_d, p * q * sizeof(float));
hipMalloc((void **) &multiply_d, m * q * sizeof(float));
hipMemcpy(first_d, first, m * n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(second_d, second, p * q * sizeof(float), hipMemcpyHostToDevice);
if (optimized == 1) {
matrixMultiply<<<dimGrid, dimBlock>>>(first_d, second_d, multiply_d, m, n, p, q, m, q);
} else {
mmul_d_thread <<< nBlocks, blockSize >>> (first_d, m, n, second_d, q, multiply_d);
}
hipMemcpy(multiply, multiply_d, m * q * sizeof(float), hipMemcpyDeviceToHost);
if (compare == 1) {
printf("first:\n");
print_flat_matrix(first, m, n);
printf("second:\n");
print_flat_matrix(second, p, q);
printf("multiply:\n");
print_flat_matrix(multiply, m, q);
}
free(multiply); free(second); free(first);
hipFree(first_d); hipFree(second_d); hipFree(multiply_d);
total_time = total_time + ((exec_time + ((double)clock())) / CLOCKS_PER_SEC);
// printf("%d: %.6f\n", i, ((exec_time + ((double)clock())) / CLOCKS_PER_SEC));
}
printf("%d\t%d\t%d\t%d\t%d\t%.6f\n", m, n, q, blockSize, reps, (total_time / reps));
return EXIT_SUCCESS;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// author: yohanes.gultom@gmail.com
// partial source: https://gist.github.com/wh5a/4313739
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define TILE_WIDTH 20
// create random matrix row-major-format
float* create_flat_matrix_rand(int row, int col, int max)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
float val = (max > 0) ? (float)(rand() % max) : 0.0f;
m[col * i + j] = val;
}
}
return m;
}
float* create_flat_matrix(int row, int col, float val)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
m[col * i + j] = val;
}
}
return m;
}
// print matrix row-major-format
void print_flat_matrix(float *m, int row, int col)
{
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
printf("%.2f ", m[col * i + j]);
}
printf("\n");
}
}
__global__ void mmul_d(float *first, int m, int p, float *second, int q, float *multiply)
{
int c, d, k = 0;
float sum = .0f;
for (c = 0; c < m; c++) {
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
}
__global__ void mmul_d_thread(float *first, int m, int p, float *second, int q, float *multiply)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int d, k = 0;
float sum = .0f;
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
// Compute C = A * B
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * TILE_WIDTH + ty,
Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) {
if (Row < numARows && m*TILE_WIDTH+tx < numAColumns)
ds_M[ty][tx] = A[Row*numAColumns + m*TILE_WIDTH+tx];
else
ds_M[ty][tx] = 0;
if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows)
ds_N[ty][tx] = B[(m*TILE_WIDTH+ty)*numBColumns+Col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += ds_M[ty][k] * ds_N[k][tx];
__syncthreads();
}
if (Row < numCRows && Col < numCColumns)
C[Row*numCColumns+Col] = Pvalue;
}
int main(int argc, char** argv)
{
if (argc < 6) {
printf("insufficient args. for A x B = C, required args: [row num A] [col num A/row num B] [col num B] [cuda block size] [reps] [optimized] [compare]\n");
return EXIT_FAILURE;
}
int m, n, p, q = 0;
m = atoi(argv[1]);
n = atoi(argv[2]);
p = n;
q = atoi(argv[3]);
int blockSize = atoi(argv[4]);
int nBlocks = (blockSize > 0) ? (m * n) / blockSize + ((m * n) % blockSize == 0 ? 0 : 1) : 0;
int reps = atoi(argv[5]);
// optimized = ignore blockSize and nBlocks
int optimized = (argc >= 7) ? atoi(argv[6]):0;
int compare = (argc >= 8) ? atoi(argv[7]):0;
//@@ Initialize the optimized grid and block dimensions here
dim3 dimGrid((q-1)/TILE_WIDTH+1, (m-1)/TILE_WIDTH+1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
float *first_d, *second_d, *multiply_d;
float *first, *second, *multiply;
int i = 0;
double total_time = 0.0f;
for (i = 0; i < reps; i++) {
double exec_time = ((double) clock()) * -1;
first = create_flat_matrix(m, n, 1);
second = create_flat_matrix(p, q, 2);
multiply = create_flat_matrix(m, q, 0);
hipMalloc((void **) &first_d, m * n * sizeof(float));
hipMalloc((void **) &second_d, p * q * sizeof(float));
hipMalloc((void **) &multiply_d, m * q * sizeof(float));
hipMemcpy(first_d, first, m * n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(second_d, second, p * q * sizeof(float), hipMemcpyHostToDevice);
if (optimized == 1) {
matrixMultiply<<<dimGrid, dimBlock>>>(first_d, second_d, multiply_d, m, n, p, q, m, q);
} else {
mmul_d_thread <<< nBlocks, blockSize >>> (first_d, m, n, second_d, q, multiply_d);
}
hipMemcpy(multiply, multiply_d, m * q * sizeof(float), hipMemcpyDeviceToHost);
if (compare == 1) {
printf("first:\n");
print_flat_matrix(first, m, n);
printf("second:\n");
print_flat_matrix(second, p, q);
printf("multiply:\n");
print_flat_matrix(multiply, m, q);
}
free(multiply); free(second); free(first);
hipFree(first_d); hipFree(second_d); hipFree(multiply_d);
total_time = total_time + ((exec_time + ((double)clock())) / CLOCKS_PER_SEC);
// printf("%d: %.6f\n", i, ((exec_time + ((double)clock())) / CLOCKS_PER_SEC));
}
printf("%d\t%d\t%d\t%d\t%d\t%.6f\n", m, n, q, blockSize, reps, (total_time / reps));
return EXIT_SUCCESS;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6mmul_dPfiiS_iS_
.globl _Z6mmul_dPfiiS_iS_
.p2align 8
.type _Z6mmul_dPfiiS_iS_,@function
_Z6mmul_dPfiiS_iS_:
s_load_b32 s16, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB0_9
s_clause 0x4
s_load_b32 s17, s[0:1], 0x18
s_load_b32 s18, s[0:1], 0xc
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_mov_b32 s9, 0
s_mov_b32 s19, 0
s_mov_b32 s10, s9
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s17, 0
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s18, 0
v_cndmask_b32_e64 v0, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, 1, s0
v_cmp_ne_u32_e64 s0, 1, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u32_e64 s1, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s19, s19, 1
s_add_i32 s10, s10, s16
s_cmp_lg_u32 s19, s16
s_cbranch_scc0 .LBB0_9
.LBB0_3:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_mov_b32 s11, s9
s_mov_b32 s20, 0
s_lshl_b64 s[12:13], s[10:11], 2
s_mul_i32 s11, s19, s17
s_add_u32 s12, s2, s12
s_addc_u32 s13, s3, s13
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_add_i32 s8, s20, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[8:9], 2
s_add_u32 s14, s6, s14
s_addc_u32 s15, s7, s15
s_add_i32 s20, s20, 1
global_store_b32 v0, v1, s[14:15]
s_cmp_lg_u32 s20, s17
s_cbranch_scc0 .LBB0_2
.LBB0_6:
v_mov_b32_e32 v1, 0
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_5
s_mov_b64 s[14:15], s[12:13]
s_mov_b32 s8, s20
s_mov_b32 s21, s18
.LBB0_8:
s_lshl_b64 s[22:23], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s22, s4, s22
s_addc_u32 s23, s5, s23
s_clause 0x1
global_load_b32 v2, v0, s[14:15]
global_load_b32 v3, v0, s[22:23]
s_add_i32 s21, s21, -1
s_add_i32 s8, s8, s17
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cmp_lg_u32 s21, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v2, v3
s_cbranch_scc1 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6mmul_dPfiiS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6mmul_dPfiiS_iS_, .Lfunc_end0-_Z6mmul_dPfiiS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13mmul_d_threadPfiiS_iS_
.globl _Z13mmul_d_threadPfiiS_iS_
.p2align 8
.type _Z13mmul_d_threadPfiiS_iS_,@function
_Z13mmul_d_threadPfiiS_iS_:
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB1_6
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s5, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x20
s_cselect_b32 s0, -1, 0
s_mov_b32 s1, 0
v_cndmask_b32_e64 v0, 0, 1, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s4
v_mul_lo_u32 v4, v1, s10
v_cmp_ne_u32_e64 s0, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s9, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
v_add_nc_u32_e32 v2, s1, v4
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s1, s10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v6, off
s_cbranch_scc0 .LBB1_6
.LBB1_3:
v_mov_b32_e32 v6, 0
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB1_2
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v1
v_mov_b32_e32 v2, v0
s_mov_b32 s8, s1
s_mov_b32 s4, s5
.LBB1_5:
s_lshl_b64 s[12:13], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s6, s12
s_addc_u32 s13, s7, s13
global_load_b32 v7, v[2:3], off
global_load_b32 v8, v5, s[12:13]
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s4, s4, -1
s_add_i32 s8, s8, s10
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v7, v8
s_cbranch_scc1 .LBB1_5
s_branch .LBB1_2
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13mmul_d_threadPfiiS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13mmul_d_threadPfiiS_iS_, .Lfunc_end1-_Z13mmul_d_threadPfiiS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14matrixMultiplyPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 8
.type _Z14matrixMultiplyPfS_S_iiiiii,@function
_Z14matrixMultiplyPfS_S_iiiiii:
s_load_b32 s10, s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, 20, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, 20, v[4:5]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmpk_lt_i32 s10, 0xffee
s_cbranch_scc1 .LBB2_18
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v4
s_add_i32 s3, s10, -1
v_mad_u64_u32 v[5:6], null, v0, s10, v[4:5]
s_mul_hi_i32 s3, s3, 0x66666667
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, 0x640, v2
s_lshr_b32 s13, s3, 31
s_ashr_i32 s3, s3, 3
v_mul_u32_u24_e32 v8, 0x50, v3
v_mad_u32_u24 v11, v3, 0x50, v2
v_mad_u32_u24 v12, v3, 0x50, v9
v_mov_b32_e32 v2, 0
s_add_i32 s3, s3, s13
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_le_i32_e64 s11, s2, v0
v_cmp_gt_i32_e64 s2, s9, v1
v_cmp_le_i32_e64 s12, s9, v1
.LBB2_2:
s_delay_alu instid0(VALU_DEP_3)
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_mul_i32 s17, s14, 20
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v7, s17, v4
v_mov_b32_e32 v13, s17
s_and_not1_b32 s17, s11, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s10, v7
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB2_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v11, v10
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB2_8
v_add_nc_u32_e32 v14, v5, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s3, s4, v14
v_add_co_ci_u32_e64 v15, s3, s5, v15, s3
global_load_b32 v7, v[14:15], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v7
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_mad_u64_u32 v[6:7], null, s14, 20, v[3:4]
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s8, v6
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB2_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v12, v10
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB2_14
v_mad_u64_u32 v[14:15], null, v6, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s3, s6, v14
v_add_co_ci_u32_e64 v15, s3, s7, v15, s3
global_load_b32 v7, v[14:15], off
s_waitcnt vmcnt(0)
ds_store_b32 v12, v7
.LBB2_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v7, v9
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_15:
v_add_nc_u32_e32 v14, s3, v8
s_add_i32 s3, s3, 4
ds_load_b32 v15, v7
ds_load_b32 v14, v14
v_add_nc_u32_e32 v7, 0x50, v7
s_cmpk_eq_i32 s3, 0x50
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v14, v15
s_cbranch_scc0 .LBB2_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_18
s_mov_b32 s14, s3
s_branch .LBB2_2
.LBB2_18:
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 3200
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14matrixMultiplyPfS_S_iiiiii, .Lfunc_end2-_Z14matrixMultiplyPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6mmul_dPfiiS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z6mmul_dPfiiS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13mmul_d_threadPfiiS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13mmul_d_threadPfiiS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 3200
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// author: yohanes.gultom@gmail.com
// partial source: https://gist.github.com/wh5a/4313739
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define TILE_WIDTH 20
// create random matrix row-major-format
float* create_flat_matrix_rand(int row, int col, int max)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
float val = (max > 0) ? (float)(rand() % max) : 0.0f;
m[col * i + j] = val;
}
}
return m;
}
float* create_flat_matrix(int row, int col, float val)
{
float* m = (float*)malloc(row*col*sizeof(float));
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
m[col * i + j] = val;
}
}
return m;
}
// print matrix row-major-format
void print_flat_matrix(float *m, int row, int col)
{
int i, j = 0;
for (i = 0; i < row; i++) {
for (j = 0; j < col; j++) {
printf("%.2f ", m[col * i + j]);
}
printf("\n");
}
}
__global__ void mmul_d(float *first, int m, int p, float *second, int q, float *multiply)
{
int c, d, k = 0;
float sum = .0f;
for (c = 0; c < m; c++) {
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
}
__global__ void mmul_d_thread(float *first, int m, int p, float *second, int q, float *multiply)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int d, k = 0;
float sum = .0f;
for (d = 0; d < q; d++) {
for (k = 0; k < p; k++) {
sum = sum + first[c*m+k] * second[k*q+d];
}
multiply[c*q+d] = sum;
sum = 0;
}
}
// Compute C = A * B
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * TILE_WIDTH + ty,
Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) {
if (Row < numARows && m*TILE_WIDTH+tx < numAColumns)
ds_M[ty][tx] = A[Row*numAColumns + m*TILE_WIDTH+tx];
else
ds_M[ty][tx] = 0;
if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows)
ds_N[ty][tx] = B[(m*TILE_WIDTH+ty)*numBColumns+Col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k)
Pvalue += ds_M[ty][k] * ds_N[k][tx];
__syncthreads();
}
if (Row < numCRows && Col < numCColumns)
C[Row*numCColumns+Col] = Pvalue;
}
int main(int argc, char** argv)
{
if (argc < 6) {
printf("insufficient args. for A x B = C, required args: [row num A] [col num A/row num B] [col num B] [cuda block size] [reps] [optimized] [compare]\n");
return EXIT_FAILURE;
}
int m, n, p, q = 0;
m = atoi(argv[1]);
n = atoi(argv[2]);
p = n;
q = atoi(argv[3]);
int blockSize = atoi(argv[4]);
int nBlocks = (blockSize > 0) ? (m * n) / blockSize + ((m * n) % blockSize == 0 ? 0 : 1) : 0;
int reps = atoi(argv[5]);
// optimized = ignore blockSize and nBlocks
int optimized = (argc >= 7) ? atoi(argv[6]):0;
int compare = (argc >= 8) ? atoi(argv[7]):0;
//@@ Initialize the optimized grid and block dimensions here
dim3 dimGrid((q-1)/TILE_WIDTH+1, (m-1)/TILE_WIDTH+1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
float *first_d, *second_d, *multiply_d;
float *first, *second, *multiply;
int i = 0;
double total_time = 0.0f;
for (i = 0; i < reps; i++) {
double exec_time = ((double) clock()) * -1;
first = create_flat_matrix(m, n, 1);
second = create_flat_matrix(p, q, 2);
multiply = create_flat_matrix(m, q, 0);
hipMalloc((void **) &first_d, m * n * sizeof(float));
hipMalloc((void **) &second_d, p * q * sizeof(float));
hipMalloc((void **) &multiply_d, m * q * sizeof(float));
hipMemcpy(first_d, first, m * n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(second_d, second, p * q * sizeof(float), hipMemcpyHostToDevice);
if (optimized == 1) {
matrixMultiply<<<dimGrid, dimBlock>>>(first_d, second_d, multiply_d, m, n, p, q, m, q);
} else {
mmul_d_thread <<< nBlocks, blockSize >>> (first_d, m, n, second_d, q, multiply_d);
}
hipMemcpy(multiply, multiply_d, m * q * sizeof(float), hipMemcpyDeviceToHost);
if (compare == 1) {
printf("first:\n");
print_flat_matrix(first, m, n);
printf("second:\n");
print_flat_matrix(second, p, q);
printf("multiply:\n");
print_flat_matrix(multiply, m, q);
}
free(multiply); free(second); free(first);
hipFree(first_d); hipFree(second_d); hipFree(multiply_d);
total_time = total_time + ((exec_time + ((double)clock())) / CLOCKS_PER_SEC);
// printf("%d: %.6f\n", i, ((exec_time + ((double)clock())) / CLOCKS_PER_SEC));
}
printf("%d\t%d\t%d\t%d\t%d\t%.6f\n", m, n, q, blockSize, reps, (total_time / reps));
return EXIT_SUCCESS;
}
|
.text
.file "mmul_cuda_20.hip"
.globl _Z23create_flat_matrix_randiii # -- Begin function _Z23create_flat_matrix_randiii
.p2align 4, 0x90
.type _Z23create_flat_matrix_randiii,@function
_Z23create_flat_matrix_randiii: # @_Z23create_flat_matrix_randiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movl %edi, %r15d
movl %esi, %eax
imull %edi, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB0_9
# %bb.1: # %.preheader.lr.ph
movl %r15d, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %r12d
xorl %r13d, %r13d
xorl %r14d, %r14d
movl %ebp, 4(%rsp) # 4-byte Spill
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r14
movl 4(%rsp), %ebp # 4-byte Reload
addl %ebp, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB0_9
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ebp, %ebp
jle .LBB0_8
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %ebp, %ebp
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=2
callq rand
cltd
idivl %ebx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
.LBB0_7: # in Loop: Header=BB0_4 Depth=2
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %r12
je .LBB0_8
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
testl %ebx, %ebx
jg .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=2
xorps %xmm0, %xmm0
jmp .LBB0_7
.LBB0_9: # %._crit_edge20
movq 8(%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23create_flat_matrix_randiii, .Lfunc_end0-_Z23create_flat_matrix_randiii
.cfi_endproc
# -- End function
.globl _Z18create_flat_matrixiif # -- Begin function _Z18create_flat_matrixiif
.p2align 4, 0x90
.type _Z18create_flat_matrixiif,@function
_Z18create_flat_matrixiif: # @_Z18create_flat_matrixiif
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl %esi, %ebx
movl %edi, %ebp
movl %esi, %eax
imull %edi, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
testl %ebp, %ebp
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %ecx
movl %ebx, %edx
xorl %esi, %esi
xorl %edi, %edi
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rdi
addl %ebx, %esi
cmpq %rcx, %rdi
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %esi, %r8d
leaq (%rax,%r8,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%r8,%r9,4)
incq %r9
cmpq %r9, %rdx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge17
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18create_flat_matrixiif, .Lfunc_end1-_Z18create_flat_matrixiif
.cfi_endproc
# -- End function
.globl _Z17print_flat_matrixPfii # -- Begin function _Z17print_flat_matrixPfii
.p2align 4, 0x90
.type _Z17print_flat_matrixPfii,@function
_Z17print_flat_matrixPfii: # @_Z17print_flat_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17print_flat_matrixPfii, .Lfunc_end2-_Z17print_flat_matrixPfii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__mmul_dPfiiS_iS_ # -- Begin function _Z21__device_stub__mmul_dPfiiS_iS_
.p2align 4, 0x90
.type _Z21__device_stub__mmul_dPfiiS_iS_,@function
_Z21__device_stub__mmul_dPfiiS_iS_: # @_Z21__device_stub__mmul_dPfiiS_iS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6mmul_dPfiiS_iS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z21__device_stub__mmul_dPfiiS_iS_, .Lfunc_end3-_Z21__device_stub__mmul_dPfiiS_iS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__mmul_d_threadPfiiS_iS_ # -- Begin function _Z28__device_stub__mmul_d_threadPfiiS_iS_
.p2align 4, 0x90
.type _Z28__device_stub__mmul_d_threadPfiiS_iS_,@function
_Z28__device_stub__mmul_d_threadPfiiS_iS_: # @_Z28__device_stub__mmul_d_threadPfiiS_iS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13mmul_d_threadPfiiS_iS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z28__device_stub__mmul_d_threadPfiiS_iS_, .Lfunc_end4-_Z28__device_stub__mmul_d_threadPfiiS_iS_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__matrixMultiplyPfS_S_iiiiii # -- Begin function _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.p2align 4, 0x90
.type _Z29__device_stub__matrixMultiplyPfS_S_iiiiii,@function
_Z29__device_stub__matrixMultiplyPfS_S_iiiiii: # @_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matrixMultiplyPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end5:
.size _Z29__device_stub__matrixMultiplyPfS_S_iiiiii, .Lfunc_end5-_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jg .LBB6_2
# %bb.1:
movl $.Lstr.3, %edi
callq puts@PLT
movl $1, %eax
jmp .LBB6_56
.LBB6_2:
movq %rsi, %rbx
movl %edi, %ebp
movabsq $4294967296, %r13 # imm = 0x100000000
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rcx
movq %r13, 224(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB6_4
# %bb.3:
movl %r15d, %eax
imull %r14d, %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
orq %r13, %rax
movq %rax, 224(%rsp) # 8-byte Spill
.LBB6_4:
movq %rcx, 216(%rsp) # 8-byte Spill
movq 40(%rbx), %rdi
xorl %eax, %eax
movq %rax, 232(%rsp) # 8-byte Spill
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
cmpl $6, %ebp
je .LBB6_6
# %bb.5:
movq 48(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
sete %al
movq %rax, 232(%rsp) # 8-byte Spill
.LBB6_6:
cmpl $8, %ebp
jl .LBB6_7
# %bb.8:
movq 56(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
sete %al
movl %eax, 28(%rsp) # 4-byte Spill
jmp .LBB6_9
.LBB6_7:
movl $0, 28(%rsp) # 4-byte Folded Spill
.LBB6_9:
movq 8(%rsp), %rsi # 8-byte Reload
cmpl $0, 72(%rsp) # 4-byte Folded Reload
jle .LBB6_10
# %bb.11: # %.lr.ph
leal -1(%rsi), %eax
cltq
imulq $1717986919, %rax, %rax # imm = 0x66666667
movq %rax, %rcx
sarq $35, %rcx
shrq $63, %rax
addl %ecx, %eax
incl %eax
leal -1(%r14), %ecx
movslq %ecx, %rcx
imulq $1717986919, %rcx, %rcx # imm = 0x66666667
movq %rcx, %rdx
sarq $35, %rdx
shrq $63, %rcx
addl %edx, %ecx
incl %ecx
shlq $32, %rcx
orq %rax, %rcx
movq %rcx, 264(%rsp) # 8-byte Spill
movq %r14, %rcx
shlq $32, %rcx
movq %r15, %rax
imulq %rcx, %rax
sarq $30, %rax
movq %rax, 248(%rsp) # 8-byte Spill
movl %r14d, %eax
movq %rax, 40(%rsp) # 8-byte Spill
movl %r15d, %r12d
movl %r15d, %eax
imull %esi, %eax
cltq
shlq $2, %rax
movq %rax, 240(%rsp) # 8-byte Spill
movl %esi, %ebp
imulq %rsi, %rcx
sarq $30, %rcx
movq %rcx, 96(%rsp) # 8-byte Spill
movl 216(%rsp), %eax # 4-byte Reload
orq %r13, %rax
movq %rax, 256(%rsp) # 8-byte Spill
leaq (,%rbp,4), %rax
movq %rax, 288(%rsp) # 8-byte Spill
shlq $2, %rsi
movq %rsi, 296(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
xorl %eax, %eax
movq %r14, 88(%rsp) # 8-byte Spill
movq %r15, 120(%rsp) # 8-byte Spill
jmp .LBB6_12
.p2align 4, 0x90
.LBB6_54: # %_Z17print_flat_matrixPfii.exit165
# in Loop: Header=BB6_12 Depth=1
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 104(%rsp), %rdi # 8-byte Reload
callq free
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
callq clock
cvtsi2sd %rax, %xmm1
subsd 80(%rsp), %xmm1 # 8-byte Folded Reload
divsd .LCPI6_0(%rip), %xmm1
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movq 272(%rsp), %rax # 8-byte Reload
incl %eax
cmpl 72(%rsp), %eax # 4-byte Folded Reload
movq 88(%rsp), %r14 # 8-byte Reload
movq 120(%rsp), %r15 # 8-byte Reload
je .LBB6_55
.LBB6_12: # =>This Loop Header: Depth=1
# Child Loop BB6_14 Depth 2
# Child Loop BB6_16 Depth 3
# Child Loop BB6_20 Depth 2
# Child Loop BB6_22 Depth 3
# Child Loop BB6_26 Depth 2
# Child Loop BB6_38 Depth 2
# Child Loop BB6_40 Depth 3
# Child Loop BB6_44 Depth 2
# Child Loop BB6_46 Depth 3
# Child Loop BB6_50 Depth 2
# Child Loop BB6_52 Depth 3
movq %rax, 272(%rsp) # 8-byte Spill
movsd %xmm0, 280(%rsp) # 8-byte Spill
callq clock
movq %rax, 80(%rsp) # 8-byte Spill
movq 248(%rsp), %rdi # 8-byte Reload
callq malloc
testl %r14d, %r14d
jle .LBB6_18
# %bb.13: # %.preheader.i.preheader
# in Loop: Header=BB6_12 Depth=1
xorl %edi, %edi
xorl %ecx, %ecx
jmp .LBB6_14
.p2align 4, 0x90
.LBB6_17: # %._crit_edge.i
# in Loop: Header=BB6_14 Depth=2
incq %rcx
addl %r15d, %edi
cmpq 40(%rsp), %rcx # 8-byte Folded Reload
je .LBB6_18
.LBB6_14: # %.preheader.i
# Parent Loop BB6_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_16 Depth 3
testl %r15d, %r15d
jle .LBB6_17
# %bb.15: # %.lr.ph.i
# in Loop: Header=BB6_14 Depth=2
movl %edi, %edx
leaq (%rax,%rdx,4), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_16: # Parent Loop BB6_12 Depth=1
# Parent Loop BB6_14 Depth=2
# => This Inner Loop Header: Depth=3
movl $1065353216, (%rdx,%rsi,4) # imm = 0x3F800000
incq %rsi
cmpq %rsi, %r12
jne .LBB6_16
jmp .LBB6_17
.p2align 4, 0x90
.LBB6_18: # %_Z18create_flat_matrixiif.exit
# in Loop: Header=BB6_12 Depth=1
movq %rax, 112(%rsp) # 8-byte Spill
movq 240(%rsp), %rdi # 8-byte Reload
callq malloc
testl %r15d, %r15d
movq 8(%rsp), %rdi # 8-byte Reload
jle .LBB6_24
# %bb.19: # %.preheader.i100.preheader
# in Loop: Header=BB6_12 Depth=1
xorl %r8d, %r8d
xorl %ecx, %ecx
jmp .LBB6_20
.p2align 4, 0x90
.LBB6_23: # %._crit_edge.i102
# in Loop: Header=BB6_20 Depth=2
incq %rcx
addl %edi, %r8d
cmpq %r12, %rcx
je .LBB6_24
.LBB6_20: # %.preheader.i100
# Parent Loop BB6_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_22 Depth 3
testl %edi, %edi
jle .LBB6_23
# %bb.21: # %.lr.ph.i105
# in Loop: Header=BB6_20 Depth=2
movl %r8d, %edx
leaq (%rax,%rdx,4), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_22: # Parent Loop BB6_12 Depth=1
# Parent Loop BB6_20 Depth=2
# => This Inner Loop Header: Depth=3
movl $1073741824, (%rdx,%rsi,4) # imm = 0x40000000
incq %rsi
cmpq %rsi, %rbp
jne .LBB6_22
jmp .LBB6_23
.p2align 4, 0x90
.LBB6_24: # %_Z18create_flat_matrixiif.exit110
# in Loop: Header=BB6_12 Depth=1
movq %rax, 104(%rsp) # 8-byte Spill
movq 96(%rsp), %rdi # 8-byte Reload
callq malloc
movq 8(%rsp), %rcx # 8-byte Reload
movq %rax, 32(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB6_29
# %bb.25: # %.preheader.i113.preheader
# in Loop: Header=BB6_12 Depth=1
movq 40(%rsp), %rbx # 8-byte Reload
xorl %r13d, %r13d
jmp .LBB6_26
.p2align 4, 0x90
.LBB6_28: # %._crit_edge.i115
# in Loop: Header=BB6_26 Depth=2
addq 296(%rsp), %r13 # 8-byte Folded Reload
decq %rbx
je .LBB6_29
.LBB6_26: # %.preheader.i113
# Parent Loop BB6_12 Depth=1
# => This Inner Loop Header: Depth=2
testl %ecx, %ecx
jle .LBB6_28
# %bb.27: # %.lr.ph.i118
# in Loop: Header=BB6_26 Depth=2
movq %r13, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq 32(%rsp), %rdi # 8-byte Folded Reload
xorl %esi, %esi
movq 288(%rsp), %rdx # 8-byte Reload
callq memset@PLT
movq 8(%rsp), %rcx # 8-byte Reload
jmp .LBB6_28
.p2align 4, 0x90
.LBB6_29: # %_Z18create_flat_matrixiif.exit123
# in Loop: Header=BB6_12 Depth=1
leaq 64(%rsp), %rdi
movq 248(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq 240(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 64(%rsp), %rdi
movq 112(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
cmpb $0, 232(%rsp) # 1-byte Folded Reload
je .LBB6_32
# %bb.30: # in Loop: Header=BB6_12 Depth=1
movq 264(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $85899345940, %rdx # imm = 0x1400000014
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_35
# %bb.31: # in Loop: Header=BB6_12 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl %r14d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r15d, 16(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 212(%rsp)
movl %r14d, 208(%rsp)
movl %eax, 204(%rsp)
leaq 192(%rsp), %rax
movq %rax, 304(%rsp)
leaq 184(%rsp), %rax
movq %rax, 312(%rsp)
leaq 176(%rsp), %rax
movq %rax, 320(%rsp)
leaq 24(%rsp), %rax
movq %rax, 328(%rsp)
leaq 20(%rsp), %rax
movq %rax, 336(%rsp)
leaq 16(%rsp), %rax
movq %rax, 344(%rsp)
leaq 212(%rsp), %rax
movq %rax, 352(%rsp)
leaq 208(%rsp), %rax
movq %rax, 360(%rsp)
leaq 204(%rsp), %rax
movq %rax, 368(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
movl $_Z14matrixMultiplyPfS_S_iiiiii, %edi
jmp .LBB6_34
.p2align 4, 0x90
.LBB6_32: # in Loop: Header=BB6_12 Depth=1
movq 224(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 256(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_35
# %bb.33: # in Loop: Header=BB6_12 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 192(%rsp)
movl %r14d, 24(%rsp)
movl %r15d, 20(%rsp)
movq %rcx, 184(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 16(%rsp)
movq %rdx, 176(%rsp)
leaq 192(%rsp), %rax
movq %rax, 304(%rsp)
leaq 24(%rsp), %rax
movq %rax, 312(%rsp)
leaq 20(%rsp), %rax
movq %rax, 320(%rsp)
leaq 184(%rsp), %rax
movq %rax, 328(%rsp)
leaq 16(%rsp), %rax
movq %rax, 336(%rsp)
leaq 176(%rsp), %rax
movq %rax, 344(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
movl $_Z13mmul_d_threadPfiiS_iS_, %edi
.LBB6_34: # in Loop: Header=BB6_12 Depth=1
leaq 304(%rsp), %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_35: # in Loop: Header=BB6_12 Depth=1
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq 96(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
cmpb $0, 28(%rsp) # 1-byte Folded Reload
je .LBB6_54
# %bb.36: # in Loop: Header=BB6_12 Depth=1
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 88(%rsp) # 4-byte Folded Reload
movq 120(%rsp), %r14 # 8-byte Reload
jle .LBB6_42
# %bb.37: # %.preheader.i131.preheader
# in Loop: Header=BB6_12 Depth=1
xorl %ebx, %ebx
xorl %r13d, %r13d
jmp .LBB6_38
.p2align 4, 0x90
.LBB6_41: # %._crit_edge.i132
# in Loop: Header=BB6_38 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r13
movq 120(%rsp), %r14 # 8-byte Reload
addl %r14d, %ebx
cmpq 40(%rsp), %r13 # 8-byte Folded Reload
je .LBB6_42
.LBB6_38: # %.preheader.i131
# Parent Loop BB6_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_40 Depth 3
testl %r14d, %r14d
jle .LBB6_41
# %bb.39: # %.lr.ph.i133
# in Loop: Header=BB6_38 Depth=2
movl %ebx, %eax
movq 112(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_40: # Parent Loop BB6_12 Depth=1
# Parent Loop BB6_38 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB6_40
jmp .LBB6_41
.p2align 4, 0x90
.LBB6_42: # %_Z17print_flat_matrixPfii.exit
# in Loop: Header=BB6_12 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
testl %r14d, %r14d
movq 8(%rsp), %rax # 8-byte Reload
jle .LBB6_48
# %bb.43: # %.preheader.i140.preheader
# in Loop: Header=BB6_12 Depth=1
xorl %ebx, %ebx
xorl %r13d, %r13d
jmp .LBB6_44
.p2align 4, 0x90
.LBB6_47: # %._crit_edge.i142
# in Loop: Header=BB6_44 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r13
movq 8(%rsp), %rax # 8-byte Reload
addl %eax, %ebx
cmpq %r12, %r13
je .LBB6_48
.LBB6_44: # %.preheader.i140
# Parent Loop BB6_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_46 Depth 3
testl %eax, %eax
jle .LBB6_47
# %bb.45: # %.lr.ph.i146
# in Loop: Header=BB6_44 Depth=2
movl %ebx, %eax
movq 104(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_46: # Parent Loop BB6_12 Depth=1
# Parent Loop BB6_44 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %rbp
jne .LBB6_46
jmp .LBB6_47
.p2align 4, 0x90
.LBB6_48: # %_Z17print_flat_matrixPfii.exit151
# in Loop: Header=BB6_12 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rax # 8-byte Reload
cmpl $0, 88(%rsp) # 4-byte Folded Reload
jle .LBB6_54
# %bb.49: # %.preheader.i154.preheader
# in Loop: Header=BB6_12 Depth=1
xorl %ebx, %ebx
xorl %r13d, %r13d
jmp .LBB6_50
.p2align 4, 0x90
.LBB6_53: # %._crit_edge.i156
# in Loop: Header=BB6_50 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r13
movq 8(%rsp), %rax # 8-byte Reload
addl %eax, %ebx
cmpq 40(%rsp), %r13 # 8-byte Folded Reload
je .LBB6_54
.LBB6_50: # %.preheader.i154
# Parent Loop BB6_12 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_52 Depth 3
testl %eax, %eax
jle .LBB6_53
# %bb.51: # %.lr.ph.i160
# in Loop: Header=BB6_50 Depth=2
movl %ebx, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_52: # Parent Loop BB6_12 Depth=1
# Parent Loop BB6_50 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %rbp
jne .LBB6_52
jmp .LBB6_53
.LBB6_10:
xorps %xmm0, %xmm0
.LBB6_55: # %._crit_edge
movq 72(%rsp), %r9 # 8-byte Reload
xorps %xmm1, %xmm1
cvtsi2sd %r9d, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.6, %edi
movl %r14d, %esi
movl %r15d, %edx
movq 8(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq 216(%rsp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
# kill: def $r9d killed $r9d killed $r9
movb $1, %al
callq printf
xorl %eax, %eax
.LBB6_56:
addq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mmul_dPfiiS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13mmul_d_threadPfiiS_iS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPfS_S_iiiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type _Z6mmul_dPfiiS_iS_,@object # @_Z6mmul_dPfiiS_iS_
.section .rodata,"a",@progbits
.globl _Z6mmul_dPfiiS_iS_
.p2align 3, 0x0
_Z6mmul_dPfiiS_iS_:
.quad _Z21__device_stub__mmul_dPfiiS_iS_
.size _Z6mmul_dPfiiS_iS_, 8
.type _Z13mmul_d_threadPfiiS_iS_,@object # @_Z13mmul_d_threadPfiiS_iS_
.globl _Z13mmul_d_threadPfiiS_iS_
.p2align 3, 0x0
_Z13mmul_d_threadPfiiS_iS_:
.quad _Z28__device_stub__mmul_d_threadPfiiS_iS_
.size _Z13mmul_d_threadPfiiS_iS_, 8
.type _Z14matrixMultiplyPfS_S_iiiiii,@object # @_Z14matrixMultiplyPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 3, 0x0
_Z14matrixMultiplyPfS_S_iiiiii:
.quad _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.size _Z14matrixMultiplyPfS_S_iiiiii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%d\t%d\t%d\t%d\t%d\t%.6f\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6mmul_dPfiiS_iS_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13mmul_d_threadPfiiS_iS_"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14matrixMultiplyPfS_S_iiiiii"
.size .L__unnamed_3, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "first:"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "second:"
.size .Lstr.1, 8
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "multiply:"
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "insufficient args. for A x B = C, required args: [row num A] [col num A/row num B] [col num B] [cuda block size] [reps] [optimized] [compare]"
.size .Lstr.3, 142
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mmul_dPfiiS_iS_
.addrsig_sym _Z28__device_stub__mmul_d_threadPfiiS_iS_
.addrsig_sym _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mmul_dPfiiS_iS_
.addrsig_sym _Z13mmul_d_threadPfiiS_iS_
.addrsig_sym _Z14matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <cmath>
#include <chrono>
using namespace std::chrono;
#define CSC(call) \
do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while(0)
float normaAvg[32];
float avg[32][3];
void CustomFormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * avg[curClass][0];
rgb[1] = curPixel.y * avg[curClass][1];
rgb[2] = curPixel.z * avg[curClass][2];
denominator = normaPix * normaAvg[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
int CustomArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
void CustomSpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
uchar4 curPixel;
float res[32];
for (int x = 0; x < width; ++x)
{
for (int y = 0; y < height; ++y)
{
curPixel = pixels[y * width + x];
CustomFormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = CustomArgMax(res, numClasses);
}
}
}
__constant__ float constAVG[32][3];
__constant__ float constNormaAVG[32];
__device__ void FormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * constAVG[curClass][0];
rgb[1] = curPixel.y * constAVG[curClass][1];
rgb[2] = curPixel.z * constAVG[curClass][2];
denominator = normaPix * constNormaAVG[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
__device__ int ArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
__global__ void SpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int xOffset = blockDim.x * gridDim.x;
int yOffset = blockDim.y * gridDim.y;
uchar4 curPixel;
float res[32];
for (int x = idx; x < width; x += xOffset)
{
for (int y = idy; y < height; y += yOffset)
{
curPixel = pixels[y * width + x];
FormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = ArgMax(res, numClasses);
}
}
}
int main(int argc, const char* argv[])
{
std::string input, output;
int width, height, numClasses, numPixels;
uchar4* pixels;
std::cin >> input >> output >> numClasses;
int2 coordinate;
std::vector<std::vector<int2>> samples(numClasses);
for (int i = 0; i < numClasses; ++i)
{
std::cin >> numPixels;
for (int j = 0; j < numPixels; ++j)
{
std::cin >> coordinate.x >> coordinate.y;
samples[i].emplace_back(coordinate);
}
}
FILE* file;
if ((file = fopen(input.c_str(), "rb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file!\n";
exit(0);
}
else
{
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
if (width * height > 400000000)
{
std::cerr << "ERROR: incorrect input.\n";
exit(0);
}
pixels = new uchar4[width * height];
fread(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
int numChannels = 3; // rgb
int maxElems = 32;
for (int i = 0; i < numClasses; ++i)
{
avg[i][0] = 0.0;
avg[i][1] = 0.0;
avg[i][2] = 0.0;
numPixels = samples[i].size();
for (int j = 0; j < numPixels; ++j)
{
coordinate.x = samples[i][j].x;
coordinate.y = samples[i][j].y;
avg[i][0] += pixels[coordinate.y * width + coordinate.x].x;
avg[i][1] += pixels[coordinate.y * width + coordinate.x].y;
avg[i][2] += pixels[coordinate.y * width + coordinate.x].z;
}
avg[i][0] /= numPixels;
avg[i][1] /= numPixels;
avg[i][2] /= numPixels;
}
for (int i = 0; i < numClasses; ++i)
{
normaAvg[i] = std::sqrt(avg[i][0] * avg[i][0] + avg[i][1] * avg[i][1] + avg[i][2] * avg[i][2]);
}
CSC(cudaMemcpyToSymbol(constAVG, avg, sizeof(float) * maxElems * numChannels));
CSC(cudaMemcpyToSymbol(constNormaAVG, normaAvg, sizeof(float) * maxElems));
uchar4* deviceRes;
CSC(cudaMalloc(&deviceRes, sizeof(uchar4) * width * height));
CSC(cudaMemcpy(deviceRes, pixels, sizeof(uchar4) * width * height, cudaMemcpyHostToDevice));
auto startt = steady_clock::now();
//custom
CustomSpectralAngleMethod(pixels, width, height, numClasses);
auto endd = steady_clock::now();
std::cout << "CPU" << std::endl;
std::cout << "time = " << ((double)duration_cast<microseconds>(endd - startt).count()) / 1000.0 << std::endl;
int xThreadCount = 32;
int yThreadCount = 32;
int xBlockCount = 32;
int yBlockCount = 32;
dim3 blockCount = dim3(xBlockCount, yBlockCount);
dim3 threadsCount = dim3(xThreadCount, yThreadCount);
cudaEvent_t start, end;
CSC(cudaEventCreate(&start));
CSC(cudaEventCreate(&end));
CSC(cudaEventRecord(start));
SpectralAngleMethod<<<blockCount, threadsCount>>>(deviceRes, width, height, numClasses);
CSC(cudaGetLastError());
CSC(cudaEventRecord(end));
CSC(cudaEventSynchronize(end));
float t;
CSC(cudaEventElapsedTime(&t, start, end));
CSC(cudaEventDestroy(start));
CSC(cudaEventDestroy(end));
printf("GPU\n");
printf("time = %f\n", t);
printf("blocks = (%d, %d)\n", xBlockCount, yBlockCount);
printf("threads = (%d, %d)\n", xThreadCount, yThreadCount);
CSC(cudaMemcpy(pixels, deviceRes, sizeof(uchar4) * width * height, cudaMemcpyDeviceToHost));
if ((file = fopen(output.c_str(), "wb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file.";
exit(0);
}
else
{
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
CSC(cudaFree(deviceRes));
delete[] pixels;
return 0;
}
|
.file "tmpxft_00096aaa_00000000-6_time3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4142:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4142:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24CustomFormulaComputationPfi6uchar4
.type _Z24CustomFormulaComputationPfi6uchar4, @function
_Z24CustomFormulaComputationPfi6uchar4:
.LFB4131:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movl %esi, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movzbl %dl, %r13d
movzbl %dh, %eax
movl %eax, %r12d
shrl $16, %edx
movzbl %dl, %ebp
movl %r13d, %eax
imull %r13d, %eax
movl %r12d, %edx
imull %r12d, %edx
addl %edx, %eax
movl %ebp, %edx
imull %ebp, %edx
addl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L14
sqrtss %xmm0, %xmm0
.L6:
testl %r14d, %r14d
jle .L3
leaq avg(%rip), %rcx
movslq %r14d, %rsi
salq $2, %rsi
movl $0, %edx
leaq normaAvg(%rip), %rdi
pxor %xmm8, %xmm8
cvtsi2ssl %r13d, %xmm8
pxor %xmm7, %xmm7
cvtsi2ssl %r12d, %xmm7
pxor %xmm6, %xmm6
cvtsi2ssl %ebp, %xmm6
leaq 24(%rsp), %r8
jmp .L9
.L14:
call sqrtf@PLT
jmp .L6
.L16:
movss %xmm2, (%rbx,%rdx)
addq $12, %rcx
addq $4, %rdx
cmpq %rsi, %rdx
je .L3
.L9:
movaps %xmm0, %xmm1
mulss (%rdi,%rdx), %xmm1
movaps %xmm8, %xmm5
mulss (%rcx), %xmm5
divss %xmm1, %xmm5
movaps %xmm7, %xmm4
mulss 4(%rcx), %xmm4
divss %xmm1, %xmm4
movaps %xmm6, %xmm3
mulss 8(%rcx), %xmm3
divss %xmm1, %xmm3
movl $0x00000000, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0x00000000, 20(%rsp)
leaq 12(%rsp), %rax
pxor %xmm2, %xmm2
.L8:
movaps %xmm5, %xmm1
addss (%rax), %xmm1
addss %xmm4, %xmm1
addss %xmm3, %xmm1
movss %xmm1, (%rax)
addss %xmm1, %xmm2
addq $4, %rax
cmpq %rax, %r8
jne .L8
jmp .L16
.L3:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4131:
.size _Z24CustomFormulaComputationPfi6uchar4, .-_Z24CustomFormulaComputationPfi6uchar4
.globl _Z12CustomArgMaxPfi
.type _Z12CustomArgMaxPfi, @function
_Z12CustomArgMaxPfi:
.LFB4132:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
testl %esi, %esi
jle .L23
movslq %esi, %rsi
movl $0, %eax
movl $0, %edx
.L22:
movss (%rdi,%rax,4), %xmm1
comiss %xmm0, %xmm1
cmova %eax, %edx
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $1, %rax
cmpq %rsi, %rax
jne .L22
.L18:
movl %edx, %eax
ret
.L23:
movl $0, %edx
jmp .L18
.cfi_endproc
.LFE4132:
.size _Z12CustomArgMaxPfi, .-_Z12CustomArgMaxPfi
.globl _Z25CustomSpectralAngleMethodP6uchar4iii
.type _Z25CustomSpectralAngleMethodP6uchar4iii, @function
_Z25CustomSpectralAngleMethodP6uchar4iii:
.LFB4133:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 16(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
testl %esi, %esi
jle .L26
movl %edx, %r14d
movl %ecx, %r12d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq 0(,%rax,4), %r15
movq $0, 8(%rsp)
leaq 32(%rsp), %r13
jmp .L28
.L29:
movl (%rbx), %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z24CustomFormulaComputationPfi6uchar4
movl %r12d, %esi
movq %r13, %rdi
call _Z12CustomArgMaxPfi
movb %al, 3(%rbx)
addl $1, %ebp
addq %r15, %rbx
cmpl %ebp, %r14d
jne .L29
.L31:
addq $1, 8(%rsp)
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
cmpq %rcx, %rax
je .L26
.L28:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
leaq (%rax,%rcx,4), %rbx
movl $0, %ebp
testl %r14d, %r14d
jg .L29
jmp .L31
.L26:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4133:
.size _Z25CustomSpectralAngleMethodP6uchar4iii, .-_Z25CustomSpectralAngleMethodP6uchar4iii
.globl _Z18FormulaComputationPfi6uchar4
.type _Z18FormulaComputationPfi6uchar4, @function
_Z18FormulaComputationPfi6uchar4:
.LFB4134:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4134:
.size _Z18FormulaComputationPfi6uchar4, .-_Z18FormulaComputationPfi6uchar4
.globl _Z6ArgMaxPfi
.type _Z6ArgMaxPfi, @function
_Z6ArgMaxPfi:
.LFB4135:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4135:
.size _Z6ArgMaxPfi, .-_Z6ArgMaxPfi
.globl _Z48__device_stub__Z19SpectralAngleMethodP6uchar4iiiP6uchar4iii
.type _Z48__device_stub__Z19SpectralAngleMethodP6uchar4iiiP6uchar4iii, @function
_Z48__device_stub__Z19SpectralAngleMethodP6uchar4iiiP6uchar4iii:
.LFB4164:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19SpectralAngleMethodP6uchar4iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4164:
.size _Z48__device_stub__Z19SpectralAngleMethodP6uchar4iiiP6uchar4iii, .-_Z48__device_stub__Z19SpectralAngleMethodP6uchar4iiiP6uchar4iii
.globl _Z19SpectralAngleMethodP6uchar4iii
.type _Z19SpectralAngleMethodP6uchar4iii, @function
_Z19SpectralAngleMethodP6uchar4iii:
.LFB4165:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z19SpectralAngleMethodP6uchar4iiiP6uchar4iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4165:
.size _Z19SpectralAngleMethodP6uchar4iii, .-_Z19SpectralAngleMethodP6uchar4iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z19SpectralAngleMethodP6uchar4iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "constAVG"
.LC3:
.string "constNormaAVG"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4167:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19SpectralAngleMethodP6uchar4iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $384, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8constAVG(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $128, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13constNormaAVG(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev
.type _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev, @function
_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev:
.LFB4508:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq 8(%rdi), %rbp
movq (%rdi), %rbx
cmpq %rbx, %rbp
jne .L54
.L52:
movq (%r12), %rdi
testq %rdi, %rdi
je .L51
movq 16(%r12), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L51:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
addq $24, %rbx
cmpq %rbx, %rbp
je .L52
.L54:
movq (%rbx), %rdi
testq %rdi, %rdi
je .L53
movq 16(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
jmp .L53
.cfi_endproc
.LFE4508:
.size _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev, .-_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev
.weak _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev
.set _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev,_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev
.section .rodata._ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_.str1.1,"aMS",@progbits,1
.LC4:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,"axG",@progbits,_ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.type _ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_, @function
_ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_:
.LFB4699:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L75
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L61
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L62
jmp .L69
.L75:
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L76:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L64
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L68
.L61:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L69:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L62:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L76
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L66
.L64:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L66:
addq %rbp, %r15
testq %r13, %r13
je .L67
movq 16(%rbx), %rsi
subq %r13, %rsi
.L68:
movq %r13, %rdi
call _ZdlPvm@PLT
.L67:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4699:
.size _ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_, .-_ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.section .rodata.str1.8
.align 8
.LC5:
.string "cannot create std::vector larger than max_size()"
.section .rodata.str1.1
.LC6:
.string "rb"
.section .rodata.str1.8
.align 8
.LC7:
.string "ERROR: something wrong with opening the file!\n"
.section .rodata.str1.1
.LC8:
.string "ERROR: incorrect input.\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/lveltman/PGP/master/lab3/time3.cu"
.section .rodata.str1.1
.LC10:
.string "ERROR in %s:%d. Message: %s\n"
.LC11:
.string "CPU"
.LC12:
.string "time = "
.LC14:
.string "GPU\n"
.LC15:
.string "time = %f\n"
.LC16:
.string "blocks = (%d, %d)\n"
.LC17:
.string "threads = (%d, %d)\n"
.LC18:
.string "wb"
.section .rodata.str1.8
.align 8
.LC19:
.string "ERROR: something wrong with opening the file."
.text
.globl main
.type main, @function
main:
.LFB4136:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4136
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 112(%rsp), %rsi
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq $0, 120(%rsp)
movb $0, 128(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $0, 152(%rsp)
movb $0, 160(%rsp)
leaq _ZSt3cin(%rip), %rdi
.LEHB0:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
movq %rax, %rdi
leaq 144(%rsp), %rsi
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
movq %rax, %rdi
leaq 12(%rsp), %rsi
call _ZNSirsERi@PLT
movslq 12(%rsp), %rax
movabsq $384307168202282325, %rdx
cmpq %rax, %rdx
jb .L131
movq $0, 88(%rsp)
movq $0, 96(%rsp)
testq %rax, %rax
je .L80
imulq $24, %rax, %rbx
movq %rbx, %rdi
call _Znwm@PLT
jmp .L132
.L131:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L133
leaq .LC5(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE0:
.L120:
endbr64
movq %rax, %rbx
jmp .L116
.L133:
call __stack_chk_fail@PLT
.L132:
movq %rax, %r13
movq %rax, 80(%rsp)
leaq (%rax,%rbx), %rdx
movq %rdx, 96(%rsp)
.L81:
movq $0, (%rax)
movq $0, 8(%rax)
movq $0, 16(%rax)
addq $24, %rax
cmpq %rdx, %rax
jne .L81
.L118:
movq %rdx, 88(%rsp)
cmpl $0, 12(%rsp)
jle .L82
movq %r13, %r15
movl $0, %r14d
leaq _ZSt3cin(%rip), %r12
jmp .L87
.L135:
cmpl $0, 16(%rsp)
jle .L83
movq %r15, %rbx
movl $0, %ebp
jmp .L86
.L134:
movq %rax, %rdi
leaq 28(%rsp), %rsi
.LEHB1:
call _ZNSirsERi@PLT
movq 8(%rbx), %rsi
cmpq 16(%rbx), %rsi
je .L84
movq 24(%rsp), %rax
movq %rax, (%rsi)
addq $8, 8(%rbx)
.L85:
addl $1, %ebp
cmpl %ebp, 16(%rsp)
jle .L83
.L86:
leaq 24(%rsp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L134
.L84:
leaq 24(%rsp), %rdx
movq %rbx, %rdi
call _ZNSt6vectorI4int2SaIS0_EE17_M_realloc_insertIJRS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
jmp .L85
.L83:
addl $1, %r14d
addq $24, %r15
cmpl %r14d, 12(%rsp)
jle .L82
.L87:
leaq 16(%rsp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L135
.L82:
leaq .LC6(%rip), %rsi
movq 112(%rsp), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L136
leaq 4(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
jmp .L137
.L136:
leaq .LC7(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call exit@PLT
.L137:
leaq 8(%rsp), %rdi
movq %r12, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 4(%rsp), %eax
imull 8(%rsp), %eax
cmpl $400000000, %eax
jg .L138
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L90
leaq 0(,%rax,4), %rbp
movq %rbp, %rdi
call _Znam@PLT
jmp .L139
.L138:
leaq .LC8(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call exit@PLT
.L139:
movq %rax, %rbx
movl 4(%rsp), %ecx
imull 8(%rsp), %ecx
movslq %ecx, %rcx
movq %r12, %r8
movl $4, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
jmp .L140
.L90:
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L92
call __stack_chk_fail@PLT
.L92:
call __cxa_throw_bad_array_new_length@PLT
.L121:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev
.L116:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L117
call __stack_chk_fail@PLT
.L140:
movq %r12, %rdi
call fclose@PLT
movl 12(%rsp), %ebp
testl %ebp, %ebp
jle .L93
movl 4(%rsp), %r8d
leaq avg(%rip), %r10
movslq %ebp, %rbp
imulq $12, %rbp, %r11
addq %r10, %r11
movq %r10, %r9
.L96:
movq %r9, %rdx
movl $0x00000000, (%r9)
movl $0x00000000, 4(%r9)
movl $0x00000000, 8(%r9)
movq 0(%r13), %rax
movq 8(%r13), %rdi
subq %rax, %rdi
sarq $3, %rdi
movl %edi, 16(%rsp)
testl %edi, %edi
jle .L94
movq %rax, %rcx
leal -1(%rdi), %esi
leaq 8(%rax,%rsi,8), %rsi
.L95:
movl (%rcx), %r12d
movl %r12d, 24(%rsp)
movl 4(%rcx), %eax
movl %eax, 28(%rsp)
imull %r8d, %eax
addl %r12d, %eax
cltq
leaq (%rbx,%rax,4), %rax
movzbl (%rax), %r12d
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
movzbl 1(%rax), %r12d
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
addss 4(%rdx), %xmm0
movss %xmm0, 4(%rdx)
movzbl 2(%rax), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss 8(%rdx), %xmm0
movss %xmm0, 8(%rdx)
addq $8, %rcx
cmpq %rsi, %rcx
jne .L95
.L94:
pxor %xmm1, %xmm1
cvtsi2ssl %edi, %xmm1
movss (%rdx), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rdx)
movss 4(%rdx), %xmm0
divss %xmm1, %xmm0
movss %xmm0, 4(%rdx)
movss 8(%rdx), %xmm0
divss %xmm1, %xmm0
movss %xmm0, 8(%rdx)
addq $12, %r9
addq $24, %r13
cmpq %r11, %r9
jne .L96
leaq normaAvg(%rip), %rax
leaq (%rax,%rbp,4), %rdx
.L97:
movss (%r10), %xmm0
movss 4(%r10), %xmm2
movss 8(%r10), %xmm1
mulss %xmm0, %xmm0
mulss %xmm2, %xmm2
addss %xmm2, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $12, %r10
addq $4, %rax
cmpq %rdx, %rax
jne .L97
.L93:
movl $1, %r8d
movl $0, %ecx
movl $384, %edx
leaq avg(%rip), %rsi
leaq _ZL8constAVG(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L98
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $247, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L98:
movl $1, %r8d
movl $0, %ecx
movl $128, %edx
leaq normaAvg(%rip), %rsi
leaq _ZL13constNormaAVG(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L99
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $248, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L99:
movslq 4(%rsp), %rsi
movslq 8(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L100
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $251, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L100:
movslq 4(%rsp), %rdx
movslq 8(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
je .L101
call cudaGetErrorString@PLT
movq %rax, %r9
movl $252, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L101:
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r12
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 4(%rsp), %esi
movq %rbx, %rdi
call _Z25CustomSpectralAngleMethodP6uchar4iii
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbp
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rax
subq %r12, %rax
movl $1000, %ecx
cqto
idivq %rcx
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC13(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
je .L102
call cudaGetErrorString@PLT
movq %rax, %r9
movl $277, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L102:
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
je .L103
call cudaGetErrorString@PLT
movq %rax, %r9
movl $278, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L103:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
je .L104
call cudaGetErrorString@PLT
movq %rax, %r9
movl $279, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L104:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L105
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 4(%rsp), %esi
movq 32(%rsp), %rdi
call _Z48__device_stub__Z19SpectralAngleMethodP6uchar4iiiP6uchar4iii
.L105:
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L106
call cudaGetErrorString@PLT
movq %rax, %r9
movl $284, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L106:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
je .L107
call cudaGetErrorString@PLT
movq %rax, %r9
movl $288, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L107:
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
je .L108
call cudaGetErrorString@PLT
movq %rax, %r9
movl $289, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L108:
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
je .L109
call cudaGetErrorString@PLT
movq %rax, %r9
movl $291, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L109:
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
je .L110
call cudaGetErrorString@PLT
movq %rax, %r9
movl $292, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L110:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
testl %eax, %eax
je .L111
call cudaGetErrorString@PLT
movq %rax, %r9
movl $293, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L111:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $32, %ecx
movl $32, %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %ecx
movl $32, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 4(%rsp), %rdx
movslq 8(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
je .L112
call cudaGetErrorString@PLT
movq %rax, %r9
movl $301, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L112:
leaq .LC18(%rip), %rsi
movq 144(%rsp), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L141
leaq 4(%rsp), %rdi
movq %rax, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
jmp .L142
.L141:
leaq .LC19(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call exit@PLT
.L142:
leaq 8(%rsp), %rdi
movq %rbp, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
movl 4(%rsp), %edx
imull 8(%rsp), %edx
movslq %edx, %rdx
movq %rbp, %rcx
movl $4, %esi
movq %rbx, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L143
movq %rbx, %rdi
call _ZdaPv@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L144
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L143:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %r9
movl $318, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE1:
movl $0, %edi
call exit@PLT
.L117:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L80:
movq $0, 80(%rsp)
movq $0, 96(%rsp)
movl $0, %r13d
movl $0, %edx
jmp .L118
.L144:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4136:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4136:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4136-.LLSDACSB4136
.LLSDACSB4136:
.uleb128 .LEHB0-.LFB4136
.uleb128 .LEHE0-.LEHB0
.uleb128 .L120-.LFB4136
.uleb128 0
.uleb128 .LEHB1-.LFB4136
.uleb128 .LEHE1-.LEHB1
.uleb128 .L121-.LFB4136
.uleb128 0
.uleb128 .LEHB2-.LFB4136
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4136:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL13constNormaAVG
.comm _ZL13constNormaAVG,128,32
.local _ZL8constAVG
.comm _ZL8constAVG,384,32
.globl avg
.bss
.align 32
.type avg, @object
.size avg, 384
avg:
.zero 384
.globl normaAvg
.align 32
.type normaAvg, @object
.size normaAvg, 128
normaAvg:
.zero 128
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC13:
.long 0
.long 1083129856
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <cmath>
#include <chrono>
using namespace std::chrono;
#define CSC(call) \
do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while(0)
float normaAvg[32];
float avg[32][3];
void CustomFormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * avg[curClass][0];
rgb[1] = curPixel.y * avg[curClass][1];
rgb[2] = curPixel.z * avg[curClass][2];
denominator = normaPix * normaAvg[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
int CustomArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
void CustomSpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
uchar4 curPixel;
float res[32];
for (int x = 0; x < width; ++x)
{
for (int y = 0; y < height; ++y)
{
curPixel = pixels[y * width + x];
CustomFormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = CustomArgMax(res, numClasses);
}
}
}
__constant__ float constAVG[32][3];
__constant__ float constNormaAVG[32];
__device__ void FormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * constAVG[curClass][0];
rgb[1] = curPixel.y * constAVG[curClass][1];
rgb[2] = curPixel.z * constAVG[curClass][2];
denominator = normaPix * constNormaAVG[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
__device__ int ArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
__global__ void SpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int xOffset = blockDim.x * gridDim.x;
int yOffset = blockDim.y * gridDim.y;
uchar4 curPixel;
float res[32];
for (int x = idx; x < width; x += xOffset)
{
for (int y = idy; y < height; y += yOffset)
{
curPixel = pixels[y * width + x];
FormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = ArgMax(res, numClasses);
}
}
}
int main(int argc, const char* argv[])
{
std::string input, output;
int width, height, numClasses, numPixels;
uchar4* pixels;
std::cin >> input >> output >> numClasses;
int2 coordinate;
std::vector<std::vector<int2>> samples(numClasses);
for (int i = 0; i < numClasses; ++i)
{
std::cin >> numPixels;
for (int j = 0; j < numPixels; ++j)
{
std::cin >> coordinate.x >> coordinate.y;
samples[i].emplace_back(coordinate);
}
}
FILE* file;
if ((file = fopen(input.c_str(), "rb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file!\n";
exit(0);
}
else
{
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
if (width * height > 400000000)
{
std::cerr << "ERROR: incorrect input.\n";
exit(0);
}
pixels = new uchar4[width * height];
fread(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
int numChannels = 3; // rgb
int maxElems = 32;
for (int i = 0; i < numClasses; ++i)
{
avg[i][0] = 0.0;
avg[i][1] = 0.0;
avg[i][2] = 0.0;
numPixels = samples[i].size();
for (int j = 0; j < numPixels; ++j)
{
coordinate.x = samples[i][j].x;
coordinate.y = samples[i][j].y;
avg[i][0] += pixels[coordinate.y * width + coordinate.x].x;
avg[i][1] += pixels[coordinate.y * width + coordinate.x].y;
avg[i][2] += pixels[coordinate.y * width + coordinate.x].z;
}
avg[i][0] /= numPixels;
avg[i][1] /= numPixels;
avg[i][2] /= numPixels;
}
for (int i = 0; i < numClasses; ++i)
{
normaAvg[i] = std::sqrt(avg[i][0] * avg[i][0] + avg[i][1] * avg[i][1] + avg[i][2] * avg[i][2]);
}
CSC(cudaMemcpyToSymbol(constAVG, avg, sizeof(float) * maxElems * numChannels));
CSC(cudaMemcpyToSymbol(constNormaAVG, normaAvg, sizeof(float) * maxElems));
uchar4* deviceRes;
CSC(cudaMalloc(&deviceRes, sizeof(uchar4) * width * height));
CSC(cudaMemcpy(deviceRes, pixels, sizeof(uchar4) * width * height, cudaMemcpyHostToDevice));
auto startt = steady_clock::now();
//custom
CustomSpectralAngleMethod(pixels, width, height, numClasses);
auto endd = steady_clock::now();
std::cout << "CPU" << std::endl;
std::cout << "time = " << ((double)duration_cast<microseconds>(endd - startt).count()) / 1000.0 << std::endl;
int xThreadCount = 32;
int yThreadCount = 32;
int xBlockCount = 32;
int yBlockCount = 32;
dim3 blockCount = dim3(xBlockCount, yBlockCount);
dim3 threadsCount = dim3(xThreadCount, yThreadCount);
cudaEvent_t start, end;
CSC(cudaEventCreate(&start));
CSC(cudaEventCreate(&end));
CSC(cudaEventRecord(start));
SpectralAngleMethod<<<blockCount, threadsCount>>>(deviceRes, width, height, numClasses);
CSC(cudaGetLastError());
CSC(cudaEventRecord(end));
CSC(cudaEventSynchronize(end));
float t;
CSC(cudaEventElapsedTime(&t, start, end));
CSC(cudaEventDestroy(start));
CSC(cudaEventDestroy(end));
printf("GPU\n");
printf("time = %f\n", t);
printf("blocks = (%d, %d)\n", xBlockCount, yBlockCount);
printf("threads = (%d, %d)\n", xThreadCount, yThreadCount);
CSC(cudaMemcpy(pixels, deviceRes, sizeof(uchar4) * width * height, cudaMemcpyDeviceToHost));
if ((file = fopen(output.c_str(), "wb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file.";
exit(0);
}
else
{
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
CSC(cudaFree(deviceRes));
delete[] pixels;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <cmath>
#include <chrono>
using namespace std::chrono;
#define CSC(call) \
do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while(0)
float normaAvg[32];
float avg[32][3];
void CustomFormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * avg[curClass][0];
rgb[1] = curPixel.y * avg[curClass][1];
rgb[2] = curPixel.z * avg[curClass][2];
denominator = normaPix * normaAvg[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
int CustomArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
void CustomSpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
uchar4 curPixel;
float res[32];
for (int x = 0; x < width; ++x)
{
for (int y = 0; y < height; ++y)
{
curPixel = pixels[y * width + x];
CustomFormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = CustomArgMax(res, numClasses);
}
}
}
__constant__ float constAVG[32][3];
__constant__ float constNormaAVG[32];
__device__ void FormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * constAVG[curClass][0];
rgb[1] = curPixel.y * constAVG[curClass][1];
rgb[2] = curPixel.z * constAVG[curClass][2];
denominator = normaPix * constNormaAVG[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
__device__ int ArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
__global__ void SpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int xOffset = blockDim.x * gridDim.x;
int yOffset = blockDim.y * gridDim.y;
uchar4 curPixel;
float res[32];
for (int x = idx; x < width; x += xOffset)
{
for (int y = idy; y < height; y += yOffset)
{
curPixel = pixels[y * width + x];
FormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = ArgMax(res, numClasses);
}
}
}
int main(int argc, const char* argv[])
{
std::string input, output;
int width, height, numClasses, numPixels;
uchar4* pixels;
std::cin >> input >> output >> numClasses;
int2 coordinate;
std::vector<std::vector<int2>> samples(numClasses);
for (int i = 0; i < numClasses; ++i)
{
std::cin >> numPixels;
for (int j = 0; j < numPixels; ++j)
{
std::cin >> coordinate.x >> coordinate.y;
samples[i].emplace_back(coordinate);
}
}
FILE* file;
if ((file = fopen(input.c_str(), "rb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file!\n";
exit(0);
}
else
{
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
if (width * height > 400000000)
{
std::cerr << "ERROR: incorrect input.\n";
exit(0);
}
pixels = new uchar4[width * height];
fread(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
int numChannels = 3; // rgb
int maxElems = 32;
for (int i = 0; i < numClasses; ++i)
{
avg[i][0] = 0.0;
avg[i][1] = 0.0;
avg[i][2] = 0.0;
numPixels = samples[i].size();
for (int j = 0; j < numPixels; ++j)
{
coordinate.x = samples[i][j].x;
coordinate.y = samples[i][j].y;
avg[i][0] += pixels[coordinate.y * width + coordinate.x].x;
avg[i][1] += pixels[coordinate.y * width + coordinate.x].y;
avg[i][2] += pixels[coordinate.y * width + coordinate.x].z;
}
avg[i][0] /= numPixels;
avg[i][1] /= numPixels;
avg[i][2] /= numPixels;
}
for (int i = 0; i < numClasses; ++i)
{
normaAvg[i] = std::sqrt(avg[i][0] * avg[i][0] + avg[i][1] * avg[i][1] + avg[i][2] * avg[i][2]);
}
CSC(hipMemcpyToSymbol(HIP_SYMBOL(constAVG), avg, sizeof(float) * maxElems * numChannels));
CSC(hipMemcpyToSymbol(HIP_SYMBOL(constNormaAVG), normaAvg, sizeof(float) * maxElems));
uchar4* deviceRes;
CSC(hipMalloc(&deviceRes, sizeof(uchar4) * width * height));
CSC(hipMemcpy(deviceRes, pixels, sizeof(uchar4) * width * height, hipMemcpyHostToDevice));
auto startt = steady_clock::now();
//custom
CustomSpectralAngleMethod(pixels, width, height, numClasses);
auto endd = steady_clock::now();
std::cout << "CPU" << std::endl;
std::cout << "time = " << ((double)duration_cast<microseconds>(endd - startt).count()) / 1000.0 << std::endl;
int xThreadCount = 32;
int yThreadCount = 32;
int xBlockCount = 32;
int yBlockCount = 32;
dim3 blockCount = dim3(xBlockCount, yBlockCount);
dim3 threadsCount = dim3(xThreadCount, yThreadCount);
hipEvent_t start, end;
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&end));
CSC(hipEventRecord(start));
SpectralAngleMethod<<<blockCount, threadsCount>>>(deviceRes, width, height, numClasses);
CSC(hipGetLastError());
CSC(hipEventRecord(end));
CSC(hipEventSynchronize(end));
float t;
CSC(hipEventElapsedTime(&t, start, end));
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(end));
printf("GPU\n");
printf("time = %f\n", t);
printf("blocks = (%d, %d)\n", xBlockCount, yBlockCount);
printf("threads = (%d, %d)\n", xThreadCount, yThreadCount);
CSC(hipMemcpy(pixels, deviceRes, sizeof(uchar4) * width * height, hipMemcpyDeviceToHost));
if ((file = fopen(output.c_str(), "wb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file.";
exit(0);
}
else
{
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
CSC(hipFree(deviceRes));
delete[] pixels;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <cmath>
#include <chrono>
using namespace std::chrono;
#define CSC(call) \
do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while(0)
float normaAvg[32];
float avg[32][3];
void CustomFormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * avg[curClass][0];
rgb[1] = curPixel.y * avg[curClass][1];
rgb[2] = curPixel.z * avg[curClass][2];
denominator = normaPix * normaAvg[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
int CustomArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
void CustomSpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
uchar4 curPixel;
float res[32];
for (int x = 0; x < width; ++x)
{
for (int y = 0; y < height; ++y)
{
curPixel = pixels[y * width + x];
CustomFormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = CustomArgMax(res, numClasses);
}
}
}
__constant__ float constAVG[32][3];
__constant__ float constNormaAVG[32];
__device__ void FormulaComputation(float* res, int numClasses, uchar4 curPixel)
{
float rgb[3];
float tmp[3];
float sum, denominator;
float normaPix = sqrt((float)(curPixel.x * curPixel.x + curPixel.y * curPixel.y + curPixel.z * curPixel.z));
for (int curClass = 0; curClass < numClasses; ++curClass)
{
rgb[0] = curPixel.x * constAVG[curClass][0];
rgb[1] = curPixel.y * constAVG[curClass][1];
rgb[2] = curPixel.z * constAVG[curClass][2];
denominator = normaPix * constNormaAVG[curClass];
rgb[0] /= denominator;
rgb[1] /= denominator;
rgb[2] /= denominator;
sum = 0.0;
for (int i = 0; i < 3; ++i) tmp[i] = 0.0;
for (int i = 0; i < 3; ++i)
{
tmp[i] += rgb[0];
tmp[i] += rgb[1];
tmp[i] += rgb[2];
sum += tmp[i];
}
res[curClass] = sum;
}
}
__device__ int ArgMax(float* arr, int numClasses)
{
float maxValue = arr[0];
int maxPoint = 0;
for (int i = 0; i < numClasses; ++i)
{
if (arr[i] > maxValue)
{
maxValue = arr[i];
maxPoint = i;
}
}
return maxPoint;
}
__global__ void SpectralAngleMethod(uchar4* pixels, int width, int height, int numClasses)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int xOffset = blockDim.x * gridDim.x;
int yOffset = blockDim.y * gridDim.y;
uchar4 curPixel;
float res[32];
for (int x = idx; x < width; x += xOffset)
{
for (int y = idy; y < height; y += yOffset)
{
curPixel = pixels[y * width + x];
FormulaComputation(res, numClasses, curPixel);
pixels[y * width + x].w = ArgMax(res, numClasses);
}
}
}
int main(int argc, const char* argv[])
{
std::string input, output;
int width, height, numClasses, numPixels;
uchar4* pixels;
std::cin >> input >> output >> numClasses;
int2 coordinate;
std::vector<std::vector<int2>> samples(numClasses);
for (int i = 0; i < numClasses; ++i)
{
std::cin >> numPixels;
for (int j = 0; j < numPixels; ++j)
{
std::cin >> coordinate.x >> coordinate.y;
samples[i].emplace_back(coordinate);
}
}
FILE* file;
if ((file = fopen(input.c_str(), "rb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file!\n";
exit(0);
}
else
{
fread(&width, sizeof(int), 1, file);
fread(&height, sizeof(int), 1, file);
if (width * height > 400000000)
{
std::cerr << "ERROR: incorrect input.\n";
exit(0);
}
pixels = new uchar4[width * height];
fread(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
int numChannels = 3; // rgb
int maxElems = 32;
for (int i = 0; i < numClasses; ++i)
{
avg[i][0] = 0.0;
avg[i][1] = 0.0;
avg[i][2] = 0.0;
numPixels = samples[i].size();
for (int j = 0; j < numPixels; ++j)
{
coordinate.x = samples[i][j].x;
coordinate.y = samples[i][j].y;
avg[i][0] += pixels[coordinate.y * width + coordinate.x].x;
avg[i][1] += pixels[coordinate.y * width + coordinate.x].y;
avg[i][2] += pixels[coordinate.y * width + coordinate.x].z;
}
avg[i][0] /= numPixels;
avg[i][1] /= numPixels;
avg[i][2] /= numPixels;
}
for (int i = 0; i < numClasses; ++i)
{
normaAvg[i] = std::sqrt(avg[i][0] * avg[i][0] + avg[i][1] * avg[i][1] + avg[i][2] * avg[i][2]);
}
CSC(hipMemcpyToSymbol(HIP_SYMBOL(constAVG), avg, sizeof(float) * maxElems * numChannels));
CSC(hipMemcpyToSymbol(HIP_SYMBOL(constNormaAVG), normaAvg, sizeof(float) * maxElems));
uchar4* deviceRes;
CSC(hipMalloc(&deviceRes, sizeof(uchar4) * width * height));
CSC(hipMemcpy(deviceRes, pixels, sizeof(uchar4) * width * height, hipMemcpyHostToDevice));
auto startt = steady_clock::now();
//custom
CustomSpectralAngleMethod(pixels, width, height, numClasses);
auto endd = steady_clock::now();
std::cout << "CPU" << std::endl;
std::cout << "time = " << ((double)duration_cast<microseconds>(endd - startt).count()) / 1000.0 << std::endl;
int xThreadCount = 32;
int yThreadCount = 32;
int xBlockCount = 32;
int yBlockCount = 32;
dim3 blockCount = dim3(xBlockCount, yBlockCount);
dim3 threadsCount = dim3(xThreadCount, yThreadCount);
hipEvent_t start, end;
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&end));
CSC(hipEventRecord(start));
SpectralAngleMethod<<<blockCount, threadsCount>>>(deviceRes, width, height, numClasses);
CSC(hipGetLastError());
CSC(hipEventRecord(end));
CSC(hipEventSynchronize(end));
float t;
CSC(hipEventElapsedTime(&t, start, end));
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(end));
printf("GPU\n");
printf("time = %f\n", t);
printf("blocks = (%d, %d)\n", xBlockCount, yBlockCount);
printf("threads = (%d, %d)\n", xThreadCount, yThreadCount);
CSC(hipMemcpy(pixels, deviceRes, sizeof(uchar4) * width * height, hipMemcpyDeviceToHost));
if ((file = fopen(output.c_str(), "wb")) == NULL)
{
std::cerr << "ERROR: something wrong with opening the file.";
exit(0);
}
else
{
fwrite(&width, sizeof(int), 1, file);
fwrite(&height, sizeof(int), 1, file);
fwrite(pixels, sizeof(uchar4), width * height, file);
fclose(file);
}
CSC(hipFree(deviceRes));
delete[] pixels;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii
.globl _Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii
.p2align 8
.type _Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii,@function
_Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s12, s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[3:4], null, s14, s8, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v3
s_cbranch_execz .LBB0_17
s_clause 0x1
s_load_b32 s9, s[2:3], 0xc
s_load_b64 s[2:3], s[2:3], 0x0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0xc
s_load_b64 s[6:7], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s16, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s1, s9, 16
s_mul_i32 s13, s2, s8
v_mad_u64_u32 v[4:5], null, s15, s1, v[0:1]
s_cmp_gt_i32 s5, 0
s_mul_i32 s15, s3, s1
s_cselect_b32 s14, -1, 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s4, v4
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v3, s13, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v3
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_17
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v7, v4
s_mov_b32 s18, 0
s_branch .LBB0_7
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
v_add_nc_u32_e32 v7, s15, v7
global_store_b8 v[5:6], v0, off offset:3
v_cmp_le_i32_e32 vcc_lo, s4, v7
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_2
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v7, s12, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v5, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
global_load_b32 v0, v[5:6], off
s_mov_b32 s8, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 0xff, v0
v_perm_b32 v2, v0, v0, 0xc0c0201
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, v1, v1
v_dot4_u32_u8 v1, v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v2
v_add_nc_u32_e32 v9, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v8, v2, v1
v_fma_f32 v11, -v9, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s1, 0, v10
v_cndmask_b32_e64 v2, v2, v8, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s1, 0, v11
v_cvt_f32_ubyte2_e32 v11, v0
v_cndmask_b32_e64 v2, v2, v9, s1
v_cvt_f32_ubyte1_e32 v9, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
v_cvt_f32_ubyte0_e32 v8, v0
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v10, v2, v1, vcc_lo
.LBB0_9:
s_mul_i32 s1, s8, 12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, constAVG@rel32@lo+4
s_addc_u32 s3, s3, constAVG@rel32@hi+12
s_mul_hi_u32 s19, s8, 12
s_add_u32 s2, s1, s2
s_addc_u32 s3, s19, s3
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, constAVG@rel32@lo+8
s_addc_u32 s11, s11, constAVG@rel32@hi+16
s_add_u32 s10, s1, s10
s_addc_u32 s11, s19, s11
s_getpc_b64 s[20:21]
s_add_u32 s20, s20, constAVG@rel32@lo+12
s_addc_u32 s21, s21, constAVG@rel32@hi+20
s_add_u32 s20, s1, s20
s_addc_u32 s21, s19, s21
s_getpc_b64 s[22:23]
s_add_u32 s22, s22, constNormaAVG@rel32@lo+4
s_addc_u32 s23, s23, constNormaAVG@rel32@hi+12
s_lshl_b64 s[24:25], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s22, s24, s22
s_addc_u32 s23, s25, s23
s_clause 0x2
s_load_b32 s1, s[2:3], 0x0
s_load_b32 s11, s[10:11], 0x0
s_load_b32 s10, s[20:21], 0x0
s_load_b32 s19, s[22:23], 0x0
s_mov_b64 s[2:3], 0
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 2
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s2, 1
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s2, 0
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 3
s_cbranch_scc1 .LBB0_10
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v12, s19, v10 :: v_dual_mul_f32 v13, s11, v9
v_dual_mul_f32 v14, s1, v8 :: v_dual_mul_f32 v15, s10, v11
s_mov_b64 s[10:11], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v16, null, v12, v12, v13
v_div_scale_f32 v17, null, v12, v12, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v18, null, v12, v12, v15
v_rcp_f32_e32 v19, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v20, v17
v_div_scale_f32 v22, vcc_lo, v13, v12, v13
v_rcp_f32_e32 v21, v18
v_div_scale_f32 v23, s1, v14, v12, v14
v_div_scale_f32 v27, s2, v15, v12, v15
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f32 v24, -v16, v19, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v25, -v17, v20, 1.0
v_fma_f32 v26, -v18, v21, 1.0
v_dual_fmac_f32 v19, v24, v19 :: v_dual_fmac_f32 v20, v25, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v24, v22, v19 :: v_dual_mul_f32 v25, v23, v20
v_fma_f32 v28, -v16, v24, v22
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v21, v26, v21
v_fma_f32 v29, -v17, v25, v23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v24, v28, v19
v_dual_mul_f32 v26, v27, v21 :: v_dual_fmac_f32 v25, v29, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v16, v24, v22
v_fma_f32 v30, -v18, v26, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v17, -v17, v25, v23
v_div_fmas_f32 v16, v16, v19, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v26, v30, v21
s_mov_b32 vcc_lo, s1
v_div_fmas_f32 v17, v17, v20, v25
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v18, -v18, v26, v27
v_div_fixup_f32 v13, v16, v12, v13
v_div_fixup_f32 v14, v17, v12, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v18, v18, v21, v26
v_div_fixup_f32 v15, v18, v12, v15
v_mov_b32_e32 v12, 0
.p2align 6
.LBB0_12:
s_cmp_eq_u32 s10, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s10, 2
v_cndmask_b32_e32 v16, v0, v1, vcc_lo
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s10, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v16, v16, v2, s1
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s10, 3
v_add_f32_e32 v16, v14, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v16, v13, v16
v_add_f32_e32 v16, v15, v16
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, v16, s1
v_cndmask_b32_e32 v1, v1, v16, vcc_lo
v_cndmask_b32_e64 v0, v0, v16, s2
v_add_f32_e32 v12, v12, v16
s_cbranch_scc0 .LBB0_12
s_lshl_b32 s1, s8, 2
s_add_i32 s8, s8, 1
s_add_i32 s1, s1, 16
s_cmp_eq_u32 s8, s5
scratch_store_b32 off, v12, s1
s_cbranch_scc0 .LBB0_9
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
scratch_load_b32 v1, off, off offset:16
v_mov_b32_e32 v2, 16
v_mov_b32_e32 v0, 0
s_mov_b32 s1, 0
.LBB0_16:
scratch_load_b32 v8, v2, off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v8, v1
v_dual_cndmask_b32 v1, v1, v8 :: v_dual_add_nc_u32 v2, 4, v2
v_cndmask_b32_e64 v0, v0, s1, vcc_lo
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s5, s1
s_cbranch_scc1 .LBB0_16
s_branch .LBB0_6
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 144
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii, .Lfunc_end0-_Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected constAVG
.type constAVG,@object
.section .bss,"aw",@nobits
.globl constAVG
.p2align 4, 0x0
constAVG:
.zero 384
.size constAVG, 384
.protected constNormaAVG
.type constNormaAVG,@object
.globl constNormaAVG
.p2align 4, 0x0
constNormaAVG:
.zero 128
.size constNormaAVG, 128
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym constAVG
.addrsig_sym constNormaAVG
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii
.private_segment_fixed_size: 144
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z19SpectralAngleMethodP15HIP_vector_typeIhLj4EEiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <iomanip>
#include <stdio.h>
#include <chrono>
#include <random> // For kernel generation
#include <algorithm>
#include <list>
using namespace std;
#pragma region Cuda
const int WARP_SIZE = 32;
// Crude benchmarks suggest 256 is better than 512 and 1024
// TODO: Autotune/use better heuristics, improve speed more.
const int MAX_BLOCK_SIZE = 256;
const int CUDA_NUM_THREADS = 1024;
int GET_BLOCKS(const int N) {
return (N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS;
}
static int getGradParamsNumThreads(int batchSize){
//warp per item in a batch, up to a maximum
return std::min(batchSize * WARP_SIZE, MAX_BLOCK_SIZE);
}
__global__ void ConvolutionRowwise(const float *input, float *rowwiseResults, int batch_ix,
int channel_ix,
int input_dim,
int result_dim )
{
float* res1 = rowwiseResults + (blockIdx.x * result_dim);
float* res2 = res1 + (input_dim * result_dim);
float* res3 = res2 + (input_dim * result_dim);
input = input + (blockIdx.x * input_dim);
float l1 = input[0],
l2 = input[1],
l3 = input[2];
for (int i = 3; i < input_dim; ++i)
{
*res1 = (l1 + l2 + l3);
++res1;
*res2 = (l1 - l2 + l3);
++res2;
*res3 = (l1 + l2 - l3);
++res3;
l1 = l2;
l2 = l3;
l3 = input[i];
}
*res1 = (l1 + l2 + l3);
*res2 = (l1 - l2 + l3);
*res3 = (l1 + l2 - l3);
}
__global__ void ConvolutionColwise(const float *rowwiseResults, float *colwiseResults, int inputDim, int resultDim)
{
// blockDim
// Z tells us which rowwiseResults matrix to work on {0,1,2}
// X tells us the rowwiseResults matrix top-row
// Y tells us the rowwiseResults matrix col
int topCell = (blockIdx.z *inputDim*resultDim) + (blockIdx.x * resultDim) + blockIdx.y;
float l1 = rowwiseResults[topCell];
float l2 = rowwiseResults[topCell + resultDim];
float l3 = rowwiseResults[topCell + resultDim + resultDim];
topCell = (blockIdx.z * resultDim * resultDim * 3) + (blockIdx.x * resultDim) + blockIdx.y;
colwiseResults[topCell] = l1 + l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 - l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 + l2 - l3;
}
#pragma endregion
#pragma region Misc
std::default_random_engine randomGeneratorEngine;
std::uniform_real_distribution<float> randomGenerator;
float *CreateArray(int size)
{
int i;
float *arr;
cudaMallocManaged(&arr, size);
for (i = 0; i < size; ++i)
{
arr[i] = i + 1;
cout << arr[i] << " ";
//arr[i] = (int)(randomGenerator(randomGeneratorEngine) * 10);
}
cout << endl;
return arr;
}
void PrintMat(float *mat, int rows, int cols)
{
for (int i = 0; i < rows; ++i)
{
cout << "[";
for (int j = 0; j < cols - 1; ++j)
{
cout << mat[i*cols + j] << " ";
}
cout << mat[i*cols + (cols - 1)] << "]";
if (i < rows - 1)
cout << endl;
}
cout << endl;
}
template <typename Function>
void zip(const vector<int> &batchSizes, const vector<int> &inputChannels, const vector<int> &outputChannels, const vector<int> &inputDims,
Function function)
{
for (int batchSize : batchSizes)
for (int inputChannel : inputChannels)
for (int outputChannel : outputChannels)
for (int inputDim : inputDims)
function(batchSize, inputChannel, outputChannel, inputDim);
}
#pragma endregion
int main()
{
const vector<int> batchSizes = { 1 };
const vector<int> inputChannels = { 1 };
const vector<int> outputChannels = { 1 };
const vector<int> inputDims = { 10 }; // 16, 32, 64, 128, 256, 512, 650, 1024, 1280, 1500
std::cout << std::setfill('0') << std::setw(5) << std::fixed << std::setprecision(1);
zip(batchSizes, inputChannels, outputChannels, inputDims,
[](int batchIndex, int inputChannel, int outputChannel, int inputDim) {
float *rowwiseResults;
int resultDim = inputDim - 2;
int rowwiseResultsSize = 3 * inputDim * resultDim;
cudaMallocManaged(&rowwiseResults, rowwiseResultsSize);
float *arr = CreateArray(inputDim * inputDim);
dim3 grid(inputDim);
ConvolutionRowwise <<< grid, 1 >>> (arr, rowwiseResults, batchIndex, inputChannel, inputDim, resultDim);
cudaDeviceSynchronize();
PrintMat(rowwiseResults, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + inputDim * resultDim, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + (2 * (inputDim * resultDim)), inputDim, resultDim); cout << endl;
float *colResults;
cudaMallocManaged <float>(&colResults, 9 * resultDim * resultDim);
grid = dim3(resultDim, resultDim, 3);
ConvolutionColwise <<< grid, 1 >>> (rowwiseResults, colResults, inputDim, resultDim);
cudaDeviceSynchronize();
for (int i = 0; i < 9; i++)
{
PrintMat(colResults + (i*resultDim*resultDim), inputDim, resultDim); cout << endl;
}
});
//for (auto& [a, b] : zip(batchSizes, inputChannels)) {
return 0;
}
|
code for sm_80
Function : _Z18ConvolutionColwisePKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.Z ; /* 0x0000000000087919 */
/* 0x000e220000002700 */
/*0020*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0050*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R8, c[0x0][0x170], R9 ; /* 0x00005c0008007a24 */
/* 0x001fc800078e0209 */
/*0070*/ IMAD R0, R0, c[0x0][0x174], R13 ; /* 0x00005d0000007a24 */
/* 0x002fc800078e020d */
/*0080*/ IMAD.WIDE R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e020f */
/*0090*/ IMAD.WIDE R4, R15.reuse, c[0x0][0x174], R2 ; /* 0x00005d000f047a25 */
/* 0x040fe400078e0202 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R15, c[0x0][0x174], R4 ; /* 0x00005d000f067a25 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ LEA R0, R8, R8, 0x1 ; /* 0x0000000808007211 */
/* 0x000fe400078e08ff */
/*00f0*/ MOV R10, c[0x0][0x174] ; /* 0x00005d00000a7a02 */
/* 0x000fc60000000f00 */
/*0100*/ IMAD R0, R0, c[0x0][0x174], R9 ; /* 0x00005d0000007a24 */
/* 0x000fc800078e0209 */
/*0110*/ IMAD R0, R0, c[0x0][0x174], R13 ; /* 0x00005d0000007a24 */
/* 0x000fc800078e020d */
/*0120*/ IMAD.WIDE R8, R0, R15, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fc800078e020f */
/*0130*/ IMAD R15, R10, c[0x0][0x174], RZ ; /* 0x00005d000a0f7a24 */
/* 0x000fe400078e02ff */
/*0140*/ FADD R13, R2.reuse, R11.reuse ; /* 0x0000000b020d7221 */
/* 0x144fe40000000000 */
/*0150*/ FADD R11, R2, -R11 ; /* 0x8000000b020b7221 */
/* 0x000fe40000000000 */
/*0160*/ IMAD.WIDE R2, R15, 0x4, R8 ; /* 0x000000040f027825 */
/* 0x000fc800078e0208 */
/*0170*/ FADD R7, R6.reuse, R13 ; /* 0x0000000d06077221 */
/* 0x048fe40000000000 */
/*0180*/ FADD R11, R6.reuse, R11 ; /* 0x0000000b060b7221 */
/* 0x040fe40000000000 */
/*0190*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x000fe20000000100 */
/*01a0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x000fe2000c101904 */
/*01b0*/ IMAD.WIDE R4, R15, 0x4, R2 ; /* 0x000000040f047825 */
/* 0x000fc600078e0202 */
/*01c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18ConvolutionRowwisePKfPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD R14, R4, c[0x0][0x178], RZ ; /* 0x00005e00040e7a24 */
/* 0x001fc800078e02ff */
/*0050*/ IMAD.WIDE.U32 R8, R14, R5, c[0x0][0x160] ; /* 0x000058000e087625 */
/* 0x000fca00078e0005 */
/*0060*/ LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b7981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R0, [R8.64+0x8] ; /* 0x0000080408007981 */
/* 0x000ee2000c1e1900 */
/*0090*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD R4, R4, c[0x0][0x17c], RZ ; /* 0x00005f0004047a24 */
/* 0x000fc600078e02ff */
/*00b0*/ ISETP.GE.AND P0, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0005 */
/*00d0*/ IMAD R21, R10, c[0x0][0x17c], RZ ; /* 0x00005f000a157a24 */
/* 0x000fc800078e02ff */
/*00e0*/ IMAD.WIDE R2, R21, 0x4, R4 ; /* 0x0000000415027825 */
/* 0x000fcc00078e0204 */
/*00f0*/ IMAD.WIDE R6, R21, 0x4, R2 ; /* 0x0000000415067825 */
/* 0x000fc800078e0202 */
/*0100*/ FADD R13, R11, R12 ; /* 0x0000000c0b0d7221 */
/* 0x004fc80000000000 */
/*0110*/ FADD R15, R13, R0 ; /* 0x000000000d0f7221 */
/* 0x008fca0000000000 */
/*0120*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e2000c101904 */
/*0130*/ @!P0 BRA 0x7c0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R8, R10.reuse, -0x4, RZ ; /* 0xfffffffc0a087810 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3 ; /* 0x00000003ff0f7424 */
/* 0x001fe200078e00ff */
/*0160*/ IADD3 R10, R10, -0x3, RZ ; /* 0xfffffffd0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f06070 */
/*0180*/ LOP3.LUT R10, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a0a7812 */
/* 0x000fd600078ec0ff */
/*0190*/ @!P0 BRA 0x5c0 ; /* 0x0000042000008947 */
/* 0x000fea0003800000 */
/*01a0*/ LEA R8, P0, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e087a11 */
/* 0x000fe200078010ff */
/*01b0*/ HFMA2.MMA R15, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff0f7435 */
/* 0x000fe200000001ff */
/*01c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R21 ; /* 0x0000001fff027819 */
/* 0x000fe40000011415 */
/*01d0*/ IADD3 R8, P1, R8, 0x18, RZ ; /* 0x0000001808087810 */
/* 0x000fe40007f3e0ff */
/*01e0*/ LEA.HI.X R27, R14, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x000059000e1b7a11 */
/* 0x000fe400000f14ff */
/*01f0*/ SHF.L.U32 R23, R21.reuse, 0x2, RZ ; /* 0x0000000215177819 */
/* 0x040fe400000006ff */
/*0200*/ SHF.L.U64.HI R19, R21.reuse, 0x2, R2.reuse ; /* 0x0000000215137819 */
/* 0x140fe20000010202 */
/*0210*/ IMAD.X R27, RZ, RZ, R27, P1 ; /* 0x000000ffff1b7224 */
/* 0x000fe200008e061b */
/*0220*/ SHF.L.U64.HI R17, R21.reuse, 0x3, R2 ; /* 0x0000000315117819 */
/* 0x040fe20000010202 */
/*0230*/ IMAD.SHL.U32 R21, R21, 0x8, RZ ; /* 0x0000000815157824 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R16, -R10, c[0x0][0x178], RZ ; /* 0x00005e000a107a10 */
/* 0x000fc40007ffe1ff */
/*0250*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x004fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fc400078e0005 */
/*0270*/ FADD R7, R12, -R11 ; /* 0x8000000b0c077221 */
/* 0x000fe20000000000 */
/*0280*/ IADD3 R4, P0, R2, R23, RZ ; /* 0x0000001702047210 */
/* 0x000fe20007f1e0ff */
/*0290*/ FADD R25, -R0, R13 ; /* 0x0000000d00197221 */
/* 0x000fe20000000100 */
/*02a0*/ IADD3 R6, P1, R2, R21, RZ ; /* 0x0000001502067210 */
/* 0x000fe20007f3e0ff */
/*02b0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x000fe20000000000 */
/*02c0*/ IADD3.X R5, R3, R19, RZ, P0, !PT ; /* 0x0000001303057210 */
/* 0x000fc600007fe4ff */
/*02d0*/ IMAD.X R7, R3, 0x1, R17, P1 ; /* 0x0000000103077824 */
/* 0x000fe400008e0611 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c101904 */
/*02f0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e2000c101904 */
/*0300*/ MOV R9, R27 ; /* 0x0000001b00097202 */
/* 0x001fca0000000f00 */
/*0310*/ LDG.E R13, [R8.64+-0xc] ; /* 0xfffff404080d7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ FADD R12, R0.reuse, R11.reuse ; /* 0x0000000b000c7221 */
/* 0x140fe40000000000 */
/*0330*/ FADD R18, -R0, R11 ; /* 0x0000000b00127221 */
/* 0x000fe40000000100 */
/*0340*/ FADD R11, R12.reuse, R13.reuse ; /* 0x0000000d0c0b7221 */
/* 0x144fe40000000000 */
/*0350*/ FADD R27, R13.reuse, R18 ; /* 0x000000120d1b7221 */
/* 0x040fe40000000000 */
/*0360*/ FADD R29, R12, -R13 ; /* 0x8000000d0c1d7221 */
/* 0x000fe20000000000 */
/*0370*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0001e8000c101904 */
/*0380*/ STG.E [R4.64+0x4], R27 ; /* 0x0000041b04007986 */
/* 0x0005e8000c101904 */
/*0390*/ STG.E [R6.64+0x4], R29 ; /* 0x0000041d06007986 */
/* 0x0007e8000c101904 */
/*03a0*/ LDG.E R12, [R8.64+-0x8] ; /* 0xfffff804080c7981 */
/* 0x000f22000c1e1900 */
/*03b0*/ FADD R25, R13, R0 ; /* 0x000000000d197221 */
/* 0x002fc40000000000 */
/*03c0*/ FADD R18, -R13, R0 ; /* 0x000000000d127221 */
/* 0x000fe40000000100 */
/*03d0*/ FADD R0, R25.reuse, R12 ; /* 0x0000000c19007221 */
/* 0x050fe40000000000 */
/*03e0*/ FADD R18, R12, R18 ; /* 0x000000120c127221 */
/* 0x000fe40000000000 */
/*03f0*/ FADD R25, R25, -R12.reuse ; /* 0x8000000c19197221 */
/* 0x100fe20000000000 */
/*0400*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x0003e8000c101904 */
/*0410*/ STG.E [R4.64+0x8], R18 ; /* 0x0000081204007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R6.64+0x8], R25 ; /* 0x0000081906007986 */
/* 0x000fe8000c101904 */
/*0430*/ LDG.E R11, [R8.64+-0x4] ; /* 0xfffffc04080b7981 */
/* 0x001ea2000c1e1900 */
/*0440*/ FADD R20, R13, R12 ; /* 0x0000000c0d147221 */
/* 0x000fc40000000000 */
/*0450*/ FADD R22, R13, -R12 ; /* 0x8000000c0d167221 */
/* 0x000fe40000000000 */
/*0460*/ FADD R27, R20.reuse, R11.reuse ; /* 0x0000000b141b7221 */
/* 0x144fe40000000000 */
/*0470*/ FADD R29, R11, R22 ; /* 0x000000160b1d7221 */
/* 0x008fe40000000000 */
/*0480*/ FADD R20, R20, -R11.reuse ; /* 0x8000000b14147221 */
/* 0x100fe20000000000 */
/*0490*/ STG.E [R2.64+0xc], R27 ; /* 0x00000c1b02007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R4.64+0xc], R29 ; /* 0x00000c1d04007986 */
/* 0x0001e8000c101904 */
/*04b0*/ STG.E [R6.64+0xc], R20 ; /* 0x00000c1406007986 */
/* 0x0005e8000c101904 */
/*04c0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0022e2000c1e1900 */
/*04d0*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ FADD R13, R12, R11 ; /* 0x0000000b0c0d7221 */
/* 0x000fe20000000000 */
/*04f0*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fc40007ffe0ff */
/*0500*/ ISETP.NE.AND P0, PT, R16, 0x3, PT ; /* 0x000000031000780c */
/* 0x000fe40003f05270 */
/*0510*/ IADD3 R4, P1, R2, 0x10, RZ ; /* 0x0000001002047810 */
/* 0x001fe40007f3e0ff */
/*0520*/ IADD3 R8, P2, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x002fc60007f5e0ff */
/*0530*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0540*/ IADD3.X R27, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff1b7210 */
/* 0x000fe200017fe4ff */
/*0550*/ FADD R25, R13, R0 ; /* 0x000000000d197221 */
/* 0x008fca0000000000 */
/*0560*/ STG.E [R2.64+0x10], R25 ; /* 0x0000101902007986 */
/* 0x0005e2000c101904 */
/*0570*/ @P0 BRA 0x250 ; /* 0xfffffcd000000947 */
/* 0x000fea000383ffff */
/*0580*/ IADD3 R2, P0, R4.reuse, R23, RZ ; /* 0x0000001704027210 */
/* 0x044fe40007f1e0ff */
/*0590*/ IADD3 R6, P1, R4, R21, RZ ; /* 0x0000001504067210 */
/* 0x000fc60007f3e0ff */
/*05a0*/ IMAD.X R3, R5.reuse, 0x1, R19, P0 ; /* 0x0000000105037824 */
/* 0x040fe200000e0613 */
/*05b0*/ IADD3.X R7, R5, R17, RZ, P1, !PT ; /* 0x0000001105077210 */
/* 0x000fe40000ffe4ff */
/*05c0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*05d0*/ @!P0 BRA 0x7c0 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R14, P0, R14, R15, RZ ; /* 0x0000000f0e0e7210 */
/* 0x000fc80007f1e0ff */
/*05f0*/ LEA R8, P1, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e087a11 */
/* 0x000fe400078210ff */
/*0600*/ LEA.HI.X.SX32 R15, R15, RZ, 0x1, P0 ; /* 0x000000ff0f0f7211 */
/* 0x000fc800000f0eff */
/*0610*/ LEA.HI.X R17, R14, c[0x0][0x164], R15, 0x2, P1 ; /* 0x000059000e117a11 */
/* 0x000fe400008f140f */
/*0620*/ FADD R9, R12, -R11 ; /* 0x8000000b0c097221 */
/* 0x000fe40000000000 */
/*0630*/ FADD R19, -R0, R13 ; /* 0x0000000d00137221 */
/* 0x000fe40000000100 */
/*0640*/ FADD R9, R9, R0 ; /* 0x0000000009097221 */
/* 0x000fca0000000000 */
/*0650*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0660*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0003e2000c101904 */
/*0670*/ MOV R9, R17 ; /* 0x0000001100097202 */
/* 0x001fca0000000f00 */
/*0680*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x0000a2000c1e1900 */
/*0690*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ FADD R13, R0, R11.reuse ; /* 0x0000000b000d7221 */
/* 0x100fe20000000000 */
/*06b0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe20007f3e0ff */
/*06c0*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000b */
/*06d0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*06e0*/ IADD3 R11, P3, R4, 0x4, RZ ; /* 0x00000004040b7810 */
/* 0x000fe20007f7e0ff */
/*06f0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0700*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fe40007f5e0ff */
/*0710*/ IADD3 R8, P4, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x001fc40007f9e0ff */
/*0720*/ IADD3.X R9, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff097210 */
/* 0x000fe40001ffe4ff */
/*0730*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400017fe4ff */
/*0740*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200027fe4ff */
/*0750*/ FADD R15, R13, R14 ; /* 0x0000000e0d0f7221 */
/* 0x004fca0000000000 */
/*0760*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0001e4000c101904 */
/*0770*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x001fe20000000f00 */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0000 */
/*0790*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*07a0*/ MOV R0, R14 ; /* 0x0000000e00007202 */
/* 0x000fe20000000f00 */
/*07b0*/ @P0 BRA 0x620 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*07c0*/ FADD R5, R12, -R11 ; /* 0x8000000b0c057221 */
/* 0x001fe40000000000 */
/*07d0*/ FADD R13, -R0, R13 ; /* 0x0000000d000d7221 */
/* 0x000fe40000000100 */
/*07e0*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x000fca0000000000 */
/*07f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0800*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <iomanip>
#include <stdio.h>
#include <chrono>
#include <random> // For kernel generation
#include <algorithm>
#include <list>
using namespace std;
#pragma region Cuda
const int WARP_SIZE = 32;
// Crude benchmarks suggest 256 is better than 512 and 1024
// TODO: Autotune/use better heuristics, improve speed more.
const int MAX_BLOCK_SIZE = 256;
const int CUDA_NUM_THREADS = 1024;
int GET_BLOCKS(const int N) {
return (N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS;
}
static int getGradParamsNumThreads(int batchSize){
//warp per item in a batch, up to a maximum
return std::min(batchSize * WARP_SIZE, MAX_BLOCK_SIZE);
}
__global__ void ConvolutionRowwise(const float *input, float *rowwiseResults, int batch_ix,
int channel_ix,
int input_dim,
int result_dim )
{
float* res1 = rowwiseResults + (blockIdx.x * result_dim);
float* res2 = res1 + (input_dim * result_dim);
float* res3 = res2 + (input_dim * result_dim);
input = input + (blockIdx.x * input_dim);
float l1 = input[0],
l2 = input[1],
l3 = input[2];
for (int i = 3; i < input_dim; ++i)
{
*res1 = (l1 + l2 + l3);
++res1;
*res2 = (l1 - l2 + l3);
++res2;
*res3 = (l1 + l2 - l3);
++res3;
l1 = l2;
l2 = l3;
l3 = input[i];
}
*res1 = (l1 + l2 + l3);
*res2 = (l1 - l2 + l3);
*res3 = (l1 + l2 - l3);
}
__global__ void ConvolutionColwise(const float *rowwiseResults, float *colwiseResults, int inputDim, int resultDim)
{
// blockDim
// Z tells us which rowwiseResults matrix to work on {0,1,2}
// X tells us the rowwiseResults matrix top-row
// Y tells us the rowwiseResults matrix col
int topCell = (blockIdx.z *inputDim*resultDim) + (blockIdx.x * resultDim) + blockIdx.y;
float l1 = rowwiseResults[topCell];
float l2 = rowwiseResults[topCell + resultDim];
float l3 = rowwiseResults[topCell + resultDim + resultDim];
topCell = (blockIdx.z * resultDim * resultDim * 3) + (blockIdx.x * resultDim) + blockIdx.y;
colwiseResults[topCell] = l1 + l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 - l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 + l2 - l3;
}
#pragma endregion
#pragma region Misc
std::default_random_engine randomGeneratorEngine;
std::uniform_real_distribution<float> randomGenerator;
float *CreateArray(int size)
{
int i;
float *arr;
cudaMallocManaged(&arr, size);
for (i = 0; i < size; ++i)
{
arr[i] = i + 1;
cout << arr[i] << " ";
//arr[i] = (int)(randomGenerator(randomGeneratorEngine) * 10);
}
cout << endl;
return arr;
}
void PrintMat(float *mat, int rows, int cols)
{
for (int i = 0; i < rows; ++i)
{
cout << "[";
for (int j = 0; j < cols - 1; ++j)
{
cout << mat[i*cols + j] << " ";
}
cout << mat[i*cols + (cols - 1)] << "]";
if (i < rows - 1)
cout << endl;
}
cout << endl;
}
template <typename Function>
void zip(const vector<int> &batchSizes, const vector<int> &inputChannels, const vector<int> &outputChannels, const vector<int> &inputDims,
Function function)
{
for (int batchSize : batchSizes)
for (int inputChannel : inputChannels)
for (int outputChannel : outputChannels)
for (int inputDim : inputDims)
function(batchSize, inputChannel, outputChannel, inputDim);
}
#pragma endregion
int main()
{
const vector<int> batchSizes = { 1 };
const vector<int> inputChannels = { 1 };
const vector<int> outputChannels = { 1 };
const vector<int> inputDims = { 10 }; // 16, 32, 64, 128, 256, 512, 650, 1024, 1280, 1500
std::cout << std::setfill('0') << std::setw(5) << std::fixed << std::setprecision(1);
zip(batchSizes, inputChannels, outputChannels, inputDims,
[](int batchIndex, int inputChannel, int outputChannel, int inputDim) {
float *rowwiseResults;
int resultDim = inputDim - 2;
int rowwiseResultsSize = 3 * inputDim * resultDim;
cudaMallocManaged(&rowwiseResults, rowwiseResultsSize);
float *arr = CreateArray(inputDim * inputDim);
dim3 grid(inputDim);
ConvolutionRowwise <<< grid, 1 >>> (arr, rowwiseResults, batchIndex, inputChannel, inputDim, resultDim);
cudaDeviceSynchronize();
PrintMat(rowwiseResults, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + inputDim * resultDim, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + (2 * (inputDim * resultDim)), inputDim, resultDim); cout << endl;
float *colResults;
cudaMallocManaged <float>(&colResults, 9 * resultDim * resultDim);
grid = dim3(resultDim, resultDim, 3);
ConvolutionColwise <<< grid, 1 >>> (rowwiseResults, colResults, inputDim, resultDim);
cudaDeviceSynchronize();
for (int i = 0; i < 9; i++)
{
PrintMat(colResults + (i*resultDim*resultDim), inputDim, resultDim); cout << endl;
}
});
//for (auto& [a, b] : zip(batchSizes, inputChannels)) {
return 0;
}
|
.file "tmpxft_00173320_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5546:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5546:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10GET_BLOCKSi
.type _Z10GET_BLOCKSi, @function
_Z10GET_BLOCKSi:
.LFB5535:
.cfi_startproc
endbr64
leal 2046(%rdi), %eax
addl $1023, %edi
cmovns %edi, %eax
sarl $10, %eax
ret
.cfi_endproc
.LFE5535:
.size _Z10GET_BLOCKSi, .-_Z10GET_BLOCKSi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z11CreateArrayi
.type _Z11CreateArrayi, @function
_Z11CreateArrayi:
.LFB5537:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %edi, %rbp
movq %rsp, %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
testl %ebx, %ebx
jle .L5
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r12
.L6:
leal 1(%rbx), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq (%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
movq (%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L6
.L5:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L14
cmpb $0, 56(%rbx)
je .L9
movzbl 67(%rbx), %esi
.L10:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L15
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L16
call _ZSt16__throw_bad_castv@PLT
.L16:
call __stack_chk_fail@PLT
.L9:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5537:
.size _Z11CreateArrayi, .-_Z11CreateArrayi
.section .rodata.str1.1
.LC1:
.string "["
.LC2:
.string "]"
.text
.globl _Z8PrintMatPfii
.type _Z8PrintMatPfii, @function
_Z8PrintMatPfii:
.LFB5538:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
testl %esi, %esi
jle .L18
movl %edx, %r15d
movslq %edx, %rdx
salq $2, %rdx
leaq (%rdi,%rdx), %rax
movq %rax, (%rsp)
movl $0, 12(%rsp)
movl $0, %r14d
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
movq %rdx, 16(%rsp)
movq %rdi, 24(%rsp)
movl %esi, 8(%rsp)
jmp .L25
.L32:
call _ZSt16__throw_bad_castv@PLT
.L23:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L21:
addl $1, %r14d
movq 16(%rsp), %rcx
addq %rcx, (%rsp)
addl %r15d, 12(%rsp)
cmpl %r14d, 8(%rsp)
je .L18
.L25:
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
cmpl $1, %r15d
jle .L19
movslq 12(%rsp), %rdx
movq 24(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
leal -2(%r15), %eax
addq %rdx, %rax
leaq 4(%rcx,%rax,4), %r12
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
.L19:
movq (%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd -4(%rax), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rsp), %eax
subl $1, %eax
cmpl %r14d, %eax
jle .L21
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L32
cmpb $0, 56(%rbx)
je .L23
movzbl 67(%rbx), %esi
jmp .L24
.L18:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L33
cmpb $0, 56(%rbx)
je .L27
movzbl 67(%rbx), %eax
.L28:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L27:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L28
.cfi_endproc
.LFE5538:
.size _Z8PrintMatPfii, .-_Z8PrintMatPfii
.globl _Z45__device_stub__Z18ConvolutionRowwisePKfPfiiiiPKfPfiiii
.type _Z45__device_stub__Z18ConvolutionRowwisePKfPfiiiiPKfPfiiii, @function
_Z45__device_stub__Z18ConvolutionRowwisePKfPfiiiiPKfPfiiii:
.LFB5568:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18ConvolutionRowwisePKfPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5568:
.size _Z45__device_stub__Z18ConvolutionRowwisePKfPfiiiiPKfPfiiii, .-_Z45__device_stub__Z18ConvolutionRowwisePKfPfiiiiPKfPfiiii
.globl _Z18ConvolutionRowwisePKfPfiiii
.type _Z18ConvolutionRowwisePKfPfiiii, @function
_Z18ConvolutionRowwisePKfPfiiii:
.LFB5569:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18ConvolutionRowwisePKfPfiiiiPKfPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5569:
.size _Z18ConvolutionRowwisePKfPfiiii, .-_Z18ConvolutionRowwisePKfPfiiii
.globl _Z43__device_stub__Z18ConvolutionColwisePKfPfiiPKfPfii
.type _Z43__device_stub__Z18ConvolutionColwisePKfPfiiPKfPfii, @function
_Z43__device_stub__Z18ConvolutionColwisePKfPfiiPKfPfii:
.LFB5570:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18ConvolutionColwisePKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5570:
.size _Z43__device_stub__Z18ConvolutionColwisePKfPfiiPKfPfii, .-_Z43__device_stub__Z18ConvolutionColwisePKfPfiiPKfPfii
.globl _Z18ConvolutionColwisePKfPfii
.type _Z18ConvolutionColwisePKfPfii, @function
_Z18ConvolutionColwisePKfPfii:
.LFB5571:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18ConvolutionColwisePKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5571:
.size _Z18ConvolutionColwisePKfPfii, .-_Z18ConvolutionColwisePKfPfii
.section .rodata.str1.1
.LC3:
.string "_Z18ConvolutionColwisePKfPfii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z18ConvolutionRowwisePKfPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5573:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z18ConvolutionColwisePKfPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18ConvolutionRowwisePKfPfiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5573:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_,"axG",@progbits,_ZNSt6vectorIiSaIiEEC5ESt16initializer_listIiERKS0_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_
.type _ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_, @function
_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_:
.LFB5952:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5952
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
leaq 0(,%rdx,4), %rbp
movabsq $9223372036854775804, %rax
cmpq %rbp, %rax
jb .L62
movq %rsi, %r12
testq %rbp, %rbp
je .L54
movq %rbp, %rdi
.LEHB0:
call _Znwm@PLT
jmp .L63
.L62:
leaq .LC5(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE0:
.L59:
endbr64
movq %rax, %rbp
movq (%rbx), %rdi
movq 16(%rbx), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L58
call _ZdlPvm@PLT
.L58:
movq %rbp, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L63:
movq %rax, %rdi
movq %rax, (%rbx)
leaq (%rax,%rbp), %r13
movq %r13, 16(%rbx)
cmpq $4, %rbp
jle .L55
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
.L56:
movq %r13, 8(%rbx)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movl (%r12), %eax
movl %eax, (%rdi)
jmp .L56
.L54:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %r13d
jmp .L56
.cfi_endproc
.LFE5952:
.globl __gxx_personality_v0
.section .gcc_except_table._ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_,"aG",@progbits,_ZNSt6vectorIiSaIiEEC5ESt16initializer_listIiERKS0_,comdat
.LLSDA5952:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5952-.LLSDACSB5952
.LLSDACSB5952:
.uleb128 .LEHB0-.LFB5952
.uleb128 .LEHE0-.LEHB0
.uleb128 .L59-.LFB5952
.uleb128 0
.uleb128 .LEHB1-.LFB5952
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE5952:
.section .text._ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_,"axG",@progbits,_ZNSt6vectorIiSaIiEEC5ESt16initializer_listIiERKS0_,comdat
.size _ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_, .-_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_
.weak _ZNSt6vectorIiSaIiEEC1ESt16initializer_listIiERKS0_
.set _ZNSt6vectorIiSaIiEEC1ESt16initializer_listIiERKS0_,_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5955:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L67
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L67:
ret
.cfi_endproc
.LFE5955:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.text
.globl main
.type main, @function
main:
.LFB5540:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5540
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl $1, 260(%rsp)
leaq 260(%rsp), %rbx
leaq 224(%rsp), %rbp
leaq 128(%rsp), %rdi
movq %rbp, %rcx
movq %rbx, %rsi
movl $1, %edx
.LEHB2:
call _ZNSt6vectorIiSaIiEEC1ESt16initializer_listIiERKS0_
.LEHE2:
movl $1, 260(%rsp)
leaq 160(%rsp), %rdi
movq %rbp, %rcx
movq %rbx, %rsi
movl $1, %edx
.LEHB3:
call _ZNSt6vectorIiSaIiEEC1ESt16initializer_listIiERKS0_
.LEHE3:
movl $1, 260(%rsp)
movq %rbx, %rsi
movq %rbp, %rcx
leaq 192(%rsp), %rdi
movl $1, %edx
.LEHB4:
call _ZNSt6vectorIiSaIiEEC1ESt16initializer_listIiERKS0_
.LEHE4:
movl $10, 260(%rsp)
movq %rbx, %rsi
leaq 116(%rsp), %rcx
movq %rbp, %rdi
movl $1, %edx
.LEHB5:
call _ZNSt6vectorIiSaIiEEC1ESt16initializer_listIiERKS0_
.LEHE5:
leaq _ZSt4cout(%rip), %rbx
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
.LEHB6:
call _ZNKSt9basic_iosIcSt11char_traitsIcEE4fillEv@PLT
movb $48, 224(%rbx)
leaq _ZSt4cout(%rip), %rdx
movq _ZSt4cout(%rip), %rcx
movq -24(%rcx), %rax
movq $5, 16(%rdx,%rax)
movq %rdx, %rsi
addq -24(%rcx), %rsi
movl 24(%rsi), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rsi)
movq -24(%rcx), %rax
movq $1, 8(%rdx,%rax)
movq 128(%rsp), %rax
movq 136(%rsp), %rcx
movq %rcx, 64(%rsp)
cmpq %rcx, %rax
je .L71
movq %rax, 56(%rsp)
movq %rdx, %r12
.L97:
movq 56(%rsp), %rax
movl (%rax), %eax
movl %eax, 36(%rsp)
movq 160(%rsp), %rax
movq 168(%rsp), %rcx
movq %rcx, 72(%rsp)
cmpq %rcx, %rax
je .L72
movq %rax, 48(%rsp)
jmp .L96
.L133:
movl %ebx, %edi
imull %ebx, %edi
call _Z11CreateArrayi
movq %rax, %r14
movl %ebx, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L115
.L75:
call cudaDeviceSynchronize@PLT
jmp .L116
.L115:
movl %ebp, %r9d
movl %ebx, %r8d
movl 32(%rsp), %ecx
movl 36(%rsp), %edx
movq 88(%rsp), %rsi
movq %r14, %rdi
call _Z45__device_stub__Z18ConvolutionRowwisePKfPfiiiiPKfPfiiii
jmp .L75
.L116:
movl %ebp, %edx
movl %ebx, %esi
movq 88(%rsp), %rdi
call _Z8PrintMatPfii
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L117
cmpb $0, 56(%r14)
je .L78
movzbl 67(%r14), %eax
.L79:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L118
.L117:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L119
call _ZSt16__throw_bad_castv@PLT
.L119:
call __stack_chk_fail@PLT
.L78:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L79
.L118:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movslq %r15d, %rax
movq 88(%rsp), %rdx
leaq (%rdx,%rax,4), %rdi
movl %ebp, %edx
movl %ebx, %esi
call _Z8PrintMatPfii
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L120
cmpb $0, 56(%r14)
je .L82
movzbl 67(%r14), %eax
.L83:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L121
.L120:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L122
call _ZSt16__throw_bad_castv@PLT
.L122:
call __stack_chk_fail@PLT
.L82:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L83
.L121:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl %r15d, %r15d
movslq %r15d, %r15
movq 88(%rsp), %rax
leaq (%rax,%r15,4), %rdi
movl %ebp, %edx
movl %ebx, %esi
call _Z8PrintMatPfii
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L123
cmpb $0, 56(%r14)
je .L86
movzbl 67(%r14), %eax
.L87:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L124
.L123:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L125
call _ZSt16__throw_bad_castv@PLT
.L125:
call __stack_chk_fail@PLT
.L86:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L87
.L124:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl %ebp, %r14d
imull %ebp, %r14d
leal (%r14,%r14,8), %esi
movslq %esi, %rsi
leaq 96(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl %ebp, 104(%rsp)
movl %ebp, 108(%rsp)
movl $3, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $3, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L126
.L88:
call cudaDeviceSynchronize@PLT
jmp .L127
.L126:
movl %ebp, %ecx
movl %ebx, %edx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z43__device_stub__Z18ConvolutionColwisePKfPfiiPKfPfii
jmp .L88
.L127:
movslq %r14d, %r14
leaq 0(,%r14,4), %rax
movq %rax, 8(%rsp)
movl $0, %r14d
movl $9, 4(%rsp)
jmp .L93
.L132:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r15
testq %r15, %r15
je .L128
cmpb $0, 56(%r15)
je .L91
movzbl 67(%r15), %esi
.L92:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L129
.L128:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L130
call _ZSt16__throw_bad_castv@PLT
.L107:
endbr64
movq %rax, %rbx
leaq 224(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L99:
leaq 192(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L100:
leaq 160(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L101:
leaq 128(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 264(%rsp), %rax
subq %fs:40, %rax
je .L102
call __stack_chk_fail@PLT
.L130:
call __stack_chk_fail@PLT
.L91:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L92
.L129:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rax
addq %rax, %r14
subl $1, 4(%rsp)
je .L131
.L93:
movq %r14, %rdi
addq 96(%rsp), %rdi
movl %ebp, %edx
movl %ebx, %esi
call _Z8PrintMatPfii
jmp .L132
.L131:
addq $4, %r13
cmpq %r13, 16(%rsp)
je .L74
.L94:
movl 0(%r13), %ebx
leal -2(%rbx), %ebp
movl %ebx, %r15d
imull %ebp, %r15d
leal (%r15,%r15,2), %esi
movslq %esi, %rsi
leaq 88(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
.LEHE6:
jmp .L133
.L74:
addq $4, 24(%rsp)
movq 24(%rsp), %rax
cmpq %rax, 40(%rsp)
je .L73
.L95:
movq 224(%rsp), %r13
movq 232(%rsp), %rax
movq %rax, 16(%rsp)
cmpq %rax, %r13
jne .L94
jmp .L74
.L73:
addq $4, 48(%rsp)
movq 48(%rsp), %rax
cmpq %rax, 72(%rsp)
je .L72
.L96:
movq 48(%rsp), %rax
movl (%rax), %eax
movl %eax, 32(%rsp)
movq 192(%rsp), %rax
movq 200(%rsp), %rcx
movq %rcx, 40(%rsp)
cmpq %rcx, %rax
je .L73
movq %rax, 24(%rsp)
jmp .L95
.L72:
addq $4, 56(%rsp)
movq 56(%rsp), %rax
cmpq %rax, 64(%rsp)
jne .L97
.L71:
leaq 224(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 192(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 160(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 128(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L134
movl $0, %eax
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L99
.L105:
endbr64
movq %rax, %rbx
jmp .L100
.L104:
endbr64
movq %rax, %rbx
jmp .L101
.L102:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L134:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5540:
.section .gcc_except_table,"a",@progbits
.LLSDA5540:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5540-.LLSDACSB5540
.LLSDACSB5540:
.uleb128 .LEHB2-.LFB5540
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB5540
.uleb128 .LEHE3-.LEHB3
.uleb128 .L104-.LFB5540
.uleb128 0
.uleb128 .LEHB4-.LFB5540
.uleb128 .LEHE4-.LEHB4
.uleb128 .L105-.LFB5540
.uleb128 0
.uleb128 .LEHB5-.LFB5540
.uleb128 .LEHE5-.LEHB5
.uleb128 .L106-.LFB5540
.uleb128 0
.uleb128 .LEHB6-.LFB5540
.uleb128 .LEHE6-.LEHB6
.uleb128 .L107-.LFB5540
.uleb128 0
.uleb128 .LEHB7-.LFB5540
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE5540:
.text
.size main, .-main
.type _GLOBAL__sub_I__Z10GET_BLOCKSi, @function
_GLOBAL__sub_I__Z10GET_BLOCKSi:
.LFB6413:
.cfi_startproc
endbr64
movq $1, randomGeneratorEngine(%rip)
movl $0x00000000, randomGenerator(%rip)
movl $0x3f800000, 4+randomGenerator(%rip)
ret
.cfi_endproc
.LFE6413:
.size _GLOBAL__sub_I__Z10GET_BLOCKSi, .-_GLOBAL__sub_I__Z10GET_BLOCKSi
.section .init_array
.align 8
.quad _GLOBAL__sub_I__Z10GET_BLOCKSi
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl randomGenerator
.bss
.align 8
.type randomGenerator, @object
.size randomGenerator, 8
randomGenerator:
.zero 8
.globl randomGeneratorEngine
.align 8
.type randomGeneratorEngine, @object
.size randomGeneratorEngine, 8
randomGeneratorEngine:
.zero 8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <iomanip>
#include <stdio.h>
#include <chrono>
#include <random> // For kernel generation
#include <algorithm>
#include <list>
using namespace std;
#pragma region Cuda
const int WARP_SIZE = 32;
// Crude benchmarks suggest 256 is better than 512 and 1024
// TODO: Autotune/use better heuristics, improve speed more.
const int MAX_BLOCK_SIZE = 256;
const int CUDA_NUM_THREADS = 1024;
int GET_BLOCKS(const int N) {
return (N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS;
}
static int getGradParamsNumThreads(int batchSize){
//warp per item in a batch, up to a maximum
return std::min(batchSize * WARP_SIZE, MAX_BLOCK_SIZE);
}
__global__ void ConvolutionRowwise(const float *input, float *rowwiseResults, int batch_ix,
int channel_ix,
int input_dim,
int result_dim )
{
float* res1 = rowwiseResults + (blockIdx.x * result_dim);
float* res2 = res1 + (input_dim * result_dim);
float* res3 = res2 + (input_dim * result_dim);
input = input + (blockIdx.x * input_dim);
float l1 = input[0],
l2 = input[1],
l3 = input[2];
for (int i = 3; i < input_dim; ++i)
{
*res1 = (l1 + l2 + l3);
++res1;
*res2 = (l1 - l2 + l3);
++res2;
*res3 = (l1 + l2 - l3);
++res3;
l1 = l2;
l2 = l3;
l3 = input[i];
}
*res1 = (l1 + l2 + l3);
*res2 = (l1 - l2 + l3);
*res3 = (l1 + l2 - l3);
}
__global__ void ConvolutionColwise(const float *rowwiseResults, float *colwiseResults, int inputDim, int resultDim)
{
// blockDim
// Z tells us which rowwiseResults matrix to work on {0,1,2}
// X tells us the rowwiseResults matrix top-row
// Y tells us the rowwiseResults matrix col
int topCell = (blockIdx.z *inputDim*resultDim) + (blockIdx.x * resultDim) + blockIdx.y;
float l1 = rowwiseResults[topCell];
float l2 = rowwiseResults[topCell + resultDim];
float l3 = rowwiseResults[topCell + resultDim + resultDim];
topCell = (blockIdx.z * resultDim * resultDim * 3) + (blockIdx.x * resultDim) + blockIdx.y;
colwiseResults[topCell] = l1 + l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 - l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 + l2 - l3;
}
#pragma endregion
#pragma region Misc
std::default_random_engine randomGeneratorEngine;
std::uniform_real_distribution<float> randomGenerator;
float *CreateArray(int size)
{
int i;
float *arr;
cudaMallocManaged(&arr, size);
for (i = 0; i < size; ++i)
{
arr[i] = i + 1;
cout << arr[i] << " ";
//arr[i] = (int)(randomGenerator(randomGeneratorEngine) * 10);
}
cout << endl;
return arr;
}
void PrintMat(float *mat, int rows, int cols)
{
for (int i = 0; i < rows; ++i)
{
cout << "[";
for (int j = 0; j < cols - 1; ++j)
{
cout << mat[i*cols + j] << " ";
}
cout << mat[i*cols + (cols - 1)] << "]";
if (i < rows - 1)
cout << endl;
}
cout << endl;
}
template <typename Function>
void zip(const vector<int> &batchSizes, const vector<int> &inputChannels, const vector<int> &outputChannels, const vector<int> &inputDims,
Function function)
{
for (int batchSize : batchSizes)
for (int inputChannel : inputChannels)
for (int outputChannel : outputChannels)
for (int inputDim : inputDims)
function(batchSize, inputChannel, outputChannel, inputDim);
}
#pragma endregion
int main()
{
const vector<int> batchSizes = { 1 };
const vector<int> inputChannels = { 1 };
const vector<int> outputChannels = { 1 };
const vector<int> inputDims = { 10 }; // 16, 32, 64, 128, 256, 512, 650, 1024, 1280, 1500
std::cout << std::setfill('0') << std::setw(5) << std::fixed << std::setprecision(1);
zip(batchSizes, inputChannels, outputChannels, inputDims,
[](int batchIndex, int inputChannel, int outputChannel, int inputDim) {
float *rowwiseResults;
int resultDim = inputDim - 2;
int rowwiseResultsSize = 3 * inputDim * resultDim;
cudaMallocManaged(&rowwiseResults, rowwiseResultsSize);
float *arr = CreateArray(inputDim * inputDim);
dim3 grid(inputDim);
ConvolutionRowwise <<< grid, 1 >>> (arr, rowwiseResults, batchIndex, inputChannel, inputDim, resultDim);
cudaDeviceSynchronize();
PrintMat(rowwiseResults, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + inputDim * resultDim, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + (2 * (inputDim * resultDim)), inputDim, resultDim); cout << endl;
float *colResults;
cudaMallocManaged <float>(&colResults, 9 * resultDim * resultDim);
grid = dim3(resultDim, resultDim, 3);
ConvolutionColwise <<< grid, 1 >>> (rowwiseResults, colResults, inputDim, resultDim);
cudaDeviceSynchronize();
for (int i = 0; i < 9; i++)
{
PrintMat(colResults + (i*resultDim*resultDim), inputDim, resultDim); cout << endl;
}
});
//for (auto& [a, b] : zip(batchSizes, inputChannels)) {
return 0;
}
|
#include "hip/hip_runtime.h"
#include <iostream>
#include <iomanip>
#include <stdio.h>
#include <chrono>
#include <random> // For kernel generation
#include <algorithm>
#include <list>
using namespace std;
#pragma region Cuda
const int WARP_SIZE = 32;
// Crude benchmarks suggest 256 is better than 512 and 1024
// TODO: Autotune/use better heuristics, improve speed more.
const int MAX_BLOCK_SIZE = 256;
const int CUDA_NUM_THREADS = 1024;
int GET_BLOCKS(const int N) {
return (N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS;
}
static int getGradParamsNumThreads(int batchSize){
//warp per item in a batch, up to a maximum
return std::min(batchSize * WARP_SIZE, MAX_BLOCK_SIZE);
}
__global__ void ConvolutionRowwise(const float *input, float *rowwiseResults, int batch_ix,
int channel_ix,
int input_dim,
int result_dim )
{
float* res1 = rowwiseResults + (blockIdx.x * result_dim);
float* res2 = res1 + (input_dim * result_dim);
float* res3 = res2 + (input_dim * result_dim);
input = input + (blockIdx.x * input_dim);
float l1 = input[0],
l2 = input[1],
l3 = input[2];
for (int i = 3; i < input_dim; ++i)
{
*res1 = (l1 + l2 + l3);
++res1;
*res2 = (l1 - l2 + l3);
++res2;
*res3 = (l1 + l2 - l3);
++res3;
l1 = l2;
l2 = l3;
l3 = input[i];
}
*res1 = (l1 + l2 + l3);
*res2 = (l1 - l2 + l3);
*res3 = (l1 + l2 - l3);
}
__global__ void ConvolutionColwise(const float *rowwiseResults, float *colwiseResults, int inputDim, int resultDim)
{
// blockDim
// Z tells us which rowwiseResults matrix to work on {0,1,2}
// X tells us the rowwiseResults matrix top-row
// Y tells us the rowwiseResults matrix col
int topCell = (blockIdx.z *inputDim*resultDim) + (blockIdx.x * resultDim) + blockIdx.y;
float l1 = rowwiseResults[topCell];
float l2 = rowwiseResults[topCell + resultDim];
float l3 = rowwiseResults[topCell + resultDim + resultDim];
topCell = (blockIdx.z * resultDim * resultDim * 3) + (blockIdx.x * resultDim) + blockIdx.y;
colwiseResults[topCell] = l1 + l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 - l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 + l2 - l3;
}
#pragma endregion
#pragma region Misc
std::default_random_engine randomGeneratorEngine;
std::uniform_real_distribution<float> randomGenerator;
float *CreateArray(int size)
{
int i;
float *arr;
hipMallocManaged(&arr, size);
for (i = 0; i < size; ++i)
{
arr[i] = i + 1;
cout << arr[i] << " ";
//arr[i] = (int)(randomGenerator(randomGeneratorEngine) * 10);
}
cout << endl;
return arr;
}
void PrintMat(float *mat, int rows, int cols)
{
for (int i = 0; i < rows; ++i)
{
cout << "[";
for (int j = 0; j < cols - 1; ++j)
{
cout << mat[i*cols + j] << " ";
}
cout << mat[i*cols + (cols - 1)] << "]";
if (i < rows - 1)
cout << endl;
}
cout << endl;
}
template <typename Function>
void zip(const vector<int> &batchSizes, const vector<int> &inputChannels, const vector<int> &outputChannels, const vector<int> &inputDims,
Function function)
{
for (int batchSize : batchSizes)
for (int inputChannel : inputChannels)
for (int outputChannel : outputChannels)
for (int inputDim : inputDims)
function(batchSize, inputChannel, outputChannel, inputDim);
}
#pragma endregion
int main()
{
const vector<int> batchSizes = { 1 };
const vector<int> inputChannels = { 1 };
const vector<int> outputChannels = { 1 };
const vector<int> inputDims = { 10 }; // 16, 32, 64, 128, 256, 512, 650, 1024, 1280, 1500
std::cout << std::setfill('0') << std::setw(5) << std::fixed << std::setprecision(1);
zip(batchSizes, inputChannels, outputChannels, inputDims,
[](int batchIndex, int inputChannel, int outputChannel, int inputDim) {
float *rowwiseResults;
int resultDim = inputDim - 2;
int rowwiseResultsSize = 3 * inputDim * resultDim;
hipMallocManaged(&rowwiseResults, rowwiseResultsSize);
float *arr = CreateArray(inputDim * inputDim);
dim3 grid(inputDim);
ConvolutionRowwise <<< grid, 1 >>> (arr, rowwiseResults, batchIndex, inputChannel, inputDim, resultDim);
hipDeviceSynchronize();
PrintMat(rowwiseResults, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + inputDim * resultDim, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + (2 * (inputDim * resultDim)), inputDim, resultDim); cout << endl;
float *colResults;
hipMallocManaged <float>(&colResults, 9 * resultDim * resultDim);
grid = dim3(resultDim, resultDim, 3);
ConvolutionColwise <<< grid, 1 >>> (rowwiseResults, colResults, inputDim, resultDim);
hipDeviceSynchronize();
for (int i = 0; i < 9; i++)
{
PrintMat(colResults + (i*resultDim*resultDim), inputDim, resultDim); cout << endl;
}
});
//for (auto& [a, b] : zip(batchSizes, inputChannels)) {
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include "hip/hip_runtime.h"
#include <iostream>
#include <iomanip>
#include <stdio.h>
#include <chrono>
#include <random> // For kernel generation
#include <algorithm>
#include <list>
using namespace std;
#pragma region Cuda
const int WARP_SIZE = 32;
// Crude benchmarks suggest 256 is better than 512 and 1024
// TODO: Autotune/use better heuristics, improve speed more.
const int MAX_BLOCK_SIZE = 256;
const int CUDA_NUM_THREADS = 1024;
int GET_BLOCKS(const int N) {
return (N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS;
}
static int getGradParamsNumThreads(int batchSize){
//warp per item in a batch, up to a maximum
return std::min(batchSize * WARP_SIZE, MAX_BLOCK_SIZE);
}
__global__ void ConvolutionRowwise(const float *input, float *rowwiseResults, int batch_ix,
int channel_ix,
int input_dim,
int result_dim )
{
float* res1 = rowwiseResults + (blockIdx.x * result_dim);
float* res2 = res1 + (input_dim * result_dim);
float* res3 = res2 + (input_dim * result_dim);
input = input + (blockIdx.x * input_dim);
float l1 = input[0],
l2 = input[1],
l3 = input[2];
for (int i = 3; i < input_dim; ++i)
{
*res1 = (l1 + l2 + l3);
++res1;
*res2 = (l1 - l2 + l3);
++res2;
*res3 = (l1 + l2 - l3);
++res3;
l1 = l2;
l2 = l3;
l3 = input[i];
}
*res1 = (l1 + l2 + l3);
*res2 = (l1 - l2 + l3);
*res3 = (l1 + l2 - l3);
}
__global__ void ConvolutionColwise(const float *rowwiseResults, float *colwiseResults, int inputDim, int resultDim)
{
// blockDim
// Z tells us which rowwiseResults matrix to work on {0,1,2}
// X tells us the rowwiseResults matrix top-row
// Y tells us the rowwiseResults matrix col
int topCell = (blockIdx.z *inputDim*resultDim) + (blockIdx.x * resultDim) + blockIdx.y;
float l1 = rowwiseResults[topCell];
float l2 = rowwiseResults[topCell + resultDim];
float l3 = rowwiseResults[topCell + resultDim + resultDim];
topCell = (blockIdx.z * resultDim * resultDim * 3) + (blockIdx.x * resultDim) + blockIdx.y;
colwiseResults[topCell] = l1 + l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 - l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 + l2 - l3;
}
#pragma endregion
#pragma region Misc
std::default_random_engine randomGeneratorEngine;
std::uniform_real_distribution<float> randomGenerator;
float *CreateArray(int size)
{
int i;
float *arr;
hipMallocManaged(&arr, size);
for (i = 0; i < size; ++i)
{
arr[i] = i + 1;
cout << arr[i] << " ";
//arr[i] = (int)(randomGenerator(randomGeneratorEngine) * 10);
}
cout << endl;
return arr;
}
void PrintMat(float *mat, int rows, int cols)
{
for (int i = 0; i < rows; ++i)
{
cout << "[";
for (int j = 0; j < cols - 1; ++j)
{
cout << mat[i*cols + j] << " ";
}
cout << mat[i*cols + (cols - 1)] << "]";
if (i < rows - 1)
cout << endl;
}
cout << endl;
}
template <typename Function>
void zip(const vector<int> &batchSizes, const vector<int> &inputChannels, const vector<int> &outputChannels, const vector<int> &inputDims,
Function function)
{
for (int batchSize : batchSizes)
for (int inputChannel : inputChannels)
for (int outputChannel : outputChannels)
for (int inputDim : inputDims)
function(batchSize, inputChannel, outputChannel, inputDim);
}
#pragma endregion
int main()
{
const vector<int> batchSizes = { 1 };
const vector<int> inputChannels = { 1 };
const vector<int> outputChannels = { 1 };
const vector<int> inputDims = { 10 }; // 16, 32, 64, 128, 256, 512, 650, 1024, 1280, 1500
std::cout << std::setfill('0') << std::setw(5) << std::fixed << std::setprecision(1);
zip(batchSizes, inputChannels, outputChannels, inputDims,
[](int batchIndex, int inputChannel, int outputChannel, int inputDim) {
float *rowwiseResults;
int resultDim = inputDim - 2;
int rowwiseResultsSize = 3 * inputDim * resultDim;
hipMallocManaged(&rowwiseResults, rowwiseResultsSize);
float *arr = CreateArray(inputDim * inputDim);
dim3 grid(inputDim);
ConvolutionRowwise <<< grid, 1 >>> (arr, rowwiseResults, batchIndex, inputChannel, inputDim, resultDim);
hipDeviceSynchronize();
PrintMat(rowwiseResults, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + inputDim * resultDim, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + (2 * (inputDim * resultDim)), inputDim, resultDim); cout << endl;
float *colResults;
hipMallocManaged <float>(&colResults, 9 * resultDim * resultDim);
grid = dim3(resultDim, resultDim, 3);
ConvolutionColwise <<< grid, 1 >>> (rowwiseResults, colResults, inputDim, resultDim);
hipDeviceSynchronize();
for (int i = 0; i < 9; i++)
{
PrintMat(colResults + (i*resultDim*resultDim), inputDim, resultDim); cout << endl;
}
});
//for (auto& [a, b] : zip(batchSizes, inputChannels)) {
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18ConvolutionRowwisePKfPfiiii
.globl _Z18ConvolutionRowwisePKfPfiiii
.p2align 8
.type _Z18ConvolutionRowwisePKfPfiiii,@function
_Z18ConvolutionRowwisePKfPfiiii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s15, s9
s_mul_i32 s6, s9, s8
s_lshl_b64 s[4:5], s[10:11], 2
s_mul_i32 s10, s15, s8
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s4, s2, s6
s_addc_u32 s5, s3, s7
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
s_lshl_b64 s[12:13], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s0, s12
s_addc_u32 s15, s1, s13
s_clause 0x1
s_load_b64 s[10:11], s[14:15], 0x0
s_load_b32 s9, s[14:15], 0x8
s_cmp_lt_i32 s8, 4
s_cbranch_scc1 .LBB0_4
s_add_i32 s8, s8, -3
s_add_u32 s0, s12, s0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s9 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v0, s11
v_mov_b32_e32 v4, s10
s_addc_u32 s1, s13, s1
s_add_u32 s9, s0, 12
s_addc_u32 s10, s1, 0
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_2:
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, v2
s_add_u32 s12, s6, s0
s_addc_u32 s13, s7, s1
s_add_u32 s14, s4, s0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v4, v1
v_sub_f32_e32 v4, v4, v1
s_addc_u32 s15, s5, s1
s_add_u32 s16, s2, s0
s_addc_u32 s17, s3, s1
v_add_f32_e32 v5, v2, v0
v_add_f32_e32 v4, v4, v0
v_sub_f32_e32 v2, v2, v0
s_add_u32 s18, s9, s0
s_addc_u32 s19, s10, s1
s_clause 0x2
global_store_b32 v3, v5, s[16:17]
global_store_b32 v3, v4, s[14:15]
global_store_b32 v3, v2, s[12:13]
global_load_b32 v2, v3, s[18:19]
v_mov_b32_e32 v4, v1
s_add_i32 s8, s8, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc0 .LBB0_2
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_add_u32 s2, s2, s0
s_addc_u32 s3, s3, s1
s_branch .LBB0_5
.LBB0_4:
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s9 :: v_dual_mov_b32 v1, s10
v_mov_b32_e32 v0, s11
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v1, v0
v_dual_sub_f32 v0, v1, v0 :: v_dual_mov_b32 v1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_f32_e32 v4, v3, v2
v_sub_f32_e32 v2, v3, v2
s_clause 0x2
global_store_b32 v1, v4, s[2:3]
global_store_b32 v1, v0, s[4:5]
global_store_b32 v1, v2, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18ConvolutionRowwisePKfPfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 20
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18ConvolutionRowwisePKfPfiiii, .Lfunc_end0-_Z18ConvolutionRowwisePKfPfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18ConvolutionColwisePKfPfii
.globl _Z18ConvolutionColwisePKfPfii
.p2align 8
.type _Z18ConvolutionColwisePKfPfii,@function
_Z18ConvolutionColwisePKfPfii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s13
s_mul_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, s14
s_mul_i32 s4, s15, s5
s_ashr_i32 s7, s6, 31
s_mul_i32 s4, s4, 3
s_lshl_b64 s[8:9], s[6:7], 2
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[10:11], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
s_add_i32 s6, s6, s5
s_clause 0x1
s_load_b32 s8, s[8:9], 0x0
s_load_b32 s9, s[10:11], 0x0
s_ashr_i32 s7, s6, 31
s_mul_i32 s11, s5, s5
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
s_add_i32 s4, s4, s13
s_load_b32 s10, s[0:1], 0x0
s_mul_i32 s4, s4, s5
s_add_i32 s0, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[6:7], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s2, s6
s_addc_u32 s5, s3, s7
s_add_i32 s0, s0, s11
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v0, s8, s9
s_ashr_i32 s1, s0, 31
v_sub_f32_e64 v1, s8, s9
s_lshl_b64 s[6:7], s[0:1], 2
v_mov_b32_e32 v2, 0
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s0, s0, s11
v_add_f32_e32 v3, s10, v0
s_ashr_i32 s1, s0, 31
v_dual_add_f32 v1, s10, v1 :: v_dual_subrev_f32 v0, s10, v0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_clause 0x2
global_store_b32 v2, v3, s[4:5]
global_store_b32 v2, v1, s[6:7]
global_store_b32 v2, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18ConvolutionColwisePKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18ConvolutionColwisePKfPfii, .Lfunc_end1-_Z18ConvolutionColwisePKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18ConvolutionRowwisePKfPfiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z18ConvolutionRowwisePKfPfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18ConvolutionColwisePKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18ConvolutionColwisePKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <iostream>
#include <iomanip>
#include <stdio.h>
#include <chrono>
#include <random> // For kernel generation
#include <algorithm>
#include <list>
using namespace std;
#pragma region Cuda
const int WARP_SIZE = 32;
// Crude benchmarks suggest 256 is better than 512 and 1024
// TODO: Autotune/use better heuristics, improve speed more.
const int MAX_BLOCK_SIZE = 256;
const int CUDA_NUM_THREADS = 1024;
int GET_BLOCKS(const int N) {
return (N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS;
}
static int getGradParamsNumThreads(int batchSize){
//warp per item in a batch, up to a maximum
return std::min(batchSize * WARP_SIZE, MAX_BLOCK_SIZE);
}
__global__ void ConvolutionRowwise(const float *input, float *rowwiseResults, int batch_ix,
int channel_ix,
int input_dim,
int result_dim )
{
float* res1 = rowwiseResults + (blockIdx.x * result_dim);
float* res2 = res1 + (input_dim * result_dim);
float* res3 = res2 + (input_dim * result_dim);
input = input + (blockIdx.x * input_dim);
float l1 = input[0],
l2 = input[1],
l3 = input[2];
for (int i = 3; i < input_dim; ++i)
{
*res1 = (l1 + l2 + l3);
++res1;
*res2 = (l1 - l2 + l3);
++res2;
*res3 = (l1 + l2 - l3);
++res3;
l1 = l2;
l2 = l3;
l3 = input[i];
}
*res1 = (l1 + l2 + l3);
*res2 = (l1 - l2 + l3);
*res3 = (l1 + l2 - l3);
}
__global__ void ConvolutionColwise(const float *rowwiseResults, float *colwiseResults, int inputDim, int resultDim)
{
// blockDim
// Z tells us which rowwiseResults matrix to work on {0,1,2}
// X tells us the rowwiseResults matrix top-row
// Y tells us the rowwiseResults matrix col
int topCell = (blockIdx.z *inputDim*resultDim) + (blockIdx.x * resultDim) + blockIdx.y;
float l1 = rowwiseResults[topCell];
float l2 = rowwiseResults[topCell + resultDim];
float l3 = rowwiseResults[topCell + resultDim + resultDim];
topCell = (blockIdx.z * resultDim * resultDim * 3) + (blockIdx.x * resultDim) + blockIdx.y;
colwiseResults[topCell] = l1 + l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 - l2 + l3;
topCell += resultDim * resultDim;
colwiseResults[topCell] = l1 + l2 - l3;
}
#pragma endregion
#pragma region Misc
std::default_random_engine randomGeneratorEngine;
std::uniform_real_distribution<float> randomGenerator;
float *CreateArray(int size)
{
int i;
float *arr;
hipMallocManaged(&arr, size);
for (i = 0; i < size; ++i)
{
arr[i] = i + 1;
cout << arr[i] << " ";
//arr[i] = (int)(randomGenerator(randomGeneratorEngine) * 10);
}
cout << endl;
return arr;
}
void PrintMat(float *mat, int rows, int cols)
{
for (int i = 0; i < rows; ++i)
{
cout << "[";
for (int j = 0; j < cols - 1; ++j)
{
cout << mat[i*cols + j] << " ";
}
cout << mat[i*cols + (cols - 1)] << "]";
if (i < rows - 1)
cout << endl;
}
cout << endl;
}
template <typename Function>
void zip(const vector<int> &batchSizes, const vector<int> &inputChannels, const vector<int> &outputChannels, const vector<int> &inputDims,
Function function)
{
for (int batchSize : batchSizes)
for (int inputChannel : inputChannels)
for (int outputChannel : outputChannels)
for (int inputDim : inputDims)
function(batchSize, inputChannel, outputChannel, inputDim);
}
#pragma endregion
int main()
{
const vector<int> batchSizes = { 1 };
const vector<int> inputChannels = { 1 };
const vector<int> outputChannels = { 1 };
const vector<int> inputDims = { 10 }; // 16, 32, 64, 128, 256, 512, 650, 1024, 1280, 1500
std::cout << std::setfill('0') << std::setw(5) << std::fixed << std::setprecision(1);
zip(batchSizes, inputChannels, outputChannels, inputDims,
[](int batchIndex, int inputChannel, int outputChannel, int inputDim) {
float *rowwiseResults;
int resultDim = inputDim - 2;
int rowwiseResultsSize = 3 * inputDim * resultDim;
hipMallocManaged(&rowwiseResults, rowwiseResultsSize);
float *arr = CreateArray(inputDim * inputDim);
dim3 grid(inputDim);
ConvolutionRowwise <<< grid, 1 >>> (arr, rowwiseResults, batchIndex, inputChannel, inputDim, resultDim);
hipDeviceSynchronize();
PrintMat(rowwiseResults, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + inputDim * resultDim, inputDim, resultDim); cout << endl;
PrintMat(rowwiseResults + (2 * (inputDim * resultDim)), inputDim, resultDim); cout << endl;
float *colResults;
hipMallocManaged <float>(&colResults, 9 * resultDim * resultDim);
grid = dim3(resultDim, resultDim, 3);
ConvolutionColwise <<< grid, 1 >>> (rowwiseResults, colResults, inputDim, resultDim);
hipDeviceSynchronize();
for (int i = 0; i < 9; i++)
{
PrintMat(colResults + (i*resultDim*resultDim), inputDim, resultDim); cout << endl;
}
});
//for (auto& [a, b] : zip(batchSizes, inputChannels)) {
return 0;
}
|
.text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10GET_BLOCKSi # -- Begin function _Z10GET_BLOCKSi
.p2align 4, 0x90
.type _Z10GET_BLOCKSi,@function
_Z10GET_BLOCKSi: # @_Z10GET_BLOCKSi
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal 1023(%rdi), %ecx
leal 2046(%rdi), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $10, %eax
retq
.Lfunc_end0:
.size _Z10GET_BLOCKSi, .Lfunc_end0-_Z10GET_BLOCKSi
.cfi_endproc
# -- End function
.globl _Z33__device_stub__ConvolutionRowwisePKfPfiiii # -- Begin function _Z33__device_stub__ConvolutionRowwisePKfPfiiii
.p2align 4, 0x90
.type _Z33__device_stub__ConvolutionRowwisePKfPfiiii,@function
_Z33__device_stub__ConvolutionRowwisePKfPfiiii: # @_Z33__device_stub__ConvolutionRowwisePKfPfiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18ConvolutionRowwisePKfPfiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z33__device_stub__ConvolutionRowwisePKfPfiiii, .Lfunc_end1-_Z33__device_stub__ConvolutionRowwisePKfPfiiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__ConvolutionColwisePKfPfii # -- Begin function _Z33__device_stub__ConvolutionColwisePKfPfii
.p2align 4, 0x90
.type _Z33__device_stub__ConvolutionColwisePKfPfii,@function
_Z33__device_stub__ConvolutionColwisePKfPfii: # @_Z33__device_stub__ConvolutionColwisePKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18ConvolutionColwisePKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z33__device_stub__ConvolutionColwisePKfPfii, .Lfunc_end2-_Z33__device_stub__ConvolutionColwisePKfPfii
.cfi_endproc
# -- End function
.globl _Z11CreateArrayi # -- Begin function _Z11CreateArrayi
.p2align 4, 0x90
.type _Z11CreateArrayi,@function
_Z11CreateArrayi: # @_Z11CreateArrayi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movslq %edi, %r14
movq %rsp, %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
testl %r14d, %r14d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %ebx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %r14
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movq (%rsp), %rcx
movss %xmm0, (%rcx,%rax,4)
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rax
cmpq %r14, %rbx
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB3_7
.LBB3_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z11CreateArrayi, .Lfunc_end3-_Z11CreateArrayi
.cfi_endproc
# -- End function
.globl _Z8PrintMatPfii # -- Begin function _Z8PrintMatPfii
.p2align 4, 0x90
.type _Z8PrintMatPfii,@function
_Z8PrintMatPfii: # @_Z8PrintMatPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB4_9
# %bb.1: # %.lr.ph26
movl %edx, %ebx
leal -1(%rbx), %r12d
leal -1(%rsi), %eax
movslq %edx, %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
movslq %r12d, %rcx
cltq
movq %rax, 24(%rsp) # 8-byte Spill
movl %esi, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq (%rsp), %rax # 8-byte Reload
leaq (%rax,%rcx,4), %rax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB4_2
.LBB4_14: # in Loop: Header=BB4_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
# in Loop: Header=BB4_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_16: # in Loop: Header=BB4_2 Depth=1
incq %r14
addl %ebx, %ebp
cmpq 8(%rsp), %r14 # 8-byte Folded Reload
je .LBB4_9
.LBB4_2: # =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $2, %ebx
jl .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
cmpq %r13, %r12
jne .LBB4_4
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movq %r14, %rax
imulq 32(%rsp), %rax # 8-byte Folded Reload
movq 16(%rsp), %rcx # 8-byte Reload
movss (%rcx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpq 24(%rsp), %r14 # 8-byte Folded Reload
jge .LBB4_16
# %bb.6: # in Loop: Header=BB4_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB4_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
# in Loop: Header=BB4_2 Depth=1
cmpb $0, 56(%r15)
je .LBB4_14
# %bb.8: # in Loop: Header=BB4_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB4_15
.LBB4_9: # %._crit_edge27
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_17
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_12
# %bb.11:
movzbl 67(%rbx), %eax
jmp .LBB4_13
.LBB4_12:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB4_17:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z8PrintMatPfii, .Lfunc_end4-_Z8PrintMatPfii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq _Znwm
movq %rax, %r15
movl $1, (%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit23
movq %rax, %rbx
movl $1, (%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit33
movq %rax, %rsi
movl $10, (%rax)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %r14
cmpb $0, _ZSt4cout+225(%r14)
movq %r15, 40(%rsp) # 8-byte Spill
movq %rbx, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
jne .LBB5_9
# %bb.3:
movq _ZSt4cout+240(%r14), %rbx
testq %rbx, %rbx
je .LBB5_49
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i.i.i
cmpb $0, 56(%rbx)
je .LBB5_6
# %bb.5:
movzbl 89(%rbx), %eax
movq 40(%rsp), %r15 # 8-byte Reload
jmp .LBB5_8
.LBB5_6:
.Ltmp6:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq 40(%rsp), %r15 # 8-byte Reload
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp7:
# %bb.7: # %.noexc34
movq (%rbx), %rax
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $32, %esi
callq *48(%rax)
.Ltmp9:
.LBB5_8:
movq 32(%rsp), %rbx # 8-byte Reload
movq 24(%rsp), %rsi # 8-byte Reload
movb %al, _ZSt4cout+224(%r14)
movb $1, _ZSt4cout+225(%r14)
.LBB5_9: # %_ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St8_SetfillIS3_E.exit
movb $48, _ZSt4cout+224(%r14)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $5, _ZSt4cout+16(%rcx)
movq -24(%rax), %rcx
movl $-261, %edx # imm = 0xFEFB
andl _ZSt4cout+24(%rcx), %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $1, _ZSt4cout+8(%rax)
movl (%r15), %r15d
movl (%rbx), %eax
movl %eax, 120(%rsp) # 4-byte Spill
movl (%rsi), %r12d
leal -2(%r12), %ebp
movl %ebp, %r14d
imull %r12d, %r14d
leal (%r14,%r14,2), %eax
movslq %eax, %rsi
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
.Ltmp11:
# %bb.10: # %.noexc41
movl %r12d, %edi
imull %r12d, %edi
.Ltmp12:
.cfi_escape 0x2e, 0x00
callq _Z11CreateArrayi
.Ltmp13:
# %bb.11: # %.noexc42
movq %rax, %rbx
movabsq $4294967296, %r13 # imm = 0x100000000
leaq (%r12,%r13), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp15:
# %bb.12: # %.noexc43
testl %eax, %eax
jne .LBB5_15
# %bb.13:
movq 16(%rsp), %rax
movq %rbx, 112(%rsp)
movq %rax, 104(%rsp)
movl %r15d, 48(%rsp)
movl 120(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
movl %r12d, 8(%rsp)
movl %ebp, 124(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 124(%rsp), %rax
movq %rax, 168(%rsp)
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp17:
# %bb.14: # %.noexc44
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp18:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z18ConvolutionRowwisePKfPfiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp19:
.LBB5_15:
.Ltmp20:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp21:
# %bb.16: # %.noexc46
movq 16(%rsp), %rdi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl %r12d, %esi
movl %ebp, %edx
callq _Z8PrintMatPfii
.Ltmp23:
# %bb.17: # %.noexc47
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_49
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i.i.i38
cmpb $0, 56(%rbx)
je .LBB5_20
# %bb.19:
movzbl 67(%rbx), %eax
jmp .LBB5_22
.LBB5_20:
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp25:
# %bb.21: # %.noexc49
movq (%rbx), %rax
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp27:
.LBB5_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit.i.i
.Ltmp28:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp29:
# %bb.23: # %.noexc51
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp31:
# %bb.24: # %.noexc52
movslq %r14d, %rdi
shlq $2, %rdi
addq 16(%rsp), %rdi
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl %r12d, %esi
movl %ebp, %edx
callq _Z8PrintMatPfii
.Ltmp33:
# %bb.25: # %.noexc53
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_49
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53.i.i
cmpb $0, 56(%rbx)
je .LBB5_28
# %bb.27:
movzbl 67(%rbx), %eax
jmp .LBB5_30
.LBB5_28:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp35:
# %bb.29: # %.noexc55
movq (%rbx), %rax
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp37:
.LBB5_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56.i.i
.Ltmp38:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp39:
# %bb.31: # %.noexc57
.Ltmp40:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp41:
# %bb.32: # %.noexc58
addl %r14d, %r14d
movslq %r14d, %rdi
shlq $2, %rdi
addq 16(%rsp), %rdi
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl %r12d, %esi
movl %ebp, %edx
callq _Z8PrintMatPfii
.Ltmp43:
# %bb.33: # %.noexc59
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_49
# %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58.i.i
cmpb $0, 56(%rbx)
je .LBB5_36
# %bb.35:
movzbl 67(%rbx), %eax
jmp .LBB5_38
.LBB5_36:
.Ltmp44:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp45:
# %bb.37: # %.noexc61
movq (%rbx), %rax
.Ltmp46:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp47:
.LBB5_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit61.i.i
.Ltmp48:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp49:
# %bb.39: # %.noexc63
.Ltmp50:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp51:
# %bb.40: # %.noexc64
movl %ebp, %r14d
imull %r14d, %r14d
leal (%r14,%r14,8), %eax
movslq %eax, %rsi
.Ltmp52:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
.Ltmp53:
# %bb.41: # %.noexc65
movl %ebp, %eax
incq %r13
imulq %rax, %r13
.Ltmp54:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdx # imm = 0x100000001
movq %r13, %rdi
movl $3, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp55:
# %bb.42: # %.noexc66
testl %eax, %eax
jne .LBB5_45
# %bb.43:
movq 16(%rsp), %rax
movq 48(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %r12d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp56:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp57:
# %bb.44: # %.noexc67
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp58:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z18ConvolutionColwisePKfPfii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp59:
.LBB5_45:
.Ltmp60:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp61:
# %bb.46: # %.noexc69.preheader
movl $9, %r13d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_47: # %.noexc69
# =>This Inner Loop Header: Depth=1
movslq %r15d, %rdi
shlq $2, %rdi
addq 48(%rsp), %rdi
.Ltmp63:
.cfi_escape 0x2e, 0x00
movl %r12d, %esi
movl %ebp, %edx
callq _Z8PrintMatPfii
.Ltmp64:
# %bb.48: # %.noexc70
# in Loop: Header=BB5_47 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_49
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i63.i.i
# in Loop: Header=BB5_47 Depth=1
cmpb $0, 56(%rbx)
je .LBB5_53
# %bb.52: # in Loop: Header=BB5_47 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB5_55
.p2align 4, 0x90
.LBB5_53: # in Loop: Header=BB5_47 Depth=1
.Ltmp65:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp66:
# %bb.54: # %.noexc72
# in Loop: Header=BB5_47 Depth=1
movq (%rbx), %rax
.Ltmp67:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp68:
.LBB5_55: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit66.i.i
# in Loop: Header=BB5_47 Depth=1
.Ltmp69:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp70:
# %bb.56: # %.noexc74
# in Loop: Header=BB5_47 Depth=1
.Ltmp71:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp72:
# %bb.57: # %.noexc75
# in Loop: Header=BB5_47 Depth=1
addl %r14d, %r15d
decq %r13
jne .LBB5_47
# %bb.58: # %_ZZ4mainENKUliiiiE_clEiiii.exit.i
.cfi_escape 0x2e, 0x00
movq 24(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq 32(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq 40(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_49: # %.invoke
.cfi_def_cfa_offset 240
.Ltmp74:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp75:
# %bb.50: # %.cont
.LBB5_66: # %_ZNSt12_Vector_baseIiSaIiEED2Ev.exit.i30
.Ltmp5:
movq %rax, %r12
jmp .LBB5_63
.LBB5_65: # %_ZNSt12_Vector_baseIiSaIiEED2Ev.exit.i20
.Ltmp2:
movq %rax, %r12
jmp .LBB5_64
.LBB5_60: # %_ZNSt6vectorIiSaIiEED2Ev.exit89.loopexit.split-lp.loopexit
.Ltmp62:
jmp .LBB5_62
.LBB5_61: # %_ZNSt6vectorIiSaIiEED2Ev.exit89.loopexit.split-lp.loopexit.split-lp
.Ltmp76:
jmp .LBB5_62
.LBB5_59: # %_ZNSt6vectorIiSaIiEED2Ev.exit89.loopexit
.Ltmp73:
.LBB5_62: # %_ZNSt6vectorIiSaIiEED2Ev.exit89
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq 24(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
movq 40(%rsp), %r15 # 8-byte Reload
movq 32(%rsp), %rbx # 8-byte Reload
.LBB5_63: # %_ZNSt6vectorIiSaIiEED2Ev.exit95
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB5_64: # %_ZNSt6vectorIiSaIiEED2Ev.exit98
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table5:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp6 # Call between .Ltmp6 and .Ltmp9
.uleb128 .Ltmp76-.Lfunc_begin0 # jumps to .Ltmp76
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp61-.Ltmp10 # Call between .Ltmp10 and .Ltmp61
.uleb128 .Ltmp62-.Lfunc_begin0 # jumps to .Ltmp62
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp72-.Ltmp63 # Call between .Ltmp63 and .Ltmp72
.uleb128 .Ltmp73-.Lfunc_begin0 # jumps to .Ltmp73
.byte 0 # On action: cleanup
.uleb128 .Ltmp74-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp75-.Ltmp74 # Call between .Ltmp74 and .Ltmp75
.uleb128 .Ltmp76-.Lfunc_begin0 # jumps to .Ltmp76
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end5-.Ltmp75 # Call between .Ltmp75 and .Lfunc_end5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18ConvolutionRowwisePKfPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18ConvolutionColwisePKfPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18ConvolutionRowwisePKfPfiiii,@object # @_Z18ConvolutionRowwisePKfPfiiii
.section .rodata,"a",@progbits
.globl _Z18ConvolutionRowwisePKfPfiiii
.p2align 3, 0x0
_Z18ConvolutionRowwisePKfPfiiii:
.quad _Z33__device_stub__ConvolutionRowwisePKfPfiiii
.size _Z18ConvolutionRowwisePKfPfiiii, 8
.type _Z18ConvolutionColwisePKfPfii,@object # @_Z18ConvolutionColwisePKfPfii
.globl _Z18ConvolutionColwisePKfPfii
.p2align 3, 0x0
_Z18ConvolutionColwisePKfPfii:
.quad _Z33__device_stub__ConvolutionColwisePKfPfii
.size _Z18ConvolutionColwisePKfPfii, 8
.type randomGeneratorEngine,@object # @randomGeneratorEngine
.data
.globl randomGeneratorEngine
.p2align 3, 0x0
randomGeneratorEngine:
.quad 1 # 0x1
.size randomGeneratorEngine, 8
.type randomGenerator,@object # @randomGenerator
.globl randomGenerator
.p2align 2, 0x0
randomGenerator:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.size randomGenerator, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "["
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "]"
.size .L.str.3, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18ConvolutionRowwisePKfPfiiii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18ConvolutionColwisePKfPfii"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__ConvolutionRowwisePKfPfiiii
.addrsig_sym _Z33__device_stub__ConvolutionColwisePKfPfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z18ConvolutionRowwisePKfPfiiii
.addrsig_sym _Z18ConvolutionColwisePKfPfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z18ConvolutionColwisePKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.Z ; /* 0x0000000000087919 */
/* 0x000e220000002700 */
/*0020*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0050*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R0, R8, c[0x0][0x170], R9 ; /* 0x00005c0008007a24 */
/* 0x001fc800078e0209 */
/*0070*/ IMAD R0, R0, c[0x0][0x174], R13 ; /* 0x00005d0000007a24 */
/* 0x002fc800078e020d */
/*0080*/ IMAD.WIDE R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e020f */
/*0090*/ IMAD.WIDE R4, R15.reuse, c[0x0][0x174], R2 ; /* 0x00005d000f047a25 */
/* 0x040fe400078e0202 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R15, c[0x0][0x174], R4 ; /* 0x00005d000f067a25 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ LEA R0, R8, R8, 0x1 ; /* 0x0000000808007211 */
/* 0x000fe400078e08ff */
/*00f0*/ MOV R10, c[0x0][0x174] ; /* 0x00005d00000a7a02 */
/* 0x000fc60000000f00 */
/*0100*/ IMAD R0, R0, c[0x0][0x174], R9 ; /* 0x00005d0000007a24 */
/* 0x000fc800078e0209 */
/*0110*/ IMAD R0, R0, c[0x0][0x174], R13 ; /* 0x00005d0000007a24 */
/* 0x000fc800078e020d */
/*0120*/ IMAD.WIDE R8, R0, R15, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fc800078e020f */
/*0130*/ IMAD R15, R10, c[0x0][0x174], RZ ; /* 0x00005d000a0f7a24 */
/* 0x000fe400078e02ff */
/*0140*/ FADD R13, R2.reuse, R11.reuse ; /* 0x0000000b020d7221 */
/* 0x144fe40000000000 */
/*0150*/ FADD R11, R2, -R11 ; /* 0x8000000b020b7221 */
/* 0x000fe40000000000 */
/*0160*/ IMAD.WIDE R2, R15, 0x4, R8 ; /* 0x000000040f027825 */
/* 0x000fc800078e0208 */
/*0170*/ FADD R7, R6.reuse, R13 ; /* 0x0000000d06077221 */
/* 0x048fe40000000000 */
/*0180*/ FADD R11, R6.reuse, R11 ; /* 0x0000000b060b7221 */
/* 0x040fe40000000000 */
/*0190*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x000fe20000000100 */
/*01a0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x000fe2000c101904 */
/*01b0*/ IMAD.WIDE R4, R15, 0x4, R2 ; /* 0x000000040f047825 */
/* 0x000fc600078e0202 */
/*01c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18ConvolutionRowwisePKfPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD R14, R4, c[0x0][0x178], RZ ; /* 0x00005e00040e7a24 */
/* 0x001fc800078e02ff */
/*0050*/ IMAD.WIDE.U32 R8, R14, R5, c[0x0][0x160] ; /* 0x000058000e087625 */
/* 0x000fca00078e0005 */
/*0060*/ LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b7981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R0, [R8.64+0x8] ; /* 0x0000080408007981 */
/* 0x000ee2000c1e1900 */
/*0090*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD R4, R4, c[0x0][0x17c], RZ ; /* 0x00005f0004047a24 */
/* 0x000fc600078e02ff */
/*00b0*/ ISETP.GE.AND P0, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0005 */
/*00d0*/ IMAD R21, R10, c[0x0][0x17c], RZ ; /* 0x00005f000a157a24 */
/* 0x000fc800078e02ff */
/*00e0*/ IMAD.WIDE R2, R21, 0x4, R4 ; /* 0x0000000415027825 */
/* 0x000fcc00078e0204 */
/*00f0*/ IMAD.WIDE R6, R21, 0x4, R2 ; /* 0x0000000415067825 */
/* 0x000fc800078e0202 */
/*0100*/ FADD R13, R11, R12 ; /* 0x0000000c0b0d7221 */
/* 0x004fc80000000000 */
/*0110*/ FADD R15, R13, R0 ; /* 0x000000000d0f7221 */
/* 0x008fca0000000000 */
/*0120*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e2000c101904 */
/*0130*/ @!P0 BRA 0x7c0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R8, R10.reuse, -0x4, RZ ; /* 0xfffffffc0a087810 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3 ; /* 0x00000003ff0f7424 */
/* 0x001fe200078e00ff */
/*0160*/ IADD3 R10, R10, -0x3, RZ ; /* 0xfffffffd0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f06070 */
/*0180*/ LOP3.LUT R10, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a0a7812 */
/* 0x000fd600078ec0ff */
/*0190*/ @!P0 BRA 0x5c0 ; /* 0x0000042000008947 */
/* 0x000fea0003800000 */
/*01a0*/ LEA R8, P0, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e087a11 */
/* 0x000fe200078010ff */
/*01b0*/ HFMA2.MMA R15, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff0f7435 */
/* 0x000fe200000001ff */
/*01c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R21 ; /* 0x0000001fff027819 */
/* 0x000fe40000011415 */
/*01d0*/ IADD3 R8, P1, R8, 0x18, RZ ; /* 0x0000001808087810 */
/* 0x000fe40007f3e0ff */
/*01e0*/ LEA.HI.X R27, R14, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x000059000e1b7a11 */
/* 0x000fe400000f14ff */
/*01f0*/ SHF.L.U32 R23, R21.reuse, 0x2, RZ ; /* 0x0000000215177819 */
/* 0x040fe400000006ff */
/*0200*/ SHF.L.U64.HI R19, R21.reuse, 0x2, R2.reuse ; /* 0x0000000215137819 */
/* 0x140fe20000010202 */
/*0210*/ IMAD.X R27, RZ, RZ, R27, P1 ; /* 0x000000ffff1b7224 */
/* 0x000fe200008e061b */
/*0220*/ SHF.L.U64.HI R17, R21.reuse, 0x3, R2 ; /* 0x0000000315117819 */
/* 0x040fe20000010202 */
/*0230*/ IMAD.SHL.U32 R21, R21, 0x8, RZ ; /* 0x0000000815157824 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R16, -R10, c[0x0][0x178], RZ ; /* 0x00005e000a107a10 */
/* 0x000fc40007ffe1ff */
/*0250*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x004fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fc400078e0005 */
/*0270*/ FADD R7, R12, -R11 ; /* 0x8000000b0c077221 */
/* 0x000fe20000000000 */
/*0280*/ IADD3 R4, P0, R2, R23, RZ ; /* 0x0000001702047210 */
/* 0x000fe20007f1e0ff */
/*0290*/ FADD R25, -R0, R13 ; /* 0x0000000d00197221 */
/* 0x000fe20000000100 */
/*02a0*/ IADD3 R6, P1, R2, R21, RZ ; /* 0x0000001502067210 */
/* 0x000fe20007f3e0ff */
/*02b0*/ FADD R9, R7, R0 ; /* 0x0000000007097221 */
/* 0x000fe20000000000 */
/*02c0*/ IADD3.X R5, R3, R19, RZ, P0, !PT ; /* 0x0000001303057210 */
/* 0x000fc600007fe4ff */
/*02d0*/ IMAD.X R7, R3, 0x1, R17, P1 ; /* 0x0000000103077824 */
/* 0x000fe400008e0611 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c101904 */
/*02f0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e2000c101904 */
/*0300*/ MOV R9, R27 ; /* 0x0000001b00097202 */
/* 0x001fca0000000f00 */
/*0310*/ LDG.E R13, [R8.64+-0xc] ; /* 0xfffff404080d7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ FADD R12, R0.reuse, R11.reuse ; /* 0x0000000b000c7221 */
/* 0x140fe40000000000 */
/*0330*/ FADD R18, -R0, R11 ; /* 0x0000000b00127221 */
/* 0x000fe40000000100 */
/*0340*/ FADD R11, R12.reuse, R13.reuse ; /* 0x0000000d0c0b7221 */
/* 0x144fe40000000000 */
/*0350*/ FADD R27, R13.reuse, R18 ; /* 0x000000120d1b7221 */
/* 0x040fe40000000000 */
/*0360*/ FADD R29, R12, -R13 ; /* 0x8000000d0c1d7221 */
/* 0x000fe20000000000 */
/*0370*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0001e8000c101904 */
/*0380*/ STG.E [R4.64+0x4], R27 ; /* 0x0000041b04007986 */
/* 0x0005e8000c101904 */
/*0390*/ STG.E [R6.64+0x4], R29 ; /* 0x0000041d06007986 */
/* 0x0007e8000c101904 */
/*03a0*/ LDG.E R12, [R8.64+-0x8] ; /* 0xfffff804080c7981 */
/* 0x000f22000c1e1900 */
/*03b0*/ FADD R25, R13, R0 ; /* 0x000000000d197221 */
/* 0x002fc40000000000 */
/*03c0*/ FADD R18, -R13, R0 ; /* 0x000000000d127221 */
/* 0x000fe40000000100 */
/*03d0*/ FADD R0, R25.reuse, R12 ; /* 0x0000000c19007221 */
/* 0x050fe40000000000 */
/*03e0*/ FADD R18, R12, R18 ; /* 0x000000120c127221 */
/* 0x000fe40000000000 */
/*03f0*/ FADD R25, R25, -R12.reuse ; /* 0x8000000c19197221 */
/* 0x100fe20000000000 */
/*0400*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x0003e8000c101904 */
/*0410*/ STG.E [R4.64+0x8], R18 ; /* 0x0000081204007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R6.64+0x8], R25 ; /* 0x0000081906007986 */
/* 0x000fe8000c101904 */
/*0430*/ LDG.E R11, [R8.64+-0x4] ; /* 0xfffffc04080b7981 */
/* 0x001ea2000c1e1900 */
/*0440*/ FADD R20, R13, R12 ; /* 0x0000000c0d147221 */
/* 0x000fc40000000000 */
/*0450*/ FADD R22, R13, -R12 ; /* 0x8000000c0d167221 */
/* 0x000fe40000000000 */
/*0460*/ FADD R27, R20.reuse, R11.reuse ; /* 0x0000000b141b7221 */
/* 0x144fe40000000000 */
/*0470*/ FADD R29, R11, R22 ; /* 0x000000160b1d7221 */
/* 0x008fe40000000000 */
/*0480*/ FADD R20, R20, -R11.reuse ; /* 0x8000000b14147221 */
/* 0x100fe20000000000 */
/*0490*/ STG.E [R2.64+0xc], R27 ; /* 0x00000c1b02007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R4.64+0xc], R29 ; /* 0x00000c1d04007986 */
/* 0x0001e8000c101904 */
/*04b0*/ STG.E [R6.64+0xc], R20 ; /* 0x00000c1406007986 */
/* 0x0005e8000c101904 */
/*04c0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0022e2000c1e1900 */
/*04d0*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ FADD R13, R12, R11 ; /* 0x0000000b0c0d7221 */
/* 0x000fe20000000000 */
/*04f0*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fc40007ffe0ff */
/*0500*/ ISETP.NE.AND P0, PT, R16, 0x3, PT ; /* 0x000000031000780c */
/* 0x000fe40003f05270 */
/*0510*/ IADD3 R4, P1, R2, 0x10, RZ ; /* 0x0000001002047810 */
/* 0x001fe40007f3e0ff */
/*0520*/ IADD3 R8, P2, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x002fc60007f5e0ff */
/*0530*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0540*/ IADD3.X R27, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff1b7210 */
/* 0x000fe200017fe4ff */
/*0550*/ FADD R25, R13, R0 ; /* 0x000000000d197221 */
/* 0x008fca0000000000 */
/*0560*/ STG.E [R2.64+0x10], R25 ; /* 0x0000101902007986 */
/* 0x0005e2000c101904 */
/*0570*/ @P0 BRA 0x250 ; /* 0xfffffcd000000947 */
/* 0x000fea000383ffff */
/*0580*/ IADD3 R2, P0, R4.reuse, R23, RZ ; /* 0x0000001704027210 */
/* 0x044fe40007f1e0ff */
/*0590*/ IADD3 R6, P1, R4, R21, RZ ; /* 0x0000001504067210 */
/* 0x000fc60007f3e0ff */
/*05a0*/ IMAD.X R3, R5.reuse, 0x1, R19, P0 ; /* 0x0000000105037824 */
/* 0x040fe200000e0613 */
/*05b0*/ IADD3.X R7, R5, R17, RZ, P1, !PT ; /* 0x0000001105077210 */
/* 0x000fe40000ffe4ff */
/*05c0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*05d0*/ @!P0 BRA 0x7c0 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R14, P0, R14, R15, RZ ; /* 0x0000000f0e0e7210 */
/* 0x000fc80007f1e0ff */
/*05f0*/ LEA R8, P1, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e087a11 */
/* 0x000fe400078210ff */
/*0600*/ LEA.HI.X.SX32 R15, R15, RZ, 0x1, P0 ; /* 0x000000ff0f0f7211 */
/* 0x000fc800000f0eff */
/*0610*/ LEA.HI.X R17, R14, c[0x0][0x164], R15, 0x2, P1 ; /* 0x000059000e117a11 */
/* 0x000fe400008f140f */
/*0620*/ FADD R9, R12, -R11 ; /* 0x8000000b0c097221 */
/* 0x000fe40000000000 */
/*0630*/ FADD R19, -R0, R13 ; /* 0x0000000d00137221 */
/* 0x000fe40000000100 */
/*0640*/ FADD R9, R9, R0 ; /* 0x0000000009097221 */
/* 0x000fca0000000000 */
/*0650*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0660*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0003e2000c101904 */
/*0670*/ MOV R9, R17 ; /* 0x0000001100097202 */
/* 0x001fca0000000f00 */
/*0680*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x0000a2000c1e1900 */
/*0690*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ FADD R13, R0, R11.reuse ; /* 0x0000000b000d7221 */
/* 0x100fe20000000000 */
/*06b0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe20007f3e0ff */
/*06c0*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000b */
/*06d0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*06e0*/ IADD3 R11, P3, R4, 0x4, RZ ; /* 0x00000004040b7810 */
/* 0x000fe20007f7e0ff */
/*06f0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0700*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fe40007f5e0ff */
/*0710*/ IADD3 R8, P4, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x001fc40007f9e0ff */
/*0720*/ IADD3.X R9, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff097210 */
/* 0x000fe40001ffe4ff */
/*0730*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400017fe4ff */
/*0740*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200027fe4ff */
/*0750*/ FADD R15, R13, R14 ; /* 0x0000000e0d0f7221 */
/* 0x004fca0000000000 */
/*0760*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0001e4000c101904 */
/*0770*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x001fe20000000f00 */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0000 */
/*0790*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*07a0*/ MOV R0, R14 ; /* 0x0000000e00007202 */
/* 0x000fe20000000f00 */
/*07b0*/ @P0 BRA 0x620 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*07c0*/ FADD R5, R12, -R11 ; /* 0x8000000b0c057221 */
/* 0x001fe40000000000 */
/*07d0*/ FADD R13, -R0, R13 ; /* 0x0000000d000d7221 */
/* 0x000fe40000000100 */
/*07e0*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x000fca0000000000 */
/*07f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0800*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18ConvolutionRowwisePKfPfiiii
.globl _Z18ConvolutionRowwisePKfPfiiii
.p2align 8
.type _Z18ConvolutionRowwisePKfPfiiii,@function
_Z18ConvolutionRowwisePKfPfiiii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s15, s9
s_mul_i32 s6, s9, s8
s_lshl_b64 s[4:5], s[10:11], 2
s_mul_i32 s10, s15, s8
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s4, s2, s6
s_addc_u32 s5, s3, s7
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
s_lshl_b64 s[12:13], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s0, s12
s_addc_u32 s15, s1, s13
s_clause 0x1
s_load_b64 s[10:11], s[14:15], 0x0
s_load_b32 s9, s[14:15], 0x8
s_cmp_lt_i32 s8, 4
s_cbranch_scc1 .LBB0_4
s_add_i32 s8, s8, -3
s_add_u32 s0, s12, s0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s9 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v0, s11
v_mov_b32_e32 v4, s10
s_addc_u32 s1, s13, s1
s_add_u32 s9, s0, 12
s_addc_u32 s10, s1, 0
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_2:
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, v2
s_add_u32 s12, s6, s0
s_addc_u32 s13, s7, s1
s_add_u32 s14, s4, s0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v4, v1
v_sub_f32_e32 v4, v4, v1
s_addc_u32 s15, s5, s1
s_add_u32 s16, s2, s0
s_addc_u32 s17, s3, s1
v_add_f32_e32 v5, v2, v0
v_add_f32_e32 v4, v4, v0
v_sub_f32_e32 v2, v2, v0
s_add_u32 s18, s9, s0
s_addc_u32 s19, s10, s1
s_clause 0x2
global_store_b32 v3, v5, s[16:17]
global_store_b32 v3, v4, s[14:15]
global_store_b32 v3, v2, s[12:13]
global_load_b32 v2, v3, s[18:19]
v_mov_b32_e32 v4, v1
s_add_i32 s8, s8, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc0 .LBB0_2
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_add_u32 s2, s2, s0
s_addc_u32 s3, s3, s1
s_branch .LBB0_5
.LBB0_4:
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s9 :: v_dual_mov_b32 v1, s10
v_mov_b32_e32 v0, s11
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v1, v0
v_dual_sub_f32 v0, v1, v0 :: v_dual_mov_b32 v1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_f32_e32 v4, v3, v2
v_sub_f32_e32 v2, v3, v2
s_clause 0x2
global_store_b32 v1, v4, s[2:3]
global_store_b32 v1, v0, s[4:5]
global_store_b32 v1, v2, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18ConvolutionRowwisePKfPfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 20
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18ConvolutionRowwisePKfPfiiii, .Lfunc_end0-_Z18ConvolutionRowwisePKfPfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18ConvolutionColwisePKfPfii
.globl _Z18ConvolutionColwisePKfPfii
.p2align 8
.type _Z18ConvolutionColwisePKfPfii,@function
_Z18ConvolutionColwisePKfPfii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s13
s_mul_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, s14
s_mul_i32 s4, s15, s5
s_ashr_i32 s7, s6, 31
s_mul_i32 s4, s4, 3
s_lshl_b64 s[8:9], s[6:7], 2
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[10:11], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
s_add_i32 s6, s6, s5
s_clause 0x1
s_load_b32 s8, s[8:9], 0x0
s_load_b32 s9, s[10:11], 0x0
s_ashr_i32 s7, s6, 31
s_mul_i32 s11, s5, s5
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
s_add_i32 s4, s4, s13
s_load_b32 s10, s[0:1], 0x0
s_mul_i32 s4, s4, s5
s_add_i32 s0, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[6:7], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s2, s6
s_addc_u32 s5, s3, s7
s_add_i32 s0, s0, s11
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v0, s8, s9
s_ashr_i32 s1, s0, 31
v_sub_f32_e64 v1, s8, s9
s_lshl_b64 s[6:7], s[0:1], 2
v_mov_b32_e32 v2, 0
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s0, s0, s11
v_add_f32_e32 v3, s10, v0
s_ashr_i32 s1, s0, 31
v_dual_add_f32 v1, s10, v1 :: v_dual_subrev_f32 v0, s10, v0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_clause 0x2
global_store_b32 v2, v3, s[4:5]
global_store_b32 v2, v1, s[6:7]
global_store_b32 v2, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18ConvolutionColwisePKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18ConvolutionColwisePKfPfii, .Lfunc_end1-_Z18ConvolutionColwisePKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18ConvolutionRowwisePKfPfiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z18ConvolutionRowwisePKfPfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18ConvolutionColwisePKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18ConvolutionColwisePKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
* model.c
*
*
*/
#include <math.h>
#include <cuda.h>
struct model_data_
{
double mygamma;
double *theta;
int N_samples;
int N_sensors;
} model_data;
extern "C"
__global__ void GPU_model(double *g, double *d,double *theta,double mygamma,int N_samples,int N_sensors)
{
int ix= blockDim.x*blockIdx.x+threadIdx.x;
int iy= blockDim.y*blockIdx.y+threadIdx.y;
if(ix<N_samples && iy<N_sensors)
{
g[ix*N_sensors+iy] = 0.0;
g[ix*N_sensors+iy] = mygamma*theta[ix*2+1]/(2*M_PI*(pow((d[0]+iy*d[1])-theta[ix*2+0],2.0) + pow(theta[ix*2+1],2)));
}
}
extern "C"
void model(double *g, double *d)
{
double mygamma = model_data.mygamma;
double *theta = model_data.theta;
int N_samples = model_data.N_samples;
int N_sensors = model_data.N_sensors;
//////////////////////////////////
// model.m
// This function provides the model function (= velocity measurements) for the
// vortex optimal sensor placement problem.
// Input:
// mygamma : vortex strength
// theta : samples of model parameters
// d : vector of design parameters, d = [x_s, h]
// N_sensors : number of sensors to be placed
//
// Author: Franziska Krummenacher, krummenf@student.ethz.ch
// Spring/Summer 2016
//////////////////////////////////
//extract number of samples
//N_samples = size(theta,1);
//initialize output matrix
//g = zeros(N_samples,N_sensors);
////allocate GPU memory
double *d_g;
double *d_d;
double *d_theta;
cudaMalloc(&d_g,N_samples*N_sensors*sizeof(double));
cudaMalloc(&d_d,2*sizeof(double));
cudaMalloc(&d_theta,2*N_samples*sizeof(double));
//GPU memory copy
cudaMemcpy(d_g,g,N_samples*N_sensors*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(d_d,d,2*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(d_theta,theta,2*N_samples*sizeof(double),cudaMemcpyHostToDevice);
//kernel call
dim3 blocks(40,1);
dim3 threads(100,5);
GPU_model<<<blocks,threads>>>(d_g,d_d,d_theta,mygamma,N_samples,N_sensors);
cudaMemcpy(g,d_g,N_samples*N_sensors*sizeof(double),cudaMemcpyDeviceToHost);
cudaFree(d_g);
cudaFree(d_d);
cudaFree(d_theta);
//for (int i = 0; i < N_samples; i++)
// for (int j = 0; j < N_sensors; j++)
// g[i*N_sensors+j] = 0.0;
//fill in model predictions
//for (int i = 0; i < N_samples; i++)
// for (int k = 0; k < N_sensors; k++)
// {
// g[i*N_sensors+k] = mygamma*theta[i*2+1]/(2*M_PI*(pow((d[0]+k*d[1])-theta[i*2+0],2.0) + pow(theta[i*2+1],2)));
// }
return;
}
|
.file "tmpxft_000136f0_00000000-6_model.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
.type _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii, @function
_Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq GPU_model(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii, .-_Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
.globl GPU_model
.type GPU_model, @function
GPU_model:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size GPU_model, .-GPU_model
.globl model
.type model, @function
model:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movsd model_data(%rip), %xmm1
movsd %xmm1, 8(%rsp)
movq 8+model_data(%rip), %r15
movl 16+model_data(%rip), %r13d
movl 20+model_data(%rip), %r14d
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leal (%r13,%r13), %ebp
movslq %ebp, %rbp
salq $3, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $100, 60(%rsp)
movl $5, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r14d, %r8d
movl %r13d, %ecx
movsd 8(%rsp), %xmm0
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size model, .-model
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU_model"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq GPU_model(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl model_data
.bss
.align 16
.type model_data, @object
.size model_data, 24
model_data:
.zero 24
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* model.c
*
*
*/
#include <math.h>
#include <cuda.h>
struct model_data_
{
double mygamma;
double *theta;
int N_samples;
int N_sensors;
} model_data;
extern "C"
__global__ void GPU_model(double *g, double *d,double *theta,double mygamma,int N_samples,int N_sensors)
{
int ix= blockDim.x*blockIdx.x+threadIdx.x;
int iy= blockDim.y*blockIdx.y+threadIdx.y;
if(ix<N_samples && iy<N_sensors)
{
g[ix*N_sensors+iy] = 0.0;
g[ix*N_sensors+iy] = mygamma*theta[ix*2+1]/(2*M_PI*(pow((d[0]+iy*d[1])-theta[ix*2+0],2.0) + pow(theta[ix*2+1],2)));
}
}
extern "C"
void model(double *g, double *d)
{
double mygamma = model_data.mygamma;
double *theta = model_data.theta;
int N_samples = model_data.N_samples;
int N_sensors = model_data.N_sensors;
//////////////////////////////////
// model.m
// This function provides the model function (= velocity measurements) for the
// vortex optimal sensor placement problem.
// Input:
// mygamma : vortex strength
// theta : samples of model parameters
// d : vector of design parameters, d = [x_s, h]
// N_sensors : number of sensors to be placed
//
// Author: Franziska Krummenacher, krummenf@student.ethz.ch
// Spring/Summer 2016
//////////////////////////////////
//extract number of samples
//N_samples = size(theta,1);
//initialize output matrix
//g = zeros(N_samples,N_sensors);
////allocate GPU memory
double *d_g;
double *d_d;
double *d_theta;
cudaMalloc(&d_g,N_samples*N_sensors*sizeof(double));
cudaMalloc(&d_d,2*sizeof(double));
cudaMalloc(&d_theta,2*N_samples*sizeof(double));
//GPU memory copy
cudaMemcpy(d_g,g,N_samples*N_sensors*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(d_d,d,2*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(d_theta,theta,2*N_samples*sizeof(double),cudaMemcpyHostToDevice);
//kernel call
dim3 blocks(40,1);
dim3 threads(100,5);
GPU_model<<<blocks,threads>>>(d_g,d_d,d_theta,mygamma,N_samples,N_sensors);
cudaMemcpy(g,d_g,N_samples*N_sensors*sizeof(double),cudaMemcpyDeviceToHost);
cudaFree(d_g);
cudaFree(d_d);
cudaFree(d_theta);
//for (int i = 0; i < N_samples; i++)
// for (int j = 0; j < N_sensors; j++)
// g[i*N_sensors+j] = 0.0;
//fill in model predictions
//for (int i = 0; i < N_samples; i++)
// for (int k = 0; k < N_sensors; k++)
// {
// g[i*N_sensors+k] = mygamma*theta[i*2+1]/(2*M_PI*(pow((d[0]+k*d[1])-theta[i*2+0],2.0) + pow(theta[i*2+1],2)));
// }
return;
}
|
/*
* model.c
*
*
*/
#include <math.h>
#include <hip/hip_runtime.h>
struct model_data_
{
double mygamma;
double *theta;
int N_samples;
int N_sensors;
} model_data;
extern "C"
__global__ void GPU_model(double *g, double *d,double *theta,double mygamma,int N_samples,int N_sensors)
{
int ix= blockDim.x*blockIdx.x+threadIdx.x;
int iy= blockDim.y*blockIdx.y+threadIdx.y;
if(ix<N_samples && iy<N_sensors)
{
g[ix*N_sensors+iy] = 0.0;
g[ix*N_sensors+iy] = mygamma*theta[ix*2+1]/(2*M_PI*(pow((d[0]+iy*d[1])-theta[ix*2+0],2.0) + pow(theta[ix*2+1],2)));
}
}
extern "C"
void model(double *g, double *d)
{
double mygamma = model_data.mygamma;
double *theta = model_data.theta;
int N_samples = model_data.N_samples;
int N_sensors = model_data.N_sensors;
//////////////////////////////////
// model.m
// This function provides the model function (= velocity measurements) for the
// vortex optimal sensor placement problem.
// Input:
// mygamma : vortex strength
// theta : samples of model parameters
// d : vector of design parameters, d = [x_s, h]
// N_sensors : number of sensors to be placed
//
// Author: Franziska Krummenacher, krummenf@student.ethz.ch
// Spring/Summer 2016
//////////////////////////////////
//extract number of samples
//N_samples = size(theta,1);
//initialize output matrix
//g = zeros(N_samples,N_sensors);
////allocate GPU memory
double *d_g;
double *d_d;
double *d_theta;
hipMalloc(&d_g,N_samples*N_sensors*sizeof(double));
hipMalloc(&d_d,2*sizeof(double));
hipMalloc(&d_theta,2*N_samples*sizeof(double));
//GPU memory copy
hipMemcpy(d_g,g,N_samples*N_sensors*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_d,d,2*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_theta,theta,2*N_samples*sizeof(double),hipMemcpyHostToDevice);
//kernel call
dim3 blocks(40,1);
dim3 threads(100,5);
GPU_model<<<blocks,threads>>>(d_g,d_d,d_theta,mygamma,N_samples,N_sensors);
hipMemcpy(g,d_g,N_samples*N_sensors*sizeof(double),hipMemcpyDeviceToHost);
hipFree(d_g);
hipFree(d_d);
hipFree(d_theta);
//for (int i = 0; i < N_samples; i++)
// for (int j = 0; j < N_sensors; j++)
// g[i*N_sensors+j] = 0.0;
//fill in model predictions
//for (int i = 0; i < N_samples; i++)
// for (int k = 0; k < N_sensors; k++)
// {
// g[i*N_sensors+k] = mygamma*theta[i*2+1]/(2*M_PI*(pow((d[0]+k*d[1])-theta[i*2+0],2.0) + pow(theta[i*2+1],2)));
// }
return;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
* model.c
*
*
*/
#include <math.h>
#include <hip/hip_runtime.h>
struct model_data_
{
double mygamma;
double *theta;
int N_samples;
int N_sensors;
} model_data;
extern "C"
__global__ void GPU_model(double *g, double *d,double *theta,double mygamma,int N_samples,int N_sensors)
{
int ix= blockDim.x*blockIdx.x+threadIdx.x;
int iy= blockDim.y*blockIdx.y+threadIdx.y;
if(ix<N_samples && iy<N_sensors)
{
g[ix*N_sensors+iy] = 0.0;
g[ix*N_sensors+iy] = mygamma*theta[ix*2+1]/(2*M_PI*(pow((d[0]+iy*d[1])-theta[ix*2+0],2.0) + pow(theta[ix*2+1],2)));
}
}
extern "C"
void model(double *g, double *d)
{
double mygamma = model_data.mygamma;
double *theta = model_data.theta;
int N_samples = model_data.N_samples;
int N_sensors = model_data.N_sensors;
//////////////////////////////////
// model.m
// This function provides the model function (= velocity measurements) for the
// vortex optimal sensor placement problem.
// Input:
// mygamma : vortex strength
// theta : samples of model parameters
// d : vector of design parameters, d = [x_s, h]
// N_sensors : number of sensors to be placed
//
// Author: Franziska Krummenacher, krummenf@student.ethz.ch
// Spring/Summer 2016
//////////////////////////////////
//extract number of samples
//N_samples = size(theta,1);
//initialize output matrix
//g = zeros(N_samples,N_sensors);
////allocate GPU memory
double *d_g;
double *d_d;
double *d_theta;
hipMalloc(&d_g,N_samples*N_sensors*sizeof(double));
hipMalloc(&d_d,2*sizeof(double));
hipMalloc(&d_theta,2*N_samples*sizeof(double));
//GPU memory copy
hipMemcpy(d_g,g,N_samples*N_sensors*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_d,d,2*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_theta,theta,2*N_samples*sizeof(double),hipMemcpyHostToDevice);
//kernel call
dim3 blocks(40,1);
dim3 threads(100,5);
GPU_model<<<blocks,threads>>>(d_g,d_d,d_theta,mygamma,N_samples,N_sensors);
hipMemcpy(g,d_g,N_samples*N_sensors*sizeof(double),hipMemcpyDeviceToHost);
hipFree(d_g);
hipFree(d_d);
hipFree(d_theta);
//for (int i = 0; i < N_samples; i++)
// for (int j = 0; j < N_sensors; j++)
// g[i*N_sensors+j] = 0.0;
//fill in model predictions
//for (int i = 0; i < N_samples; i++)
// for (int k = 0; k < N_sensors; k++)
// {
// g[i*N_sensors+k] = mygamma*theta[i*2+1]/(2*M_PI*(pow((d[0]+k*d[1])-theta[i*2+0],2.0) + pow(theta[i*2+1],2)));
// }
return;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected GPU_model
.globl GPU_model
.p2align 8
.type GPU_model,@function
GPU_model:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v2
v_cmp_gt_i32_e64 s2, s9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, v2, s9, v[4:5]
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
v_lshlrev_b32_e32 v2, 1, v2
v_cvt_f64_i32_e32 v[4:5], v4
s_mov_b32 s9, 0x3fbdee67
v_mov_b32_e32 v7, v6
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s8, 0x4222de17
s_mov_b32 s11, 0x3fbe25e4
s_mov_b32 s10, 0x3abe935a
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3c7abc9e
global_store_b64 v[0:1], v[6:7], off
global_load_b128 v[7:10], v3, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 3, v[2:3]
v_or_b32_e32 v2, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[2:3]
global_load_b64 v[11:12], v[11:12], off
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s5, 0x3fba6564
s_mov_b32 s4, 0x968915a9
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(2)
v_fma_f64 v[4:5], v[9:10], v[4:5], v[7:8]
s_waitcnt vmcnt(0)
v_frexp_mant_f64_e64 v[9:10], |v[2:3]|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], -v[11:12]
v_cmp_gt_f64_e64 s0, s[2:3], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_frexp_mant_f64_e64 v[7:8], |v[4:5]|
v_cndmask_b32_e64 v13, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[9:10], v[9:10], v13
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[15:16], v[9:10], 1.0
v_add_f64 v[25:26], v[9:10], -1.0
v_cndmask_b32_e64 v11, 0, 1, vcc_lo
v_ldexp_f64 v[7:8], v[7:8], v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[19:20], v[15:16]
v_add_f64 v[11:12], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[17:18], v[13:14], v[13:14]
v_fma_f64 v[17:18], -v[15:16], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[21:22], -v[11:12], v[13:14], 1.0
v_fma_f64 v[17:18], v[17:18], v[19:20], v[19:20]
v_add_f64 v[19:20], v[7:8], -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[21:22], v[13:14], v[13:14]
v_fma_f64 v[21:22], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[23:24], v[19:20], v[13:14]
v_fma_f64 v[17:18], v[21:22], v[17:18], v[17:18]
v_add_f64 v[21:22], v[11:12], -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[27:28], v[11:12], v[23:24]
v_mul_f64 v[29:30], v[25:26], v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[7:8], v[7:8], -v[21:22]
v_add_f64 v[21:22], v[15:16], -1.0
v_fma_f64 v[11:12], v[23:24], v[11:12], -v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[31:32], v[15:16], v[29:30]
v_add_f64 v[9:10], v[9:10], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[7:8], v[23:24], v[7:8], v[11:12]
v_fma_f64 v[11:12], v[29:30], v[15:16], -v[31:32]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[15:16], v[27:28], v[7:8]
v_fma_f64 v[9:10], v[29:30], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[19:20], -v[15:16]
v_add_f64 v[21:22], v[31:32], v[9:10]
v_add_f64 v[27:28], v[15:16], -v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], v[19:20], -v[11:12]
v_add_f64 v[33:34], v[25:26], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[27:28], -v[7:8]
v_add_f64 v[15:16], v[19:20], -v[15:16]
v_add_f64 v[19:20], v[21:22], -v[31:32]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[25:26], v[25:26], -v[33:34]
v_add_f64 v[7:8], v[7:8], v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[19:20], -v[9:10]
v_add_f64 v[15:16], v[25:26], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[11:12], v[7:8]
v_add_f64 v[9:10], v[9:10], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[7:8], v[13:14], v[7:8]
v_add_f64 v[9:10], v[33:34], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[23:24], v[7:8]
v_mul_f64 v[9:10], v[17:18], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[11:12], -v[23:24]
v_mul_f64 v[17:18], v[11:12], v[11:12]
v_add_f64 v[15:16], v[29:30], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[7:8], -v[13:14]
v_fma_f64 v[19:20], v[11:12], v[11:12], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[13:14], v[15:16], -v[29:30]
v_mul_f64 v[23:24], v[15:16], v[15:16]
v_add_f64 v[21:22], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], -v[13:14]
v_fma_f64 v[13:14], v[11:12], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[19:20], v[15:16], v[15:16], -v[23:24]
v_add_f64 v[21:22], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[25:26], v[17:18], v[13:14]
v_fma_f64 v[19:20], v[15:16], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[21:22], v[25:26], s[8:9], s[4:5]
v_add_f64 v[17:18], v[25:26], -v[17:18]
v_add_f64 v[27:28], v[23:24], v[19:20]
v_mul_f64 v[35:36], v[11:12], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[21:22], v[25:26], v[21:22], s[10:11]
v_add_f64 v[13:14], v[13:14], -v[17:18]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[29:30], v[27:28], s[8:9], s[4:5]
s_mov_b32 s5, 0x3fc110ef
s_mov_b32 s4, 0x47e6c9c2
s_mov_b32 s9, 0x3fc3b13b
s_mov_b32 s8, 0xcfa74449
v_add_f64 v[23:24], v[27:28], -v[23:24]
v_mul_f64 v[43:44], v[15:16], v[27:28]
v_fma_f64 v[21:22], v[25:26], v[21:22], s[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[29:30], v[27:28], v[29:30], s[10:11]
v_add_f64 v[19:20], v[19:20], -v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[21:22], v[25:26], v[21:22], s[8:9]
v_fma_f64 v[29:30], v[27:28], v[29:30], s[4:5]
s_mov_b32 s5, 0x3fc745d1
s_mov_b32 s4, 0x71bf3c30
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[21:22], v[25:26], v[21:22], s[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[29:30], v[27:28], v[29:30], s[8:9]
s_mov_b32 s9, 0x3fcc71c7
s_mov_b32 s8, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[21:22], v[25:26], v[21:22], s[8:9]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[29:30], v[27:28], v[29:30], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x924920da
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[21:22], v[25:26], v[21:22], s[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[29:30], v[27:28], v[29:30], s[8:9]
s_mov_b32 s9, 0x3fd99999
s_mov_b32 s8, 0x9999999c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[21:22], v[25:26], v[21:22], s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[29:30], v[27:28], v[29:30], s[4:5]
s_mov_b32 s5, 0xbfe55555
s_mov_b32 s4, s2
v_mul_f64 v[31:32], v[25:26], v[21:22]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[29:30], v[27:28], v[29:30], s[8:9]
v_fma_f64 v[17:18], v[25:26], v[21:22], -v[31:32]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[33:34], v[27:28], v[29:30]
v_fma_f64 v[17:18], v[13:14], v[21:22], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[21:22], v[27:28], v[29:30], -v[33:34]
v_add_f64 v[23:24], v[31:32], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[21:22], v[19:20], v[29:30], v[21:22]
v_add_f64 v[29:30], v[23:24], s[2:3]
v_add_f64 v[31:32], v[23:24], -v[31:32]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[37:38], v[33:34], v[21:22]
v_add_f64 v[39:40], v[29:30], s[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[17:18], v[17:18], -v[31:32]
v_fma_f64 v[31:32], v[25:26], v[11:12], -v[35:36]
v_add_f64 v[41:42], v[37:38], s[2:3]
v_add_f64 v[33:34], v[37:38], -v[33:34]
s_mov_b32 s3, 0x3c8543b0
s_mov_b32 s2, 0xd5df274d
v_add_f64 v[23:24], v[23:24], -v[39:40]
v_add_f64 v[17:18], v[17:18], s[2:3]
v_fma_f64 v[25:26], v[25:26], v[7:8], v[31:32]
v_add_f64 v[31:32], v[41:42], s[4:5]
v_add_f64 v[21:22], v[21:22], -v[33:34]
v_fma_f64 v[33:34], v[27:28], v[15:16], -v[43:44]
v_ldexp_f64 v[7:8], v[7:8], 1
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
v_add_f64 v[17:18], v[17:18], v[23:24]
v_fma_f64 v[13:14], v[13:14], v[11:12], v[25:26]
v_add_f64 v[23:24], v[37:38], -v[31:32]
v_add_f64 v[21:22], v[21:22], s[2:3]
v_fma_f64 v[25:26], v[27:28], v[9:10], v[33:34]
v_ldexp_f64 v[11:12], v[11:12], 1
s_mov_b32 s3, 0x3fe62e42
s_mov_b32 s2, 0xfefa39ef
v_ldexp_f64 v[9:10], v[9:10], 1
v_add_f64 v[27:28], v[29:30], v[17:18]
v_add_f64 v[31:32], v[35:36], v[13:14]
v_add_f64 v[21:22], v[21:22], v[23:24]
v_fma_f64 v[19:20], v[19:20], v[15:16], v[25:26]
v_ldexp_f64 v[15:16], v[15:16], 1
v_add_f64 v[23:24], v[29:30], -v[27:28]
v_mul_f64 v[25:26], v[31:32], v[27:28]
v_add_f64 v[35:36], v[31:32], -v[35:36]
v_add_f64 v[29:30], v[41:42], v[21:22]
v_add_f64 v[33:34], v[43:44], v[19:20]
v_add_f64 v[17:18], v[17:18], v[23:24]
v_fma_f64 v[23:24], v[31:32], v[27:28], -v[25:26]
v_add_f64 v[13:14], v[13:14], -v[35:36]
v_add_f64 v[37:38], v[41:42], -v[29:30]
v_mul_f64 v[39:40], v[33:34], v[29:30]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[17:18], v[31:32], v[17:18], v[23:24]
v_add_f64 v[23:24], v[33:34], -v[43:44]
v_add_f64 v[21:22], v[21:22], v[37:38]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[31:32], v[33:34], v[29:30], -v[39:40]
v_fma_f64 v[13:14], v[13:14], v[27:28], v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[17:18], v[19:20], -v[23:24]
v_frexp_exp_i32_f64_e32 v23, v[4:5]
v_fma_f64 v[19:20], v[33:34], v[21:22], v[31:32]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[21:22], v[25:26], v[13:14]
v_fma_f64 v[17:18], v[17:18], v[29:30], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v19, vcc_lo, 0, v23, vcc_lo
v_frexp_exp_i32_f64_e32 v29, v[2:3]
v_cvt_f64_i32_e32 v[19:20], v19
v_add_f64 v[23:24], v[11:12], v[21:22]
v_add_f64 v[25:26], v[21:22], -v[25:26]
v_add_f64 v[27:28], v[39:40], v[17:18]
v_subrev_co_ci_u32_e64 v31, vcc_lo, 0, v29, s0
s_mov_b32 s0, 0x3b39803f
v_mul_f64 v[29:30], v[19:20], s[2:3]
v_cmp_eq_f64_e32 vcc_lo, 1.0, v[4:5]
v_add_f64 v[11:12], v[23:24], -v[11:12]
v_add_f64 v[13:14], v[13:14], -v[25:26]
v_cvt_f64_i32_e32 v[25:26], v31
v_add_f64 v[31:32], v[15:16], v[27:28]
v_add_f64 v[33:34], v[27:28], -v[39:40]
v_fma_f64 v[35:36], v[19:20], s[2:3], -v[29:30]
v_add_f64 v[11:12], v[21:22], -v[11:12]
v_add_f64 v[7:8], v[7:8], v[13:14]
v_mul_f64 v[13:14], v[25:26], s[2:3]
v_add_f64 v[15:16], v[31:32], -v[15:16]
v_add_f64 v[17:18], v[17:18], -v[33:34]
v_fma_f64 v[19:20], v[19:20], s[0:1], v[35:36]
v_add_f64 v[7:8], v[7:8], v[11:12]
v_fma_f64 v[11:12], v[25:26], s[2:3], -v[13:14]
v_add_f64 v[15:16], v[27:28], -v[15:16]
v_add_f64 v[9:10], v[9:10], v[17:18]
s_mov_b32 s3, 0xbfe62e42
v_add_f64 v[17:18], v[29:30], v[19:20]
v_add_f64 v[21:22], v[23:24], v[7:8]
v_fma_f64 v[11:12], v[25:26], s[0:1], v[11:12]
s_mov_b32 s1, 0xbc7abc9e
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[9:10], v[9:10], v[15:16]
v_add_f64 v[29:30], v[17:18], -v[29:30]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[15:16], v[17:18], v[21:22]
v_add_f64 v[25:26], v[13:14], v[11:12]
v_add_f64 v[23:24], v[21:22], -v[23:24]
v_add_f64 v[27:28], v[31:32], v[9:10]
v_add_f64 v[19:20], v[19:20], -v[29:30]
v_add_f64 v[33:34], v[15:16], -v[17:18]
v_add_f64 v[13:14], v[25:26], -v[13:14]
v_add_f64 v[7:8], v[7:8], -v[23:24]
v_add_f64 v[35:36], v[25:26], v[27:28]
v_add_f64 v[23:24], v[27:28], -v[31:32]
v_add_f64 v[37:38], v[15:16], -v[33:34]
v_add_f64 v[21:22], v[21:22], -v[33:34]
v_add_f64 v[31:32], v[19:20], v[7:8]
v_add_f64 v[39:40], v[35:36], -v[25:26]
v_add_f64 v[11:12], v[11:12], -v[13:14]
v_add_f64 v[9:10], v[9:10], -v[23:24]
v_add_f64 v[17:18], v[17:18], -v[37:38]
v_add_f64 v[23:24], v[31:32], -v[19:20]
v_add_f64 v[29:30], v[35:36], -v[39:40]
v_add_f64 v[13:14], v[27:28], -v[39:40]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[17:18], v[21:22], v[17:18]
v_add_f64 v[7:8], v[7:8], -v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[21:22], v[25:26], -v[29:30]
v_add_f64 v[25:26], v[11:12], v[9:10]
v_add_f64 v[17:18], v[31:32], v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[13:14], v[13:14], v[21:22]
v_add_f64 v[21:22], v[31:32], -v[23:24]
v_add_f64 v[29:30], v[25:26], -v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[27:28], v[15:16], v[17:18]
v_add_f64 v[13:14], v[25:26], v[13:14]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[19:20], v[19:20], -v[21:22]
v_add_f64 v[21:22], v[25:26], -v[29:30]
v_add_f64 v[9:10], v[9:10], -v[29:30]
v_add_f64 v[15:16], v[27:28], -v[15:16]
v_add_f64 v[23:24], v[35:36], v[13:14]
v_add_f64 v[7:8], v[7:8], v[19:20]
v_add_f64 v[11:12], v[11:12], -v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[15:16], v[17:18], -v[15:16]
v_add_f64 v[17:18], v[23:24], -v[35:36]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[15:16], v[7:8], v[15:16]
v_add_f64 v[7:8], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[13:14], -v[17:18]
v_add_f64 v[11:12], v[27:28], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[7:8], v[9:10]
v_cndmask_b32_e64 v7, 2.0, 0x3ff00000, vcc_lo
v_add_f64 v[13:14], v[11:12], -v[27:28]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[17:18], v[6:7], v[11:12]
v_add_f64 v[19:20], v[23:24], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[15:16], -v[13:14]
v_fma_f64 v[10:11], v[6:7], v[11:12], -v[17:18]
v_cmp_class_f64_e64 vcc_lo, v[17:18], 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[15:16], v[19:20], -v[23:24]
v_add_f64 v[21:22], v[19:20], v[19:20]
v_fma_f64 v[10:11], v[6:7], v[13:14], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[15:16]
v_fma_f64 v[12:13], v[19:20], 2.0, -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[17:18], v[10:11]
v_fma_f64 v[8:9], v[8:9], 2.0, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v13, v15, v18 :: v_dual_cndmask_b32 v12, v14, v17
v_cmp_class_f64_e64 vcc_lo, v[21:22], 0x204
v_add_f64 v[19:20], v[21:22], v[8:9]
v_add_f64 v[14:15], v[14:15], -v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[23:24], v[12:13], s[4:5]
v_dual_cndmask_b32 v26, v20, v22 :: v_dual_cndmask_b32 v25, v19, v21
v_add_f64 v[18:19], v[19:20], -v[21:22]
s_delay_alu instid0(VALU_DEP_3)
v_rndne_f64_e32 v[23:24], v[23:24]
v_add_f64 v[10:11], v[10:11], -v[14:15]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[12:13]|
v_mul_f64 v[27:28], v[25:26], s[4:5]
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[29:30], v[23:24], s[2:3], v[12:13]
v_cvt_i32_f64_e32 v16, v[23:24]
v_rndne_f64_e32 v[27:28], v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[29:30], v[23:24], s[0:1], v[29:30]
v_fma_f64 v[31:32], v[27:28], s[2:3], v[25:26]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], s[4:5], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[31:32], v[27:28], s[0:1], v[31:32]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], v[33:34], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fma_f64 v[35:36], v[31:32], s[4:5], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
v_cmp_neq_f64_e64 s4, 0x7ff00000, |v[25:26]|
v_fma_f64 v[33:34], v[29:30], v[33:34], s[2:3]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], v[33:34], s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], v[33:34], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], v[33:34], s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], v[33:34], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], v[33:34], s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[33:34], v[29:30], v[33:34], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[0:1]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[12:13]
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[12:13]
v_fma_f64 v[33:34], v[29:30], v[33:34], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[2:3]
v_fma_f64 v[23:24], v[29:30], v[33:34], 1.0
v_mul_f64 v[33:34], v[6:7], 0.5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f64 v[29:30], v[31:32], v[35:36], 1.0
v_cvt_i32_f64_e32 v35, v[27:28]
v_trunc_f64_e32 v[27:28], v[6:7]
v_ldexp_f64 v[16:17], v[23:24], v16
v_fma_f64 v[23:24], v[31:32], v[29:30], 1.0
v_trunc_f64_e32 v[29:30], v[33:34]
s_delay_alu instid0(VALU_DEP_4)
v_cmp_eq_f64_e64 s2, v[27:28], v[6:7]
v_add_f64 v[6:7], v[8:9], -v[18:19]
v_dual_cndmask_b32 v9, 0, v11 :: v_dual_cndmask_b32 v8, 0, v10
s_and_b32 vcc_lo, s1, s0
v_cndmask_b32_e64 v14, 0x7ff00000, v17, s0
v_cndmask_b32_e32 v10, 0, v16, vcc_lo
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[25:26]
v_ldexp_f64 v[12:13], v[23:24], v35
v_cmp_neq_f64_e64 s3, v[29:30], v[33:34]
v_cndmask_b32_e64 v11, 0, v14, s1
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[25:26]
v_cndmask_b32_e64 v7, 0, v7, s4
v_cndmask_b32_e64 v6, 0, v6, s4
v_cmp_class_f64_e64 s4, v[4:5], 0x204
v_fma_f64 v[8:9], v[10:11], v[8:9], v[10:11]
v_cmp_class_f64_e64 s1, v[10:11], 0x204
v_cndmask_b32_e32 v13, 0x7ff00000, v13, vcc_lo
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v14, 0x3ff00000, v5, s3
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e64 v13, 0, v13, s0
v_cmp_eq_f64_e64 s0, 0, v[4:5]
v_cndmask_b32_e64 v9, v9, v11, s1
v_cndmask_b32_e64 v8, v8, v10, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_bfi_b32 v9, 0x7fffffff, v9, v14
v_cndmask_b32_e64 v11, 0, v8, s2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v10, 0x7ff80000, v9, s2
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
v_cmp_neq_f64_e64 s2, 0, v[2:3]
v_cndmask_b32_e64 v14, 0x7ff00000, 0, s0
s_or_b32 s0, s0, s4
v_cndmask_b32_e32 v9, v9, v10, vcc_lo
v_fma_f64 v[6:7], v[12:13], v[6:7], v[12:13]
v_cmp_class_f64_e64 s1, v[12:13], 0x204
v_cndmask_b32_e32 v8, v8, v11, vcc_lo
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
v_mul_f64 v[2:3], v[2:3], s[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, v8, 0, s0
v_cndmask_b32_e64 v7, v7, v13, s1
v_cndmask_b32_e64 v13, 0, v5, s3
v_and_b32_e32 v7, 0x7fffffff, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_bfi_b32 v13, 0x7fffffff, v14, v13
v_cndmask_b32_e32 v7, 0x7ff00000, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v9, v9, v13, s0
v_cmp_o_f64_e64 s0, v[4:5], v[4:5]
v_cndmask_b32_e64 v4, v6, v12, s1
s_and_b32 vcc_lo, s2, vcc_lo
v_cndmask_b32_e64 v5, 0, v7, s2
s_mov_b32 s1, 0x401921fb
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v6, 0, v8, s0
v_cndmask_b32_e64 v7, 0x7ff80000, v9, s0
s_mov_b32 s0, 0x54442d18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_mul_f64 v[4:5], v[4:5], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel GPU_model
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 45
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size GPU_model, .Lfunc_end0-GPU_model
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: GPU_model
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: GPU_model.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 45
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
* model.c
*
*
*/
#include <math.h>
#include <hip/hip_runtime.h>
struct model_data_
{
double mygamma;
double *theta;
int N_samples;
int N_sensors;
} model_data;
extern "C"
__global__ void GPU_model(double *g, double *d,double *theta,double mygamma,int N_samples,int N_sensors)
{
int ix= blockDim.x*blockIdx.x+threadIdx.x;
int iy= blockDim.y*blockIdx.y+threadIdx.y;
if(ix<N_samples && iy<N_sensors)
{
g[ix*N_sensors+iy] = 0.0;
g[ix*N_sensors+iy] = mygamma*theta[ix*2+1]/(2*M_PI*(pow((d[0]+iy*d[1])-theta[ix*2+0],2.0) + pow(theta[ix*2+1],2)));
}
}
extern "C"
void model(double *g, double *d)
{
double mygamma = model_data.mygamma;
double *theta = model_data.theta;
int N_samples = model_data.N_samples;
int N_sensors = model_data.N_sensors;
//////////////////////////////////
// model.m
// This function provides the model function (= velocity measurements) for the
// vortex optimal sensor placement problem.
// Input:
// mygamma : vortex strength
// theta : samples of model parameters
// d : vector of design parameters, d = [x_s, h]
// N_sensors : number of sensors to be placed
//
// Author: Franziska Krummenacher, krummenf@student.ethz.ch
// Spring/Summer 2016
//////////////////////////////////
//extract number of samples
//N_samples = size(theta,1);
//initialize output matrix
//g = zeros(N_samples,N_sensors);
////allocate GPU memory
double *d_g;
double *d_d;
double *d_theta;
hipMalloc(&d_g,N_samples*N_sensors*sizeof(double));
hipMalloc(&d_d,2*sizeof(double));
hipMalloc(&d_theta,2*N_samples*sizeof(double));
//GPU memory copy
hipMemcpy(d_g,g,N_samples*N_sensors*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_d,d,2*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_theta,theta,2*N_samples*sizeof(double),hipMemcpyHostToDevice);
//kernel call
dim3 blocks(40,1);
dim3 threads(100,5);
GPU_model<<<blocks,threads>>>(d_g,d_d,d_theta,mygamma,N_samples,N_sensors);
hipMemcpy(g,d_g,N_samples*N_sensors*sizeof(double),hipMemcpyDeviceToHost);
hipFree(d_g);
hipFree(d_d);
hipFree(d_theta);
//for (int i = 0; i < N_samples; i++)
// for (int j = 0; j < N_sensors; j++)
// g[i*N_sensors+j] = 0.0;
//fill in model predictions
//for (int i = 0; i < N_samples; i++)
// for (int k = 0; k < N_sensors; k++)
// {
// g[i*N_sensors+k] = mygamma*theta[i*2+1]/(2*M_PI*(pow((d[0]+k*d[1])-theta[i*2+0],2.0) + pow(theta[i*2+1],2)));
// }
return;
}
|
.text
.file "model.hip"
.globl __device_stub__GPU_model # -- Begin function __device_stub__GPU_model
.p2align 4, 0x90
.type __device_stub__GPU_model,@function
__device_stub__GPU_model: # @__device_stub__GPU_model
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $GPU_model, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__GPU_model, .Lfunc_end0-__device_stub__GPU_model
.cfi_endproc
# -- End function
.globl model # -- Begin function model
.p2align 4, 0x90
.type model,@function
model: # @model
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq %rdi, %rbx
movsd model_data(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq model_data+8(%rip), %r15
movslq model_data+16(%rip), %rbp
movl model_data+20(%rip), %eax
movl %eax, 36(%rsp) # 4-byte Spill
imull %ebp, %eax
movslq %eax, %r14
shlq $3, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rbp, %r13
shlq $4, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967336, %rdi # imm = 0x100000028
movabsq $21474836580, %rdx # imm = 0x500000064
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
movl %ebp, 44(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $GPU_model, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size model, .Lfunc_end1-model
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $GPU_model, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type model_data,@object # @model_data
.bss
.globl model_data
.p2align 3, 0x0
model_data:
.zero 24
.size model_data, 24
.type GPU_model,@object # @GPU_model
.section .rodata,"a",@progbits
.globl GPU_model
.p2align 3, 0x0
GPU_model:
.quad __device_stub__GPU_model
.size GPU_model, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "GPU_model"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__GPU_model
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym GPU_model
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000136f0_00000000-6_model.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
.type _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii, @function
_Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq GPU_model(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii, .-_Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
.globl GPU_model
.type GPU_model, @function
GPU_model:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size GPU_model, .-GPU_model
.globl model
.type model, @function
model:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movsd model_data(%rip), %xmm1
movsd %xmm1, 8(%rsp)
movq 8+model_data(%rip), %r15
movl 16+model_data(%rip), %r13d
movl 20+model_data(%rip), %r14d
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leal (%r13,%r13), %ebp
movslq %ebp, %rbp
salq $3, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $100, 60(%rsp)
movl $5, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r14d, %r8d
movl %r13d, %ecx
movsd 8(%rsp), %xmm0
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z9GPU_modelPdS_S_diiPdS_S_dii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size model, .-model
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU_model"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq GPU_model(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl model_data
.bss
.align 16
.type model_data, @object
.size model_data, 24
model_data:
.zero 24
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "model.hip"
.globl __device_stub__GPU_model # -- Begin function __device_stub__GPU_model
.p2align 4, 0x90
.type __device_stub__GPU_model,@function
__device_stub__GPU_model: # @__device_stub__GPU_model
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $GPU_model, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__GPU_model, .Lfunc_end0-__device_stub__GPU_model
.cfi_endproc
# -- End function
.globl model # -- Begin function model
.p2align 4, 0x90
.type model,@function
model: # @model
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq %rdi, %rbx
movsd model_data(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq model_data+8(%rip), %r15
movslq model_data+16(%rip), %rbp
movl model_data+20(%rip), %eax
movl %eax, 36(%rsp) # 4-byte Spill
imull %ebp, %eax
movslq %eax, %r14
shlq $3, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rbp, %r13
shlq $4, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967336, %rdi # imm = 0x100000028
movabsq $21474836580, %rdx # imm = 0x500000064
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
movl %ebp, 44(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $GPU_model, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size model, .Lfunc_end1-model
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $GPU_model, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type model_data,@object # @model_data
.bss
.globl model_data
.p2align 3, 0x0
model_data:
.zero 24
.size model_data, 24
.type GPU_model,@object # @GPU_model
.section .rodata,"a",@progbits
.globl GPU_model
.p2align 3, 0x0
GPU_model:
.quad __device_stub__GPU_model
.size GPU_model, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "GPU_model"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__GPU_model
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym GPU_model
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#ifdef __CUDACC__
#define cuda_SYNCTHREADS() __syncthreads();
#else
#define cuda_SYNCTHREADS()
#endif
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <math.h>
#define N 32
/*
calcula el valor aproximado de pi, realizando particiones (entre mas, hay mas aproximacion al valor)
*/
__host__ float func(float valor)
{
return 4 / (1 + powf(valor,2));
}
__global__ void calcula(float *particion, float *funcion, float *sum)
{
//reserva dinamica de memoria compartida en tiempo de ejecucion
extern __shared__ float temporal[];
float add[N];
//float h = (1 - 0) / N;
int id = threadIdx.x;// +blockIdx.x * blockDim.x;
float xi, xim;
float yi, yim;
//printf("%.2f, \n", particion[id]);
xi = particion[id];
xim = particion[id - 1];
yi = funcion[id];
yim = funcion[id - 1];
add[id] = .5f * ((xi - xim) * (yi + yim));
temporal[id] = add[id];
printf("(%.4f - %.4f) * (%.4f + %.4f): %.4f\n", xi, xim, yi, yim, temporal[id]);
cuda_SYNCTHREADS();
//reduccion paralela
int salto = N / 2;
//realizamos log2(N) iteraciones
while (salto)
{
//solo trabajan la mitad de los hilos
if (id < salto)
{
temporal[id] = temporal[id] + temporal[id + salto];
}
//cuda_SYNCTHREADS();
cuda_SYNCTHREADS();
salto = salto / 2;
}
//el hilo 0 escribe el resultado final en la memoria global
if (id == 0)
{
*sum = temporal[id];
//printf("temporal: %.3f\n", *sum);
}
}
int main(int argc, char** argv)
{
float *vector1, *vector2, *resultado;
float *dev_vector1, *dev_vector2, *dev_resultado;
size_t size = N * sizeof(float);
//reserva de memoria en el host
vector1 = (float*)malloc(size);
vector2 = (float*)malloc(size);
resultado = (float*)malloc(size);
//reserva de memoria en el device
cudaMalloc((void**)&dev_vector1, size);
cudaMalloc((void**)&dev_vector2, size);
cudaMalloc((void**)&dev_resultado, size);
// inicializacion de los vectores
for (int i = 0; i < N; i++) {
vector1[i] = (float)i / (N - 1);
vector2[i] = func(vector1[i]);
//printf("xi: %.2f, f(xi): %.2f \n", vector1[i], vector2[i]);
}
//enviar los datos hacia el Device
cudaMemcpy(dev_vector1, vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_vector2, vector2, size, cudaMemcpyHostToDevice);
//cudaMemcpy(dev_resultado, resultado, size, cudaMemcpyHostToDevice);
//lanzamiento del kernel con memoria dinamica compartida
calcula <<<1, N, size>>>(dev_vector1, dev_vector2, dev_resultado);
//recogida de los datos
cudaMemcpy(resultado, dev_resultado, size, cudaMemcpyDeviceToHost);
printf("pi = %.5f, \n", resultado[0]);
return 0;
}
|
code for sm_80
Function : _Z7calculaPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x28, RZ ; /* 0xffffffd801017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE R4, R2, R7, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fe200078e0207 */
/*0070*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc2404007981 */
/* 0x0000a8000c1e1900 */
/*0080*/ LDG.E R19, [R4.64] ; /* 0x0000002404137981 */
/* 0x0000e8000c1e1900 */
/*0090*/ LDG.E R18, [R6.64+-0x4] ; /* 0xfffffc2406127981 */
/* 0x000328000c1e1900 */
/*00a0*/ LDG.E R13, [R6.64] ; /* 0x00000024060d7981 */
/* 0x000322000c1e1900 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x001fe200078e00ff */
/*00c0*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fc40000000f00 */
/*00d0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x002fca0007f1e0ff */
/*00e0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00f0*/ F2F.F64.F32 R10, R0 ; /* 0x00000000000a7310 */
/* 0x0040620000201800 */
/*0100*/ FADD R3, -R0, R19 ; /* 0x0000001300037221 */
/* 0x008fce0000000100 */
/*0110*/ F2F.F64.F32 R8, R19 ; /* 0x0000001300087310 */
/* 0x000ea20000201800 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe20000000f00 */
/*0130*/ FADD R16, R18, R13 ; /* 0x0000000d12107221 */
/* 0x010fc80000000000 */
/*0140*/ FMUL.D2 R3, R3, R16 ; /* 0x0000001003037220 */
/* 0x000fe40000300000 */
/*0150*/ F2F.F64.F32 R14, R18 ; /* 0x00000012000e7310 */
/* 0x0000e20000201800 */
/*0160*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0023e80000100a00 */
/*0170*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x0003e60000004800 */
/*0180*/ F2F.F64.F32 R12, R13 ; /* 0x0000000d000c7310 */
/* 0x000f220000201800 */
/*0190*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0043e20000100a00 */
/*01a0*/ LDC.64 R18, c[0x4][R0] ; /* 0x0100000000127b82 */
/* 0x00122c0000000a00 */
/*01b0*/ F2F.F64.F32 R16, R3 ; /* 0x0000000300107310 */
/* 0x000ea20000201800 */
/*01c0*/ STL.64 [R1+0x18], R14 ; /* 0x0000180e01007387 */
/* 0x0083e80000100a00 */
/*01d0*/ STL.64 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0103e80000100a00 */
/*01e0*/ STL.64 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0043e40000100a00 */
/*01f0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe40000000000 */
/*0200*/ MOV R3, 0x270 ; /* 0x0000027000037802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R20, 0x1f0 ; /* 0x000001f000147802 */
/* 0x000fc40000000f00 */
/*0220*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0230*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0240*/ IADD3 R20, P0, P1, -R20, R3, R8 ; /* 0x0000000314147210 */
/* 0x000fc8000791e108 */
/*0250*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0260*/ CALL.ABS.NOINC R18 ; /* 0x0000000012007343 */
/* 0x001fea0003c00000 */
/*0270*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GT.AND P0, PT, R2.reuse, 0xf, PT ; /* 0x0000000f0200780c */
/* 0x040fe40003f04270 */
/*02a0*/ ISETP.GT.AND P1, PT, R2, 0x7, PT ; /* 0x000000070200780c */
/* 0x000fd60003f24270 */
/*02b0*/ @!P0 LDS R0, [R2.X4] ; /* 0x0000000002008984 */
/* 0x000fe80000004800 */
/*02c0*/ @!P0 LDS R3, [R2.X4+0x40] ; /* 0x0000400002038984 */
/* 0x000e240000004800 */
/*02d0*/ @!P0 FADD R3, R0, R3 ; /* 0x0000000300038221 */
/* 0x001fca0000000000 */
/*02e0*/ @!P0 STS [R2.X4], R3 ; /* 0x0000000302008388 */
/* 0x000fe80000004800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ ISETP.GT.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fca0003f04270 */
/*0310*/ @!P1 LDS R0, [R2.X4] ; /* 0x0000000002009984 */
/* 0x000fe80000004800 */
/*0320*/ @!P1 LDS R5, [R2.X4+0x20] ; /* 0x0000200002059984 */
/* 0x000e240000004800 */
/*0330*/ @!P1 FADD R5, R0, R5 ; /* 0x0000000500059221 */
/* 0x001fca0000000000 */
/*0340*/ @!P1 STS [R2.X4], R5 ; /* 0x0000000502009388 */
/* 0x000fe80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ ISETP.GT.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fca0003f24270 */
/*0370*/ @!P0 LDS R0, [R2.X4] ; /* 0x0000000002008984 */
/* 0x000fe80000004800 */
/*0380*/ @!P0 LDS R7, [R2.X4+0x10] ; /* 0x0000100002078984 */
/* 0x000e240000004800 */
/*0390*/ @!P0 FADD R7, R0, R7 ; /* 0x0000000700078221 */
/* 0x001fca0000000000 */
/*03a0*/ @!P0 STS [R2.X4], R7 ; /* 0x0000000702008388 */
/* 0x000fe80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fca0003f04270 */
/*03d0*/ @!P1 LDS R0, [R2.X4] ; /* 0x0000000002009984 */
/* 0x000fe80000004800 */
/*03e0*/ @!P1 LDS R3, [R2.X4+0x8] ; /* 0x0000080002039984 */
/* 0x000e240000004800 */
/*03f0*/ @!P1 FADD R3, R0, R3 ; /* 0x0000000300039221 */
/* 0x001fca0000000000 */
/*0400*/ @!P1 STS [R2.X4], R3 ; /* 0x0000000302009388 */
/* 0x000fe80000004800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0420*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fca0003f25270 */
/*0430*/ @!P0 LDS R0, [R2.X4] ; /* 0x0000000002008984 */
/* 0x000fe80000004800 */
/*0440*/ @!P0 LDS R5, [R2.X4+0x4] ; /* 0x0000040002058984 */
/* 0x000e240000004800 */
/*0450*/ @!P0 FADD R5, R0, R5 ; /* 0x0000000500058221 */
/* 0x001fca0000000000 */
/*0460*/ @!P0 STS [R2.X4], R5 ; /* 0x0000000502008388 */
/* 0x0001e80000004800 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0480*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0490*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*04b0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*04c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101924 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#ifdef __CUDACC__
#define cuda_SYNCTHREADS() __syncthreads();
#else
#define cuda_SYNCTHREADS()
#endif
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <math.h>
#define N 32
/*
calcula el valor aproximado de pi, realizando particiones (entre mas, hay mas aproximacion al valor)
*/
__host__ float func(float valor)
{
return 4 / (1 + powf(valor,2));
}
__global__ void calcula(float *particion, float *funcion, float *sum)
{
//reserva dinamica de memoria compartida en tiempo de ejecucion
extern __shared__ float temporal[];
float add[N];
//float h = (1 - 0) / N;
int id = threadIdx.x;// +blockIdx.x * blockDim.x;
float xi, xim;
float yi, yim;
//printf("%.2f, \n", particion[id]);
xi = particion[id];
xim = particion[id - 1];
yi = funcion[id];
yim = funcion[id - 1];
add[id] = .5f * ((xi - xim) * (yi + yim));
temporal[id] = add[id];
printf("(%.4f - %.4f) * (%.4f + %.4f): %.4f\n", xi, xim, yi, yim, temporal[id]);
cuda_SYNCTHREADS();
//reduccion paralela
int salto = N / 2;
//realizamos log2(N) iteraciones
while (salto)
{
//solo trabajan la mitad de los hilos
if (id < salto)
{
temporal[id] = temporal[id] + temporal[id + salto];
}
//cuda_SYNCTHREADS();
cuda_SYNCTHREADS();
salto = salto / 2;
}
//el hilo 0 escribe el resultado final en la memoria global
if (id == 0)
{
*sum = temporal[id];
//printf("temporal: %.3f\n", *sum);
}
}
int main(int argc, char** argv)
{
float *vector1, *vector2, *resultado;
float *dev_vector1, *dev_vector2, *dev_resultado;
size_t size = N * sizeof(float);
//reserva de memoria en el host
vector1 = (float*)malloc(size);
vector2 = (float*)malloc(size);
resultado = (float*)malloc(size);
//reserva de memoria en el device
cudaMalloc((void**)&dev_vector1, size);
cudaMalloc((void**)&dev_vector2, size);
cudaMalloc((void**)&dev_resultado, size);
// inicializacion de los vectores
for (int i = 0; i < N; i++) {
vector1[i] = (float)i / (N - 1);
vector2[i] = func(vector1[i]);
//printf("xi: %.2f, f(xi): %.2f \n", vector1[i], vector2[i]);
}
//enviar los datos hacia el Device
cudaMemcpy(dev_vector1, vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_vector2, vector2, size, cudaMemcpyHostToDevice);
//cudaMemcpy(dev_resultado, resultado, size, cudaMemcpyHostToDevice);
//lanzamiento del kernel con memoria dinamica compartida
calcula <<<1, N, size>>>(dev_vector1, dev_vector2, dev_resultado);
//recogida de los datos
cudaMemcpy(resultado, dev_resultado, size, cudaMemcpyDeviceToHost);
printf("pi = %.5f, \n", resultado[0]);
return 0;
}
|
.file "tmpxft_000157e1_00000000-6_ejercicio10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4funcf
.type _Z4funcf, @function
_Z4funcf:
.LFB2057:
.cfi_startproc
endbr64
mulss %xmm0, %xmm0
addss .LC0(%rip), %xmm0
movss .LC1(%rip), %xmm1
divss %xmm0, %xmm1
movaps %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z4funcf, .-_Z4funcf
.globl _Z30__device_stub__Z7calculaPfS_S_PfS_S_
.type _Z30__device_stub__Z7calculaPfS_S_PfS_S_, @function
_Z30__device_stub__Z7calculaPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7calculaPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z7calculaPfS_S_PfS_S_, .-_Z30__device_stub__Z7calculaPfS_S_PfS_S_
.globl _Z7calculaPfS_S_
.type _Z7calculaPfS_S_, @function
_Z7calculaPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7calculaPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7calculaPfS_S_, .-_Z7calculaPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "pi = %.5f, \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
movl $128, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC2(%rip), %xmm4
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm4, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
mulss %xmm0, %xmm0
addss %xmm3, %xmm0
movaps %xmm2, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L13
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $128, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7calculaPfS_S_PfS_S_
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7calculaPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calculaPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1082130432
.align 4
.LC2:
.long 1106771968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#ifdef __CUDACC__
#define cuda_SYNCTHREADS() __syncthreads();
#else
#define cuda_SYNCTHREADS()
#endif
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <math.h>
#define N 32
/*
calcula el valor aproximado de pi, realizando particiones (entre mas, hay mas aproximacion al valor)
*/
__host__ float func(float valor)
{
return 4 / (1 + powf(valor,2));
}
__global__ void calcula(float *particion, float *funcion, float *sum)
{
//reserva dinamica de memoria compartida en tiempo de ejecucion
extern __shared__ float temporal[];
float add[N];
//float h = (1 - 0) / N;
int id = threadIdx.x;// +blockIdx.x * blockDim.x;
float xi, xim;
float yi, yim;
//printf("%.2f, \n", particion[id]);
xi = particion[id];
xim = particion[id - 1];
yi = funcion[id];
yim = funcion[id - 1];
add[id] = .5f * ((xi - xim) * (yi + yim));
temporal[id] = add[id];
printf("(%.4f - %.4f) * (%.4f + %.4f): %.4f\n", xi, xim, yi, yim, temporal[id]);
cuda_SYNCTHREADS();
//reduccion paralela
int salto = N / 2;
//realizamos log2(N) iteraciones
while (salto)
{
//solo trabajan la mitad de los hilos
if (id < salto)
{
temporal[id] = temporal[id] + temporal[id + salto];
}
//cuda_SYNCTHREADS();
cuda_SYNCTHREADS();
salto = salto / 2;
}
//el hilo 0 escribe el resultado final en la memoria global
if (id == 0)
{
*sum = temporal[id];
//printf("temporal: %.3f\n", *sum);
}
}
int main(int argc, char** argv)
{
float *vector1, *vector2, *resultado;
float *dev_vector1, *dev_vector2, *dev_resultado;
size_t size = N * sizeof(float);
//reserva de memoria en el host
vector1 = (float*)malloc(size);
vector2 = (float*)malloc(size);
resultado = (float*)malloc(size);
//reserva de memoria en el device
cudaMalloc((void**)&dev_vector1, size);
cudaMalloc((void**)&dev_vector2, size);
cudaMalloc((void**)&dev_resultado, size);
// inicializacion de los vectores
for (int i = 0; i < N; i++) {
vector1[i] = (float)i / (N - 1);
vector2[i] = func(vector1[i]);
//printf("xi: %.2f, f(xi): %.2f \n", vector1[i], vector2[i]);
}
//enviar los datos hacia el Device
cudaMemcpy(dev_vector1, vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_vector2, vector2, size, cudaMemcpyHostToDevice);
//cudaMemcpy(dev_resultado, resultado, size, cudaMemcpyHostToDevice);
//lanzamiento del kernel con memoria dinamica compartida
calcula <<<1, N, size>>>(dev_vector1, dev_vector2, dev_resultado);
//recogida de los datos
cudaMemcpy(resultado, dev_resultado, size, cudaMemcpyDeviceToHost);
printf("pi = %.5f, \n", resultado[0]);
return 0;
}
|
/*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#ifdef __HIPCC__
#define cuda_SYNCTHREADS() __syncthreads();
#else
#define cuda_SYNCTHREADS()
#endif
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define N 32
/*
calcula el valor aproximado de pi, realizando particiones (entre mas, hay mas aproximacion al valor)
*/
__host__ float func(float valor)
{
return 4 / (1 + powf(valor,2));
}
__global__ void calcula(float *particion, float *funcion, float *sum)
{
//reserva dinamica de memoria compartida en tiempo de ejecucion
extern __shared__ float temporal[];
float add[N];
//float h = (1 - 0) / N;
int id = threadIdx.x;// +blockIdx.x * blockDim.x;
float xi, xim;
float yi, yim;
//printf("%.2f, \n", particion[id]);
xi = particion[id];
xim = particion[id - 1];
yi = funcion[id];
yim = funcion[id - 1];
add[id] = .5f * ((xi - xim) * (yi + yim));
temporal[id] = add[id];
printf("(%.4f - %.4f) * (%.4f + %.4f): %.4f\n", xi, xim, yi, yim, temporal[id]);
cuda_SYNCTHREADS();
//reduccion paralela
int salto = N / 2;
//realizamos log2(N) iteraciones
while (salto)
{
//solo trabajan la mitad de los hilos
if (id < salto)
{
temporal[id] = temporal[id] + temporal[id + salto];
}
//cuda_SYNCTHREADS();
cuda_SYNCTHREADS();
salto = salto / 2;
}
//el hilo 0 escribe el resultado final en la memoria global
if (id == 0)
{
*sum = temporal[id];
//printf("temporal: %.3f\n", *sum);
}
}
int main(int argc, char** argv)
{
float *vector1, *vector2, *resultado;
float *dev_vector1, *dev_vector2, *dev_resultado;
size_t size = N * sizeof(float);
//reserva de memoria en el host
vector1 = (float*)malloc(size);
vector2 = (float*)malloc(size);
resultado = (float*)malloc(size);
//reserva de memoria en el device
hipMalloc((void**)&dev_vector1, size);
hipMalloc((void**)&dev_vector2, size);
hipMalloc((void**)&dev_resultado, size);
// inicializacion de los vectores
for (int i = 0; i < N; i++) {
vector1[i] = (float)i / (N - 1);
vector2[i] = func(vector1[i]);
//printf("xi: %.2f, f(xi): %.2f \n", vector1[i], vector2[i]);
}
//enviar los datos hacia el Device
hipMemcpy(dev_vector1, vector1, size, hipMemcpyHostToDevice);
hipMemcpy(dev_vector2, vector2, size, hipMemcpyHostToDevice);
//cudaMemcpy(dev_resultado, resultado, size, cudaMemcpyHostToDevice);
//lanzamiento del kernel con memoria dinamica compartida
calcula <<<1, N, size>>>(dev_vector1, dev_vector2, dev_resultado);
//recogida de los datos
hipMemcpy(resultado, dev_resultado, size, hipMemcpyDeviceToHost);
printf("pi = %.5f, \n", resultado[0]);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
autor fredy m
uaem
desonses@gmail.com para mas comentarios
*/
#ifdef __HIPCC__
#define cuda_SYNCTHREADS() __syncthreads();
#else
#define cuda_SYNCTHREADS()
#endif
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define N 32
/*
calcula el valor aproximado de pi, realizando particiones (entre mas, hay mas aproximacion al valor)
*/
__host__ float func(float valor)
{
return 4 / (1 + powf(valor,2));
}
__global__ void calcula(float *particion, float *funcion, float *sum)
{
//reserva dinamica de memoria compartida en tiempo de ejecucion
extern __shared__ float temporal[];
float add[N];
//float h = (1 - 0) / N;
int id = threadIdx.x;// +blockIdx.x * blockDim.x;
float xi, xim;
float yi, yim;
//printf("%.2f, \n", particion[id]);
xi = particion[id];
xim = particion[id - 1];
yi = funcion[id];
yim = funcion[id - 1];
add[id] = .5f * ((xi - xim) * (yi + yim));
temporal[id] = add[id];
printf("(%.4f - %.4f) * (%.4f + %.4f): %.4f\n", xi, xim, yi, yim, temporal[id]);
cuda_SYNCTHREADS();
//reduccion paralela
int salto = N / 2;
//realizamos log2(N) iteraciones
while (salto)
{
//solo trabajan la mitad de los hilos
if (id < salto)
{
temporal[id] = temporal[id] + temporal[id + salto];
}
//cuda_SYNCTHREADS();
cuda_SYNCTHREADS();
salto = salto / 2;
}
//el hilo 0 escribe el resultado final en la memoria global
if (id == 0)
{
*sum = temporal[id];
//printf("temporal: %.3f\n", *sum);
}
}
int main(int argc, char** argv)
{
float *vector1, *vector2, *resultado;
float *dev_vector1, *dev_vector2, *dev_resultado;
size_t size = N * sizeof(float);
//reserva de memoria en el host
vector1 = (float*)malloc(size);
vector2 = (float*)malloc(size);
resultado = (float*)malloc(size);
//reserva de memoria en el device
hipMalloc((void**)&dev_vector1, size);
hipMalloc((void**)&dev_vector2, size);
hipMalloc((void**)&dev_resultado, size);
// inicializacion de los vectores
for (int i = 0; i < N; i++) {
vector1[i] = (float)i / (N - 1);
vector2[i] = func(vector1[i]);
//printf("xi: %.2f, f(xi): %.2f \n", vector1[i], vector2[i]);
}
//enviar los datos hacia el Device
hipMemcpy(dev_vector1, vector1, size, hipMemcpyHostToDevice);
hipMemcpy(dev_vector2, vector2, size, hipMemcpyHostToDevice);
//cudaMemcpy(dev_resultado, resultado, size, cudaMemcpyHostToDevice);
//lanzamiento del kernel con memoria dinamica compartida
calcula <<<1, N, size>>>(dev_vector1, dev_vector2, dev_resultado);
//recogida de los datos
hipMemcpy(resultado, dev_resultado, size, hipMemcpyDeviceToHost);
printf("pi = %.5f, \n", resultado[0]);
return 0;
}
|
.text
.file "ejercicio10.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4funcf
.LCPI0_0:
.long 0x3f800000 # float 1
.LCPI0_1:
.long 0x40800000 # float 4
.text
.globl _Z4funcf
.p2align 4, 0x90
.type _Z4funcf,@function
_Z4funcf: # @_Z4funcf
.cfi_startproc
# %bb.0:
mulss %xmm0, %xmm0
addss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z4funcf, .Lfunc_end0-_Z4funcf
.cfi_endproc
# -- End function
.globl _Z22__device_stub__calculaPfS_S_ # -- Begin function _Z22__device_stub__calculaPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__calculaPfS_S_,@function
_Z22__device_stub__calculaPfS_S_: # @_Z22__device_stub__calculaPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7calculaPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__calculaPfS_S_, .Lfunc_end1-_Z22__device_stub__calculaPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x41f80000 # float 31
.LCPI2_1:
.long 0x3f800000 # float 1
.LCPI2_2:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %r15
movl $128, %edi
callq malloc
movq %rax, %r14
movl $128, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %eax, %xmm3
divss %xmm0, %xmm3
movss %xmm3, (%r15,%rax,4)
mulss %xmm3, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm4
divss %xmm3, %xmm4
movss %xmm4, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB2_1
# %bb.2:
movq 16(%rsp), %rdi
movl $128, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $128, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7calculaPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calculaPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calculaPfS_S_,@object # @_Z7calculaPfS_S_
.section .rodata,"a",@progbits
.globl _Z7calculaPfS_S_
.p2align 3, 0x0
_Z7calculaPfS_S_:
.quad _Z22__device_stub__calculaPfS_S_
.size _Z7calculaPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "pi = %.5f, \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7calculaPfS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calculaPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calculaPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000157e1_00000000-6_ejercicio10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4funcf
.type _Z4funcf, @function
_Z4funcf:
.LFB2057:
.cfi_startproc
endbr64
mulss %xmm0, %xmm0
addss .LC0(%rip), %xmm0
movss .LC1(%rip), %xmm1
divss %xmm0, %xmm1
movaps %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z4funcf, .-_Z4funcf
.globl _Z30__device_stub__Z7calculaPfS_S_PfS_S_
.type _Z30__device_stub__Z7calculaPfS_S_PfS_S_, @function
_Z30__device_stub__Z7calculaPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7calculaPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z7calculaPfS_S_PfS_S_, .-_Z30__device_stub__Z7calculaPfS_S_PfS_S_
.globl _Z7calculaPfS_S_
.type _Z7calculaPfS_S_, @function
_Z7calculaPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7calculaPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7calculaPfS_S_, .-_Z7calculaPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "pi = %.5f, \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
movl $128, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC2(%rip), %xmm4
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm4, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
mulss %xmm0, %xmm0
addss %xmm3, %xmm0
movaps %xmm2, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L13
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $128, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7calculaPfS_S_PfS_S_
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7calculaPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calculaPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1082130432
.align 4
.LC2:
.long 1106771968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "ejercicio10.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4funcf
.LCPI0_0:
.long 0x3f800000 # float 1
.LCPI0_1:
.long 0x40800000 # float 4
.text
.globl _Z4funcf
.p2align 4, 0x90
.type _Z4funcf,@function
_Z4funcf: # @_Z4funcf
.cfi_startproc
# %bb.0:
mulss %xmm0, %xmm0
addss .LCPI0_0(%rip), %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z4funcf, .Lfunc_end0-_Z4funcf
.cfi_endproc
# -- End function
.globl _Z22__device_stub__calculaPfS_S_ # -- Begin function _Z22__device_stub__calculaPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__calculaPfS_S_,@function
_Z22__device_stub__calculaPfS_S_: # @_Z22__device_stub__calculaPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7calculaPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__calculaPfS_S_, .Lfunc_end1-_Z22__device_stub__calculaPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x41f80000 # float 31
.LCPI2_1:
.long 0x3f800000 # float 1
.LCPI2_2:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %r15
movl $128, %edi
callq malloc
movq %rax, %r14
movl $128, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %eax, %xmm3
divss %xmm0, %xmm3
movss %xmm3, (%r15,%rax,4)
mulss %xmm3, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm4
divss %xmm3, %xmm4
movss %xmm4, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB2_1
# %bb.2:
movq 16(%rsp), %rdi
movl $128, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $128, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7calculaPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calculaPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calculaPfS_S_,@object # @_Z7calculaPfS_S_
.section .rodata,"a",@progbits
.globl _Z7calculaPfS_S_
.p2align 3, 0x0
_Z7calculaPfS_S_:
.quad _Z22__device_stub__calculaPfS_S_
.size _Z7calculaPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "pi = %.5f, \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7calculaPfS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calculaPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calculaPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <unistd.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
__global__ void gpu_sleep(const int sleep_time)
{
int tmp = 0;
for (int i=sleep_time; i<sleep_time; i++)
tmp += i;
printf("GPU job threadId (%d) done, sleep for %d seconds.\n", threadIdx.x, sleep_time);
}
int main(int argc, char **argv)
{
// set up device.
int dev_count;
int dev = 0;
cudaDeviceProp dprop;
CHECK(cudaGetDeviceCount(&dev_count));
CHECK(cudaGetDeviceProperties(&dprop, dev));
printf("There are %d devices in the system. \n", dev_count);
printf("%s start at device %d: %s \n", argv[0], dev, dprop.name);
CHECK(cudaSetDevice(dev));
int sleep_time = 1;
if (argc > 1)
{
sleep_time = atoi(argv[1]);
}
int blocksize = 1;
if (argc > 2)
{
blocksize = atoi(argv[2]);
}
// execution configuration
dim3 block (blocksize);
dim3 grid (1);
// kernel: sleep.
gpu_sleep <<<grid, block>>> (sleep_time);
sleep(sleep_time);
// reset device.
CHECK(cudaDeviceReset());
return EXIT_SUCCESS;
}
|
code for sm_80
Function : _Z9gpu_sleepi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff097624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <unistd.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
__global__ void gpu_sleep(const int sleep_time)
{
int tmp = 0;
for (int i=sleep_time; i<sleep_time; i++)
tmp += i;
printf("GPU job threadId (%d) done, sleep for %d seconds.\n", threadIdx.x, sleep_time);
}
int main(int argc, char **argv)
{
// set up device.
int dev_count;
int dev = 0;
cudaDeviceProp dprop;
CHECK(cudaGetDeviceCount(&dev_count));
CHECK(cudaGetDeviceProperties(&dprop, dev));
printf("There are %d devices in the system. \n", dev_count);
printf("%s start at device %d: %s \n", argv[0], dev, dprop.name);
CHECK(cudaSetDevice(dev));
int sleep_time = 1;
if (argc > 1)
{
sleep_time = atoi(argv[1]);
}
int blocksize = 1;
if (argc > 2)
{
blocksize = atoi(argv[2]);
}
// execution configuration
dim3 block (blocksize);
dim3 grid (1);
// kernel: sleep.
gpu_sleep <<<grid, block>>> (sleep_time);
sleep(sleep_time);
// reset device.
CHECK(cudaDeviceReset());
return EXIT_SUCCESS;
}
|
.file "tmpxft_00165a83_00000000-6_gpuSleep.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9gpu_sleepii
.type _Z27__device_stub__Z9gpu_sleepii, @function
_Z27__device_stub__Z9gpu_sleepii:
.LFB2095:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9gpu_sleepi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z27__device_stub__Z9gpu_sleepii, .-_Z27__device_stub__Z9gpu_sleepii
.globl _Z9gpu_sleepi
.type _Z9gpu_sleepi, @function
_Z9gpu_sleepi:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9gpu_sleepii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z9gpu_sleepi, .-_Z9gpu_sleepi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/hanhiver/CudaBasic/master/first/gpuSleep/gpuSleep.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: %s:%d, "
.LC2:
.string "code: %d, reason: %s\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "There are %d devices in the system. \n"
.section .rodata.str1.1
.LC4:
.string "%s start at device %d: %s \n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1072, %rsp
.cfi_def_cfa_offset 1104
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L22
leaq 32(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L23
movl 4(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq 32(%rsp), %r8
movl $0, %ecx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L24
movl $1, %r12d
movl $1, %eax
cmpl $1, %ebp
jg .L25
.L15:
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L16:
movl %r12d, %edi
call sleep@PLT
call cudaDeviceReset@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %eax, %r12d
movl $34, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movl $35, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl $38, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movl $1, %eax
cmpl $2, %ebp
jle .L15
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L15
.L26:
movl %r12d, %edi
call _Z27__device_stub__Z9gpu_sleepii
jmp .L16
.L27:
movl $62, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9gpu_sleepi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpu_sleepi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <unistd.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
__global__ void gpu_sleep(const int sleep_time)
{
int tmp = 0;
for (int i=sleep_time; i<sleep_time; i++)
tmp += i;
printf("GPU job threadId (%d) done, sleep for %d seconds.\n", threadIdx.x, sleep_time);
}
int main(int argc, char **argv)
{
// set up device.
int dev_count;
int dev = 0;
cudaDeviceProp dprop;
CHECK(cudaGetDeviceCount(&dev_count));
CHECK(cudaGetDeviceProperties(&dprop, dev));
printf("There are %d devices in the system. \n", dev_count);
printf("%s start at device %d: %s \n", argv[0], dev, dprop.name);
CHECK(cudaSetDevice(dev));
int sleep_time = 1;
if (argc > 1)
{
sleep_time = atoi(argv[1]);
}
int blocksize = 1;
if (argc > 2)
{
blocksize = atoi(argv[2]);
}
// execution configuration
dim3 block (blocksize);
dim3 grid (1);
// kernel: sleep.
gpu_sleep <<<grid, block>>> (sleep_time);
sleep(sleep_time);
// reset device.
CHECK(cudaDeviceReset());
return EXIT_SUCCESS;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <unistd.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
__global__ void gpu_sleep(const int sleep_time)
{
int tmp = 0;
for (int i=sleep_time; i<sleep_time; i++)
tmp += i;
printf("GPU job threadId (%d) done, sleep for %d seconds.\n", threadIdx.x, sleep_time);
}
int main(int argc, char **argv)
{
// set up device.
int dev_count;
int dev = 0;
hipDeviceProp_t dprop;
CHECK(hipGetDeviceCount(&dev_count));
CHECK(hipGetDeviceProperties(&dprop, dev));
printf("There are %d devices in the system. \n", dev_count);
printf("%s start at device %d: %s \n", argv[0], dev, dprop.name);
CHECK(hipSetDevice(dev));
int sleep_time = 1;
if (argc > 1)
{
sleep_time = atoi(argv[1]);
}
int blocksize = 1;
if (argc > 2)
{
blocksize = atoi(argv[2]);
}
// execution configuration
dim3 block (blocksize);
dim3 grid (1);
// kernel: sleep.
gpu_sleep <<<grid, block>>> (sleep_time);
sleep(sleep_time);
// reset device.
CHECK(hipDeviceReset());
return EXIT_SUCCESS;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <unistd.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
__global__ void gpu_sleep(const int sleep_time)
{
int tmp = 0;
for (int i=sleep_time; i<sleep_time; i++)
tmp += i;
printf("GPU job threadId (%d) done, sleep for %d seconds.\n", threadIdx.x, sleep_time);
}
int main(int argc, char **argv)
{
// set up device.
int dev_count;
int dev = 0;
hipDeviceProp_t dprop;
CHECK(hipGetDeviceCount(&dev_count));
CHECK(hipGetDeviceProperties(&dprop, dev));
printf("There are %d devices in the system. \n", dev_count);
printf("%s start at device %d: %s \n", argv[0], dev, dprop.name);
CHECK(hipSetDevice(dev));
int sleep_time = 1;
if (argc > 1)
{
sleep_time = atoi(argv[1]);
}
int blocksize = 1;
if (argc > 2)
{
blocksize = atoi(argv[2]);
}
// execution configuration
dim3 block (blocksize);
dim3 grid (1);
// kernel: sleep.
gpu_sleep <<<grid, block>>> (sleep_time);
sleep(sleep_time);
// reset device.
CHECK(hipDeviceReset());
return EXIT_SUCCESS;
}
|
.text
.file "gpuSleep.hip"
.globl _Z24__device_stub__gpu_sleepi # -- Begin function _Z24__device_stub__gpu_sleepi
.p2align 4, 0x90
.type _Z24__device_stub__gpu_sleepi,@function
_Z24__device_stub__gpu_sleepi: # @_Z24__device_stub__gpu_sleepi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9gpu_sleepi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__gpu_sleepi, .Lfunc_end0-_Z24__device_stub__gpu_sleepi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl 8(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq (%r14), %rsi
leaq 72(%rsp), %rcx
movl $.L.str.4, %edi
xorl %edx, %edx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $1, %ebx
cmpl $2, %ebp
jl .LBB1_9
# %bb.8:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB1_9:
movabsq $4294967297, %r15 # imm = 0x100000001
movq %r15, %rdx
cmpl $3, %ebp
jl .LBB1_11
# %bb.10:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %eax
leaq (%r15,%rax), %rdx
decq %rdx
.LBB1_11:
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movl %ebx, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9gpu_sleepi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
movl %ebx, %edi
callq sleep
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_14
# %bb.15:
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1584
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $34, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $35, %ecx
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $38, %ecx
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $62, %ecx
.LBB1_2:
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_sleepi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpu_sleepi,@object # @_Z9gpu_sleepi
.section .rodata,"a",@progbits
.globl _Z9gpu_sleepi
.p2align 3, 0x0
_Z9gpu_sleepi:
.quad _Z24__device_stub__gpu_sleepi
.size _Z9gpu_sleepi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s:%d, "
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/hanhiver/CudaBasic/master/first/gpuSleep/gpuSleep.hip"
.size .L.str.1, 111
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "code: %d, reason: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "There are %d devices in the system. \n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s start at device %d: %s \n"
.size .L.str.4, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpu_sleepi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpu_sleepi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpu_sleepi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00165a83_00000000-6_gpuSleep.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9gpu_sleepii
.type _Z27__device_stub__Z9gpu_sleepii, @function
_Z27__device_stub__Z9gpu_sleepii:
.LFB2095:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9gpu_sleepi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z27__device_stub__Z9gpu_sleepii, .-_Z27__device_stub__Z9gpu_sleepii
.globl _Z9gpu_sleepi
.type _Z9gpu_sleepi, @function
_Z9gpu_sleepi:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9gpu_sleepii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z9gpu_sleepi, .-_Z9gpu_sleepi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/hanhiver/CudaBasic/master/first/gpuSleep/gpuSleep.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: %s:%d, "
.LC2:
.string "code: %d, reason: %s\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "There are %d devices in the system. \n"
.section .rodata.str1.1
.LC4:
.string "%s start at device %d: %s \n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1072, %rsp
.cfi_def_cfa_offset 1104
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L22
leaq 32(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L23
movl 4(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq 32(%rsp), %r8
movl $0, %ecx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L24
movl $1, %r12d
movl $1, %eax
cmpl $1, %ebp
jg .L25
.L15:
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L16:
movl %r12d, %edi
call sleep@PLT
call cudaDeviceReset@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %eax, %r12d
movl $34, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movl $35, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl $38, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movl $1, %eax
cmpl $2, %ebp
jle .L15
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L15
.L26:
movl %r12d, %edi
call _Z27__device_stub__Z9gpu_sleepii
jmp .L16
.L27:
movl $62, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9gpu_sleepi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpu_sleepi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "gpuSleep.hip"
.globl _Z24__device_stub__gpu_sleepi # -- Begin function _Z24__device_stub__gpu_sleepi
.p2align 4, 0x90
.type _Z24__device_stub__gpu_sleepi,@function
_Z24__device_stub__gpu_sleepi: # @_Z24__device_stub__gpu_sleepi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9gpu_sleepi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__gpu_sleepi, .Lfunc_end0-_Z24__device_stub__gpu_sleepi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl 8(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq (%r14), %rsi
leaq 72(%rsp), %rcx
movl $.L.str.4, %edi
xorl %edx, %edx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $1, %ebx
cmpl $2, %ebp
jl .LBB1_9
# %bb.8:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB1_9:
movabsq $4294967297, %r15 # imm = 0x100000001
movq %r15, %rdx
cmpl $3, %ebp
jl .LBB1_11
# %bb.10:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %eax
leaq (%r15,%rax), %rdx
decq %rdx
.LBB1_11:
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movl %ebx, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9gpu_sleepi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
movl %ebx, %edi
callq sleep
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_14
# %bb.15:
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1584
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $34, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $35, %ecx
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $38, %ecx
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $62, %ecx
.LBB1_2:
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_sleepi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpu_sleepi,@object # @_Z9gpu_sleepi
.section .rodata,"a",@progbits
.globl _Z9gpu_sleepi
.p2align 3, 0x0
_Z9gpu_sleepi:
.quad _Z24__device_stub__gpu_sleepi
.size _Z9gpu_sleepi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s:%d, "
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/hanhiver/CudaBasic/master/first/gpuSleep/gpuSleep.hip"
.size .L.str.1, 111
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "code: %d, reason: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "There are %d devices in the system. \n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s start at device %d: %s \n"
.size .L.str.4, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpu_sleepi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpu_sleepi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpu_sleepi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
#define BIN_WIDTH 0.25
#define BLOCK_DIM 256
#define COVERAGE 180
#define LINE_LENGTH 30
#define BINS_TOTAL (COVERAGE * (int)(1 / BIN_WIDTH))
typedef struct Galaxy
{
float declination;
float declination_cos;
float declination_sin;
float right_ascension;
} Galaxy;
__global__ void measure_galaxy_distribution(int *DD_histogram, int *DR_histogram, int *RR_histogram, float *distribution, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
if (RR_histogram[i] == 0)
continue;
distribution[i] = (DD_histogram[i] - 2.0f * DR_histogram[i] + RR_histogram[i]) / RR_histogram[i];
}
}
|
.file "tmpxft_00169d0f_00000000-6_measure_galaxy_distribution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi
.type _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi, @function
_Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27measure_galaxy_distributionPiS_S_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi, .-_Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi
.globl _Z27measure_galaxy_distributionPiS_S_Pfi
.type _Z27measure_galaxy_distributionPiS_S_Pfi, @function
_Z27measure_galaxy_distributionPiS_S_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27measure_galaxy_distributionPiS_S_Pfi, .-_Z27measure_galaxy_distributionPiS_S_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27measure_galaxy_distributionPiS_S_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27measure_galaxy_distributionPiS_S_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
#define BIN_WIDTH 0.25
#define BLOCK_DIM 256
#define COVERAGE 180
#define LINE_LENGTH 30
#define BINS_TOTAL (COVERAGE * (int)(1 / BIN_WIDTH))
typedef struct Galaxy
{
float declination;
float declination_cos;
float declination_sin;
float right_ascension;
} Galaxy;
__global__ void measure_galaxy_distribution(int *DD_histogram, int *DR_histogram, int *RR_histogram, float *distribution, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
if (RR_histogram[i] == 0)
continue;
distribution[i] = (DD_histogram[i] - 2.0f * DR_histogram[i] + RR_histogram[i]) / RR_histogram[i];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
#define BIN_WIDTH 0.25
#define BLOCK_DIM 256
#define COVERAGE 180
#define LINE_LENGTH 30
#define BINS_TOTAL (COVERAGE * (int)(1 / BIN_WIDTH))
typedef struct Galaxy
{
float declination;
float declination_cos;
float declination_sin;
float right_ascension;
} Galaxy;
__global__ void measure_galaxy_distribution(int *DD_histogram, int *DR_histogram, int *RR_histogram, float *distribution, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
if (RR_histogram[i] == 0)
continue;
distribution[i] = (DD_histogram[i] - 2.0f * DR_histogram[i] + RR_histogram[i]) / RR_histogram[i];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
#define BIN_WIDTH 0.25
#define BLOCK_DIM 256
#define COVERAGE 180
#define LINE_LENGTH 30
#define BINS_TOTAL (COVERAGE * (int)(1 / BIN_WIDTH))
typedef struct Galaxy
{
float declination;
float declination_cos;
float declination_sin;
float right_ascension;
} Galaxy;
__global__ void measure_galaxy_distribution(int *DD_histogram, int *DR_histogram, int *RR_histogram, float *distribution, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
if (RR_histogram[i] == 0)
continue;
distribution[i] = (DD_histogram[i] - 2.0f * DR_histogram[i] + RR_histogram[i]) / RR_histogram[i];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27measure_galaxy_distributionPiS_S_Pfi
.globl _Z27measure_galaxy_distributionPiS_S_Pfi
.p2align 8
.type _Z27measure_galaxy_distributionPiS_S_Pfi,@function
_Z27measure_galaxy_distributionPiS_S_Pfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s14, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s14, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[2:3], 0x0
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s12
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v2, s0, v2, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s13, v3, s0
v_cmp_le_i32_e32 vcc_lo, s14, v1
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cvt_f32_i32_e32 v0, v0
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v4, v4
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, -2.0, v5
v_add_f32_e32 v4, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v0, v0, v4
v_div_scale_f32 v8, vcc_lo, v4, v0, v4
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v5, v0, v4
v_add_co_u32 v4, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
global_store_b32 v[4:5], v0, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27measure_galaxy_distributionPiS_S_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27measure_galaxy_distributionPiS_S_Pfi, .Lfunc_end0-_Z27measure_galaxy_distributionPiS_S_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27measure_galaxy_distributionPiS_S_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27measure_galaxy_distributionPiS_S_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
#define BIN_WIDTH 0.25
#define BLOCK_DIM 256
#define COVERAGE 180
#define LINE_LENGTH 30
#define BINS_TOTAL (COVERAGE * (int)(1 / BIN_WIDTH))
typedef struct Galaxy
{
float declination;
float declination_cos;
float declination_sin;
float right_ascension;
} Galaxy;
__global__ void measure_galaxy_distribution(int *DD_histogram, int *DR_histogram, int *RR_histogram, float *distribution, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
if (RR_histogram[i] == 0)
continue;
distribution[i] = (DD_histogram[i] - 2.0f * DR_histogram[i] + RR_histogram[i]) / RR_histogram[i];
}
}
|
.text
.file "measure_galaxy_distribution.hip"
.globl _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi # -- Begin function _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.p2align 4, 0x90
.type _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi,@function
_Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi: # @_Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27measure_galaxy_distributionPiS_S_Pfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi, .Lfunc_end0-_Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27measure_galaxy_distributionPiS_S_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27measure_galaxy_distributionPiS_S_Pfi,@object # @_Z27measure_galaxy_distributionPiS_S_Pfi
.section .rodata,"a",@progbits
.globl _Z27measure_galaxy_distributionPiS_S_Pfi
.p2align 3, 0x0
_Z27measure_galaxy_distributionPiS_S_Pfi:
.quad _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.size _Z27measure_galaxy_distributionPiS_S_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27measure_galaxy_distributionPiS_S_Pfi"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27measure_galaxy_distributionPiS_S_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00169d0f_00000000-6_measure_galaxy_distribution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi
.type _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi, @function
_Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27measure_galaxy_distributionPiS_S_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi, .-_Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi
.globl _Z27measure_galaxy_distributionPiS_S_Pfi
.type _Z27measure_galaxy_distributionPiS_S_Pfi, @function
_Z27measure_galaxy_distributionPiS_S_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z27measure_galaxy_distributionPiS_S_PfiPiS_S_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27measure_galaxy_distributionPiS_S_Pfi, .-_Z27measure_galaxy_distributionPiS_S_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27measure_galaxy_distributionPiS_S_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27measure_galaxy_distributionPiS_S_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "measure_galaxy_distribution.hip"
.globl _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi # -- Begin function _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.p2align 4, 0x90
.type _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi,@function
_Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi: # @_Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27measure_galaxy_distributionPiS_S_Pfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi, .Lfunc_end0-_Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27measure_galaxy_distributionPiS_S_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27measure_galaxy_distributionPiS_S_Pfi,@object # @_Z27measure_galaxy_distributionPiS_S_Pfi
.section .rodata,"a",@progbits
.globl _Z27measure_galaxy_distributionPiS_S_Pfi
.p2align 3, 0x0
_Z27measure_galaxy_distributionPiS_S_Pfi:
.quad _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.size _Z27measure_galaxy_distributionPiS_S_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27measure_galaxy_distributionPiS_S_Pfi"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__measure_galaxy_distributionPiS_S_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27measure_galaxy_distributionPiS_S_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void kExtractPatches(float* images, float* patches, float* indices, float* width_offset, float* height_offset, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
const unsigned long idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned long numThreads = blockDim.x * gridDim.x;
const unsigned long total_pixels = patch_width * patch_height * num_colors * num_images;
unsigned long ind, pos;
unsigned long image_id, dest_row, dest_col, color, source_row, source_col;
for (unsigned long i = idx; i < total_pixels; i += numThreads) {
ind = i;
image_id = ind % num_images; ind /= num_images;
dest_col = ind % patch_width; ind /= patch_width;
dest_row = ind % patch_height; ind /= patch_height;
color = ind % num_colors;
source_row = int(height_offset[image_id]) + dest_row;
source_col = int(width_offset[image_id]) + dest_col;
pos = img_width * img_height * num_colors * (int)indices[image_id] + img_width * img_height * color + img_width * source_row + source_col;
patches[i] = images[pos];
}
}
|
.file "tmpxft_000b581e_00000000-6_kExtractPatches.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.type _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, @function
_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kExtractPatchesPfS_S_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, .-_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.globl _Z15kExtractPatchesPfS_S_S_S_iiiiii
.type _Z15kExtractPatchesPfS_S_S_S_iiiiii, @function
_Z15kExtractPatchesPfS_S_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15kExtractPatchesPfS_S_S_S_iiiiii, .-_Z15kExtractPatchesPfS_S_S_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15kExtractPatchesPfS_S_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kExtractPatchesPfS_S_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void kExtractPatches(float* images, float* patches, float* indices, float* width_offset, float* height_offset, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
const unsigned long idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned long numThreads = blockDim.x * gridDim.x;
const unsigned long total_pixels = patch_width * patch_height * num_colors * num_images;
unsigned long ind, pos;
unsigned long image_id, dest_row, dest_col, color, source_row, source_col;
for (unsigned long i = idx; i < total_pixels; i += numThreads) {
ind = i;
image_id = ind % num_images; ind /= num_images;
dest_col = ind % patch_width; ind /= patch_width;
dest_row = ind % patch_height; ind /= patch_height;
color = ind % num_colors;
source_row = int(height_offset[image_id]) + dest_row;
source_col = int(width_offset[image_id]) + dest_col;
pos = img_width * img_height * num_colors * (int)indices[image_id] + img_width * img_height * color + img_width * source_row + source_col;
patches[i] = images[pos];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExtractPatches(float* images, float* patches, float* indices, float* width_offset, float* height_offset, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
const unsigned long idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned long numThreads = blockDim.x * gridDim.x;
const unsigned long total_pixels = patch_width * patch_height * num_colors * num_images;
unsigned long ind, pos;
unsigned long image_id, dest_row, dest_col, color, source_row, source_col;
for (unsigned long i = idx; i < total_pixels; i += numThreads) {
ind = i;
image_id = ind % num_images; ind /= num_images;
dest_col = ind % patch_width; ind /= patch_width;
dest_row = ind % patch_height; ind /= patch_height;
color = ind % num_colors;
source_row = int(height_offset[image_id]) + dest_row;
source_col = int(width_offset[image_id]) + dest_col;
pos = img_width * img_height * num_colors * (int)indices[image_id] + img_width * img_height * color + img_width * source_row + source_col;
patches[i] = images[pos];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExtractPatches(float* images, float* patches, float* indices, float* width_offset, float* height_offset, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
const unsigned long idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned long numThreads = blockDim.x * gridDim.x;
const unsigned long total_pixels = patch_width * patch_height * num_colors * num_images;
unsigned long ind, pos;
unsigned long image_id, dest_row, dest_col, color, source_row, source_col;
for (unsigned long i = idx; i < total_pixels; i += numThreads) {
ind = i;
image_id = ind % num_images; ind /= num_images;
dest_col = ind % patch_width; ind /= patch_width;
dest_row = ind % patch_height; ind /= patch_height;
color = ind % num_colors;
source_row = int(height_offset[image_id]) + dest_row;
source_col = int(width_offset[image_id]) + dest_col;
pos = img_width * img_height * num_colors * (int)indices[image_id] + img_width * img_height * color + img_width * source_row + source_col;
patches[i] = images[pos];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kExtractPatchesPfS_S_S_S_iiiiii
.globl _Z15kExtractPatchesPfS_S_S_S_iiiiii
.p2align 8
.type _Z15kExtractPatchesPfS_S_S_S_iiiiii,@function
_Z15kExtractPatchesPfS_S_S_S_iiiiii:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s18, s[0:1], 0x28
s_load_b64 s[16:17], s[0:1], 0x34
s_load_b32 s19, s[0:1], 0x3c
v_mov_b32_e32 v1, 0
s_add_u32 s4, s0, 64
s_addc_u32 s5, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s14, v[0:1]
s_mul_i32 s2, s16, s18
v_mov_b32_e32 v4, v1
s_mul_i32 s2, s2, s17
s_mul_i32 s2, s2, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_19
s_ashr_i32 s20, s18, 31
v_cvt_f32_u32_e32 v0, s18
v_cvt_f32_u32_e32 v2, s20
s_load_b64 s[26:27], s[0:1], 0x2c
s_load_b32 s25, s[4:5], 0x0
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x20
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_mov_b32 s15, 0
v_fmac_f32_e32 v0, 0x4f800000, v2
s_ashr_i32 s1, s16, 31
s_ashr_i32 s21, s17, 31
s_ashr_i32 s22, s19, 31
s_sub_i32 s28, 0, s18
v_rcp_f32_e32 v0, v0
s_mov_b32 s29, s15
s_waitcnt lgkmcnt(0)
s_ashr_i32 s23, s26, 31
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, 0x2f800000, v0
s_mul_i32 s14, s25, s14
s_mul_i32 s25, s27, s26
s_mov_b32 s24, s26
s_mul_i32 s26, s25, s19
v_trunc_f32_e32 v2, v2
s_ashr_i32 s27, s25, 31
s_lshl_b64 s[6:7], s[14:15], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v0, 0xcf800000, v2
v_cvt_u32_f32_e32 v15, v2
v_cvt_u32_f32_e32 v0, v0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_mul_lo_u32 v2, v8, s18
v_mul_lo_u32 v18, v7, s20
v_mad_u64_u32 v[16:17], null, v7, s18, 0
v_mul_lo_u32 v22, v12, s17
v_mul_lo_u32 v23, v11, s21
v_mul_lo_u32 v24, v10, s16
v_mul_lo_u32 v25, v9, s1
v_mul_lo_u32 v26, v13, s27
v_mul_lo_u32 v14, v14, s25
v_add3_u32 v2, v17, v18, v2
v_sub_co_u32 v16, vcc_lo, v3, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_co_ci_u32_e32 v17, vcc_lo, v4, v2, vcc_lo
v_lshlrev_b64 v[16:17], 2, v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v19, vcc_lo, s13, v17, vcc_lo
v_add_co_u32 v20, vcc_lo, s8, v16
v_add_co_ci_u32_e32 v21, vcc_lo, s9, v17, vcc_lo
global_load_b32 v2, v[18:19], off
global_load_b32 v20, v[20:21], off
v_add_co_u32 v16, vcc_lo, s10, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s11, v17, vcc_lo
v_mad_u64_u32 v[18:19], null, v13, s25, 0
global_load_b32 v21, v[16:17], off
v_mad_u64_u32 v[16:17], null, v11, s17, 0
v_mad_u64_u32 v[11:12], null, v9, s16, 0
v_add3_u32 v19, v19, v26, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add3_u32 v13, v17, v23, v22
v_sub_co_u32 v9, vcc_lo, v9, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v17, v12, v25, v24
v_sub_co_ci_u32_e32 v10, vcc_lo, v10, v13, vcc_lo
s_waitcnt vmcnt(2)
v_cvt_i32_f32_e32 v2, v2
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v12, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v13, 31, v2
v_add_co_u32 v2, vcc_lo, v9, v2
v_mul_lo_u32 v9, s26, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, v10, v13, vcc_lo
v_mul_lo_u32 v14, v2, s23
v_mad_u64_u32 v[12:13], null, v2, s24, 0
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v2, v10, s24
v_sub_co_u32 v7, vcc_lo, v7, v11
v_sub_co_ci_u32_e32 v8, vcc_lo, v8, v17, vcc_lo
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[16:17], 2, v[18:19]
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v11, v21
v_add3_u32 v13, v13, v14, v2
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v2, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v17, vcc_lo
v_lshlrev_b64 v[13:14], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, v9
v_add_co_ci_u32_e32 v9, vcc_lo, v16, v10, vcc_lo
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, v13
v_add_co_ci_u32_e32 v13, vcc_lo, v9, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[11:12]
v_add_co_u32 v2, vcc_lo, v2, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, v13, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, v2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s14
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
global_load_b32 v2, v[7:8], off
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s29, vcc_lo, s29
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off
v_add_co_u32 v5, s0, v5, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_19
.LBB0_3:
v_or_b32_e32 v2, s20, v4
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u64_e32 0, v[1:2]
s_xor_b32 s30, exec_lo, s0
s_cbranch_execz .LBB0_5
s_sub_u32 s0, 0, s18
s_subb_u32 s31, 0, s20
v_mul_hi_u32 v2, s0, v0
v_mul_lo_u32 v7, s0, v15
v_mul_lo_u32 v8, s31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v7
v_mul_lo_u32 v7, s0, v0
v_add_nc_u32_e32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v2
v_mul_hi_u32 v10, v0, v2
v_mul_hi_u32 v11, v15, v7
v_mul_lo_u32 v7, v15, v7
v_mul_hi_u32 v12, v15, v2
v_mul_lo_u32 v2, v15, v2
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v7, v2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, v15, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v8, s0, v2
v_mul_lo_u32 v10, s31, v2
v_mul_lo_u32 v9, s0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v8, v9
v_mul_lo_u32 v9, s0, v2
v_add_nc_u32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v2, v9
v_mul_lo_u32 v11, v2, v8
v_mul_hi_u32 v12, v2, v8
v_mul_hi_u32 v13, v7, v9
v_mul_lo_u32 v9, v7, v9
v_mul_hi_u32 v14, v7, v8
v_mul_lo_u32 v8, v7, v8
v_add_co_u32 v10, vcc_lo, v10, v11
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v8
v_add_co_ci_u32_e32 v13, vcc_lo, v7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v14, v3, v2
v_mad_u64_u32 v[9:10], null, v4, v2, 0
v_mad_u64_u32 v[7:8], null, v3, v13, 0
v_mad_u64_u32 v[11:12], null, v4, v13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v14, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v9
v_add_co_ci_u32_e32 v2, vcc_lo, v7, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v11
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v10, s20, v2
v_mad_u64_u32 v[7:8], null, s18, v2, 0
v_mul_lo_u32 v11, s18, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v7, vcc_lo, v3, v7
v_add3_u32 v8, v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v4, v8
v_subrev_co_ci_u32_e64 v10, s0, s20, v10, vcc_lo
v_add_co_u32 v11, s0, v2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v12, s0, 0, v9, s0
v_sub_co_u32 v13, s0, v7, s18
v_sub_co_ci_u32_e32 v8, vcc_lo, v4, v8, vcc_lo
v_subrev_co_ci_u32_e64 v10, s0, 0, v10, s0
v_cmp_le_u32_e32 vcc_lo, s18, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s0, s20, v8
v_cndmask_b32_e64 v13, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s20, v10
v_cndmask_b32_e64 v14, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s18, v7
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s20, v8
v_cndmask_b32_e64 v16, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s20, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v16, v7, s0
v_cndmask_b32_e32 v10, v14, v13, vcc_lo
v_add_co_u32 v13, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v9, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v14, v12, vcc_lo
v_cndmask_b32_e32 v10, v13, v11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v7, v2, v10 :: v_dual_cndmask_b32 v8, v9, v8
.LBB0_5:
s_and_not1_saveexec_b32 s0, s30
s_cbranch_execz .LBB0_7
v_cvt_f32_u32_e32 v2, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, s28, v2
v_mul_hi_u32 v7, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v7
v_mul_hi_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v2, s18
v_add_nc_u32_e32 v8, 1, v2
v_sub_nc_u32_e32 v7, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s18, v7
v_cmp_le_u32_e32 vcc_lo, s18, v7
v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s18, v7
v_add_nc_u32_e32 v8, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v7, v2, v8 :: v_dual_mov_b32 v8, v1
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, s1, v8
s_mov_b32 s0, exec_lo
v_cmpx_ne_u64_e32 0, v[1:2]
s_xor_b32 s30, exec_lo, s0
s_cbranch_execz .LBB0_9
v_cvt_f32_u32_e32 v2, s16
v_cvt_f32_u32_e32 v9, s1
s_sub_u32 s0, 0, s16
s_subb_u32 s31, 0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0x4f800000, v9
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, 0x2f800000, v2
v_trunc_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, 0xcf800000, v9
v_cvt_u32_f32_e32 v9, v9
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, s0, v9
v_mul_hi_u32 v11, s0, v2
v_mul_lo_u32 v12, s31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v11, v10
v_mul_lo_u32 v11, s0, v2
v_add_nc_u32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v12, v2, v11
v_mul_lo_u32 v13, v2, v10
v_mul_hi_u32 v14, v2, v10
v_mul_hi_u32 v16, v9, v11
v_mul_lo_u32 v11, v9, v11
v_mul_hi_u32 v17, v9, v10
v_mul_lo_u32 v10, v9, v10
v_add_co_u32 v12, vcc_lo, v12, v13
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, v12, v11
v_add_co_ci_u32_e32 v11, vcc_lo, v13, v16, vcc_lo
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v10
v_add_co_ci_u32_e32 v9, vcc_lo, v9, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, s0, v2
v_mul_lo_u32 v12, s31, v2
v_mul_lo_u32 v11, s0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v10, v11
v_mul_lo_u32 v11, s0, v2
v_add_nc_u32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v12, v2, v11
v_mul_lo_u32 v13, v2, v10
v_mul_hi_u32 v14, v2, v10
v_mul_hi_u32 v16, v9, v11
v_mul_lo_u32 v11, v9, v11
v_mul_hi_u32 v17, v9, v10
v_mul_lo_u32 v10, v9, v10
v_add_co_u32 v12, vcc_lo, v12, v13
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, v12, v11
v_add_co_ci_u32_e32 v11, vcc_lo, v13, v16, vcc_lo
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v10
v_add_co_ci_u32_e32 v16, vcc_lo, v9, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v17, v7, v2
v_mad_u64_u32 v[11:12], null, v8, v2, 0
v_mad_u64_u32 v[9:10], null, v7, v16, 0
v_mad_u64_u32 v[13:14], null, v8, v16, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v17, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v11
v_add_co_ci_u32_e32 v2, vcc_lo, v9, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v13
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v12, s1, v2
v_mad_u64_u32 v[9:10], null, s16, v2, 0
v_mul_lo_u32 v13, s16, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v9, vcc_lo, v7, v9
v_add3_u32 v10, v10, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v12, v8, v10
v_subrev_co_ci_u32_e64 v12, s0, s1, v12, vcc_lo
v_add_co_u32 v13, s0, v2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v14, s0, 0, v11, s0
v_sub_co_u32 v16, s0, v9, s16
v_sub_co_ci_u32_e32 v10, vcc_lo, v8, v10, vcc_lo
v_subrev_co_ci_u32_e64 v12, s0, 0, v12, s0
v_cmp_le_u32_e32 vcc_lo, s16, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s0, s1, v10
v_cndmask_b32_e64 v16, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s1, v12
v_cndmask_b32_e64 v17, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s16, v9
v_cndmask_b32_e64 v9, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s1, v10
v_cndmask_b32_e64 v18, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v18, v9, s0
v_cndmask_b32_e32 v12, v17, v16, vcc_lo
v_add_co_u32 v16, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v10, v17, v14, vcc_lo
v_cndmask_b32_e32 v12, v16, v13, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v9, v2, v12 :: v_dual_cndmask_b32 v10, v11, v10
.LBB0_9:
s_and_not1_saveexec_b32 s0, s30
s_cbranch_execz .LBB0_11
v_cvt_f32_u32_e32 v2, s16
s_sub_i32 s30, 0, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, s30, v2
v_mul_hi_u32 v9, v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v9
v_mul_hi_u32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v9, v2, s16
v_add_nc_u32_e32 v10, 1, v2
v_sub_nc_u32_e32 v9, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v11, s16, v9
v_cmp_le_u32_e32 vcc_lo, s16, v9
v_dual_cndmask_b32 v9, v9, v11 :: v_dual_cndmask_b32 v2, v2, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s16, v9
v_add_nc_u32_e32 v10, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v9, v2, v10 :: v_dual_mov_b32 v10, v1
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, s21, v10
s_mov_b32 s0, exec_lo
v_cmpx_ne_u64_e32 0, v[1:2]
s_xor_b32 s30, exec_lo, s0
s_cbranch_execz .LBB0_13
v_cvt_f32_u32_e32 v2, s17
v_cvt_f32_u32_e32 v11, s21
s_sub_u32 s0, 0, s17
s_subb_u32 s31, 0, s21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0x4f800000, v11
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x2f800000, v2
v_trunc_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, 0xcf800000, v11
v_cvt_u32_f32_e32 v11, v11
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v12, s0, v11
v_mul_hi_u32 v13, s0, v2
v_mul_lo_u32 v14, s31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v13, v12
v_mul_lo_u32 v13, s0, v2
v_add_nc_u32_e32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v14, v2, v13
v_mul_lo_u32 v16, v2, v12
v_mul_hi_u32 v17, v2, v12
v_mul_hi_u32 v18, v11, v13
v_mul_lo_u32 v13, v11, v13
v_mul_hi_u32 v19, v11, v12
v_mul_lo_u32 v12, v11, v12
v_add_co_u32 v14, vcc_lo, v14, v16
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, v14, v13
v_add_co_ci_u32_e32 v13, vcc_lo, v16, v18, vcc_lo
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v13, v12
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v11, vcc_lo, v11, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v12, s0, v2
v_mul_lo_u32 v14, s31, v2
v_mul_lo_u32 v13, s0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v12, v13
v_mul_lo_u32 v13, s0, v2
v_add_nc_u32_e32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v14, v2, v13
v_mul_lo_u32 v16, v2, v12
v_mul_hi_u32 v17, v2, v12
v_mul_hi_u32 v18, v11, v13
v_mul_lo_u32 v13, v11, v13
v_mul_hi_u32 v19, v11, v12
v_mul_lo_u32 v12, v11, v12
v_add_co_u32 v14, vcc_lo, v14, v16
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, v14, v13
v_add_co_ci_u32_e32 v13, vcc_lo, v16, v18, vcc_lo
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v13, v12
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v18, vcc_lo, v11, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v19, v9, v2
v_mad_u64_u32 v[13:14], null, v10, v2, 0
v_mad_u64_u32 v[11:12], null, v9, v18, 0
v_mad_u64_u32 v[16:17], null, v10, v18, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v19, v11
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v13
v_add_co_ci_u32_e32 v2, vcc_lo, v11, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v16
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v14, s21, v2
v_mad_u64_u32 v[11:12], null, s17, v2, 0
v_mul_lo_u32 v16, s17, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v11, vcc_lo, v9, v11
v_add3_u32 v12, v12, v16, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, v10, v12
v_subrev_co_ci_u32_e64 v14, s0, s21, v14, vcc_lo
v_add_co_u32 v16, s0, v2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v17, s0, 0, v13, s0
v_sub_co_u32 v18, s0, v11, s17
v_sub_co_ci_u32_e32 v12, vcc_lo, v10, v12, vcc_lo
v_subrev_co_ci_u32_e64 v14, s0, 0, v14, s0
v_cmp_le_u32_e32 vcc_lo, s17, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s0, s21, v12
v_cndmask_b32_e64 v18, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s21, v14
v_cndmask_b32_e64 v19, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s17, v11
v_cndmask_b32_e64 v11, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s21, v12
v_cndmask_b32_e64 v20, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s21, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v11, v20, v11, s0
v_cndmask_b32_e32 v14, v19, v18, vcc_lo
v_add_co_u32 v18, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v13, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v12, v19, v17, vcc_lo
v_cndmask_b32_e32 v14, v18, v16, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v11
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v11, v2, v14 :: v_dual_cndmask_b32 v12, v13, v12
.LBB0_13:
s_and_not1_saveexec_b32 s0, s30
s_cbranch_execz .LBB0_15
v_cvt_f32_u32_e32 v2, s17
s_sub_i32 s30, 0, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v11, s30, v2
v_mul_hi_u32 v11, v2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v11
v_mul_hi_u32 v2, v9, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v11, v2, s17
v_add_nc_u32_e32 v12, 1, v2
v_sub_nc_u32_e32 v11, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s17, v11
v_cmp_le_u32_e32 vcc_lo, s17, v11
v_dual_cndmask_b32 v11, v11, v13 :: v_dual_cndmask_b32 v2, v2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s17, v11
v_add_nc_u32_e32 v12, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v11, v2, v12 :: v_dual_mov_b32 v12, v1
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, s22, v12
s_mov_b32 s0, exec_lo
v_cmpx_ne_u64_e32 0, v[1:2]
s_xor_b32 s30, exec_lo, s0
s_cbranch_execz .LBB0_17
v_cvt_f32_u32_e32 v2, s19
v_cvt_f32_u32_e32 v13, s22
s_sub_u32 s0, 0, s19
s_subb_u32 s31, 0, s22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0x4f800000, v13
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, 0x2f800000, v2
v_trunc_f32_e32 v13, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, 0xcf800000, v13
v_cvt_u32_f32_e32 v13, v13
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v14, s0, v13
v_mul_hi_u32 v16, s0, v2
v_mul_lo_u32 v17, s31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v16, v14
v_mul_lo_u32 v16, s0, v2
v_add_nc_u32_e32 v14, v14, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v17, v2, v16
v_mul_lo_u32 v18, v2, v14
v_mul_hi_u32 v19, v2, v14
v_mul_hi_u32 v20, v13, v16
v_mul_lo_u32 v16, v13, v16
v_mul_hi_u32 v21, v13, v14
v_mul_lo_u32 v14, v13, v14
v_add_co_u32 v17, vcc_lo, v17, v18
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, v17, v16
v_add_co_ci_u32_e32 v16, vcc_lo, v18, v20, vcc_lo
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v21, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v16, v14
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v14
v_add_co_ci_u32_e32 v13, vcc_lo, v13, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v14, s0, v2
v_mul_lo_u32 v17, s31, v2
v_mul_lo_u32 v16, s0, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v16
v_mul_lo_u32 v16, s0, v2
v_add_nc_u32_e32 v14, v14, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v17, v2, v16
v_mul_lo_u32 v18, v2, v14
v_mul_hi_u32 v19, v2, v14
v_mul_hi_u32 v20, v13, v16
v_mul_lo_u32 v16, v13, v16
v_mul_hi_u32 v21, v13, v14
v_mul_lo_u32 v14, v13, v14
v_add_co_u32 v17, vcc_lo, v17, v18
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, v17, v16
v_add_co_ci_u32_e32 v16, vcc_lo, v18, v20, vcc_lo
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v21, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v16, v14
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v14
v_add_co_ci_u32_e32 v20, vcc_lo, v13, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v21, v11, v2
v_mad_u64_u32 v[16:17], null, v12, v2, 0
v_mad_u64_u32 v[13:14], null, v11, v20, 0
v_mad_u64_u32 v[18:19], null, v12, v20, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v21, v13
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v16
v_add_co_ci_u32_e32 v2, vcc_lo, v13, v17, vcc_lo
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v18
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v17, s22, v2
v_mad_u64_u32 v[13:14], null, s19, v2, 0
v_mul_lo_u32 v2, s19, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v13, vcc_lo, v11, v13
v_add3_u32 v2, v14, v2, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, v12, v2
v_subrev_co_ci_u32_e64 v14, s0, s22, v14, vcc_lo
v_sub_co_ci_u32_e32 v2, vcc_lo, v12, v2, vcc_lo
v_sub_co_u32 v16, vcc_lo, v13, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v17, s0, 0, v14, vcc_lo
v_cmp_le_u32_e64 s0, s19, v13
v_subrev_co_ci_u32_e32 v14, vcc_lo, s22, v14, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s22, v2
v_cndmask_b32_e64 v18, 0, -1, s0
v_cmp_le_u32_e64 s0, s19, v16
v_cndmask_b32_e64 v21, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s22, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v19, 0, -1, s0
v_cmp_le_u32_e64 s0, s22, v17
v_cndmask_b32_e64 v20, 0, -1, s0
v_cmp_eq_u32_e64 s0, s22, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v19, v20, v19, vcc_lo
v_sub_co_u32 v20, vcc_lo, v16, s19
v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v19
v_cndmask_b32_e64 v18, v21, v18, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v14, v17, v14, vcc_lo
v_cndmask_b32_e32 v16, v16, v20, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v18
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v14, v2, v14 :: v_dual_cndmask_b32 v13, v13, v16
.LBB0_17:
s_and_not1_saveexec_b32 s0, s30
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v2, s19
s_sub_i32 s30, 0, s19
v_mov_b32_e32 v14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, s30, v2
v_mul_hi_u32 v13, v2, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v13
v_mul_hi_u32 v2, v11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s19
v_sub_nc_u32_e32 v2, v11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s19, v2
v_cmp_le_u32_e32 vcc_lo, s19, v2
v_cndmask_b32_e32 v2, v2, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s19, v2
v_cmp_le_u32_e32 vcc_lo, s19, v2
v_cndmask_b32_e32 v13, v2, v13, vcc_lo
s_branch .LBB0_2
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kExtractPatchesPfS_S_S_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kExtractPatchesPfS_S_S_S_iiiiii, .Lfunc_end0-_Z15kExtractPatchesPfS_S_S_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kExtractPatchesPfS_S_S_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z15kExtractPatchesPfS_S_S_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExtractPatches(float* images, float* patches, float* indices, float* width_offset, float* height_offset, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
const unsigned long idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned long numThreads = blockDim.x * gridDim.x;
const unsigned long total_pixels = patch_width * patch_height * num_colors * num_images;
unsigned long ind, pos;
unsigned long image_id, dest_row, dest_col, color, source_row, source_col;
for (unsigned long i = idx; i < total_pixels; i += numThreads) {
ind = i;
image_id = ind % num_images; ind /= num_images;
dest_col = ind % patch_width; ind /= patch_width;
dest_row = ind % patch_height; ind /= patch_height;
color = ind % num_colors;
source_row = int(height_offset[image_id]) + dest_row;
source_col = int(width_offset[image_id]) + dest_col;
pos = img_width * img_height * num_colors * (int)indices[image_id] + img_width * img_height * color + img_width * source_row + source_col;
patches[i] = images[pos];
}
}
|
.text
.file "kExtractPatches.hip"
.globl _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii # -- Begin function _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.p2align 4, 0x90
.type _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii,@function
_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii: # @_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15kExtractPatchesPfS_S_S_S_iiiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii, .Lfunc_end0-_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kExtractPatchesPfS_S_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kExtractPatchesPfS_S_S_S_iiiiii,@object # @_Z15kExtractPatchesPfS_S_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z15kExtractPatchesPfS_S_S_S_iiiiii
.p2align 3, 0x0
_Z15kExtractPatchesPfS_S_S_S_iiiiii:
.quad _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.size _Z15kExtractPatchesPfS_S_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15kExtractPatchesPfS_S_S_S_iiiiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kExtractPatchesPfS_S_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000b581e_00000000-6_kExtractPatches.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.type _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, @function
_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kExtractPatchesPfS_S_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, .-_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.globl _Z15kExtractPatchesPfS_S_S_S_iiiiii
.type _Z15kExtractPatchesPfS_S_S_S_iiiiii, @function
_Z15kExtractPatchesPfS_S_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15kExtractPatchesPfS_S_S_S_iiiiii, .-_Z15kExtractPatchesPfS_S_S_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15kExtractPatchesPfS_S_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kExtractPatchesPfS_S_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kExtractPatches.hip"
.globl _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii # -- Begin function _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.p2align 4, 0x90
.type _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii,@function
_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii: # @_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15kExtractPatchesPfS_S_S_S_iiiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii, .Lfunc_end0-_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kExtractPatchesPfS_S_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kExtractPatchesPfS_S_S_S_iiiiii,@object # @_Z15kExtractPatchesPfS_S_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z15kExtractPatchesPfS_S_S_S_iiiiii
.p2align 3, 0x0
_Z15kExtractPatchesPfS_S_S_S_iiiiii:
.quad _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.size _Z15kExtractPatchesPfS_S_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15kExtractPatchesPfS_S_S_S_iiiiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kExtractPatchesPfS_S_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void empty_kernel(void)
{
}
|
code for sm_80
Function : _Z12empty_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void empty_kernel(void)
{
}
|
.file "tmpxft_0000dd51_00000000-6_empty_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12empty_kernelvv
.type _Z31__device_stub__Z12empty_kernelvv, @function
_Z31__device_stub__Z12empty_kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12empty_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z12empty_kernelvv, .-_Z31__device_stub__Z12empty_kernelvv
.globl _Z12empty_kernelv
.type _Z12empty_kernelv, @function
_Z12empty_kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12empty_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12empty_kernelv, .-_Z12empty_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12empty_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12empty_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void empty_kernel(void)
{
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void empty_kernel(void)
{
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void empty_kernel(void)
{
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12empty_kernelv
.globl _Z12empty_kernelv
.p2align 8
.type _Z12empty_kernelv,@function
_Z12empty_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12empty_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12empty_kernelv, .Lfunc_end0-_Z12empty_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12empty_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z12empty_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void empty_kernel(void)
{
}
|
.text
.file "empty_kernel.hip"
.globl _Z27__device_stub__empty_kernelv # -- Begin function _Z27__device_stub__empty_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__empty_kernelv,@function
_Z27__device_stub__empty_kernelv: # @_Z27__device_stub__empty_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12empty_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__empty_kernelv, .Lfunc_end0-_Z27__device_stub__empty_kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12empty_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12empty_kernelv,@object # @_Z12empty_kernelv
.section .rodata,"a",@progbits
.globl _Z12empty_kernelv
.p2align 3, 0x0
_Z12empty_kernelv:
.quad _Z27__device_stub__empty_kernelv
.size _Z12empty_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12empty_kernelv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__empty_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12empty_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12empty_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12empty_kernelv
.globl _Z12empty_kernelv
.p2align 8
.type _Z12empty_kernelv,@function
_Z12empty_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12empty_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12empty_kernelv, .Lfunc_end0-_Z12empty_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12empty_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z12empty_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0000dd51_00000000-6_empty_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12empty_kernelvv
.type _Z31__device_stub__Z12empty_kernelvv, @function
_Z31__device_stub__Z12empty_kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12empty_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z12empty_kernelvv, .-_Z31__device_stub__Z12empty_kernelvv
.globl _Z12empty_kernelv
.type _Z12empty_kernelv, @function
_Z12empty_kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12empty_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12empty_kernelv, .-_Z12empty_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12empty_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12empty_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "empty_kernel.hip"
.globl _Z27__device_stub__empty_kernelv # -- Begin function _Z27__device_stub__empty_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__empty_kernelv,@function
_Z27__device_stub__empty_kernelv: # @_Z27__device_stub__empty_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12empty_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__empty_kernelv, .Lfunc_end0-_Z27__device_stub__empty_kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12empty_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12empty_kernelv,@object # @_Z12empty_kernelv
.section .rodata,"a",@progbits
.globl _Z12empty_kernelv
.p2align 3, 0x0
_Z12empty_kernelv:
.quad _Z27__device_stub__empty_kernelv
.size _Z12empty_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12empty_kernelv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__empty_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12empty_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/* 32-bit (int) largest prime finder.
Atomic reduction solution.
*/
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 128
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
__device__ int d_xmax;
// Kernel(s) should go here:
// The kernel:
__global__ void MyKernel ()
{
int x, y, ymax;
// Global index is shifted by KMIN:
int k = KMIN + threadIdx.x + blockDim.x * blockIdx.x;
if (k > KMAX)
return;
int j = 2*blockIdx.y - 1;
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// To be a success, the modulus should not be equal to zero:
if (x%y == 0)
return;
}
// We get here only if x is a prime number
// Storing the globally largest prime:
atomicMax (&d_xmax, x);
return;
}
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, xmax;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
cudaGetDevice(&devid);
/* find how many devices are available */
if (cudaGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// It is very convenient to create blocks on a 2D grid, with the second dimension
// of size two corresponding to "-1" and "+1" cases:
dim3 Nblocks (NBLOCKS, 2, 1);
// The kernel call:
MyKernel <<<Nblocks, BLOCK_SIZE>>> ();
// Copying the result back to host:
if (error = cudaMemcpyFromSymbol (&xmax, d_xmax, sizeof(int), 0, cudaMemcpyDeviceToHost))
{
printf ("Error %d\n", error);
exit (error);
}
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
}
|
code for sm_80
Function : _Z8MyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ IADD3 R0, R0, 0x5f5e100, RZ ; /* 0x05f5e10000007810 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GT.AND P0, PT, R0, 0x5f767a0, PT ; /* 0x05f767a00000780c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0080*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*0090*/ BSSY B0, 0x220 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R2, R0, 0x3, R3 ; /* 0x0000000300027824 */
/* 0x001fc800078e0203 */
/*00c0*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x000e300000201c00 */
/*00f0*/ MUFU.RSQ64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e220000001c00 */
/*0100*/ IADD3 R8, R7, -0x3500000, RZ ; /* 0xfcb0000007087810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R8, 0x7ca00000, PT ; /* 0x7ca000000800780c */
/* 0x000fe40003f06070 */
/*0120*/ DMUL R4, R8, R8 ; /* 0x0000000808047228 */
/* 0x001e0c0000000000 */
/*0130*/ DFMA R4, R6, -R4, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000804 */
/*0140*/ DFMA R10, R4, R10, 0.5 ; /* 0x3fe00000040a742b */
/* 0x001fc8000000000a */
/*0150*/ DMUL R4, R8, R4 ; /* 0x0000000408047228 */
/* 0x000e0c0000000000 */
/*0160*/ DFMA R10, R10, R4, R8 ; /* 0x000000040a0a722b */
/* 0x001e0c0000000008 */
/*0170*/ DMUL R12, R6, R10 ; /* 0x0000000a060c7228 */
/* 0x001e080000000000 */
/*0180*/ IADD3 R17, R11, -0x100000, RZ ; /* 0xfff000000b117810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*01a0*/ DFMA R14, R12, -R12, R6 ; /* 0x8000000c0c0e722b */
/* 0x001e0c0000000006 */
/*01b0*/ DFMA R4, R14, R16, R12 ; /* 0x000000100e04722b */
/* 0x001062000000000c */
/*01c0*/ @!P0 BRA 0x210 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01d0*/ MOV R4, 0x1f0 ; /* 0x000001f000047802 */
/* 0x002fca0000000f00 */
/*01e0*/ CALL.REL.NOINC 0x500 ; /* 0x0000031000007944 */
/* 0x001fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0008 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ F2I.F64.CEIL R9, R4 ; /* 0x0000000400097311 */
/* 0x002e620000309100 */
/*0230*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0240*/ BSSY B0, 0x450 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.GE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x002fda0003f06270 */
/*0260*/ @!P0 BRA 0x440 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0270*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f06270 */
/*0280*/ IABS R6, R0.reuse ; /* 0x0000000000067213 */
/* 0x081fe40000000000 */
/*0290*/ IABS R11, R0 ; /* 0x00000000000b7213 */
/* 0x000fe20000000000 */
/*02a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fca00078e00ff */
/*02b0*/ IABS R8, R0.reuse ; /* 0x0000000000087213 */
/* 0x080fe40000000000 */
/*02c0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*02d0*/ I2F.RP R3, R8 ; /* 0x0000000800037306 */
/* 0x000e260000209400 */
/*02e0*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0a0a */
/*02f0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0300*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0310*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0320*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0330*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0340*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0350*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*0360*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0370*/ IMAD R5, R5, R10, R11 ; /* 0x0000000a05057224 */
/* 0x000fca00078e020b */
/*0380*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*0390*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a08 */
/*03a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f25270 */
/*03b0*/ ISETP.GT.U32.AND P2, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f44070 */
/*03c0*/ @!P2 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x000000010505a824 */
/* 0x000fc800078e0a08 */
/*03d0*/ @!P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff058224 */
/* 0x000fe200078e0a05 */
/*03e0*/ @!P1 LOP3.LUT R5, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff059212 */
/* 0x000fc800078e33ff */
/*03f0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0400*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.AND P1, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fda0003f24270 */
/*0430*/ @!P1 BRA 0x2b0 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e620000000000 */
/*0460*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe20007ffe0ff */
/*0470*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff027624 */
/* 0x000fe200078e00ff */
/*0490*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*04a0*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000eaa0000014200 */
/*04b0*/ ISETP.EQ.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x002fe2000bf02070 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fc400078e00ff */
/*04d0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x004fd4000f8e00ff */
/*04e0*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000d10e386 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ ISETP.GE.U32.AND P0, PT, R8, -0x3400000, PT ; /* 0xfcc000000800780c */
/* 0x000fe20003f06070 */
/*0510*/ BSSY B1, 0x760 ; /* 0x0000024000017945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fd600078e0011 */
/*0530*/ @!P0 BRA 0x5c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0540*/ DFMA.RM R10, R14, R10, R12 ; /* 0x0000000a0e0a722b */
/* 0x000e14000000400c */
/*0550*/ IADD3 R8, P0, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x001fca0007f1e0ff */
/*0560*/ IMAD.X R9, RZ, RZ, R11, P0 ; /* 0x000000ffff097224 */
/* 0x000fcc00000e060b */
/*0570*/ DFMA.RP R6, -R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x000e0c0000008106 */
/*0580*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x001e0c0003f04000 */
/*0590*/ FSEL R8, R8, R10, P0 ; /* 0x0000000a08087208 */
/* 0x001fe40000000000 */
/*05a0*/ FSEL R9, R9, R11, P0 ; /* 0x0000000b09097208 */
/* 0x000fe20000000000 */
/*05b0*/ BRA 0x750 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*05c0*/ DSETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e1c0003f05000 */
/*05d0*/ @!P0 BRA 0x740 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*05f0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff088424 */
/* 0x000fe400078e00ff */
/*0600*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ; /* 0xfff80000ff098424 */
/* 0x000fe200078e00ff */
/*0610*/ @!P0 BRA 0x750 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GT.AND P0, PT, R7, 0x7fefffff, PT ; /* 0x7fefffff0700780c */
/* 0x000fda0003f04270 */
/*0630*/ @P0 BRA 0x740 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0640*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x000e220000000000 */
/*0650*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0660*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0670*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0d7424 */
/* 0x000fe200078e00ff */
/*0680*/ MUFU.RSQ64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001c00 */
/*0690*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x001e0c0000000000 */
/*06a0*/ DFMA R10, R6, -R10, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c000000080a */
/*06b0*/ DFMA R12, R10, R12, 0.5 ; /* 0x3fe000000a0c742b */
/* 0x001fc8000000000c */
/*06c0*/ DMUL R10, R8, R10 ; /* 0x0000000a080a7228 */
/* 0x000e0c0000000000 */
/*06d0*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x001e0c0000000008 */
/*06e0*/ DMUL R8, R6, R10 ; /* 0x0000000a06087228 */
/* 0x0010480000000000 */
/*06f0*/ IADD3 R11, R11, -0x100000, RZ ; /* 0xfff000000b0b7810 */
/* 0x001fe40007ffe0ff */
/*0700*/ DFMA R12, R8, -R8, R6 ; /* 0x80000008080c722b */
/* 0x002e0c0000000006 */
/*0710*/ DFMA R8, R10, R12, R8 ; /* 0x0000000c0a08722b */
/* 0x001e140000000008 */
/*0720*/ IADD3 R9, R9, -0x3500000, RZ ; /* 0xfcb0000009097810 */
/* 0x001fe20007ffe0ff */
/*0730*/ BRA 0x750 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0740*/ DADD R8, R6, R6 ; /* 0x0000000006087229 */
/* 0x00004c0000000006 */
/*0750*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0770*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff88004007950 */
/* 0x000fea0003c3ffff */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/* 32-bit (int) largest prime finder.
Atomic reduction solution.
*/
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 128
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
__device__ int d_xmax;
// Kernel(s) should go here:
// The kernel:
__global__ void MyKernel ()
{
int x, y, ymax;
// Global index is shifted by KMIN:
int k = KMIN + threadIdx.x + blockDim.x * blockIdx.x;
if (k > KMAX)
return;
int j = 2*blockIdx.y - 1;
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// To be a success, the modulus should not be equal to zero:
if (x%y == 0)
return;
}
// We get here only if x is a prime number
// Storing the globally largest prime:
atomicMax (&d_xmax, x);
return;
}
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, xmax;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
cudaGetDevice(&devid);
/* find how many devices are available */
if (cudaGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// It is very convenient to create blocks on a 2D grid, with the second dimension
// of size two corresponding to "-1" and "+1" cases:
dim3 Nblocks (NBLOCKS, 2, 1);
// The kernel call:
MyKernel <<<Nblocks, BLOCK_SIZE>>> ();
// Copying the result back to host:
if (error = cudaMemcpyFromSymbol (&xmax, d_xmax, sizeof(int), 0, cudaMemcpyDeviceToHost))
{
printf ("Error %d\n", error);
exit (error);
}
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
}
|
.file "tmpxft_000f9ba9_00000000-6_primes2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16timeval_subtractPdP7timevalS1_
.type _Z16timeval_subtractPdP7timevalS1_, @function
_Z16timeval_subtractPdP7timevalS1_:
.LFB2070:
.cfi_startproc
endbr64
movq %rdx, %rcx
movq 8(%rsi), %rax
movq 8(%rdx), %r8
cmpq %r8, %rax
jge .L4
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
addl $1, %edx
imull $1000000, %edx, %eax
cltq
subq %rax, %r8
movq %r8, 8(%rcx)
movslq %edx, %rdx
addq %rdx, (%rcx)
.L4:
movq 8(%rsi), %rax
movq 8(%rcx), %r8
movq %rax, %rdx
subq %r8, %rdx
cmpq $1000000, %rdx
jle .L5
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
imull $1000000, %edx, %eax
cltq
addq %r8, %rax
movq %rax, 8(%rcx)
movslq %edx, %rdx
subq %rdx, (%rcx)
.L5:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq (%rsi), %rax
subq (%rcx), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rdi)
movq (%rcx), %rax
cmpq %rax, (%rsi)
setl %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2070:
.size _Z16timeval_subtractPdP7timevalS1_, .-_Z16timeval_subtractPdP7timevalS1_
.globl _Z26__device_stub__Z8MyKernelvv
.type _Z26__device_stub__Z8MyKernelvv, @function
_Z26__device_stub__Z8MyKernelvv:
.LFB2096:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z26__device_stub__Z8MyKernelvv, .-_Z26__device_stub__Z8MyKernelvv
.globl _Z8MyKernelv
.type _Z8MyKernelv, @function
_Z8MyKernelv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8MyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8MyKernelv, .-_Z8MyKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Device count, devid: %d %d\n"
.LC2:
.string "Device: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.section .rodata.str1.1
.LC4:
.string "No CUDA devices!\n"
.LC5:
.string "Error %d\n"
.LC6:
.string "%d\n"
.LC7:
.string "Time: %e\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1136, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L15
cmpl $0, 16(%rsp)
je .L15
leaq 96(%rsp), %rbx
movl 12(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 12(%rsp), %ecx
movl 16(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 460(%rsp), %ecx
movl 456(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $782, 36(%rsp)
movl $2, 40(%rsp)
movl $128, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
leaq 20(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6d_xmax(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
leaq 64(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movdqa 48(%rsp), %xmm1
movaps %xmm1, 80(%rsp)
leaq 80(%rsp), %rdx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call _Z16timeval_subtractPdP7timevalS1_
movl 20(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $1136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L25:
call _Z26__device_stub__Z8MyKernelvv
jmp .L18
.L26:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L27:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z8MyKernelv"
.LC9:
.string "d_xmax"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6d_xmax(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6d_xmax
.comm _ZL6d_xmax,4,4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/* 32-bit (int) largest prime finder.
Atomic reduction solution.
*/
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 128
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
__device__ int d_xmax;
// Kernel(s) should go here:
// The kernel:
__global__ void MyKernel ()
{
int x, y, ymax;
// Global index is shifted by KMIN:
int k = KMIN + threadIdx.x + blockDim.x * blockIdx.x;
if (k > KMAX)
return;
int j = 2*blockIdx.y - 1;
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// To be a success, the modulus should not be equal to zero:
if (x%y == 0)
return;
}
// We get here only if x is a prime number
// Storing the globally largest prime:
atomicMax (&d_xmax, x);
return;
}
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, xmax;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
cudaGetDevice(&devid);
/* find how many devices are available */
if (cudaGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// It is very convenient to create blocks on a 2D grid, with the second dimension
// of size two corresponding to "-1" and "+1" cases:
dim3 Nblocks (NBLOCKS, 2, 1);
// The kernel call:
MyKernel <<<Nblocks, BLOCK_SIZE>>> ();
// Copying the result back to host:
if (error = cudaMemcpyFromSymbol (&xmax, d_xmax, sizeof(int), 0, cudaMemcpyDeviceToHost))
{
printf ("Error %d\n", error);
exit (error);
}
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
}
|
/* 32-bit (int) largest prime finder.
Atomic reduction solution.
*/
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 128
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
__device__ int d_xmax;
// Kernel(s) should go here:
// The kernel:
__global__ void MyKernel ()
{
int x, y, ymax;
// Global index is shifted by KMIN:
int k = KMIN + threadIdx.x + blockDim.x * blockIdx.x;
if (k > KMAX)
return;
int j = 2*blockIdx.y - 1;
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// To be a success, the modulus should not be equal to zero:
if (x%y == 0)
return;
}
// We get here only if x is a prime number
// Storing the globally largest prime:
atomicMax (&d_xmax, x);
return;
}
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, xmax;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
hipGetDevice(&devid);
/* find how many devices are available */
if (hipGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// It is very convenient to create blocks on a 2D grid, with the second dimension
// of size two corresponding to "-1" and "+1" cases:
dim3 Nblocks (NBLOCKS, 2, 1);
// The kernel call:
MyKernel <<<Nblocks, BLOCK_SIZE>>> ();
// Copying the result back to host:
if (error = hipMemcpyFromSymbol (&xmax, HIP_SYMBOL(d_xmax), sizeof(int), 0, hipMemcpyDeviceToHost))
{
printf ("Error %d\n", error);
exit (error);
}
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/* 32-bit (int) largest prime finder.
Atomic reduction solution.
*/
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 128
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
__device__ int d_xmax;
// Kernel(s) should go here:
// The kernel:
__global__ void MyKernel ()
{
int x, y, ymax;
// Global index is shifted by KMIN:
int k = KMIN + threadIdx.x + blockDim.x * blockIdx.x;
if (k > KMAX)
return;
int j = 2*blockIdx.y - 1;
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// To be a success, the modulus should not be equal to zero:
if (x%y == 0)
return;
}
// We get here only if x is a prime number
// Storing the globally largest prime:
atomicMax (&d_xmax, x);
return;
}
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, xmax;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
hipGetDevice(&devid);
/* find how many devices are available */
if (hipGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// It is very convenient to create blocks on a 2D grid, with the second dimension
// of size two corresponding to "-1" and "+1" cases:
dim3 Nblocks (NBLOCKS, 2, 1);
// The kernel call:
MyKernel <<<Nblocks, BLOCK_SIZE>>> ();
// Copying the result back to host:
if (error = hipMemcpyFromSymbol (&xmax, HIP_SYMBOL(d_xmax), sizeof(int), 0, hipMemcpyDeviceToHost))
{
printf ("Error %d\n", error);
exit (error);
}
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelv
.globl _Z8MyKernelv
.p2align 8
.type _Z8MyKernelv,@function
_Z8MyKernelv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s0
s_mov_b32 s0, exec_lo
v_add3_u32 v0, v0, s14, 0x5f5e100
v_cmpx_gt_i32_e32 0x5f767a1, v0
s_cbranch_execz .LBB0_12
v_mul_lo_u32 v0, v0, 6
s_lshl_b32 s0, s15, 1
s_mov_b32 s2, -1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s0, -1, v0
s_mov_b32 s0, exec_lo
v_cvt_f64_i32_e32 v[1:2], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_lshlrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], v3
v_rsq_f64_e32 v[3:4], v[1:2]
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[1:2], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[1:2], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], v5
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f64_e32 v[1:2], v[1:2]
v_cvt_i32_f64_e32 v1, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 2, v1
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v2, 31, v0
s_mov_b32 s2, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v0, v2
v_xor_b32_e32 v3, v3, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_xor_b32 s6, s4, -1
s_and_b32 s7, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s7, s1
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s6, s6, exec_lo
s_or_b32 s3, s3, s6
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_6
.LBB0_4:
v_cvt_f32_u32_e32 v4, s2
s_sub_i32 s6, 0, s2
s_or_b32 s4, s4, exec_lo
s_or_b32 s5, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s6, v4
s_mov_b32 s6, exec_lo
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s2
v_sub_nc_u32_e32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v4
v_cmp_le_u32_e32 vcc_lo, s2, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v4
v_cmp_le_u32_e32 vcc_lo, s2, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v2
v_sub_nc_u32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB0_3
s_add_i32 s2, s2, 2
s_and_not1_b32 s5, s5, exec_lo
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s2, s3, exec_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_12
s_mov_b32 s1, exec_lo
s_brev_b32 s0, 1
.LBB0_9:
s_ctz_i32_b32 s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s3, v0, s2
s_lshl_b32 s2, 1, s2
s_and_not1_b32 s1, s1, s2
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s0, s0, s3
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB0_9
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_xmax@rel32@lo+4
s_addc_u32 s3, s3, d_xmax@rel32@hi+12
global_atomic_max_i32 v0, v1, s[2:3]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelv, .Lfunc_end0-_Z8MyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_xmax
.type d_xmax,@object
.section .bss,"aw",@nobits
.globl d_xmax
.p2align 2, 0x0
d_xmax:
.long 0
.size d_xmax, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_xmax
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/* 32-bit (int) largest prime finder.
Atomic reduction solution.
*/
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 128
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
__device__ int d_xmax;
// Kernel(s) should go here:
// The kernel:
__global__ void MyKernel ()
{
int x, y, ymax;
// Global index is shifted by KMIN:
int k = KMIN + threadIdx.x + blockDim.x * blockIdx.x;
if (k > KMAX)
return;
int j = 2*blockIdx.y - 1;
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// To be a success, the modulus should not be equal to zero:
if (x%y == 0)
return;
}
// We get here only if x is a prime number
// Storing the globally largest prime:
atomicMax (&d_xmax, x);
return;
}
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, xmax;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
hipGetDevice(&devid);
/* find how many devices are available */
if (hipGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// It is very convenient to create blocks on a 2D grid, with the second dimension
// of size two corresponding to "-1" and "+1" cases:
dim3 Nblocks (NBLOCKS, 2, 1);
// The kernel call:
MyKernel <<<Nblocks, BLOCK_SIZE>>> ();
// Copying the result back to host:
if (error = hipMemcpyFromSymbol (&xmax, HIP_SYMBOL(d_xmax), sizeof(int), 0, hipMemcpyDeviceToHost))
{
printf ("Error %d\n", error);
exit (error);
}
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
}
|
.text
.file "primes2.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16timeval_subtractPdP7timevalS1_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z16timeval_subtractPdP7timevalS1_
.p2align 4, 0x90
.type _Z16timeval_subtractPdP7timevalS1_,@function
_Z16timeval_subtractPdP7timevalS1_: # @_Z16timeval_subtractPdP7timevalS1_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movq 8(%rdx), %r9
movq %r9, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq 8(%rsi), %rax
jle .LBB0_2
# %bb.1:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %r9
movq %r9, 8(%rcx)
cltq
addq %rax, (%rcx)
.LBB0_2:
movq 8(%rsi), %rdx
movq 8(%rcx), %r9
movq %rdx, %rax
subq %r9, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB0_4
# %bb.3:
movq %r9, %rax
subq %rdx, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rax
subq %rax, (%rcx)
.LBB0_4:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
cvtsi2sd %rax, %xmm0
movq (%rsi), %rdx
divsd .LCPI0_0(%rip), %xmm0
xorl %eax, %eax
subq (%rcx), %rdx
cvtsi2sd %rdx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rdi)
setl %al
retq
.Lfunc_end0:
.size _Z16timeval_subtractPdP7timevalS1_, .Lfunc_end0-_Z16timeval_subtractPdP7timevalS1_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__MyKernelv # -- Begin function _Z23__device_stub__MyKernelv
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelv,@function
_Z23__device_stub__MyKernelv: # @_Z23__device_stub__MyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z23__device_stub__MyKernelv, .Lfunc_end1-_Z23__device_stub__MyKernelv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -16
leaq 4(%rsp), %rdi
callq hipGetDevice
movq %rsp, %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB2_12
# %bb.1:
cmpl $0, (%rsp)
je .LBB2_12
# %bb.2:
movl 4(%rsp), %esi
leaq 80(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl (%rsp), %esi
movl 4(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 440(%rsp), %esi
movl 444(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_13
# %bb.3:
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $8589935374, %rdi # imm = 0x20000030E
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
leaq 8(%rsp), %rdi
movl $d_xmax, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
testl %eax, %eax
jne .LBB2_13
# %bb.6:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_13
# %bb.7:
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 80(%rsp), %rdi
movq 88(%rsp), %rsi
movq 32(%rsp), %rcx
movq %rsi, %rax
subq %rcx, %rax
jle .LBB2_9
# %bb.8:
movabsq $4835703278458516699, %rdx # imm = 0x431BDE82D7B634DB
imulq %rdx
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %rsi
cltq
addq %rax, %rdi
.LBB2_9:
movq %rcx, %rax
subq %rsi, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB2_11
# %bb.10:
movq %rsi, %rax
subq %rcx, %rax
movabsq $4835703278458516699, %rdx # imm = 0x431BDE82D7B634DB
imulq %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %rax, %rsi
movslq %edx, %rax
subq %rax, %rdi
.LBB2_11: # %_Z16timeval_subtractPdP7timevalS1_.exit
movq 24(%rsp), %rax
subq %rdi, %rax
subq %rsi, %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsi2sd %rax, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl 8(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 1568
movl $.L.str.4, %edi
movl %eax, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq exit
.LBB2_12:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_xmax, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_xmax,@object # @d_xmax
.local d_xmax
.comm d_xmax,4,4
.type _Z8MyKernelv,@object # @_Z8MyKernelv
.section .rodata,"a",@progbits
.globl _Z8MyKernelv
.p2align 3, 0x0
_Z8MyKernelv:
.quad _Z23__device_stub__MyKernelv
.size _Z8MyKernelv, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device count, devid: %d %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device: %s\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.size .L.str.3, 48
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %d\n"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time: %e\n"
.size .L.str.6, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernelv"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_xmax"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "No CUDA devices!"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_xmax
.addrsig_sym _Z8MyKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z8MyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ IADD3 R0, R0, 0x5f5e100, RZ ; /* 0x05f5e10000007810 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GT.AND P0, PT, R0, 0x5f767a0, PT ; /* 0x05f767a00000780c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0080*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*0090*/ BSSY B0, 0x220 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R2, R0, 0x3, R3 ; /* 0x0000000300027824 */
/* 0x001fc800078e0203 */
/*00c0*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x000e300000201c00 */
/*00f0*/ MUFU.RSQ64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e220000001c00 */
/*0100*/ IADD3 R8, R7, -0x3500000, RZ ; /* 0xfcb0000007087810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R8, 0x7ca00000, PT ; /* 0x7ca000000800780c */
/* 0x000fe40003f06070 */
/*0120*/ DMUL R4, R8, R8 ; /* 0x0000000808047228 */
/* 0x001e0c0000000000 */
/*0130*/ DFMA R4, R6, -R4, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000804 */
/*0140*/ DFMA R10, R4, R10, 0.5 ; /* 0x3fe00000040a742b */
/* 0x001fc8000000000a */
/*0150*/ DMUL R4, R8, R4 ; /* 0x0000000408047228 */
/* 0x000e0c0000000000 */
/*0160*/ DFMA R10, R10, R4, R8 ; /* 0x000000040a0a722b */
/* 0x001e0c0000000008 */
/*0170*/ DMUL R12, R6, R10 ; /* 0x0000000a060c7228 */
/* 0x001e080000000000 */
/*0180*/ IADD3 R17, R11, -0x100000, RZ ; /* 0xfff000000b117810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*01a0*/ DFMA R14, R12, -R12, R6 ; /* 0x8000000c0c0e722b */
/* 0x001e0c0000000006 */
/*01b0*/ DFMA R4, R14, R16, R12 ; /* 0x000000100e04722b */
/* 0x001062000000000c */
/*01c0*/ @!P0 BRA 0x210 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01d0*/ MOV R4, 0x1f0 ; /* 0x000001f000047802 */
/* 0x002fca0000000f00 */
/*01e0*/ CALL.REL.NOINC 0x500 ; /* 0x0000031000007944 */
/* 0x001fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0008 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ F2I.F64.CEIL R9, R4 ; /* 0x0000000400097311 */
/* 0x002e620000309100 */
/*0230*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0240*/ BSSY B0, 0x450 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.GE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x002fda0003f06270 */
/*0260*/ @!P0 BRA 0x440 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0270*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f06270 */
/*0280*/ IABS R6, R0.reuse ; /* 0x0000000000067213 */
/* 0x081fe40000000000 */
/*0290*/ IABS R11, R0 ; /* 0x00000000000b7213 */
/* 0x000fe20000000000 */
/*02a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fca00078e00ff */
/*02b0*/ IABS R8, R0.reuse ; /* 0x0000000000087213 */
/* 0x080fe40000000000 */
/*02c0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*02d0*/ I2F.RP R3, R8 ; /* 0x0000000800037306 */
/* 0x000e260000209400 */
/*02e0*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0a0a */
/*02f0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0300*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0310*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0320*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0330*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0340*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0350*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*0360*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0370*/ IMAD R5, R5, R10, R11 ; /* 0x0000000a05057224 */
/* 0x000fca00078e020b */
/*0380*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*0390*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a08 */
/*03a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f25270 */
/*03b0*/ ISETP.GT.U32.AND P2, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f44070 */
/*03c0*/ @!P2 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x000000010505a824 */
/* 0x000fc800078e0a08 */
/*03d0*/ @!P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff058224 */
/* 0x000fe200078e0a05 */
/*03e0*/ @!P1 LOP3.LUT R5, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff059212 */
/* 0x000fc800078e33ff */
/*03f0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0400*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.AND P1, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fda0003f24270 */
/*0430*/ @!P1 BRA 0x2b0 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e620000000000 */
/*0460*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe20007ffe0ff */
/*0470*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff027624 */
/* 0x000fe200078e00ff */
/*0490*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*04a0*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000eaa0000014200 */
/*04b0*/ ISETP.EQ.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x002fe2000bf02070 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fc400078e00ff */
/*04d0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x004fd4000f8e00ff */
/*04e0*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000d10e386 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ ISETP.GE.U32.AND P0, PT, R8, -0x3400000, PT ; /* 0xfcc000000800780c */
/* 0x000fe20003f06070 */
/*0510*/ BSSY B1, 0x760 ; /* 0x0000024000017945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fd600078e0011 */
/*0530*/ @!P0 BRA 0x5c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0540*/ DFMA.RM R10, R14, R10, R12 ; /* 0x0000000a0e0a722b */
/* 0x000e14000000400c */
/*0550*/ IADD3 R8, P0, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x001fca0007f1e0ff */
/*0560*/ IMAD.X R9, RZ, RZ, R11, P0 ; /* 0x000000ffff097224 */
/* 0x000fcc00000e060b */
/*0570*/ DFMA.RP R6, -R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x000e0c0000008106 */
/*0580*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x001e0c0003f04000 */
/*0590*/ FSEL R8, R8, R10, P0 ; /* 0x0000000a08087208 */
/* 0x001fe40000000000 */
/*05a0*/ FSEL R9, R9, R11, P0 ; /* 0x0000000b09097208 */
/* 0x000fe20000000000 */
/*05b0*/ BRA 0x750 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*05c0*/ DSETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e1c0003f05000 */
/*05d0*/ @!P0 BRA 0x740 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*05f0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff088424 */
/* 0x000fe400078e00ff */
/*0600*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ; /* 0xfff80000ff098424 */
/* 0x000fe200078e00ff */
/*0610*/ @!P0 BRA 0x750 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GT.AND P0, PT, R7, 0x7fefffff, PT ; /* 0x7fefffff0700780c */
/* 0x000fda0003f04270 */
/*0630*/ @P0 BRA 0x740 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0640*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x000e220000000000 */
/*0650*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0660*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0670*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0d7424 */
/* 0x000fe200078e00ff */
/*0680*/ MUFU.RSQ64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001c00 */
/*0690*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x001e0c0000000000 */
/*06a0*/ DFMA R10, R6, -R10, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c000000080a */
/*06b0*/ DFMA R12, R10, R12, 0.5 ; /* 0x3fe000000a0c742b */
/* 0x001fc8000000000c */
/*06c0*/ DMUL R10, R8, R10 ; /* 0x0000000a080a7228 */
/* 0x000e0c0000000000 */
/*06d0*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x001e0c0000000008 */
/*06e0*/ DMUL R8, R6, R10 ; /* 0x0000000a06087228 */
/* 0x0010480000000000 */
/*06f0*/ IADD3 R11, R11, -0x100000, RZ ; /* 0xfff000000b0b7810 */
/* 0x001fe40007ffe0ff */
/*0700*/ DFMA R12, R8, -R8, R6 ; /* 0x80000008080c722b */
/* 0x002e0c0000000006 */
/*0710*/ DFMA R8, R10, R12, R8 ; /* 0x0000000c0a08722b */
/* 0x001e140000000008 */
/*0720*/ IADD3 R9, R9, -0x3500000, RZ ; /* 0xfcb0000009097810 */
/* 0x001fe20007ffe0ff */
/*0730*/ BRA 0x750 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0740*/ DADD R8, R6, R6 ; /* 0x0000000006087229 */
/* 0x00004c0000000006 */
/*0750*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0770*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff88004007950 */
/* 0x000fea0003c3ffff */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelv
.globl _Z8MyKernelv
.p2align 8
.type _Z8MyKernelv,@function
_Z8MyKernelv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s0
s_mov_b32 s0, exec_lo
v_add3_u32 v0, v0, s14, 0x5f5e100
v_cmpx_gt_i32_e32 0x5f767a1, v0
s_cbranch_execz .LBB0_12
v_mul_lo_u32 v0, v0, 6
s_lshl_b32 s0, s15, 1
s_mov_b32 s2, -1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s0, -1, v0
s_mov_b32 s0, exec_lo
v_cvt_f64_i32_e32 v[1:2], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_lshlrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], v3
v_rsq_f64_e32 v[3:4], v[1:2]
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[1:2], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[1:2], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], v5
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f64_e32 v[1:2], v[1:2]
v_cvt_i32_f64_e32 v1, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 2, v1
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v2, 31, v0
s_mov_b32 s2, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v0, v2
v_xor_b32_e32 v3, v3, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_xor_b32 s6, s4, -1
s_and_b32 s7, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s7, s1
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s6, s6, exec_lo
s_or_b32 s3, s3, s6
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_6
.LBB0_4:
v_cvt_f32_u32_e32 v4, s2
s_sub_i32 s6, 0, s2
s_or_b32 s4, s4, exec_lo
s_or_b32 s5, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s6, v4
s_mov_b32 s6, exec_lo
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s2
v_sub_nc_u32_e32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v4
v_cmp_le_u32_e32 vcc_lo, s2, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v4
v_cmp_le_u32_e32 vcc_lo, s2, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v2
v_sub_nc_u32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB0_3
s_add_i32 s2, s2, 2
s_and_not1_b32 s5, s5, exec_lo
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s2, s3, exec_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_12
s_mov_b32 s1, exec_lo
s_brev_b32 s0, 1
.LBB0_9:
s_ctz_i32_b32 s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s3, v0, s2
s_lshl_b32 s2, 1, s2
s_and_not1_b32 s1, s1, s2
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s0, s0, s3
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB0_9
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_xmax@rel32@lo+4
s_addc_u32 s3, s3, d_xmax@rel32@hi+12
global_atomic_max_i32 v0, v1, s[2:3]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelv, .Lfunc_end0-_Z8MyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_xmax
.type d_xmax,@object
.section .bss,"aw",@nobits
.globl d_xmax
.p2align 2, 0x0
d_xmax:
.long 0
.size d_xmax, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_xmax
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000f9ba9_00000000-6_primes2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16timeval_subtractPdP7timevalS1_
.type _Z16timeval_subtractPdP7timevalS1_, @function
_Z16timeval_subtractPdP7timevalS1_:
.LFB2070:
.cfi_startproc
endbr64
movq %rdx, %rcx
movq 8(%rsi), %rax
movq 8(%rdx), %r8
cmpq %r8, %rax
jge .L4
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
addl $1, %edx
imull $1000000, %edx, %eax
cltq
subq %rax, %r8
movq %r8, 8(%rcx)
movslq %edx, %rdx
addq %rdx, (%rcx)
.L4:
movq 8(%rsi), %rax
movq 8(%rcx), %r8
movq %rax, %rdx
subq %r8, %rdx
cmpq $1000000, %rdx
jle .L5
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
imull $1000000, %edx, %eax
cltq
addq %r8, %rax
movq %rax, 8(%rcx)
movslq %edx, %rdx
subq %rdx, (%rcx)
.L5:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq (%rsi), %rax
subq (%rcx), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rdi)
movq (%rcx), %rax
cmpq %rax, (%rsi)
setl %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2070:
.size _Z16timeval_subtractPdP7timevalS1_, .-_Z16timeval_subtractPdP7timevalS1_
.globl _Z26__device_stub__Z8MyKernelvv
.type _Z26__device_stub__Z8MyKernelvv, @function
_Z26__device_stub__Z8MyKernelvv:
.LFB2096:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z26__device_stub__Z8MyKernelvv, .-_Z26__device_stub__Z8MyKernelvv
.globl _Z8MyKernelv
.type _Z8MyKernelv, @function
_Z8MyKernelv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8MyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8MyKernelv, .-_Z8MyKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Device count, devid: %d %d\n"
.LC2:
.string "Device: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.section .rodata.str1.1
.LC4:
.string "No CUDA devices!\n"
.LC5:
.string "Error %d\n"
.LC6:
.string "%d\n"
.LC7:
.string "Time: %e\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1136, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L15
cmpl $0, 16(%rsp)
je .L15
leaq 96(%rsp), %rbx
movl 12(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 12(%rsp), %ecx
movl 16(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 460(%rsp), %ecx
movl 456(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $782, 36(%rsp)
movl $2, 40(%rsp)
movl $128, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
leaq 20(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6d_xmax(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
leaq 64(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movdqa 48(%rsp), %xmm1
movaps %xmm1, 80(%rsp)
leaq 80(%rsp), %rdx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call _Z16timeval_subtractPdP7timevalS1_
movl 20(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $1136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L25:
call _Z26__device_stub__Z8MyKernelvv
jmp .L18
.L26:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L27:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z8MyKernelv"
.LC9:
.string "d_xmax"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6d_xmax(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6d_xmax
.comm _ZL6d_xmax,4,4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "primes2.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16timeval_subtractPdP7timevalS1_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z16timeval_subtractPdP7timevalS1_
.p2align 4, 0x90
.type _Z16timeval_subtractPdP7timevalS1_,@function
_Z16timeval_subtractPdP7timevalS1_: # @_Z16timeval_subtractPdP7timevalS1_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movq 8(%rdx), %r9
movq %r9, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq 8(%rsi), %rax
jle .LBB0_2
# %bb.1:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %r9
movq %r9, 8(%rcx)
cltq
addq %rax, (%rcx)
.LBB0_2:
movq 8(%rsi), %rdx
movq 8(%rcx), %r9
movq %rdx, %rax
subq %r9, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB0_4
# %bb.3:
movq %r9, %rax
subq %rdx, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rax
subq %rax, (%rcx)
.LBB0_4:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
cvtsi2sd %rax, %xmm0
movq (%rsi), %rdx
divsd .LCPI0_0(%rip), %xmm0
xorl %eax, %eax
subq (%rcx), %rdx
cvtsi2sd %rdx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rdi)
setl %al
retq
.Lfunc_end0:
.size _Z16timeval_subtractPdP7timevalS1_, .Lfunc_end0-_Z16timeval_subtractPdP7timevalS1_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__MyKernelv # -- Begin function _Z23__device_stub__MyKernelv
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelv,@function
_Z23__device_stub__MyKernelv: # @_Z23__device_stub__MyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z23__device_stub__MyKernelv, .Lfunc_end1-_Z23__device_stub__MyKernelv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -16
leaq 4(%rsp), %rdi
callq hipGetDevice
movq %rsp, %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB2_12
# %bb.1:
cmpl $0, (%rsp)
je .LBB2_12
# %bb.2:
movl 4(%rsp), %esi
leaq 80(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl (%rsp), %esi
movl 4(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 440(%rsp), %esi
movl 444(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_13
# %bb.3:
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $8589935374, %rdi # imm = 0x20000030E
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
leaq 8(%rsp), %rdi
movl $d_xmax, %esi
movl $4, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
testl %eax, %eax
jne .LBB2_13
# %bb.6:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_13
# %bb.7:
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 80(%rsp), %rdi
movq 88(%rsp), %rsi
movq 32(%rsp), %rcx
movq %rsi, %rax
subq %rcx, %rax
jle .LBB2_9
# %bb.8:
movabsq $4835703278458516699, %rdx # imm = 0x431BDE82D7B634DB
imulq %rdx
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %rsi
cltq
addq %rax, %rdi
.LBB2_9:
movq %rcx, %rax
subq %rsi, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB2_11
# %bb.10:
movq %rsi, %rax
subq %rcx, %rax
movabsq $4835703278458516699, %rdx # imm = 0x431BDE82D7B634DB
imulq %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %rax, %rsi
movslq %edx, %rax
subq %rax, %rdi
.LBB2_11: # %_Z16timeval_subtractPdP7timevalS1_.exit
movq 24(%rsp), %rax
subq %rdi, %rax
subq %rsi, %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsi2sd %rax, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl 8(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 1568
movl $.L.str.4, %edi
movl %eax, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq exit
.LBB2_12:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_xmax, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_xmax,@object # @d_xmax
.local d_xmax
.comm d_xmax,4,4
.type _Z8MyKernelv,@object # @_Z8MyKernelv
.section .rodata,"a",@progbits
.globl _Z8MyKernelv
.p2align 3, 0x0
_Z8MyKernelv:
.quad _Z23__device_stub__MyKernelv
.size _Z8MyKernelv, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device count, devid: %d %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device: %s\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.size .L.str.3, 48
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %d\n"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time: %e\n"
.size .L.str.6, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernelv"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_xmax"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "No CUDA devices!"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_xmax
.addrsig_sym _Z8MyKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void scan(float * input, float * output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float sh_input[2048];
int tx = threadIdx.x;
int tx2= tx + blockDim.x;
int bdimx = blockDim.x;
int i = 2*blockIdx.x*blockDim.x + tx;
int start = 2*blockIdx.x*blockDim.x;
int Col1 = start + tx;
int Col2 = start + bdimx + tx;
if( Col2 < len)
{
// Collaborative loading of A
sh_input[tx] = input[ Col1];
sh_input[tx2] = input[ Col2];
}
else if ( Col1 < len)
{ // Control divergence at the edge
sh_input[tx] = input[ Col1];
sh_input[tx2]= 0.0f;
}
else
{ // Control divergence at the edge
sh_input[tx] = 0.0f;
sh_input[tx2]= 0.0f;
}
__syncthreads();
//output[Col1] = sh_input[tx]; output[Col2] = sh_input[tx2];
unsigned int stride; int index;
// @@ Traverse the reduction tree down
for (stride = 1;stride <= 2*bdimx ; stride *= 2)
{
index = (tx +1)* stride*2 -1;
if (index < 2*bdimx)
sh_input[index] += sh_input[index-stride];
__syncthreads();
}
//@@ Traverse the reduction tree up
for ( stride = bdimx/2; stride > 0; stride/=2)
{
__syncthreads();
index = (tx +1)* stride*2 -1;
if (index + stride < 2*bdimx)
sh_input[index+stride] += sh_input[index];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
__syncthreads();
output[i] = sh_input[tx];
if ( i + bdimx < len)
{
output[i + bdimx] = sh_input[tx2];
}
}
|
code for sm_80
Function : _Z4scanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x1c0 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x001fc800078e00ff */
/*0070*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x002fe400078e0200 */
/*0080*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.WIDE R6, R4.reuse, R9, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x040fe200078e0209 */
/*00a0*/ IADD3 R3, R4, c[0x0][0x0], RZ ; /* 0x0000000004037a10 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD R2, R9, c[0x0][0x0], R2 ; /* 0x0000000009027a24 */
/* 0x000fe200078e0202 */
/*00c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @!P0 BRA 0x160 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 STS [R0.X4], RZ ; /* 0x000000ff00000388 */
/* 0x0001e80000004800 */
/*0100*/ @P0 STS [R2], RZ ; /* 0x000000ff02000388 */
/* 0x0001e20000000800 */
/*0110*/ @P0 BRA 0x1b0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1900 */
/*0130*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0043e80000004800 */
/*0140*/ STS [R2], RZ ; /* 0x000000ff02007388 */
/* 0x0003e20000000800 */
/*0150*/ BRA 0x1b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.WIDE R8, R3, R9, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fe200078e0209 */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000eaa000c1e1900 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee8000c1e1900 */
/*0190*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e80000004800 */
/*01a0*/ STS [R2], R9 ; /* 0x0000000902007388 */
/* 0x0081e40000000800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f25270 */
/*01e0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fc800078e00ff */
/*01f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0200*/ IADD3 R5, R10, 0x1, RZ ; /* 0x000000010a057810 */
/* 0x000fe20007ffe0ff */
/*0210*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc6000800063f */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fc60003f06070 */
/*0230*/ @!P1 BRA 0x310 ; /* 0x000000d000009947 */
/* 0x000ff40003800000 */
/*0240*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fe200000001ff */
/*0250*/ LEA R5, R0, 0x2, 0x1 ; /* 0x0000000200057811 */
/* 0x000fd200078e08ff */
/*0260*/ IMAD R9, R5, R6, -0x1 ; /* 0xffffffff05097424 */
/* 0x001fca00078e0206 */
/*0270*/ ISETP.GE.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fda000bf26270 */
/*0280*/ @!P1 IMAD.IADD R7, R9, 0x1, -R6 ; /* 0x0000000109079824 */
/* 0x002fe200078e0a06 */
/*0290*/ @!P1 LDS R8, [R9.X4] ; /* 0x0000000009089984 */
/* 0x000fe20000004800 */
/*02a0*/ IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206067824 */
/* 0x000fc800078e00ff */
/*02b0*/ @!P1 LDS R7, [R7.X4] ; /* 0x0000000007079984 */
/* 0x000e240000004800 */
/*02c0*/ @!P1 FADD R8, R8, R7 ; /* 0x0000000708089221 */
/* 0x001fca0000000000 */
/*02d0*/ @!P1 STS [R9.X4], R8 ; /* 0x0000000809009388 */
/* 0x0001e80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02f0*/ ISETP.GT.U32.AND P1, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf24070 */
/*0300*/ @!P1 BRA 0x260 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*0310*/ @!P0 BRA 0x420 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0320*/ LEA.HI R5, R10, c[0x0][0x0], RZ, 0x1 ; /* 0x000000000a057a11 */
/* 0x000fe400078f08ff */
/*0330*/ LEA R10, R0, 0x2, 0x1 ; /* 0x00000002000a7811 */
/* 0x000fe400078e08ff */
/*0340*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fca0000011405 */
/*0350*/ IMAD R8, R10, R5.reuse, -0x1 ; /* 0xffffffff0a087424 */
/* 0x080fe200078e0205 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0370*/ IADD3 R6, R8, R5, RZ ; /* 0x0000000508067210 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06070 */
/*0390*/ @!P0 IMAD.SHL.U32 R6, R8, 0x4, RZ ; /* 0x0000000408068824 */
/* 0x000fe400078e00ff */
/*03a0*/ @!P0 LDS R8, [R8.X4] ; /* 0x0000000008088984 */
/* 0x000fe60000004800 */
/*03b0*/ @!P0 LEA R6, R5, R6, 0x2 ; /* 0x0000000605068211 */
/* 0x000fe400078e10ff */
/*03c0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fc60000011605 */
/*03d0*/ @!P0 LDS R7, [R6] ; /* 0x0000000006078984 */
/* 0x003e240000000800 */
/*03e0*/ @!P0 FADD R7, R7, R8 ; /* 0x0000000807078221 */
/* 0x001fca0000000000 */
/*03f0*/ @!P0 STS [R6], R7 ; /* 0x0000000706008388 */
/* 0x0001e20000000800 */
/*0400*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0410*/ @P0 BRA 0x350 ; /* 0xffffff3000000947 */
/* 0x001fea000383ffff */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0450*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*0460*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x003e280000004800 */
/*0470*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e6000c101906 */
/*0480*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0490*/ LDS R3, [R2] ; /* 0x0000000002037984 */
/* 0x000e620000000800 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x001fca0000000f00 */
/*04b0*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x000fca00078e0204 */
/*04c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x002fe2000c101906 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void scan(float * input, float * output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float sh_input[2048];
int tx = threadIdx.x;
int tx2= tx + blockDim.x;
int bdimx = blockDim.x;
int i = 2*blockIdx.x*blockDim.x + tx;
int start = 2*blockIdx.x*blockDim.x;
int Col1 = start + tx;
int Col2 = start + bdimx + tx;
if( Col2 < len)
{
// Collaborative loading of A
sh_input[tx] = input[ Col1];
sh_input[tx2] = input[ Col2];
}
else if ( Col1 < len)
{ // Control divergence at the edge
sh_input[tx] = input[ Col1];
sh_input[tx2]= 0.0f;
}
else
{ // Control divergence at the edge
sh_input[tx] = 0.0f;
sh_input[tx2]= 0.0f;
}
__syncthreads();
//output[Col1] = sh_input[tx]; output[Col2] = sh_input[tx2];
unsigned int stride; int index;
// @@ Traverse the reduction tree down
for (stride = 1;stride <= 2*bdimx ; stride *= 2)
{
index = (tx +1)* stride*2 -1;
if (index < 2*bdimx)
sh_input[index] += sh_input[index-stride];
__syncthreads();
}
//@@ Traverse the reduction tree up
for ( stride = bdimx/2; stride > 0; stride/=2)
{
__syncthreads();
index = (tx +1)* stride*2 -1;
if (index + stride < 2*bdimx)
sh_input[index+stride] += sh_input[index];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
__syncthreads();
output[i] = sh_input[tx];
if ( i + bdimx < len)
{
output[i + bdimx] = sh_input[tx2];
}
}
|
.file "tmpxft_000df603_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4scanPfS_iPfS_i
.type _Z26__device_stub__Z4scanPfS_iPfS_i, @function
_Z26__device_stub__Z4scanPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4scanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4scanPfS_iPfS_i, .-_Z26__device_stub__Z4scanPfS_iPfS_i
.globl _Z4scanPfS_i
.type _Z4scanPfS_i, @function
_Z4scanPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4scanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4scanPfS_i, .-_Z4scanPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4scanPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void scan(float * input, float * output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float sh_input[2048];
int tx = threadIdx.x;
int tx2= tx + blockDim.x;
int bdimx = blockDim.x;
int i = 2*blockIdx.x*blockDim.x + tx;
int start = 2*blockIdx.x*blockDim.x;
int Col1 = start + tx;
int Col2 = start + bdimx + tx;
if( Col2 < len)
{
// Collaborative loading of A
sh_input[tx] = input[ Col1];
sh_input[tx2] = input[ Col2];
}
else if ( Col1 < len)
{ // Control divergence at the edge
sh_input[tx] = input[ Col1];
sh_input[tx2]= 0.0f;
}
else
{ // Control divergence at the edge
sh_input[tx] = 0.0f;
sh_input[tx2]= 0.0f;
}
__syncthreads();
//output[Col1] = sh_input[tx]; output[Col2] = sh_input[tx2];
unsigned int stride; int index;
// @@ Traverse the reduction tree down
for (stride = 1;stride <= 2*bdimx ; stride *= 2)
{
index = (tx +1)* stride*2 -1;
if (index < 2*bdimx)
sh_input[index] += sh_input[index-stride];
__syncthreads();
}
//@@ Traverse the reduction tree up
for ( stride = bdimx/2; stride > 0; stride/=2)
{
__syncthreads();
index = (tx +1)* stride*2 -1;
if (index + stride < 2*bdimx)
sh_input[index+stride] += sh_input[index];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
__syncthreads();
output[i] = sh_input[tx];
if ( i + bdimx < len)
{
output[i + bdimx] = sh_input[tx2];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan(float * input, float * output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float sh_input[2048];
int tx = threadIdx.x;
int tx2= tx + blockDim.x;
int bdimx = blockDim.x;
int i = 2*blockIdx.x*blockDim.x + tx;
int start = 2*blockIdx.x*blockDim.x;
int Col1 = start + tx;
int Col2 = start + bdimx + tx;
if( Col2 < len)
{
// Collaborative loading of A
sh_input[tx] = input[ Col1];
sh_input[tx2] = input[ Col2];
}
else if ( Col1 < len)
{ // Control divergence at the edge
sh_input[tx] = input[ Col1];
sh_input[tx2]= 0.0f;
}
else
{ // Control divergence at the edge
sh_input[tx] = 0.0f;
sh_input[tx2]= 0.0f;
}
__syncthreads();
//output[Col1] = sh_input[tx]; output[Col2] = sh_input[tx2];
unsigned int stride; int index;
// @@ Traverse the reduction tree down
for (stride = 1;stride <= 2*bdimx ; stride *= 2)
{
index = (tx +1)* stride*2 -1;
if (index < 2*bdimx)
sh_input[index] += sh_input[index-stride];
__syncthreads();
}
//@@ Traverse the reduction tree up
for ( stride = bdimx/2; stride > 0; stride/=2)
{
__syncthreads();
index = (tx +1)* stride*2 -1;
if (index + stride < 2*bdimx)
sh_input[index+stride] += sh_input[index];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
__syncthreads();
output[i] = sh_input[tx];
if ( i + bdimx < len)
{
output[i + bdimx] = sh_input[tx2];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan(float * input, float * output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float sh_input[2048];
int tx = threadIdx.x;
int tx2= tx + blockDim.x;
int bdimx = blockDim.x;
int i = 2*blockIdx.x*blockDim.x + tx;
int start = 2*blockIdx.x*blockDim.x;
int Col1 = start + tx;
int Col2 = start + bdimx + tx;
if( Col2 < len)
{
// Collaborative loading of A
sh_input[tx] = input[ Col1];
sh_input[tx2] = input[ Col2];
}
else if ( Col1 < len)
{ // Control divergence at the edge
sh_input[tx] = input[ Col1];
sh_input[tx2]= 0.0f;
}
else
{ // Control divergence at the edge
sh_input[tx] = 0.0f;
sh_input[tx2]= 0.0f;
}
__syncthreads();
//output[Col1] = sh_input[tx]; output[Col2] = sh_input[tx2];
unsigned int stride; int index;
// @@ Traverse the reduction tree down
for (stride = 1;stride <= 2*bdimx ; stride *= 2)
{
index = (tx +1)* stride*2 -1;
if (index < 2*bdimx)
sh_input[index] += sh_input[index-stride];
__syncthreads();
}
//@@ Traverse the reduction tree up
for ( stride = bdimx/2; stride > 0; stride/=2)
{
__syncthreads();
index = (tx +1)* stride*2 -1;
if (index + stride < 2*bdimx)
sh_input[index+stride] += sh_input[index];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
__syncthreads();
output[i] = sh_input[tx];
if ( i + bdimx < len)
{
output[i + bdimx] = sh_input[tx2];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPfS_i
.globl _Z4scanPfS_i
.p2align 8
.type _Z4scanPfS_i,@function
_Z4scanPfS_i:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s5
s_lshl_b32 s7, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add3_u32 v3, s7, s5, v0
v_add_nc_u32_e32 v1, s7, v0
s_mov_b32 s7, exec_lo
v_cmpx_le_i32_e64 s4, v3
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_6
s_mov_b32 s8, exec_lo
v_cmpx_le_i32_e64 s4, v1
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_mov_b32 s9, 0
ds_store_b32 v2, v3
.LBB0_3:
s_or_saveexec_b32 s8, s8
v_mov_b32_e32 v4, s9
s_xor_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_6:
s_or_saveexec_b32 s7, s7
v_ashrrev_i32_e32 v2, 31, v1
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v4, v[3:4], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(1)
ds_store_b32 v3, v5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v3, s5, v0
v_cmp_eq_u16_e64 s6, s6, 0
s_mov_b32 s3, 1
s_lshl_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v3
s_and_b32 vcc_lo, exec_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_13
v_lshl_add_u32 v4, v0, 1, 2
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v4, s3
s_mov_b32 s6, exec_lo
v_cmpx_ge_u32_e64 s2, v5
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v5, -1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v5
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_10
.LBB0_13:
s_cmp_lt_u32 s5, 2
s_cbranch_scc1 .LBB0_18
v_lshl_add_u32 v4, v0, 1, 2
s_mov_b32 s3, s5
s_branch .LBB0_16
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s6
s_cbranch_scc0 .LBB0_18
.LBB0_16:
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_mad_u32_u24 v6, v4, s6, -1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v5, s6, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v5
s_cbranch_execz .LBB0_15
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_15
.LBB0_18:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[4:5], 2, v[1:2]
ds_load_b32 v6, v0
v_add_nc_u32_e32 v0, s5, v1
s_mov_b32 s2, exec_lo
v_add_co_u32 v1, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v5, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v6, off
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_20
v_lshlrev_b32_e32 v1, 2, v3
ds_load_b32 v2, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPfS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPfS_i, .Lfunc_end0-_Z4scanPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4scanPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
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