system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafe... | .text
.file "lakegpu.hip"
.globl _Z25__device_stub__evolve_GPUPdS_S_S_idddi # -- Begin function _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.p2align 4, 0x90
.type _Z25__device_stub__evolve_GPUPdS_S_S_idddi,@function
_Z25__device_stub__evolve_GPUPdS_S_S_idddi: # @_Z25__device_stub__evolve_GPUPdS_S_S_idddi
.cfi_startproc
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10evolve_GPUPdS_S_S_idddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10evolve_GPUPdS_S_S_idddi
.globl _Z10evolve_GPUPdS_S_S_idddi
.p2align 8
.type _Z10evolve_GPUPdS_S_S_idddi,@function
_Z10evolve_GPUPdS_S_S_idddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s10, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b3... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062ed2_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "lakegpu.hip"
.globl _Z25__device_stub__evolve_GPUPdS_S_S_idddi # -- Begin function _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.p2align 4, 0x90
.type _Z25__device_stub__evolve_GPUPdS_S_S_idddi,@function
_Z25__device_stub__evolve_GPUPdS_S_S_idddi: # @_Z25__device_stub__evolve_GPUPdS_S_S_idddi
.cfi_startproc
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
for( int ks = 0; ks < p; ks +=... | .file "tmpxft_00179a46_00000000-6_k5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
for( int ks = 0; ks < p; ks +=... | #include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
f... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
f... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mmkernel
.globl mmkernel
.p2align 8
.type mmkernel,@function
mmkernel:
s_load_b32 s9, s[0:1], 0x2c
v_lshl_add_u32 v6, s14, 6, v0
s_lshl_b32 s8, s15, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cb... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
f... | .text
.file "k5.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rs... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00179a46_00000000-6_k5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_... | .text
.file "k5.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | code for sm_80
Function : _Z10square_i32PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | .file "tmpxft_000fc9c7_00000000-6_square_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10square_i32PiS_i
.globl _Z10square_i32PiS_i
.p2align 8
.type _Z10square_i32PiS_i,@function
_Z10square_i32PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | .text
.file "square_i32.hip"
.globl _Z25__device_stub__square_i32PiS_i # -- Begin function _Z25__device_stub__square_i32PiS_i
.p2align 4, 0x90
.type _Z25__device_stub__square_i32PiS_i,@function
_Z25__device_stub__square_i32PiS_i: # @_Z25__device_stub__square_i32PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10square_i32PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10square_i32PiS_i
.globl _Z10square_i32PiS_i
.p2align 8
.type _Z10square_i32PiS_i,@function
_Z10square_i32PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fc9c7_00000000-6_square_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "square_i32.hip"
.globl _Z25__device_stub__square_i32PiS_i # -- Begin function _Z25__device_stub__square_i32PiS_i
.p2align 4, 0x90
.type _Z25__device_stub__square_i32PiS_i,@function
_Z25__device_stub__square_i32PiS_i: # @_Z25__device_stub__square_i32PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | code for sm_80
Function : _Z17calcCDFnormalizedPKjPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | .file "tmpxft_0009c3d6_00000000-6_calcCDFnormalized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17calcCDFnormalizedPKjPfmm
.globl _Z17calcCDFnormalizedPKjPfmm
.p2align 8
.type _Z17calcCDFnormalizedPKjPfmm,@function
_Z17calcCDFnormalizedPKjPfmm:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_add_nc_u32_e32 v4, 1, v0
s_waitcnt... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | .text
.file "calcCDFnormalized.hip"
.globl _Z32__device_stub__calcCDFnormalizedPKjPfmm # -- Begin function _Z32__device_stub__calcCDFnormalizedPKjPfmm
.p2align 4, 0x90
.type _Z32__device_stub__calcCDFnormalizedPKjPfmm,@function
_Z32__device_stub__calcCDFnormalizedPKjPfmm: # @_Z32__device_stub__calcCDFnormalizedPKjPfmm
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17calcCDFnormalizedPKjPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17calcCDFnormalizedPKjPfmm
.globl _Z17calcCDFnormalizedPKjPfmm
.p2align 8
.type _Z17calcCDFnormalizedPKjPfmm,@function
_Z17calcCDFnormalizedPKjPfmm:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_add_nc_u32_e32 v4, 1, v0
s_waitcnt... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009c3d6_00000000-6_calcCDFnormalized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq... | .text
.file "calcCDFnormalized.hip"
.globl _Z32__device_stub__calcCDFnormalizedPKjPfmm # -- Begin function _Z32__device_stub__calcCDFnormalizedPKjPfmm
.p2align 4, 0x90
.type _Z32__device_stub__calcCDFnormalizedPKjPfmm,@function
_Z32__device_stub__calcCDFnormalizedPKjPfmm: # @_Z32__device_stub__calcCDFnormalizedPKjPfmm
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
/* Usag... | code for sm_80
Function : _Z6matMulPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R9, c[0x0][0x178] ; /* 0x00005e0000097a02 */
/* 0x000fe20000000f00 */
/*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
/* Usag... | .file "tmpxft_0006d7ad_00000000-6_mp2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL6matMulPfS_S_iii, @function
_ZL6matMulPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movl... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
/* Usag... | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL6matMulPfS_S_iii,"axG",@progbits,_ZL6matMulPfS_S_iii,comdat
.globl _ZL6matMulPfS_S_iii
.p2align 8
.type _ZL6matMulPfS_S_iii,@function
_ZL6matMulPfS_S_iii:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math... | .text
.file "mp2.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x41200000 # float 10
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <cuda.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i])... | code for sm_80
Function : _Z9AddVectorPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <cuda.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i])... | .file "tmpxft_000b1bf5_00000000-6_add_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <cuda.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i])... | #include <stdlib.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9AddVectorPfS_S_i
.globl _Z9AddVectorPfS_S_i
.p2align 8
.type _Z9AddVectorPfS_S_i,@function
_Z9AddVectorPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.... | .text
.file "add_vector.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_vectorPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x40a00000 # float 5
.text
.globl _Z11fill_vectorPfi
.p2align 4,... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9AddVectorPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9AddVectorPfS_S_i
.globl _Z9AddVectorPfS_S_i
.p2align 8
.type _Z9AddVectorPfS_S_i,@function
_Z9AddVectorPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b1bf5_00000000-6_add_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "add_vector.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_vectorPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x40a00000 # float 5
.text
.globl _Z11fill_vectorPfi
.p2align 4,... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | code for sm_80
Function : _Z15grads_w1_kernelPdS_di
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 *... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | .file "tmpxft_00135141_00000000-6_grads_w1_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j]... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j]... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15grads_w1_kernelPdS_di
.globl _Z15grads_w1_kernelPdS_di
.p2align 8
.type _Z15grads_w1_kernelPdS_di,@function
_Z15grads_w1_kernelPdS_di:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j]... | .text
.file "grads_w1_kernel.hip"
.globl _Z30__device_stub__grads_w1_kernelPdS_di # -- Begin function _Z30__device_stub__grads_w1_kernelPdS_di
.p2align 4, 0x90
.type _Z30__device_stub__grads_w1_kernelPdS_di,@function
_Z30__device_stub__grads_w1_kernelPdS_di: # @_Z30__device_stub__grads_w1_kernelPdS_di
.cfi_startproc
# ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15grads_w1_kernelPdS_di
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 *... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15grads_w1_kernelPdS_di
.globl _Z15grads_w1_kernelPdS_di
.p2align 8
.type _Z15grads_w1_kernelPdS_di,@function
_Z15grads_w1_kernelPdS_di:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00135141_00000000-6_grads_w1_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... | .text
.file "grads_w1_kernel.hip"
.globl _Z30__device_stub__grads_w1_kernelPdS_di # -- Begin function _Z30__device_stub__grads_w1_kernelPdS_di
.p2align 4, 0x90
.type _Z30__device_stub__grads_w1_kernelPdS_di,@function
_Z30__device_stub__grads_w1_kernelPdS_di: # @_Z30__device_stub__grads_w1_kernelPdS_di
.cfi_startproc
# ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.... | code for sm_80
Function : _Z9ApplyMat3PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.... | .file "tmpxft_0007bd96_00000000-6_ApplyMat3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
/... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ApplyMat3PfS_S_
.globl _Z9ApplyMat3PfS_S_
.p2align 8
.type _Z9ApplyMat3PfS_S_,@function
_Z9ApplyMat3PfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v4... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
/... | .text
.file "ApplyMat3.hip"
.globl _Z24__device_stub__ApplyMat3PfS_S_ # -- Begin function _Z24__device_stub__ApplyMat3PfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__ApplyMat3PfS_S_,@function
_Z24__device_stub__ApplyMat3PfS_S_: # @_Z24__device_stub__ApplyMat3PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9ApplyMat3PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*002... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ApplyMat3PfS_S_
.globl _Z9ApplyMat3PfS_S_
.p2align 8
.type _Z9ApplyMat3PfS_S_,@function
_Z9ApplyMat3PfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v4... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007bd96_00000000-6_ApplyMat3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... | .text
.file "ApplyMat3.hip"
.globl _Z24__device_stub__ApplyMat3PfS_S_ # -- Begin function _Z24__device_stub__ApplyMat3PfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__ApplyMat3PfS_S_,@function
_Z24__device_stub__ApplyMat3PfS_S_: # @_Z24__device_stub__ApplyMat3PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort ... | code for sm_80
Function : _Z17dipoleCorrelationPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort ... | .file "tmpxft_00196827_00000000-6_stat2dipole.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4235:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cu... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort ... | #include "hip/hip_runtime.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if(code != hipSuccess)
{
f... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if(code != hipSuccess)
{
f... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17dipoleCorrelationPdS_S_S_i
.globl _Z17dipoleCorrelationPdS_S_S_i
.p2align 8
.type _Z17dipoleCorrelationPdS_S_S_i,@function
_Z17dipoleCorrelationPdS_S_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_mov_b32 s14, exec_l... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17dipoleCorrelationPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17dipoleCorrelationPdS_S_S_i
.globl _Z17dipoleCorrelationPdS_S_S_i
.p2align 8
.type _Z17dipoleCorrelationPdS_S_S_i,@function
_Z17dipoleCorrelationPdS_S_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_mov_b32 s14, exec_l... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | code for sm_80
Function : _Z10wave1Dmac1PdS_dddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | .file "tmpxft_00090652_00000000-6_wave1Dmac1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | #include <hip/hip_runtime.h>
__global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10wave1Dmac1PdS_dddi
.globl _Z10wave1Dmac1PdS_dddi
.p2align 8
.type _Z10wave1Dmac1PdS_dddi,@function
_Z10wave1Dmac1PdS_dddi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xfff... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | .text
.file "wave1Dmac1.hip"
.globl _Z25__device_stub__wave1Dmac1PdS_dddi # -- Begin function _Z25__device_stub__wave1Dmac1PdS_dddi
.p2align 4, 0x90
.type _Z25__device_stub__wave1Dmac1PdS_dddi,@function
_Z25__device_stub__wave1Dmac1PdS_dddi: # @_Z25__device_stub__wave1Dmac1PdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10wave1Dmac1PdS_dddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10wave1Dmac1PdS_dddi
.globl _Z10wave1Dmac1PdS_dddi
.p2align 8
.type _Z10wave1Dmac1PdS_dddi,@function
_Z10wave1Dmac1PdS_dddi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xfff... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00090652_00000000-6_wave1Dmac1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "wave1Dmac1.hip"
.globl _Z25__device_stub__wave1Dmac1PdS_dddi # -- Begin function _Z25__device_stub__wave1Dmac1PdS_dddi
.p2align 4, 0x90
.type _Z25__device_stub__wave1Dmac1PdS_dddi,@function
_Z25__device_stub__wave1Dmac1PdS_dddi: # @_Z25__device_stub__wave1Dmac1PdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%... | .file "tmpxft_000395f2_00000000-6_debugFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%... | #include <stdio.h>
#include <hip/hip_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf... | .text
.file "debugFunctions.hip"
.globl _Z11printMatrixiiPKfiPKc # -- Begin function _Z11printMatrixiiPKfiPKc
.p2align 4, 0x90
.type _Z11printMatrixiiPKfiPKc,@function
_Z11printMatrixiiPKfiPKc: # @_Z11printMatrixiiPKfiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000395f2_00000000-6_debugFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "debugFunctions.hip"
.globl _Z11printMatrixiiPKfiPKc # -- Begin function _Z11printMatrixiiPKfiPKc
.p2align 4, 0x90
.type _Z11printMatrixiiPKfiPKc,@function
_Z11printMatrixiiPKfiPKc: # @_Z11printMatrixiiPKfiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this fil... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this fil... | .file "tmpxft_0018a879_00000000-6_checkedc-notsupported-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this fil... | #include <hip/hip_runtime.h>
// Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
/... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
/... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
/... | .text
.file "checkedc-notsupported-cuda.hip"
.globl _Z1fv # -- Begin function _Z1fv
.p2align 4, 0x90
.type _Z1fv,@function
_Z1fv: # @_Z1fv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z1fv, .Lfunc_end0-_Z1fv
.cfi_endproc
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018a879_00000000-6_checkedc-notsupported-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary... | .text
.file "checkedc-notsupported-cuda.hip"
.globl _Z1fv # -- Begin function _Z1fv
.p2align 4, 0x90
.type _Z1fv,@function
_Z1fv: # @_Z1fv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z1fv, .Lfunc_end0-_Z1fv
.cfi_endproc
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | code for sm_80
Function : _Z9broadcastPKfPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | .file "tmpxft_00113cc1_00000000-6_broadcast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9broadcastPKfPfjj
.globl _Z9broadcastPKfPfjj
.p2align 8
.type _Z9broadcastPKfPfjj,@function
_Z9broadcastPKfPfjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | .text
.file "broadcast.hip"
.globl _Z24__device_stub__broadcastPKfPfjj # -- Begin function _Z24__device_stub__broadcastPKfPfjj
.p2align 4, 0x90
.type _Z24__device_stub__broadcastPKfPfjj,@function
_Z24__device_stub__broadcastPKfPfjj: # @_Z24__device_stub__broadcastPKfPfjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9broadcastPKfPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9broadcastPKfPfjj
.globl _Z9broadcastPKfPfjj
.p2align 8
.type _Z9broadcastPKfPfjj,@function
_Z9broadcastPKfPfjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00113cc1_00000000-6_broadcast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... | .text
.file "broadcast.hip"
.globl _Z24__device_stub__broadcastPKfPfjj # -- Begin function _Z24__device_stub__broadcastPKfPfjj
.p2align 4, 0x90
.type _Z24__device_stub__broadcastPKfPfjj,@function
_Z24__device_stub__broadcastPKfPfjj: # @_Z24__device_stub__broadcastPKfPfjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ st... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ st... | .file "tmpxft_00017bc0_00000000-6_hash_helper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ st... | #include <hip/hip_runtime.h>
//This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<i... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<i... | .text
.file "hash_helper.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-proj... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017bc0_00000000-6_hash_helper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "hash_helper.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-proj... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////... | code for sm_80
Function : _Z10timeFilterPKdPKfS2_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x000058... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////... | .file "tmpxft_00158dba_00000000-6_timeFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////... | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10timeFilterPKdPKfS2_Pf
.globl _Z10timeFilterPKdPKfS2_Pf
.p2align 8
.type _Z10timeFilterPKdPKfS2_Pf,@function
_Z10timeFilterPKdPKfS2_Pf:
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_clause 0x2
s_load_b64 s[10:11], s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////... | .text
.file "timeFilter.hip"
.globl _Z25__device_stub__timeFilterPKdPKfS2_Pf # -- Begin function _Z25__device_stub__timeFilterPKdPKfS2_Pf
.p2align 4, 0x90
.type _Z25__device_stub__timeFilterPKdPKfS2_Pf,@function
_Z25__device_stub__timeFilterPKdPKfS2_Pf: # @_Z25__device_stub__timeFilterPKdPKfS2_Pf
.cfi_startproc
# %bb.0... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00158dba_00000000-6_timeFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "timeFilter.hip"
.globl _Z25__device_stub__timeFilterPKdPKfS2_Pf # -- Begin function _Z25__device_stub__timeFilterPKdPKfS2_Pf
.p2align 4, 0x90
.type _Z25__device_stub__timeFilterPKdPKfS2_Pf,@function
_Z25__device_stub__timeFilterPKdPKfS2_Pf: # @_Z25__device_stub__timeFilterPKdPKfS2_Pf
.cfi_startproc
# %bb.0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid under NVE ensemble;
Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms of the GNU General Public License.*/
#include <stdio.h>
#include <s... | .file "tmpxft_00027b09_00000000-6_md_teacher.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid under NVE ensemble;
Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms of the GNU General Public License.*/
#include <stdio.h>
#include <s... | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid under NVE ensemble;
Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms of the GNU General Public License.*/
#include <stdio.h>
#include <s... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0] ;
... | .file "tmpxft_001b94f5_00000000-6_histo1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0] ;
... | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0]... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0]... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5histoPiPKii
.globl _Z5histoPiPKii
.p2align 8
.type _Z5histoPiPKii,@function
_Z5histoPiPKii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b64 s[0:1], src_shared... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0]... | .text
.file "histo1.hip"
.globl _Z20__device_stub__histoPiPKii # -- Begin function _Z20__device_stub__histoPiPKii
.p2align 4, 0x90
.type _Z20__device_stub__histoPiPKii,@function
_Z20__device_stub__histoPiPKii: # @_Z20__device_stub__histoPiPKii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
mov... |
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