system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel(float *output, float *input, float *target, int nframe, int dim, int sizeaverage, float *positiveWeight)
{
__shared__ float buffer[MULTIMARGIN_THREADS];
int k = blockIdx.x;
float *input_k = input + k*dim;
float *output_k = output + k;
int target_k = ((int)target[k])-1;
int i_start = threadIdx.x;
int i_end = dim;
int i_step = blockDim.x;
buffer[threadIdx.x] = 0;
for(int i = i_start; i < i_end; i += i_step)
{
float y = (i==target_k) ? 1.0 : -1.0;
float z = 1 - input_k[i]*y;
if(z > 0){
float weight = (i==target_k) ? positiveWeight[i] : 1.0;
buffer[threadIdx.x] += z*weight;
}
}
__syncthreads();
// reduce
if (threadIdx.x == 0)
{
float sum = 0;
for (int i=0; i<blockDim.x; i++)
sum += buffer[i];
if(sizeaverage)
*output_k = sum/dim;
else
*output_k = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.globl _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.p2align 8
.type _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_,@function
_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s9, s[0:1], 0x3c
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
s_mov_b32 s10, exec_lo
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s9, 0xffff
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_7
s_load_b128 s[12:15], s[0:1], 0x8
s_mul_i32 s6, s4, s3
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, v0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[6:7], 2
s_load_b64 s[6:7], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_add_u32 s11, s12, s16
s_addc_u32 s12, s13, s17
s_lshl_b64 s[16:17], s[4:5], 2
s_mov_b32 s13, 0
s_add_u32 s14, s14, s16
s_addc_u32 s15, s15, s17
s_load_b32 s2, s[14:15], 0x0
s_lshl_b32 s14, s8, 2
s_mov_b32 s15, s13
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v4, s2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v2 :: v_dual_add_nc_u32 v4, -1, v4
v_mov_b32_e32 v2, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
ds_load_b32 v8, v1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v8, v6, v7
ds_store_b32 v1, v8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v5, s8, v5
v_add_co_u32 v2, s2, v2, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s13, v3, s2
v_cmp_le_i32_e32 vcc_lo, s3, v5
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_7
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, s11, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s12, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v4, v5
s_mov_b32 s16, exec_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v6, -v6, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, 1.0, v6
v_cmpx_lt_f32_e32 0, v6
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v7, 1.0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v7, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v3, vcc_lo
global_load_b32 v7, v[7:8], off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_14
v_cmp_eq_u16_e64 s2, s9, 0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_11
s_mov_b32 s2, 0
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s2
s_add_i32 s8, s8, -1
s_add_i32 s2, s2, 4
s_cmp_eq_u32 s8, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
s_cbranch_scc0 .LBB0_10
.LBB0_11:
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s2, 0
s_cbranch_scc0 .LBB0_13
v_cvt_f32_i32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v2, null, v1, v1, v0
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v0, v1, v0
v_mul_f32_e32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v5, v4
v_fmac_f32_e32 v5, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v5, v4
v_div_fmas_f32 v2, v2, v3, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v2, v1, v0
.LBB0_13:
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, .Lfunc_end0-_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel(float *output, float *input, float *target, int nframe, int dim, int sizeaverage, float *positiveWeight)
{
__shared__ float buffer[MULTIMARGIN_THREADS];
int k = blockIdx.x;
float *input_k = input + k*dim;
float *output_k = output + k;
int target_k = ((int)target[k])-1;
int i_start = threadIdx.x;
int i_end = dim;
int i_step = blockDim.x;
buffer[threadIdx.x] = 0;
for(int i = i_start; i < i_end; i += i_step)
{
float y = (i==target_k) ? 1.0 : -1.0;
float z = 1 - input_k[i]*y;
if(z > 0){
float weight = (i==target_k) ? positiveWeight[i] : 1.0;
buffer[threadIdx.x] += z*weight;
}
}
__syncthreads();
// reduce
if (threadIdx.x == 0)
{
float sum = 0;
for (int i=0; i<blockDim.x; i++)
sum += buffer[i];
if(sizeaverage)
*output_k = sum/dim;
else
*output_k = sum;
}
} | .text
.file "cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel.hip"
.globl _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_ # -- Begin function _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.p2align 4, 0x90
.type _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_,@function
_Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_: # @_Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, .Lfunc_end0-_Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_,@object # @_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.section .rodata,"a",@progbits
.globl _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.p2align 3, 0x0
_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_:
.quad _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.size _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_"
.size .L__unnamed_1, 69
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012fc8c_00000000-6_cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_
.type _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_, @function
_Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_, .-_Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_
.globl _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.type _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, @function
_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, .-_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel.hip"
.globl _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_ # -- Begin function _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.p2align 4, 0x90
.type _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_,@function
_Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_: # @_Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, .Lfunc_end0-_Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_,@object # @_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.section .rodata,"a",@progbits
.globl _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.p2align 3, 0x0
_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_:
.quad _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.size _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_"
.size .L__unnamed_1, 69
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z68__device_stub__cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
/*
Aqui se defina la funcion que se quiere integrar
*/
double funcion(double x){
return 4/(1+x*x); // mofificar con la funcion deseada
}
__global__
void aproxIntegral( double (*f)(double), double a, double b , long n, double *result ){
double suma, tiempoInicio, tiempoEjecucion, resultado;
int i = blockDim.x * blockIdx.x + threadIdx.x;
if ( i < n ) *result+=(*f)(a+i*(b-a)/n);
}
int main(){
int N = 10;
int nblocks = (N+255) / 256;
double a;
aproxIntegral<<<nblocks, 256>>>(funcion, 0, 1, N, &a);
printf("> Result %lf", a );
return 0;
} | code for sm_80
Function : _Z13aproxIntegralPFddEddlPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F.F64.S64 R4, c[0x0][0x178] ; /* 0x00005e0000047b12 */
/* 0x000e220000301c00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*00a0*/ BSSY B0, 0x220 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fc600078e00ff */
/*00d0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*00e0*/ DFMA R2, -R4, R6, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000106 */
/*00f0*/ DFMA R8, R2, R2, R2 ; /* 0x000000020208722b */
/* 0x0010480000000002 */
/*0100*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x001e240000201c00 */
/*0110*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x002e480000000006 */
/*0120*/ DADD R6, R10, -c[0x0][0x168] ; /* 0x80005a000a067629 */
/* 0x000e080000000000 */
/*0130*/ DFMA R10, -R4, R8, 1 ; /* 0x3ff00000040a742b */
/* 0x002e480000000108 */
/*0140*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x001fc80000000000 */
/*0150*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x002e0c0000000008 */
/*0160*/ DMUL R2, R6, R10 ; /* 0x0000000a06027228 */
/* 0x001e220000000000 */
/*0170*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0180*/ DFMA R8, -R4, R2, R6 ; /* 0x000000020408722b */
/* 0x001e0c0000000106 */
/*0190*/ DFMA R2, R10, R8, R2 ; /* 0x000000080a02722b */
/* 0x001e140000000002 */
/*01a0*/ FFMA R8, RZ, R5, R3 ; /* 0x00000005ff087223 */
/* 0x001fca0000000003 */
/*01b0*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*01c0*/ @P0 BRA P1, 0x210 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01d0*/ MOV R0, 0x1f0 ; /* 0x000001f000007802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x2f0 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ DADD R4, R2, c[0x0][0x168] ; /* 0x00005a0002047629 */
/* 0x0000620000000000 */
/*0230*/ MOV R20, 0x290 ; /* 0x0000029000147802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe200078e00ff */
/*0250*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; /* 0x00000000ff157424 */
/* 0x000fc800078e00ff */
/*0280*/ CALL.REL.NOINC R2 0x0 ; /* 0xfffffd7002007344 */
/* 0x002fea0003c3ffff */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*02b0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000002402067981 */
/* 0x000ea4000c1e1b00 */
/*02c0*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0e0000000006 */
/*02d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b24 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0300*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R2, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05027812 */
/* 0x000fe200078ec0ff */
/*0320*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0b7424 */
/* 0x000fe200078e00ff */
/*0330*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0340*/ BSSY B1, 0x880 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*0350*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0370*/ LOP3.LUT R10, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070a7812 */
/* 0x000fe400078ec0ff */
/*0380*/ LOP3.LUT R15, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050f7812 */
/* 0x000fc600078ec0ff */
/*0390*/ @!P0 DMUL R2, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004028828 */
/* 0x000e220000000000 */
/*03a0*/ ISETP.GE.U32.AND P1, PT, R10.reuse, R15, PT ; /* 0x0000000f0a00720c */
/* 0x040fe20003f26070 */
/*03b0*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e000a */
/*03c0*/ @!P2 LOP3.LUT R9, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000509a812 */
/* 0x000fe200078ec0ff */
/*03d0*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*03e0*/ MUFU.RCP64H R13, R3 ; /* 0x00000003000d7308 */
/* 0x001e220000001800 */
/*03f0*/ SEL R17, R11, 0x63400000, !P1 ; /* 0x634000000b117807 */
/* 0x000fe40004800000 */
/*0400*/ @!P2 ISETP.GE.U32.AND P3, PT, R10, R9, PT ; /* 0x000000090a00a20c */
/* 0x000fe40003f66070 */
/*0410*/ @!P0 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030f8812 */
/* 0x000fc400078ec0ff */
/*0420*/ @!P2 SEL R21, R11, 0x63400000, !P3 ; /* 0x634000000b15a807 */
/* 0x000fe40005800000 */
/*0430*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe40007ffe0ff */
/*0440*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fe200078ef807 */
/*0450*/ DFMA R8, R12, -R2, 1 ; /* 0x3ff000000c08742b */
/* 0x001e0c0000000802 */
/*0460*/ DFMA R18, R8, R8, R8 ; /* 0x000000080812722b */
/* 0x0010640000000008 */
/*0470*/ LOP3.LUT R9, R17, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff11097812 */
/* 0x001fe200078ef807 */
/*0480*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0490*/ @!P2 LOP3.LUT R17, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001511a812 */
/* 0x000fe400078efcff */
/*04a0*/ DFMA R12, R12, R18, R12 ; /* 0x000000120c0c722b */
/* 0x002e08000000000c */
/*04b0*/ @!P2 DFMA R8, R8, 2, -R16 ; /* 0x400000000808a82b */
/* 0x000e480000000810 */
/*04c0*/ DFMA R16, R12, -R2, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c0000000802 */
/*04d0*/ @!P2 LOP3.LUT R14, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ea812 */
/* 0x002fe200078ec0ff */
/*04e0*/ DFMA R12, R12, R16, R12 ; /* 0x000000100c0c722b */
/* 0x001e06000000000c */
/*04f0*/ IADD3 R18, R14, -0x1, RZ ; /* 0xffffffff0e127810 */
/* 0x000fc60007ffe0ff */
/*0500*/ DMUL R16, R12, R8 ; /* 0x000000080c107228 */
/* 0x001e220000000000 */
/*0510*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc80003f04070 */
/*0520*/ ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ; /* 0x7feffffe1400780c */
/* 0x000fe20000704470 */
/*0530*/ DFMA R18, R16, -R2, R8 ; /* 0x800000021012722b */
/* 0x001e0c0000000008 */
/*0540*/ DFMA R12, R12, R18, R16 ; /* 0x000000120c0c722b */
/* 0x00104c0000000010 */
/*0550*/ @P0 BRA 0x720 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0560*/ LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005077812 */
/* 0x003fc800078ec0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R10.reuse, R7, PT ; /* 0x000000070a00720c */
/* 0x040fe20003f06070 */
/*0580*/ IMAD.IADD R6, R10, 0x1, -R7 ; /* 0x000000010a067824 */
/* 0x000fc600078e0a07 */
/*0590*/ SEL R11, R11, 0x63400000, !P0 ; /* 0x634000000b0b7807 */
/* 0x000fe40004000000 */
/*05a0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*05b0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*05c0*/ IMAD.IADD R14, R6, 0x1, -R11 ; /* 0x00000001060e7824 */
/* 0x000fe400078e0a0b */
/*05d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05e0*/ IADD3 R7, R14, 0x7fe00000, RZ ; /* 0x7fe000000e077810 */
/* 0x000fcc0007ffe0ff */
/*05f0*/ DMUL R10, R12, R6 ; /* 0x000000060c0a7228 */
/* 0x000e140000000000 */
/*0600*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*0610*/ @P0 BRA 0x870 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0620*/ DFMA R2, R12, -R2, R8 ; /* 0x800000020c02722b */
/* 0x000e220000000008 */
/*0630*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0640*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0650*/ LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ; /* 0x8000000003057812 */
/* 0x000fc800078e4805 */
/*0660*/ LOP3.LUT R7, R5, R7, RZ, 0xfc, !PT ; /* 0x0000000705077212 */
/* 0x000fce00078efcff */
/*0670*/ @!P0 BRA 0x870 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*0690*/ DMUL.RP R6, R12, R6 ; /* 0x000000060c067228 */
/* 0x000e220000008000 */
/*06a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*06b0*/ DFMA R2, R10, -R2, R12 ; /* 0x800000020a02722b */
/* 0x000e46000000000c */
/*06c0*/ LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ; /* 0x0000000507057212 */
/* 0x001fc600078e3cff */
/*06d0*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*06e0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*06f0*/ FSEL R10, R6, R10, !P0 ; /* 0x0000000a060a7208 */
/* 0x000fe40004000000 */
/*0700*/ FSEL R11, R5, R11, !P0 ; /* 0x0000000b050b7208 */
/* 0x000fe20004000000 */
/*0710*/ BRA 0x870 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0730*/ @P0 BRA 0x850 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0740*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e1c0003f08000 */
/*0750*/ @P0 BRA 0x820 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0760*/ ISETP.NE.AND P0, PT, R14, R15, PT ; /* 0x0000000f0e00720c */
/* 0x000fe20003f05270 */
/*0770*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x000fd400078e00ff */
/*0790*/ @!P0 BRA 0x870 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.NE.AND P0, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fe40003f05270 */
/*07b0*/ LOP3.LUT R11, R7, 0x80000000, R5, 0x48, !PT ; /* 0x80000000070b7812 */
/* 0x000fe400078e4805 */
/*07c0*/ ISETP.EQ.OR P0, PT, R15, RZ, !P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0004702670 */
/*07d0*/ @P0 LOP3.LUT R2, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b020812 */
/* 0x000fe200078efcff */
/*07e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*07f0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0800*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0002 */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R11, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050b7812 */
/* 0x000fe200078efcff */
/*0830*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*0840*/ BRA 0x870 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0850*/ LOP3.LUT R11, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070b7812 */
/* 0x000fe200078efcff */
/*0860*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0890*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08a0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff75002007950 */
/* 0x000fea0003c3ffff */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
/*
Aqui se defina la funcion que se quiere integrar
*/
double funcion(double x){
return 4/(1+x*x); // mofificar con la funcion deseada
}
__global__
void aproxIntegral( double (*f)(double), double a, double b , long n, double *result ){
double suma, tiempoInicio, tiempoEjecucion, resultado;
int i = blockDim.x * blockIdx.x + threadIdx.x;
if ( i < n ) *result+=(*f)(a+i*(b-a)/n);
}
int main(){
int N = 10;
int nblocks = (N+255) / 256;
double a;
aproxIntegral<<<nblocks, 256>>>(funcion, 0, 1, N, &a);
printf("> Result %lf", a );
return 0;
} | .file "tmpxft_0013fecd_00000000-6_integrals.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z7funciond
.type _Z7funciond, @function
_Z7funciond:
.LFB2057:
.cfi_startproc
endbr64
mulsd %xmm0, %xmm0
addsd .LC0(%rip), %xmm0
movsd .LC1(%rip), %xmm1
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z7funciond, .-_Z7funciond
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
.type _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd, @function
_Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13aproxIntegralPFddEddlPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd, .-_Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
.globl _Z13aproxIntegralPFddEddlPd
.type _Z13aproxIntegralPFddEddlPd, @function
_Z13aproxIntegralPFddEddlPd:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13aproxIntegralPFddEddlPd, .-_Z13aproxIntegralPFddEddlPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "> Result %lf"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq 8(%rsp), %rdx
movl $10, %esi
movsd .LC0(%rip), %xmm1
pxor %xmm0, %xmm0
leaq _Z7funciond(%rip), %rdi
call _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13aproxIntegralPFddEddlPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13aproxIntegralPFddEddlPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.align 8
.LC1:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
/*
Aqui se defina la funcion que se quiere integrar
*/
double funcion(double x){
return 4/(1+x*x); // mofificar con la funcion deseada
}
__global__
void aproxIntegral( double (*f)(double), double a, double b , long n, double *result ){
double suma, tiempoInicio, tiempoEjecucion, resultado;
int i = blockDim.x * blockIdx.x + threadIdx.x;
if ( i < n ) *result+=(*f)(a+i*(b-a)/n);
}
int main(){
int N = 10;
int nblocks = (N+255) / 256;
double a;
aproxIntegral<<<nblocks, 256>>>(funcion, 0, 1, N, &a);
printf("> Result %lf", a );
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
Aqui se defina la funcion que se quiere integrar
*/
double funcion(double x){
return 4/(1+x*x); // mofificar con la funcion deseada
}
__global__
void aproxIntegral( double (*f)(double), double a, double b , long n, double *result ){
double suma, tiempoInicio, tiempoEjecucion, resultado;
int i = blockDim.x * blockIdx.x + threadIdx.x;
if ( i < n ) *result+=(*f)(a+i*(b-a)/n);
}
int main(){
int N = 10;
int nblocks = (N+255) / 256;
double a;
aproxIntegral<<<nblocks, 256>>>(funcion, 0, 1, N, &a);
printf("> Result %lf", a );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
Aqui se defina la funcion que se quiere integrar
*/
double funcion(double x){
return 4/(1+x*x); // mofificar con la funcion deseada
}
__global__
void aproxIntegral( double (*f)(double), double a, double b , long n, double *result ){
double suma, tiempoInicio, tiempoEjecucion, resultado;
int i = blockDim.x * blockIdx.x + threadIdx.x;
if ( i < n ) *result+=(*f)(a+i*(b-a)/n);
}
int main(){
int N = 10;
int nblocks = (N+255) / 256;
double a;
aproxIntegral<<<nblocks, 256>>>(funcion, 0, 1, N, &a);
printf("> Result %lf", a );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13aproxIntegralPFddEddlPd
.globl _Z13aproxIntegralPFddEddlPd
.p2align 8
.type _Z13aproxIntegralPFddEddlPd,@function
_Z13aproxIntegralPFddEddlPd:
s_mov_b64 s[10:11], s[4:5]
s_clause 0x1
s_load_b32 s6, s[2:3], 0x34
s_load_b64 s[4:5], s[2:3], 0x18
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s32, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s13, s6, v[3:4]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[2:3], s5
s_clause 0x1
s_load_b128 s[16:19], s[2:3], 0x0
s_load_b64 s[6:7], s[2:3], 0x10
v_cvt_f64_i32_e32 v[4:5], v1
v_cvt_f64_u32_e32 v[6:7], s4
s_load_b64 s[34:35], s[2:3], 0x20
v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v31, v0
s_add_u32 s8, s2, 40
s_addc_u32 s9, s3, 0
s_mov_b64 s[4:5], s[0:1]
s_mov_b32 s12, s13
s_mov_b32 s13, s14
s_mov_b32 s14, s15
s_waitcnt lgkmcnt(0)
v_add_f64 v[8:9], s[6:7], -s[18:19]
v_ldexp_f64 v[1:2], v[2:3], 32
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[3:4], v[8:9], v[4:5]
v_add_f64 v[1:2], v[1:2], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[5:6], null, v[1:2], v[1:2], v[3:4]
v_div_scale_f64 v[11:12], vcc_lo, v[3:4], v[1:2], v[3:4]
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_mul_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[5:6], v[1:2], v[3:4]
v_add_f64 v[1:2], v[1:2], s[18:19]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v2
s_swappc_b64 s[30:31], s[16:17]
global_load_b64 v[2:3], v40, s[34:35]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v40, v[0:1], s[34:35]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13aproxIntegralPFddEddlPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 1
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 1
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 41
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13aproxIntegralPFddEddlPd, .Lfunc_end0-_Z13aproxIntegralPFddEddlPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 120
.size: 8
.value_kind: hidden_hostcall_buffer
- .offset: 128
.size: 8
.value_kind: hidden_multigrid_sync_arg
- .offset: 136
.size: 8
.value_kind: hidden_heap_v1
- .offset: 144
.size: 8
.value_kind: hidden_default_queue
- .offset: 240
.size: 8
.value_kind: hidden_queue_ptr
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13aproxIntegralPFddEddlPd
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z13aproxIntegralPFddEddlPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: true
.vgpr_count: 41
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
Aqui se defina la funcion que se quiere integrar
*/
double funcion(double x){
return 4/(1+x*x); // mofificar con la funcion deseada
}
__global__
void aproxIntegral( double (*f)(double), double a, double b , long n, double *result ){
double suma, tiempoInicio, tiempoEjecucion, resultado;
int i = blockDim.x * blockIdx.x + threadIdx.x;
if ( i < n ) *result+=(*f)(a+i*(b-a)/n);
}
int main(){
int N = 10;
int nblocks = (N+255) / 256;
double a;
aproxIntegral<<<nblocks, 256>>>(funcion, 0, 1, N, &a);
printf("> Result %lf", a );
return 0;
} | .text
.file "integrals.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7funciond
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0x4010000000000000 # double 4
.text
.globl _Z7funciond
.p2align 4, 0x90
.type _Z7funciond,@function
_Z7funciond: # @_Z7funciond
.cfi_startproc
# %bb.0:
mulsd %xmm0, %xmm0
addsd .LCPI0_0(%rip), %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z7funciond, .Lfunc_end0-_Z7funciond
.cfi_endproc
# -- End function
.globl _Z28__device_stub__aproxIntegralPFddEddlPd # -- Begin function _Z28__device_stub__aproxIntegralPFddEddlPd
.p2align 4, 0x90
.type _Z28__device_stub__aproxIntegralPFddEddlPd,@function
_Z28__device_stub__aproxIntegralPFddEddlPd: # @_Z28__device_stub__aproxIntegralPFddEddlPd
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13aproxIntegralPFddEddlPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z28__device_stub__aproxIntegralPFddEddlPd, .Lfunc_end1-_Z28__device_stub__aproxIntegralPFddEddlPd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq $_Z7funciond, 88(%rsp)
movq $0, 80(%rsp)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 72(%rsp)
movq $10, 64(%rsp)
movq %rsp, %rax
movq %rax, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13aproxIntegralPFddEddlPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13aproxIntegralPFddEddlPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13aproxIntegralPFddEddlPd,@object # @_Z13aproxIntegralPFddEddlPd
.section .rodata,"a",@progbits
.globl _Z13aproxIntegralPFddEddlPd
.p2align 3, 0x0
_Z13aproxIntegralPFddEddlPd:
.quad _Z28__device_stub__aproxIntegralPFddEddlPd
.size _Z13aproxIntegralPFddEddlPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "> Result %lf"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13aproxIntegralPFddEddlPd"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z7funciond
.addrsig_sym _Z28__device_stub__aproxIntegralPFddEddlPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13aproxIntegralPFddEddlPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13aproxIntegralPFddEddlPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F.F64.S64 R4, c[0x0][0x178] ; /* 0x00005e0000047b12 */
/* 0x000e220000301c00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*00a0*/ BSSY B0, 0x220 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fc600078e00ff */
/*00d0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*00e0*/ DFMA R2, -R4, R6, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000106 */
/*00f0*/ DFMA R8, R2, R2, R2 ; /* 0x000000020208722b */
/* 0x0010480000000002 */
/*0100*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x001e240000201c00 */
/*0110*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x002e480000000006 */
/*0120*/ DADD R6, R10, -c[0x0][0x168] ; /* 0x80005a000a067629 */
/* 0x000e080000000000 */
/*0130*/ DFMA R10, -R4, R8, 1 ; /* 0x3ff00000040a742b */
/* 0x002e480000000108 */
/*0140*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x001fc80000000000 */
/*0150*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x002e0c0000000008 */
/*0160*/ DMUL R2, R6, R10 ; /* 0x0000000a06027228 */
/* 0x001e220000000000 */
/*0170*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0180*/ DFMA R8, -R4, R2, R6 ; /* 0x000000020408722b */
/* 0x001e0c0000000106 */
/*0190*/ DFMA R2, R10, R8, R2 ; /* 0x000000080a02722b */
/* 0x001e140000000002 */
/*01a0*/ FFMA R8, RZ, R5, R3 ; /* 0x00000005ff087223 */
/* 0x001fca0000000003 */
/*01b0*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*01c0*/ @P0 BRA P1, 0x210 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01d0*/ MOV R0, 0x1f0 ; /* 0x000001f000007802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x2f0 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ DADD R4, R2, c[0x0][0x168] ; /* 0x00005a0002047629 */
/* 0x0000620000000000 */
/*0230*/ MOV R20, 0x290 ; /* 0x0000029000147802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe200078e00ff */
/*0250*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; /* 0x00000000ff157424 */
/* 0x000fc800078e00ff */
/*0280*/ CALL.REL.NOINC R2 0x0 ; /* 0xfffffd7002007344 */
/* 0x002fea0003c3ffff */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*02b0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000002402067981 */
/* 0x000ea4000c1e1b00 */
/*02c0*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0e0000000006 */
/*02d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b24 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0300*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R2, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05027812 */
/* 0x000fe200078ec0ff */
/*0320*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0b7424 */
/* 0x000fe200078e00ff */
/*0330*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0340*/ BSSY B1, 0x880 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*0350*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0360*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0370*/ LOP3.LUT R10, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070a7812 */
/* 0x000fe400078ec0ff */
/*0380*/ LOP3.LUT R15, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050f7812 */
/* 0x000fc600078ec0ff */
/*0390*/ @!P0 DMUL R2, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004028828 */
/* 0x000e220000000000 */
/*03a0*/ ISETP.GE.U32.AND P1, PT, R10.reuse, R15, PT ; /* 0x0000000f0a00720c */
/* 0x040fe20003f26070 */
/*03b0*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e000a */
/*03c0*/ @!P2 LOP3.LUT R9, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000509a812 */
/* 0x000fe200078ec0ff */
/*03d0*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*03e0*/ MUFU.RCP64H R13, R3 ; /* 0x00000003000d7308 */
/* 0x001e220000001800 */
/*03f0*/ SEL R17, R11, 0x63400000, !P1 ; /* 0x634000000b117807 */
/* 0x000fe40004800000 */
/*0400*/ @!P2 ISETP.GE.U32.AND P3, PT, R10, R9, PT ; /* 0x000000090a00a20c */
/* 0x000fe40003f66070 */
/*0410*/ @!P0 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030f8812 */
/* 0x000fc400078ec0ff */
/*0420*/ @!P2 SEL R21, R11, 0x63400000, !P3 ; /* 0x634000000b15a807 */
/* 0x000fe40005800000 */
/*0430*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe40007ffe0ff */
/*0440*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fe200078ef807 */
/*0450*/ DFMA R8, R12, -R2, 1 ; /* 0x3ff000000c08742b */
/* 0x001e0c0000000802 */
/*0460*/ DFMA R18, R8, R8, R8 ; /* 0x000000080812722b */
/* 0x0010640000000008 */
/*0470*/ LOP3.LUT R9, R17, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff11097812 */
/* 0x001fe200078ef807 */
/*0480*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0490*/ @!P2 LOP3.LUT R17, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001511a812 */
/* 0x000fe400078efcff */
/*04a0*/ DFMA R12, R12, R18, R12 ; /* 0x000000120c0c722b */
/* 0x002e08000000000c */
/*04b0*/ @!P2 DFMA R8, R8, 2, -R16 ; /* 0x400000000808a82b */
/* 0x000e480000000810 */
/*04c0*/ DFMA R16, R12, -R2, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c0000000802 */
/*04d0*/ @!P2 LOP3.LUT R14, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ea812 */
/* 0x002fe200078ec0ff */
/*04e0*/ DFMA R12, R12, R16, R12 ; /* 0x000000100c0c722b */
/* 0x001e06000000000c */
/*04f0*/ IADD3 R18, R14, -0x1, RZ ; /* 0xffffffff0e127810 */
/* 0x000fc60007ffe0ff */
/*0500*/ DMUL R16, R12, R8 ; /* 0x000000080c107228 */
/* 0x001e220000000000 */
/*0510*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc80003f04070 */
/*0520*/ ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ; /* 0x7feffffe1400780c */
/* 0x000fe20000704470 */
/*0530*/ DFMA R18, R16, -R2, R8 ; /* 0x800000021012722b */
/* 0x001e0c0000000008 */
/*0540*/ DFMA R12, R12, R18, R16 ; /* 0x000000120c0c722b */
/* 0x00104c0000000010 */
/*0550*/ @P0 BRA 0x720 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0560*/ LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005077812 */
/* 0x003fc800078ec0ff */
/*0570*/ ISETP.GE.U32.AND P0, PT, R10.reuse, R7, PT ; /* 0x000000070a00720c */
/* 0x040fe20003f06070 */
/*0580*/ IMAD.IADD R6, R10, 0x1, -R7 ; /* 0x000000010a067824 */
/* 0x000fc600078e0a07 */
/*0590*/ SEL R11, R11, 0x63400000, !P0 ; /* 0x634000000b0b7807 */
/* 0x000fe40004000000 */
/*05a0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*05b0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*05c0*/ IMAD.IADD R14, R6, 0x1, -R11 ; /* 0x00000001060e7824 */
/* 0x000fe400078e0a0b */
/*05d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*05e0*/ IADD3 R7, R14, 0x7fe00000, RZ ; /* 0x7fe000000e077810 */
/* 0x000fcc0007ffe0ff */
/*05f0*/ DMUL R10, R12, R6 ; /* 0x000000060c0a7228 */
/* 0x000e140000000000 */
/*0600*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*0610*/ @P0 BRA 0x870 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0620*/ DFMA R2, R12, -R2, R8 ; /* 0x800000020c02722b */
/* 0x000e220000000008 */
/*0630*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0640*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0650*/ LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ; /* 0x8000000003057812 */
/* 0x000fc800078e4805 */
/*0660*/ LOP3.LUT R7, R5, R7, RZ, 0xfc, !PT ; /* 0x0000000705077212 */
/* 0x000fce00078efcff */
/*0670*/ @!P0 BRA 0x870 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*0690*/ DMUL.RP R6, R12, R6 ; /* 0x000000060c067228 */
/* 0x000e220000008000 */
/*06a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*06b0*/ DFMA R2, R10, -R2, R12 ; /* 0x800000020a02722b */
/* 0x000e46000000000c */
/*06c0*/ LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ; /* 0x0000000507057212 */
/* 0x001fc600078e3cff */
/*06d0*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*06e0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*06f0*/ FSEL R10, R6, R10, !P0 ; /* 0x0000000a060a7208 */
/* 0x000fe40004000000 */
/*0700*/ FSEL R11, R5, R11, !P0 ; /* 0x0000000b050b7208 */
/* 0x000fe20004000000 */
/*0710*/ BRA 0x870 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0720*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0730*/ @P0 BRA 0x850 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0740*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e1c0003f08000 */
/*0750*/ @P0 BRA 0x820 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0760*/ ISETP.NE.AND P0, PT, R14, R15, PT ; /* 0x0000000f0e00720c */
/* 0x000fe20003f05270 */
/*0770*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x000fd400078e00ff */
/*0790*/ @!P0 BRA 0x870 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.NE.AND P0, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fe40003f05270 */
/*07b0*/ LOP3.LUT R11, R7, 0x80000000, R5, 0x48, !PT ; /* 0x80000000070b7812 */
/* 0x000fe400078e4805 */
/*07c0*/ ISETP.EQ.OR P0, PT, R15, RZ, !P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0004702670 */
/*07d0*/ @P0 LOP3.LUT R2, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b020812 */
/* 0x000fe200078efcff */
/*07e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*07f0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0800*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0002 */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R11, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050b7812 */
/* 0x000fe200078efcff */
/*0830*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*0840*/ BRA 0x870 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0850*/ LOP3.LUT R11, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070b7812 */
/* 0x000fe200078efcff */
/*0860*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0890*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08a0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff75002007950 */
/* 0x000fea0003c3ffff */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13aproxIntegralPFddEddlPd
.globl _Z13aproxIntegralPFddEddlPd
.p2align 8
.type _Z13aproxIntegralPFddEddlPd,@function
_Z13aproxIntegralPFddEddlPd:
s_mov_b64 s[10:11], s[4:5]
s_clause 0x1
s_load_b32 s6, s[2:3], 0x34
s_load_b64 s[4:5], s[2:3], 0x18
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s32, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s13, s6, v[3:4]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[2:3], s5
s_clause 0x1
s_load_b128 s[16:19], s[2:3], 0x0
s_load_b64 s[6:7], s[2:3], 0x10
v_cvt_f64_i32_e32 v[4:5], v1
v_cvt_f64_u32_e32 v[6:7], s4
s_load_b64 s[34:35], s[2:3], 0x20
v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v31, v0
s_add_u32 s8, s2, 40
s_addc_u32 s9, s3, 0
s_mov_b64 s[4:5], s[0:1]
s_mov_b32 s12, s13
s_mov_b32 s13, s14
s_mov_b32 s14, s15
s_waitcnt lgkmcnt(0)
v_add_f64 v[8:9], s[6:7], -s[18:19]
v_ldexp_f64 v[1:2], v[2:3], 32
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[3:4], v[8:9], v[4:5]
v_add_f64 v[1:2], v[1:2], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[5:6], null, v[1:2], v[1:2], v[3:4]
v_div_scale_f64 v[11:12], vcc_lo, v[3:4], v[1:2], v[3:4]
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_mul_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[5:6], v[1:2], v[3:4]
v_add_f64 v[1:2], v[1:2], s[18:19]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v1, v2
s_swappc_b64 s[30:31], s[16:17]
global_load_b64 v[2:3], v40, s[34:35]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v40, v[0:1], s[34:35]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13aproxIntegralPFddEddlPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 1
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 1
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 41
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13aproxIntegralPFddEddlPd, .Lfunc_end0-_Z13aproxIntegralPFddEddlPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 120
.size: 8
.value_kind: hidden_hostcall_buffer
- .offset: 128
.size: 8
.value_kind: hidden_multigrid_sync_arg
- .offset: 136
.size: 8
.value_kind: hidden_heap_v1
- .offset: 144
.size: 8
.value_kind: hidden_default_queue
- .offset: 240
.size: 8
.value_kind: hidden_queue_ptr
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13aproxIntegralPFddEddlPd
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z13aproxIntegralPFddEddlPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: true
.vgpr_count: 41
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013fecd_00000000-6_integrals.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z7funciond
.type _Z7funciond, @function
_Z7funciond:
.LFB2057:
.cfi_startproc
endbr64
mulsd %xmm0, %xmm0
addsd .LC0(%rip), %xmm0
movsd .LC1(%rip), %xmm1
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z7funciond, .-_Z7funciond
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
.type _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd, @function
_Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13aproxIntegralPFddEddlPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd, .-_Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
.globl _Z13aproxIntegralPFddEddlPd
.type _Z13aproxIntegralPFddEddlPd, @function
_Z13aproxIntegralPFddEddlPd:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13aproxIntegralPFddEddlPd, .-_Z13aproxIntegralPFddEddlPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "> Result %lf"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq 8(%rsp), %rdx
movl $10, %esi
movsd .LC0(%rip), %xmm1
pxor %xmm0, %xmm0
leaq _Z7funciond(%rip), %rdi
call _Z41__device_stub__Z13aproxIntegralPFddEddlPdPFddEddlPd
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13aproxIntegralPFddEddlPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13aproxIntegralPFddEddlPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.align 8
.LC1:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "integrals.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7funciond
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0x4010000000000000 # double 4
.text
.globl _Z7funciond
.p2align 4, 0x90
.type _Z7funciond,@function
_Z7funciond: # @_Z7funciond
.cfi_startproc
# %bb.0:
mulsd %xmm0, %xmm0
addsd .LCPI0_0(%rip), %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z7funciond, .Lfunc_end0-_Z7funciond
.cfi_endproc
# -- End function
.globl _Z28__device_stub__aproxIntegralPFddEddlPd # -- Begin function _Z28__device_stub__aproxIntegralPFddEddlPd
.p2align 4, 0x90
.type _Z28__device_stub__aproxIntegralPFddEddlPd,@function
_Z28__device_stub__aproxIntegralPFddEddlPd: # @_Z28__device_stub__aproxIntegralPFddEddlPd
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13aproxIntegralPFddEddlPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z28__device_stub__aproxIntegralPFddEddlPd, .Lfunc_end1-_Z28__device_stub__aproxIntegralPFddEddlPd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq $_Z7funciond, 88(%rsp)
movq $0, 80(%rsp)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 72(%rsp)
movq $10, 64(%rsp)
movq %rsp, %rax
movq %rax, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13aproxIntegralPFddEddlPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13aproxIntegralPFddEddlPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13aproxIntegralPFddEddlPd,@object # @_Z13aproxIntegralPFddEddlPd
.section .rodata,"a",@progbits
.globl _Z13aproxIntegralPFddEddlPd
.p2align 3, 0x0
_Z13aproxIntegralPFddEddlPd:
.quad _Z28__device_stub__aproxIntegralPFddEddlPd
.size _Z13aproxIntegralPFddEddlPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "> Result %lf"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13aproxIntegralPFddEddlPd"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z7funciond
.addrsig_sym _Z28__device_stub__aproxIntegralPFddEddlPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13aproxIntegralPFddEddlPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuComplex.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void multiply_kernel_ccc(cuFloatComplex *in1, cuFloatComplex *in2,
cuFloatComplex *out, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
float re, im;
re = in1[i].x * in2[i].x - in1[i].y * in2[i].y;
im = in1[i].x * in2[i].y + in1[i].y * in2[i].x;
out[i].x = re;
out[i].y = im;
}
}
void exec_multiply_kernel_ccc(cuFloatComplex *in1, cuFloatComplex *in2,
cuFloatComplex *out, int n, int grid_size,
int block_size, cudaStream_t stream) {
multiply_kernel_ccc<<<grid_size, block_size, 0, stream>>>(in1, in2, out, n);
}
void get_block_and_grid_multiply(int *minGrid, int *minBlock) {
cudaOccupancyMaxPotentialBlockSize(minGrid, minBlock, multiply_kernel_ccc, 0,
0);
} | code for sm_80
Function : _Z19multiply_kernel_cccP6float2S0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R3.reuse, R5.reuse ; /* 0x0000000503097220 */
/* 0x0c4fe40000400000 */
/*00e0*/ FMUL R0, R3, R4.reuse ; /* 0x0000000403007220 */
/* 0x080fe40000400000 */
/*00f0*/ FFMA R8, R2.reuse, R4, -R9 ; /* 0x0000000402087223 */
/* 0x040fe40000000809 */
/*0100*/ FFMA R9, R2, R5, R0 ; /* 0x0000000502097223 */
/* 0x000fca0000000000 */
/*0110*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x000fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuComplex.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void multiply_kernel_ccc(cuFloatComplex *in1, cuFloatComplex *in2,
cuFloatComplex *out, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
float re, im;
re = in1[i].x * in2[i].x - in1[i].y * in2[i].y;
im = in1[i].x * in2[i].y + in1[i].y * in2[i].x;
out[i].x = re;
out[i].y = im;
}
}
void exec_multiply_kernel_ccc(cuFloatComplex *in1, cuFloatComplex *in2,
cuFloatComplex *out, int n, int grid_size,
int block_size, cudaStream_t stream) {
multiply_kernel_ccc<<<grid_size, block_size, 0, stream>>>(in1, in2, out, n);
}
void get_block_and_grid_multiply(int *minGrid, int *minBlock) {
cudaOccupancyMaxPotentialBlockSize(minGrid, minBlock, multiply_kernel_ccc, 0,
0);
} | .file "tmpxft_0005560f_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27get_block_and_grid_multiplyPiS_
.type _Z27get_block_and_grid_multiplyPiS_, @function
_Z27get_block_and_grid_multiplyPiS_:
.LFB2051:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
testq %rdi, %rdi
je .L3
movq %rdi, %rbx
movq %rsi, %rbp
testq %rsi, %rsi
je .L3
leaq 40(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L14
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq 44(%rsp), %rdi
movl 40(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 48(%rsp), %rdi
movl 40(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 52(%rsp), %rdi
movl 40(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 56(%rsp), %rdi
movl 40(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 64(%rsp), %rdi
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L3
movl 44(%rsp), %esi
movl 48(%rsp), %ecx
movl 88(%rsp), %r14d
movl 52(%rsp), %eax
cmpl %eax, %r14d
cmovg %eax, %r14d
leal -1(%rcx,%r14), %eax
cltd
idivl %ecx
imull %ecx, %eax
movl %eax, %r12d
testl %eax, %eax
jle .L9
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, %r15d
movl %ecx, %r13d
movq %rbx, 16(%rsp)
movq %rbp, 24(%rsp)
movl %esi, %ebp
jmp .L7
.L6:
cmpl %r15d, %ebp
je .L12
subl %r13d, %r12d
testl %r12d, %r12d
jle .L16
.L7:
cmpl %r12d, %r14d
movl %r12d, %ebx
cmovle %r14d, %ebx
leaq 60(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L3
movl 60(%rsp), %eax
movl %ebx, %edx
imull %eax, %edx
cmpl %r15d, %edx
jle .L6
movl %edx, %r15d
movl %eax, 8(%rsp)
movl %ebx, 12(%rsp)
jmp .L6
.L16:
movq 16(%rsp), %rbx
movq 24(%rsp), %rbp
jmp .L5
.L9:
movl $0, 8(%rsp)
movl $0, 12(%rsp)
jmp .L5
.L12:
movq 16(%rsp), %rbx
movq 24(%rsp), %rbp
.L5:
movl 8(%rsp), %eax
imull 56(%rsp), %eax
movl %eax, (%rbx)
movl 12(%rsp), %eax
movl %eax, 0(%rbp)
jmp .L3
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27get_block_and_grid_multiplyPiS_, .-_Z27get_block_and_grid_multiplyPiS_
.globl _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
.type _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i, @function
_Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i:
.LFB2076:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i, .-_Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
.globl _Z19multiply_kernel_cccP6float2S0_S0_i
.type _Z19multiply_kernel_cccP6float2S0_S0_i, @function
_Z19multiply_kernel_cccP6float2S0_S0_i:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _Z19multiply_kernel_cccP6float2S0_S0_i, .-_Z19multiply_kernel_cccP6float2S0_S0_i
.globl _Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st
.type _Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st, @function
_Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st:
.LFB2050:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movl %r9d, 20(%rsp)
movl $1, 24(%rsp)
movl %r8d, 8(%rsp)
movl $1, 12(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
jmp .L25
.cfi_endproc
.LFE2050:
.size _Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st, .-_Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19multiply_kernel_cccP6float2S0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuComplex.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void multiply_kernel_ccc(cuFloatComplex *in1, cuFloatComplex *in2,
cuFloatComplex *out, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
float re, im;
re = in1[i].x * in2[i].x - in1[i].y * in2[i].y;
im = in1[i].x * in2[i].y + in1[i].y * in2[i].x;
out[i].x = re;
out[i].y = im;
}
}
void exec_multiply_kernel_ccc(cuFloatComplex *in1, cuFloatComplex *in2,
cuFloatComplex *out, int n, int grid_size,
int block_size, cudaStream_t stream) {
multiply_kernel_ccc<<<grid_size, block_size, 0, stream>>>(in1, in2, out, n);
}
void get_block_and_grid_multiply(int *minGrid, int *minBlock) {
cudaOccupancyMaxPotentialBlockSize(minGrid, minBlock, multiply_kernel_ccc, 0,
0);
} | #include <hip/hip_complex.h>
#include <hip/hip_runtime.h>
__global__ void multiply_kernel_ccc(hipFloatComplex *in1, hipFloatComplex *in2,
hipFloatComplex *out, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
float re, im;
re = in1[i].x * in2[i].x - in1[i].y * in2[i].y;
im = in1[i].x * in2[i].y + in1[i].y * in2[i].x;
out[i].x = re;
out[i].y = im;
}
}
void exec_multiply_kernel_ccc(hipFloatComplex *in1, hipFloatComplex *in2,
hipFloatComplex *out, int n, int grid_size,
int block_size, hipStream_t stream) {
multiply_kernel_ccc<<<grid_size, block_size, 0, stream>>>(in1, in2, out, n);
}
void get_block_and_grid_multiply(int *minGrid, int *minBlock) {
hipOccupancyMaxPotentialBlockSize(minGrid, minBlock, multiply_kernel_ccc, 0,
0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_complex.h>
#include <hip/hip_runtime.h>
__global__ void multiply_kernel_ccc(hipFloatComplex *in1, hipFloatComplex *in2,
hipFloatComplex *out, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
float re, im;
re = in1[i].x * in2[i].x - in1[i].y * in2[i].y;
im = in1[i].x * in2[i].y + in1[i].y * in2[i].x;
out[i].x = re;
out[i].y = im;
}
}
void exec_multiply_kernel_ccc(hipFloatComplex *in1, hipFloatComplex *in2,
hipFloatComplex *out, int n, int grid_size,
int block_size, hipStream_t stream) {
multiply_kernel_ccc<<<grid_size, block_size, 0, stream>>>(in1, in2, out, n);
}
void get_block_and_grid_multiply(int *minGrid, int *minBlock) {
hipOccupancyMaxPotentialBlockSize(minGrid, minBlock, multiply_kernel_ccc, 0,
0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.globl _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.p2align 8
.type _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i,@function
_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v6, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v3, v5 :: v_dual_fmac_f32 v6, v4, v3
v_fma_f32 v5, v2, v4, -v7
global_store_b64 v[0:1], v[5:6], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, .Lfunc_end0-_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_complex.h>
#include <hip/hip_runtime.h>
__global__ void multiply_kernel_ccc(hipFloatComplex *in1, hipFloatComplex *in2,
hipFloatComplex *out, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
float re, im;
re = in1[i].x * in2[i].x - in1[i].y * in2[i].y;
im = in1[i].x * in2[i].y + in1[i].y * in2[i].x;
out[i].x = re;
out[i].y = im;
}
}
void exec_multiply_kernel_ccc(hipFloatComplex *in1, hipFloatComplex *in2,
hipFloatComplex *out, int n, int grid_size,
int block_size, hipStream_t stream) {
multiply_kernel_ccc<<<grid_size, block_size, 0, stream>>>(in1, in2, out, n);
}
void get_block_and_grid_multiply(int *minGrid, int *minBlock) {
hipOccupancyMaxPotentialBlockSize(minGrid, minBlock, multiply_kernel_ccc, 0,
0);
} | .text
.file "multiply.hip"
.globl _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i # -- Begin function _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.p2align 4, 0x90
.type _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i,@function
_Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i: # @_Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, .Lfunc_end0-_Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.cfi_endproc
# -- End function
.globl _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t # -- Begin function _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t
.p2align 4, 0x90
.type _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t,@function
_Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t: # @_Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq 160(%rsp), %rax
movl %r8d, %edi
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rdi
movl %r9d, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq %rax, %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t, .Lfunc_end1-_Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t
.cfi_endproc
# -- End function
.globl _Z27get_block_and_grid_multiplyPiS_ # -- Begin function _Z27get_block_and_grid_multiplyPiS_
.p2align 4, 0x90
.type _Z27get_block_and_grid_multiplyPiS_,@function
_Z27get_block_and_grid_multiplyPiS_: # @_Z27get_block_and_grid_multiplyPiS_
.cfi_startproc
# %bb.0:
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
jmp hipOccupancyMaxPotentialBlockSize # TAILCALL
.Lfunc_end2:
.size _Z27get_block_and_grid_multiplyPiS_, .Lfunc_end2-_Z27get_block_and_grid_multiplyPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i,@object # @_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.section .rodata,"a",@progbits
.globl _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.p2align 3, 0x0
_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i:
.quad _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.size _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19multiply_kernel_cccP6float2S0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R3.reuse, R5.reuse ; /* 0x0000000503097220 */
/* 0x0c4fe40000400000 */
/*00e0*/ FMUL R0, R3, R4.reuse ; /* 0x0000000403007220 */
/* 0x080fe40000400000 */
/*00f0*/ FFMA R8, R2.reuse, R4, -R9 ; /* 0x0000000402087223 */
/* 0x040fe40000000809 */
/*0100*/ FFMA R9, R2, R5, R0 ; /* 0x0000000502097223 */
/* 0x000fca0000000000 */
/*0110*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x000fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.globl _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.p2align 8
.type _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i,@function
_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v6, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v3, v5 :: v_dual_fmac_f32 v6, v4, v3
v_fma_f32 v5, v2, v4, -v7
global_store_b64 v[0:1], v[5:6], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, .Lfunc_end0-_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005560f_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27get_block_and_grid_multiplyPiS_
.type _Z27get_block_and_grid_multiplyPiS_, @function
_Z27get_block_and_grid_multiplyPiS_:
.LFB2051:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
testq %rdi, %rdi
je .L3
movq %rdi, %rbx
movq %rsi, %rbp
testq %rsi, %rsi
je .L3
leaq 40(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L14
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq 44(%rsp), %rdi
movl 40(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 48(%rsp), %rdi
movl 40(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 52(%rsp), %rdi
movl 40(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 56(%rsp), %rdi
movl 40(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 64(%rsp), %rdi
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L3
movl 44(%rsp), %esi
movl 48(%rsp), %ecx
movl 88(%rsp), %r14d
movl 52(%rsp), %eax
cmpl %eax, %r14d
cmovg %eax, %r14d
leal -1(%rcx,%r14), %eax
cltd
idivl %ecx
imull %ecx, %eax
movl %eax, %r12d
testl %eax, %eax
jle .L9
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, %r15d
movl %ecx, %r13d
movq %rbx, 16(%rsp)
movq %rbp, 24(%rsp)
movl %esi, %ebp
jmp .L7
.L6:
cmpl %r15d, %ebp
je .L12
subl %r13d, %r12d
testl %r12d, %r12d
jle .L16
.L7:
cmpl %r12d, %r14d
movl %r12d, %ebx
cmovle %r14d, %ebx
leaq 60(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L3
movl 60(%rsp), %eax
movl %ebx, %edx
imull %eax, %edx
cmpl %r15d, %edx
jle .L6
movl %edx, %r15d
movl %eax, 8(%rsp)
movl %ebx, 12(%rsp)
jmp .L6
.L16:
movq 16(%rsp), %rbx
movq 24(%rsp), %rbp
jmp .L5
.L9:
movl $0, 8(%rsp)
movl $0, 12(%rsp)
jmp .L5
.L12:
movq 16(%rsp), %rbx
movq 24(%rsp), %rbp
.L5:
movl 8(%rsp), %eax
imull 56(%rsp), %eax
movl %eax, (%rbx)
movl 12(%rsp), %eax
movl %eax, 0(%rbp)
jmp .L3
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27get_block_and_grid_multiplyPiS_, .-_Z27get_block_and_grid_multiplyPiS_
.globl _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
.type _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i, @function
_Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i:
.LFB2076:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i, .-_Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
.globl _Z19multiply_kernel_cccP6float2S0_S0_i
.type _Z19multiply_kernel_cccP6float2S0_S0_i, @function
_Z19multiply_kernel_cccP6float2S0_S0_i:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _Z19multiply_kernel_cccP6float2S0_S0_i, .-_Z19multiply_kernel_cccP6float2S0_S0_i
.globl _Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st
.type _Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st, @function
_Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st:
.LFB2050:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movl %r9d, 20(%rsp)
movl $1, 24(%rsp)
movl %r8d, 8(%rsp)
movl $1, 12(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z19multiply_kernel_cccP6float2S0_S0_iP6float2S0_S0_i
jmp .L25
.cfi_endproc
.LFE2050:
.size _Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st, .-_Z24exec_multiply_kernel_cccP6float2S0_S0_iiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19multiply_kernel_cccP6float2S0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19multiply_kernel_cccP6float2S0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiply.hip"
.globl _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i # -- Begin function _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.p2align 4, 0x90
.type _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i,@function
_Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i: # @_Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, .Lfunc_end0-_Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.cfi_endproc
# -- End function
.globl _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t # -- Begin function _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t
.p2align 4, 0x90
.type _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t,@function
_Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t: # @_Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq 160(%rsp), %rax
movl %r8d, %edi
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rdi
movl %r9d, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq %rax, %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t, .Lfunc_end1-_Z24exec_multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_iiiP12ihipStream_t
.cfi_endproc
# -- End function
.globl _Z27get_block_and_grid_multiplyPiS_ # -- Begin function _Z27get_block_and_grid_multiplyPiS_
.p2align 4, 0x90
.type _Z27get_block_and_grid_multiplyPiS_,@function
_Z27get_block_and_grid_multiplyPiS_: # @_Z27get_block_and_grid_multiplyPiS_
.cfi_startproc
# %bb.0:
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
jmp hipOccupancyMaxPotentialBlockSize # TAILCALL
.Lfunc_end2:
.size _Z27get_block_and_grid_multiplyPiS_, .Lfunc_end2-_Z27get_block_and_grid_multiplyPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i,@object # @_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.section .rodata,"a",@progbits
.globl _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.p2align 3, 0x0
_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i:
.quad _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.size _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19multiply_kernel_cccP15HIP_vector_typeIfLj2EES1_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ExactResampleKernel_Nto1(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
int xRatio = inputWidth / outputWidth;
int yRatio = inputHeight / outputHeight;
float sum = 0;
for (int sx = 0; sx < xRatio; sx++) {
for (int sy = 0; sy < yRatio; sy++) {
//corresponding coordinates in the original image
int x = px * xRatio + sx;
int y = py * yRatio + sy;
sum += input[y * inputWidth + x];
}
}
output[py * outputWidth + px] = sum / (float)(xRatio * yRatio);
}
} | .file "tmpxft_000bf600_00000000-6_ExactResampleKernel_Nto1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii
.type _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii, @function
_Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24ExactResampleKernel_Nto1PfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii, .-_Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii
.globl _Z24ExactResampleKernel_Nto1PfS_iiii
.type _Z24ExactResampleKernel_Nto1PfS_iiii, @function
_Z24ExactResampleKernel_Nto1PfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24ExactResampleKernel_Nto1PfS_iiii, .-_Z24ExactResampleKernel_Nto1PfS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24ExactResampleKernel_Nto1PfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24ExactResampleKernel_Nto1PfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ExactResampleKernel_Nto1(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
int xRatio = inputWidth / outputWidth;
int yRatio = inputHeight / outputHeight;
float sum = 0;
for (int sx = 0; sx < xRatio; sx++) {
for (int sy = 0; sy < yRatio; sy++) {
//corresponding coordinates in the original image
int x = px * xRatio + sx;
int y = py * yRatio + sy;
sum += input[y * inputWidth + x];
}
}
output[py * outputWidth + px] = sum / (float)(xRatio * yRatio);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExactResampleKernel_Nto1(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
int xRatio = inputWidth / outputWidth;
int yRatio = inputHeight / outputHeight;
float sum = 0;
for (int sx = 0; sx < xRatio; sx++) {
for (int sy = 0; sy < yRatio; sy++) {
//corresponding coordinates in the original image
int x = px * xRatio + sx;
int y = py * yRatio + sy;
sum += input[y * inputWidth + x];
}
}
output[py * outputWidth + px] = sum / (float)(xRatio * yRatio);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExactResampleKernel_Nto1(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
int xRatio = inputWidth / outputWidth;
int yRatio = inputHeight / outputHeight;
float sum = 0;
for (int sx = 0; sx < xRatio; sx++) {
for (int sy = 0; sy < yRatio; sy++) {
//corresponding coordinates in the original image
int x = px * xRatio + sx;
int y = py * yRatio + sy;
sum += input[y * inputWidth + x];
}
}
output[py * outputWidth + px] = sum / (float)(xRatio * yRatio);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24ExactResampleKernel_Nto1PfS_iiii
.globl _Z24ExactResampleKernel_Nto1PfS_iiii
.p2align 8
.type _Z24ExactResampleKernel_Nto1PfS_iiii,@function
_Z24ExactResampleKernel_Nto1PfS_iiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_ashr_i32 s6, s2, 31
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s4, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_xor_b32 s7, s4, s6
s_load_b64 s[4:5], s[0:1], 0x10
v_cvt_f32_u32_e32 v0, s7
s_sub_i32 s9, 0, s7
v_add_nc_u32_e32 v3, v1, v2
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s10, s4, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_add_i32 s11, s4, s10
v_readfirstlane_b32 s8, v0
v_xor_b32_e32 v0, v3, v2
v_xor_b32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s8
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_xor_b32 s9, s11, s10
v_mul_hi_u32 v3, v0, s8
s_mul_hi_u32 s8, s9, s8
s_xor_b32 s10, s10, s6
s_mul_i32 s11, s8, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s9, s11
s_add_i32 s11, s8, 1
s_sub_i32 s12, s9, s7
s_cmp_ge_u32 s9, s7
v_mul_lo_u32 v4, v3, s7
s_cselect_b32 s8, s11, s8
s_cselect_b32 s9, s12, s9
s_add_i32 s11, s8, 1
s_cmp_ge_u32 s9, s7
s_cselect_b32 s8, s11, s8
s_ashr_i32 s9, s3, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v0, v0, v4
s_add_i32 s3, s3, s9
s_xor_b32 s11, s3, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v4, s11
v_subrev_nc_u32_e32 v6, s7, v0
v_cmp_le_u32_e32 vcc_lo, s7, v0
v_add_nc_u32_e32 v5, 1, v3
s_sub_i32 s6, 0, s11
v_rcp_iflag_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v6 :: v_dual_cndmask_b32 v3, v3, v5
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_ashr_i32 s7, s5, 31
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v4, 0x4f7ffffe, v4 :: v_dual_add_nc_u32 v5, 1, v3
s_add_i32 s5, s5, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_xor_b32 s5, s5, s7
s_xor_b32 s7, s7, s9
v_cndmask_b32_e32 v0, v3, v5, vcc_lo
v_cvt_u32_f32_e32 v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v2
v_readfirstlane_b32 s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v0, v2
s_mul_i32 s6, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s3, s6
s_add_i32 s3, s3, s6
s_xor_b32 s6, s8, s10
s_mul_hi_u32 s8, s5, s3
s_sub_i32 s3, s6, s10
s_mul_i32 s6, s8, s11
v_mul_lo_u32 v0, v4, s2
s_sub_i32 s5, s5, s6
s_add_i32 s6, s8, 1
s_sub_i32 s9, s5, s11
s_cmp_ge_u32 s5, s11
s_cselect_b32 s6, s6, s8
s_cselect_b32 s5, s9, s5
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s5, s11
v_sub_nc_u32_e32 v0, v1, v0
s_cselect_b32 s5, s8, s6
s_mov_b32 s8, 0
s_xor_b32 s5, s5, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s5, s5, s7
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_6
s_load_b64 s[6:7], s[0:1], 0x0
v_mul_lo_u32 v3, s3, v0
s_mul_i32 s9, s4, s5
v_mov_b32_e32 v5, 0
s_cmp_gt_i32 s5, 0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s9, v4, v[3:4]
s_cselect_b32 s9, -1, 0
s_branch .LBB0_4
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v1, 1, v1
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_cbranch_scc1 .LBB0_7
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v1
s_and_not1_b32 vcc_lo, exec_lo, s9
s_mov_b32 s10, s5
s_cbranch_vccnz .LBB0_3
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s10, s10, -1
s_cmp_eq_u32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, s4, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v3
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_3
.LBB0_6:
v_mov_b32_e32 v5, 0
.LBB0_7:
s_mul_i32 s5, s5, s3
s_load_b64 s[0:1], s[0:1], 0x8
v_cvt_f32_i32_e32 v3, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v3, v3, v5
v_div_scale_f32 v8, vcc_lo, v5, v3, v5
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, v1, v7
v_mad_u64_u32 v[1:2], null, v4, s2, v[0:1]
v_mul_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_fma_f32 v10, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v7
v_fma_f32 v0, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v0, v7, v9
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_div_fixup_f32 v2, v4, v3, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24ExactResampleKernel_Nto1PfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24ExactResampleKernel_Nto1PfS_iiii, .Lfunc_end0-_Z24ExactResampleKernel_Nto1PfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24ExactResampleKernel_Nto1PfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24ExactResampleKernel_Nto1PfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExactResampleKernel_Nto1(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
int xRatio = inputWidth / outputWidth;
int yRatio = inputHeight / outputHeight;
float sum = 0;
for (int sx = 0; sx < xRatio; sx++) {
for (int sy = 0; sy < yRatio; sy++) {
//corresponding coordinates in the original image
int x = px * xRatio + sx;
int y = py * yRatio + sy;
sum += input[y * inputWidth + x];
}
}
output[py * outputWidth + px] = sum / (float)(xRatio * yRatio);
}
} | .text
.file "ExactResampleKernel_Nto1.hip"
.globl _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii # -- Begin function _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.p2align 4, 0x90
.type _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii,@function
_Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii: # @_Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24ExactResampleKernel_Nto1PfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii, .Lfunc_end0-_Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24ExactResampleKernel_Nto1PfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24ExactResampleKernel_Nto1PfS_iiii,@object # @_Z24ExactResampleKernel_Nto1PfS_iiii
.section .rodata,"a",@progbits
.globl _Z24ExactResampleKernel_Nto1PfS_iiii
.p2align 3, 0x0
_Z24ExactResampleKernel_Nto1PfS_iiii:
.quad _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.size _Z24ExactResampleKernel_Nto1PfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24ExactResampleKernel_Nto1PfS_iiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24ExactResampleKernel_Nto1PfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bf600_00000000-6_ExactResampleKernel_Nto1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii
.type _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii, @function
_Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24ExactResampleKernel_Nto1PfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii, .-_Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii
.globl _Z24ExactResampleKernel_Nto1PfS_iiii
.type _Z24ExactResampleKernel_Nto1PfS_iiii, @function
_Z24ExactResampleKernel_Nto1PfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24ExactResampleKernel_Nto1PfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24ExactResampleKernel_Nto1PfS_iiii, .-_Z24ExactResampleKernel_Nto1PfS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24ExactResampleKernel_Nto1PfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24ExactResampleKernel_Nto1PfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ExactResampleKernel_Nto1.hip"
.globl _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii # -- Begin function _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.p2align 4, 0x90
.type _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii,@function
_Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii: # @_Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24ExactResampleKernel_Nto1PfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii, .Lfunc_end0-_Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24ExactResampleKernel_Nto1PfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24ExactResampleKernel_Nto1PfS_iiii,@object # @_Z24ExactResampleKernel_Nto1PfS_iiii
.section .rodata,"a",@progbits
.globl _Z24ExactResampleKernel_Nto1PfS_iiii
.p2align 3, 0x0
_Z24ExactResampleKernel_Nto1PfS_iiii:
.quad _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.size _Z24ExactResampleKernel_Nto1PfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24ExactResampleKernel_Nto1PfS_iiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__ExactResampleKernel_Nto1PfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24ExactResampleKernel_Nto1PfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
// Input Array Variables
float* h_MatA = NULL;
// Output Array
float* h_VecV = NULL;
float* h_VecW = NULL;
float* h_NormW = NULL;
// Variables to change
int GlobalSize = 5000; // this is the dimension of the matrix, GlobalSize*GlobalSize
const float EPS = 0.000005; // tolerence of the error
int max_iteration = 100; // the maximum iteration steps
// Functions
void Cleanup(void);
void InitOne(float*, int);
void UploadArray(float*, int);
float CPUReduce(float*, int);
void Arguments(int, char**);
void CPU_AvProduct()
{
int N = GlobalSize;
int matIndex =0;
for(int i=0;i<N;i++)
{
h_VecW[i] = 0;
for(int j=0;j<N;j++)
{
matIndex = i*N + j;
h_VecW[i] += h_MatA[matIndex] * h_VecV[j];
}
}
}
void CPU_NormalizeW()
{
int N = GlobalSize;
float normW=0;
for(int i=0;i<N;i++)
normW += h_VecW[i] * h_VecW[i];
normW = sqrt(normW);
for(int i=0;i<N;i++)
h_VecV[i] = h_VecW[i]/normW;
}
float CPU_ComputeLamda()
{
int N = GlobalSize;
float lamda =0;
for(int i=0;i<N;i++)
lamda += h_VecV[i] * h_VecW[i];
return lamda;
}
void RunCPUPowerMethod()
{
printf("*************************************\n");
float oldLamda =0;
float lamda=0;
//AvProduct
CPU_AvProduct();
//power loop
for (int i=0;i<max_iteration;i++)
{
CPU_NormalizeW();
CPU_AvProduct();
lamda= CPU_ComputeLamda();
printf("CPU lamda at %d: %f \n", i, lamda);
//If residual is lass than epsilon break
if(abs(oldLamda - lamda) < EPS)
break;
oldLamda = lamda;
}
printf("*************************************\n");
}
// Host code
int main(int argc, char** argv)
{
struct timespec t_start,t_end;
double runtime;
Arguments(argc, argv);
int N = GlobalSize;
printf("Matrix size %d X %d \n", N, N);
size_t vec_size = N * sizeof(float);
size_t mat_size = N * N * sizeof(float);
size_t norm_size = sizeof(float);
// Allocate normalized value in host memory
h_NormW = (float*)malloc(norm_size);
// Allocate input matrix in host memory
h_MatA = (float*)malloc(mat_size);
// Allocate initial vector V in host memory
h_VecV = (float*)malloc(vec_size);
// Allocate W vector for computations
h_VecW = (float*)malloc(vec_size);
// Initialize input matrix
UploadArray(h_MatA, N);
InitOne(h_VecV,N);
printf("Power method in CPU starts\n");
clock_gettime(CLOCK_REALTIME,&t_start);
RunCPUPowerMethod(); // the lamda is already solved here
clock_gettime(CLOCK_REALTIME,&t_end);
runtime = (t_end.tv_sec - t_start.tv_sec) + 1e-9*(t_end.tv_nsec - t_start.tv_nsec);
printf("CPU: run time = %f secs.\n",runtime);
printf("Power method in CPU is finished\n");
Cleanup();
}
void Cleanup(void)
{
// Free host memory
if (h_MatA)
free(h_MatA);
if (h_VecV)
free(h_VecV);
if (h_VecW)
free(h_VecW);
if (h_NormW)
free(h_NormW);
exit(0);
}
// Allocates an array with zero value.
void InitOne(float* data, int n)
{
for (int i = 0; i < n; i++)
data[i] = 0;
data[0]=1;
}
void UploadArray(float* data, int n)
{
int total = n*n;
int value=1;
for (int i = 0; i < total; i++)
{
data[i] = (int) (rand() % (int)(101));//1;//value;
value ++; if(value>n) value =1;
// data[i] = 1;
}
}
// Obtain program arguments
void Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
{
if (strcmp(argv[i], "--size") == 0 || strcmp(argv[i], "-size") == 0)
{
GlobalSize = atoi(argv[i+1]);
i = i + 1;
}
if (strcmp(argv[i], "--max_iteration") == 0 || strcmp(argv[i], "-max_iteration") == 0)
{
max_iteration = atoi(argv[i+1]);
i = i + 1;
}
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
// Input Array Variables
float* h_MatA = NULL;
// Output Array
float* h_VecV = NULL;
float* h_VecW = NULL;
float* h_NormW = NULL;
// Variables to change
int GlobalSize = 5000; // this is the dimension of the matrix, GlobalSize*GlobalSize
const float EPS = 0.000005; // tolerence of the error
int max_iteration = 100; // the maximum iteration steps
// Functions
void Cleanup(void);
void InitOne(float*, int);
void UploadArray(float*, int);
float CPUReduce(float*, int);
void Arguments(int, char**);
void CPU_AvProduct()
{
int N = GlobalSize;
int matIndex =0;
for(int i=0;i<N;i++)
{
h_VecW[i] = 0;
for(int j=0;j<N;j++)
{
matIndex = i*N + j;
h_VecW[i] += h_MatA[matIndex] * h_VecV[j];
}
}
}
void CPU_NormalizeW()
{
int N = GlobalSize;
float normW=0;
for(int i=0;i<N;i++)
normW += h_VecW[i] * h_VecW[i];
normW = sqrt(normW);
for(int i=0;i<N;i++)
h_VecV[i] = h_VecW[i]/normW;
}
float CPU_ComputeLamda()
{
int N = GlobalSize;
float lamda =0;
for(int i=0;i<N;i++)
lamda += h_VecV[i] * h_VecW[i];
return lamda;
}
void RunCPUPowerMethod()
{
printf("*************************************\n");
float oldLamda =0;
float lamda=0;
//AvProduct
CPU_AvProduct();
//power loop
for (int i=0;i<max_iteration;i++)
{
CPU_NormalizeW();
CPU_AvProduct();
lamda= CPU_ComputeLamda();
printf("CPU lamda at %d: %f \n", i, lamda);
//If residual is lass than epsilon break
if(abs(oldLamda - lamda) < EPS)
break;
oldLamda = lamda;
}
printf("*************************************\n");
}
// Host code
int main(int argc, char** argv)
{
struct timespec t_start,t_end;
double runtime;
Arguments(argc, argv);
int N = GlobalSize;
printf("Matrix size %d X %d \n", N, N);
size_t vec_size = N * sizeof(float);
size_t mat_size = N * N * sizeof(float);
size_t norm_size = sizeof(float);
// Allocate normalized value in host memory
h_NormW = (float*)malloc(norm_size);
// Allocate input matrix in host memory
h_MatA = (float*)malloc(mat_size);
// Allocate initial vector V in host memory
h_VecV = (float*)malloc(vec_size);
// Allocate W vector for computations
h_VecW = (float*)malloc(vec_size);
// Initialize input matrix
UploadArray(h_MatA, N);
InitOne(h_VecV,N);
printf("Power method in CPU starts\n");
clock_gettime(CLOCK_REALTIME,&t_start);
RunCPUPowerMethod(); // the lamda is already solved here
clock_gettime(CLOCK_REALTIME,&t_end);
runtime = (t_end.tv_sec - t_start.tv_sec) + 1e-9*(t_end.tv_nsec - t_start.tv_nsec);
printf("CPU: run time = %f secs.\n",runtime);
printf("Power method in CPU is finished\n");
Cleanup();
}
void Cleanup(void)
{
// Free host memory
if (h_MatA)
free(h_MatA);
if (h_VecV)
free(h_VecV);
if (h_VecW)
free(h_VecW);
if (h_NormW)
free(h_NormW);
exit(0);
}
// Allocates an array with zero value.
void InitOne(float* data, int n)
{
for (int i = 0; i < n; i++)
data[i] = 0;
data[0]=1;
}
void UploadArray(float* data, int n)
{
int total = n*n;
int value=1;
for (int i = 0; i < total; i++)
{
data[i] = (int) (rand() % (int)(101));//1;//value;
value ++; if(value>n) value =1;
// data[i] = 1;
}
}
// Obtain program arguments
void Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
{
if (strcmp(argv[i], "--size") == 0 || strcmp(argv[i], "-size") == 0)
{
GlobalSize = atoi(argv[i+1]);
i = i + 1;
}
if (strcmp(argv[i], "--max_iteration") == 0 || strcmp(argv[i], "-max_iteration") == 0)
{
max_iteration = atoi(argv[i+1]);
i = i + 1;
}
}
} | .file "tmpxft_00135126_00000000-6_power_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13CPU_AvProductv
.type _Z13CPU_AvProductv, @function
_Z13CPU_AvProductv:
.LFB2057:
.cfi_startproc
endbr64
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .L3
cltq
leaq 0(,%rax,4), %rdi
movl $0, %r8d
movl $0, %esi
.L6:
movq h_VecW(%rip), %rax
movl $0x00000000, (%rax,%rsi)
movl $0, %eax
.L5:
movq %rsi, %rdx
addq h_VecW(%rip), %rdx
movq %rax, %rcx
addq h_MatA(%rip), %rcx
movss (%rcx,%r8), %xmm0
movq h_VecV(%rip), %rcx
mulss (%rcx,%rax), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rdi, %rax
jne .L5
addq $4, %rsi
addq %rdi, %r8
cmpq %rdi, %rsi
jne .L6
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13CPU_AvProductv, .-_Z13CPU_AvProductv
.globl _Z14CPU_NormalizeWv
.type _Z14CPU_NormalizeWv, @function
_Z14CPU_NormalizeWv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl GlobalSize(%rip), %ebx
testl %ebx, %ebx
jle .L17
movq h_VecW(%rip), %rax
movslq %ebx, %rdx
leaq (%rax,%rdx,4), %rdx
pxor %xmm0, %xmm0
.L11:
movss (%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L11
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L22
.L10:
sqrtss %xmm0, %xmm0
testl %ebx, %ebx
jle .L9
.L14:
movslq %ebx, %rcx
salq $2, %rcx
movl $0, %eax
.L16:
movq h_VecW(%rip), %rdx
movss (%rdx,%rax), %xmm1
divss %xmm0, %xmm1
movq h_VecV(%rip), %rdx
movss %xmm1, (%rdx,%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L16
.L9:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pxor %xmm0, %xmm0
jmp .L10
.L22:
call sqrtf@PLT
jmp .L14
.cfi_endproc
.LFE2058:
.size _Z14CPU_NormalizeWv, .-_Z14CPU_NormalizeWv
.globl _Z16CPU_ComputeLamdav
.type _Z16CPU_ComputeLamdav, @function
_Z16CPU_ComputeLamdav:
.LFB2059:
.cfi_startproc
endbr64
movl GlobalSize(%rip), %edx
testl %edx, %edx
jle .L26
movq h_VecV(%rip), %rsi
movq h_VecW(%rip), %rcx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
.L25:
movss (%rsi,%rax), %xmm0
mulss (%rcx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rdx, %rax
jne .L25
.L23:
movaps %xmm1, %xmm0
ret
.L26:
pxor %xmm1, %xmm1
jmp .L23
.cfi_endproc
.LFE2059:
.size _Z16CPU_ComputeLamdav, .-_Z16CPU_ComputeLamdav
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "*************************************\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU lamda at %d: %f \n"
.text
.globl _Z17RunCPUPowerMethodv
.type _Z17RunCPUPowerMethodv, @function
_Z17RunCPUPowerMethodv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z13CPU_AvProductv
cmpl $0, max_iteration(%rip)
jle .L29
movl $0, %ebx
movl $0x00000000, 8(%rsp)
leaq .LC2(%rip), %rbp
.L30:
call _Z14CPU_NormalizeWv
call _Z13CPU_AvProductv
movss 8(%rsp), %xmm2
movss %xmm2, 12(%rsp)
call _Z16CPU_ComputeLamdav
movss %xmm0, 8(%rsp)
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm2
subss 8(%rsp), %xmm2
movaps %xmm2, %xmm0
andps .LC3(%rip), %xmm0
movss .LC4(%rip), %xmm3
comiss %xmm0, %xmm3
ja .L29
addl $1, %ebx
cmpl %ebx, max_iteration(%rip)
jg .L30
.L29:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z17RunCPUPowerMethodv, .-_Z17RunCPUPowerMethodv
.globl _Z7Cleanupv
.type _Z7Cleanupv, @function
_Z7Cleanupv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq h_MatA(%rip), %rdi
testq %rdi, %rdi
je .L34
call free@PLT
.L34:
movq h_VecV(%rip), %rdi
testq %rdi, %rdi
je .L35
call free@PLT
.L35:
movq h_VecW(%rip), %rdi
testq %rdi, %rdi
je .L36
call free@PLT
.L36:
movq h_NormW(%rip), %rdi
testq %rdi, %rdi
je .L37
call free@PLT
.L37:
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z7Cleanupv, .-_Z7Cleanupv
.globl _Z7InitOnePfi
.type _Z7InitOnePfi, @function
_Z7InitOnePfi:
.LFB2063:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L40
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L41:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L41
.L40:
movl $0x3f800000, (%rdi)
ret
.cfi_endproc
.LFE2063:
.size _Z7InitOnePfi, .-_Z7InitOnePfi
.globl _Z11UploadArrayPfi
.type _Z11UploadArrayPfi, @function
_Z11UploadArrayPfi:
.LFB2064:
.cfi_startproc
endbr64
movl %esi, %eax
imull %esi, %eax
testl %eax, %eax
jle .L50
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %esi, %r12d
movq %rdi, %rbp
cltq
leaq (%rdi,%rax,4), %r14
movl $1, %ebx
movl $1, %r13d
.L46:
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addl $1, %ebx
cmpl %ebx, %r12d
cmovl %r13d, %ebx
addq $4, %rbp
cmpq %r14, %rbp
jne .L46
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2064:
.size _Z11UploadArrayPfi, .-_Z11UploadArrayPfi
.section .rodata.str1.1
.LC6:
.string "--size"
.LC7:
.string "-size"
.LC8:
.string "--max_iteration"
.LC9:
.string "-max_iteration"
.text
.globl _Z9ArgumentsiPPc
.type _Z9ArgumentsiPPc, @function
_Z9ArgumentsiPPc:
.LFB2065:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L62
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r13d
movq %rsi, %rbp
movl $0, %ebx
leaq .LC6(%rip), %r14
jmp .L59
.L57:
movq 8(%rbp,%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, max_iteration(%rip)
addl $1, %ebx
.L58:
addl $1, %ebx
cmpl %ebx, %r13d
jle .L65
.L59:
movslq %ebx, %rax
leaq 0(,%rax,8), %r15
movq 0(%rbp,%rax,8), %r12
movq %r14, %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L55
leaq .LC7(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L56
.L55:
movq 8(%rbp,%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, GlobalSize(%rip)
addl $1, %ebx
.L56:
movslq %ebx, %rax
leaq 0(,%rax,8), %r15
movq 0(%rbp,%rax,8), %r12
leaq .LC8(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L57
leaq .LC9(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L58
jmp .L57
.L65:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2065:
.size _Z9ArgumentsiPPc, .-_Z9ArgumentsiPPc
.section .rodata.str1.1
.LC10:
.string "Matrix size %d X %d \n"
.LC11:
.string "Power method in CPU starts\n"
.LC13:
.string "CPU: run time = %f secs.\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Power method in CPU is finished\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Z9ArgumentsiPPc
movl GlobalSize(%rip), %ebx
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %r12
salq $2, %r12
movl $4, %edi
call malloc@PLT
movq %rax, h_NormW(%rip)
movl %ebx, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, h_MatA(%rip)
movq %r12, %rdi
call malloc@PLT
movq %rax, h_VecV(%rip)
movq %r12, %rdi
call malloc@PLT
movq %rax, h_VecW(%rip)
movl %ebx, %esi
movq %rbp, %rdi
call _Z11UploadArrayPfi
movl %ebx, %esi
movq h_VecV(%rip), %rdi
call _Z7InitOnePfi
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
call _Z17RunCPUPowerMethodv
leaq 16(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 24(%rsp), %rax
subq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC12(%rip), %xmm0
movq 16(%rsp), %rax
subq (%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7Cleanupv
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl max_iteration
.data
.align 4
.type max_iteration, @object
.size max_iteration, 4
max_iteration:
.long 100
.globl GlobalSize
.align 4
.type GlobalSize, @object
.size GlobalSize, 4
GlobalSize:
.long 5000
.globl h_NormW
.bss
.align 8
.type h_NormW, @object
.size h_NormW, 8
h_NormW:
.zero 8
.globl h_VecW
.align 8
.type h_VecW, @object
.size h_VecW, 8
h_VecW:
.zero 8
.globl h_VecV
.align 8
.type h_VecV, @object
.size h_VecV, 8
h_VecV:
.zero 8
.globl h_MatA
.align 8
.type h_MatA, @object
.size h_MatA, 8
h_MatA:
.zero 8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 916964780
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
// Input Array Variables
float* h_MatA = NULL;
// Output Array
float* h_VecV = NULL;
float* h_VecW = NULL;
float* h_NormW = NULL;
// Variables to change
int GlobalSize = 5000; // this is the dimension of the matrix, GlobalSize*GlobalSize
const float EPS = 0.000005; // tolerence of the error
int max_iteration = 100; // the maximum iteration steps
// Functions
void Cleanup(void);
void InitOne(float*, int);
void UploadArray(float*, int);
float CPUReduce(float*, int);
void Arguments(int, char**);
void CPU_AvProduct()
{
int N = GlobalSize;
int matIndex =0;
for(int i=0;i<N;i++)
{
h_VecW[i] = 0;
for(int j=0;j<N;j++)
{
matIndex = i*N + j;
h_VecW[i] += h_MatA[matIndex] * h_VecV[j];
}
}
}
void CPU_NormalizeW()
{
int N = GlobalSize;
float normW=0;
for(int i=0;i<N;i++)
normW += h_VecW[i] * h_VecW[i];
normW = sqrt(normW);
for(int i=0;i<N;i++)
h_VecV[i] = h_VecW[i]/normW;
}
float CPU_ComputeLamda()
{
int N = GlobalSize;
float lamda =0;
for(int i=0;i<N;i++)
lamda += h_VecV[i] * h_VecW[i];
return lamda;
}
void RunCPUPowerMethod()
{
printf("*************************************\n");
float oldLamda =0;
float lamda=0;
//AvProduct
CPU_AvProduct();
//power loop
for (int i=0;i<max_iteration;i++)
{
CPU_NormalizeW();
CPU_AvProduct();
lamda= CPU_ComputeLamda();
printf("CPU lamda at %d: %f \n", i, lamda);
//If residual is lass than epsilon break
if(abs(oldLamda - lamda) < EPS)
break;
oldLamda = lamda;
}
printf("*************************************\n");
}
// Host code
int main(int argc, char** argv)
{
struct timespec t_start,t_end;
double runtime;
Arguments(argc, argv);
int N = GlobalSize;
printf("Matrix size %d X %d \n", N, N);
size_t vec_size = N * sizeof(float);
size_t mat_size = N * N * sizeof(float);
size_t norm_size = sizeof(float);
// Allocate normalized value in host memory
h_NormW = (float*)malloc(norm_size);
// Allocate input matrix in host memory
h_MatA = (float*)malloc(mat_size);
// Allocate initial vector V in host memory
h_VecV = (float*)malloc(vec_size);
// Allocate W vector for computations
h_VecW = (float*)malloc(vec_size);
// Initialize input matrix
UploadArray(h_MatA, N);
InitOne(h_VecV,N);
printf("Power method in CPU starts\n");
clock_gettime(CLOCK_REALTIME,&t_start);
RunCPUPowerMethod(); // the lamda is already solved here
clock_gettime(CLOCK_REALTIME,&t_end);
runtime = (t_end.tv_sec - t_start.tv_sec) + 1e-9*(t_end.tv_nsec - t_start.tv_nsec);
printf("CPU: run time = %f secs.\n",runtime);
printf("Power method in CPU is finished\n");
Cleanup();
}
void Cleanup(void)
{
// Free host memory
if (h_MatA)
free(h_MatA);
if (h_VecV)
free(h_VecV);
if (h_VecW)
free(h_VecW);
if (h_NormW)
free(h_NormW);
exit(0);
}
// Allocates an array with zero value.
void InitOne(float* data, int n)
{
for (int i = 0; i < n; i++)
data[i] = 0;
data[0]=1;
}
void UploadArray(float* data, int n)
{
int total = n*n;
int value=1;
for (int i = 0; i < total; i++)
{
data[i] = (int) (rand() % (int)(101));//1;//value;
value ++; if(value>n) value =1;
// data[i] = 1;
}
}
// Obtain program arguments
void Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
{
if (strcmp(argv[i], "--size") == 0 || strcmp(argv[i], "-size") == 0)
{
GlobalSize = atoi(argv[i+1]);
i = i + 1;
}
if (strcmp(argv[i], "--max_iteration") == 0 || strcmp(argv[i], "-max_iteration") == 0)
{
max_iteration = atoi(argv[i+1]);
i = i + 1;
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
// Input Array Variables
float* h_MatA = NULL;
// Output Array
float* h_VecV = NULL;
float* h_VecW = NULL;
float* h_NormW = NULL;
// Variables to change
int GlobalSize = 5000; // this is the dimension of the matrix, GlobalSize*GlobalSize
const float EPS = 0.000005; // tolerence of the error
int max_iteration = 100; // the maximum iteration steps
// Functions
void Cleanup(void);
void InitOne(float*, int);
void UploadArray(float*, int);
float CPUReduce(float*, int);
void Arguments(int, char**);
void CPU_AvProduct()
{
int N = GlobalSize;
int matIndex =0;
for(int i=0;i<N;i++)
{
h_VecW[i] = 0;
for(int j=0;j<N;j++)
{
matIndex = i*N + j;
h_VecW[i] += h_MatA[matIndex] * h_VecV[j];
}
}
}
void CPU_NormalizeW()
{
int N = GlobalSize;
float normW=0;
for(int i=0;i<N;i++)
normW += h_VecW[i] * h_VecW[i];
normW = sqrt(normW);
for(int i=0;i<N;i++)
h_VecV[i] = h_VecW[i]/normW;
}
float CPU_ComputeLamda()
{
int N = GlobalSize;
float lamda =0;
for(int i=0;i<N;i++)
lamda += h_VecV[i] * h_VecW[i];
return lamda;
}
void RunCPUPowerMethod()
{
printf("*************************************\n");
float oldLamda =0;
float lamda=0;
//AvProduct
CPU_AvProduct();
//power loop
for (int i=0;i<max_iteration;i++)
{
CPU_NormalizeW();
CPU_AvProduct();
lamda= CPU_ComputeLamda();
printf("CPU lamda at %d: %f \n", i, lamda);
//If residual is lass than epsilon break
if(abs(oldLamda - lamda) < EPS)
break;
oldLamda = lamda;
}
printf("*************************************\n");
}
// Host code
int main(int argc, char** argv)
{
struct timespec t_start,t_end;
double runtime;
Arguments(argc, argv);
int N = GlobalSize;
printf("Matrix size %d X %d \n", N, N);
size_t vec_size = N * sizeof(float);
size_t mat_size = N * N * sizeof(float);
size_t norm_size = sizeof(float);
// Allocate normalized value in host memory
h_NormW = (float*)malloc(norm_size);
// Allocate input matrix in host memory
h_MatA = (float*)malloc(mat_size);
// Allocate initial vector V in host memory
h_VecV = (float*)malloc(vec_size);
// Allocate W vector for computations
h_VecW = (float*)malloc(vec_size);
// Initialize input matrix
UploadArray(h_MatA, N);
InitOne(h_VecV,N);
printf("Power method in CPU starts\n");
clock_gettime(CLOCK_REALTIME,&t_start);
RunCPUPowerMethod(); // the lamda is already solved here
clock_gettime(CLOCK_REALTIME,&t_end);
runtime = (t_end.tv_sec - t_start.tv_sec) + 1e-9*(t_end.tv_nsec - t_start.tv_nsec);
printf("CPU: run time = %f secs.\n",runtime);
printf("Power method in CPU is finished\n");
Cleanup();
}
void Cleanup(void)
{
// Free host memory
if (h_MatA)
free(h_MatA);
if (h_VecV)
free(h_VecV);
if (h_VecW)
free(h_VecW);
if (h_NormW)
free(h_NormW);
exit(0);
}
// Allocates an array with zero value.
void InitOne(float* data, int n)
{
for (int i = 0; i < n; i++)
data[i] = 0;
data[0]=1;
}
void UploadArray(float* data, int n)
{
int total = n*n;
int value=1;
for (int i = 0; i < total; i++)
{
data[i] = (int) (rand() % (int)(101));//1;//value;
value ++; if(value>n) value =1;
// data[i] = 1;
}
}
// Obtain program arguments
void Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
{
if (strcmp(argv[i], "--size") == 0 || strcmp(argv[i], "-size") == 0)
{
GlobalSize = atoi(argv[i+1]);
i = i + 1;
}
if (strcmp(argv[i], "--max_iteration") == 0 || strcmp(argv[i], "-max_iteration") == 0)
{
max_iteration = atoi(argv[i+1]);
i = i + 1;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
// Input Array Variables
float* h_MatA = NULL;
// Output Array
float* h_VecV = NULL;
float* h_VecW = NULL;
float* h_NormW = NULL;
// Variables to change
int GlobalSize = 5000; // this is the dimension of the matrix, GlobalSize*GlobalSize
const float EPS = 0.000005; // tolerence of the error
int max_iteration = 100; // the maximum iteration steps
// Functions
void Cleanup(void);
void InitOne(float*, int);
void UploadArray(float*, int);
float CPUReduce(float*, int);
void Arguments(int, char**);
void CPU_AvProduct()
{
int N = GlobalSize;
int matIndex =0;
for(int i=0;i<N;i++)
{
h_VecW[i] = 0;
for(int j=0;j<N;j++)
{
matIndex = i*N + j;
h_VecW[i] += h_MatA[matIndex] * h_VecV[j];
}
}
}
void CPU_NormalizeW()
{
int N = GlobalSize;
float normW=0;
for(int i=0;i<N;i++)
normW += h_VecW[i] * h_VecW[i];
normW = sqrt(normW);
for(int i=0;i<N;i++)
h_VecV[i] = h_VecW[i]/normW;
}
float CPU_ComputeLamda()
{
int N = GlobalSize;
float lamda =0;
for(int i=0;i<N;i++)
lamda += h_VecV[i] * h_VecW[i];
return lamda;
}
void RunCPUPowerMethod()
{
printf("*************************************\n");
float oldLamda =0;
float lamda=0;
//AvProduct
CPU_AvProduct();
//power loop
for (int i=0;i<max_iteration;i++)
{
CPU_NormalizeW();
CPU_AvProduct();
lamda= CPU_ComputeLamda();
printf("CPU lamda at %d: %f \n", i, lamda);
//If residual is lass than epsilon break
if(abs(oldLamda - lamda) < EPS)
break;
oldLamda = lamda;
}
printf("*************************************\n");
}
// Host code
int main(int argc, char** argv)
{
struct timespec t_start,t_end;
double runtime;
Arguments(argc, argv);
int N = GlobalSize;
printf("Matrix size %d X %d \n", N, N);
size_t vec_size = N * sizeof(float);
size_t mat_size = N * N * sizeof(float);
size_t norm_size = sizeof(float);
// Allocate normalized value in host memory
h_NormW = (float*)malloc(norm_size);
// Allocate input matrix in host memory
h_MatA = (float*)malloc(mat_size);
// Allocate initial vector V in host memory
h_VecV = (float*)malloc(vec_size);
// Allocate W vector for computations
h_VecW = (float*)malloc(vec_size);
// Initialize input matrix
UploadArray(h_MatA, N);
InitOne(h_VecV,N);
printf("Power method in CPU starts\n");
clock_gettime(CLOCK_REALTIME,&t_start);
RunCPUPowerMethod(); // the lamda is already solved here
clock_gettime(CLOCK_REALTIME,&t_end);
runtime = (t_end.tv_sec - t_start.tv_sec) + 1e-9*(t_end.tv_nsec - t_start.tv_nsec);
printf("CPU: run time = %f secs.\n",runtime);
printf("Power method in CPU is finished\n");
Cleanup();
}
void Cleanup(void)
{
// Free host memory
if (h_MatA)
free(h_MatA);
if (h_VecV)
free(h_VecV);
if (h_VecW)
free(h_VecW);
if (h_NormW)
free(h_NormW);
exit(0);
}
// Allocates an array with zero value.
void InitOne(float* data, int n)
{
for (int i = 0; i < n; i++)
data[i] = 0;
data[0]=1;
}
void UploadArray(float* data, int n)
{
int total = n*n;
int value=1;
for (int i = 0; i < total; i++)
{
data[i] = (int) (rand() % (int)(101));//1;//value;
value ++; if(value>n) value =1;
// data[i] = 1;
}
}
// Obtain program arguments
void Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
{
if (strcmp(argv[i], "--size") == 0 || strcmp(argv[i], "-size") == 0)
{
GlobalSize = atoi(argv[i+1]);
i = i + 1;
}
if (strcmp(argv[i], "--max_iteration") == 0 || strcmp(argv[i], "-max_iteration") == 0)
{
max_iteration = atoi(argv[i+1]);
i = i + 1;
}
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
// Input Array Variables
float* h_MatA = NULL;
// Output Array
float* h_VecV = NULL;
float* h_VecW = NULL;
float* h_NormW = NULL;
// Variables to change
int GlobalSize = 5000; // this is the dimension of the matrix, GlobalSize*GlobalSize
const float EPS = 0.000005; // tolerence of the error
int max_iteration = 100; // the maximum iteration steps
// Functions
void Cleanup(void);
void InitOne(float*, int);
void UploadArray(float*, int);
float CPUReduce(float*, int);
void Arguments(int, char**);
void CPU_AvProduct()
{
int N = GlobalSize;
int matIndex =0;
for(int i=0;i<N;i++)
{
h_VecW[i] = 0;
for(int j=0;j<N;j++)
{
matIndex = i*N + j;
h_VecW[i] += h_MatA[matIndex] * h_VecV[j];
}
}
}
void CPU_NormalizeW()
{
int N = GlobalSize;
float normW=0;
for(int i=0;i<N;i++)
normW += h_VecW[i] * h_VecW[i];
normW = sqrt(normW);
for(int i=0;i<N;i++)
h_VecV[i] = h_VecW[i]/normW;
}
float CPU_ComputeLamda()
{
int N = GlobalSize;
float lamda =0;
for(int i=0;i<N;i++)
lamda += h_VecV[i] * h_VecW[i];
return lamda;
}
void RunCPUPowerMethod()
{
printf("*************************************\n");
float oldLamda =0;
float lamda=0;
//AvProduct
CPU_AvProduct();
//power loop
for (int i=0;i<max_iteration;i++)
{
CPU_NormalizeW();
CPU_AvProduct();
lamda= CPU_ComputeLamda();
printf("CPU lamda at %d: %f \n", i, lamda);
//If residual is lass than epsilon break
if(abs(oldLamda - lamda) < EPS)
break;
oldLamda = lamda;
}
printf("*************************************\n");
}
// Host code
int main(int argc, char** argv)
{
struct timespec t_start,t_end;
double runtime;
Arguments(argc, argv);
int N = GlobalSize;
printf("Matrix size %d X %d \n", N, N);
size_t vec_size = N * sizeof(float);
size_t mat_size = N * N * sizeof(float);
size_t norm_size = sizeof(float);
// Allocate normalized value in host memory
h_NormW = (float*)malloc(norm_size);
// Allocate input matrix in host memory
h_MatA = (float*)malloc(mat_size);
// Allocate initial vector V in host memory
h_VecV = (float*)malloc(vec_size);
// Allocate W vector for computations
h_VecW = (float*)malloc(vec_size);
// Initialize input matrix
UploadArray(h_MatA, N);
InitOne(h_VecV,N);
printf("Power method in CPU starts\n");
clock_gettime(CLOCK_REALTIME,&t_start);
RunCPUPowerMethod(); // the lamda is already solved here
clock_gettime(CLOCK_REALTIME,&t_end);
runtime = (t_end.tv_sec - t_start.tv_sec) + 1e-9*(t_end.tv_nsec - t_start.tv_nsec);
printf("CPU: run time = %f secs.\n",runtime);
printf("Power method in CPU is finished\n");
Cleanup();
}
void Cleanup(void)
{
// Free host memory
if (h_MatA)
free(h_MatA);
if (h_VecV)
free(h_VecV);
if (h_VecW)
free(h_VecW);
if (h_NormW)
free(h_NormW);
exit(0);
}
// Allocates an array with zero value.
void InitOne(float* data, int n)
{
for (int i = 0; i < n; i++)
data[i] = 0;
data[0]=1;
}
void UploadArray(float* data, int n)
{
int total = n*n;
int value=1;
for (int i = 0; i < total; i++)
{
data[i] = (int) (rand() % (int)(101));//1;//value;
value ++; if(value>n) value =1;
// data[i] = 1;
}
}
// Obtain program arguments
void Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
{
if (strcmp(argv[i], "--size") == 0 || strcmp(argv[i], "-size") == 0)
{
GlobalSize = atoi(argv[i+1]);
i = i + 1;
}
if (strcmp(argv[i], "--max_iteration") == 0 || strcmp(argv[i], "-max_iteration") == 0)
{
max_iteration = atoi(argv[i+1]);
i = i + 1;
}
}
} | .text
.file "power_cpu.hip"
.globl _Z13CPU_AvProductv # -- Begin function _Z13CPU_AvProductv
.p2align 4, 0x90
.type _Z13CPU_AvProductv,@function
_Z13CPU_AvProductv: # @_Z13CPU_AvProductv
.cfi_startproc
# %bb.0:
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB0_5
# %bb.1: # %.lr.ph18
movq h_VecW(%rip), %rcx
movq h_MatA(%rip), %rdx
xorl %esi, %esi
movq h_VecV(%rip), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %esi, %r9d
leaq (%rdx,%r9,4), %r9
movl $0, (%rcx,%r8,4)
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rcx,%r8,4)
incq %r10
cmpq %r10, %rax
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r8
addl %eax, %esi
cmpq %rax, %r8
jne .LBB0_2
.LBB0_5: # %._crit_edge19
retq
.Lfunc_end0:
.size _Z13CPU_AvProductv, .Lfunc_end0-_Z13CPU_AvProductv
.cfi_endproc
# -- End function
.globl _Z14CPU_NormalizeWv # -- Begin function _Z14CPU_NormalizeWv
.p2align 4, 0x90
.type _Z14CPU_NormalizeWv,@function
_Z14CPU_NormalizeWv: # @_Z14CPU_NormalizeWv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl GlobalSize(%rip), %ebx
xorps %xmm1, %xmm1
xorps %xmm0, %xmm0
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph
movq h_VecW(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movss (%rax,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm2, %xmm2
addss %xmm2, %xmm0
incq %rcx
cmpq %rcx, %rbx
jne .LBB1_2
.LBB1_3: # %._crit_edge
ucomiss %xmm1, %xmm0
jb .LBB1_5
# %bb.4:
sqrtss %xmm0, %xmm0
testl %ebx, %ebx
jg .LBB1_7
jmp .LBB1_9
.LBB1_5: # %call.sqrt
callq sqrtf
testl %ebx, %ebx
jle .LBB1_9
.LBB1_7: # %.lr.ph19
movq h_VecW(%rip), %rax
movq h_VecV(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rcx,%rdx,4)
incq %rdx
cmpq %rdx, %rbx
jne .LBB1_8
.LBB1_9: # %._crit_edge20
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14CPU_NormalizeWv, .Lfunc_end1-_Z14CPU_NormalizeWv
.cfi_endproc
# -- End function
.globl _Z16CPU_ComputeLamdav # -- Begin function _Z16CPU_ComputeLamdav
.p2align 4, 0x90
.type _Z16CPU_ComputeLamdav,@function
_Z16CPU_ComputeLamdav: # @_Z16CPU_ComputeLamdav
.cfi_startproc
# %bb.0:
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB2_1
# %bb.3: # %.lr.ph
movq h_VecV(%rip), %rcx
xorps %xmm0, %xmm0
movq h_VecW(%rip), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%rsi,4), %xmm1
addss %xmm1, %xmm0
incq %rsi
cmpq %rsi, %rax
jne .LBB2_4
# %bb.2: # %._crit_edge
retq
.LBB2_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end2:
.size _Z16CPU_ComputeLamdav, .Lfunc_end2-_Z16CPU_ComputeLamdav
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z17RunCPUPowerMethodv
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x36a7c5ac # float 4.99999987E-6
.LCPI3_2:
.long 0x00000000 # float 0
.text
.globl _Z17RunCPUPowerMethodv
.p2align 4, 0x90
.type _Z17RunCPUPowerMethodv,@function
_Z17RunCPUPowerMethodv: # @_Z17RunCPUPowerMethodv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.Lstr.1, %edi
callq puts@PLT
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB3_5
# %bb.1: # %.lr.ph18.i
movq h_VecW(%rip), %rcx
movq h_MatA(%rip), %rdx
xorl %esi, %esi
movq h_VecV(%rip), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %esi, %r9d
leaq (%rdx,%r9,4), %r9
movl $0, (%rcx,%r8,4)
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rcx,%r8,4)
incq %r10
cmpq %r10, %rax
jne .LBB3_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
incq %r8
addl %eax, %esi
cmpq %rax, %r8
jne .LBB3_2
.LBB3_5: # %_Z13CPU_AvProductv.exit
cmpl $0, max_iteration(%rip)
jle .LBB3_27
# %bb.6: # %.lr.ph.preheader
xorl %ebx, %ebx
xorps %xmm2, %xmm2
.p2align 4, 0x90
.LBB3_7: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
# Child Loop BB3_14 Depth 2
# Child Loop BB3_17 Depth 2
# Child Loop BB3_18 Depth 3
# Child Loop BB3_22 Depth 2
movl GlobalSize(%rip), %r14d
xorps %xmm0, %xmm0
testl %r14d, %r14d
jle .LBB3_10
# %bb.8: # %.lr.ph.i9
# in Loop: Header=BB3_7 Depth=1
movq h_VecW(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_9: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rcx
cmpq %rcx, %r14
jne .LBB3_9
.LBB3_10: # %._crit_edge.i8
# in Loop: Header=BB3_7 Depth=1
ucomiss .LCPI3_2(%rip), %xmm0
movaps %xmm2, 16(%rsp) # 16-byte Spill
jb .LBB3_12
# %bb.11: # in Loop: Header=BB3_7 Depth=1
sqrtss %xmm0, %xmm0
testl %r14d, %r14d
jg .LBB3_13
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_12: # %call.sqrt
# in Loop: Header=BB3_7 Depth=1
callq sqrtf
testl %r14d, %r14d
jle .LBB3_15
.LBB3_13: # %.lr.ph19.i
# in Loop: Header=BB3_7 Depth=1
movq h_VecW(%rip), %rax
movq h_VecV(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_14: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rcx,%rdx,4)
incq %rdx
cmpq %rdx, %r14
jne .LBB3_14
.LBB3_15: # %_Z14CPU_NormalizeWv.exit
# in Loop: Header=BB3_7 Depth=1
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB3_24
# %bb.16: # %.lr.ph18.i14
# in Loop: Header=BB3_7 Depth=1
movq h_VecW(%rip), %rcx
movq h_MatA(%rip), %rdx
xorl %esi, %esi
movq h_VecV(%rip), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_17: # %.lr.ph.i16
# Parent Loop BB3_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_18 Depth 3
movl %esi, %r9d
leaq (%rdx,%r9,4), %r9
movl $0, (%rcx,%r8,4)
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_18: # Parent Loop BB3_7 Depth=1
# Parent Loop BB3_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rcx,%r8,4)
incq %r10
cmpq %r10, %rax
jne .LBB3_18
# %bb.19: # %._crit_edge.i22
# in Loop: Header=BB3_17 Depth=2
incq %r8
addl %eax, %esi
cmpq %rax, %r8
jne .LBB3_17
# %bb.20: # %_Z13CPU_AvProductv.exit25
# in Loop: Header=BB3_7 Depth=1
testl %eax, %eax
jle .LBB3_24
# %bb.21: # %.lr.ph.i27
# in Loop: Header=BB3_7 Depth=1
movq h_VecV(%rip), %rcx
xorps %xmm1, %xmm1
movq h_VecW(%rip), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_22: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdx,%rsi,4), %xmm0
addss %xmm0, %xmm1
incq %rsi
cmpq %rsi, %rax
jne .LBB3_22
jmp .LBB3_25
.p2align 4, 0x90
.LBB3_24: # in Loop: Header=BB3_7 Depth=1
xorps %xmm1, %xmm1
.LBB3_25: # %_Z16CPU_ComputeLamdav.exit
# in Loop: Header=BB3_7 Depth=1
movss %xmm1, 12(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movaps 16(%rsp), %xmm1 # 16-byte Reload
subss %xmm2, %xmm1
andps .LCPI3_0(%rip), %xmm1
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
ja .LBB3_27
# %bb.26: # in Loop: Header=BB3_7 Depth=1
incl %ebx
cmpl max_iteration(%rip), %ebx
jl .LBB3_7
.LBB3_27: # %_Z16CPU_ComputeLamdav.exit._crit_edge
movl $.Lstr.1, %edi
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z17RunCPUPowerMethodv, .Lfunc_end3-_Z17RunCPUPowerMethodv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z9ArgumentsiPPc
movslq GlobalSize(%rip), %r15
movl $.L.str.2, %edi
movl %r15d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
leaq (,%r15,4), %r14
movl %r15d, %r12d
imull %r12d, %r12d
leaq (,%r12,4), %rbx
movl $4, %edi
callq malloc
movq %rax, h_NormW(%rip)
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movq %rax, h_MatA(%rip)
movq %r14, %rdi
callq malloc
movq %rax, h_VecV(%rip)
movq %r14, %rdi
callq malloc
movl %r15d, %r14d
movq %rax, h_VecW(%rip)
testq %r15, %r15
je .LBB4_3
# %bb.1: # %.lr.ph.preheader.i
cmpl $1, %r12d
adcl $0, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_2
.LBB4_3: # %_Z11UploadArrayPfi.exit
movq h_VecV(%rip), %rbx
testl %r14d, %r14d
jle .LBB4_5
# %bb.4: # %.lr.ph.preheader.i14
shlq $2, %r14
movq %rbx, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
.LBB4_5: # %_Z7InitOnePfi.exit
movl $1065353216, (%rbx) # imm = 0x3F800000
movl $.Lstr.2, %edi
callq puts@PLT
leaq 24(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
callq _Z17RunCPUPowerMethodv
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq 24(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 32(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
movq h_MatA(%rip), %rdi
testq %rdi, %rdi
je .LBB4_7
# %bb.6:
callq free
.LBB4_7:
movq h_VecV(%rip), %rdi
testq %rdi, %rdi
je .LBB4_9
# %bb.8:
callq free
.LBB4_9:
movq h_VecW(%rip), %rdi
testq %rdi, %rdi
je .LBB4_11
# %bb.10:
callq free
.LBB4_11:
movq h_NormW(%rip), %rdi
testq %rdi, %rdi
je .LBB4_13
# %bb.12:
callq free
.LBB4_13:
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.globl _Z9ArgumentsiPPc # -- Begin function _Z9ArgumentsiPPc
.p2align 4, 0x90
.type _Z9ArgumentsiPPc,@function
_Z9ArgumentsiPPc: # @_Z9ArgumentsiPPc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB5_10
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
xorl %r15d, %r15d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_2 Depth=1
leal 1(%r12), %r15d
movq 8(%rbx,%r12,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, max_iteration(%rip)
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
incl %r15d
cmpl %ebp, %r15d
jge .LBB5_9
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r15d, %r12
movq (%rbx,%r12,8), %r14
movl $.L.str.6, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl $.L.str.7, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
jne .LBB5_5
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
leal 1(%r12), %r15d
movq 8(%rbx,%r12,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, GlobalSize(%rip)
.LBB5_5: # in Loop: Header=BB5_2 Depth=1
movslq %r15d, %r12
movq (%rbx,%r12,8), %r14
movl $.L.str.8, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB5_7
# %bb.6: # in Loop: Header=BB5_2 Depth=1
movl $.L.str.9, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
jne .LBB5_8
jmp .LBB5_7
.LBB5_9:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB5_10: # %._crit_edge
retq
.Lfunc_end5:
.size _Z9ArgumentsiPPc, .Lfunc_end5-_Z9ArgumentsiPPc
.cfi_endproc
# -- End function
.globl _Z11UploadArrayPfi # -- Begin function _Z11UploadArrayPfi
.p2align 4, 0x90
.type _Z11UploadArrayPfi,@function
_Z11UploadArrayPfi: # @_Z11UploadArrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB6_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
imull %ebx, %ebx
cmpl $1, %ebx
adcl $0, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB6_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB6_4: # %._crit_edge
retq
.Lfunc_end6:
.size _Z11UploadArrayPfi, .Lfunc_end6-_Z11UploadArrayPfi
.cfi_endproc
# -- End function
.globl _Z7InitOnePfi # -- Begin function _Z7InitOnePfi
.p2align 4, 0x90
.type _Z7InitOnePfi,@function
_Z7InitOnePfi: # @_Z7InitOnePfi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
testl %esi, %esi
jle .LBB7_2
# %bb.1: # %.lr.ph.preheader
movl %esi, %edx
shlq $2, %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB7_2: # %._crit_edge
movl $1065353216, (%rbx) # imm = 0x3F800000
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z7InitOnePfi, .Lfunc_end7-_Z7InitOnePfi
.cfi_endproc
# -- End function
.globl _Z7Cleanupv # -- Begin function _Z7Cleanupv
.p2align 4, 0x90
.type _Z7Cleanupv,@function
_Z7Cleanupv: # @_Z7Cleanupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq h_MatA(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
callq free
.LBB8_2:
movq h_VecV(%rip), %rdi
testq %rdi, %rdi
je .LBB8_4
# %bb.3:
callq free
.LBB8_4:
movq h_VecW(%rip), %rdi
testq %rdi, %rdi
je .LBB8_6
# %bb.5:
callq free
.LBB8_6:
movq h_NormW(%rip), %rdi
testq %rdi, %rdi
je .LBB8_8
# %bb.7:
callq free
.LBB8_8:
xorl %edi, %edi
callq exit
.Lfunc_end8:
.size _Z7Cleanupv, .Lfunc_end8-_Z7Cleanupv
.cfi_endproc
# -- End function
.type h_MatA,@object # @h_MatA
.bss
.globl h_MatA
.p2align 3, 0x0
h_MatA:
.quad 0
.size h_MatA, 8
.type h_VecV,@object # @h_VecV
.globl h_VecV
.p2align 3, 0x0
h_VecV:
.quad 0
.size h_VecV, 8
.type h_VecW,@object # @h_VecW
.globl h_VecW
.p2align 3, 0x0
h_VecW:
.quad 0
.size h_VecW, 8
.type h_NormW,@object # @h_NormW
.globl h_NormW
.p2align 3, 0x0
h_NormW:
.quad 0
.size h_NormW, 8
.type GlobalSize,@object # @GlobalSize
.data
.globl GlobalSize
.p2align 2, 0x0
GlobalSize:
.long 5000 # 0x1388
.size GlobalSize, 4
.type max_iteration,@object # @max_iteration
.globl max_iteration
.p2align 2, 0x0
max_iteration:
.long 100 # 0x64
.size max_iteration, 4
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "CPU lamda at %d: %f \n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Matrix size %d X %d \n"
.size .L.str.2, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU: run time = %f secs.\n"
.size .L.str.4, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "--size"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "-size"
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "--max_iteration"
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "-max_iteration"
.size .L.str.9, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "*************************************"
.size .Lstr.1, 38
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Power method in CPU starts"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Power method in CPU is finished"
.size .Lstr.3, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00135126_00000000-6_power_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13CPU_AvProductv
.type _Z13CPU_AvProductv, @function
_Z13CPU_AvProductv:
.LFB2057:
.cfi_startproc
endbr64
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .L3
cltq
leaq 0(,%rax,4), %rdi
movl $0, %r8d
movl $0, %esi
.L6:
movq h_VecW(%rip), %rax
movl $0x00000000, (%rax,%rsi)
movl $0, %eax
.L5:
movq %rsi, %rdx
addq h_VecW(%rip), %rdx
movq %rax, %rcx
addq h_MatA(%rip), %rcx
movss (%rcx,%r8), %xmm0
movq h_VecV(%rip), %rcx
mulss (%rcx,%rax), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rdi, %rax
jne .L5
addq $4, %rsi
addq %rdi, %r8
cmpq %rdi, %rsi
jne .L6
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13CPU_AvProductv, .-_Z13CPU_AvProductv
.globl _Z14CPU_NormalizeWv
.type _Z14CPU_NormalizeWv, @function
_Z14CPU_NormalizeWv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl GlobalSize(%rip), %ebx
testl %ebx, %ebx
jle .L17
movq h_VecW(%rip), %rax
movslq %ebx, %rdx
leaq (%rax,%rdx,4), %rdx
pxor %xmm0, %xmm0
.L11:
movss (%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L11
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L22
.L10:
sqrtss %xmm0, %xmm0
testl %ebx, %ebx
jle .L9
.L14:
movslq %ebx, %rcx
salq $2, %rcx
movl $0, %eax
.L16:
movq h_VecW(%rip), %rdx
movss (%rdx,%rax), %xmm1
divss %xmm0, %xmm1
movq h_VecV(%rip), %rdx
movss %xmm1, (%rdx,%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L16
.L9:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pxor %xmm0, %xmm0
jmp .L10
.L22:
call sqrtf@PLT
jmp .L14
.cfi_endproc
.LFE2058:
.size _Z14CPU_NormalizeWv, .-_Z14CPU_NormalizeWv
.globl _Z16CPU_ComputeLamdav
.type _Z16CPU_ComputeLamdav, @function
_Z16CPU_ComputeLamdav:
.LFB2059:
.cfi_startproc
endbr64
movl GlobalSize(%rip), %edx
testl %edx, %edx
jle .L26
movq h_VecV(%rip), %rsi
movq h_VecW(%rip), %rcx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
.L25:
movss (%rsi,%rax), %xmm0
mulss (%rcx,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rdx, %rax
jne .L25
.L23:
movaps %xmm1, %xmm0
ret
.L26:
pxor %xmm1, %xmm1
jmp .L23
.cfi_endproc
.LFE2059:
.size _Z16CPU_ComputeLamdav, .-_Z16CPU_ComputeLamdav
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "*************************************\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU lamda at %d: %f \n"
.text
.globl _Z17RunCPUPowerMethodv
.type _Z17RunCPUPowerMethodv, @function
_Z17RunCPUPowerMethodv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z13CPU_AvProductv
cmpl $0, max_iteration(%rip)
jle .L29
movl $0, %ebx
movl $0x00000000, 8(%rsp)
leaq .LC2(%rip), %rbp
.L30:
call _Z14CPU_NormalizeWv
call _Z13CPU_AvProductv
movss 8(%rsp), %xmm2
movss %xmm2, 12(%rsp)
call _Z16CPU_ComputeLamdav
movss %xmm0, 8(%rsp)
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm2
subss 8(%rsp), %xmm2
movaps %xmm2, %xmm0
andps .LC3(%rip), %xmm0
movss .LC4(%rip), %xmm3
comiss %xmm0, %xmm3
ja .L29
addl $1, %ebx
cmpl %ebx, max_iteration(%rip)
jg .L30
.L29:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z17RunCPUPowerMethodv, .-_Z17RunCPUPowerMethodv
.globl _Z7Cleanupv
.type _Z7Cleanupv, @function
_Z7Cleanupv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq h_MatA(%rip), %rdi
testq %rdi, %rdi
je .L34
call free@PLT
.L34:
movq h_VecV(%rip), %rdi
testq %rdi, %rdi
je .L35
call free@PLT
.L35:
movq h_VecW(%rip), %rdi
testq %rdi, %rdi
je .L36
call free@PLT
.L36:
movq h_NormW(%rip), %rdi
testq %rdi, %rdi
je .L37
call free@PLT
.L37:
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z7Cleanupv, .-_Z7Cleanupv
.globl _Z7InitOnePfi
.type _Z7InitOnePfi, @function
_Z7InitOnePfi:
.LFB2063:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L40
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L41:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L41
.L40:
movl $0x3f800000, (%rdi)
ret
.cfi_endproc
.LFE2063:
.size _Z7InitOnePfi, .-_Z7InitOnePfi
.globl _Z11UploadArrayPfi
.type _Z11UploadArrayPfi, @function
_Z11UploadArrayPfi:
.LFB2064:
.cfi_startproc
endbr64
movl %esi, %eax
imull %esi, %eax
testl %eax, %eax
jle .L50
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %esi, %r12d
movq %rdi, %rbp
cltq
leaq (%rdi,%rax,4), %r14
movl $1, %ebx
movl $1, %r13d
.L46:
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addl $1, %ebx
cmpl %ebx, %r12d
cmovl %r13d, %ebx
addq $4, %rbp
cmpq %r14, %rbp
jne .L46
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2064:
.size _Z11UploadArrayPfi, .-_Z11UploadArrayPfi
.section .rodata.str1.1
.LC6:
.string "--size"
.LC7:
.string "-size"
.LC8:
.string "--max_iteration"
.LC9:
.string "-max_iteration"
.text
.globl _Z9ArgumentsiPPc
.type _Z9ArgumentsiPPc, @function
_Z9ArgumentsiPPc:
.LFB2065:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L62
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r13d
movq %rsi, %rbp
movl $0, %ebx
leaq .LC6(%rip), %r14
jmp .L59
.L57:
movq 8(%rbp,%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, max_iteration(%rip)
addl $1, %ebx
.L58:
addl $1, %ebx
cmpl %ebx, %r13d
jle .L65
.L59:
movslq %ebx, %rax
leaq 0(,%rax,8), %r15
movq 0(%rbp,%rax,8), %r12
movq %r14, %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L55
leaq .LC7(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L56
.L55:
movq 8(%rbp,%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, GlobalSize(%rip)
addl $1, %ebx
.L56:
movslq %ebx, %rax
leaq 0(,%rax,8), %r15
movq 0(%rbp,%rax,8), %r12
leaq .LC8(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L57
leaq .LC9(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L58
jmp .L57
.L65:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2065:
.size _Z9ArgumentsiPPc, .-_Z9ArgumentsiPPc
.section .rodata.str1.1
.LC10:
.string "Matrix size %d X %d \n"
.LC11:
.string "Power method in CPU starts\n"
.LC13:
.string "CPU: run time = %f secs.\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Power method in CPU is finished\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Z9ArgumentsiPPc
movl GlobalSize(%rip), %ebx
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %r12
salq $2, %r12
movl $4, %edi
call malloc@PLT
movq %rax, h_NormW(%rip)
movl %ebx, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, h_MatA(%rip)
movq %r12, %rdi
call malloc@PLT
movq %rax, h_VecV(%rip)
movq %r12, %rdi
call malloc@PLT
movq %rax, h_VecW(%rip)
movl %ebx, %esi
movq %rbp, %rdi
call _Z11UploadArrayPfi
movl %ebx, %esi
movq h_VecV(%rip), %rdi
call _Z7InitOnePfi
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
call _Z17RunCPUPowerMethodv
leaq 16(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 24(%rsp), %rax
subq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC12(%rip), %xmm0
movq 16(%rsp), %rax
subq (%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7Cleanupv
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl max_iteration
.data
.align 4
.type max_iteration, @object
.size max_iteration, 4
max_iteration:
.long 100
.globl GlobalSize
.align 4
.type GlobalSize, @object
.size GlobalSize, 4
GlobalSize:
.long 5000
.globl h_NormW
.bss
.align 8
.type h_NormW, @object
.size h_NormW, 8
h_NormW:
.zero 8
.globl h_VecW
.align 8
.type h_VecW, @object
.size h_VecW, 8
h_VecW:
.zero 8
.globl h_VecV
.align 8
.type h_VecV, @object
.size h_VecV, 8
h_VecV:
.zero 8
.globl h_MatA
.align 8
.type h_MatA, @object
.size h_MatA, 8
h_MatA:
.zero 8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 916964780
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "power_cpu.hip"
.globl _Z13CPU_AvProductv # -- Begin function _Z13CPU_AvProductv
.p2align 4, 0x90
.type _Z13CPU_AvProductv,@function
_Z13CPU_AvProductv: # @_Z13CPU_AvProductv
.cfi_startproc
# %bb.0:
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB0_5
# %bb.1: # %.lr.ph18
movq h_VecW(%rip), %rcx
movq h_MatA(%rip), %rdx
xorl %esi, %esi
movq h_VecV(%rip), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %esi, %r9d
leaq (%rdx,%r9,4), %r9
movl $0, (%rcx,%r8,4)
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rcx,%r8,4)
incq %r10
cmpq %r10, %rax
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r8
addl %eax, %esi
cmpq %rax, %r8
jne .LBB0_2
.LBB0_5: # %._crit_edge19
retq
.Lfunc_end0:
.size _Z13CPU_AvProductv, .Lfunc_end0-_Z13CPU_AvProductv
.cfi_endproc
# -- End function
.globl _Z14CPU_NormalizeWv # -- Begin function _Z14CPU_NormalizeWv
.p2align 4, 0x90
.type _Z14CPU_NormalizeWv,@function
_Z14CPU_NormalizeWv: # @_Z14CPU_NormalizeWv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl GlobalSize(%rip), %ebx
xorps %xmm1, %xmm1
xorps %xmm0, %xmm0
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph
movq h_VecW(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movss (%rax,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm2, %xmm2
addss %xmm2, %xmm0
incq %rcx
cmpq %rcx, %rbx
jne .LBB1_2
.LBB1_3: # %._crit_edge
ucomiss %xmm1, %xmm0
jb .LBB1_5
# %bb.4:
sqrtss %xmm0, %xmm0
testl %ebx, %ebx
jg .LBB1_7
jmp .LBB1_9
.LBB1_5: # %call.sqrt
callq sqrtf
testl %ebx, %ebx
jle .LBB1_9
.LBB1_7: # %.lr.ph19
movq h_VecW(%rip), %rax
movq h_VecV(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rcx,%rdx,4)
incq %rdx
cmpq %rdx, %rbx
jne .LBB1_8
.LBB1_9: # %._crit_edge20
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14CPU_NormalizeWv, .Lfunc_end1-_Z14CPU_NormalizeWv
.cfi_endproc
# -- End function
.globl _Z16CPU_ComputeLamdav # -- Begin function _Z16CPU_ComputeLamdav
.p2align 4, 0x90
.type _Z16CPU_ComputeLamdav,@function
_Z16CPU_ComputeLamdav: # @_Z16CPU_ComputeLamdav
.cfi_startproc
# %bb.0:
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB2_1
# %bb.3: # %.lr.ph
movq h_VecV(%rip), %rcx
xorps %xmm0, %xmm0
movq h_VecW(%rip), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%rsi,4), %xmm1
addss %xmm1, %xmm0
incq %rsi
cmpq %rsi, %rax
jne .LBB2_4
# %bb.2: # %._crit_edge
retq
.LBB2_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end2:
.size _Z16CPU_ComputeLamdav, .Lfunc_end2-_Z16CPU_ComputeLamdav
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z17RunCPUPowerMethodv
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x36a7c5ac # float 4.99999987E-6
.LCPI3_2:
.long 0x00000000 # float 0
.text
.globl _Z17RunCPUPowerMethodv
.p2align 4, 0x90
.type _Z17RunCPUPowerMethodv,@function
_Z17RunCPUPowerMethodv: # @_Z17RunCPUPowerMethodv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.Lstr.1, %edi
callq puts@PLT
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB3_5
# %bb.1: # %.lr.ph18.i
movq h_VecW(%rip), %rcx
movq h_MatA(%rip), %rdx
xorl %esi, %esi
movq h_VecV(%rip), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %esi, %r9d
leaq (%rdx,%r9,4), %r9
movl $0, (%rcx,%r8,4)
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rcx,%r8,4)
incq %r10
cmpq %r10, %rax
jne .LBB3_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
incq %r8
addl %eax, %esi
cmpq %rax, %r8
jne .LBB3_2
.LBB3_5: # %_Z13CPU_AvProductv.exit
cmpl $0, max_iteration(%rip)
jle .LBB3_27
# %bb.6: # %.lr.ph.preheader
xorl %ebx, %ebx
xorps %xmm2, %xmm2
.p2align 4, 0x90
.LBB3_7: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
# Child Loop BB3_14 Depth 2
# Child Loop BB3_17 Depth 2
# Child Loop BB3_18 Depth 3
# Child Loop BB3_22 Depth 2
movl GlobalSize(%rip), %r14d
xorps %xmm0, %xmm0
testl %r14d, %r14d
jle .LBB3_10
# %bb.8: # %.lr.ph.i9
# in Loop: Header=BB3_7 Depth=1
movq h_VecW(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_9: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rcx
cmpq %rcx, %r14
jne .LBB3_9
.LBB3_10: # %._crit_edge.i8
# in Loop: Header=BB3_7 Depth=1
ucomiss .LCPI3_2(%rip), %xmm0
movaps %xmm2, 16(%rsp) # 16-byte Spill
jb .LBB3_12
# %bb.11: # in Loop: Header=BB3_7 Depth=1
sqrtss %xmm0, %xmm0
testl %r14d, %r14d
jg .LBB3_13
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_12: # %call.sqrt
# in Loop: Header=BB3_7 Depth=1
callq sqrtf
testl %r14d, %r14d
jle .LBB3_15
.LBB3_13: # %.lr.ph19.i
# in Loop: Header=BB3_7 Depth=1
movq h_VecW(%rip), %rax
movq h_VecV(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_14: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%rcx,%rdx,4)
incq %rdx
cmpq %rdx, %r14
jne .LBB3_14
.LBB3_15: # %_Z14CPU_NormalizeWv.exit
# in Loop: Header=BB3_7 Depth=1
movl GlobalSize(%rip), %eax
testl %eax, %eax
jle .LBB3_24
# %bb.16: # %.lr.ph18.i14
# in Loop: Header=BB3_7 Depth=1
movq h_VecW(%rip), %rcx
movq h_MatA(%rip), %rdx
xorl %esi, %esi
movq h_VecV(%rip), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_17: # %.lr.ph.i16
# Parent Loop BB3_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_18 Depth 3
movl %esi, %r9d
leaq (%rdx,%r9,4), %r9
movl $0, (%rcx,%r8,4)
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_18: # Parent Loop BB3_7 Depth=1
# Parent Loop BB3_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rcx,%r8,4)
incq %r10
cmpq %r10, %rax
jne .LBB3_18
# %bb.19: # %._crit_edge.i22
# in Loop: Header=BB3_17 Depth=2
incq %r8
addl %eax, %esi
cmpq %rax, %r8
jne .LBB3_17
# %bb.20: # %_Z13CPU_AvProductv.exit25
# in Loop: Header=BB3_7 Depth=1
testl %eax, %eax
jle .LBB3_24
# %bb.21: # %.lr.ph.i27
# in Loop: Header=BB3_7 Depth=1
movq h_VecV(%rip), %rcx
xorps %xmm1, %xmm1
movq h_VecW(%rip), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_22: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdx,%rsi,4), %xmm0
addss %xmm0, %xmm1
incq %rsi
cmpq %rsi, %rax
jne .LBB3_22
jmp .LBB3_25
.p2align 4, 0x90
.LBB3_24: # in Loop: Header=BB3_7 Depth=1
xorps %xmm1, %xmm1
.LBB3_25: # %_Z16CPU_ComputeLamdav.exit
# in Loop: Header=BB3_7 Depth=1
movss %xmm1, 12(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
movss 12(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movaps 16(%rsp), %xmm1 # 16-byte Reload
subss %xmm2, %xmm1
andps .LCPI3_0(%rip), %xmm1
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
ja .LBB3_27
# %bb.26: # in Loop: Header=BB3_7 Depth=1
incl %ebx
cmpl max_iteration(%rip), %ebx
jl .LBB3_7
.LBB3_27: # %_Z16CPU_ComputeLamdav.exit._crit_edge
movl $.Lstr.1, %edi
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z17RunCPUPowerMethodv, .Lfunc_end3-_Z17RunCPUPowerMethodv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z9ArgumentsiPPc
movslq GlobalSize(%rip), %r15
movl $.L.str.2, %edi
movl %r15d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
leaq (,%r15,4), %r14
movl %r15d, %r12d
imull %r12d, %r12d
leaq (,%r12,4), %rbx
movl $4, %edi
callq malloc
movq %rax, h_NormW(%rip)
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movq %rax, h_MatA(%rip)
movq %r14, %rdi
callq malloc
movq %rax, h_VecV(%rip)
movq %r14, %rdi
callq malloc
movl %r15d, %r14d
movq %rax, h_VecW(%rip)
testq %r15, %r15
je .LBB4_3
# %bb.1: # %.lr.ph.preheader.i
cmpl $1, %r12d
adcl $0, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_2
.LBB4_3: # %_Z11UploadArrayPfi.exit
movq h_VecV(%rip), %rbx
testl %r14d, %r14d
jle .LBB4_5
# %bb.4: # %.lr.ph.preheader.i14
shlq $2, %r14
movq %rbx, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
.LBB4_5: # %_Z7InitOnePfi.exit
movl $1065353216, (%rbx) # imm = 0x3F800000
movl $.Lstr.2, %edi
callq puts@PLT
leaq 24(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
callq _Z17RunCPUPowerMethodv
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq 24(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 32(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
movq h_MatA(%rip), %rdi
testq %rdi, %rdi
je .LBB4_7
# %bb.6:
callq free
.LBB4_7:
movq h_VecV(%rip), %rdi
testq %rdi, %rdi
je .LBB4_9
# %bb.8:
callq free
.LBB4_9:
movq h_VecW(%rip), %rdi
testq %rdi, %rdi
je .LBB4_11
# %bb.10:
callq free
.LBB4_11:
movq h_NormW(%rip), %rdi
testq %rdi, %rdi
je .LBB4_13
# %bb.12:
callq free
.LBB4_13:
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.globl _Z9ArgumentsiPPc # -- Begin function _Z9ArgumentsiPPc
.p2align 4, 0x90
.type _Z9ArgumentsiPPc,@function
_Z9ArgumentsiPPc: # @_Z9ArgumentsiPPc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB5_10
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
xorl %r15d, %r15d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_2 Depth=1
leal 1(%r12), %r15d
movq 8(%rbx,%r12,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, max_iteration(%rip)
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
incl %r15d
cmpl %ebp, %r15d
jge .LBB5_9
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r15d, %r12
movq (%rbx,%r12,8), %r14
movl $.L.str.6, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl $.L.str.7, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
jne .LBB5_5
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
leal 1(%r12), %r15d
movq 8(%rbx,%r12,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, GlobalSize(%rip)
.LBB5_5: # in Loop: Header=BB5_2 Depth=1
movslq %r15d, %r12
movq (%rbx,%r12,8), %r14
movl $.L.str.8, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB5_7
# %bb.6: # in Loop: Header=BB5_2 Depth=1
movl $.L.str.9, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
jne .LBB5_8
jmp .LBB5_7
.LBB5_9:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB5_10: # %._crit_edge
retq
.Lfunc_end5:
.size _Z9ArgumentsiPPc, .Lfunc_end5-_Z9ArgumentsiPPc
.cfi_endproc
# -- End function
.globl _Z11UploadArrayPfi # -- Begin function _Z11UploadArrayPfi
.p2align 4, 0x90
.type _Z11UploadArrayPfi,@function
_Z11UploadArrayPfi: # @_Z11UploadArrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB6_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
imull %ebx, %ebx
cmpl $1, %ebx
adcl $0, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB6_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB6_4: # %._crit_edge
retq
.Lfunc_end6:
.size _Z11UploadArrayPfi, .Lfunc_end6-_Z11UploadArrayPfi
.cfi_endproc
# -- End function
.globl _Z7InitOnePfi # -- Begin function _Z7InitOnePfi
.p2align 4, 0x90
.type _Z7InitOnePfi,@function
_Z7InitOnePfi: # @_Z7InitOnePfi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
testl %esi, %esi
jle .LBB7_2
# %bb.1: # %.lr.ph.preheader
movl %esi, %edx
shlq $2, %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB7_2: # %._crit_edge
movl $1065353216, (%rbx) # imm = 0x3F800000
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z7InitOnePfi, .Lfunc_end7-_Z7InitOnePfi
.cfi_endproc
# -- End function
.globl _Z7Cleanupv # -- Begin function _Z7Cleanupv
.p2align 4, 0x90
.type _Z7Cleanupv,@function
_Z7Cleanupv: # @_Z7Cleanupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq h_MatA(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
callq free
.LBB8_2:
movq h_VecV(%rip), %rdi
testq %rdi, %rdi
je .LBB8_4
# %bb.3:
callq free
.LBB8_4:
movq h_VecW(%rip), %rdi
testq %rdi, %rdi
je .LBB8_6
# %bb.5:
callq free
.LBB8_6:
movq h_NormW(%rip), %rdi
testq %rdi, %rdi
je .LBB8_8
# %bb.7:
callq free
.LBB8_8:
xorl %edi, %edi
callq exit
.Lfunc_end8:
.size _Z7Cleanupv, .Lfunc_end8-_Z7Cleanupv
.cfi_endproc
# -- End function
.type h_MatA,@object # @h_MatA
.bss
.globl h_MatA
.p2align 3, 0x0
h_MatA:
.quad 0
.size h_MatA, 8
.type h_VecV,@object # @h_VecV
.globl h_VecV
.p2align 3, 0x0
h_VecV:
.quad 0
.size h_VecV, 8
.type h_VecW,@object # @h_VecW
.globl h_VecW
.p2align 3, 0x0
h_VecW:
.quad 0
.size h_VecW, 8
.type h_NormW,@object # @h_NormW
.globl h_NormW
.p2align 3, 0x0
h_NormW:
.quad 0
.size h_NormW, 8
.type GlobalSize,@object # @GlobalSize
.data
.globl GlobalSize
.p2align 2, 0x0
GlobalSize:
.long 5000 # 0x1388
.size GlobalSize, 4
.type max_iteration,@object # @max_iteration
.globl max_iteration
.p2align 2, 0x0
max_iteration:
.long 100 # 0x64
.size max_iteration, 4
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "CPU lamda at %d: %f \n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Matrix size %d X %d \n"
.size .L.str.2, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU: run time = %f secs.\n"
.size .L.str.4, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "--size"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "-size"
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "--max_iteration"
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "-max_iteration"
.size .L.str.9, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "*************************************"
.size .Lstr.1, 38
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Power method in CPU starts"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Power method in CPU is finished"
.size .Lstr.3, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include <stdio.h>
int main(void) {
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
for (int i=0; i<count; i++){
cudaGetDeviceProperties(&prop, i);
printf("---General information for device %d---\n", i);
printf("Name : %s\n", prop.name);
printf("Compute Capability : %d.%d\n", prop.major, prop.minor);
printf("\n---Memory information for device %d---\n", i);
printf("Total global Mem : %lu\n", prop.totalGlobalMem);
printf("Total constant Mem : %lu\n", prop.totalConstMem);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include <stdio.h>
int main(void) {
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
for (int i=0; i<count; i++){
cudaGetDeviceProperties(&prop, i);
printf("---General information for device %d---\n", i);
printf("Name : %s\n", prop.name);
printf("Compute Capability : %d.%d\n", prop.major, prop.minor);
printf("\n---Memory information for device %d---\n", i);
printf("Total global Mem : %lu\n", prop.totalGlobalMem);
printf("Total constant Mem : %lu\n", prop.totalConstMem);
}
return 0;
} | .file "tmpxft_00118253_00000000-6_02_Device_Prop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "---General information for device %d---\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Name : %s\n"
.LC2:
.string "Compute Capability : %d.%d\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "\n---Memory information for device %d---\n"
.section .rodata.str1.1
.LC4:
.string "Total global Mem : %lu\n"
.LC5:
.string "Total constant Mem : %lu\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include <stdio.h>
int main(void) {
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
for (int i=0; i<count; i++){
cudaGetDeviceProperties(&prop, i);
printf("---General information for device %d---\n", i);
printf("Name : %s\n", prop.name);
printf("Compute Capability : %d.%d\n", prop.major, prop.minor);
printf("\n---Memory information for device %d---\n", i);
printf("Total global Mem : %lu\n", prop.totalGlobalMem);
printf("Total constant Mem : %lu\n", prop.totalConstMem);
}
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
int main(void) {
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
for (int i=0; i<count; i++){
hipGetDeviceProperties(&prop, i);
printf("---General information for device %d---\n", i);
printf("Name : %s\n", prop.name);
printf("Compute Capability : %d.%d\n", prop.major, prop.minor);
printf("\n---Memory information for device %d---\n", i);
printf("Total global Mem : %lu\n", prop.totalGlobalMem);
printf("Total constant Mem : %lu\n", prop.totalConstMem);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
int main(void) {
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
for (int i=0; i<count; i++){
hipGetDeviceProperties(&prop, i);
printf("---General information for device %d---\n", i);
printf("Name : %s\n", prop.name);
printf("Compute Capability : %d.%d\n", prop.major, prop.minor);
printf("\n---Memory information for device %d---\n", i);
printf("Total global Mem : %lu\n", prop.totalGlobalMem);
printf("Total constant Mem : %lu\n", prop.totalConstMem);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
int main(void) {
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
for (int i=0; i<count; i++){
hipGetDeviceProperties(&prop, i);
printf("---General information for device %d---\n", i);
printf("Name : %s\n", prop.name);
printf("Compute Capability : %d.%d\n", prop.major, prop.minor);
printf("\n---Memory information for device %d---\n", i);
printf("Total global Mem : %lu\n", prop.totalGlobalMem);
printf("Total constant Mem : %lu\n", prop.totalConstMem);
}
return 0;
} | .text
.file "02_Device_Prop.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "---General information for device %d---\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Name : %s\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute Capability : %d.%d\n"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n---Memory information for device %d---\n"
.size .L.str.3, 41
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total global Mem : %lu\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total constant Mem : %lu\n"
.size .L.str.5, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118253_00000000-6_02_Device_Prop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "---General information for device %d---\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Name : %s\n"
.LC2:
.string "Compute Capability : %d.%d\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "\n---Memory information for device %d---\n"
.section .rodata.str1.1
.LC4:
.string "Total global Mem : %lu\n"
.LC5:
.string "Total constant Mem : %lu\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "02_Device_Prop.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "---General information for device %d---\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Name : %s\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute Capability : %d.%d\n"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n---Memory information for device %d---\n"
.size .L.str.3, 41
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total global Mem : %lu\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total constant Mem : %lu\n"
.size .L.str.5, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // RUN: %run_test hipify "%s" "%t" --skip-excluded-preprocessor-conditional-blocks %hipify_args -D__CUDA_API_VERSION_INTERNAL %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
int main() {
printf("08. CUDA Runtime API Defines synthetic test\n");
// CHECK: int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
// CHECK-NEXT: int ArrayDefault = hipArrayDefault;
// CHECK-NEXT: int ArrayLayered = hipArrayLayered;
// CHECK-NEXT: int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
// CHECK-NEXT: int ArrayCubemap = hipArrayCubemap;
// CHECK-NEXT: int ArrayTextureGather = hipArrayTextureGather;
// CHECK-NEXT: int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
// CHECK-NEXT: int DeviceMapHost = hipDeviceMapHost;
// CHECK-NEXT: int DeviceScheduleAuto = hipDeviceScheduleAuto;
// CHECK-NEXT: int DeviceScheduleSpin = hipDeviceScheduleSpin;
// CHECK-NEXT: int DeviceScheduleYield = hipDeviceScheduleYield;
// CHECK-NEXT: int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceScheduleMask = hipDeviceScheduleMask;
// CHECK-NEXT: int EventDefault = hipEventDefault;
// CHECK-NEXT: int EventBlockingSync = hipEventBlockingSync;
// CHECK-NEXT: int EventDisableTiming = hipEventDisableTiming;
// CHECK-NEXT: int EventInterprocess = hipEventInterprocess;
// CHECK-NEXT: int HostAllocDefault = hipHostMallocDefault;
// CHECK-NEXT: int HostAllocPortable = hipHostMallocPortable;
// CHECK-NEXT: int HostAllocMapped = hipHostMallocMapped;
// CHECK-NEXT: int HostAllocWriteCombined = hipHostMallocWriteCombined;
// CHECK-NEXT: int HostRegisterDefault = hipHostRegisterDefault;
// CHECK-NEXT: int HostRegisterPortable = hipHostRegisterPortable;
// CHECK-NEXT: int HostRegisterMapped = hipHostRegisterMapped;
// CHECK-NEXT: int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
// CHECK-NEXT: int MemAttachGlobal = hipMemAttachGlobal;
// CHECK-NEXT: int MemAttachHost = hipMemAttachHost;
// CHECK-NEXT: int MemAttachSingle = hipMemAttachSingle;
// CHECK-NEXT: int TextureType1D = hipTextureType1D;
// CHECK-NEXT: int TextureType2D = hipTextureType2D;
// CHECK-NEXT: int TextureType3D = hipTextureType3D;
// CHECK-NEXT: int TextureTypeCubemap = hipTextureTypeCubemap;
// CHECK-NEXT: int TextureType1DLayered = hipTextureType1DLayered;
// CHECK-NEXT: int TextureType2DLayered = hipTextureType2DLayered;
// CHECK-NEXT: int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
// CHECK-NEXT: int OccupancyDefault = hipOccupancyDefault;
// CHECK-NEXT: int StreamDefault = hipStreamDefault;
// CHECK-NEXT: int StreamNonBlocking = hipStreamNonBlocking;
// CHECK-NEXT: hipStream_t StreamPerThread = hipStreamPerThread;
int IPC_HANDLE_SIZE = CUDA_IPC_HANDLE_SIZE;
int ArrayDefault = cudaArrayDefault;
int ArrayLayered = cudaArrayLayered;
int ArraySurfaceLoadStore = cudaArraySurfaceLoadStore;
int ArrayCubemap = cudaArrayCubemap;
int ArrayTextureGather = cudaArrayTextureGather;
int DeviceBlockingSync = cudaDeviceBlockingSync;
int DeviceLmemResizeToMax = cudaDeviceLmemResizeToMax;
int DeviceMapHost = cudaDeviceMapHost;
int DeviceScheduleAuto = cudaDeviceScheduleAuto;
int DeviceScheduleSpin = cudaDeviceScheduleSpin;
int DeviceScheduleYield = cudaDeviceScheduleYield;
int DeviceScheduleBlockingSync = cudaDeviceScheduleBlockingSync;
int DeviceScheduleMask = cudaDeviceScheduleMask;
int EventDefault = cudaEventDefault;
int EventBlockingSync = cudaEventBlockingSync;
int EventDisableTiming = cudaEventDisableTiming;
int EventInterprocess = cudaEventInterprocess;
int HostAllocDefault = cudaHostAllocDefault;
int HostAllocPortable = cudaHostAllocPortable;
int HostAllocMapped = cudaHostAllocMapped;
int HostAllocWriteCombined = cudaHostAllocWriteCombined;
int HostRegisterDefault = cudaHostRegisterDefault;
int HostRegisterPortable = cudaHostRegisterPortable;
int HostRegisterMapped = cudaHostRegisterMapped;
int IpcMemLazyEnablePeerAccess = cudaIpcMemLazyEnablePeerAccess;
int MemAttachGlobal = cudaMemAttachGlobal;
int MemAttachHost = cudaMemAttachHost;
int MemAttachSingle = cudaMemAttachSingle;
int TextureType1D = cudaTextureType1D;
int TextureType2D = cudaTextureType2D;
int TextureType3D = cudaTextureType3D;
int TextureTypeCubemap = cudaTextureTypeCubemap;
int TextureType1DLayered = cudaTextureType1DLayered;
int TextureType2DLayered = cudaTextureType2DLayered;
int TextureTypeCubemapLayered = cudaTextureTypeCubemapLayered;
int OccupancyDefault = cudaOccupancyDefault;
int StreamDefault = cudaStreamDefault;
int StreamNonBlocking = cudaStreamNonBlocking;
cudaStream_t StreamPerThread = cudaStreamPerThread;
#if CUDA_VERSION > 7000
// CHECK: int HostRegisterIoMemory = hipHostRegisterIoMemory;
int HostRegisterIoMemory = cudaHostRegisterIoMemory;
#endif
#if CUDA_VERSION > 7050
// CHECK: int CpuDeviceId = hipCpuDeviceId;
// CHECK-NEXT: int InvalidDeviceId = hipInvalidDeviceId;
int CpuDeviceId = cudaCpuDeviceId;
int InvalidDeviceId = cudaInvalidDeviceId;
#endif
#if CUDA_VERSION > 8000
// CHECK: int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
// CHECK-NEXT: int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
int CooperativeLaunchMultiDeviceNoPreSync = cudaCooperativeLaunchMultiDeviceNoPreSync;
int CooperativeLaunchMultiDeviceNoPostSync = cudaCooperativeLaunchMultiDeviceNoPostSync;
#endif
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // RUN: %run_test hipify "%s" "%t" --skip-excluded-preprocessor-conditional-blocks %hipify_args -D__CUDA_API_VERSION_INTERNAL %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
int main() {
printf("08. CUDA Runtime API Defines synthetic test\n");
// CHECK: int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
// CHECK-NEXT: int ArrayDefault = hipArrayDefault;
// CHECK-NEXT: int ArrayLayered = hipArrayLayered;
// CHECK-NEXT: int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
// CHECK-NEXT: int ArrayCubemap = hipArrayCubemap;
// CHECK-NEXT: int ArrayTextureGather = hipArrayTextureGather;
// CHECK-NEXT: int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
// CHECK-NEXT: int DeviceMapHost = hipDeviceMapHost;
// CHECK-NEXT: int DeviceScheduleAuto = hipDeviceScheduleAuto;
// CHECK-NEXT: int DeviceScheduleSpin = hipDeviceScheduleSpin;
// CHECK-NEXT: int DeviceScheduleYield = hipDeviceScheduleYield;
// CHECK-NEXT: int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceScheduleMask = hipDeviceScheduleMask;
// CHECK-NEXT: int EventDefault = hipEventDefault;
// CHECK-NEXT: int EventBlockingSync = hipEventBlockingSync;
// CHECK-NEXT: int EventDisableTiming = hipEventDisableTiming;
// CHECK-NEXT: int EventInterprocess = hipEventInterprocess;
// CHECK-NEXT: int HostAllocDefault = hipHostMallocDefault;
// CHECK-NEXT: int HostAllocPortable = hipHostMallocPortable;
// CHECK-NEXT: int HostAllocMapped = hipHostMallocMapped;
// CHECK-NEXT: int HostAllocWriteCombined = hipHostMallocWriteCombined;
// CHECK-NEXT: int HostRegisterDefault = hipHostRegisterDefault;
// CHECK-NEXT: int HostRegisterPortable = hipHostRegisterPortable;
// CHECK-NEXT: int HostRegisterMapped = hipHostRegisterMapped;
// CHECK-NEXT: int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
// CHECK-NEXT: int MemAttachGlobal = hipMemAttachGlobal;
// CHECK-NEXT: int MemAttachHost = hipMemAttachHost;
// CHECK-NEXT: int MemAttachSingle = hipMemAttachSingle;
// CHECK-NEXT: int TextureType1D = hipTextureType1D;
// CHECK-NEXT: int TextureType2D = hipTextureType2D;
// CHECK-NEXT: int TextureType3D = hipTextureType3D;
// CHECK-NEXT: int TextureTypeCubemap = hipTextureTypeCubemap;
// CHECK-NEXT: int TextureType1DLayered = hipTextureType1DLayered;
// CHECK-NEXT: int TextureType2DLayered = hipTextureType2DLayered;
// CHECK-NEXT: int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
// CHECK-NEXT: int OccupancyDefault = hipOccupancyDefault;
// CHECK-NEXT: int StreamDefault = hipStreamDefault;
// CHECK-NEXT: int StreamNonBlocking = hipStreamNonBlocking;
// CHECK-NEXT: hipStream_t StreamPerThread = hipStreamPerThread;
int IPC_HANDLE_SIZE = CUDA_IPC_HANDLE_SIZE;
int ArrayDefault = cudaArrayDefault;
int ArrayLayered = cudaArrayLayered;
int ArraySurfaceLoadStore = cudaArraySurfaceLoadStore;
int ArrayCubemap = cudaArrayCubemap;
int ArrayTextureGather = cudaArrayTextureGather;
int DeviceBlockingSync = cudaDeviceBlockingSync;
int DeviceLmemResizeToMax = cudaDeviceLmemResizeToMax;
int DeviceMapHost = cudaDeviceMapHost;
int DeviceScheduleAuto = cudaDeviceScheduleAuto;
int DeviceScheduleSpin = cudaDeviceScheduleSpin;
int DeviceScheduleYield = cudaDeviceScheduleYield;
int DeviceScheduleBlockingSync = cudaDeviceScheduleBlockingSync;
int DeviceScheduleMask = cudaDeviceScheduleMask;
int EventDefault = cudaEventDefault;
int EventBlockingSync = cudaEventBlockingSync;
int EventDisableTiming = cudaEventDisableTiming;
int EventInterprocess = cudaEventInterprocess;
int HostAllocDefault = cudaHostAllocDefault;
int HostAllocPortable = cudaHostAllocPortable;
int HostAllocMapped = cudaHostAllocMapped;
int HostAllocWriteCombined = cudaHostAllocWriteCombined;
int HostRegisterDefault = cudaHostRegisterDefault;
int HostRegisterPortable = cudaHostRegisterPortable;
int HostRegisterMapped = cudaHostRegisterMapped;
int IpcMemLazyEnablePeerAccess = cudaIpcMemLazyEnablePeerAccess;
int MemAttachGlobal = cudaMemAttachGlobal;
int MemAttachHost = cudaMemAttachHost;
int MemAttachSingle = cudaMemAttachSingle;
int TextureType1D = cudaTextureType1D;
int TextureType2D = cudaTextureType2D;
int TextureType3D = cudaTextureType3D;
int TextureTypeCubemap = cudaTextureTypeCubemap;
int TextureType1DLayered = cudaTextureType1DLayered;
int TextureType2DLayered = cudaTextureType2DLayered;
int TextureTypeCubemapLayered = cudaTextureTypeCubemapLayered;
int OccupancyDefault = cudaOccupancyDefault;
int StreamDefault = cudaStreamDefault;
int StreamNonBlocking = cudaStreamNonBlocking;
cudaStream_t StreamPerThread = cudaStreamPerThread;
#if CUDA_VERSION > 7000
// CHECK: int HostRegisterIoMemory = hipHostRegisterIoMemory;
int HostRegisterIoMemory = cudaHostRegisterIoMemory;
#endif
#if CUDA_VERSION > 7050
// CHECK: int CpuDeviceId = hipCpuDeviceId;
// CHECK-NEXT: int InvalidDeviceId = hipInvalidDeviceId;
int CpuDeviceId = cudaCpuDeviceId;
int InvalidDeviceId = cudaInvalidDeviceId;
#endif
#if CUDA_VERSION > 8000
// CHECK: int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
// CHECK-NEXT: int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
int CooperativeLaunchMultiDeviceNoPreSync = cudaCooperativeLaunchMultiDeviceNoPreSync;
int CooperativeLaunchMultiDeviceNoPostSync = cudaCooperativeLaunchMultiDeviceNoPostSync;
#endif
return 0;
} | .file "tmpxft_00021751_00000000-6_runtime_defines.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "08. CUDA Runtime API Defines synthetic test\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // RUN: %run_test hipify "%s" "%t" --skip-excluded-preprocessor-conditional-blocks %hipify_args -D__CUDA_API_VERSION_INTERNAL %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
int main() {
printf("08. CUDA Runtime API Defines synthetic test\n");
// CHECK: int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
// CHECK-NEXT: int ArrayDefault = hipArrayDefault;
// CHECK-NEXT: int ArrayLayered = hipArrayLayered;
// CHECK-NEXT: int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
// CHECK-NEXT: int ArrayCubemap = hipArrayCubemap;
// CHECK-NEXT: int ArrayTextureGather = hipArrayTextureGather;
// CHECK-NEXT: int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
// CHECK-NEXT: int DeviceMapHost = hipDeviceMapHost;
// CHECK-NEXT: int DeviceScheduleAuto = hipDeviceScheduleAuto;
// CHECK-NEXT: int DeviceScheduleSpin = hipDeviceScheduleSpin;
// CHECK-NEXT: int DeviceScheduleYield = hipDeviceScheduleYield;
// CHECK-NEXT: int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceScheduleMask = hipDeviceScheduleMask;
// CHECK-NEXT: int EventDefault = hipEventDefault;
// CHECK-NEXT: int EventBlockingSync = hipEventBlockingSync;
// CHECK-NEXT: int EventDisableTiming = hipEventDisableTiming;
// CHECK-NEXT: int EventInterprocess = hipEventInterprocess;
// CHECK-NEXT: int HostAllocDefault = hipHostMallocDefault;
// CHECK-NEXT: int HostAllocPortable = hipHostMallocPortable;
// CHECK-NEXT: int HostAllocMapped = hipHostMallocMapped;
// CHECK-NEXT: int HostAllocWriteCombined = hipHostMallocWriteCombined;
// CHECK-NEXT: int HostRegisterDefault = hipHostRegisterDefault;
// CHECK-NEXT: int HostRegisterPortable = hipHostRegisterPortable;
// CHECK-NEXT: int HostRegisterMapped = hipHostRegisterMapped;
// CHECK-NEXT: int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
// CHECK-NEXT: int MemAttachGlobal = hipMemAttachGlobal;
// CHECK-NEXT: int MemAttachHost = hipMemAttachHost;
// CHECK-NEXT: int MemAttachSingle = hipMemAttachSingle;
// CHECK-NEXT: int TextureType1D = hipTextureType1D;
// CHECK-NEXT: int TextureType2D = hipTextureType2D;
// CHECK-NEXT: int TextureType3D = hipTextureType3D;
// CHECK-NEXT: int TextureTypeCubemap = hipTextureTypeCubemap;
// CHECK-NEXT: int TextureType1DLayered = hipTextureType1DLayered;
// CHECK-NEXT: int TextureType2DLayered = hipTextureType2DLayered;
// CHECK-NEXT: int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
// CHECK-NEXT: int OccupancyDefault = hipOccupancyDefault;
// CHECK-NEXT: int StreamDefault = hipStreamDefault;
// CHECK-NEXT: int StreamNonBlocking = hipStreamNonBlocking;
// CHECK-NEXT: hipStream_t StreamPerThread = hipStreamPerThread;
int IPC_HANDLE_SIZE = CUDA_IPC_HANDLE_SIZE;
int ArrayDefault = cudaArrayDefault;
int ArrayLayered = cudaArrayLayered;
int ArraySurfaceLoadStore = cudaArraySurfaceLoadStore;
int ArrayCubemap = cudaArrayCubemap;
int ArrayTextureGather = cudaArrayTextureGather;
int DeviceBlockingSync = cudaDeviceBlockingSync;
int DeviceLmemResizeToMax = cudaDeviceLmemResizeToMax;
int DeviceMapHost = cudaDeviceMapHost;
int DeviceScheduleAuto = cudaDeviceScheduleAuto;
int DeviceScheduleSpin = cudaDeviceScheduleSpin;
int DeviceScheduleYield = cudaDeviceScheduleYield;
int DeviceScheduleBlockingSync = cudaDeviceScheduleBlockingSync;
int DeviceScheduleMask = cudaDeviceScheduleMask;
int EventDefault = cudaEventDefault;
int EventBlockingSync = cudaEventBlockingSync;
int EventDisableTiming = cudaEventDisableTiming;
int EventInterprocess = cudaEventInterprocess;
int HostAllocDefault = cudaHostAllocDefault;
int HostAllocPortable = cudaHostAllocPortable;
int HostAllocMapped = cudaHostAllocMapped;
int HostAllocWriteCombined = cudaHostAllocWriteCombined;
int HostRegisterDefault = cudaHostRegisterDefault;
int HostRegisterPortable = cudaHostRegisterPortable;
int HostRegisterMapped = cudaHostRegisterMapped;
int IpcMemLazyEnablePeerAccess = cudaIpcMemLazyEnablePeerAccess;
int MemAttachGlobal = cudaMemAttachGlobal;
int MemAttachHost = cudaMemAttachHost;
int MemAttachSingle = cudaMemAttachSingle;
int TextureType1D = cudaTextureType1D;
int TextureType2D = cudaTextureType2D;
int TextureType3D = cudaTextureType3D;
int TextureTypeCubemap = cudaTextureTypeCubemap;
int TextureType1DLayered = cudaTextureType1DLayered;
int TextureType2DLayered = cudaTextureType2DLayered;
int TextureTypeCubemapLayered = cudaTextureTypeCubemapLayered;
int OccupancyDefault = cudaOccupancyDefault;
int StreamDefault = cudaStreamDefault;
int StreamNonBlocking = cudaStreamNonBlocking;
cudaStream_t StreamPerThread = cudaStreamPerThread;
#if CUDA_VERSION > 7000
// CHECK: int HostRegisterIoMemory = hipHostRegisterIoMemory;
int HostRegisterIoMemory = cudaHostRegisterIoMemory;
#endif
#if CUDA_VERSION > 7050
// CHECK: int CpuDeviceId = hipCpuDeviceId;
// CHECK-NEXT: int InvalidDeviceId = hipInvalidDeviceId;
int CpuDeviceId = cudaCpuDeviceId;
int InvalidDeviceId = cudaInvalidDeviceId;
#endif
#if CUDA_VERSION > 8000
// CHECK: int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
// CHECK-NEXT: int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
int CooperativeLaunchMultiDeviceNoPreSync = cudaCooperativeLaunchMultiDeviceNoPreSync;
int CooperativeLaunchMultiDeviceNoPostSync = cudaCooperativeLaunchMultiDeviceNoPostSync;
#endif
return 0;
} | // RUN: %run_test hipify "%s" "%t" --skip-excluded-preprocessor-conditional-blocks %hipify_args -D__CUDA_API_VERSION_INTERNAL %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
int main() {
printf("08. CUDA Runtime API Defines synthetic test\n");
// CHECK: int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
// CHECK-NEXT: int ArrayDefault = hipArrayDefault;
// CHECK-NEXT: int ArrayLayered = hipArrayLayered;
// CHECK-NEXT: int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
// CHECK-NEXT: int ArrayCubemap = hipArrayCubemap;
// CHECK-NEXT: int ArrayTextureGather = hipArrayTextureGather;
// CHECK-NEXT: int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
// CHECK-NEXT: int DeviceMapHost = hipDeviceMapHost;
// CHECK-NEXT: int DeviceScheduleAuto = hipDeviceScheduleAuto;
// CHECK-NEXT: int DeviceScheduleSpin = hipDeviceScheduleSpin;
// CHECK-NEXT: int DeviceScheduleYield = hipDeviceScheduleYield;
// CHECK-NEXT: int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceScheduleMask = hipDeviceScheduleMask;
// CHECK-NEXT: int EventDefault = hipEventDefault;
// CHECK-NEXT: int EventBlockingSync = hipEventBlockingSync;
// CHECK-NEXT: int EventDisableTiming = hipEventDisableTiming;
// CHECK-NEXT: int EventInterprocess = hipEventInterprocess;
// CHECK-NEXT: int HostAllocDefault = hipHostMallocDefault;
// CHECK-NEXT: int HostAllocPortable = hipHostMallocPortable;
// CHECK-NEXT: int HostAllocMapped = hipHostMallocMapped;
// CHECK-NEXT: int HostAllocWriteCombined = hipHostMallocWriteCombined;
// CHECK-NEXT: int HostRegisterDefault = hipHostRegisterDefault;
// CHECK-NEXT: int HostRegisterPortable = hipHostRegisterPortable;
// CHECK-NEXT: int HostRegisterMapped = hipHostRegisterMapped;
// CHECK-NEXT: int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
// CHECK-NEXT: int MemAttachGlobal = hipMemAttachGlobal;
// CHECK-NEXT: int MemAttachHost = hipMemAttachHost;
// CHECK-NEXT: int MemAttachSingle = hipMemAttachSingle;
// CHECK-NEXT: int TextureType1D = hipTextureType1D;
// CHECK-NEXT: int TextureType2D = hipTextureType2D;
// CHECK-NEXT: int TextureType3D = hipTextureType3D;
// CHECK-NEXT: int TextureTypeCubemap = hipTextureTypeCubemap;
// CHECK-NEXT: int TextureType1DLayered = hipTextureType1DLayered;
// CHECK-NEXT: int TextureType2DLayered = hipTextureType2DLayered;
// CHECK-NEXT: int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
// CHECK-NEXT: int OccupancyDefault = hipOccupancyDefault;
// CHECK-NEXT: int StreamDefault = hipStreamDefault;
// CHECK-NEXT: int StreamNonBlocking = hipStreamNonBlocking;
// CHECK-NEXT: hipStream_t StreamPerThread = hipStreamPerThread;
int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
int ArrayDefault = hipArrayDefault;
int ArrayLayered = hipArrayLayered;
int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
int ArrayCubemap = hipArrayCubemap;
int ArrayTextureGather = hipArrayTextureGather;
int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
int DeviceMapHost = hipDeviceMapHost;
int DeviceScheduleAuto = hipDeviceScheduleAuto;
int DeviceScheduleSpin = hipDeviceScheduleSpin;
int DeviceScheduleYield = hipDeviceScheduleYield;
int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
int DeviceScheduleMask = hipDeviceScheduleMask;
int EventDefault = hipEventDefault;
int EventBlockingSync = hipEventBlockingSync;
int EventDisableTiming = hipEventDisableTiming;
int EventInterprocess = hipEventInterprocess;
int HostAllocDefault = hipHostMallocDefault;
int HostAllocPortable = hipHostMallocPortable;
int HostAllocMapped = hipHostMallocMapped;
int HostAllocWriteCombined = hipHostMallocWriteCombined;
int HostRegisterDefault = hipHostRegisterDefault;
int HostRegisterPortable = hipHostRegisterPortable;
int HostRegisterMapped = hipHostRegisterMapped;
int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
int MemAttachGlobal = hipMemAttachGlobal;
int MemAttachHost = hipMemAttachHost;
int MemAttachSingle = hipMemAttachSingle;
int TextureType1D = hipTextureType1D;
int TextureType2D = hipTextureType2D;
int TextureType3D = hipTextureType3D;
int TextureTypeCubemap = hipTextureTypeCubemap;
int TextureType1DLayered = hipTextureType1DLayered;
int TextureType2DLayered = hipTextureType2DLayered;
int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
int OccupancyDefault = hipOccupancyDefault;
int StreamDefault = hipStreamDefault;
int StreamNonBlocking = hipStreamNonBlocking;
hipStream_t StreamPerThread = hipStreamPerThread;
#if CUDA_VERSION > 7000
// CHECK: int HostRegisterIoMemory = hipHostRegisterIoMemory;
int HostRegisterIoMemory = hipHostRegisterIoMemory;
#endif
#if CUDA_VERSION > 7050
// CHECK: int CpuDeviceId = hipCpuDeviceId;
// CHECK-NEXT: int InvalidDeviceId = hipInvalidDeviceId;
int CpuDeviceId = hipCpuDeviceId;
int InvalidDeviceId = hipInvalidDeviceId;
#endif
#if CUDA_VERSION > 8000
// CHECK: int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
// CHECK-NEXT: int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
#endif
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // RUN: %run_test hipify "%s" "%t" --skip-excluded-preprocessor-conditional-blocks %hipify_args -D__CUDA_API_VERSION_INTERNAL %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
int main() {
printf("08. CUDA Runtime API Defines synthetic test\n");
// CHECK: int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
// CHECK-NEXT: int ArrayDefault = hipArrayDefault;
// CHECK-NEXT: int ArrayLayered = hipArrayLayered;
// CHECK-NEXT: int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
// CHECK-NEXT: int ArrayCubemap = hipArrayCubemap;
// CHECK-NEXT: int ArrayTextureGather = hipArrayTextureGather;
// CHECK-NEXT: int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
// CHECK-NEXT: int DeviceMapHost = hipDeviceMapHost;
// CHECK-NEXT: int DeviceScheduleAuto = hipDeviceScheduleAuto;
// CHECK-NEXT: int DeviceScheduleSpin = hipDeviceScheduleSpin;
// CHECK-NEXT: int DeviceScheduleYield = hipDeviceScheduleYield;
// CHECK-NEXT: int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceScheduleMask = hipDeviceScheduleMask;
// CHECK-NEXT: int EventDefault = hipEventDefault;
// CHECK-NEXT: int EventBlockingSync = hipEventBlockingSync;
// CHECK-NEXT: int EventDisableTiming = hipEventDisableTiming;
// CHECK-NEXT: int EventInterprocess = hipEventInterprocess;
// CHECK-NEXT: int HostAllocDefault = hipHostMallocDefault;
// CHECK-NEXT: int HostAllocPortable = hipHostMallocPortable;
// CHECK-NEXT: int HostAllocMapped = hipHostMallocMapped;
// CHECK-NEXT: int HostAllocWriteCombined = hipHostMallocWriteCombined;
// CHECK-NEXT: int HostRegisterDefault = hipHostRegisterDefault;
// CHECK-NEXT: int HostRegisterPortable = hipHostRegisterPortable;
// CHECK-NEXT: int HostRegisterMapped = hipHostRegisterMapped;
// CHECK-NEXT: int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
// CHECK-NEXT: int MemAttachGlobal = hipMemAttachGlobal;
// CHECK-NEXT: int MemAttachHost = hipMemAttachHost;
// CHECK-NEXT: int MemAttachSingle = hipMemAttachSingle;
// CHECK-NEXT: int TextureType1D = hipTextureType1D;
// CHECK-NEXT: int TextureType2D = hipTextureType2D;
// CHECK-NEXT: int TextureType3D = hipTextureType3D;
// CHECK-NEXT: int TextureTypeCubemap = hipTextureTypeCubemap;
// CHECK-NEXT: int TextureType1DLayered = hipTextureType1DLayered;
// CHECK-NEXT: int TextureType2DLayered = hipTextureType2DLayered;
// CHECK-NEXT: int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
// CHECK-NEXT: int OccupancyDefault = hipOccupancyDefault;
// CHECK-NEXT: int StreamDefault = hipStreamDefault;
// CHECK-NEXT: int StreamNonBlocking = hipStreamNonBlocking;
// CHECK-NEXT: hipStream_t StreamPerThread = hipStreamPerThread;
int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
int ArrayDefault = hipArrayDefault;
int ArrayLayered = hipArrayLayered;
int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
int ArrayCubemap = hipArrayCubemap;
int ArrayTextureGather = hipArrayTextureGather;
int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
int DeviceMapHost = hipDeviceMapHost;
int DeviceScheduleAuto = hipDeviceScheduleAuto;
int DeviceScheduleSpin = hipDeviceScheduleSpin;
int DeviceScheduleYield = hipDeviceScheduleYield;
int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
int DeviceScheduleMask = hipDeviceScheduleMask;
int EventDefault = hipEventDefault;
int EventBlockingSync = hipEventBlockingSync;
int EventDisableTiming = hipEventDisableTiming;
int EventInterprocess = hipEventInterprocess;
int HostAllocDefault = hipHostMallocDefault;
int HostAllocPortable = hipHostMallocPortable;
int HostAllocMapped = hipHostMallocMapped;
int HostAllocWriteCombined = hipHostMallocWriteCombined;
int HostRegisterDefault = hipHostRegisterDefault;
int HostRegisterPortable = hipHostRegisterPortable;
int HostRegisterMapped = hipHostRegisterMapped;
int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
int MemAttachGlobal = hipMemAttachGlobal;
int MemAttachHost = hipMemAttachHost;
int MemAttachSingle = hipMemAttachSingle;
int TextureType1D = hipTextureType1D;
int TextureType2D = hipTextureType2D;
int TextureType3D = hipTextureType3D;
int TextureTypeCubemap = hipTextureTypeCubemap;
int TextureType1DLayered = hipTextureType1DLayered;
int TextureType2DLayered = hipTextureType2DLayered;
int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
int OccupancyDefault = hipOccupancyDefault;
int StreamDefault = hipStreamDefault;
int StreamNonBlocking = hipStreamNonBlocking;
hipStream_t StreamPerThread = hipStreamPerThread;
#if CUDA_VERSION > 7000
// CHECK: int HostRegisterIoMemory = hipHostRegisterIoMemory;
int HostRegisterIoMemory = hipHostRegisterIoMemory;
#endif
#if CUDA_VERSION > 7050
// CHECK: int CpuDeviceId = hipCpuDeviceId;
// CHECK-NEXT: int InvalidDeviceId = hipInvalidDeviceId;
int CpuDeviceId = hipCpuDeviceId;
int InvalidDeviceId = hipInvalidDeviceId;
#endif
#if CUDA_VERSION > 8000
// CHECK: int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
// CHECK-NEXT: int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
#endif
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // RUN: %run_test hipify "%s" "%t" --skip-excluded-preprocessor-conditional-blocks %hipify_args -D__CUDA_API_VERSION_INTERNAL %clang_args
// CHECK: #include <hip/hip_runtime.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
int main() {
printf("08. CUDA Runtime API Defines synthetic test\n");
// CHECK: int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
// CHECK-NEXT: int ArrayDefault = hipArrayDefault;
// CHECK-NEXT: int ArrayLayered = hipArrayLayered;
// CHECK-NEXT: int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
// CHECK-NEXT: int ArrayCubemap = hipArrayCubemap;
// CHECK-NEXT: int ArrayTextureGather = hipArrayTextureGather;
// CHECK-NEXT: int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
// CHECK-NEXT: int DeviceMapHost = hipDeviceMapHost;
// CHECK-NEXT: int DeviceScheduleAuto = hipDeviceScheduleAuto;
// CHECK-NEXT: int DeviceScheduleSpin = hipDeviceScheduleSpin;
// CHECK-NEXT: int DeviceScheduleYield = hipDeviceScheduleYield;
// CHECK-NEXT: int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
// CHECK-NEXT: int DeviceScheduleMask = hipDeviceScheduleMask;
// CHECK-NEXT: int EventDefault = hipEventDefault;
// CHECK-NEXT: int EventBlockingSync = hipEventBlockingSync;
// CHECK-NEXT: int EventDisableTiming = hipEventDisableTiming;
// CHECK-NEXT: int EventInterprocess = hipEventInterprocess;
// CHECK-NEXT: int HostAllocDefault = hipHostMallocDefault;
// CHECK-NEXT: int HostAllocPortable = hipHostMallocPortable;
// CHECK-NEXT: int HostAllocMapped = hipHostMallocMapped;
// CHECK-NEXT: int HostAllocWriteCombined = hipHostMallocWriteCombined;
// CHECK-NEXT: int HostRegisterDefault = hipHostRegisterDefault;
// CHECK-NEXT: int HostRegisterPortable = hipHostRegisterPortable;
// CHECK-NEXT: int HostRegisterMapped = hipHostRegisterMapped;
// CHECK-NEXT: int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
// CHECK-NEXT: int MemAttachGlobal = hipMemAttachGlobal;
// CHECK-NEXT: int MemAttachHost = hipMemAttachHost;
// CHECK-NEXT: int MemAttachSingle = hipMemAttachSingle;
// CHECK-NEXT: int TextureType1D = hipTextureType1D;
// CHECK-NEXT: int TextureType2D = hipTextureType2D;
// CHECK-NEXT: int TextureType3D = hipTextureType3D;
// CHECK-NEXT: int TextureTypeCubemap = hipTextureTypeCubemap;
// CHECK-NEXT: int TextureType1DLayered = hipTextureType1DLayered;
// CHECK-NEXT: int TextureType2DLayered = hipTextureType2DLayered;
// CHECK-NEXT: int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
// CHECK-NEXT: int OccupancyDefault = hipOccupancyDefault;
// CHECK-NEXT: int StreamDefault = hipStreamDefault;
// CHECK-NEXT: int StreamNonBlocking = hipStreamNonBlocking;
// CHECK-NEXT: hipStream_t StreamPerThread = hipStreamPerThread;
int IPC_HANDLE_SIZE = HIP_IPC_HANDLE_SIZE;
int ArrayDefault = hipArrayDefault;
int ArrayLayered = hipArrayLayered;
int ArraySurfaceLoadStore = hipArraySurfaceLoadStore;
int ArrayCubemap = hipArrayCubemap;
int ArrayTextureGather = hipArrayTextureGather;
int DeviceBlockingSync = hipDeviceScheduleBlockingSync;
int DeviceLmemResizeToMax = hipDeviceLmemResizeToMax;
int DeviceMapHost = hipDeviceMapHost;
int DeviceScheduleAuto = hipDeviceScheduleAuto;
int DeviceScheduleSpin = hipDeviceScheduleSpin;
int DeviceScheduleYield = hipDeviceScheduleYield;
int DeviceScheduleBlockingSync = hipDeviceScheduleBlockingSync;
int DeviceScheduleMask = hipDeviceScheduleMask;
int EventDefault = hipEventDefault;
int EventBlockingSync = hipEventBlockingSync;
int EventDisableTiming = hipEventDisableTiming;
int EventInterprocess = hipEventInterprocess;
int HostAllocDefault = hipHostMallocDefault;
int HostAllocPortable = hipHostMallocPortable;
int HostAllocMapped = hipHostMallocMapped;
int HostAllocWriteCombined = hipHostMallocWriteCombined;
int HostRegisterDefault = hipHostRegisterDefault;
int HostRegisterPortable = hipHostRegisterPortable;
int HostRegisterMapped = hipHostRegisterMapped;
int IpcMemLazyEnablePeerAccess = hipIpcMemLazyEnablePeerAccess;
int MemAttachGlobal = hipMemAttachGlobal;
int MemAttachHost = hipMemAttachHost;
int MemAttachSingle = hipMemAttachSingle;
int TextureType1D = hipTextureType1D;
int TextureType2D = hipTextureType2D;
int TextureType3D = hipTextureType3D;
int TextureTypeCubemap = hipTextureTypeCubemap;
int TextureType1DLayered = hipTextureType1DLayered;
int TextureType2DLayered = hipTextureType2DLayered;
int TextureTypeCubemapLayered = hipTextureTypeCubemapLayered;
int OccupancyDefault = hipOccupancyDefault;
int StreamDefault = hipStreamDefault;
int StreamNonBlocking = hipStreamNonBlocking;
hipStream_t StreamPerThread = hipStreamPerThread;
#if CUDA_VERSION > 7000
// CHECK: int HostRegisterIoMemory = hipHostRegisterIoMemory;
int HostRegisterIoMemory = hipHostRegisterIoMemory;
#endif
#if CUDA_VERSION > 7050
// CHECK: int CpuDeviceId = hipCpuDeviceId;
// CHECK-NEXT: int InvalidDeviceId = hipInvalidDeviceId;
int CpuDeviceId = hipCpuDeviceId;
int InvalidDeviceId = hipInvalidDeviceId;
#endif
#if CUDA_VERSION > 8000
// CHECK: int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
// CHECK-NEXT: int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
int CooperativeLaunchMultiDeviceNoPreSync = hipCooperativeLaunchMultiDeviceNoPreSync;
int CooperativeLaunchMultiDeviceNoPostSync = hipCooperativeLaunchMultiDeviceNoPostSync;
#endif
return 0;
} | .text
.file "runtime_defines.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "08. CUDA Runtime API Defines synthetic test"
.size .Lstr, 44
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00021751_00000000-6_runtime_defines.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "08. CUDA Runtime API Defines synthetic test\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "runtime_defines.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "08. CUDA Runtime API Defines synthetic test"
.size .Lstr, 44
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define tamBloque 64
__constant__ int mascaraX[3][3];
__constant__ int mascaraY[3][3];
// Kernel que se ejecutará en el grid de la GPU
__global__ void sobelKernel(float *entrada, float *salida, int filas, int columnas){
int sumx = 0;
int sumy = 0;
int SUM = 0;
int x, y;
int i, j, pix, piy;
int R, G, B, NC, posR, posG, posB;
float newPixel;
y= blockIdx.y;
x= blockIdx.x * blockDim.x + threadIdx.x;
if (y == 0 || y == filas-1 || x==0 || x == columnas-1){
SUM = 0;
}
else{
for(i=-1; i<=1; i++) {
for(j=-1; j<=1; j++) {
pix = j + x;
piy = i + y;
posR= piy*columnas + pix; // posición en el vector del componente R del pixel sobre el que trabajamos
R = (int)entrada[posR]; // imagen(pix,piy,0,0);
posG= filas*columnas + piy*columnas + pix; // posición en el vector del componente G del pixel sobre el que trabajamos
G = (int)entrada[posG]; // imagen(pix,piy,0,1);
posB= 2*filas*columnas + piy*columnas + pix; // posición en el vector del componente B del pixel sobre el que trabajamos
B = (int)entrada[posB]; // imagen(pix,piy,0,2);
NC = (R+G+B)/3;
sumx = sumx + (NC) * mascaraX[j+1][i+1];
sumy = sumy + (NC) * mascaraY[j+1][i+1];
}
}
SUM = abs(sumx) + abs(sumy);
}
if(SUM>255){
SUM=255;
}
newPixel = 255 - (float)(SUM);
salida[y*columnas + x] = newPixel; // componente R
salida[filas*columnas + y*columnas + x] = newPixel; // componente G
salida[2*filas*columnas + y*columnas + x] = newPixel; // componente B
}
// Función que lanza la ejecución de vectores en la GPU
void calcularSobelCuda (float *hEntrada, float *hSalida, int filas, int columnas){
float *dEntrada, *dSalida;
int tam;
dim3 DimGrid, DimBlock;
int Gx [3][3]; int Gy [3][3];
// Sobel Horizontal Mask
Gx[0][0] = 1; Gx[0][1] = 0; Gx[0][2] = -1;
Gx[1][0] = 2; Gx[1][1] = 0; Gx[1][2] = -2;
Gx[2][0] = 1; Gx[2][1] = 0; Gx[2][2] = -1;
// Sobel Vertical Mask
Gy[0][0] = 1; Gy[0][1] = 2; Gy[0][2] = 1;
Gy[1][0] = 0; Gy[1][1] = 0; Gy[1][2] = 0;
Gy[2][0] = -1; Gy[2][1] =-2; Gy[2][2] = -1;
// Transferimos las máscaras a la memoria constante de la GPU
cudaMemcpyToSymbol(mascaraX, Gx, 3*3*sizeof(int));
cudaMemcpyToSymbol(mascaraY, Gy, 3*3*sizeof(int));
// Espacio que ocupa en memoria la imagen
tam= filas * columnas * 3 * sizeof(float); // 3 colores (R, G, B)
// Reservamos espacio y copiamos en GPU la imagen de entrada
cudaMalloc((void **) &dEntrada, tam);
cudaMemcpy(dEntrada,hEntrada,tam,cudaMemcpyHostToDevice);
// Reservamos espacio en GPU para la imagen de salida
cudaMalloc((void **) &dSalida, tam);
// tamaño del grid y de los bloques de hebras
DimBlock= dim3(tamBloque, 1, 1); // bloques de tamBloque hebras
DimGrid= dim3( ((columnas-1)/tamBloque)+1, filas, 1); // grid 2D, x= bloques necesarios para cubrir 1 fila de la imagen, y= n filas imagen
// Llamada al kernel
sobelKernel<<<DimGrid,DimBlock>>>(dEntrada,dSalida,filas,columnas);
// Copia de resultados GPU -> host
cudaMemcpy(hSalida,dSalida,tam,cudaMemcpyDeviceToHost);
// Liberación de memoria en GPU
cudaFree(dEntrada);
cudaFree(dSalida);
} | code for sm_80
Function : _Z11sobelKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0030*/ BSSY B0, 0x970 ; /* 0x0000093000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002500 */
/*0060*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e660000002100 */
/*0080*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf05270 */
/*0090*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fc6000fffe13f */
/*00a0*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fe20004702670 */
/*00b0*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */
/* 0x002fca00078e0202 */
/*00c0*/ ISETP.EQ.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fc80000702670 */
/*00d0*/ ISETP.EQ.OR P0, PT, R11, UR4, P0 ; /* 0x000000040b007c0c */
/* 0x000fe20008702670 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00f0*/ @P0 BRA 0x950 ; /* 0x0000085000000947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fc600000001ff */
/*0120*/ IADD3 R4, R2.reuse, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD R23, R2, c[0x0][0x174], R11 ; /* 0x00005d0002177a24 */
/* 0x000fc600078e020b */
/*0140*/ IADD3 R6, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD R3, R4, c[0x0][0x174], R11 ; /* 0x00005d0004037a24 */
/* 0x000fe400078e020b */
/*0160*/ IMAD.WIDE R4, R23, R8, c[0x0][0x160] ; /* 0x0000580017047625 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD R13, R6, c[0x0][0x174], R11 ; /* 0x00005d00060d7a24 */
/* 0x000fe200078e020b */
/*0180*/ LDG.E R18, [R4.64+-0x4] ; /* 0xfffffc0404127981 */
/* 0x0000a2000c1e1900 */
/*0190*/ IMAD.WIDE R2, R3, R8, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0208 */
/*01a0*/ LDG.E R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x0000e2000c1e1900 */
/*01b0*/ IMAD.WIDE R12, R13, R8, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc600078e0208 */
/*01c0*/ LDG.E R25, [R2.64+-0x4] ; /* 0xfffffc0402197981 */
/* 0x000328000c1e1900 */
/*01d0*/ LDG.E R26, [R12.64+-0x4] ; /* 0xfffffc040c1a7981 */
/* 0x000ae8000c1e1900 */
/*01e0*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x0002e8000c1e1900 */
/*01f0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000ae8000c1e1900 */
/*0200*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x0000e8000c1e1900 */
/*0210*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x0002e8000c1e1900 */
/*0220*/ LDG.E R20, [R12.64+0x4] ; /* 0x000004040c147981 */
/* 0x000ae2000c1e1900 */
/*0230*/ HFMA2.MMA R29, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff1d7435 */
/* 0x000fe200000001ff */
/*0240*/ IADD3 R24, R0, 0x1, RZ ; /* 0x0000000100187810 */
/* 0x000fc40007ffe0ff */
/*0250*/ MOV R27, c[0x0][0x170] ; /* 0x00005c00001b7a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD R7, R0, c[0x0][0x174], R11.reuse ; /* 0x00005d0000077a24 */
/* 0x100fe400078e020b */
/*0270*/ IMAD R3, R24, c[0x0][0x174], R11 ; /* 0x00005d0018037a24 */
/* 0x002fe200078e020b */
/*0280*/ LEA R28, R27, R0, 0x1 ; /* 0x000000001b1c7211 */
/* 0x000fc600078e08ff */
/*0290*/ IADD3 R29, R29, c[0x0][0x170], RZ ; /* 0x00005c001d1d7a10 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0208 */
/*02b0*/ IADD3 R27, R23, -0x1, RZ ; /* 0xffffffff171b7810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ IMAD.WIDE R2, R3, R8.reuse, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x080fe200078e0208 */
/*02d0*/ LDG.E R12, [R6.64+-0x4] ; /* 0xfffffc04060c7981 */
/* 0x020366000c1e1900 */
/*02e0*/ IMAD R23, R29, c[0x0][0x174], RZ ; /* 0x00005d001d177a24 */
/* 0x000fe200078e02ff */
/*02f0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000366000c1e1900 */
/*0300*/ IMAD.WIDE R4, R23, 0x4, R4 ; /* 0x0000000417047825 */
/* 0x001fe200078e0204 */
/*0310*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000404060e7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc04020f7981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000162000c1e1900 */
/*0340*/ IMAD.WIDE R6, R27, R8, c[0x0][0x160] ; /* 0x000058001b067625 */
/* 0x002fc600078e0208 */
/*0350*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000162000c1e1900 */
/*0360*/ IADD3 R24, R24, c[0x0][0x170], RZ ; /* 0x00005c0018187a10 */
/* 0x000fe40007ffe0ff */
/*0370*/ IMAD.WIDE R6, R23, 0x4, R6 ; /* 0x0000000417067825 */
/* 0x000fcc00078e0206 */
/*0380*/ IMAD.WIDE R6, R23, 0x4, R6 ; /* 0x0000000417067825 */
/* 0x000fe200078e0206 */
/*0390*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x004ff0000020f100 */
/*03a0*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x010ff0000020f100 */
/*03b0*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x008e70000020f100 */
/*03c0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000ff0000020f100 */
/*03d0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000fe2000020f100 */
/*03e0*/ IADD3 R18, R26, R25, R18 ; /* 0x000000191a127210 */
/* 0x002fce0007ffe012 */
/*03f0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e62000020f100 */
/*0400*/ IMAD R25, R28, c[0x0][0x174], R11 ; /* 0x00005d001c197a24 */
/* 0x000fc800078e020b */
/*0410*/ IMAD.WIDE R2, R25, R8, c[0x0][0x160] ; /* 0x0000580019027625 */
/* 0x001fe400078e0208 */
/*0420*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x0000a2000c1e1900 */
/*0430*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000fe6000020f100 */
/*0440*/ LDG.E R26, [R2.64+-0x4] ; /* 0xfffffc04021a7981 */
/* 0x000ee8000c1e1900 */
/*0450*/ LDG.E R27, [R2.64] ; /* 0x00000004021b7981 */
/* 0x0008a2000c1e1900 */
/*0460*/ F2I.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000fe2000020f100 */
/*0470*/ IADD3 R21, R9, R22, R21 ; /* 0x0000001609157210 */
/* 0x002fc40007ffe015 */
/*0480*/ LDG.E R22, [R4.64+-0x4] ; /* 0xfffffc0404167981 */
/* 0x00012a000c1e1900 */
/*0490*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e62000020f100 */
/*04a0*/ IMAD R9, R24, c[0x0][0x174], R11 ; /* 0x00005d0018097a24 */
/* 0x000fe200078e020b */
/*04b0*/ LDG.E R28, [R2.64+0x4] ; /* 0x00000404021c7981 */
/* 0x0008a8000c1e1900 */
/*04c0*/ LDG.E R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x0000a2000c1e1900 */
/*04d0*/ IMAD.WIDE R8, R9, R8, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fca00078e0208 */
/*04e0*/ LDG.E R29, [R8.64+-0x4] ; /* 0xfffffc04081d7981 */
/* 0x0000a2000c1e1900 */
/*04f0*/ IADD3 R19, R20, R19, R10 ; /* 0x0000001314137210 */
/* 0x002fc60007ffe00a */
/*0500*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0002a8000c1e1900 */
/*0510*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R4, [R6.64+0x4] ; /* 0x0000040406047981 */
/* 0x001ea8000c1e1900 */
/*0530*/ LDG.E R8, [R8.64+0x4] ; /* 0x0000040408087981 */
/* 0x002ea8000c1e1900 */
/*0540*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea2000c1e1900 */
/*0550*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x020fe2000020f100 */
/*0560*/ IMAD.HI R18, R18, 0x55555556, RZ ; /* 0x5555555612127827 */
/* 0x000fce00078e02ff */
/*0570*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000fe2000020f100 */
/*0580*/ IMAD.HI R21, R21, 0x55555556, RZ ; /* 0x5555555615157827 */
/* 0x000fe200078e02ff */
/*0590*/ LEA.HI R18, R18, R18, RZ, 0x1 ; /* 0x0000001212127211 */
/* 0x000fcc00078f08ff */
/*05a0*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000fe2000020f100 */
/*05b0*/ IMAD.HI R19, R19, 0x55555556, RZ ; /* 0x5555555613137827 */
/* 0x000fe200078e02ff */
/*05c0*/ LEA.HI R21, R21, R21, RZ, 0x1 ; /* 0x0000001515157211 */
/* 0x000fcc00078f08ff */
/*05d0*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000fe2000020f100 */
/*05e0*/ LEA.HI R19, R19, R19, RZ, 0x1 ; /* 0x0000001313137211 */
/* 0x000fce00078f08ff */
/*05f0*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000ff0000020f100 */
/*0600*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000ff0000020f100 */
/*0610*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x008ff0000020f100 */
/*0620*/ F2I.TRUNC.NTZ R3, R22 ; /* 0x0000001600037305 */
/* 0x010e30000020f100 */
/*0630*/ F2I.TRUNC.NTZ R27, R27 ; /* 0x0000001b001b7305 */
/* 0x004ff0000020f100 */
/*0640*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e70000020f100 */
/*0650*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000ff0000020f100 */
/*0660*/ F2I.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000ea2000020f100 */
/*0670*/ IADD3 R12, R26, R3, R12 ; /* 0x000000031a0c7210 */
/* 0x001fe20007ffe00c */
/*0680*/ IMAD R3, R18, c[0x3][0x0], RZ ; /* 0x00c0000012037a24 */
/* 0x000fcc00078e02ff */
/*0690*/ F2I.TRUNC.NTZ R2, R29 ; /* 0x0000001d00027305 */
/* 0x000fe2000020f100 */
/*06a0*/ IMAD R18, R18, c[0x3][0x24], RZ ; /* 0x00c0090012127a24 */
/* 0x000fce00078e02ff */
/*06b0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*06c0*/ IADD3 R13, R27, R24, R13 ; /* 0x000000181b0d7210 */
/* 0x002fe20007ffe00d */
/*06d0*/ IMAD.HI R12, R12, 0x55555556, RZ ; /* 0x555555560c0c7827 */
/* 0x000fcc00078e02ff */
/*06e0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000fe2000020f100 */
/*06f0*/ IMAD R3, R21, c[0x3][0xc], R3 ; /* 0x00c0030015037a24 */
/* 0x000fce00078e0203 */
/*0700*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e62000020f100 */
/*0710*/ IMAD R18, R21, c[0x3][0x30], R18 ; /* 0x00c00c0015127a24 */
/* 0x000fe200078e0212 */
/*0720*/ IADD3 R14, R28, R25, R14 ; /* 0x000000191c0e7210 */
/* 0x004fe20007ffe00e */
/*0730*/ IMAD.HI R13, R13, 0x55555556, RZ ; /* 0x555555560d0d7827 */
/* 0x000fca00078e02ff */
/*0740*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000fe2000020f100 */
/*0750*/ LEA.HI R12, R12, R12, RZ, 0x1 ; /* 0x0000000c0c0c7211 */
/* 0x000fce00078f08ff */
/*0760*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000ea2000020f100 */
/*0770*/ IMAD R3, R19.reuse, c[0x3][0x18], R3 ; /* 0x00c0060013037a24 */
/* 0x040fe200078e0203 */
/*0780*/ IADD3 R2, R10, R2, R15 ; /* 0x000000020a027210 */
/* 0x001fe20007ffe00f */
/*0790*/ IMAD R18, R19, c[0x3][0x3c], R18 ; /* 0x00c00f0013127a24 */
/* 0x000fe200078e0212 */
/*07a0*/ LEA.HI R13, R13, R13, RZ, 0x1 ; /* 0x0000000d0d0d7211 */
/* 0x000fe200078f08ff */
/*07b0*/ IMAD.HI R14, R14, 0x55555556, RZ ; /* 0x555555560e0e7827 */
/* 0x000fe200078e02ff */
/*07c0*/ IADD3 R4, R4, R23, R16 ; /* 0x0000001704047210 */
/* 0x002fc60007ffe010 */
/*07d0*/ IMAD R3, R12.reuse, c[0x3][0x4], R3 ; /* 0x00c001000c037a24 */
/* 0x040fe400078e0203 */
/*07e0*/ IMAD R18, R12, c[0x3][0x28], R18 ; /* 0x00c00a000c127a24 */
/* 0x000fe200078e0212 */
/*07f0*/ LEA.HI R14, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0e7211 */
/* 0x000fe200078f08ff */
/*0800*/ IMAD.HI R2, R2, 0x55555556, RZ ; /* 0x5555555602027827 */
/* 0x000fe200078e02ff */
/*0810*/ IADD3 R5, R5, R8, R17 ; /* 0x0000000805057210 */
/* 0x004fc60007ffe011 */
/*0820*/ IMAD R3, R13.reuse, c[0x3][0x10], R3 ; /* 0x00c004000d037a24 */
/* 0x040fe400078e0203 */
/*0830*/ IMAD R18, R13, c[0x3][0x34], R18 ; /* 0x00c00d000d127a24 */
/* 0x000fe200078e0212 */
/*0840*/ LEA.HI R2, R2, R2, RZ, 0x1 ; /* 0x0000000202027211 */
/* 0x000fe200078f08ff */
/*0850*/ IMAD.HI R4, R4, 0x55555556, RZ ; /* 0x5555555604047827 */
/* 0x000fc800078e02ff */
/*0860*/ IMAD R18, R14.reuse, c[0x3][0x40], R18 ; /* 0x00c010000e127a24 */
/* 0x040fe400078e0212 */
/*0870*/ IMAD R3, R14, c[0x3][0x1c], R3 ; /* 0x00c007000e037a24 */
/* 0x000fe200078e0203 */
/*0880*/ LEA.HI R4, R4, R4, RZ, 0x1 ; /* 0x0000000404047211 */
/* 0x000fe200078f08ff */
/*0890*/ IMAD.HI R5, R5, 0x55555556, RZ ; /* 0x5555555605057827 */
/* 0x000fc800078e02ff */
/*08a0*/ IMAD R18, R2.reuse, c[0x3][0x2c], R18 ; /* 0x00c00b0002127a24 */
/* 0x040fe400078e0212 */
/*08b0*/ IMAD R3, R2, c[0x3][0x8], R3 ; /* 0x00c0020002037a24 */
/* 0x000fe200078e0203 */
/*08c0*/ LEA.HI R5, R5, R5, RZ, 0x1 ; /* 0x0000000505057211 */
/* 0x000fe200078f08ff */
/*08d0*/ IMAD R18, R4.reuse, c[0x3][0x38], R18 ; /* 0x00c00e0004127a24 */
/* 0x040fe400078e0212 */
/*08e0*/ IMAD R3, R4, c[0x3][0x14], R3 ; /* 0x00c0050004037a24 */
/* 0x000fe400078e0203 */
/*08f0*/ IMAD R18, R5.reuse, c[0x3][0x44], R18 ; /* 0x00c0110005127a24 */
/* 0x040fe400078e0212 */
/*0900*/ IMAD R3, R5, c[0x3][0x20], R3 ; /* 0x00c0080005037a24 */
/* 0x000fc600078e0203 */
/*0910*/ IABS R2, R18 ; /* 0x0000001200027213 */
/* 0x000fe40000000000 */
/*0920*/ IABS R3, R3 ; /* 0x0000000300037213 */
/* 0x000fc80000000000 */
/*0930*/ IADD3 R2, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x000fe20007ffe0ff */
/*0940*/ BRA 0x960 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0950*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ IMNMX R8, R2, 0xff, PT ; /* 0x000000ff02087817 */
/* 0x000fe20003800200 */
/*0980*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0990*/ IMAD R2, R0, c[0x0][0x174], R11 ; /* 0x00005d0000027a24 */
/* 0x000fe200078e020b */
/*09a0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fc60000000f00 */
/*09b0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e240000201400 */
/*09c0*/ IMAD R7, R7, c[0x0][0x170], RZ ; /* 0x00005c0007077a24 */
/* 0x000fc600078e02ff */
/*09d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*09e0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fc800078e0202 */
/*09f0*/ FADD R9, -R8, 255 ; /* 0x437f000008097421 */
/* 0x001fe40000000100 */
/*0a00*/ IMAD.WIDE R6, R7, 0x4, R4 ; /* 0x0000000407067825 */
/* 0x000fc600078e0204 */
/*0a10*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0a20*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0a30*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0a40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define tamBloque 64
__constant__ int mascaraX[3][3];
__constant__ int mascaraY[3][3];
// Kernel que se ejecutará en el grid de la GPU
__global__ void sobelKernel(float *entrada, float *salida, int filas, int columnas){
int sumx = 0;
int sumy = 0;
int SUM = 0;
int x, y;
int i, j, pix, piy;
int R, G, B, NC, posR, posG, posB;
float newPixel;
y= blockIdx.y;
x= blockIdx.x * blockDim.x + threadIdx.x;
if (y == 0 || y == filas-1 || x==0 || x == columnas-1){
SUM = 0;
}
else{
for(i=-1; i<=1; i++) {
for(j=-1; j<=1; j++) {
pix = j + x;
piy = i + y;
posR= piy*columnas + pix; // posición en el vector del componente R del pixel sobre el que trabajamos
R = (int)entrada[posR]; // imagen(pix,piy,0,0);
posG= filas*columnas + piy*columnas + pix; // posición en el vector del componente G del pixel sobre el que trabajamos
G = (int)entrada[posG]; // imagen(pix,piy,0,1);
posB= 2*filas*columnas + piy*columnas + pix; // posición en el vector del componente B del pixel sobre el que trabajamos
B = (int)entrada[posB]; // imagen(pix,piy,0,2);
NC = (R+G+B)/3;
sumx = sumx + (NC) * mascaraX[j+1][i+1];
sumy = sumy + (NC) * mascaraY[j+1][i+1];
}
}
SUM = abs(sumx) + abs(sumy);
}
if(SUM>255){
SUM=255;
}
newPixel = 255 - (float)(SUM);
salida[y*columnas + x] = newPixel; // componente R
salida[filas*columnas + y*columnas + x] = newPixel; // componente G
salida[2*filas*columnas + y*columnas + x] = newPixel; // componente B
}
// Función que lanza la ejecución de vectores en la GPU
void calcularSobelCuda (float *hEntrada, float *hSalida, int filas, int columnas){
float *dEntrada, *dSalida;
int tam;
dim3 DimGrid, DimBlock;
int Gx [3][3]; int Gy [3][3];
// Sobel Horizontal Mask
Gx[0][0] = 1; Gx[0][1] = 0; Gx[0][2] = -1;
Gx[1][0] = 2; Gx[1][1] = 0; Gx[1][2] = -2;
Gx[2][0] = 1; Gx[2][1] = 0; Gx[2][2] = -1;
// Sobel Vertical Mask
Gy[0][0] = 1; Gy[0][1] = 2; Gy[0][2] = 1;
Gy[1][0] = 0; Gy[1][1] = 0; Gy[1][2] = 0;
Gy[2][0] = -1; Gy[2][1] =-2; Gy[2][2] = -1;
// Transferimos las máscaras a la memoria constante de la GPU
cudaMemcpyToSymbol(mascaraX, Gx, 3*3*sizeof(int));
cudaMemcpyToSymbol(mascaraY, Gy, 3*3*sizeof(int));
// Espacio que ocupa en memoria la imagen
tam= filas * columnas * 3 * sizeof(float); // 3 colores (R, G, B)
// Reservamos espacio y copiamos en GPU la imagen de entrada
cudaMalloc((void **) &dEntrada, tam);
cudaMemcpy(dEntrada,hEntrada,tam,cudaMemcpyHostToDevice);
// Reservamos espacio en GPU para la imagen de salida
cudaMalloc((void **) &dSalida, tam);
// tamaño del grid y de los bloques de hebras
DimBlock= dim3(tamBloque, 1, 1); // bloques de tamBloque hebras
DimGrid= dim3( ((columnas-1)/tamBloque)+1, filas, 1); // grid 2D, x= bloques necesarios para cubrir 1 fila de la imagen, y= n filas imagen
// Llamada al kernel
sobelKernel<<<DimGrid,DimBlock>>>(dEntrada,dSalida,filas,columnas);
// Copia de resultados GPU -> host
cudaMemcpy(hSalida,dSalida,tam,cudaMemcpyDeviceToHost);
// Liberación de memoria en GPU
cudaFree(dEntrada);
cudaFree(dSalida);
} | .file "tmpxft_001b2597_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
.type _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii, @function
_Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sobelKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii, .-_Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
.globl _Z11sobelKernelPfS_ii
.type _Z11sobelKernelPfS_ii, @function
_Z11sobelKernelPfS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11sobelKernelPfS_ii, .-_Z11sobelKernelPfS_ii
.globl _Z17calcularSobelCudaPfS_ii
.type _Z17calcularSobelCudaPfS_ii, @function
_Z17calcularSobelCudaPfS_ii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $144, %rsp
.cfi_def_cfa_offset 192
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, 52(%rsp)
movl $-1, 56(%rsp)
movl $2, 60(%rsp)
movl $0, 64(%rsp)
movl $-2, 68(%rsp)
movl $1, 72(%rsp)
movl $0, 76(%rsp)
movl $-1, 80(%rsp)
movl $1, 96(%rsp)
movl $2, 100(%rsp)
movl $1, 104(%rsp)
movl $0, 108(%rsp)
movl $0, 112(%rsp)
movl $0, 116(%rsp)
movl $-1, 120(%rsp)
movl $-2, 124(%rsp)
movl $-1, 128(%rsp)
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq _ZL8mascaraX(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 96(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq _ZL8mascaraY(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %r12d, %eax
imull %ebp, %eax
leal (%rax,%rax,2), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $64, 36(%rsp)
leal 62(%rbp), %eax
movl %ebp, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $6, %eax
addl $1, %eax
movl %eax, 24(%rsp)
movl %r12d, 28(%rsp)
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movl %r12d, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z17calcularSobelCudaPfS_ii, .-_Z17calcularSobelCudaPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11sobelKernelPfS_ii"
.LC1:
.string "mascaraX"
.LC2:
.string "mascaraY"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sobelKernelPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mascaraX(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mascaraY(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8mascaraY
.comm _ZL8mascaraY,36,32
.local _ZL8mascaraX
.comm _ZL8mascaraX,36,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define tamBloque 64
__constant__ int mascaraX[3][3];
__constant__ int mascaraY[3][3];
// Kernel que se ejecutará en el grid de la GPU
__global__ void sobelKernel(float *entrada, float *salida, int filas, int columnas){
int sumx = 0;
int sumy = 0;
int SUM = 0;
int x, y;
int i, j, pix, piy;
int R, G, B, NC, posR, posG, posB;
float newPixel;
y= blockIdx.y;
x= blockIdx.x * blockDim.x + threadIdx.x;
if (y == 0 || y == filas-1 || x==0 || x == columnas-1){
SUM = 0;
}
else{
for(i=-1; i<=1; i++) {
for(j=-1; j<=1; j++) {
pix = j + x;
piy = i + y;
posR= piy*columnas + pix; // posición en el vector del componente R del pixel sobre el que trabajamos
R = (int)entrada[posR]; // imagen(pix,piy,0,0);
posG= filas*columnas + piy*columnas + pix; // posición en el vector del componente G del pixel sobre el que trabajamos
G = (int)entrada[posG]; // imagen(pix,piy,0,1);
posB= 2*filas*columnas + piy*columnas + pix; // posición en el vector del componente B del pixel sobre el que trabajamos
B = (int)entrada[posB]; // imagen(pix,piy,0,2);
NC = (R+G+B)/3;
sumx = sumx + (NC) * mascaraX[j+1][i+1];
sumy = sumy + (NC) * mascaraY[j+1][i+1];
}
}
SUM = abs(sumx) + abs(sumy);
}
if(SUM>255){
SUM=255;
}
newPixel = 255 - (float)(SUM);
salida[y*columnas + x] = newPixel; // componente R
salida[filas*columnas + y*columnas + x] = newPixel; // componente G
salida[2*filas*columnas + y*columnas + x] = newPixel; // componente B
}
// Función que lanza la ejecución de vectores en la GPU
void calcularSobelCuda (float *hEntrada, float *hSalida, int filas, int columnas){
float *dEntrada, *dSalida;
int tam;
dim3 DimGrid, DimBlock;
int Gx [3][3]; int Gy [3][3];
// Sobel Horizontal Mask
Gx[0][0] = 1; Gx[0][1] = 0; Gx[0][2] = -1;
Gx[1][0] = 2; Gx[1][1] = 0; Gx[1][2] = -2;
Gx[2][0] = 1; Gx[2][1] = 0; Gx[2][2] = -1;
// Sobel Vertical Mask
Gy[0][0] = 1; Gy[0][1] = 2; Gy[0][2] = 1;
Gy[1][0] = 0; Gy[1][1] = 0; Gy[1][2] = 0;
Gy[2][0] = -1; Gy[2][1] =-2; Gy[2][2] = -1;
// Transferimos las máscaras a la memoria constante de la GPU
cudaMemcpyToSymbol(mascaraX, Gx, 3*3*sizeof(int));
cudaMemcpyToSymbol(mascaraY, Gy, 3*3*sizeof(int));
// Espacio que ocupa en memoria la imagen
tam= filas * columnas * 3 * sizeof(float); // 3 colores (R, G, B)
// Reservamos espacio y copiamos en GPU la imagen de entrada
cudaMalloc((void **) &dEntrada, tam);
cudaMemcpy(dEntrada,hEntrada,tam,cudaMemcpyHostToDevice);
// Reservamos espacio en GPU para la imagen de salida
cudaMalloc((void **) &dSalida, tam);
// tamaño del grid y de los bloques de hebras
DimBlock= dim3(tamBloque, 1, 1); // bloques de tamBloque hebras
DimGrid= dim3( ((columnas-1)/tamBloque)+1, filas, 1); // grid 2D, x= bloques necesarios para cubrir 1 fila de la imagen, y= n filas imagen
// Llamada al kernel
sobelKernel<<<DimGrid,DimBlock>>>(dEntrada,dSalida,filas,columnas);
// Copia de resultados GPU -> host
cudaMemcpy(hSalida,dSalida,tam,cudaMemcpyDeviceToHost);
// Liberación de memoria en GPU
cudaFree(dEntrada);
cudaFree(dSalida);
} | #include <hip/hip_runtime.h>
#define tamBloque 64
__constant__ int mascaraX[3][3];
__constant__ int mascaraY[3][3];
// Kernel que se ejecutará en el grid de la GPU
__global__ void sobelKernel(float *entrada, float *salida, int filas, int columnas){
int sumx = 0;
int sumy = 0;
int SUM = 0;
int x, y;
int i, j, pix, piy;
int R, G, B, NC, posR, posG, posB;
float newPixel;
y= blockIdx.y;
x= blockIdx.x * blockDim.x + threadIdx.x;
if (y == 0 || y == filas-1 || x==0 || x == columnas-1){
SUM = 0;
}
else{
for(i=-1; i<=1; i++) {
for(j=-1; j<=1; j++) {
pix = j + x;
piy = i + y;
posR= piy*columnas + pix; // posición en el vector del componente R del pixel sobre el que trabajamos
R = (int)entrada[posR]; // imagen(pix,piy,0,0);
posG= filas*columnas + piy*columnas + pix; // posición en el vector del componente G del pixel sobre el que trabajamos
G = (int)entrada[posG]; // imagen(pix,piy,0,1);
posB= 2*filas*columnas + piy*columnas + pix; // posición en el vector del componente B del pixel sobre el que trabajamos
B = (int)entrada[posB]; // imagen(pix,piy,0,2);
NC = (R+G+B)/3;
sumx = sumx + (NC) * mascaraX[j+1][i+1];
sumy = sumy + (NC) * mascaraY[j+1][i+1];
}
}
SUM = abs(sumx) + abs(sumy);
}
if(SUM>255){
SUM=255;
}
newPixel = 255 - (float)(SUM);
salida[y*columnas + x] = newPixel; // componente R
salida[filas*columnas + y*columnas + x] = newPixel; // componente G
salida[2*filas*columnas + y*columnas + x] = newPixel; // componente B
}
// Función que lanza la ejecución de vectores en la GPU
void calcularSobelCuda (float *hEntrada, float *hSalida, int filas, int columnas){
float *dEntrada, *dSalida;
int tam;
dim3 DimGrid, DimBlock;
int Gx [3][3]; int Gy [3][3];
// Sobel Horizontal Mask
Gx[0][0] = 1; Gx[0][1] = 0; Gx[0][2] = -1;
Gx[1][0] = 2; Gx[1][1] = 0; Gx[1][2] = -2;
Gx[2][0] = 1; Gx[2][1] = 0; Gx[2][2] = -1;
// Sobel Vertical Mask
Gy[0][0] = 1; Gy[0][1] = 2; Gy[0][2] = 1;
Gy[1][0] = 0; Gy[1][1] = 0; Gy[1][2] = 0;
Gy[2][0] = -1; Gy[2][1] =-2; Gy[2][2] = -1;
// Transferimos las máscaras a la memoria constante de la GPU
hipMemcpyToSymbol(HIP_SYMBOL(mascaraX), Gx, 3*3*sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(mascaraY), Gy, 3*3*sizeof(int));
// Espacio que ocupa en memoria la imagen
tam= filas * columnas * 3 * sizeof(float); // 3 colores (R, G, B)
// Reservamos espacio y copiamos en GPU la imagen de entrada
hipMalloc((void **) &dEntrada, tam);
hipMemcpy(dEntrada,hEntrada,tam,hipMemcpyHostToDevice);
// Reservamos espacio en GPU para la imagen de salida
hipMalloc((void **) &dSalida, tam);
// tamaño del grid y de los bloques de hebras
DimBlock= dim3(tamBloque, 1, 1); // bloques de tamBloque hebras
DimGrid= dim3( ((columnas-1)/tamBloque)+1, filas, 1); // grid 2D, x= bloques necesarios para cubrir 1 fila de la imagen, y= n filas imagen
// Llamada al kernel
sobelKernel<<<DimGrid,DimBlock>>>(dEntrada,dSalida,filas,columnas);
// Copia de resultados GPU -> host
hipMemcpy(hSalida,dSalida,tam,hipMemcpyDeviceToHost);
// Liberación de memoria en GPU
hipFree(dEntrada);
hipFree(dSalida);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define tamBloque 64
__constant__ int mascaraX[3][3];
__constant__ int mascaraY[3][3];
// Kernel que se ejecutará en el grid de la GPU
__global__ void sobelKernel(float *entrada, float *salida, int filas, int columnas){
int sumx = 0;
int sumy = 0;
int SUM = 0;
int x, y;
int i, j, pix, piy;
int R, G, B, NC, posR, posG, posB;
float newPixel;
y= blockIdx.y;
x= blockIdx.x * blockDim.x + threadIdx.x;
if (y == 0 || y == filas-1 || x==0 || x == columnas-1){
SUM = 0;
}
else{
for(i=-1; i<=1; i++) {
for(j=-1; j<=1; j++) {
pix = j + x;
piy = i + y;
posR= piy*columnas + pix; // posición en el vector del componente R del pixel sobre el que trabajamos
R = (int)entrada[posR]; // imagen(pix,piy,0,0);
posG= filas*columnas + piy*columnas + pix; // posición en el vector del componente G del pixel sobre el que trabajamos
G = (int)entrada[posG]; // imagen(pix,piy,0,1);
posB= 2*filas*columnas + piy*columnas + pix; // posición en el vector del componente B del pixel sobre el que trabajamos
B = (int)entrada[posB]; // imagen(pix,piy,0,2);
NC = (R+G+B)/3;
sumx = sumx + (NC) * mascaraX[j+1][i+1];
sumy = sumy + (NC) * mascaraY[j+1][i+1];
}
}
SUM = abs(sumx) + abs(sumy);
}
if(SUM>255){
SUM=255;
}
newPixel = 255 - (float)(SUM);
salida[y*columnas + x] = newPixel; // componente R
salida[filas*columnas + y*columnas + x] = newPixel; // componente G
salida[2*filas*columnas + y*columnas + x] = newPixel; // componente B
}
// Función que lanza la ejecución de vectores en la GPU
void calcularSobelCuda (float *hEntrada, float *hSalida, int filas, int columnas){
float *dEntrada, *dSalida;
int tam;
dim3 DimGrid, DimBlock;
int Gx [3][3]; int Gy [3][3];
// Sobel Horizontal Mask
Gx[0][0] = 1; Gx[0][1] = 0; Gx[0][2] = -1;
Gx[1][0] = 2; Gx[1][1] = 0; Gx[1][2] = -2;
Gx[2][0] = 1; Gx[2][1] = 0; Gx[2][2] = -1;
// Sobel Vertical Mask
Gy[0][0] = 1; Gy[0][1] = 2; Gy[0][2] = 1;
Gy[1][0] = 0; Gy[1][1] = 0; Gy[1][2] = 0;
Gy[2][0] = -1; Gy[2][1] =-2; Gy[2][2] = -1;
// Transferimos las máscaras a la memoria constante de la GPU
hipMemcpyToSymbol(HIP_SYMBOL(mascaraX), Gx, 3*3*sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(mascaraY), Gy, 3*3*sizeof(int));
// Espacio que ocupa en memoria la imagen
tam= filas * columnas * 3 * sizeof(float); // 3 colores (R, G, B)
// Reservamos espacio y copiamos en GPU la imagen de entrada
hipMalloc((void **) &dEntrada, tam);
hipMemcpy(dEntrada,hEntrada,tam,hipMemcpyHostToDevice);
// Reservamos espacio en GPU para la imagen de salida
hipMalloc((void **) &dSalida, tam);
// tamaño del grid y de los bloques de hebras
DimBlock= dim3(tamBloque, 1, 1); // bloques de tamBloque hebras
DimGrid= dim3( ((columnas-1)/tamBloque)+1, filas, 1); // grid 2D, x= bloques necesarios para cubrir 1 fila de la imagen, y= n filas imagen
// Llamada al kernel
sobelKernel<<<DimGrid,DimBlock>>>(dEntrada,dSalida,filas,columnas);
// Copia de resultados GPU -> host
hipMemcpy(hSalida,dSalida,tam,hipMemcpyDeviceToHost);
// Liberación de memoria en GPU
hipFree(dEntrada);
hipFree(dSalida);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sobelKernelPfS_ii
.globl _Z11sobelKernelPfS_ii
.p2align 8
.type _Z11sobelKernelPfS_ii,@function
_Z11sobelKernelPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_eq_u32 s15, 0
s_mul_i32 s6, s14, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s6, v0
s_cbranch_scc1 .LBB0_8
s_add_i32 s2, s4, -1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_cmp_lg_u32 s15, s2
v_mov_b32_e32 v2, 0
s_cselect_b32 s3, -1, 0
s_add_i32 s2, s5, -1
s_and_b32 s3, s3, vcc_lo
v_cmp_ne_u32_e64 s2, s2, v1
s_mov_b32 s16, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s7, s15, -1
s_lshl_b32 s9, s4, 1
s_mul_i32 s8, s5, s7
s_add_i32 s10, s7, s4
s_add_i32 s8, s6, s8
s_add_i32 s7, s7, s9
v_add3_u32 v5, s8, v0, -1
s_mul_i32 s8, s5, s10
s_mul_i32 s7, s5, s7
s_add_i32 s8, s6, s8
s_add_i32 s6, s6, s7
v_add3_u32 v6, s8, v0, -1
v_add3_u32 v0, s6, v0, -1
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, mascaraX@rel32@lo+4
s_addc_u32 s7, s7, mascaraX@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mascaraY@rel32@lo+4
s_addc_u32 s9, s9, mascaraY@rel32@hi+12
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[10:11], s[8:9]
s_mov_b64 s[12:13], s[6:7]
s_mov_b32 s17, 0
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, s17, v5
v_add_nc_u32_e32 v9, s17, v6
v_add_nc_u32_e32 v11, s17, v0
s_add_i32 s17, s17, 1
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_clause 0x2
global_load_b32 v4, v[7:8], off
global_load_b32 v7, v[9:10], off
global_load_b32 v8, v[11:12], off
s_load_b32 s18, s[12:13], 0x0
s_load_b32 s19, s[10:11], 0x0
s_add_u32 s12, s12, 12
s_addc_u32 s13, s13, 0
s_add_u32 s10, s10, 12
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s17, 3
s_waitcnt vmcnt(2)
v_cvt_i32_f32_e32 v4, v4
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v7, v7
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v7, v4, v8
v_mul_hi_i32 v8, v4, 0x55555556
v_mov_b32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v9, 31, v8
v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v8, v8, v9
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v8, s18, v[4:5]
v_mad_u64_u32 v[3:4], null, v8, s19, v[7:8]
s_cbranch_scc1 .LBB0_4
s_add_i32 s16, s16, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
v_add_nc_u32_e32 v5, s5, v5
v_add_nc_u32_e32 v6, s5, v6
v_add_nc_u32_e32 v0, s5, v0
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s16, 2
s_cbranch_scc1 .LBB0_3
v_sub_nc_u32_e32 v0, 0, v2
v_sub_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_max_i32_e32 v0, v2, v0
v_max_i32_e32 v2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, v0, v2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s5, v[1:2]
s_add_i32 s2, s15, s4
s_lshl_b32 s3, s4, 1
v_mad_u64_u32 v[5:6], null, s2, s5, v[1:2]
s_add_i32 s3, s3, s15
v_min_i32_e32 v0, 0xff, v2
v_mad_u64_u32 v[7:8], null, s3, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_cvt_f32_i32_e32 v2, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_ashrrev_i32_e32 v8, 31, v7
v_sub_f32_e32 v9, 0x437f0000, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[4:5], 2, v[7:8]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x2
global_store_b32 v[0:1], v9, off
global_store_b32 v[2:3], v9, off
global_store_b32 v[4:5], v9, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sobelKernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sobelKernelPfS_ii, .Lfunc_end0-_Z11sobelKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected mascaraX
.type mascaraX,@object
.section .bss,"aw",@nobits
.globl mascaraX
.p2align 4, 0x0
mascaraX:
.zero 36
.size mascaraX, 36
.protected mascaraY
.type mascaraY,@object
.globl mascaraY
.p2align 4, 0x0
mascaraY:
.zero 36
.size mascaraY, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym mascaraX
.addrsig_sym mascaraY
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sobelKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z11sobelKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define tamBloque 64
__constant__ int mascaraX[3][3];
__constant__ int mascaraY[3][3];
// Kernel que se ejecutará en el grid de la GPU
__global__ void sobelKernel(float *entrada, float *salida, int filas, int columnas){
int sumx = 0;
int sumy = 0;
int SUM = 0;
int x, y;
int i, j, pix, piy;
int R, G, B, NC, posR, posG, posB;
float newPixel;
y= blockIdx.y;
x= blockIdx.x * blockDim.x + threadIdx.x;
if (y == 0 || y == filas-1 || x==0 || x == columnas-1){
SUM = 0;
}
else{
for(i=-1; i<=1; i++) {
for(j=-1; j<=1; j++) {
pix = j + x;
piy = i + y;
posR= piy*columnas + pix; // posición en el vector del componente R del pixel sobre el que trabajamos
R = (int)entrada[posR]; // imagen(pix,piy,0,0);
posG= filas*columnas + piy*columnas + pix; // posición en el vector del componente G del pixel sobre el que trabajamos
G = (int)entrada[posG]; // imagen(pix,piy,0,1);
posB= 2*filas*columnas + piy*columnas + pix; // posición en el vector del componente B del pixel sobre el que trabajamos
B = (int)entrada[posB]; // imagen(pix,piy,0,2);
NC = (R+G+B)/3;
sumx = sumx + (NC) * mascaraX[j+1][i+1];
sumy = sumy + (NC) * mascaraY[j+1][i+1];
}
}
SUM = abs(sumx) + abs(sumy);
}
if(SUM>255){
SUM=255;
}
newPixel = 255 - (float)(SUM);
salida[y*columnas + x] = newPixel; // componente R
salida[filas*columnas + y*columnas + x] = newPixel; // componente G
salida[2*filas*columnas + y*columnas + x] = newPixel; // componente B
}
// Función que lanza la ejecución de vectores en la GPU
void calcularSobelCuda (float *hEntrada, float *hSalida, int filas, int columnas){
float *dEntrada, *dSalida;
int tam;
dim3 DimGrid, DimBlock;
int Gx [3][3]; int Gy [3][3];
// Sobel Horizontal Mask
Gx[0][0] = 1; Gx[0][1] = 0; Gx[0][2] = -1;
Gx[1][0] = 2; Gx[1][1] = 0; Gx[1][2] = -2;
Gx[2][0] = 1; Gx[2][1] = 0; Gx[2][2] = -1;
// Sobel Vertical Mask
Gy[0][0] = 1; Gy[0][1] = 2; Gy[0][2] = 1;
Gy[1][0] = 0; Gy[1][1] = 0; Gy[1][2] = 0;
Gy[2][0] = -1; Gy[2][1] =-2; Gy[2][2] = -1;
// Transferimos las máscaras a la memoria constante de la GPU
hipMemcpyToSymbol(HIP_SYMBOL(mascaraX), Gx, 3*3*sizeof(int));
hipMemcpyToSymbol(HIP_SYMBOL(mascaraY), Gy, 3*3*sizeof(int));
// Espacio que ocupa en memoria la imagen
tam= filas * columnas * 3 * sizeof(float); // 3 colores (R, G, B)
// Reservamos espacio y copiamos en GPU la imagen de entrada
hipMalloc((void **) &dEntrada, tam);
hipMemcpy(dEntrada,hEntrada,tam,hipMemcpyHostToDevice);
// Reservamos espacio en GPU para la imagen de salida
hipMalloc((void **) &dSalida, tam);
// tamaño del grid y de los bloques de hebras
DimBlock= dim3(tamBloque, 1, 1); // bloques de tamBloque hebras
DimGrid= dim3( ((columnas-1)/tamBloque)+1, filas, 1); // grid 2D, x= bloques necesarios para cubrir 1 fila de la imagen, y= n filas imagen
// Llamada al kernel
sobelKernel<<<DimGrid,DimBlock>>>(dEntrada,dSalida,filas,columnas);
// Copia de resultados GPU -> host
hipMemcpy(hSalida,dSalida,tam,hipMemcpyDeviceToHost);
// Liberación de memoria en GPU
hipFree(dEntrada);
hipFree(dSalida);
} | .text
.file "sobel.hip"
.globl _Z26__device_stub__sobelKernelPfS_ii # -- Begin function _Z26__device_stub__sobelKernelPfS_ii
.p2align 4, 0x90
.type _Z26__device_stub__sobelKernelPfS_ii,@function
_Z26__device_stub__sobelKernelPfS_ii: # @_Z26__device_stub__sobelKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sobelKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__sobelKernelPfS_ii, .Lfunc_end0-_Z26__device_stub__sobelKernelPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z17calcularSobelCudaPfS_ii
.LCPI1_0:
.long 1 # 0x1
.long 0 # 0x0
.long 4294967295 # 0xffffffff
.long 2 # 0x2
.LCPI1_1:
.long 0 # 0x0
.long 4294967294 # 0xfffffffe
.long 1 # 0x1
.long 0 # 0x0
.LCPI1_2:
.long 1 # 0x1
.long 2 # 0x2
.long 1 # 0x1
.long 0 # 0x0
.LCPI1_3:
.long 0 # 0x0
.long 0 # 0x0
.long 4294967295 # 0xffffffff
.long 4294967294 # 0xfffffffe
.text
.globl _Z17calcularSobelCudaPfS_ii
.p2align 4, 0x90
.type _Z17calcularSobelCudaPfS_ii,@function
_Z17calcularSobelCudaPfS_ii: # @_Z17calcularSobelCudaPfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $224, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movl %edx, %r12d
movq %rsi, %rbx
movq %rdi, %r13
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,0,4294967295,2]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [0,4294967294,1,0]
movaps %xmm0, 192(%rsp)
movl $-1, 208(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [1,2,1,0]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [0,0,4294967295,4294967294]
movaps %xmm0, 144(%rsp)
movl $-1, 160(%rsp)
leaq 176(%rsp), %rsi
movl $mascaraX, %edi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 128(%rsp), %rsi
movl $mascaraY, %edi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl %r12d, %eax
imull %r15d, %eax
shll $2, %eax
leal (%rax,%rax,2), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal -1(%r15), %eax
leal 62(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $6, %ecx
incl %ecx
movq %r12, %rdi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $4294967360, %rdx # imm = 0x100000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r12d, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11sobelKernelPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $224, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17calcularSobelCudaPfS_ii, .Lfunc_end1-_Z17calcularSobelCudaPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sobelKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $mascaraX, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mascaraY, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type mascaraX,@object # @mascaraX
.local mascaraX
.comm mascaraX,36,16
.type mascaraY,@object # @mascaraY
.local mascaraY
.comm mascaraY,36,16
.type _Z11sobelKernelPfS_ii,@object # @_Z11sobelKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z11sobelKernelPfS_ii
.p2align 3, 0x0
_Z11sobelKernelPfS_ii:
.quad _Z26__device_stub__sobelKernelPfS_ii
.size _Z11sobelKernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11sobelKernelPfS_ii"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "mascaraX"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mascaraY"
.size .L__unnamed_3, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sobelKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mascaraX
.addrsig_sym mascaraY
.addrsig_sym _Z11sobelKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11sobelKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0030*/ BSSY B0, 0x970 ; /* 0x0000093000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002500 */
/*0060*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e660000002100 */
/*0080*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf05270 */
/*0090*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fc6000fffe13f */
/*00a0*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fe20004702670 */
/*00b0*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */
/* 0x002fca00078e0202 */
/*00c0*/ ISETP.EQ.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fc80000702670 */
/*00d0*/ ISETP.EQ.OR P0, PT, R11, UR4, P0 ; /* 0x000000040b007c0c */
/* 0x000fe20008702670 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00f0*/ @P0 BRA 0x950 ; /* 0x0000085000000947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fc600000001ff */
/*0120*/ IADD3 R4, R2.reuse, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x040fe20007ffe0ff */
/*0130*/ IMAD R23, R2, c[0x0][0x174], R11 ; /* 0x00005d0002177a24 */
/* 0x000fc600078e020b */
/*0140*/ IADD3 R6, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD R3, R4, c[0x0][0x174], R11 ; /* 0x00005d0004037a24 */
/* 0x000fe400078e020b */
/*0160*/ IMAD.WIDE R4, R23, R8, c[0x0][0x160] ; /* 0x0000580017047625 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD R13, R6, c[0x0][0x174], R11 ; /* 0x00005d00060d7a24 */
/* 0x000fe200078e020b */
/*0180*/ LDG.E R18, [R4.64+-0x4] ; /* 0xfffffc0404127981 */
/* 0x0000a2000c1e1900 */
/*0190*/ IMAD.WIDE R2, R3, R8, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0208 */
/*01a0*/ LDG.E R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x0000e2000c1e1900 */
/*01b0*/ IMAD.WIDE R12, R13, R8, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc600078e0208 */
/*01c0*/ LDG.E R25, [R2.64+-0x4] ; /* 0xfffffc0402197981 */
/* 0x000328000c1e1900 */
/*01d0*/ LDG.E R26, [R12.64+-0x4] ; /* 0xfffffc040c1a7981 */
/* 0x000ae8000c1e1900 */
/*01e0*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x0002e8000c1e1900 */
/*01f0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000ae8000c1e1900 */
/*0200*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x0000e8000c1e1900 */
/*0210*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x0002e8000c1e1900 */
/*0220*/ LDG.E R20, [R12.64+0x4] ; /* 0x000004040c147981 */
/* 0x000ae2000c1e1900 */
/*0230*/ HFMA2.MMA R29, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff1d7435 */
/* 0x000fe200000001ff */
/*0240*/ IADD3 R24, R0, 0x1, RZ ; /* 0x0000000100187810 */
/* 0x000fc40007ffe0ff */
/*0250*/ MOV R27, c[0x0][0x170] ; /* 0x00005c00001b7a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD R7, R0, c[0x0][0x174], R11.reuse ; /* 0x00005d0000077a24 */
/* 0x100fe400078e020b */
/*0270*/ IMAD R3, R24, c[0x0][0x174], R11 ; /* 0x00005d0018037a24 */
/* 0x002fe200078e020b */
/*0280*/ LEA R28, R27, R0, 0x1 ; /* 0x000000001b1c7211 */
/* 0x000fc600078e08ff */
/*0290*/ IADD3 R29, R29, c[0x0][0x170], RZ ; /* 0x00005c001d1d7a10 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0208 */
/*02b0*/ IADD3 R27, R23, -0x1, RZ ; /* 0xffffffff171b7810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ IMAD.WIDE R2, R3, R8.reuse, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x080fe200078e0208 */
/*02d0*/ LDG.E R12, [R6.64+-0x4] ; /* 0xfffffc04060c7981 */
/* 0x020366000c1e1900 */
/*02e0*/ IMAD R23, R29, c[0x0][0x174], RZ ; /* 0x00005d001d177a24 */
/* 0x000fe200078e02ff */
/*02f0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000366000c1e1900 */
/*0300*/ IMAD.WIDE R4, R23, 0x4, R4 ; /* 0x0000000417047825 */
/* 0x001fe200078e0204 */
/*0310*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000404060e7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc04020f7981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000162000c1e1900 */
/*0340*/ IMAD.WIDE R6, R27, R8, c[0x0][0x160] ; /* 0x000058001b067625 */
/* 0x002fc600078e0208 */
/*0350*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000162000c1e1900 */
/*0360*/ IADD3 R24, R24, c[0x0][0x170], RZ ; /* 0x00005c0018187a10 */
/* 0x000fe40007ffe0ff */
/*0370*/ IMAD.WIDE R6, R23, 0x4, R6 ; /* 0x0000000417067825 */
/* 0x000fcc00078e0206 */
/*0380*/ IMAD.WIDE R6, R23, 0x4, R6 ; /* 0x0000000417067825 */
/* 0x000fe200078e0206 */
/*0390*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x004ff0000020f100 */
/*03a0*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x010ff0000020f100 */
/*03b0*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x008e70000020f100 */
/*03c0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000ff0000020f100 */
/*03d0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000fe2000020f100 */
/*03e0*/ IADD3 R18, R26, R25, R18 ; /* 0x000000191a127210 */
/* 0x002fce0007ffe012 */
/*03f0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e62000020f100 */
/*0400*/ IMAD R25, R28, c[0x0][0x174], R11 ; /* 0x00005d001c197a24 */
/* 0x000fc800078e020b */
/*0410*/ IMAD.WIDE R2, R25, R8, c[0x0][0x160] ; /* 0x0000580019027625 */
/* 0x001fe400078e0208 */
/*0420*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x0000a2000c1e1900 */
/*0430*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000fe6000020f100 */
/*0440*/ LDG.E R26, [R2.64+-0x4] ; /* 0xfffffc04021a7981 */
/* 0x000ee8000c1e1900 */
/*0450*/ LDG.E R27, [R2.64] ; /* 0x00000004021b7981 */
/* 0x0008a2000c1e1900 */
/*0460*/ F2I.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000fe2000020f100 */
/*0470*/ IADD3 R21, R9, R22, R21 ; /* 0x0000001609157210 */
/* 0x002fc40007ffe015 */
/*0480*/ LDG.E R22, [R4.64+-0x4] ; /* 0xfffffc0404167981 */
/* 0x00012a000c1e1900 */
/*0490*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e62000020f100 */
/*04a0*/ IMAD R9, R24, c[0x0][0x174], R11 ; /* 0x00005d0018097a24 */
/* 0x000fe200078e020b */
/*04b0*/ LDG.E R28, [R2.64+0x4] ; /* 0x00000404021c7981 */
/* 0x0008a8000c1e1900 */
/*04c0*/ LDG.E R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x0000a2000c1e1900 */
/*04d0*/ IMAD.WIDE R8, R9, R8, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fca00078e0208 */
/*04e0*/ LDG.E R29, [R8.64+-0x4] ; /* 0xfffffc04081d7981 */
/* 0x0000a2000c1e1900 */
/*04f0*/ IADD3 R19, R20, R19, R10 ; /* 0x0000001314137210 */
/* 0x002fc60007ffe00a */
/*0500*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0002a8000c1e1900 */
/*0510*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R4, [R6.64+0x4] ; /* 0x0000040406047981 */
/* 0x001ea8000c1e1900 */
/*0530*/ LDG.E R8, [R8.64+0x4] ; /* 0x0000040408087981 */
/* 0x002ea8000c1e1900 */
/*0540*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea2000c1e1900 */
/*0550*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x020fe2000020f100 */
/*0560*/ IMAD.HI R18, R18, 0x55555556, RZ ; /* 0x5555555612127827 */
/* 0x000fce00078e02ff */
/*0570*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000fe2000020f100 */
/*0580*/ IMAD.HI R21, R21, 0x55555556, RZ ; /* 0x5555555615157827 */
/* 0x000fe200078e02ff */
/*0590*/ LEA.HI R18, R18, R18, RZ, 0x1 ; /* 0x0000001212127211 */
/* 0x000fcc00078f08ff */
/*05a0*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000fe2000020f100 */
/*05b0*/ IMAD.HI R19, R19, 0x55555556, RZ ; /* 0x5555555613137827 */
/* 0x000fe200078e02ff */
/*05c0*/ LEA.HI R21, R21, R21, RZ, 0x1 ; /* 0x0000001515157211 */
/* 0x000fcc00078f08ff */
/*05d0*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000fe2000020f100 */
/*05e0*/ LEA.HI R19, R19, R19, RZ, 0x1 ; /* 0x0000001313137211 */
/* 0x000fce00078f08ff */
/*05f0*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000ff0000020f100 */
/*0600*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000ff0000020f100 */
/*0610*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x008ff0000020f100 */
/*0620*/ F2I.TRUNC.NTZ R3, R22 ; /* 0x0000001600037305 */
/* 0x010e30000020f100 */
/*0630*/ F2I.TRUNC.NTZ R27, R27 ; /* 0x0000001b001b7305 */
/* 0x004ff0000020f100 */
/*0640*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e70000020f100 */
/*0650*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000ff0000020f100 */
/*0660*/ F2I.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000ea2000020f100 */
/*0670*/ IADD3 R12, R26, R3, R12 ; /* 0x000000031a0c7210 */
/* 0x001fe20007ffe00c */
/*0680*/ IMAD R3, R18, c[0x3][0x0], RZ ; /* 0x00c0000012037a24 */
/* 0x000fcc00078e02ff */
/*0690*/ F2I.TRUNC.NTZ R2, R29 ; /* 0x0000001d00027305 */
/* 0x000fe2000020f100 */
/*06a0*/ IMAD R18, R18, c[0x3][0x24], RZ ; /* 0x00c0090012127a24 */
/* 0x000fce00078e02ff */
/*06b0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*06c0*/ IADD3 R13, R27, R24, R13 ; /* 0x000000181b0d7210 */
/* 0x002fe20007ffe00d */
/*06d0*/ IMAD.HI R12, R12, 0x55555556, RZ ; /* 0x555555560c0c7827 */
/* 0x000fcc00078e02ff */
/*06e0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000fe2000020f100 */
/*06f0*/ IMAD R3, R21, c[0x3][0xc], R3 ; /* 0x00c0030015037a24 */
/* 0x000fce00078e0203 */
/*0700*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e62000020f100 */
/*0710*/ IMAD R18, R21, c[0x3][0x30], R18 ; /* 0x00c00c0015127a24 */
/* 0x000fe200078e0212 */
/*0720*/ IADD3 R14, R28, R25, R14 ; /* 0x000000191c0e7210 */
/* 0x004fe20007ffe00e */
/*0730*/ IMAD.HI R13, R13, 0x55555556, RZ ; /* 0x555555560d0d7827 */
/* 0x000fca00078e02ff */
/*0740*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000fe2000020f100 */
/*0750*/ LEA.HI R12, R12, R12, RZ, 0x1 ; /* 0x0000000c0c0c7211 */
/* 0x000fce00078f08ff */
/*0760*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000ea2000020f100 */
/*0770*/ IMAD R3, R19.reuse, c[0x3][0x18], R3 ; /* 0x00c0060013037a24 */
/* 0x040fe200078e0203 */
/*0780*/ IADD3 R2, R10, R2, R15 ; /* 0x000000020a027210 */
/* 0x001fe20007ffe00f */
/*0790*/ IMAD R18, R19, c[0x3][0x3c], R18 ; /* 0x00c00f0013127a24 */
/* 0x000fe200078e0212 */
/*07a0*/ LEA.HI R13, R13, R13, RZ, 0x1 ; /* 0x0000000d0d0d7211 */
/* 0x000fe200078f08ff */
/*07b0*/ IMAD.HI R14, R14, 0x55555556, RZ ; /* 0x555555560e0e7827 */
/* 0x000fe200078e02ff */
/*07c0*/ IADD3 R4, R4, R23, R16 ; /* 0x0000001704047210 */
/* 0x002fc60007ffe010 */
/*07d0*/ IMAD R3, R12.reuse, c[0x3][0x4], R3 ; /* 0x00c001000c037a24 */
/* 0x040fe400078e0203 */
/*07e0*/ IMAD R18, R12, c[0x3][0x28], R18 ; /* 0x00c00a000c127a24 */
/* 0x000fe200078e0212 */
/*07f0*/ LEA.HI R14, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0e7211 */
/* 0x000fe200078f08ff */
/*0800*/ IMAD.HI R2, R2, 0x55555556, RZ ; /* 0x5555555602027827 */
/* 0x000fe200078e02ff */
/*0810*/ IADD3 R5, R5, R8, R17 ; /* 0x0000000805057210 */
/* 0x004fc60007ffe011 */
/*0820*/ IMAD R3, R13.reuse, c[0x3][0x10], R3 ; /* 0x00c004000d037a24 */
/* 0x040fe400078e0203 */
/*0830*/ IMAD R18, R13, c[0x3][0x34], R18 ; /* 0x00c00d000d127a24 */
/* 0x000fe200078e0212 */
/*0840*/ LEA.HI R2, R2, R2, RZ, 0x1 ; /* 0x0000000202027211 */
/* 0x000fe200078f08ff */
/*0850*/ IMAD.HI R4, R4, 0x55555556, RZ ; /* 0x5555555604047827 */
/* 0x000fc800078e02ff */
/*0860*/ IMAD R18, R14.reuse, c[0x3][0x40], R18 ; /* 0x00c010000e127a24 */
/* 0x040fe400078e0212 */
/*0870*/ IMAD R3, R14, c[0x3][0x1c], R3 ; /* 0x00c007000e037a24 */
/* 0x000fe200078e0203 */
/*0880*/ LEA.HI R4, R4, R4, RZ, 0x1 ; /* 0x0000000404047211 */
/* 0x000fe200078f08ff */
/*0890*/ IMAD.HI R5, R5, 0x55555556, RZ ; /* 0x5555555605057827 */
/* 0x000fc800078e02ff */
/*08a0*/ IMAD R18, R2.reuse, c[0x3][0x2c], R18 ; /* 0x00c00b0002127a24 */
/* 0x040fe400078e0212 */
/*08b0*/ IMAD R3, R2, c[0x3][0x8], R3 ; /* 0x00c0020002037a24 */
/* 0x000fe200078e0203 */
/*08c0*/ LEA.HI R5, R5, R5, RZ, 0x1 ; /* 0x0000000505057211 */
/* 0x000fe200078f08ff */
/*08d0*/ IMAD R18, R4.reuse, c[0x3][0x38], R18 ; /* 0x00c00e0004127a24 */
/* 0x040fe400078e0212 */
/*08e0*/ IMAD R3, R4, c[0x3][0x14], R3 ; /* 0x00c0050004037a24 */
/* 0x000fe400078e0203 */
/*08f0*/ IMAD R18, R5.reuse, c[0x3][0x44], R18 ; /* 0x00c0110005127a24 */
/* 0x040fe400078e0212 */
/*0900*/ IMAD R3, R5, c[0x3][0x20], R3 ; /* 0x00c0080005037a24 */
/* 0x000fc600078e0203 */
/*0910*/ IABS R2, R18 ; /* 0x0000001200027213 */
/* 0x000fe40000000000 */
/*0920*/ IABS R3, R3 ; /* 0x0000000300037213 */
/* 0x000fc80000000000 */
/*0930*/ IADD3 R2, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x000fe20007ffe0ff */
/*0940*/ BRA 0x960 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0950*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ IMNMX R8, R2, 0xff, PT ; /* 0x000000ff02087817 */
/* 0x000fe20003800200 */
/*0980*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0990*/ IMAD R2, R0, c[0x0][0x174], R11 ; /* 0x00005d0000027a24 */
/* 0x000fe200078e020b */
/*09a0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fc60000000f00 */
/*09b0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e240000201400 */
/*09c0*/ IMAD R7, R7, c[0x0][0x170], RZ ; /* 0x00005c0007077a24 */
/* 0x000fc600078e02ff */
/*09d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*09e0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fc800078e0202 */
/*09f0*/ FADD R9, -R8, 255 ; /* 0x437f000008097421 */
/* 0x001fe40000000100 */
/*0a00*/ IMAD.WIDE R6, R7, 0x4, R4 ; /* 0x0000000407067825 */
/* 0x000fc600078e0204 */
/*0a10*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0a20*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0a30*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0a40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sobelKernelPfS_ii
.globl _Z11sobelKernelPfS_ii
.p2align 8
.type _Z11sobelKernelPfS_ii,@function
_Z11sobelKernelPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_eq_u32 s15, 0
s_mul_i32 s6, s14, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s6, v0
s_cbranch_scc1 .LBB0_8
s_add_i32 s2, s4, -1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_cmp_lg_u32 s15, s2
v_mov_b32_e32 v2, 0
s_cselect_b32 s3, -1, 0
s_add_i32 s2, s5, -1
s_and_b32 s3, s3, vcc_lo
v_cmp_ne_u32_e64 s2, s2, v1
s_mov_b32 s16, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s7, s15, -1
s_lshl_b32 s9, s4, 1
s_mul_i32 s8, s5, s7
s_add_i32 s10, s7, s4
s_add_i32 s8, s6, s8
s_add_i32 s7, s7, s9
v_add3_u32 v5, s8, v0, -1
s_mul_i32 s8, s5, s10
s_mul_i32 s7, s5, s7
s_add_i32 s8, s6, s8
s_add_i32 s6, s6, s7
v_add3_u32 v6, s8, v0, -1
v_add3_u32 v0, s6, v0, -1
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, mascaraX@rel32@lo+4
s_addc_u32 s7, s7, mascaraX@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mascaraY@rel32@lo+4
s_addc_u32 s9, s9, mascaraY@rel32@hi+12
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[10:11], s[8:9]
s_mov_b64 s[12:13], s[6:7]
s_mov_b32 s17, 0
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, s17, v5
v_add_nc_u32_e32 v9, s17, v6
v_add_nc_u32_e32 v11, s17, v0
s_add_i32 s17, s17, 1
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_clause 0x2
global_load_b32 v4, v[7:8], off
global_load_b32 v7, v[9:10], off
global_load_b32 v8, v[11:12], off
s_load_b32 s18, s[12:13], 0x0
s_load_b32 s19, s[10:11], 0x0
s_add_u32 s12, s12, 12
s_addc_u32 s13, s13, 0
s_add_u32 s10, s10, 12
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s17, 3
s_waitcnt vmcnt(2)
v_cvt_i32_f32_e32 v4, v4
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v7, v7
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v7, v4, v8
v_mul_hi_i32 v8, v4, 0x55555556
v_mov_b32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v9, 31, v8
v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v8, v8, v9
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v8, s18, v[4:5]
v_mad_u64_u32 v[3:4], null, v8, s19, v[7:8]
s_cbranch_scc1 .LBB0_4
s_add_i32 s16, s16, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
v_add_nc_u32_e32 v5, s5, v5
v_add_nc_u32_e32 v6, s5, v6
v_add_nc_u32_e32 v0, s5, v0
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s16, 2
s_cbranch_scc1 .LBB0_3
v_sub_nc_u32_e32 v0, 0, v2
v_sub_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_max_i32_e32 v0, v2, v0
v_max_i32_e32 v2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, v0, v2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s5, v[1:2]
s_add_i32 s2, s15, s4
s_lshl_b32 s3, s4, 1
v_mad_u64_u32 v[5:6], null, s2, s5, v[1:2]
s_add_i32 s3, s3, s15
v_min_i32_e32 v0, 0xff, v2
v_mad_u64_u32 v[7:8], null, s3, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_cvt_f32_i32_e32 v2, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_ashrrev_i32_e32 v8, 31, v7
v_sub_f32_e32 v9, 0x437f0000, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[4:5], 2, v[7:8]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x2
global_store_b32 v[0:1], v9, off
global_store_b32 v[2:3], v9, off
global_store_b32 v[4:5], v9, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sobelKernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sobelKernelPfS_ii, .Lfunc_end0-_Z11sobelKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected mascaraX
.type mascaraX,@object
.section .bss,"aw",@nobits
.globl mascaraX
.p2align 4, 0x0
mascaraX:
.zero 36
.size mascaraX, 36
.protected mascaraY
.type mascaraY,@object
.globl mascaraY
.p2align 4, 0x0
mascaraY:
.zero 36
.size mascaraY, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym mascaraX
.addrsig_sym mascaraY
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sobelKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z11sobelKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2597_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
.type _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii, @function
_Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sobelKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii, .-_Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
.globl _Z11sobelKernelPfS_ii
.type _Z11sobelKernelPfS_ii, @function
_Z11sobelKernelPfS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11sobelKernelPfS_ii, .-_Z11sobelKernelPfS_ii
.globl _Z17calcularSobelCudaPfS_ii
.type _Z17calcularSobelCudaPfS_ii, @function
_Z17calcularSobelCudaPfS_ii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $144, %rsp
.cfi_def_cfa_offset 192
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, 52(%rsp)
movl $-1, 56(%rsp)
movl $2, 60(%rsp)
movl $0, 64(%rsp)
movl $-2, 68(%rsp)
movl $1, 72(%rsp)
movl $0, 76(%rsp)
movl $-1, 80(%rsp)
movl $1, 96(%rsp)
movl $2, 100(%rsp)
movl $1, 104(%rsp)
movl $0, 108(%rsp)
movl $0, 112(%rsp)
movl $0, 116(%rsp)
movl $-1, 120(%rsp)
movl $-2, 124(%rsp)
movl $-1, 128(%rsp)
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq _ZL8mascaraX(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 96(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq _ZL8mascaraY(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %r12d, %eax
imull %ebp, %eax
leal (%rax,%rax,2), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $64, 36(%rsp)
leal 62(%rbp), %eax
movl %ebp, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $6, %eax
addl $1, %eax
movl %eax, 24(%rsp)
movl %r12d, 28(%rsp)
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movl %r12d, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z11sobelKernelPfS_iiPfS_ii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z17calcularSobelCudaPfS_ii, .-_Z17calcularSobelCudaPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11sobelKernelPfS_ii"
.LC1:
.string "mascaraX"
.LC2:
.string "mascaraY"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sobelKernelPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mascaraX(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mascaraY(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8mascaraY
.comm _ZL8mascaraY,36,32
.local _ZL8mascaraX
.comm _ZL8mascaraX,36,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sobel.hip"
.globl _Z26__device_stub__sobelKernelPfS_ii # -- Begin function _Z26__device_stub__sobelKernelPfS_ii
.p2align 4, 0x90
.type _Z26__device_stub__sobelKernelPfS_ii,@function
_Z26__device_stub__sobelKernelPfS_ii: # @_Z26__device_stub__sobelKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sobelKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__sobelKernelPfS_ii, .Lfunc_end0-_Z26__device_stub__sobelKernelPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z17calcularSobelCudaPfS_ii
.LCPI1_0:
.long 1 # 0x1
.long 0 # 0x0
.long 4294967295 # 0xffffffff
.long 2 # 0x2
.LCPI1_1:
.long 0 # 0x0
.long 4294967294 # 0xfffffffe
.long 1 # 0x1
.long 0 # 0x0
.LCPI1_2:
.long 1 # 0x1
.long 2 # 0x2
.long 1 # 0x1
.long 0 # 0x0
.LCPI1_3:
.long 0 # 0x0
.long 0 # 0x0
.long 4294967295 # 0xffffffff
.long 4294967294 # 0xfffffffe
.text
.globl _Z17calcularSobelCudaPfS_ii
.p2align 4, 0x90
.type _Z17calcularSobelCudaPfS_ii,@function
_Z17calcularSobelCudaPfS_ii: # @_Z17calcularSobelCudaPfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $224, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movl %edx, %r12d
movq %rsi, %rbx
movq %rdi, %r13
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,0,4294967295,2]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [0,4294967294,1,0]
movaps %xmm0, 192(%rsp)
movl $-1, 208(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [1,2,1,0]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [0,0,4294967295,4294967294]
movaps %xmm0, 144(%rsp)
movl $-1, 160(%rsp)
leaq 176(%rsp), %rsi
movl $mascaraX, %edi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 128(%rsp), %rsi
movl $mascaraY, %edi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl %r12d, %eax
imull %r15d, %eax
shll $2, %eax
leal (%rax,%rax,2), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal -1(%r15), %eax
leal 62(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $6, %ecx
incl %ecx
movq %r12, %rdi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $4294967360, %rdx # imm = 0x100000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r12d, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11sobelKernelPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $224, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17calcularSobelCudaPfS_ii, .Lfunc_end1-_Z17calcularSobelCudaPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sobelKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $mascaraX, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mascaraY, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type mascaraX,@object # @mascaraX
.local mascaraX
.comm mascaraX,36,16
.type mascaraY,@object # @mascaraY
.local mascaraY
.comm mascaraY,36,16
.type _Z11sobelKernelPfS_ii,@object # @_Z11sobelKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z11sobelKernelPfS_ii
.p2align 3, 0x0
_Z11sobelKernelPfS_ii:
.quad _Z26__device_stub__sobelKernelPfS_ii
.size _Z11sobelKernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11sobelKernelPfS_ii"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "mascaraX"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mascaraY"
.size .L__unnamed_3, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sobelKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mascaraX
.addrsig_sym mascaraY
.addrsig_sym _Z11sobelKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void fillTwoFloatsArraysKernel(
int numberRows,
int numberEntries,
float* firstArray,
float firstConstant,
float* secondArray,
float secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | code for sm_80
Function : _Z25fillTwoFloatsArraysKerneliiPffS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R0, R0, c[0x0][0x160], R5 ; /* 0x0000580000007a24 */
/* 0x001fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R3, c[0x0][0x164], R0 ; /* 0x0000590003007a24 */
/* 0x002fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void fillTwoFloatsArraysKernel(
int numberRows,
int numberEntries,
float* firstArray,
float firstConstant,
float* secondArray,
float secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | .file "tmpxft_000b7e7d_00000000-6_FillTwoFloatArraysKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f
.type _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f, @function
_Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rcx, (%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25fillTwoFloatsArraysKerneliiPffS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f, .-_Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f
.globl _Z25fillTwoFloatsArraysKerneliiPffS_f
.type _Z25fillTwoFloatsArraysKerneliiPffS_f, @function
_Z25fillTwoFloatsArraysKerneliiPffS_f:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25fillTwoFloatsArraysKerneliiPffS_f, .-_Z25fillTwoFloatsArraysKerneliiPffS_f
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25fillTwoFloatsArraysKerneliiPffS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25fillTwoFloatsArraysKerneliiPffS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void fillTwoFloatsArraysKernel(
int numberRows,
int numberEntries,
float* firstArray,
float firstConstant,
float* secondArray,
float secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | #include <hip/hip_runtime.h>
__global__ void fillTwoFloatsArraysKernel(
int numberRows,
int numberEntries,
float* firstArray,
float firstConstant,
float* secondArray,
float secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void fillTwoFloatsArraysKernel(
int numberRows,
int numberEntries,
float* firstArray,
float firstConstant,
float* secondArray,
float secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25fillTwoFloatsArraysKerneliiPffS_f
.globl _Z25fillTwoFloatsArraysKerneliiPffS_f
.p2align 8
.type _Z25fillTwoFloatsArraysKerneliiPffS_f,@function
_Z25fillTwoFloatsArraysKerneliiPffS_f:
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
v_add3_u32 v0, s14, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25fillTwoFloatsArraysKerneliiPffS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25fillTwoFloatsArraysKerneliiPffS_f, .Lfunc_end0-_Z25fillTwoFloatsArraysKerneliiPffS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25fillTwoFloatsArraysKerneliiPffS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25fillTwoFloatsArraysKerneliiPffS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void fillTwoFloatsArraysKernel(
int numberRows,
int numberEntries,
float* firstArray,
float firstConstant,
float* secondArray,
float secondConstant) {
int index = blockIdx.x * numberEntries + blockIdx.y * numberRows + threadIdx.x;
firstArray[index] = firstConstant;
secondArray[index] = secondConstant;
} | .text
.file "FillTwoFloatArraysKernel.hip"
.globl _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f # -- Begin function _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.p2align 4, 0x90
.type _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f,@function
_Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f: # @_Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 4(%rsp)
movq %rcx, 64(%rsp)
movss %xmm1, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25fillTwoFloatsArraysKerneliiPffS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f, .Lfunc_end0-_Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25fillTwoFloatsArraysKerneliiPffS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25fillTwoFloatsArraysKerneliiPffS_f,@object # @_Z25fillTwoFloatsArraysKerneliiPffS_f
.section .rodata,"a",@progbits
.globl _Z25fillTwoFloatsArraysKerneliiPffS_f
.p2align 3, 0x0
_Z25fillTwoFloatsArraysKerneliiPffS_f:
.quad _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.size _Z25fillTwoFloatsArraysKerneliiPffS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25fillTwoFloatsArraysKerneliiPffS_f"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25fillTwoFloatsArraysKerneliiPffS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25fillTwoFloatsArraysKerneliiPffS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R0, R0, c[0x0][0x160], R5 ; /* 0x0000580000007a24 */
/* 0x001fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R3, c[0x0][0x164], R0 ; /* 0x0000590003007a24 */
/* 0x002fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25fillTwoFloatsArraysKerneliiPffS_f
.globl _Z25fillTwoFloatsArraysKerneliiPffS_f
.p2align 8
.type _Z25fillTwoFloatsArraysKerneliiPffS_f,@function
_Z25fillTwoFloatsArraysKerneliiPffS_f:
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
v_add3_u32 v0, s14, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25fillTwoFloatsArraysKerneliiPffS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25fillTwoFloatsArraysKerneliiPffS_f, .Lfunc_end0-_Z25fillTwoFloatsArraysKerneliiPffS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25fillTwoFloatsArraysKerneliiPffS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25fillTwoFloatsArraysKerneliiPffS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b7e7d_00000000-6_FillTwoFloatArraysKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f
.type _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f, @function
_Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rcx, (%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25fillTwoFloatsArraysKerneliiPffS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f, .-_Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f
.globl _Z25fillTwoFloatsArraysKerneliiPffS_f
.type _Z25fillTwoFloatsArraysKerneliiPffS_f, @function
_Z25fillTwoFloatsArraysKerneliiPffS_f:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25fillTwoFloatsArraysKerneliiPffS_fiiPffS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25fillTwoFloatsArraysKerneliiPffS_f, .-_Z25fillTwoFloatsArraysKerneliiPffS_f
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25fillTwoFloatsArraysKerneliiPffS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25fillTwoFloatsArraysKerneliiPffS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FillTwoFloatArraysKernel.hip"
.globl _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f # -- Begin function _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.p2align 4, 0x90
.type _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f,@function
_Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f: # @_Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 4(%rsp)
movq %rcx, 64(%rsp)
movss %xmm1, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25fillTwoFloatsArraysKerneliiPffS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f, .Lfunc_end0-_Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25fillTwoFloatsArraysKerneliiPffS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25fillTwoFloatsArraysKerneliiPffS_f,@object # @_Z25fillTwoFloatsArraysKerneliiPffS_f
.section .rodata,"a",@progbits
.globl _Z25fillTwoFloatsArraysKerneliiPffS_f
.p2align 3, 0x0
_Z25fillTwoFloatsArraysKerneliiPffS_f:
.quad _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.size _Z25fillTwoFloatsArraysKerneliiPffS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25fillTwoFloatsArraysKerneliiPffS_f"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__fillTwoFloatsArraysKerneliiPffS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25fillTwoFloatsArraysKerneliiPffS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cstdio>
#include<cassert>
__global__ void doit() {
auto nt = blockDim.x;
__shared__ int x[2048];
x[threadIdx.x]=1;
x[threadIdx.x+nt]=1;
__syncthreads();
int nl=0;
while (__syncthreads_and(nt)) {
if(threadIdx.x>=nt) continue;
++nl;
x[threadIdx.x]+=x[threadIdx.x+nt];
nt = nt/2;
}
if (threadIdx.x==0) printf("sum %d in %d for %d\n",x[0],nl,nt);
}
int main() {
doit<<<1,1024>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z4doitv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f05070 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD.SHL.U32 R5, R9.reuse, 0x4, RZ ; /* 0x0000000409057824 */
/* 0x041fe200078e00ff */
/*0090*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0001e20000004800 */
/*00a0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc40003f25270 */
/*00b0*/ IMAD R2, R2, 0x4, R5 ; /* 0x0000000402027824 */
/* 0x000fca00078e0205 */
/*00c0*/ STS [R2], R4 ; /* 0x0000000402007388 */
/* 0x0001e80000000800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ BAR.RED.AND.DEFER_BLOCKING 0x0, P0 ; /* 0x0000000000007b1d */
/* 0x000fe20000014400 */
/*00f0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0100*/ B2R.RESULT RZ, P2 ; /* 0x0000000000ff731c */
/* 0x000e640000044000 */
/*0110*/ @!P2 BRA 0x1f0 ; /* 0x000000d00000a947 */
/* 0x003fea0003800000 */
/*0120*/ ISETP.GE.U32.AND P2, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f46070 */
/*0130*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fd80003800000 */
/*0140*/ @!P2 IMAD R4, R0, 0x4, R5 ; /* 0x000000040004a824 */
/* 0x000fe200078e0205 */
/*0150*/ @!P2 LDS R2, [R9.X4] ; /* 0x000000000902a984 */
/* 0x000fe20000004800 */
/*0160*/ @!P2 SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff00a819 */
/* 0x000fe40000011600 */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe20007ffe0ff */
/*0180*/ @!P2 LDS R7, [R4] ; /* 0x000000000407a984 */
/* 0x000e220000000800 */
/*0190*/ ISETP.NE.U32.AND P3, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f65070 */
/*01a0*/ @!P2 IMAD.IADD R2, R2, 0x1, R7 ; /* 0x000000010202a824 */
/* 0x001fca00078e0207 */
/*01b0*/ @!P2 STS [R9.X4], R2 ; /* 0x000000020900a388 */
/* 0x0001ee0000004800 */
/*01c0*/ BAR.RED.AND.DEFER_BLOCKING 0x0, P3 ; /* 0x0000000000007b1d */
/* 0x000fec0001814400 */
/*01d0*/ B2R.RESULT RZ, P3 ; /* 0x0000000000ff731c */
/* 0x000e640000064000 */
/*01e0*/ @P3 BRA 0x120 ; /* 0xffffff3000003947 */
/* 0x003fea000383ffff */
/*01f0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0200*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e220000000800 */
/*0210*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*0230*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0003e20000100800 */
/*0240*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0250*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000ea20000000a00 */
/*0260*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0270*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0013ec0000100a00 */
/*0280*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x006fe20000000000 */
/*0290*/ MOV R11, 0x300 ; /* 0x00000300000b7802 */
/* 0x000fe40000000f00 */
/*02a0*/ MOV R20, 0x280 ; /* 0x0000028000147802 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*02c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*02d0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*02e0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*02f0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cstdio>
#include<cassert>
__global__ void doit() {
auto nt = blockDim.x;
__shared__ int x[2048];
x[threadIdx.x]=1;
x[threadIdx.x+nt]=1;
__syncthreads();
int nl=0;
while (__syncthreads_and(nt)) {
if(threadIdx.x>=nt) continue;
++nl;
x[threadIdx.x]+=x[threadIdx.x+nt];
nt = nt/2;
}
if (threadIdx.x==0) printf("sum %d in %d for %d\n",x[0],nl,nt);
}
int main() {
doit<<<1,1024>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_00084738_00000000-6_whileReduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4doitvv
.type _Z22__device_stub__Z4doitvv, @function
_Z22__device_stub__Z4doitvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4doitv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4doitvv, .-_Z22__device_stub__Z4doitvv
.globl _Z4doitv
.type _Z4doitv, @function
_Z4doitv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4doitvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4doitv, .-_Z4doitv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4doitvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4doitv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4doitv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cstdio>
#include<cassert>
__global__ void doit() {
auto nt = blockDim.x;
__shared__ int x[2048];
x[threadIdx.x]=1;
x[threadIdx.x+nt]=1;
__syncthreads();
int nl=0;
while (__syncthreads_and(nt)) {
if(threadIdx.x>=nt) continue;
++nl;
x[threadIdx.x]+=x[threadIdx.x+nt];
nt = nt/2;
}
if (threadIdx.x==0) printf("sum %d in %d for %d\n",x[0],nl,nt);
}
int main() {
doit<<<1,1024>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include<cstdio>
#include<cassert>
__global__ void doit() {
auto nt = blockDim.x;
__shared__ int x[2048];
x[threadIdx.x]=1;
x[threadIdx.x+nt]=1;
__syncthreads();
int nl=0;
while (__syncthreads_and(nt)) {
if(threadIdx.x>=nt) continue;
++nl;
x[threadIdx.x]+=x[threadIdx.x+nt];
nt = nt/2;
}
if (threadIdx.x==0) printf("sum %d in %d for %d\n",x[0],nl,nt);
}
int main() {
doit<<<1,1024>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<cstdio>
#include<cassert>
__global__ void doit() {
auto nt = blockDim.x;
__shared__ int x[2048];
x[threadIdx.x]=1;
x[threadIdx.x+nt]=1;
__syncthreads();
int nl=0;
while (__syncthreads_and(nt)) {
if(threadIdx.x>=nt) continue;
++nl;
x[threadIdx.x]+=x[threadIdx.x+nt];
nt = nt/2;
}
if (threadIdx.x==0) printf("sum %d in %d for %d\n",x[0],nl,nt);
}
int main() {
doit<<<1,1024>>>();
hipDeviceSynchronize();
} | .text
.file "whileReduce.hip"
.globl _Z19__device_stub__doitv # -- Begin function _Z19__device_stub__doitv
.p2align 4, 0x90
.type _Z19__device_stub__doitv,@function
_Z19__device_stub__doitv: # @_Z19__device_stub__doitv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4doitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__doitv, .Lfunc_end0-_Z19__device_stub__doitv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4doitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4doitv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4doitv,@object # @_Z4doitv
.section .rodata,"a",@progbits
.globl _Z4doitv
.p2align 3, 0x0
_Z4doitv:
.quad _Z19__device_stub__doitv
.size _Z4doitv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4doitv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__doitv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4doitv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00084738_00000000-6_whileReduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4doitvv
.type _Z22__device_stub__Z4doitvv, @function
_Z22__device_stub__Z4doitvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4doitv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4doitvv, .-_Z22__device_stub__Z4doitvv
.globl _Z4doitv
.type _Z4doitv, @function
_Z4doitv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4doitvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4doitv, .-_Z4doitv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4doitvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4doitv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4doitv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "whileReduce.hip"
.globl _Z19__device_stub__doitv # -- Begin function _Z19__device_stub__doitv
.p2align 4, 0x90
.type _Z19__device_stub__doitv,@function
_Z19__device_stub__doitv: # @_Z19__device_stub__doitv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4doitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__doitv, .Lfunc_end0-_Z19__device_stub__doitv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4doitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4doitv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4doitv,@object # @_Z4doitv
.section .rodata,"a",@progbits
.globl _Z4doitv
.p2align 3, 0x0
_Z4doitv:
.quad _Z19__device_stub__doitv
.size _Z4doitv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4doitv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__doitv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4doitv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | int launch_bf_sig_insert(unsigned char *d_sig_cache, size_t num_sigs,
unsigned char *d_bloom_filter)
{
/* TODO: Call kernel that inserts signatures into bloom filter */
return -1;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | int launch_bf_sig_insert(unsigned char *d_sig_cache, size_t num_sigs,
unsigned char *d_bloom_filter)
{
/* TODO: Call kernel that inserts signatures into bloom filter */
return -1;
} | .file "tmpxft_000ce08b_00000000-6_cuda_avscan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20launch_bf_sig_insertPhmS_
.type _Z20launch_bf_sig_insertPhmS_, @function
_Z20launch_bf_sig_insertPhmS_:
.LFB2027:
.cfi_startproc
endbr64
movl $-1, %eax
ret
.cfi_endproc
.LFE2027:
.size _Z20launch_bf_sig_insertPhmS_, .-_Z20launch_bf_sig_insertPhmS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | int launch_bf_sig_insert(unsigned char *d_sig_cache, size_t num_sigs,
unsigned char *d_bloom_filter)
{
/* TODO: Call kernel that inserts signatures into bloom filter */
return -1;
} | #include <hip/hip_runtime.h>
int launch_bf_sig_insert(unsigned char *d_sig_cache, size_t num_sigs,
unsigned char *d_bloom_filter)
{
/* TODO: Call kernel that inserts signatures into bloom filter */
return -1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
int launch_bf_sig_insert(unsigned char *d_sig_cache, size_t num_sigs,
unsigned char *d_bloom_filter)
{
/* TODO: Call kernel that inserts signatures into bloom filter */
return -1;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
int launch_bf_sig_insert(unsigned char *d_sig_cache, size_t num_sigs,
unsigned char *d_bloom_filter)
{
/* TODO: Call kernel that inserts signatures into bloom filter */
return -1;
} | .text
.file "cuda_avscan.hip"
.globl _Z20launch_bf_sig_insertPhmS_ # -- Begin function _Z20launch_bf_sig_insertPhmS_
.p2align 4, 0x90
.type _Z20launch_bf_sig_insertPhmS_,@function
_Z20launch_bf_sig_insertPhmS_: # @_Z20launch_bf_sig_insertPhmS_
.cfi_startproc
# %bb.0:
movl $-1, %eax
retq
.Lfunc_end0:
.size _Z20launch_bf_sig_insertPhmS_, .Lfunc_end0-_Z20launch_bf_sig_insertPhmS_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce08b_00000000-6_cuda_avscan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20launch_bf_sig_insertPhmS_
.type _Z20launch_bf_sig_insertPhmS_, @function
_Z20launch_bf_sig_insertPhmS_:
.LFB2027:
.cfi_startproc
endbr64
movl $-1, %eax
ret
.cfi_endproc
.LFE2027:
.size _Z20launch_bf_sig_insertPhmS_, .-_Z20launch_bf_sig_insertPhmS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_avscan.hip"
.globl _Z20launch_bf_sig_insertPhmS_ # -- Begin function _Z20launch_bf_sig_insertPhmS_
.p2align 4, 0x90
.type _Z20launch_bf_sig_insertPhmS_,@function
_Z20launch_bf_sig_insertPhmS_: # @_Z20launch_bf_sig_insertPhmS_
.cfi_startproc
# %bb.0:
movl $-1, %eax
retq
.Lfunc_end0:
.size _Z20launch_bf_sig_insertPhmS_, .Lfunc_end0-_Z20launch_bf_sig_insertPhmS_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
if (l[i] > i) {
goto LABEL1;
} else {
goto LABEL2;
}
LABEL1:
result[i] = exp(l[i]);
goto END;
LABEL2:
result[i] = l[i] + r[i];
goto END;
END:
return;
} | code for sm_80
Function : _Z6vecAddPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fcc00078e0003 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ I2F.U32 R0, R8 ; /* 0x0000000800007306 */
/* 0x000ea40000201000 */
/*0070*/ FSETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fda0003f04000 */
/*0080*/ @!P0 LEA R4, P1, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008048a11 */
/* 0x000fc800078210ff */
/*0090*/ @!P0 LEA.HI.X R5, R8, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0008058a11 */
/* 0x000fca00008f14ff */
/*00a0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ @P0 MOV R0, 0x3bbb989d ; /* 0x3bbb989d00000802 */
/* 0x000fe40000000f00 */
/*00c0*/ @P0 MOV R7, 0x437c0000 ; /* 0x437c000000070802 */
/* 0x000fe40000000f00 */
/*00d0*/ LEA R2, P1, R8, c[0x0][0x170], 0x2 ; /* 0x00005c0008027a11 */
/* 0x000fe200078210ff */
/*00e0*/ @P0 FFMA.SAT R0, R3, R0, 0.5 ; /* 0x3f00000003000423 */
/* 0x000fc80000002000 */
/*00f0*/ @P0 FFMA.RM R0, R0, R7, 12582913 ; /* 0x4b40000100000423 */
/* 0x000fc80000004007 */
/*0100*/ @P0 FADD R6, R0.reuse, -12583039 ; /* 0xcb40007f00060421 */
/* 0x040fe20000000000 */
/*0110*/ @P0 SHF.L.U32 R0, R0, 0x17, RZ ; /* 0x0000001700000819 */
/* 0x000fc600000006ff */
/*0120*/ @P0 FFMA R6, R3, 1.4426950216293334961, -R6 ; /* 0x3fb8aa3b03060823 */
/* 0x000fc80000000806 */
/*0130*/ @P0 FFMA R6, R3, 1.925963033500011079e-08, R6 ; /* 0x32a5706003060823 */
/* 0x000fc80000000006 */
/*0140*/ @P0 MUFU.EX2 R7, R6 ; /* 0x0000000600070308 */
/* 0x000e220000000800 */
/*0150*/ @!P0 FADD R5, R3, R4 ; /* 0x0000000403058221 */
/* 0x004fe20000000000 */
/*0160*/ LEA.HI.X R3, R8, c[0x0][0x174], RZ, 0x2, P1 ; /* 0x00005d0008037a11 */
/* 0x000fe200008f14ff */
/*0170*/ @P0 FMUL R5, R0, R7 ; /* 0x0000000700050220 */
/* 0x001fca0000400000 */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
if (l[i] > i) {
goto LABEL1;
} else {
goto LABEL2;
}
LABEL1:
result[i] = exp(l[i]);
goto END;
LABEL2:
result[i] = l[i] + r[i];
goto END;
END:
return;
} | .file "tmpxft_00135bb4_00000000-6_loop3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.type _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, @function
_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, .-_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.globl _Z6vecAddPfS_S_m
.type _Z6vecAddPfS_S_m, @function
_Z6vecAddPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_m, .-_Z6vecAddPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
if (l[i] > i) {
goto LABEL1;
} else {
goto LABEL2;
}
LABEL1:
result[i] = exp(l[i]);
goto END;
LABEL2:
result[i] = l[i] + r[i];
goto END;
END:
return;
} | #include <hip/hip_runtime.h>
__global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
if (l[i] > i) {
goto LABEL1;
} else {
goto LABEL2;
}
LABEL1:
result[i] = exp(l[i]);
goto END;
LABEL2:
result[i] = l[i] + r[i];
goto END;
END:
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
if (l[i] > i) {
goto LABEL1;
} else {
goto LABEL2;
}
LABEL1:
result[i] = exp(l[i]);
goto END;
LABEL2:
result[i] = l[i] + r[i];
goto END;
END:
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_m
.globl _Z6vecAddPfS_S_m
.p2align 8
.type _Z6vecAddPfS_S_m,@function
_Z6vecAddPfS_S_m:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_cvt_f32_u32_e32 v2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v2, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v1, v2
.LBB0_2:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_4
v_mul_f32_e32 v2, 0x3fb8aa3b, v1
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rndne_f32_e32 v3, v2
v_fma_f32 v4, v1, 0x3fb8aa3b, -v2
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v1, 0x32a5705f, v4
v_cvt_i32_f32_e32 v3, v3
v_add_f32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_ldexp_f32 v2, v2, v3
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_m, .Lfunc_end0-_Z6vecAddPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
if (l[i] > i) {
goto LABEL1;
} else {
goto LABEL2;
}
LABEL1:
result[i] = exp(l[i]);
goto END;
LABEL2:
result[i] = l[i] + r[i];
goto END;
END:
return;
} | .text
.file "loop3.hip"
.globl _Z21__device_stub__vecAddPfS_S_m # -- Begin function _Z21__device_stub__vecAddPfS_S_m
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_m,@function
_Z21__device_stub__vecAddPfS_S_m: # @_Z21__device_stub__vecAddPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_m, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_m,@object # @_Z6vecAddPfS_S_m
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_m
.p2align 3, 0x0
_Z6vecAddPfS_S_m:
.quad _Z21__device_stub__vecAddPfS_S_m
.size _Z6vecAddPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_m"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fcc00078e0003 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ I2F.U32 R0, R8 ; /* 0x0000000800007306 */
/* 0x000ea40000201000 */
/*0070*/ FSETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fda0003f04000 */
/*0080*/ @!P0 LEA R4, P1, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008048a11 */
/* 0x000fc800078210ff */
/*0090*/ @!P0 LEA.HI.X R5, R8, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0008058a11 */
/* 0x000fca00008f14ff */
/*00a0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ @P0 MOV R0, 0x3bbb989d ; /* 0x3bbb989d00000802 */
/* 0x000fe40000000f00 */
/*00c0*/ @P0 MOV R7, 0x437c0000 ; /* 0x437c000000070802 */
/* 0x000fe40000000f00 */
/*00d0*/ LEA R2, P1, R8, c[0x0][0x170], 0x2 ; /* 0x00005c0008027a11 */
/* 0x000fe200078210ff */
/*00e0*/ @P0 FFMA.SAT R0, R3, R0, 0.5 ; /* 0x3f00000003000423 */
/* 0x000fc80000002000 */
/*00f0*/ @P0 FFMA.RM R0, R0, R7, 12582913 ; /* 0x4b40000100000423 */
/* 0x000fc80000004007 */
/*0100*/ @P0 FADD R6, R0.reuse, -12583039 ; /* 0xcb40007f00060421 */
/* 0x040fe20000000000 */
/*0110*/ @P0 SHF.L.U32 R0, R0, 0x17, RZ ; /* 0x0000001700000819 */
/* 0x000fc600000006ff */
/*0120*/ @P0 FFMA R6, R3, 1.4426950216293334961, -R6 ; /* 0x3fb8aa3b03060823 */
/* 0x000fc80000000806 */
/*0130*/ @P0 FFMA R6, R3, 1.925963033500011079e-08, R6 ; /* 0x32a5706003060823 */
/* 0x000fc80000000006 */
/*0140*/ @P0 MUFU.EX2 R7, R6 ; /* 0x0000000600070308 */
/* 0x000e220000000800 */
/*0150*/ @!P0 FADD R5, R3, R4 ; /* 0x0000000403058221 */
/* 0x004fe20000000000 */
/*0160*/ LEA.HI.X R3, R8, c[0x0][0x174], RZ, 0x2, P1 ; /* 0x00005d0008037a11 */
/* 0x000fe200008f14ff */
/*0170*/ @P0 FMUL R5, R0, R7 ; /* 0x0000000700050220 */
/* 0x001fca0000400000 */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_m
.globl _Z6vecAddPfS_S_m
.p2align 8
.type _Z6vecAddPfS_S_m,@function
_Z6vecAddPfS_S_m:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_cvt_f32_u32_e32 v2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v1, v2
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v2, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v1, v2
.LBB0_2:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_4
v_mul_f32_e32 v2, 0x3fb8aa3b, v1
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rndne_f32_e32 v3, v2
v_fma_f32 v4, v1, 0x3fb8aa3b, -v2
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v1, 0x32a5705f, v4
v_cvt_i32_f32_e32 v3, v3
v_add_f32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_ldexp_f32 v2, v2, v3
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_m, .Lfunc_end0-_Z6vecAddPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00135bb4_00000000-6_loop3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.type _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, @function
_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, .-_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.globl _Z6vecAddPfS_S_m
.type _Z6vecAddPfS_S_m, @function
_Z6vecAddPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_m, .-_Z6vecAddPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "loop3.hip"
.globl _Z21__device_stub__vecAddPfS_S_m # -- Begin function _Z21__device_stub__vecAddPfS_S_m
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_m,@function
_Z21__device_stub__vecAddPfS_S_m: # @_Z21__device_stub__vecAddPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_m, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_m,@object # @_Z6vecAddPfS_S_m
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_m
.p2align 3, 0x0
_Z6vecAddPfS_S_m:
.quad _Z21__device_stub__vecAddPfS_S_m
.size _Z6vecAddPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_m"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
} | code for sm_80
Function : _Z4gamePiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R2, R7, R5, R4 ; /* 0x0000000507027224 */
/* 0x000fca00078e0204 */
/*0110*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*0130*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0003 */
/*01a0*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*01b0*/ @!P1 LOP3.LUT R8, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff089a12 */
/* 0x000fca00078e33ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R8 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a08 */
/*01d0*/ IMAD R14, R3, c[0x0][0x16c], R0 ; /* 0x00005b00030e7a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x16c], PT ; /* 0x00005b000e007a0c */
/* 0x000fc80003f06270 */
/*01f0*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x170], P0 ; /* 0x00005c0008007a0c */
/* 0x000fda0000706670 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0220*/ ISETP.GE.AND P2, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f46270 */
/*0230*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0240*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0250*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f06270 */
/*0280*/ IMAD.WIDE R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e020f */
/*0290*/ ISETP.GE.AND P3, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf66270 */
/*02a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*02b0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*02d0*/ @P2 IADD3 R4, R0, -c[0x0][0x16c], RZ ; /* 0x80005b0000042a10 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fc60003f26270 */
/*02f0*/ @P2 IMAD.WIDE R4, R4, R15, c[0x0][0x160] ; /* 0x0000580004042625 */
/* 0x000fe200078e020f */
/*0300*/ ULDC UR5, c[0x0][0x16c] ; /* 0x00005b0000057ab9 */
/* 0x000fc60000000800 */
/*0310*/ @!P3 IMAD.WIDE R6, R7, 0x4, R2 ; /* 0x000000040706b825 */
/* 0x000fe200078e0202 */
/*0320*/ @P2 LDG.E R12, [R4.64] ; /* 0x00000006040c2981 */
/* 0x0000a2000c1e1900 */
/*0330*/ ISETP.GE.OR P2, PT, R8.reuse, UR4, P1 ; /* 0x0000000408007c0c */
/* 0x040fe20008f46670 */
/*0340*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe2000f8e333f */
/*0350*/ ISETP.LT.OR P4, PT, R8.reuse, 0x1, !P0 ; /* 0x000000010800780c */
/* 0x040fe20004781670 */
/*0360*/ @!P3 LDG.E R10, [R6.64] ; /* 0x00000006060ab981 */
/* 0x0002e2000c1e1900 */
/*0370*/ ISETP.GE.OR P3, PT, R8, UR4, !P0 ; /* 0x0000000408007c0c */
/* 0x000fe2000c766670 */
/*0380*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x000fe200078e020b */
/*0390*/ ISETP.LT.OR P5, PT, R8, 0x1, P1 ; /* 0x000000010800780c */
/* 0x000fe40000fa1670 */
/*03a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*03b0*/ IADD3 R0, R0, UR5, RZ ; /* 0x0000000500007c10 */
/* 0x000fe2000fffe0ff */
/*03c0*/ IMAD.WIDE R4, R11, R15, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x001fc800078e020f */
/*03d0*/ @P0 LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0602090981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*03f0*/ @!P1 LDG.E R8, [R2.64+0x4] ; /* 0x0000040602089981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0410*/ IMAD.WIDE R6, R0, R15, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x002fe200078e020f */
/*0420*/ @!P2 LDG.E R13, [R4.64+0x8] ; /* 0x00000806040da981 */
/* 0x000ee6000c1e1900 */
/*0430*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0440*/ @!P3 LDG.E R11, [R4.64] ; /* 0x00000006040bb981 */
/* 0x000f28000c1e1900 */
/*0450*/ @!P4 LDG.E R16, [R6.64] ; /* 0x000000060610c981 */
/* 0x000f28000c1e1900 */
/*0460*/ @!P5 LDG.E R14, [R6.64+0x8] ; /* 0x00000806060ed981 */
/* 0x000f68000c1e1900 */
/*0470*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000f62000c1e1900 */
/*0480*/ IADD3 R8, R12, R8, R9 ; /* 0x000000080c087210 */
/* 0x004fc80007ffe009 */
/*0490*/ IADD3 R8, R13, R8, R10 ; /* 0x000000080d087210 */
/* 0x008fc80007ffe00a */
/*04a0*/ IADD3 R11, R16, R8, R11 ; /* 0x00000008100b7210 */
/* 0x010fca0007ffe00b */
/*04b0*/ IMAD.IADD R11, R11, 0x1, R14 ; /* 0x000000010b0b7824 */
/* 0x020fca00078e020e */
/*04c0*/ ISETP.GE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fc80003f06270 */
/*04d0*/ ISETP.EQ.AND P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fc80004702270 */
/*04e0*/ ISETP.GT.OR P0, PT, R11, 0x3, P0 ; /* 0x000000030b00780c */
/* 0x000fda0000704670 */
/*04f0*/ @P0 BRA 0x560 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.NE.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fc80003f05270 */
/*0510*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0520*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0540*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
} | .file "tmpxft_0012f654_00000000-6_game.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4gamePiiiiPiiii
.type _Z26__device_stub__Z4gamePiiiiPiiii, @function
_Z26__device_stub__Z4gamePiiiiPiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4gamePiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4gamePiiiiPiiii, .-_Z26__device_stub__Z4gamePiiiiPiiii
.globl _Z4gamePiiii
.type _Z4gamePiiii, @function
_Z4gamePiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4gamePiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4gamePiiii, .-_Z4gamePiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4gamePiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gamePiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gamePiiii
.globl _Z4gamePiiii
.p2align 8
.type _Z4gamePiiii,@function
_Z4gamePiiii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0xc
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s5, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s6, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s3
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s6
v_mul_lo_u32 v0, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s6
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v1
v_cmp_le_u32_e32 vcc_lo, s6, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v5, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v5, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v5
v_sub_nc_u32_e32 v4, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_21
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_lt_i32_e64 s0, 0, v4
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v6, v[0:1], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_3
global_load_b32 v7, v[0:1], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s1, s4, -1
v_mov_b32_e32 v8, 0
v_cmp_le_i32_e32 vcc_lo, s1, v4
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s1, v4
s_cbranch_execz .LBB0_5
global_load_b32 v8, v[0:1], off offset:4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_i32_e64 s1, 0, v5
v_mov_b32_e32 v9, 0
v_subrev_nc_u32_e32 v3, s4, v2
s_delay_alu instid0(VALU_DEP_3)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[9:10], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s2, s6, v9
v_add_co_ci_u32_e64 v10, s2, s7, v10, s2
global_load_b32 v9, v[9:10], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s5, -1
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
v_cmp_gt_i32_e64 s2, s2, v5
v_add_nc_u32_e32 v4, s4, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[11:12], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v11, v[11:12], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
s_xor_b32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s3
s_xor_b32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[4:5]
v_add_co_u32 v12, s3, s6, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
global_load_b32 v10, v[12:13], off offset:4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v5, 0
s_and_b32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, s2, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
global_load_b32 v5, v[4:5], off offset:-4
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_15
v_xad_u32 v12, s4, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v12, v[12:13], off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_xor_b32 s0, s1, -1
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s0, -1
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_17
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v4, v[3:4], off offset:4
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v8, v7
v_cmp_eq_u32_e32 vcc_lo, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v9, v11
v_add3_u32 v3, v3, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v12, v4
v_cmp_gt_i32_e64 s0, 2, v3
v_cmp_lt_i32_e64 s1, 3, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s1, -1
s_and_saveexec_b32 s2, s0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cmp_eq_u32_e64 s0, 3, v3
v_mov_b32_e32 v2, 1
s_and_not1_b32 s1, s1, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s1, s1, s0
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_21
global_store_b32 v[0:1], v2, off
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gamePiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gamePiiii, .Lfunc_end0-_Z4gamePiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gamePiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gamePiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
} | .text
.file "game.hip"
.globl _Z19__device_stub__gamePiiii # -- Begin function _Z19__device_stub__gamePiiii
.p2align 4, 0x90
.type _Z19__device_stub__gamePiiii,@function
_Z19__device_stub__gamePiiii: # @_Z19__device_stub__gamePiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4gamePiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__gamePiiii, .Lfunc_end0-_Z19__device_stub__gamePiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gamePiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4gamePiiii,@object # @_Z4gamePiiii
.section .rodata,"a",@progbits
.globl _Z4gamePiiii
.p2align 3, 0x0
_Z4gamePiiii:
.quad _Z19__device_stub__gamePiiii
.size _Z4gamePiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4gamePiiii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gamePiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gamePiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4gamePiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R2, R7, R5, R4 ; /* 0x0000000507027224 */
/* 0x000fca00078e0204 */
/*0110*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*0130*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0003 */
/*01a0*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*01b0*/ @!P1 LOP3.LUT R8, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff089a12 */
/* 0x000fca00078e33ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R8 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a08 */
/*01d0*/ IMAD R14, R3, c[0x0][0x16c], R0 ; /* 0x00005b00030e7a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x16c], PT ; /* 0x00005b000e007a0c */
/* 0x000fc80003f06270 */
/*01f0*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x170], P0 ; /* 0x00005c0008007a0c */
/* 0x000fda0000706670 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0220*/ ISETP.GE.AND P2, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f46270 */
/*0230*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0240*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0250*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f06270 */
/*0280*/ IMAD.WIDE R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e020f */
/*0290*/ ISETP.GE.AND P3, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf66270 */
/*02a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*02b0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*02d0*/ @P2 IADD3 R4, R0, -c[0x0][0x16c], RZ ; /* 0x80005b0000042a10 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fc60003f26270 */
/*02f0*/ @P2 IMAD.WIDE R4, R4, R15, c[0x0][0x160] ; /* 0x0000580004042625 */
/* 0x000fe200078e020f */
/*0300*/ ULDC UR5, c[0x0][0x16c] ; /* 0x00005b0000057ab9 */
/* 0x000fc60000000800 */
/*0310*/ @!P3 IMAD.WIDE R6, R7, 0x4, R2 ; /* 0x000000040706b825 */
/* 0x000fe200078e0202 */
/*0320*/ @P2 LDG.E R12, [R4.64] ; /* 0x00000006040c2981 */
/* 0x0000a2000c1e1900 */
/*0330*/ ISETP.GE.OR P2, PT, R8.reuse, UR4, P1 ; /* 0x0000000408007c0c */
/* 0x040fe20008f46670 */
/*0340*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe2000f8e333f */
/*0350*/ ISETP.LT.OR P4, PT, R8.reuse, 0x1, !P0 ; /* 0x000000010800780c */
/* 0x040fe20004781670 */
/*0360*/ @!P3 LDG.E R10, [R6.64] ; /* 0x00000006060ab981 */
/* 0x0002e2000c1e1900 */
/*0370*/ ISETP.GE.OR P3, PT, R8, UR4, !P0 ; /* 0x0000000408007c0c */
/* 0x000fe2000c766670 */
/*0380*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x000fe200078e020b */
/*0390*/ ISETP.LT.OR P5, PT, R8, 0x1, P1 ; /* 0x000000010800780c */
/* 0x000fe40000fa1670 */
/*03a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*03b0*/ IADD3 R0, R0, UR5, RZ ; /* 0x0000000500007c10 */
/* 0x000fe2000fffe0ff */
/*03c0*/ IMAD.WIDE R4, R11, R15, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x001fc800078e020f */
/*03d0*/ @P0 LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0602090981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*03f0*/ @!P1 LDG.E R8, [R2.64+0x4] ; /* 0x0000040602089981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0410*/ IMAD.WIDE R6, R0, R15, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x002fe200078e020f */
/*0420*/ @!P2 LDG.E R13, [R4.64+0x8] ; /* 0x00000806040da981 */
/* 0x000ee6000c1e1900 */
/*0430*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0440*/ @!P3 LDG.E R11, [R4.64] ; /* 0x00000006040bb981 */
/* 0x000f28000c1e1900 */
/*0450*/ @!P4 LDG.E R16, [R6.64] ; /* 0x000000060610c981 */
/* 0x000f28000c1e1900 */
/*0460*/ @!P5 LDG.E R14, [R6.64+0x8] ; /* 0x00000806060ed981 */
/* 0x000f68000c1e1900 */
/*0470*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000f62000c1e1900 */
/*0480*/ IADD3 R8, R12, R8, R9 ; /* 0x000000080c087210 */
/* 0x004fc80007ffe009 */
/*0490*/ IADD3 R8, R13, R8, R10 ; /* 0x000000080d087210 */
/* 0x008fc80007ffe00a */
/*04a0*/ IADD3 R11, R16, R8, R11 ; /* 0x00000008100b7210 */
/* 0x010fca0007ffe00b */
/*04b0*/ IMAD.IADD R11, R11, 0x1, R14 ; /* 0x000000010b0b7824 */
/* 0x020fca00078e020e */
/*04c0*/ ISETP.GE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fc80003f06270 */
/*04d0*/ ISETP.EQ.AND P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fc80004702270 */
/*04e0*/ ISETP.GT.OR P0, PT, R11, 0x3, P0 ; /* 0x000000030b00780c */
/* 0x000fda0000704670 */
/*04f0*/ @P0 BRA 0x560 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.NE.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fc80003f05270 */
/*0510*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0520*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0540*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gamePiiii
.globl _Z4gamePiiii
.p2align 8
.type _Z4gamePiiii,@function
_Z4gamePiiii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0xc
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s5, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s6, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s3
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s6
v_mul_lo_u32 v0, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s6
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v1
v_cmp_le_u32_e32 vcc_lo, s6, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v5, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v5, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v5
v_sub_nc_u32_e32 v4, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_21
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_lt_i32_e64 s0, 0, v4
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v6, v[0:1], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_3
global_load_b32 v7, v[0:1], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s1, s4, -1
v_mov_b32_e32 v8, 0
v_cmp_le_i32_e32 vcc_lo, s1, v4
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s1, v4
s_cbranch_execz .LBB0_5
global_load_b32 v8, v[0:1], off offset:4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_i32_e64 s1, 0, v5
v_mov_b32_e32 v9, 0
v_subrev_nc_u32_e32 v3, s4, v2
s_delay_alu instid0(VALU_DEP_3)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[9:10], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s2, s6, v9
v_add_co_ci_u32_e64 v10, s2, s7, v10, s2
global_load_b32 v9, v[9:10], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s5, -1
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
v_cmp_gt_i32_e64 s2, s2, v5
v_add_nc_u32_e32 v4, s4, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[11:12], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v11, v[11:12], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
s_xor_b32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s3
s_xor_b32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[4:5]
v_add_co_u32 v12, s3, s6, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
global_load_b32 v10, v[12:13], off offset:4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v5, 0
s_and_b32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, s2, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
global_load_b32 v5, v[4:5], off offset:-4
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_15
v_xad_u32 v12, s4, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v12, v[12:13], off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_xor_b32 s0, s1, -1
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s0, -1
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_17
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v4, v[3:4], off offset:4
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v8, v7
v_cmp_eq_u32_e32 vcc_lo, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v9, v11
v_add3_u32 v3, v3, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v12, v4
v_cmp_gt_i32_e64 s0, 2, v3
v_cmp_lt_i32_e64 s1, 3, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s1, -1
s_and_saveexec_b32 s2, s0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cmp_eq_u32_e64 s0, 3, v3
v_mov_b32_e32 v2, 1
s_and_not1_b32 s1, s1, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s1, s1, s0
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_21
global_store_b32 v[0:1], v2, off
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gamePiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gamePiiii, .Lfunc_end0-_Z4gamePiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gamePiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gamePiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012f654_00000000-6_game.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4gamePiiiiPiiii
.type _Z26__device_stub__Z4gamePiiiiPiiii, @function
_Z26__device_stub__Z4gamePiiiiPiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4gamePiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4gamePiiiiPiiii, .-_Z26__device_stub__Z4gamePiiiiPiiii
.globl _Z4gamePiiii
.type _Z4gamePiiii, @function
_Z4gamePiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4gamePiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4gamePiiii, .-_Z4gamePiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4gamePiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gamePiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "game.hip"
.globl _Z19__device_stub__gamePiiii # -- Begin function _Z19__device_stub__gamePiiii
.p2align 4, 0x90
.type _Z19__device_stub__gamePiiii,@function
_Z19__device_stub__gamePiiii: # @_Z19__device_stub__gamePiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4gamePiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__gamePiiii, .Lfunc_end0-_Z19__device_stub__gamePiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gamePiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4gamePiiii,@object # @_Z4gamePiiii
.section .rodata,"a",@progbits
.globl _Z4gamePiiii
.p2align 3, 0x0
_Z4gamePiiii:
.quad _Z19__device_stub__gamePiiii
.size _Z4gamePiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4gamePiiii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gamePiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gamePiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
extern "C"
{
__global__ void NewModuleWithSourceDepsKernel(float* input, float* output, float incrementSize, int itemCount)
{
int threadId = blockIdx.y*blockDim.x*gridDim.x
+ blockIdx.x*blockDim.x
+ threadIdx.x;
}
} | code for sm_80
Function : NewModuleWithSourceDepsKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
extern "C"
{
__global__ void NewModuleWithSourceDepsKernel(float* input, float* output, float incrementSize, int itemCount)
{
int threadId = blockIdx.y*blockDim.x*gridDim.x
+ blockIdx.x*blockDim.x
+ threadIdx.x;
}
} | .file "tmpxft_000132c3_00000000-6_NewModuleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi
.type _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi, @function
_Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq NewModuleWithSourceDepsKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi, .-_Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi
.globl NewModuleWithSourceDepsKernel
.type NewModuleWithSourceDepsKernel, @function
NewModuleWithSourceDepsKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size NewModuleWithSourceDepsKernel, .-NewModuleWithSourceDepsKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "NewModuleWithSourceDepsKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq NewModuleWithSourceDepsKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
extern "C"
{
__global__ void NewModuleWithSourceDepsKernel(float* input, float* output, float incrementSize, int itemCount)
{
int threadId = blockIdx.y*blockDim.x*gridDim.x
+ blockIdx.x*blockDim.x
+ threadIdx.x;
}
} | #include "hip/hip_runtime.h"
extern "C"
{
__global__ void NewModuleWithSourceDepsKernel(float* input, float* output, float incrementSize, int itemCount)
{
int threadId = blockIdx.y*blockDim.x*gridDim.x
+ blockIdx.x*blockDim.x
+ threadIdx.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
extern "C"
{
__global__ void NewModuleWithSourceDepsKernel(float* input, float* output, float incrementSize, int itemCount)
{
int threadId = blockIdx.y*blockDim.x*gridDim.x
+ blockIdx.x*blockDim.x
+ threadIdx.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected NewModuleWithSourceDepsKernel
.globl NewModuleWithSourceDepsKernel
.p2align 8
.type NewModuleWithSourceDepsKernel,@function
NewModuleWithSourceDepsKernel:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel NewModuleWithSourceDepsKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size NewModuleWithSourceDepsKernel, .Lfunc_end0-NewModuleWithSourceDepsKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: NewModuleWithSourceDepsKernel
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: NewModuleWithSourceDepsKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
extern "C"
{
__global__ void NewModuleWithSourceDepsKernel(float* input, float* output, float incrementSize, int itemCount)
{
int threadId = blockIdx.y*blockDim.x*gridDim.x
+ blockIdx.x*blockDim.x
+ threadIdx.x;
}
} | .text
.file "NewModuleKernel.hip"
.globl __device_stub__NewModuleWithSourceDepsKernel # -- Begin function __device_stub__NewModuleWithSourceDepsKernel
.p2align 4, 0x90
.type __device_stub__NewModuleWithSourceDepsKernel,@function
__device_stub__NewModuleWithSourceDepsKernel: # @__device_stub__NewModuleWithSourceDepsKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $NewModuleWithSourceDepsKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__NewModuleWithSourceDepsKernel, .Lfunc_end0-__device_stub__NewModuleWithSourceDepsKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $NewModuleWithSourceDepsKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type NewModuleWithSourceDepsKernel,@object # @NewModuleWithSourceDepsKernel
.section .rodata,"a",@progbits
.globl NewModuleWithSourceDepsKernel
.p2align 3, 0x0
NewModuleWithSourceDepsKernel:
.quad __device_stub__NewModuleWithSourceDepsKernel
.size NewModuleWithSourceDepsKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "NewModuleWithSourceDepsKernel"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__NewModuleWithSourceDepsKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym NewModuleWithSourceDepsKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : NewModuleWithSourceDepsKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected NewModuleWithSourceDepsKernel
.globl NewModuleWithSourceDepsKernel
.p2align 8
.type NewModuleWithSourceDepsKernel,@function
NewModuleWithSourceDepsKernel:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel NewModuleWithSourceDepsKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size NewModuleWithSourceDepsKernel, .Lfunc_end0-NewModuleWithSourceDepsKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: NewModuleWithSourceDepsKernel
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: NewModuleWithSourceDepsKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000132c3_00000000-6_NewModuleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi
.type _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi, @function
_Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq NewModuleWithSourceDepsKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi, .-_Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi
.globl NewModuleWithSourceDepsKernel
.type NewModuleWithSourceDepsKernel, @function
NewModuleWithSourceDepsKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z29NewModuleWithSourceDepsKernelPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size NewModuleWithSourceDepsKernel, .-NewModuleWithSourceDepsKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "NewModuleWithSourceDepsKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq NewModuleWithSourceDepsKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NewModuleKernel.hip"
.globl __device_stub__NewModuleWithSourceDepsKernel # -- Begin function __device_stub__NewModuleWithSourceDepsKernel
.p2align 4, 0x90
.type __device_stub__NewModuleWithSourceDepsKernel,@function
__device_stub__NewModuleWithSourceDepsKernel: # @__device_stub__NewModuleWithSourceDepsKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $NewModuleWithSourceDepsKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__NewModuleWithSourceDepsKernel, .Lfunc_end0-__device_stub__NewModuleWithSourceDepsKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $NewModuleWithSourceDepsKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type NewModuleWithSourceDepsKernel,@object # @NewModuleWithSourceDepsKernel
.section .rodata,"a",@progbits
.globl NewModuleWithSourceDepsKernel
.p2align 3, 0x0
NewModuleWithSourceDepsKernel:
.quad __device_stub__NewModuleWithSourceDepsKernel
.size NewModuleWithSourceDepsKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "NewModuleWithSourceDepsKernel"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__NewModuleWithSourceDepsKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym NewModuleWithSourceDepsKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// C++ 17 Includes:
// Project Includes:
// Defines:
__global__ void sum_dynamic_kernel(const int* pIn, int* pOut, size_t numInts)
{
extern __shared__ int ps[]; // Automatically points to our shared memory array
// Load shared memory:
ps[threadIdx.x] = pIn[threadIdx.x];
if (threadIdx.x + blockDim.x < numInts)
ps[threadIdx.x + blockDim.x] = pIn[threadIdx.x + blockDim.x];
if (0 == threadIdx.x && 1 == (1 & numInts))
ps[numInts - 1] = pIn[numInts - 1];
size_t prevNumThreads{numInts};
for (size_t numThreads{blockDim.x}; numThreads > 0; numThreads >>= 1)
{
if (threadIdx.x > numThreads)
return;
__syncthreads();
ps[threadIdx.x] += ps[threadIdx.x + numThreads];
if (1 == (prevNumThreads & 1))
ps[0] += ps[prevNumThreads - 1];
prevNumThreads = numThreads;
}
*pOut = ps[0];
} | code for sm_80
Function : _Z18sum_dynamic_kernelPKiPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*0050*/ LOP3.LUT R2, R10, 0x1, RZ, 0xc0, !PT ; /* 0x000000010a027812 */
/* 0x000fc800078ec0ff */
/*0060*/ ISETP.NE.U32.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f25070 */
/*0070*/ ISETP.NE.U32.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40003f25110 */
/*0080*/ IADD3 R5, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000057a10 */
/* 0x041fe20007ffe0ff */
/*0090*/ IMAD.WIDE.U32 R2, R0.reuse, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe200078e0009 */
/*00a0*/ ISETP.NE.OR P1, PT, R0, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40000f25670 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc60003f06070 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fce0003f06100 */
/*00e0*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff079624 */
/* 0x000fe200078e00ff */
/*00f0*/ @!P1 LEA R6, P3, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a069a11 */
/* 0x000fc800078610ff */
/*0100*/ @!P1 LEA.HI.X R7, R10, c[0x0][0x164], R7, 0x2, P3 ; /* 0x000059000a079a11 */
/* 0x000fe400018f1407 */
/*0110*/ @!P0 LEA R4, P2, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005048a11 */
/* 0x000fc600078410ff */
/*0120*/ @!P1 LDG.E R6, [R6.64+-0x4] ; /* 0xfffffc0406069981 */
/* 0x000ee2000c1e1900 */
/*0130*/ @!P0 LEA.HI.X R5, R5, c[0x0][0x164], RZ, 0x2, P2 ; /* 0x0000590005058a11 */
/* 0x000fca00010f14ff */
/*0140*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000f22000c1e1900 */
/*0150*/ IMAD.SHL.U32 R8, R0, 0x4, RZ ; /* 0x0000000400087824 */
/* 0x000fe200078e00ff */
/*0160*/ @!P1 LEA R11, R10, 0xfffffffc, 0x2 ; /* 0xfffffffc0a0b9811 */
/* 0x000fc600078e10ff */
/*0170*/ @!P0 IMAD R9, R9, c[0x0][0x0], R8 ; /* 0x0000000009098a24 */
/* 0x000fe200078e0208 */
/*0180*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0041e80000004800 */
/*0190*/ @!P0 STS [R9], R4 ; /* 0x0000000409008388 */
/* 0x0101e80000000800 */
/*01a0*/ @!P1 STS [R11], R6 ; /* 0x000000060b009388 */
/* 0x0081e20000000800 */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fda0003f05270 */
/*01c0*/ @!P0 BRA 0x370 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fc80003f06070 */
/*0210*/ ISETP.GE.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f06100 */
/*0220*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ IMAD R2, R7, 0x4, R8 ; /* 0x0000000407027824 */
/* 0x000fe200078e0208 */
/*0250*/ LOP3.LUT R4, R9, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109047812 */
/* 0x000fc800078ec0ff */
/*0260*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f05070 */
/*0270*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*0280*/ @!P0 LEA R5, R9, 0xfffffffc, 0x2 ; /* 0xfffffffc09058811 */
/* 0x000fe200078e10ff */
/*0290*/ LDS R2, [R2] ; /* 0x0000000002027984 */
/* 0x000fe20000000800 */
/*02a0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*02b0*/ SHF.R.U64 R7, R7, 0x1, R6.reuse ; /* 0x0000000107077819 */
/* 0x100fe40000001206 */
/*02c0*/ LDS R3, [R0.X4] ; /* 0x0000000000037984 */
/* 0x000e220000004800 */
/*02d0*/ SHF.R.U32.HI R6, RZ, 0x1, R6 ; /* 0x00000001ff067819 */
/* 0x000fe20000011606 */
/*02e0*/ IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103037824 */
/* 0x001fca00078e0202 */
/*02f0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x000fe80000004800 */
/*0300*/ @!P0 LDS R5, [R5] ; /* 0x0000000005058984 */
/* 0x000fe80000000800 */
/*0310*/ @!P0 LDS R4, [RZ] ; /* 0x00000000ff048984 */
/* 0x000e240000000800 */
/*0320*/ @!P0 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104048824 */
/* 0x001fca00078e0205 */
/*0330*/ @!P0 STS [RZ], R4 ; /* 0x00000004ff008388 */
/* 0x0001e20000000800 */
/*0340*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05070 */
/*0350*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f05300 */
/*0360*/ @P0 BRA 0x200 ; /* 0xfffffe9000000947 */
/* 0x001fea000383ffff */
/*0370*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*03a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// C++ 17 Includes:
// Project Includes:
// Defines:
__global__ void sum_dynamic_kernel(const int* pIn, int* pOut, size_t numInts)
{
extern __shared__ int ps[]; // Automatically points to our shared memory array
// Load shared memory:
ps[threadIdx.x] = pIn[threadIdx.x];
if (threadIdx.x + blockDim.x < numInts)
ps[threadIdx.x + blockDim.x] = pIn[threadIdx.x + blockDim.x];
if (0 == threadIdx.x && 1 == (1 & numInts))
ps[numInts - 1] = pIn[numInts - 1];
size_t prevNumThreads{numInts};
for (size_t numThreads{blockDim.x}; numThreads > 0; numThreads >>= 1)
{
if (threadIdx.x > numThreads)
return;
__syncthreads();
ps[threadIdx.x] += ps[threadIdx.x + numThreads];
if (1 == (prevNumThreads & 1))
ps[0] += ps[prevNumThreads - 1];
prevNumThreads = numThreads;
}
*pOut = ps[0];
} | .file "tmpxft_000991de_00000000-6_sum_dynamic_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim
.type _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim, @function
_Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18sum_dynamic_kernelPKiPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim, .-_Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim
.globl _Z18sum_dynamic_kernelPKiPim
.type _Z18sum_dynamic_kernelPKiPim, @function
_Z18sum_dynamic_kernelPKiPim:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18sum_dynamic_kernelPKiPim, .-_Z18sum_dynamic_kernelPKiPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18sum_dynamic_kernelPKiPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18sum_dynamic_kernelPKiPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// C++ 17 Includes:
// Project Includes:
// Defines:
__global__ void sum_dynamic_kernel(const int* pIn, int* pOut, size_t numInts)
{
extern __shared__ int ps[]; // Automatically points to our shared memory array
// Load shared memory:
ps[threadIdx.x] = pIn[threadIdx.x];
if (threadIdx.x + blockDim.x < numInts)
ps[threadIdx.x + blockDim.x] = pIn[threadIdx.x + blockDim.x];
if (0 == threadIdx.x && 1 == (1 & numInts))
ps[numInts - 1] = pIn[numInts - 1];
size_t prevNumThreads{numInts};
for (size_t numThreads{blockDim.x}; numThreads > 0; numThreads >>= 1)
{
if (threadIdx.x > numThreads)
return;
__syncthreads();
ps[threadIdx.x] += ps[threadIdx.x + numThreads];
if (1 == (prevNumThreads & 1))
ps[0] += ps[prevNumThreads - 1];
prevNumThreads = numThreads;
}
*pOut = ps[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
// C++ 17 Includes:
// Project Includes:
// Defines:
__global__ void sum_dynamic_kernel(const int* pIn, int* pOut, size_t numInts)
{
extern __shared__ int ps[]; // Automatically points to our shared memory array
// Load shared memory:
ps[threadIdx.x] = pIn[threadIdx.x];
if (threadIdx.x + blockDim.x < numInts)
ps[threadIdx.x + blockDim.x] = pIn[threadIdx.x + blockDim.x];
if (0 == threadIdx.x && 1 == (1 & numInts))
ps[numInts - 1] = pIn[numInts - 1];
size_t prevNumThreads{numInts};
for (size_t numThreads{blockDim.x}; numThreads > 0; numThreads >>= 1)
{
if (threadIdx.x > numThreads)
return;
__syncthreads();
ps[threadIdx.x] += ps[threadIdx.x + numThreads];
if (1 == (prevNumThreads & 1))
ps[0] += ps[prevNumThreads - 1];
prevNumThreads = numThreads;
}
*pOut = ps[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// C++ 17 Includes:
// Project Includes:
// Defines:
__global__ void sum_dynamic_kernel(const int* pIn, int* pOut, size_t numInts)
{
extern __shared__ int ps[]; // Automatically points to our shared memory array
// Load shared memory:
ps[threadIdx.x] = pIn[threadIdx.x];
if (threadIdx.x + blockDim.x < numInts)
ps[threadIdx.x + blockDim.x] = pIn[threadIdx.x + blockDim.x];
if (0 == threadIdx.x && 1 == (1 & numInts))
ps[numInts - 1] = pIn[numInts - 1];
size_t prevNumThreads{numInts};
for (size_t numThreads{blockDim.x}; numThreads > 0; numThreads >>= 1)
{
if (threadIdx.x > numThreads)
return;
__syncthreads();
ps[threadIdx.x] += ps[threadIdx.x + numThreads];
if (1 == (prevNumThreads & 1))
ps[0] += ps[prevNumThreads - 1];
prevNumThreads = numThreads;
}
*pOut = ps[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18sum_dynamic_kernelPKiPim
.globl _Z18sum_dynamic_kernelPKiPim
.p2align 8
.type _Z18sum_dynamic_kernelPKiPim,@function
_Z18sum_dynamic_kernelPKiPim:
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v3, v1
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v4, s[4:5]
v_add_nc_u32_e32 v4, 0, v4
s_and_b32 s7, s6, 0xffff
v_add_nc_u32_e32 v2, s7, v0
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
v_cmpx_gt_u64_e64 s[2:3], v[2:3]
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 2, v2
global_load_b32 v3, v2, s[4:5]
v_add_nc_u32_e32 v2, 0, v2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_bitcmp1_b32 s2, 0
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s7
s_and_saveexec_b32 s7, s8
s_cbranch_execz .LBB0_4
s_add_u32 s8, s2, -1
s_addc_u32 s9, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_add_u32 s4, s4, s10
s_addc_u32 s5, s5, s11
s_load_b32 s3, s[4:5], 0x0
s_lshl_b32 s4, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s4, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
ds_store_b32 v2, v3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
v_cmp_eq_u16_e64 s3, s6, 0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_14
s_and_b32 s4, 0xffff, s6
s_mov_b32 s10, 0
s_mov_b64 s[6:7], s[4:5]
s_branch .LBB0_8
.LBB0_6:
v_cmp_lt_u64_e64 s2, s[6:7], 2
s_and_not1_b32 s4, s12, exec_lo
s_lshr_b64 s[8:9], s[6:7], 1
s_and_not1_b32 s11, s11, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s12, s4, s2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s13
s_xor_b32 s2, s11, -1
s_and_b32 s4, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s4, s10
s_and_not1_b32 s4, s3, exec_lo
s_and_b32 s13, s2, exec_lo
s_mov_b64 s[2:3], s[6:7]
s_or_b32 s3, s4, s13
s_mov_b64 s[6:7], s[8:9]
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_11
.LBB0_8:
s_or_b32 s11, s11, exec_lo
s_or_b32 s12, s12, exec_lo
s_mov_b32 s13, exec_lo
v_cmpx_ge_u64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v2, s6, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s4, s2, 1
v_lshl_add_u32 v2, v2, 2, 0
s_cmp_eq_u64 s[4:5], 0
ds_load_b32 v2, v2
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v4, v2
s_cbranch_scc1 .LBB0_6
s_lshl_b32 s2, s2, 2
v_mov_b32_e32 v3, 0
s_add_i32 s2, s2, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, -4
v_mov_b32_e32 v2, s2
ds_load_b32 v2, v2
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v5, v2
ds_store_b32 v3, v2
s_branch .LBB0_6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s10
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_13
.LBB0_12:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_14:
s_mov_b32 s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execnz .LBB0_12
s_branch .LBB0_13
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18sum_dynamic_kernelPKiPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18sum_dynamic_kernelPKiPim, .Lfunc_end0-_Z18sum_dynamic_kernelPKiPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18sum_dynamic_kernelPKiPim
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18sum_dynamic_kernelPKiPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// C++ 17 Includes:
// Project Includes:
// Defines:
__global__ void sum_dynamic_kernel(const int* pIn, int* pOut, size_t numInts)
{
extern __shared__ int ps[]; // Automatically points to our shared memory array
// Load shared memory:
ps[threadIdx.x] = pIn[threadIdx.x];
if (threadIdx.x + blockDim.x < numInts)
ps[threadIdx.x + blockDim.x] = pIn[threadIdx.x + blockDim.x];
if (0 == threadIdx.x && 1 == (1 & numInts))
ps[numInts - 1] = pIn[numInts - 1];
size_t prevNumThreads{numInts};
for (size_t numThreads{blockDim.x}; numThreads > 0; numThreads >>= 1)
{
if (threadIdx.x > numThreads)
return;
__syncthreads();
ps[threadIdx.x] += ps[threadIdx.x + numThreads];
if (1 == (prevNumThreads & 1))
ps[0] += ps[prevNumThreads - 1];
prevNumThreads = numThreads;
}
*pOut = ps[0];
} | .text
.file "sum_dynamic_kernel.hip"
.globl _Z33__device_stub__sum_dynamic_kernelPKiPim # -- Begin function _Z33__device_stub__sum_dynamic_kernelPKiPim
.p2align 4, 0x90
.type _Z33__device_stub__sum_dynamic_kernelPKiPim,@function
_Z33__device_stub__sum_dynamic_kernelPKiPim: # @_Z33__device_stub__sum_dynamic_kernelPKiPim
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18sum_dynamic_kernelPKiPim, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__sum_dynamic_kernelPKiPim, .Lfunc_end0-_Z33__device_stub__sum_dynamic_kernelPKiPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18sum_dynamic_kernelPKiPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18sum_dynamic_kernelPKiPim,@object # @_Z18sum_dynamic_kernelPKiPim
.section .rodata,"a",@progbits
.globl _Z18sum_dynamic_kernelPKiPim
.p2align 3, 0x0
_Z18sum_dynamic_kernelPKiPim:
.quad _Z33__device_stub__sum_dynamic_kernelPKiPim
.size _Z18sum_dynamic_kernelPKiPim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18sum_dynamic_kernelPKiPim"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__sum_dynamic_kernelPKiPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18sum_dynamic_kernelPKiPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18sum_dynamic_kernelPKiPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*0050*/ LOP3.LUT R2, R10, 0x1, RZ, 0xc0, !PT ; /* 0x000000010a027812 */
/* 0x000fc800078ec0ff */
/*0060*/ ISETP.NE.U32.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f25070 */
/*0070*/ ISETP.NE.U32.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40003f25110 */
/*0080*/ IADD3 R5, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000057a10 */
/* 0x041fe20007ffe0ff */
/*0090*/ IMAD.WIDE.U32 R2, R0.reuse, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe200078e0009 */
/*00a0*/ ISETP.NE.OR P1, PT, R0, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40000f25670 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc60003f06070 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fce0003f06100 */
/*00e0*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff079624 */
/* 0x000fe200078e00ff */
/*00f0*/ @!P1 LEA R6, P3, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a069a11 */
/* 0x000fc800078610ff */
/*0100*/ @!P1 LEA.HI.X R7, R10, c[0x0][0x164], R7, 0x2, P3 ; /* 0x000059000a079a11 */
/* 0x000fe400018f1407 */
/*0110*/ @!P0 LEA R4, P2, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005048a11 */
/* 0x000fc600078410ff */
/*0120*/ @!P1 LDG.E R6, [R6.64+-0x4] ; /* 0xfffffc0406069981 */
/* 0x000ee2000c1e1900 */
/*0130*/ @!P0 LEA.HI.X R5, R5, c[0x0][0x164], RZ, 0x2, P2 ; /* 0x0000590005058a11 */
/* 0x000fca00010f14ff */
/*0140*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000f22000c1e1900 */
/*0150*/ IMAD.SHL.U32 R8, R0, 0x4, RZ ; /* 0x0000000400087824 */
/* 0x000fe200078e00ff */
/*0160*/ @!P1 LEA R11, R10, 0xfffffffc, 0x2 ; /* 0xfffffffc0a0b9811 */
/* 0x000fc600078e10ff */
/*0170*/ @!P0 IMAD R9, R9, c[0x0][0x0], R8 ; /* 0x0000000009098a24 */
/* 0x000fe200078e0208 */
/*0180*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0041e80000004800 */
/*0190*/ @!P0 STS [R9], R4 ; /* 0x0000000409008388 */
/* 0x0101e80000000800 */
/*01a0*/ @!P1 STS [R11], R6 ; /* 0x000000060b009388 */
/* 0x0081e20000000800 */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fda0003f05270 */
/*01c0*/ @!P0 BRA 0x370 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fc80003f06070 */
/*0210*/ ISETP.GE.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f06100 */
/*0220*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ IMAD R2, R7, 0x4, R8 ; /* 0x0000000407027824 */
/* 0x000fe200078e0208 */
/*0250*/ LOP3.LUT R4, R9, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109047812 */
/* 0x000fc800078ec0ff */
/*0260*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f05070 */
/*0270*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*0280*/ @!P0 LEA R5, R9, 0xfffffffc, 0x2 ; /* 0xfffffffc09058811 */
/* 0x000fe200078e10ff */
/*0290*/ LDS R2, [R2] ; /* 0x0000000002027984 */
/* 0x000fe20000000800 */
/*02a0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*02b0*/ SHF.R.U64 R7, R7, 0x1, R6.reuse ; /* 0x0000000107077819 */
/* 0x100fe40000001206 */
/*02c0*/ LDS R3, [R0.X4] ; /* 0x0000000000037984 */
/* 0x000e220000004800 */
/*02d0*/ SHF.R.U32.HI R6, RZ, 0x1, R6 ; /* 0x00000001ff067819 */
/* 0x000fe20000011606 */
/*02e0*/ IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103037824 */
/* 0x001fca00078e0202 */
/*02f0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x000fe80000004800 */
/*0300*/ @!P0 LDS R5, [R5] ; /* 0x0000000005058984 */
/* 0x000fe80000000800 */
/*0310*/ @!P0 LDS R4, [RZ] ; /* 0x00000000ff048984 */
/* 0x000e240000000800 */
/*0320*/ @!P0 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104048824 */
/* 0x001fca00078e0205 */
/*0330*/ @!P0 STS [RZ], R4 ; /* 0x00000004ff008388 */
/* 0x0001e20000000800 */
/*0340*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05070 */
/*0350*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f05300 */
/*0360*/ @P0 BRA 0x200 ; /* 0xfffffe9000000947 */
/* 0x001fea000383ffff */
/*0370*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*03a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18sum_dynamic_kernelPKiPim
.globl _Z18sum_dynamic_kernelPKiPim
.p2align 8
.type _Z18sum_dynamic_kernelPKiPim,@function
_Z18sum_dynamic_kernelPKiPim:
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v3, v1
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v4, s[4:5]
v_add_nc_u32_e32 v4, 0, v4
s_and_b32 s7, s6, 0xffff
v_add_nc_u32_e32 v2, s7, v0
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
v_cmpx_gt_u64_e64 s[2:3], v[2:3]
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 2, v2
global_load_b32 v3, v2, s[4:5]
v_add_nc_u32_e32 v2, 0, v2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_bitcmp1_b32 s2, 0
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s7
s_and_saveexec_b32 s7, s8
s_cbranch_execz .LBB0_4
s_add_u32 s8, s2, -1
s_addc_u32 s9, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_add_u32 s4, s4, s10
s_addc_u32 s5, s5, s11
s_load_b32 s3, s[4:5], 0x0
s_lshl_b32 s4, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s4, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
ds_store_b32 v2, v3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
v_cmp_eq_u16_e64 s3, s6, 0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_14
s_and_b32 s4, 0xffff, s6
s_mov_b32 s10, 0
s_mov_b64 s[6:7], s[4:5]
s_branch .LBB0_8
.LBB0_6:
v_cmp_lt_u64_e64 s2, s[6:7], 2
s_and_not1_b32 s4, s12, exec_lo
s_lshr_b64 s[8:9], s[6:7], 1
s_and_not1_b32 s11, s11, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s12, s4, s2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s13
s_xor_b32 s2, s11, -1
s_and_b32 s4, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s4, s10
s_and_not1_b32 s4, s3, exec_lo
s_and_b32 s13, s2, exec_lo
s_mov_b64 s[2:3], s[6:7]
s_or_b32 s3, s4, s13
s_mov_b64 s[6:7], s[8:9]
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_11
.LBB0_8:
s_or_b32 s11, s11, exec_lo
s_or_b32 s12, s12, exec_lo
s_mov_b32 s13, exec_lo
v_cmpx_ge_u64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v2, s6, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s4, s2, 1
v_lshl_add_u32 v2, v2, 2, 0
s_cmp_eq_u64 s[4:5], 0
ds_load_b32 v2, v2
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v4, v2
s_cbranch_scc1 .LBB0_6
s_lshl_b32 s2, s2, 2
v_mov_b32_e32 v3, 0
s_add_i32 s2, s2, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, -4
v_mov_b32_e32 v2, s2
ds_load_b32 v2, v2
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v5, v2
ds_store_b32 v3, v2
s_branch .LBB0_6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s10
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_13
.LBB0_12:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_14:
s_mov_b32 s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execnz .LBB0_12
s_branch .LBB0_13
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18sum_dynamic_kernelPKiPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18sum_dynamic_kernelPKiPim, .Lfunc_end0-_Z18sum_dynamic_kernelPKiPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18sum_dynamic_kernelPKiPim
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18sum_dynamic_kernelPKiPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000991de_00000000-6_sum_dynamic_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim
.type _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim, @function
_Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18sum_dynamic_kernelPKiPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim, .-_Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim
.globl _Z18sum_dynamic_kernelPKiPim
.type _Z18sum_dynamic_kernelPKiPim, @function
_Z18sum_dynamic_kernelPKiPim:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18sum_dynamic_kernelPKiPimPKiPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18sum_dynamic_kernelPKiPim, .-_Z18sum_dynamic_kernelPKiPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18sum_dynamic_kernelPKiPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18sum_dynamic_kernelPKiPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_dynamic_kernel.hip"
.globl _Z33__device_stub__sum_dynamic_kernelPKiPim # -- Begin function _Z33__device_stub__sum_dynamic_kernelPKiPim
.p2align 4, 0x90
.type _Z33__device_stub__sum_dynamic_kernelPKiPim,@function
_Z33__device_stub__sum_dynamic_kernelPKiPim: # @_Z33__device_stub__sum_dynamic_kernelPKiPim
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18sum_dynamic_kernelPKiPim, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__sum_dynamic_kernelPKiPim, .Lfunc_end0-_Z33__device_stub__sum_dynamic_kernelPKiPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18sum_dynamic_kernelPKiPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18sum_dynamic_kernelPKiPim,@object # @_Z18sum_dynamic_kernelPKiPim
.section .rodata,"a",@progbits
.globl _Z18sum_dynamic_kernelPKiPim
.p2align 3, 0x0
_Z18sum_dynamic_kernelPKiPim:
.quad _Z33__device_stub__sum_dynamic_kernelPKiPim
.size _Z18sum_dynamic_kernelPKiPim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18sum_dynamic_kernelPKiPim"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__sum_dynamic_kernelPKiPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18sum_dynamic_kernelPKiPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/device_vector.h>
template <typename PairType>
__device__ void load_pair_array(PairType* arr, PairType* pair_ptr)
{
if constexpr (sizeof(PairType) == 4) {
auto const tmp = *reinterpret_cast<ushort4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
} else {
auto const tmp = *reinterpret_cast<uint4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
}
}
template <typename PairType, typename OutputIt>
__global__ void kernel(PairType* array, OutputIt output, const int n)
{
int tid = threadIdx.x;
auto idx = tid - tid % 2;
PairType arr[2];
load_pair_array(&arr[0], array + idx);
*(output + tid) = arr[0].first + arr[1].first;
}
int main()
{
auto constexpr N = 128;
std::vector<thrust::pair<int, int>> h_pairs(N);
for (auto i = 0; i < N; ++i) {
h_pairs[i].first = h_pairs[i].second = i;
}
thrust::device_vector<thrust::pair<int, int>> d_pairs(h_pairs);
auto input_begin = d_pairs.data().get();
thrust::device_vector<int> d_results(N);
auto output_begin = d_results.data().get();
kernel<<<1, N>>>(input_begin, output_begin, N);
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6kernelIN6thrust20THRUST_200700_800_NS4pairIiiEEPiEvPT_T0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ LEA.HI R0, R4, R4, RZ, 0x1 ; /* 0x0000000404007211 */
/* 0x001fc800078f08ff */
/*0050*/ LOP3.LUT R0, R0, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe00007812 */
/* 0x000fca00078ec0ff */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080402077981 */
/* 0x000ea2000c1e1900 */
/*0090*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
template <typename PairType>
__device__ void load_pair_array(PairType* arr, PairType* pair_ptr)
{
if constexpr (sizeof(PairType) == 4) {
auto const tmp = *reinterpret_cast<ushort4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
} else {
auto const tmp = *reinterpret_cast<uint4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
}
}
template <typename PairType, typename OutputIt>
__global__ void kernel(PairType* array, OutputIt output, const int n)
{
int tid = threadIdx.x;
auto idx = tid - tid % 2;
PairType arr[2];
load_pair_array(&arr[0], array + idx);
*(output + tid) = arr[0].first + arr[1].first;
}
int main()
{
auto constexpr N = 128;
std::vector<thrust::pair<int, int>> h_pairs(N);
for (auto i = 0; i < N; ++i) {
h_pairs[i].first = h_pairs[i].second = i;
}
thrust::device_vector<thrust::pair<int, int>> d_pairs(h_pairs);
auto input_begin = d_pairs.data().get();
thrust::device_vector<int> d_results(N);
auto output_begin = d_results.data().get();
kernel<<<1, N>>>(input_begin, output_begin, N);
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
template <typename PairType>
__device__ void load_pair_array(PairType* arr, PairType* pair_ptr)
{
if constexpr (sizeof(PairType) == 4) {
auto const tmp = *reinterpret_cast<ushort4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
} else {
auto const tmp = *reinterpret_cast<uint4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
}
}
template <typename PairType, typename OutputIt>
__global__ void kernel(PairType* array, OutputIt output, const int n)
{
int tid = threadIdx.x;
auto idx = tid - tid % 2;
PairType arr[2];
load_pair_array(&arr[0], array + idx);
*(output + tid) = arr[0].first + arr[1].first;
}
int main()
{
auto constexpr N = 128;
std::vector<thrust::pair<int, int>> h_pairs(N);
for (auto i = 0; i < N; ++i) {
h_pairs[i].first = h_pairs[i].second = i;
}
thrust::device_vector<thrust::pair<int, int>> d_pairs(h_pairs);
auto input_begin = d_pairs.data().get();
thrust::device_vector<int> d_results(N);
auto output_begin = d_results.data().get();
kernel<<<1, N>>>(input_begin, output_begin, N);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
template <typename PairType>
__device__ void load_pair_array(PairType* arr, PairType* pair_ptr)
{
if constexpr (sizeof(PairType) == 4) {
auto const tmp = *reinterpret_cast<ushort4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
} else {
auto const tmp = *reinterpret_cast<uint4 const*>(pair_ptr);
memcpy(&arr[0], &tmp, 2 * sizeof(PairType));
}
}
template <typename PairType, typename OutputIt>
__global__ void kernel(PairType* array, OutputIt output, const int n)
{
int tid = threadIdx.x;
auto idx = tid - tid % 2;
PairType arr[2];
load_pair_array(&arr[0], array + idx);
*(output + tid) = arr[0].first + arr[1].first;
}
int main()
{
auto constexpr N = 128;
std::vector<thrust::pair<int, int>> h_pairs(N);
for (auto i = 0; i < N; ++i) {
h_pairs[i].first = h_pairs[i].second = i;
}
thrust::device_vector<thrust::pair<int, int>> d_pairs(h_pairs);
auto input_begin = d_pairs.data().get();
thrust::device_vector<int> d_results(N);
auto output_begin = d_results.data().get();
kernel<<<1, N>>>(input_begin, output_begin, N);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,"axG",@progbits,_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,comdat
.protected _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.globl _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.p2align 8
.type _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,@function
_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i:
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
.LBB2_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, v1
s_add_i32 s3, s2, 32
s_add_i32 s2, s2, 8
s_cmp_lg_u32 s2, 16
scratch_store_b64 off, v[1:2], s3
s_cbranch_scc1 .LBB2_1
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, 32 :: v_dual_and_b32 v1, 0x3fe, v0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 3, v1
s_waitcnt lgkmcnt(0)
global_load_b128 v[3:6], v1, s[2:3]
v_mov_b32_e32 v1, 16
s_mov_b64 s[2:3], -16
s_waitcnt vmcnt(0)
scratch_store_b128 off, v[3:6], off offset:16
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_3:
v_readfirstlane_b32 s5, v1
s_add_i32 s6, s4, 16
scratch_load_u8 v3, off, s6
s_add_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s5, 1
s_add_i32 s7, s5, 2
s_add_i32 s5, s5, 3
s_clause 0x2
scratch_load_u8 v4, off, s6
scratch_load_u8 v5, off, s7
scratch_load_u8 v6, off, s5
v_readfirstlane_b32 s5, v2
s_add_i32 s6, s4, 32
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s5, s5, s4
s_add_i32 s4, s4, 4
s_add_i32 s7, s5, 1
s_add_i32 s8, s5, 2
s_add_i32 s5, s5, 3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(3)
scratch_store_b8 off, v3, s6
s_waitcnt vmcnt(2)
scratch_store_b8 off, v4, s7
s_waitcnt vmcnt(1)
scratch_store_b8 off, v5, s8
s_waitcnt vmcnt(0)
scratch_store_b8 off, v6, s5
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc1 .LBB2_3
s_set_inst_prefetch_distance 0x2
s_clause 0x1
scratch_load_b32 v1, off, off offset:32
scratch_load_b32 v2, off, off offset:40
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 48
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,"axG",@progbits,_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,comdat
.Lfunc_end2:
.size _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i, .Lfunc_end2-_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.private_segment_fixed_size: 48
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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