system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6kernelIN6thrust20THRUST_200700_800_NS4pairIiiEEPiEvPT_T0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ LEA.HI R0, R4, R4, RZ, 0x1 ; /* 0x0000000404007211 */
/* 0x001fc800078f08ff */
/*0050*/ LOP3.LUT R0, R0, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe00007812 */
/* 0x000fca00078ec0ff */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080402077981 */
/* 0x000ea2000c1e1900 */
/*0090*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,"axG",@progbits,_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,comdat
.protected _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.globl _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.p2align 8
.type _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,@function
_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i:
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
.LBB2_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, v1
s_add_i32 s3, s2, 32
s_add_i32 s2, s2, 8
s_cmp_lg_u32 s2, 16
scratch_store_b64 off, v[1:2], s3
s_cbranch_scc1 .LBB2_1
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, 32 :: v_dual_and_b32 v1, 0x3fe, v0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 3, v1
s_waitcnt lgkmcnt(0)
global_load_b128 v[3:6], v1, s[2:3]
v_mov_b32_e32 v1, 16
s_mov_b64 s[2:3], -16
s_waitcnt vmcnt(0)
scratch_store_b128 off, v[3:6], off offset:16
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_3:
v_readfirstlane_b32 s5, v1
s_add_i32 s6, s4, 16
scratch_load_u8 v3, off, s6
s_add_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s5, 1
s_add_i32 s7, s5, 2
s_add_i32 s5, s5, 3
s_clause 0x2
scratch_load_u8 v4, off, s6
scratch_load_u8 v5, off, s7
scratch_load_u8 v6, off, s5
v_readfirstlane_b32 s5, v2
s_add_i32 s6, s4, 32
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s5, s5, s4
s_add_i32 s4, s4, 4
s_add_i32 s7, s5, 1
s_add_i32 s8, s5, 2
s_add_i32 s5, s5, 3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(3)
scratch_store_b8 off, v3, s6
s_waitcnt vmcnt(2)
scratch_store_b8 off, v4, s7
s_waitcnt vmcnt(1)
scratch_store_b8 off, v5, s8
s_waitcnt vmcnt(0)
scratch_store_b8 off, v6, s5
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc1 .LBB2_3
s_set_inst_prefetch_distance 0x2
s_clause 0x1
scratch_load_b32 v1, off, off offset:32
scratch_load_b32 v2, off, off offset:40
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 48
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,"axG",@progbits,_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i,comdat
.Lfunc_end2:
.size _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i, .Lfunc_end2-_Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_10device_ptrINS_4pairIiiEEEENS_6detail16wrapped_functionINS8_23allocator_traits_detail5gozerEvEEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i
.private_segment_fixed_size: 48
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z6kernelIN6thrust4pairIiiEEPiEvPT_T0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// 2 - 2d block of threads --> 4 values in each dimension of x and y , grid = 2
__global__ void unique_gid_calculation2d(int * input)
{
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_per_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_per_block;
int num_threads_in_row = num_threads_per_block * gridDim.x;
int row_offset = num_threads_in_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("blockIdx.x : %d, blockIdx.y : %d, threadIdx.x : %d, gid : %d - data : %d \n", blockIdx.x, blockIdx.y, tid, gid, input[gid]);
}
int main()
{
int array_size = 16;
int array_bite_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 64, 12, 1, 33, 22, 11, 9, 12, 13, 89, 90, 77};
for (int i=0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf ("\n \n");
int * d_data;
cudaMalloc((void **)&d_data, array_bite_size);
cudaMemcpy(d_data, h_data, array_bite_size, cudaMemcpyHostToDevice);
dim3 block(2,2);
dim3 grid(2,2);
//unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
} | code for sm_80
Function : _Z24unique_gid_calculation2dPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fc60007ffe0ff */
/*0070*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0080*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002600 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R13, c[0x0][0xc], R12 ; /* 0x000003000d037a24 */
/* 0x002fc800078e020c */
/*00b0*/ IMAD R3, R3, UR4, R2 ; /* 0x0000000403037c24 */
/* 0x000fe2000f8e0202 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fcc00078e0208 */
/*00e0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0120*/ STL.64 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0001e20000100a00 */
/*0130*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0000620000000a00 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0150*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e20000100a00 */
/*0160*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc600000e06ff */
/*0170*/ STL [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0041e80000100800 */
/*0180*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*0190*/ MOV R9, 0x200 ; /* 0x0000020000097802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R20, 0x180 ; /* 0x0000018000147802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01d0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*01e0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01f0*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// 2 - 2d block of threads --> 4 values in each dimension of x and y , grid = 2
__global__ void unique_gid_calculation2d(int * input)
{
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_per_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_per_block;
int num_threads_in_row = num_threads_per_block * gridDim.x;
int row_offset = num_threads_in_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("blockIdx.x : %d, blockIdx.y : %d, threadIdx.x : %d, gid : %d - data : %d \n", blockIdx.x, blockIdx.y, tid, gid, input[gid]);
}
int main()
{
int array_size = 16;
int array_bite_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 64, 12, 1, 33, 22, 11, 9, 12, 13, 89, 90, 77};
for (int i=0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf ("\n \n");
int * d_data;
cudaMalloc((void **)&d_data, array_bite_size);
cudaMemcpy(d_data, h_data, array_bite_size, cudaMemcpyHostToDevice);
dim3 block(2,2);
dim3 grid(2,2);
//unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
} | .file "tmpxft_00044f75_00000000-6_unique_2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z24unique_gid_calculation2dPiPi
.type _Z44__device_stub__Z24unique_gid_calculation2dPiPi, @function
_Z44__device_stub__Z24unique_gid_calculation2dPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24unique_gid_calculation2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z44__device_stub__Z24unique_gid_calculation2dPiPi, .-_Z44__device_stub__Z24unique_gid_calculation2dPiPi
.globl _Z24unique_gid_calculation2dPi
.type _Z24unique_gid_calculation2dPi, @function
_Z24unique_gid_calculation2dPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z24unique_gid_calculation2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z24unique_gid_calculation2dPi, .-_Z24unique_gid_calculation2dPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $4, 40(%rsp)
movl $53, 44(%rsp)
movl $64, 48(%rsp)
movl $12, 52(%rsp)
movl $1, 56(%rsp)
movl $33, 60(%rsp)
movl $22, 64(%rsp)
movl $11, 68(%rsp)
movl $9, 72(%rsp)
movl $12, 76(%rsp)
movl $13, 80(%rsp)
movl $89, 84(%rsp)
movl $90, 88(%rsp)
movl $77, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r12
leaq .LC0(%rip), %rbp
.L12:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z44__device_stub__Z24unique_gid_calculation2dPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z24unique_gid_calculation2dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z24unique_gid_calculation2dPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// 2 - 2d block of threads --> 4 values in each dimension of x and y , grid = 2
__global__ void unique_gid_calculation2d(int * input)
{
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_per_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_per_block;
int num_threads_in_row = num_threads_per_block * gridDim.x;
int row_offset = num_threads_in_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("blockIdx.x : %d, blockIdx.y : %d, threadIdx.x : %d, gid : %d - data : %d \n", blockIdx.x, blockIdx.y, tid, gid, input[gid]);
}
int main()
{
int array_size = 16;
int array_bite_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 64, 12, 1, 33, 22, 11, 9, 12, 13, 89, 90, 77};
for (int i=0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf ("\n \n");
int * d_data;
cudaMalloc((void **)&d_data, array_bite_size);
cudaMemcpy(d_data, h_data, array_bite_size, cudaMemcpyHostToDevice);
dim3 block(2,2);
dim3 grid(2,2);
//unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation2d<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
} | #include "hip/hip_runtime.h"
#include <stdio.h>
// 2 - 2d block of threads --> 4 values in each dimension of x and y , grid = 2
__global__ void unique_gid_calculation2d(int * input)
{
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_per_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_per_block;
int num_threads_in_row = num_threads_per_block * gridDim.x;
int row_offset = num_threads_in_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("blockIdx.x : %d, blockIdx.y : %d, threadIdx.x : %d, gid : %d - data : %d \n", blockIdx.x, blockIdx.y, tid, gid, input[gid]);
}
int main()
{
int array_size = 16;
int array_bite_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 64, 12, 1, 33, 22, 11, 9, 12, 13, 89, 90, 77};
for (int i=0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf ("\n \n");
int * d_data;
hipMalloc((void **)&d_data, array_bite_size);
hipMemcpy(d_data, h_data, array_bite_size, hipMemcpyHostToDevice);
dim3 block(2,2);
dim3 grid(2,2);
//unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation2d<<<grid, block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
// 2 - 2d block of threads --> 4 values in each dimension of x and y , grid = 2
__global__ void unique_gid_calculation2d(int * input)
{
int tid = blockDim.x * threadIdx.y + threadIdx.x;
int num_threads_per_block = blockDim.x * blockDim.y;
int block_offset = blockIdx.x * num_threads_per_block;
int num_threads_in_row = num_threads_per_block * gridDim.x;
int row_offset = num_threads_in_row * blockIdx.y;
int gid = tid + block_offset + row_offset;
printf("blockIdx.x : %d, blockIdx.y : %d, threadIdx.x : %d, gid : %d - data : %d \n", blockIdx.x, blockIdx.y, tid, gid, input[gid]);
}
int main()
{
int array_size = 16;
int array_bite_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 64, 12, 1, 33, 22, 11, 9, 12, 13, 89, 90, 77};
for (int i=0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf ("\n \n");
int * d_data;
hipMalloc((void **)&d_data, array_bite_size);
hipMemcpy(d_data, h_data, array_bite_size, hipMemcpyHostToDevice);
dim3 block(2,2);
dim3 grid(2,2);
//unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation2d<<<grid, block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
} | .text
.file "unique_2d.hip"
.globl _Z39__device_stub__unique_gid_calculation2dPi # -- Begin function _Z39__device_stub__unique_gid_calculation2dPi
.p2align 4, 0x90
.type _Z39__device_stub__unique_gid_calculation2dPi,@function
_Z39__device_stub__unique_gid_calculation2dPi: # @_Z39__device_stub__unique_gid_calculation2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z24unique_gid_calculation2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z39__device_stub__unique_gid_calculation2dPi, .Lfunc_end0-_Z39__device_stub__unique_gid_calculation2dPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 23 # 0x17
.long 9 # 0x9
.long 4 # 0x4
.long 53 # 0x35
.LCPI1_1:
.long 64 # 0x40
.long 12 # 0xc
.long 1 # 0x1
.long 33 # 0x21
.LCPI1_2:
.long 22 # 0x16
.long 11 # 0xb
.long 9 # 0x9
.long 12 # 0xc
.LCPI1_3:
.long 13 # 0xd
.long 89 # 0x59
.long 90 # 0x5a
.long 77 # 0x4d
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [23,9,4,53]
movaps %xmm0, 80(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [64,12,1,33]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [22,11,9,12]
movaps %xmm0, 112(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [13,89,90,77]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z24unique_gid_calculation2dPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24unique_gid_calculation2dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24unique_gid_calculation2dPi,@object # @_Z24unique_gid_calculation2dPi
.section .rodata,"a",@progbits
.globl _Z24unique_gid_calculation2dPi
.p2align 3, 0x0
_Z24unique_gid_calculation2dPi:
.quad _Z39__device_stub__unique_gid_calculation2dPi
.size _Z24unique_gid_calculation2dPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24unique_gid_calculation2dPi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n "
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__unique_gid_calculation2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24unique_gid_calculation2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00044f75_00000000-6_unique_2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z24unique_gid_calculation2dPiPi
.type _Z44__device_stub__Z24unique_gid_calculation2dPiPi, @function
_Z44__device_stub__Z24unique_gid_calculation2dPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24unique_gid_calculation2dPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z44__device_stub__Z24unique_gid_calculation2dPiPi, .-_Z44__device_stub__Z24unique_gid_calculation2dPiPi
.globl _Z24unique_gid_calculation2dPi
.type _Z24unique_gid_calculation2dPi, @function
_Z24unique_gid_calculation2dPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z24unique_gid_calculation2dPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z24unique_gid_calculation2dPi, .-_Z24unique_gid_calculation2dPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $4, 40(%rsp)
movl $53, 44(%rsp)
movl $64, 48(%rsp)
movl $12, 52(%rsp)
movl $1, 56(%rsp)
movl $33, 60(%rsp)
movl $22, 64(%rsp)
movl $11, 68(%rsp)
movl $9, 72(%rsp)
movl $12, 76(%rsp)
movl $13, 80(%rsp)
movl $89, 84(%rsp)
movl $90, 88(%rsp)
movl $77, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r12
leaq .LC0(%rip), %rbp
.L12:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z44__device_stub__Z24unique_gid_calculation2dPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z24unique_gid_calculation2dPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z24unique_gid_calculation2dPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unique_2d.hip"
.globl _Z39__device_stub__unique_gid_calculation2dPi # -- Begin function _Z39__device_stub__unique_gid_calculation2dPi
.p2align 4, 0x90
.type _Z39__device_stub__unique_gid_calculation2dPi,@function
_Z39__device_stub__unique_gid_calculation2dPi: # @_Z39__device_stub__unique_gid_calculation2dPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z24unique_gid_calculation2dPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z39__device_stub__unique_gid_calculation2dPi, .Lfunc_end0-_Z39__device_stub__unique_gid_calculation2dPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 23 # 0x17
.long 9 # 0x9
.long 4 # 0x4
.long 53 # 0x35
.LCPI1_1:
.long 64 # 0x40
.long 12 # 0xc
.long 1 # 0x1
.long 33 # 0x21
.LCPI1_2:
.long 22 # 0x16
.long 11 # 0xb
.long 9 # 0x9
.long 12 # 0xc
.LCPI1_3:
.long 13 # 0xd
.long 89 # 0x59
.long 90 # 0x5a
.long 77 # 0x4d
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [23,9,4,53]
movaps %xmm0, 80(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [64,12,1,33]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [22,11,9,12]
movaps %xmm0, 112(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [13,89,90,77]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z24unique_gid_calculation2dPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24unique_gid_calculation2dPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24unique_gid_calculation2dPi,@object # @_Z24unique_gid_calculation2dPi
.section .rodata,"a",@progbits
.globl _Z24unique_gid_calculation2dPi
.p2align 3, 0x0
_Z24unique_gid_calculation2dPi:
.quad _Z39__device_stub__unique_gid_calculation2dPi
.size _Z24unique_gid_calculation2dPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24unique_gid_calculation2dPi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n "
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__unique_gid_calculation2dPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24unique_gid_calculation2dPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*******************************************************************************
*
*******************************************************************************/
/*************************************************************************
/*************************************************************************/
/*************************************************************************/
__global__ void drawColor(unsigned char* optr, const float* red, const float* green, const float* blue) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float theRed = red[offset];
// theRed = (theRed / 50.0) + 0.5;
if (theRed < 0) theRed = 0;
if (theRed > 1) theRed = 1;
float theGreen = green[offset];
// theGreen = (theGreen / 50.0) + 0.5;
if (theGreen < 0) theGreen = 0;
if (theGreen > 1) theGreen = 1;
float theBlue = blue[offset];
// theBlue = (theBlue / 50.0) + 0.5;
if (theBlue < 0) theBlue = 0;
if (theBlue > 1) theBlue = 1;
optr[offset * 4 + 0] = 255 * theRed; // red
optr[offset * 4 + 1] = 255 * theGreen; // green
optr[offset * 4 + 2] = 255 * theBlue; // blue
optr[offset * 4 + 3] = 255; // alpha (opacity)
} | code for sm_80
Function : _Z9drawColorPhPKfS1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc400078e00ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x040fe400078e0207 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0100*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fc400000006ff */
/*0110*/ FSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fc80003f0e000 */
/*0120*/ FSEL R8, R2, RZ, P0 ; /* 0x000000ff02087208 */
/* 0x000fe40000000000 */
/*0130*/ FSETP.GEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x008fe40003f0e000 */
/*0140*/ FSETP.GEU.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x010fe40003f2e000 */
/*0150*/ FSEL R9, R4, RZ, P0 ; /* 0x000000ff04097208 */
/* 0x000fe40000000000 */
/*0160*/ FSEL R2, R6, RZ, P1 ; /* 0x000000ff06027208 */
/* 0x000fe20000800000 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, 0xff ; /* 0x000000ffff067424 */
/* 0x000fe200078e00ff */
/*0180*/ FMNMX.NAN R9, R9, 1, PT ; /* 0x3f80000009097809 */
/* 0x000fc40003820000 */
/*0190*/ FMNMX.NAN R8, R8, 1, PT ; /* 0x3f80000008087809 */
/* 0x000fe40003820000 */
/*01a0*/ FMNMX.NAN R2, R2, 1, PT ; /* 0x3f80000002027809 */
/* 0x000fe20003820000 */
/*01b0*/ FMUL R9, R9, 255 ; /* 0x437f000009097820 */
/* 0x000fe40000400000 */
/*01c0*/ FMUL R8, R8, 255 ; /* 0x437f000008087820 */
/* 0x000fe40000400000 */
/*01d0*/ FMUL R4, R2, 255 ; /* 0x437f000002047820 */
/* 0x000fe20000400000 */
/*01e0*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe20007f1e0ff */
/*01f0*/ F2I.U32.TRUNC.NTZ R5, R8 ; /* 0x0000000800057305 */
/* 0x000e26000020f000 */
/*0200*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fc400000f0eff */
/*0210*/ PRMT R0, R6, 0x7610, R0 ; /* 0x0000761006007816 */
/* 0x000fc60000000000 */
/*0220*/ F2I.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e64000020f000 */
/*0230*/ STG.E.U8 [R2.64+0x3], R0 ; /* 0x0000030002007986 */
/* 0x000fec000c101104 */
/*0240*/ F2I.U32.TRUNC.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000ea2000020f000 */
/*0250*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe8000c101104 */
/*0260*/ STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902007986 */
/* 0x002fe8000c101104 */
/*0270*/ STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x004fe2000c101104 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*******************************************************************************
*
*******************************************************************************/
/*************************************************************************
/*************************************************************************/
/*************************************************************************/
__global__ void drawColor(unsigned char* optr, const float* red, const float* green, const float* blue) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float theRed = red[offset];
// theRed = (theRed / 50.0) + 0.5;
if (theRed < 0) theRed = 0;
if (theRed > 1) theRed = 1;
float theGreen = green[offset];
// theGreen = (theGreen / 50.0) + 0.5;
if (theGreen < 0) theGreen = 0;
if (theGreen > 1) theGreen = 1;
float theBlue = blue[offset];
// theBlue = (theBlue / 50.0) + 0.5;
if (theBlue < 0) theBlue = 0;
if (theBlue > 1) theBlue = 1;
optr[offset * 4 + 0] = 255 * theRed; // red
optr[offset * 4 + 1] = 255 * theGreen; // green
optr[offset * 4 + 2] = 255 * theBlue; // blue
optr[offset * 4 + 3] = 255; // alpha (opacity)
} | .file "tmpxft_000a3b8b_00000000-6_drawColor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_
.type _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_, @function
_Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9drawColorPhPKfS1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_, .-_Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_
.globl _Z9drawColorPhPKfS1_S1_
.type _Z9drawColorPhPKfS1_S1_, @function
_Z9drawColorPhPKfS1_S1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9drawColorPhPKfS1_S1_, .-_Z9drawColorPhPKfS1_S1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9drawColorPhPKfS1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9drawColorPhPKfS1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*******************************************************************************
*
*******************************************************************************/
/*************************************************************************
/*************************************************************************/
/*************************************************************************/
__global__ void drawColor(unsigned char* optr, const float* red, const float* green, const float* blue) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float theRed = red[offset];
// theRed = (theRed / 50.0) + 0.5;
if (theRed < 0) theRed = 0;
if (theRed > 1) theRed = 1;
float theGreen = green[offset];
// theGreen = (theGreen / 50.0) + 0.5;
if (theGreen < 0) theGreen = 0;
if (theGreen > 1) theGreen = 1;
float theBlue = blue[offset];
// theBlue = (theBlue / 50.0) + 0.5;
if (theBlue < 0) theBlue = 0;
if (theBlue > 1) theBlue = 1;
optr[offset * 4 + 0] = 255 * theRed; // red
optr[offset * 4 + 1] = 255 * theGreen; // green
optr[offset * 4 + 2] = 255 * theBlue; // blue
optr[offset * 4 + 3] = 255; // alpha (opacity)
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*******************************************************************************
*
*******************************************************************************/
/*************************************************************************
/*************************************************************************/
/*************************************************************************/
__global__ void drawColor(unsigned char* optr, const float* red, const float* green, const float* blue) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float theRed = red[offset];
// theRed = (theRed / 50.0) + 0.5;
if (theRed < 0) theRed = 0;
if (theRed > 1) theRed = 1;
float theGreen = green[offset];
// theGreen = (theGreen / 50.0) + 0.5;
if (theGreen < 0) theGreen = 0;
if (theGreen > 1) theGreen = 1;
float theBlue = blue[offset];
// theBlue = (theBlue / 50.0) + 0.5;
if (theBlue < 0) theBlue = 0;
if (theBlue > 1) theBlue = 1;
optr[offset * 4 + 0] = 255 * theRed; // red
optr[offset * 4 + 1] = 255 * theGreen; // green
optr[offset * 4 + 2] = 255 * theBlue; // blue
optr[offset * 4 + 3] = 255; // alpha (opacity)
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*******************************************************************************
*
*******************************************************************************/
/*************************************************************************
/*************************************************************************/
/*************************************************************************/
__global__ void drawColor(unsigned char* optr, const float* red, const float* green, const float* blue) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float theRed = red[offset];
// theRed = (theRed / 50.0) + 0.5;
if (theRed < 0) theRed = 0;
if (theRed > 1) theRed = 1;
float theGreen = green[offset];
// theGreen = (theGreen / 50.0) + 0.5;
if (theGreen < 0) theGreen = 0;
if (theGreen > 1) theGreen = 1;
float theBlue = blue[offset];
// theBlue = (theBlue / 50.0) + 0.5;
if (theBlue < 0) theBlue = 0;
if (theBlue > 1) theBlue = 1;
optr[offset * 4 + 0] = 255 * theRed; // red
optr[offset * 4 + 1] = 255 * theGreen; // green
optr[offset * 4 + 2] = 255 * theBlue; // blue
optr[offset * 4 + 3] = 255; // alpha (opacity)
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9drawColorPhPKfS1_S1_
.globl _Z9drawColorPhPKfS1_S1_
.p2align 8
.type _Z9drawColorPhPKfS1_S1_,@function
_Z9drawColorPhPKfS1_S1_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s8, 16
s_and_b32 s8, s8, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b256 s[0:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v3, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v0, 2, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
global_load_b32 v2, v[2:3], off
v_or_b32_e32 v3, 1, v0
v_or_b32_e32 v6, 2, v0
v_or_b32_e32 v7, 3, v0
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_ashrrev_i32_e32 v9, 31, v3
v_ashrrev_i32_e32 v10, 31, v6
v_ashrrev_i32_e32 v11, 31, v7
s_waitcnt vmcnt(2)
v_cmp_ngt_f32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
s_waitcnt vmcnt(1)
v_cmp_ngt_f32_e32 vcc_lo, 0, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 1.0, v4
v_cndmask_b32_e32 v4, 1.0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 1.0, v5
v_dual_mov_b32 v8, 0xff :: v_dual_cndmask_b32 v5, 1.0, v5
v_cmp_nlt_f32_e32 vcc_lo, 1.0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_mul_f32 v13, 0x437f0000, v5 :: v_dual_cndmask_b32 v12, 1.0, v2
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v9, vcc_lo
v_mul_f32_e32 v9, 0x437f0000, v4
v_mul_f32_e32 v12, 0x437f0000, v12
v_add_co_u32 v4, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cvt_i32_f32_e32 v9, v9
v_cvt_i32_f32_e32 v10, v13
v_add_co_u32 v6, vcc_lo, s0, v7
v_cvt_i32_f32_e32 v12, v12
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v11, vcc_lo
s_clause 0x3
global_store_b8 v[0:1], v9, off
global_store_b8 v[2:3], v10, off
global_store_b8 v[4:5], v12, off
global_store_b8 v[6:7], v8, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9drawColorPhPKfS1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9drawColorPhPKfS1_S1_, .Lfunc_end0-_Z9drawColorPhPKfS1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9drawColorPhPKfS1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9drawColorPhPKfS1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*******************************************************************************
*
*******************************************************************************/
/*************************************************************************
/*************************************************************************/
/*************************************************************************/
__global__ void drawColor(unsigned char* optr, const float* red, const float* green, const float* blue) {
// map from threadIdx/BlockIdx to pixel position
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float theRed = red[offset];
// theRed = (theRed / 50.0) + 0.5;
if (theRed < 0) theRed = 0;
if (theRed > 1) theRed = 1;
float theGreen = green[offset];
// theGreen = (theGreen / 50.0) + 0.5;
if (theGreen < 0) theGreen = 0;
if (theGreen > 1) theGreen = 1;
float theBlue = blue[offset];
// theBlue = (theBlue / 50.0) + 0.5;
if (theBlue < 0) theBlue = 0;
if (theBlue > 1) theBlue = 1;
optr[offset * 4 + 0] = 255 * theRed; // red
optr[offset * 4 + 1] = 255 * theGreen; // green
optr[offset * 4 + 2] = 255 * theBlue; // blue
optr[offset * 4 + 3] = 255; // alpha (opacity)
} | .text
.file "drawColor.hip"
.globl _Z24__device_stub__drawColorPhPKfS1_S1_ # -- Begin function _Z24__device_stub__drawColorPhPKfS1_S1_
.p2align 4, 0x90
.type _Z24__device_stub__drawColorPhPKfS1_S1_,@function
_Z24__device_stub__drawColorPhPKfS1_S1_: # @_Z24__device_stub__drawColorPhPKfS1_S1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9drawColorPhPKfS1_S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__drawColorPhPKfS1_S1_, .Lfunc_end0-_Z24__device_stub__drawColorPhPKfS1_S1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9drawColorPhPKfS1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9drawColorPhPKfS1_S1_,@object # @_Z9drawColorPhPKfS1_S1_
.section .rodata,"a",@progbits
.globl _Z9drawColorPhPKfS1_S1_
.p2align 3, 0x0
_Z9drawColorPhPKfS1_S1_:
.quad _Z24__device_stub__drawColorPhPKfS1_S1_
.size _Z9drawColorPhPKfS1_S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9drawColorPhPKfS1_S1_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__drawColorPhPKfS1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9drawColorPhPKfS1_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9drawColorPhPKfS1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc400078e00ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x040fe400078e0207 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0100*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fc400000006ff */
/*0110*/ FSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fc80003f0e000 */
/*0120*/ FSEL R8, R2, RZ, P0 ; /* 0x000000ff02087208 */
/* 0x000fe40000000000 */
/*0130*/ FSETP.GEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x008fe40003f0e000 */
/*0140*/ FSETP.GEU.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x010fe40003f2e000 */
/*0150*/ FSEL R9, R4, RZ, P0 ; /* 0x000000ff04097208 */
/* 0x000fe40000000000 */
/*0160*/ FSEL R2, R6, RZ, P1 ; /* 0x000000ff06027208 */
/* 0x000fe20000800000 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, 0xff ; /* 0x000000ffff067424 */
/* 0x000fe200078e00ff */
/*0180*/ FMNMX.NAN R9, R9, 1, PT ; /* 0x3f80000009097809 */
/* 0x000fc40003820000 */
/*0190*/ FMNMX.NAN R8, R8, 1, PT ; /* 0x3f80000008087809 */
/* 0x000fe40003820000 */
/*01a0*/ FMNMX.NAN R2, R2, 1, PT ; /* 0x3f80000002027809 */
/* 0x000fe20003820000 */
/*01b0*/ FMUL R9, R9, 255 ; /* 0x437f000009097820 */
/* 0x000fe40000400000 */
/*01c0*/ FMUL R8, R8, 255 ; /* 0x437f000008087820 */
/* 0x000fe40000400000 */
/*01d0*/ FMUL R4, R2, 255 ; /* 0x437f000002047820 */
/* 0x000fe20000400000 */
/*01e0*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe20007f1e0ff */
/*01f0*/ F2I.U32.TRUNC.NTZ R5, R8 ; /* 0x0000000800057305 */
/* 0x000e26000020f000 */
/*0200*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fc400000f0eff */
/*0210*/ PRMT R0, R6, 0x7610, R0 ; /* 0x0000761006007816 */
/* 0x000fc60000000000 */
/*0220*/ F2I.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e64000020f000 */
/*0230*/ STG.E.U8 [R2.64+0x3], R0 ; /* 0x0000030002007986 */
/* 0x000fec000c101104 */
/*0240*/ F2I.U32.TRUNC.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000ea2000020f000 */
/*0250*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe8000c101104 */
/*0260*/ STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902007986 */
/* 0x002fe8000c101104 */
/*0270*/ STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x004fe2000c101104 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9drawColorPhPKfS1_S1_
.globl _Z9drawColorPhPKfS1_S1_
.p2align 8
.type _Z9drawColorPhPKfS1_S1_,@function
_Z9drawColorPhPKfS1_S1_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s8, 16
s_and_b32 s8, s8, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b256 s[0:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v3, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v0, 2, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
global_load_b32 v2, v[2:3], off
v_or_b32_e32 v3, 1, v0
v_or_b32_e32 v6, 2, v0
v_or_b32_e32 v7, 3, v0
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_ashrrev_i32_e32 v9, 31, v3
v_ashrrev_i32_e32 v10, 31, v6
v_ashrrev_i32_e32 v11, 31, v7
s_waitcnt vmcnt(2)
v_cmp_ngt_f32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
s_waitcnt vmcnt(1)
v_cmp_ngt_f32_e32 vcc_lo, 0, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 1.0, v4
v_cndmask_b32_e32 v4, 1.0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 1.0, v5
v_dual_mov_b32 v8, 0xff :: v_dual_cndmask_b32 v5, 1.0, v5
v_cmp_nlt_f32_e32 vcc_lo, 1.0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_mul_f32 v13, 0x437f0000, v5 :: v_dual_cndmask_b32 v12, 1.0, v2
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v9, vcc_lo
v_mul_f32_e32 v9, 0x437f0000, v4
v_mul_f32_e32 v12, 0x437f0000, v12
v_add_co_u32 v4, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cvt_i32_f32_e32 v9, v9
v_cvt_i32_f32_e32 v10, v13
v_add_co_u32 v6, vcc_lo, s0, v7
v_cvt_i32_f32_e32 v12, v12
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v11, vcc_lo
s_clause 0x3
global_store_b8 v[0:1], v9, off
global_store_b8 v[2:3], v10, off
global_store_b8 v[4:5], v12, off
global_store_b8 v[6:7], v8, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9drawColorPhPKfS1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9drawColorPhPKfS1_S1_, .Lfunc_end0-_Z9drawColorPhPKfS1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9drawColorPhPKfS1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9drawColorPhPKfS1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a3b8b_00000000-6_drawColor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_
.type _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_, @function
_Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9drawColorPhPKfS1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_, .-_Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_
.globl _Z9drawColorPhPKfS1_S1_
.type _Z9drawColorPhPKfS1_S1_, @function
_Z9drawColorPhPKfS1_S1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9drawColorPhPKfS1_S1_PhPKfS1_S1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9drawColorPhPKfS1_S1_, .-_Z9drawColorPhPKfS1_S1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9drawColorPhPKfS1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9drawColorPhPKfS1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "drawColor.hip"
.globl _Z24__device_stub__drawColorPhPKfS1_S1_ # -- Begin function _Z24__device_stub__drawColorPhPKfS1_S1_
.p2align 4, 0x90
.type _Z24__device_stub__drawColorPhPKfS1_S1_,@function
_Z24__device_stub__drawColorPhPKfS1_S1_: # @_Z24__device_stub__drawColorPhPKfS1_S1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9drawColorPhPKfS1_S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__drawColorPhPKfS1_S1_, .Lfunc_end0-_Z24__device_stub__drawColorPhPKfS1_S1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9drawColorPhPKfS1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9drawColorPhPKfS1_S1_,@object # @_Z9drawColorPhPKfS1_S1_
.section .rodata,"a",@progbits
.globl _Z9drawColorPhPKfS1_S1_
.p2align 3, 0x0
_Z9drawColorPhPKfS1_S1_:
.quad _Z24__device_stub__drawColorPhPKfS1_S1_
.size _Z9drawColorPhPKfS1_S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9drawColorPhPKfS1_S1_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__drawColorPhPKfS1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9drawColorPhPKfS1_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define SZ 8
__global__ void write(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
__global__ void append(int *ret, int a, int b) {
ret[threadIdx.x] += a + b + threadIdx.x;
}
int main() {
int *ret;
cudaMallocManaged(&ret, SZ * sizeof(int));
// set direct access hint
cudaMemAdvise(ret, SZ * sizeof(int), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
// pages populated in GPU memory
write<<< 1, SZ >>>(ret, 10, 100);
cudaDeviceSynchronize();
// print operation - directManagedMemAccessFromHost=1: CPU accesses GPU memory directly without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
// directManagedMemAccessFromHost=1: GPU accesses GPU memory without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
append <<<1, SZ>>>(ret, 10, 100);
cudaDeviceSynchronize();
printf("\nNew results:\n");
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
cudaFree(ret);
return 0;
} | code for sm_80
Function : _Z6appendPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0002 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ IADD3 R5, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000057a10 */
/* 0x004fca0007ffe005 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5writePiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002007a10 */
/* 0x001fd00007ffe0ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0003 */
/*0060*/ IADD3 R5, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000057a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define SZ 8
__global__ void write(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
__global__ void append(int *ret, int a, int b) {
ret[threadIdx.x] += a + b + threadIdx.x;
}
int main() {
int *ret;
cudaMallocManaged(&ret, SZ * sizeof(int));
// set direct access hint
cudaMemAdvise(ret, SZ * sizeof(int), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
// pages populated in GPU memory
write<<< 1, SZ >>>(ret, 10, 100);
cudaDeviceSynchronize();
// print operation - directManagedMemAccessFromHost=1: CPU accesses GPU memory directly without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
// directManagedMemAccessFromHost=1: GPU accesses GPU memory without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
append <<<1, SZ>>>(ret, 10, 100);
cudaDeviceSynchronize();
printf("\nNew results:\n");
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
cudaFree(ret);
return 0;
} | .file "tmpxft_000fa4b1_00000000-6_hwCoherency.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5writePiiiPiii
.type _Z26__device_stub__Z5writePiiiPiii, @function
_Z26__device_stub__Z5writePiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5writePiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5writePiiiPiii, .-_Z26__device_stub__Z5writePiiiPiii
.globl _Z5writePiii
.type _Z5writePiii, @function
_Z5writePiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5writePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5writePiii, .-_Z5writePiii
.globl _Z27__device_stub__Z6appendPiiiPiii
.type _Z27__device_stub__Z6appendPiiiPiii, @function
_Z27__device_stub__Z6appendPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6appendPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z6appendPiiiPiii, .-_Z27__device_stub__Z6appendPiiiPiii
.globl _Z6appendPiii
.type _Z6appendPiii, @function
_Z6appendPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6appendPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6appendPiii, .-_Z6appendPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d: A+B = %d\n"
.LC1:
.string "\nNew results:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32, %esi
call cudaMallocManaged@PLT
movl $-1, %ecx
movl $5, %edx
movl $32, %esi
movq 8(%rsp), %rdi
call cudaMemAdvise@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L21:
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L21
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L23:
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $100, %edx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5writePiiiPiii
jmp .L20
.L29:
movl $100, %edx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6appendPiiiPiii
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6appendPiii"
.LC3:
.string "_Z5writePiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6appendPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5writePiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define SZ 8
__global__ void write(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
__global__ void append(int *ret, int a, int b) {
ret[threadIdx.x] += a + b + threadIdx.x;
}
int main() {
int *ret;
cudaMallocManaged(&ret, SZ * sizeof(int));
// set direct access hint
cudaMemAdvise(ret, SZ * sizeof(int), cudaMemAdviseSetAccessedBy, cudaCpuDeviceId);
// pages populated in GPU memory
write<<< 1, SZ >>>(ret, 10, 100);
cudaDeviceSynchronize();
// print operation - directManagedMemAccessFromHost=1: CPU accesses GPU memory directly without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
// directManagedMemAccessFromHost=1: GPU accesses GPU memory without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
append <<<1, SZ>>>(ret, 10, 100);
cudaDeviceSynchronize();
printf("\nNew results:\n");
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
cudaFree(ret);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SZ 8
__global__ void write(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
__global__ void append(int *ret, int a, int b) {
ret[threadIdx.x] += a + b + threadIdx.x;
}
int main() {
int *ret;
hipMallocManaged(&ret, SZ * sizeof(int));
// set direct access hint
hipMemAdvise(ret, SZ * sizeof(int), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
// pages populated in GPU memory
write<<< 1, SZ >>>(ret, 10, 100);
hipDeviceSynchronize();
// print operation - directManagedMemAccessFromHost=1: CPU accesses GPU memory directly without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
// directManagedMemAccessFromHost=1: GPU accesses GPU memory without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
append <<<1, SZ>>>(ret, 10, 100);
hipDeviceSynchronize();
printf("\nNew results:\n");
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
hipFree(ret);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SZ 8
__global__ void write(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
__global__ void append(int *ret, int a, int b) {
ret[threadIdx.x] += a + b + threadIdx.x;
}
int main() {
int *ret;
hipMallocManaged(&ret, SZ * sizeof(int));
// set direct access hint
hipMemAdvise(ret, SZ * sizeof(int), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
// pages populated in GPU memory
write<<< 1, SZ >>>(ret, 10, 100);
hipDeviceSynchronize();
// print operation - directManagedMemAccessFromHost=1: CPU accesses GPU memory directly without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
// directManagedMemAccessFromHost=1: GPU accesses GPU memory without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
append <<<1, SZ>>>(ret, 10, 100);
hipDeviceSynchronize();
printf("\nNew results:\n");
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
hipFree(ret);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5writePiii
.globl _Z5writePiii
.p2align 8
.type _Z5writePiii,@function
_Z5writePiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add3_u32 v1, s3, s2, v0
v_lshlrev_b32_e32 v0, 2, v0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5writePiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5writePiii, .Lfunc_end0-_Z5writePiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6appendPiii
.globl _Z6appendPiii
.p2align 8
.type _Z6appendPiii,@function
_Z6appendPiii:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[0:1]
s_add_i32 s2, s3, s2
s_waitcnt vmcnt(0)
v_add3_u32 v0, s2, v0, v2
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6appendPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6appendPiii, .Lfunc_end1-_Z6appendPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5writePiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z5writePiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6appendPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6appendPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SZ 8
__global__ void write(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
__global__ void append(int *ret, int a, int b) {
ret[threadIdx.x] += a + b + threadIdx.x;
}
int main() {
int *ret;
hipMallocManaged(&ret, SZ * sizeof(int));
// set direct access hint
hipMemAdvise(ret, SZ * sizeof(int), hipMemAdviseSetAccessedBy, hipCpuDeviceId);
// pages populated in GPU memory
write<<< 1, SZ >>>(ret, 10, 100);
hipDeviceSynchronize();
// print operation - directManagedMemAccessFromHost=1: CPU accesses GPU memory directly without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
// directManagedMemAccessFromHost=1: GPU accesses GPU memory without migrations
// If directManagedMemAccessFromHost was 0, then CPU faults and triggers device-to-host migration
append <<<1, SZ>>>(ret, 10, 100);
hipDeviceSynchronize();
printf("\nNew results:\n");
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
hipFree(ret);
return 0;
} | .text
.file "hwCoherency.hip"
.globl _Z20__device_stub__writePiii # -- Begin function _Z20__device_stub__writePiii
.p2align 4, 0x90
.type _Z20__device_stub__writePiii,@function
_Z20__device_stub__writePiii: # @_Z20__device_stub__writePiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5writePiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__writePiii, .Lfunc_end0-_Z20__device_stub__writePiii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__appendPiii # -- Begin function _Z21__device_stub__appendPiii
.p2align 4, 0x90
.type _Z21__device_stub__appendPiii,@function
_Z21__device_stub__appendPiii: # @_Z21__device_stub__appendPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6appendPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__appendPiii, .Lfunc_end1-_Z21__device_stub__appendPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 16(%rsp), %rdi
movl $32, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
movl $32, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
leaq 7(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
movl $100, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5writePiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%r15,4), %edx
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq $8, %r15
jne .LBB2_3
# %bb.4:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
movl $100, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6appendPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB2_7
# %bb.8:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5writePiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6appendPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5writePiii,@object # @_Z5writePiii
.section .rodata,"a",@progbits
.globl _Z5writePiii
.p2align 3, 0x0
_Z5writePiii:
.quad _Z20__device_stub__writePiii
.size _Z5writePiii, 8
.type _Z6appendPiii,@object # @_Z6appendPiii
.globl _Z6appendPiii
.p2align 3, 0x0
_Z6appendPiii:
.quad _Z21__device_stub__appendPiii
.size _Z6appendPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d: A+B = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5writePiii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6appendPiii"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNew results:"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__writePiii
.addrsig_sym _Z21__device_stub__appendPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5writePiii
.addrsig_sym _Z6appendPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6appendPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0002 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ IADD3 R5, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000057a10 */
/* 0x004fca0007ffe005 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5writePiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002007a10 */
/* 0x001fd00007ffe0ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0003 */
/*0060*/ IADD3 R5, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000057a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5writePiii
.globl _Z5writePiii
.p2align 8
.type _Z5writePiii,@function
_Z5writePiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add3_u32 v1, s3, s2, v0
v_lshlrev_b32_e32 v0, 2, v0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5writePiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5writePiii, .Lfunc_end0-_Z5writePiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6appendPiii
.globl _Z6appendPiii
.p2align 8
.type _Z6appendPiii,@function
_Z6appendPiii:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[0:1]
s_add_i32 s2, s3, s2
s_waitcnt vmcnt(0)
v_add3_u32 v0, s2, v0, v2
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6appendPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6appendPiii, .Lfunc_end1-_Z6appendPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5writePiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z5writePiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6appendPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6appendPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fa4b1_00000000-6_hwCoherency.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5writePiiiPiii
.type _Z26__device_stub__Z5writePiiiPiii, @function
_Z26__device_stub__Z5writePiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5writePiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5writePiiiPiii, .-_Z26__device_stub__Z5writePiiiPiii
.globl _Z5writePiii
.type _Z5writePiii, @function
_Z5writePiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5writePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5writePiii, .-_Z5writePiii
.globl _Z27__device_stub__Z6appendPiiiPiii
.type _Z27__device_stub__Z6appendPiiiPiii, @function
_Z27__device_stub__Z6appendPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6appendPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z6appendPiiiPiii, .-_Z27__device_stub__Z6appendPiiiPiii
.globl _Z6appendPiii
.type _Z6appendPiii, @function
_Z6appendPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6appendPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6appendPiii, .-_Z6appendPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d: A+B = %d\n"
.LC1:
.string "\nNew results:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32, %esi
call cudaMallocManaged@PLT
movl $-1, %ecx
movl $5, %edx
movl $32, %esi
movq 8(%rsp), %rdi
call cudaMemAdvise@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L21:
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L21
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L23:
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $100, %edx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5writePiiiPiii
jmp .L20
.L29:
movl $100, %edx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6appendPiiiPiii
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6appendPiii"
.LC3:
.string "_Z5writePiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6appendPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5writePiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hwCoherency.hip"
.globl _Z20__device_stub__writePiii # -- Begin function _Z20__device_stub__writePiii
.p2align 4, 0x90
.type _Z20__device_stub__writePiii,@function
_Z20__device_stub__writePiii: # @_Z20__device_stub__writePiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5writePiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__writePiii, .Lfunc_end0-_Z20__device_stub__writePiii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__appendPiii # -- Begin function _Z21__device_stub__appendPiii
.p2align 4, 0x90
.type _Z21__device_stub__appendPiii,@function
_Z21__device_stub__appendPiii: # @_Z21__device_stub__appendPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6appendPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__appendPiii, .Lfunc_end1-_Z21__device_stub__appendPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 16(%rsp), %rdi
movl $32, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
movl $32, %esi
movl $5, %edx
movl $-1, %ecx
callq hipMemAdvise
leaq 7(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
movl $100, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5writePiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%r15,4), %edx
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq $8, %r15
jne .LBB2_3
# %bb.4:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
movl $100, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6appendPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB2_7
# %bb.8:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5writePiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6appendPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5writePiii,@object # @_Z5writePiii
.section .rodata,"a",@progbits
.globl _Z5writePiii
.p2align 3, 0x0
_Z5writePiii:
.quad _Z20__device_stub__writePiii
.size _Z5writePiii, 8
.type _Z6appendPiii,@object # @_Z6appendPiii
.globl _Z6appendPiii
.p2align 3, 0x0
_Z6appendPiii:
.quad _Z21__device_stub__appendPiii
.size _Z6appendPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d: A+B = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5writePiii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6appendPiii"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNew results:"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__writePiii
.addrsig_sym _Z21__device_stub__appendPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5writePiii
.addrsig_sym _Z6appendPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void x3(int* x4, int x5, int x6) {
int x7 = gridDim.x * blockDim.x;
int x8 = threadIdx.x + blockIdx.x * blockDim.x;
int x9 = -x5;
while (x8 < x6) {
int x10 = x8;
if (x4[x10] > x5) x4[x10] = x5;
if (x4[x10] < x9) x4[x10] = x9;
x8 = x8 + x7;
}
} | code for sm_80
Function : _Z2x3Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x360 ; /* 0x000002d000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f45070 */
/*00d0*/ IMAD.IADD R2, R0, 0x1, R3 ; /* 0x0000000100027824 */
/* 0x000fca00078e0203 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x16c], R0 ; /* 0x00005b0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0210*/ IMAD.MOV R2, RZ, RZ, -c[0x0][0x168] ; /* 0x80005a00ff027624 */
/* 0x000fe200078e02ff */
/*0220*/ LOP3.LUT P1, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000782c0ff */
/*0230*/ @!P1 BRA 0x350 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0260*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0208 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*0280*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0290*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*02b0*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe200078e0203 */
/*02c0*/ ISETP.GT.AND P1, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x004fc80003f24270 */
/*02d0*/ SEL R7, R8, c[0x0][0x168], !P1 ; /* 0x00005a0008077a07 */
/* 0x000fc80004800000 */
/*02e0*/ ISETP.GE.AND P2, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fc8000bf46270 */
/*02f0*/ ISETP.GT.OR P1, PT, R8, c[0x0][0x168], !P2 ; /* 0x00005a0008007a0c */
/* 0x000fe40005724670 */
/*0300*/ SEL R7, R2, R7, !P2 ; /* 0x0000000702077207 */
/* 0x000fd60005000000 */
/*0310*/ @P1 STG.E [R4.64], R7 ; /* 0x0000000704001986 */
/* 0x0001e2000c101906 */
/*0320*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*0330*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fd800078e0204 */
/*0340*/ @P1 BRA 0x270 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0204 */
/*0390*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*03b0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*03c0*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x004fc80003f04270 */
/*03d0*/ SEL R11, R6, c[0x0][0x168], !P0 ; /* 0x00005a00060b7a07 */
/* 0x000fc80004000000 */
/*03e0*/ ISETP.GE.AND P1, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fc8000bf26270 */
/*03f0*/ ISETP.GT.OR P0, PT, R6, c[0x0][0x168], !P1 ; /* 0x00005a0006007a0c */
/* 0x000fe20004f04670 */
/*0400*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x000fd800078e0204 */
/*0410*/ @P0 SEL R11, R2, R11, !P1 ; /* 0x0000000b020b0207 */
/* 0x000fca0004800000 */
/*0420*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0430*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea4000c1e1900 */
/*0440*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x004fc80003f04270 */
/*0450*/ SEL R9, R8, c[0x0][0x168], !P0 ; /* 0x00005a0008097a07 */
/* 0x000fc80004000000 */
/*0460*/ ISETP.GE.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fc8000bf26270 */
/*0470*/ ISETP.GT.OR P0, PT, R8, c[0x0][0x168], !P1 ; /* 0x00005a0008007a0c */
/* 0x000fe40004f04670 */
/*0480*/ SEL R13, R2, R9, !P1 ; /* 0x00000009020d7207 */
/* 0x000fe20004800000 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fd400078e0206 */
/*04a0*/ @P0 STG.E [R6.64], R13 ; /* 0x0000000d06000986 */
/* 0x0003e8000c101906 */
/*04b0*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x004fc80003f04270 */
/*04d0*/ SEL R5, R10, c[0x0][0x168], !P0 ; /* 0x00005a000a057a07 */
/* 0x001fc80004000000 */
/*04e0*/ ISETP.GE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fc8000bf26270 */
/*04f0*/ ISETP.GT.OR P0, PT, R10, c[0x0][0x168], !P1 ; /* 0x00005a000a007a0c */
/* 0x000fe40004f04670 */
/*0500*/ SEL R11, R2, R5, !P1 ; /* 0x00000005020b7207 */
/* 0x000fe20004800000 */
/*0510*/ IMAD.WIDE R4, R0, 0x4, R8 ; /* 0x0000000400047825 */
/* 0x000fd400078e0208 */
/*0520*/ @P0 STG.E [R8.64], R11 ; /* 0x0000000b08000986 */
/* 0x0001e8000c101906 */
/*0530*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0550*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fe40007ffe000 */
/*0560*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x004fc80003f04270 */
/*0570*/ SEL R7, R10, c[0x0][0x168], !P0 ; /* 0x00005a000a077a07 */
/* 0x002fc80004000000 */
/*0580*/ ISETP.GE.AND P1, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fc8000bf26270 */
/*0590*/ ISETP.GT.OR P0, PT, R10, c[0x0][0x168], !P1 ; /* 0x00005a000a007a0c */
/* 0x000fe40004f04670 */
/*05a0*/ SEL R7, R2, R7, !P1 ; /* 0x0000000702077207 */
/* 0x000fd60004800000 */
/*05b0*/ @P0 STG.E [R4.64], R7 ; /* 0x0000000704000986 */
/* 0x0001e2000c101906 */
/*05c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*05d0*/ @!P0 BRA 0x370 ; /* 0xfffffd9000008947 */
/* 0x001fea000383ffff */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void x3(int* x4, int x5, int x6) {
int x7 = gridDim.x * blockDim.x;
int x8 = threadIdx.x + blockIdx.x * blockDim.x;
int x9 = -x5;
while (x8 < x6) {
int x10 = x8;
if (x4[x10] > x5) x4[x10] = x5;
if (x4[x10] < x9) x4[x10] = x9;
x8 = x8 + x7;
}
} | .file "tmpxft_00138797_00000000-6_x3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z2x3PiiiPiii
.type _Z23__device_stub__Z2x3PiiiPiii, @function
_Z23__device_stub__Z2x3PiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2x3Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z2x3PiiiPiii, .-_Z23__device_stub__Z2x3PiiiPiii
.globl _Z2x3Piii
.type _Z2x3Piii, @function
_Z2x3Piii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2x3PiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2x3Piii, .-_Z2x3Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2x3Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2x3Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void x3(int* x4, int x5, int x6) {
int x7 = gridDim.x * blockDim.x;
int x8 = threadIdx.x + blockIdx.x * blockDim.x;
int x9 = -x5;
while (x8 < x6) {
int x10 = x8;
if (x4[x10] > x5) x4[x10] = x5;
if (x4[x10] < x9) x4[x10] = x9;
x8 = x8 + x7;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void x3(int* x4, int x5, int x6) {
int x7 = gridDim.x * blockDim.x;
int x8 = threadIdx.x + blockIdx.x * blockDim.x;
int x9 = -x5;
while (x8 < x6) {
int x10 = x8;
if (x4[x10] > x5) x4[x10] = x5;
if (x4[x10] < x9) x4[x10] = x9;
x8 = x8 + x7;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void x3(int* x4, int x5, int x6) {
int x7 = gridDim.x * blockDim.x;
int x8 = threadIdx.x + blockIdx.x * blockDim.x;
int x9 = -x5;
while (x8 < x6) {
int x10 = x8;
if (x4[x10] > x5) x4[x10] = x5;
if (x4[x10] < x9) x4[x10] = x9;
x8 = x8 + x7;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2x3Piii
.globl _Z2x3Piii
.p2align 8
.type _Z2x3Piii,@function
_Z2x3Piii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s6, s[0:1], 0xc
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_ashr_i32 s3, s2, 31
s_sub_i32 s8, 0, s1
s_lshl_b64 s[4:5], s[2:3], 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_7
.LBB0_3:
global_load_b32 v0, v[2:3], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 s1, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, s1
global_store_b32 v[2:3], v0, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v0, v[2:3], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, s8
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2x3Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2x3Piii, .Lfunc_end0-_Z2x3Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2x3Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2x3Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void x3(int* x4, int x5, int x6) {
int x7 = gridDim.x * blockDim.x;
int x8 = threadIdx.x + blockIdx.x * blockDim.x;
int x9 = -x5;
while (x8 < x6) {
int x10 = x8;
if (x4[x10] > x5) x4[x10] = x5;
if (x4[x10] < x9) x4[x10] = x9;
x8 = x8 + x7;
}
} | .text
.file "x3.hip"
.globl _Z17__device_stub__x3Piii # -- Begin function _Z17__device_stub__x3Piii
.p2align 4, 0x90
.type _Z17__device_stub__x3Piii,@function
_Z17__device_stub__x3Piii: # @_Z17__device_stub__x3Piii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2x3Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z17__device_stub__x3Piii, .Lfunc_end0-_Z17__device_stub__x3Piii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2x3Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2x3Piii,@object # @_Z2x3Piii
.section .rodata,"a",@progbits
.globl _Z2x3Piii
.p2align 3, 0x0
_Z2x3Piii:
.quad _Z17__device_stub__x3Piii
.size _Z2x3Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2x3Piii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__x3Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2x3Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2x3Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x360 ; /* 0x000002d000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f45070 */
/*00d0*/ IMAD.IADD R2, R0, 0x1, R3 ; /* 0x0000000100027824 */
/* 0x000fca00078e0203 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x16c], R0 ; /* 0x00005b0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0210*/ IMAD.MOV R2, RZ, RZ, -c[0x0][0x168] ; /* 0x80005a00ff027624 */
/* 0x000fe200078e02ff */
/*0220*/ LOP3.LUT P1, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000782c0ff */
/*0230*/ @!P1 BRA 0x350 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0260*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0208 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*0280*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0290*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*02b0*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe200078e0203 */
/*02c0*/ ISETP.GT.AND P1, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x004fc80003f24270 */
/*02d0*/ SEL R7, R8, c[0x0][0x168], !P1 ; /* 0x00005a0008077a07 */
/* 0x000fc80004800000 */
/*02e0*/ ISETP.GE.AND P2, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fc8000bf46270 */
/*02f0*/ ISETP.GT.OR P1, PT, R8, c[0x0][0x168], !P2 ; /* 0x00005a0008007a0c */
/* 0x000fe40005724670 */
/*0300*/ SEL R7, R2, R7, !P2 ; /* 0x0000000702077207 */
/* 0x000fd60005000000 */
/*0310*/ @P1 STG.E [R4.64], R7 ; /* 0x0000000704001986 */
/* 0x0001e2000c101906 */
/*0320*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*0330*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fd800078e0204 */
/*0340*/ @P1 BRA 0x270 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0204 */
/*0390*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*03b0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*03c0*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x004fc80003f04270 */
/*03d0*/ SEL R11, R6, c[0x0][0x168], !P0 ; /* 0x00005a00060b7a07 */
/* 0x000fc80004000000 */
/*03e0*/ ISETP.GE.AND P1, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fc8000bf26270 */
/*03f0*/ ISETP.GT.OR P0, PT, R6, c[0x0][0x168], !P1 ; /* 0x00005a0006007a0c */
/* 0x000fe20004f04670 */
/*0400*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x000fd800078e0204 */
/*0410*/ @P0 SEL R11, R2, R11, !P1 ; /* 0x0000000b020b0207 */
/* 0x000fca0004800000 */
/*0420*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101906 */
/*0430*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea4000c1e1900 */
/*0440*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x004fc80003f04270 */
/*0450*/ SEL R9, R8, c[0x0][0x168], !P0 ; /* 0x00005a0008097a07 */
/* 0x000fc80004000000 */
/*0460*/ ISETP.GE.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fc8000bf26270 */
/*0470*/ ISETP.GT.OR P0, PT, R8, c[0x0][0x168], !P1 ; /* 0x00005a0008007a0c */
/* 0x000fe40004f04670 */
/*0480*/ SEL R13, R2, R9, !P1 ; /* 0x00000009020d7207 */
/* 0x000fe20004800000 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fd400078e0206 */
/*04a0*/ @P0 STG.E [R6.64], R13 ; /* 0x0000000d06000986 */
/* 0x0003e8000c101906 */
/*04b0*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x004fc80003f04270 */
/*04d0*/ SEL R5, R10, c[0x0][0x168], !P0 ; /* 0x00005a000a057a07 */
/* 0x001fc80004000000 */
/*04e0*/ ISETP.GE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fc8000bf26270 */
/*04f0*/ ISETP.GT.OR P0, PT, R10, c[0x0][0x168], !P1 ; /* 0x00005a000a007a0c */
/* 0x000fe40004f04670 */
/*0500*/ SEL R11, R2, R5, !P1 ; /* 0x00000005020b7207 */
/* 0x000fe20004800000 */
/*0510*/ IMAD.WIDE R4, R0, 0x4, R8 ; /* 0x0000000400047825 */
/* 0x000fd400078e0208 */
/*0520*/ @P0 STG.E [R8.64], R11 ; /* 0x0000000b08000986 */
/* 0x0001e8000c101906 */
/*0530*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0550*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fe40007ffe000 */
/*0560*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x004fc80003f04270 */
/*0570*/ SEL R7, R10, c[0x0][0x168], !P0 ; /* 0x00005a000a077a07 */
/* 0x002fc80004000000 */
/*0580*/ ISETP.GE.AND P1, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fc8000bf26270 */
/*0590*/ ISETP.GT.OR P0, PT, R10, c[0x0][0x168], !P1 ; /* 0x00005a000a007a0c */
/* 0x000fe40004f04670 */
/*05a0*/ SEL R7, R2, R7, !P1 ; /* 0x0000000702077207 */
/* 0x000fd60004800000 */
/*05b0*/ @P0 STG.E [R4.64], R7 ; /* 0x0000000704000986 */
/* 0x0001e2000c101906 */
/*05c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*05d0*/ @!P0 BRA 0x370 ; /* 0xfffffd9000008947 */
/* 0x001fea000383ffff */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2x3Piii
.globl _Z2x3Piii
.p2align 8
.type _Z2x3Piii,@function
_Z2x3Piii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s6, s[0:1], 0xc
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_ashr_i32 s3, s2, 31
s_sub_i32 s8, 0, s1
s_lshl_b64 s[4:5], s[2:3], 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_7
.LBB0_3:
global_load_b32 v0, v[2:3], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 s1, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, s1
global_store_b32 v[2:3], v0, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v0, v[2:3], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, s8
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2x3Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2x3Piii, .Lfunc_end0-_Z2x3Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2x3Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2x3Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00138797_00000000-6_x3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z2x3PiiiPiii
.type _Z23__device_stub__Z2x3PiiiPiii, @function
_Z23__device_stub__Z2x3PiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2x3Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z2x3PiiiPiii, .-_Z23__device_stub__Z2x3PiiiPiii
.globl _Z2x3Piii
.type _Z2x3Piii, @function
_Z2x3Piii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2x3PiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2x3Piii, .-_Z2x3Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2x3Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2x3Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "x3.hip"
.globl _Z17__device_stub__x3Piii # -- Begin function _Z17__device_stub__x3Piii
.p2align 4, 0x90
.type _Z17__device_stub__x3Piii,@function
_Z17__device_stub__x3Piii: # @_Z17__device_stub__x3Piii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2x3Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z17__device_stub__x3Piii, .Lfunc_end0-_Z17__device_stub__x3Piii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2x3Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2x3Piii,@object # @_Z2x3Piii
.section .rodata,"a",@progbits
.globl _Z2x3Piii
.p2align 3, 0x0
_Z2x3Piii:
.quad _Z17__device_stub__x3Piii
.size _Z2x3Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2x3Piii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__x3Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2x3Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kRgb2CIELab(uchar4* inputImg, float4* outputImg, int width, int height)
{
int offsetBlock = blockIdx.x * blockDim.x + blockIdx.y * blockDim.y * width;
int offset = offsetBlock + threadIdx.x + threadIdx.y * width;
uchar4 nPixel=inputImg[offset];
float _b=(float)nPixel.x/255.0;
float _g=(float)nPixel.y/255.0;
float _r=(float)nPixel.z/255.0;
float x=_r*0.412453 +_g*0.357580 +_b*0.180423;
float y=_r*0.212671 +_g*0.715160 +_b*0.072169;
float z=_r*0.019334 +_g*0.119193 +_b*0.950227;
x/=0.950456;
float y3=exp(log(y)/3.0);
z/=1.088754;
float l,a,b;
x = x>0.008856 ? exp(log(x)/3.0) : (7.787*x+0.13793);
y = y>0.008856 ? y3 : 7.787*y+0.13793;
z = z>0.008856 ? z/=exp(log(z)/3.0) : (7.787*z+0.13793);
l = y>0.008856 ? (116.0*y3-16.0) : 903.3*y;
a=(x-y)*500.0;
b=(y-z)*200.0;
float4 fPixel;
fPixel.x=l;
fPixel.y=a;
fPixel.z=b;
outputImg[offset]=fPixel;
} | .file "tmpxft_001939c3_00000000-6_kRgb2CIELab.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii
.type _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii, @function
_Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kRgb2CIELabP6uchar4P6float4ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii, .-_Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii
.globl _Z11kRgb2CIELabP6uchar4P6float4ii
.type _Z11kRgb2CIELabP6uchar4P6float4ii, @function
_Z11kRgb2CIELabP6uchar4P6float4ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kRgb2CIELabP6uchar4P6float4ii, .-_Z11kRgb2CIELabP6uchar4P6float4ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11kRgb2CIELabP6uchar4P6float4ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kRgb2CIELabP6uchar4P6float4ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kRgb2CIELab(uchar4* inputImg, float4* outputImg, int width, int height)
{
int offsetBlock = blockIdx.x * blockDim.x + blockIdx.y * blockDim.y * width;
int offset = offsetBlock + threadIdx.x + threadIdx.y * width;
uchar4 nPixel=inputImg[offset];
float _b=(float)nPixel.x/255.0;
float _g=(float)nPixel.y/255.0;
float _r=(float)nPixel.z/255.0;
float x=_r*0.412453 +_g*0.357580 +_b*0.180423;
float y=_r*0.212671 +_g*0.715160 +_b*0.072169;
float z=_r*0.019334 +_g*0.119193 +_b*0.950227;
x/=0.950456;
float y3=exp(log(y)/3.0);
z/=1.088754;
float l,a,b;
x = x>0.008856 ? exp(log(x)/3.0) : (7.787*x+0.13793);
y = y>0.008856 ? y3 : 7.787*y+0.13793;
z = z>0.008856 ? z/=exp(log(z)/3.0) : (7.787*z+0.13793);
l = y>0.008856 ? (116.0*y3-16.0) : 903.3*y;
a=(x-y)*500.0;
b=(y-z)*200.0;
float4 fPixel;
fPixel.x=l;
fPixel.y=a;
fPixel.z=b;
outputImg[offset]=fPixel;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kRgb2CIELab(uchar4* inputImg, float4* outputImg, int width, int height)
{
int offsetBlock = blockIdx.x * blockDim.x + blockIdx.y * blockDim.y * width;
int offset = offsetBlock + threadIdx.x + threadIdx.y * width;
uchar4 nPixel=inputImg[offset];
float _b=(float)nPixel.x/255.0;
float _g=(float)nPixel.y/255.0;
float _r=(float)nPixel.z/255.0;
float x=_r*0.412453 +_g*0.357580 +_b*0.180423;
float y=_r*0.212671 +_g*0.715160 +_b*0.072169;
float z=_r*0.019334 +_g*0.119193 +_b*0.950227;
x/=0.950456;
float y3=exp(log(y)/3.0);
z/=1.088754;
float l,a,b;
x = x>0.008856 ? exp(log(x)/3.0) : (7.787*x+0.13793);
y = y>0.008856 ? y3 : 7.787*y+0.13793;
z = z>0.008856 ? z/=exp(log(z)/3.0) : (7.787*z+0.13793);
l = y>0.008856 ? (116.0*y3-16.0) : 903.3*y;
a=(x-y)*500.0;
b=(y-z)*200.0;
float4 fPixel;
fPixel.x=l;
fPixel.y=a;
fPixel.z=b;
outputImg[offset]=fPixel;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kRgb2CIELab(uchar4* inputImg, float4* outputImg, int width, int height)
{
int offsetBlock = blockIdx.x * blockDim.x + blockIdx.y * blockDim.y * width;
int offset = offsetBlock + threadIdx.x + threadIdx.y * width;
uchar4 nPixel=inputImg[offset];
float _b=(float)nPixel.x/255.0;
float _g=(float)nPixel.y/255.0;
float _r=(float)nPixel.z/255.0;
float x=_r*0.412453 +_g*0.357580 +_b*0.180423;
float y=_r*0.212671 +_g*0.715160 +_b*0.072169;
float z=_r*0.019334 +_g*0.119193 +_b*0.950227;
x/=0.950456;
float y3=exp(log(y)/3.0);
z/=1.088754;
float l,a,b;
x = x>0.008856 ? exp(log(x)/3.0) : (7.787*x+0.13793);
y = y>0.008856 ? y3 : 7.787*y+0.13793;
z = z>0.008856 ? z/=exp(log(z)/3.0) : (7.787*z+0.13793);
l = y>0.008856 ? (116.0*y3-16.0) : 903.3*y;
a=(x-y)*500.0;
b=(y-z)*200.0;
float4 fPixel;
fPixel.x=l;
fPixel.y=a;
fPixel.z=b;
outputImg[offset]=fPixel;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.globl _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.p2align 8
.type _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii,@function
_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
s_load_b64 s[2:3], s[0:1], 0x0
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_clause 0x2
global_load_u8 v4, v[2:3], off
global_load_u8 v5, v[2:3], off offset:1
global_load_u8 v6, v[2:3], off offset:2
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[2:3], v4
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[4:5], v5
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f64 v[8:9], null, 0x406fe000, 0x406fe000, v[2:3]
v_div_scale_f64 v[10:11], null, 0x406fe000, 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_scale_f64 v[12:13], null, 0x406fe000, 0x406fe000, v[6:7]
v_div_scale_f64 v[26:27], vcc_lo, v[2:3], 0x406fe000, v[2:3]
v_rcp_f64_e32 v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[16:17], v[10:11]
v_rcp_f64_e32 v[18:19], v[12:13]
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[22:23], -v[10:11], v[16:17], 1.0
v_fma_f64 v[24:25], -v[12:13], v[18:19], 1.0
v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[22:23], -v[10:11], v[16:17], 1.0
v_fma_f64 v[24:25], -v[12:13], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
v_div_scale_f64 v[20:21], s2, v[4:5], 0x406fe000, v[4:5]
v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
v_div_scale_f64 v[22:23], s3, v[6:7], 0x406fe000, v[6:7]
v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
v_mul_f64 v[24:25], v[26:27], v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[28:29], v[20:21], v[16:17]
v_mul_f64 v[30:31], v[22:23], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], -v[8:9], v[24:25], v[26:27]
v_fma_f64 v[10:11], -v[10:11], v[28:29], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], -v[12:13], v[30:31], v[22:23]
v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[24:25]
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0x4488c60d
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[10:11], v[10:11], v[16:17], v[28:29]
s_mov_b32 vcc_lo, s3
s_mov_b32 s3, 0x3fda65a1
v_div_fmas_f64 v[12:13], v[12:13], v[18:19], v[30:31]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[2:3], v[8:9], 0x406fe000, v[2:3]
v_div_fixup_f64 v[4:5], v[10:11], 0x406fe000, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[6:7], v[12:13], 0x406fe000, v[6:7]
v_cvt_f32_f64_e32 v8, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f32_f64_e32 v6, v[6:7]
v_cvt_f32_f64_e32 v7, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[8:9], v8
v_cvt_f64_f32_e32 v[4:5], v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[6:7], v7
v_mul_f64 v[2:3], v[4:5], s[2:3]
s_mov_b32 s3, 0x3fd6e297
s_mov_b32 s2, 0x396d0918
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[6:7], s[2:3], v[2:3]
s_mov_b32 s3, 0x3fc71819
s_mov_b32 s2, 0xd2391d58
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[8:9], s[2:3], v[2:3]
s_mov_b32 s3, 0x3fee6a22
s_mov_b32 s2, 0xb3892ee8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[10:11], null, s[2:3], s[2:3], v[2:3]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[2:3], s[2:3], v[2:3]
v_mul_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[10:11], s[2:3], v[2:3]
s_mov_b32 s3, 0x3f822318
s_mov_b32 s2, 0x32fcac8e
v_cvt_f32_f64_e32 v12, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[10:11], v12
v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[10:11]
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_mov_b32 s5, 0x3fc1a7b0
s_mov_b32 s4, 0xb3919264
s_mov_b32 s7, 0x401f25e3
s_mov_b32 s6, 0x53f7ced9
s_delay_alu instid0(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[10:11], s[6:7], s[4:5]
s_and_not1_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v12
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
s_mov_b32 s7, 0x3e5ade15
s_mov_b32 s6, 0x6a5dcb37
v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v12, v2
v_log_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x3f317217, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, v2, 0x3f317217, -v3
v_fmamk_f32 v10, v2, 0x3377d1cf, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v3, v3, v10
v_cndmask_b32_e64 v10, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v10
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, 0x40080000, 0x40080000, v[2:3]
v_div_scale_f64 v[16:17], vcc_lo, v[2:3], 0x40080000, v[2:3]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_mul_f64 v[14:15], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[10:11], 0x40080000, v[2:3]
v_mul_f64 v[10:11], v[2:3], s[4:5]
s_mov_b32 s5, 0xbfe62e42
s_mov_b32 s4, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[10:11], v[10:11]
v_fma_f64 v[12:13], v[10:11], s[4:5], v[2:3]
s_mov_b32 s5, 0xbc7abc9e
s_mov_b32 s4, 0x3b39803f
v_cvt_i32_f64_e32 v16, v[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[12:13], v[10:11], s[4:5], v[12:13]
s_mov_b32 s5, 0x3e928af3
s_mov_b32 s4, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], s[6:7], s[4:5]
s_mov_b32 s5, 0x3ec71dee
s_mov_b32 s4, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3efa0199
s_mov_b32 s4, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3f2a01a0
s_mov_b32 s4, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3f56c16c
s_mov_b32 s4, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3f811111
s_mov_b32 s4, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fa55555
s_mov_b32 s4, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fc55555
s_mov_b32 s4, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fe00000
s_mov_b32 s4, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], 1.0
v_fma_f64 v[10:11], v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[10:11], v[10:11], v16
v_cndmask_b32_e32 v11, 0x7ff00000, v11, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v10, vcc_lo
v_cndmask_b32_e64 v3, 0, v11, s2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0x3fcb38cd
s_mov_b32 s2, 0xa6e75ff6
s_mov_b32 s5, 0x3e5ade15
v_mul_f64 v[10:11], v[4:5], s[2:3]
s_mov_b32 s3, 0x3fe6e297
s_mov_b32 s2, 0x396d0918
s_mov_b32 s4, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], v[6:7], s[2:3], v[10:11]
s_mov_b32 s3, 0x3fb279aa
s_mov_b32 s2, 0xe6c8f755
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[8:9], s[2:3], v[10:11]
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s2, 0x652b82fe
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v20, v[10:11]
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v20
v_cndmask_b32_e64 v10, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v20, v10
v_log_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, 0x3f317217, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v10, 0x3f317217, -v11
v_fmamk_f32 v12, v10, 0x3377d1cf, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v11, v11, v12
v_cndmask_b32_e64 v12, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v10|
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v10, v12
v_cvt_f64_f32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[12:13], null, 0x40080000, 0x40080000, v[10:11]
v_div_scale_f64 v[18:19], vcc_lo, v[10:11], 0x40080000, v[10:11]
v_rcp_f64_e32 v[14:15], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_mul_f64 v[16:17], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[10:11], v[12:13], 0x40080000, v[10:11]
v_mul_f64 v[12:13], v[10:11], s[2:3]
s_mov_b32 s3, 0xbfe62e42
s_mov_b32 s2, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[12:13], v[12:13]
v_fma_f64 v[14:15], v[12:13], s[2:3], v[10:11]
s_mov_b32 s3, 0xbc7abc9e
s_mov_b32 s2, 0x3b39803f
v_cvt_i32_f64_e32 v18, v[12:13]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[14:15], v[12:13], s[2:3], v[14:15]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], s[4:5], s[2:3]
s_mov_b32 s3, 0x3ec71dee
s_mov_b32 s2, 0x623fde64
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
s_mov_b32 s3, 0x3f2a01a0
s_mov_b32 s2, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
s_mov_b32 s3, 0x3fc55555
s_mov_b32 s2, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[10:11]
v_cvt_f64_f32_e32 v[10:11], v20
s_mov_b32 s3, 0x3f822318
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], 1.0
v_fma_f64 v[12:13], v[14:15], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[12:13], v[12:13], v18
v_cndmask_b32_e32 v13, 0x7ff00000, v13, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cndmask_b32_e64 v13, 0, v13, s2
s_mov_b32 s2, 0x32fcac8e
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v13, v[12:13]
v_mov_b32_e32 v12, v13
v_cmpx_nlt_f64_e32 s[2:3], v[10:11]
s_mov_b32 s7, 0x3fc1a7b0
s_mov_b32 s6, 0xb3919264
s_mov_b32 s9, 0x401f25e3
s_mov_b32 s8, 0x53f7ced9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], s[8:9], s[6:7]
v_cvt_f32_f64_e32 v12, v[10:11]
s_or_b32 exec_lo, exec_lo, s4
s_mov_b32 s5, 0x3f93cc4a
s_mov_b32 s4, 0xc6cdaf4b
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_f64 v[4:5], v[4:5], s[4:5]
s_mov_b32 s5, 0x3fbe836e
s_mov_b32 s4, 0xb4e98138
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[4:5], v[6:7], s[4:5], v[4:5]
s_mov_b32 s5, 0x3fee6842
s_mov_b32 s4, 0x7418d691
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[4:5], v[8:9], s[4:5], v[4:5]
s_mov_b32 s5, 0x3ff16b89
s_mov_b32 s4, 0x50763a19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v4, v[4:5]
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, s[4:5], s[4:5], v[4:5]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[4:5], s[4:5], v[4:5]
v_mul_f64 v[14:15], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[14:15], v[10:11]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], s[4:5], v[4:5]
v_cvt_f32_f64_e32 v8, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v8
v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_mov_b32 s5, 0x3fc1a7b0
s_mov_b32 s4, 0xb3919264
s_mov_b32 s7, 0x401f25e3
s_mov_b32 s6, 0x53f7ced9
s_delay_alu instid0(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], s[6:7], s[4:5]
s_and_not1_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v8
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
s_mov_b32 s7, 0x3e5ade15
s_mov_b32 s6, 0x6a5dcb37
v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v8, v6
v_log_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x3f317217, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v6, 0x3f317217, -v7
v_fmamk_f32 v8, v6, 0x3377d1cf, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v7, v7, v8
v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v8
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, 0x40080000, 0x40080000, v[6:7]
v_div_scale_f64 v[16:17], vcc_lo, v[6:7], 0x40080000, v[6:7]
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
v_mul_f64 v[14:15], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[14:15], v[16:17]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[8:9], 0x40080000, v[6:7]
v_mul_f64 v[8:9], v[6:7], s[4:5]
s_mov_b32 s5, 0xbfe62e42
s_mov_b32 s4, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[6:7]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[8:9], v[8:9]
v_fma_f64 v[10:11], v[8:9], s[4:5], v[6:7]
s_mov_b32 s5, 0xbc7abc9e
s_mov_b32 s4, 0x3b39803f
v_cvt_i32_f64_e32 v16, v[8:9]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], s[4:5], v[10:11]
s_mov_b32 s5, 0x3e928af3
s_mov_b32 s4, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], s[6:7], s[4:5]
s_mov_b32 s5, 0x3ec71dee
s_mov_b32 s4, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3efa0199
s_mov_b32 s4, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3f2a01a0
s_mov_b32 s4, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3f56c16c
s_mov_b32 s4, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3f811111
s_mov_b32 s4, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fa55555
s_mov_b32 s4, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fc55555
s_mov_b32 s4, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fe00000
s_mov_b32 s4, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], 1.0
v_fma_f64 v[8:9], v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[8:9], v[8:9], v16
v_cndmask_b32_e32 v9, 0x7ff00000, v9, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, 0, v8, vcc_lo
v_cndmask_b32_e64 v7, 0, v9, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[6:7], v[4:5]
v_mul_f64 v[16:17], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[8:9], v[6:7], v[4:5]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
v_cvt_f64_f32_e32 v[8:9], v12
s_mov_b32 s3, 0x3f822318
s_mov_b32 s2, 0x32fcac8e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[8:9]
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_mov_b32 s5, 0x408c3a66
s_mov_b32 s4, 0x66666666
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_f64 v[4:5], v[8:9], s[4:5]
s_and_not1_saveexec_b32 s2, s2
v_cvt_f64_f32_e32 v[4:5], v13
s_mov_b32 s4, 0
s_mov_b32 s5, 0x405d0000
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[4:5], v[4:5], s[4:5], 0xc0300000
s_or_b32 exec_lo, exec_lo, s2
v_cvt_f32_f64_e32 v3, v[2:3]
v_cvt_f32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[4:5]
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 4, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_dual_sub_f32 v3, v3, v12 :: v_dual_sub_f32 v4, v12, v6
v_mul_f32_e32 v3, 0x43fa0000, v3
s_delay_alu instid0(VALU_DEP_2)
v_mul_f32_e32 v4, 0x43480000, v4
global_store_b96 v[0:1], v[2:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, .Lfunc_end0-_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kRgb2CIELab(uchar4* inputImg, float4* outputImg, int width, int height)
{
int offsetBlock = blockIdx.x * blockDim.x + blockIdx.y * blockDim.y * width;
int offset = offsetBlock + threadIdx.x + threadIdx.y * width;
uchar4 nPixel=inputImg[offset];
float _b=(float)nPixel.x/255.0;
float _g=(float)nPixel.y/255.0;
float _r=(float)nPixel.z/255.0;
float x=_r*0.412453 +_g*0.357580 +_b*0.180423;
float y=_r*0.212671 +_g*0.715160 +_b*0.072169;
float z=_r*0.019334 +_g*0.119193 +_b*0.950227;
x/=0.950456;
float y3=exp(log(y)/3.0);
z/=1.088754;
float l,a,b;
x = x>0.008856 ? exp(log(x)/3.0) : (7.787*x+0.13793);
y = y>0.008856 ? y3 : 7.787*y+0.13793;
z = z>0.008856 ? z/=exp(log(z)/3.0) : (7.787*z+0.13793);
l = y>0.008856 ? (116.0*y3-16.0) : 903.3*y;
a=(x-y)*500.0;
b=(y-z)*200.0;
float4 fPixel;
fPixel.x=l;
fPixel.y=a;
fPixel.z=b;
outputImg[offset]=fPixel;
} | .text
.file "kRgb2CIELab.hip"
.globl _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii # -- Begin function _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.p2align 4, 0x90
.type _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii,@function
_Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii: # @_Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, .Lfunc_end0-_Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii,@object # @_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.section .rodata,"a",@progbits
.globl _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.p2align 3, 0x0
_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii:
.quad _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.size _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001939c3_00000000-6_kRgb2CIELab.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii
.type _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii, @function
_Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kRgb2CIELabP6uchar4P6float4ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii, .-_Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii
.globl _Z11kRgb2CIELabP6uchar4P6float4ii
.type _Z11kRgb2CIELabP6uchar4P6float4ii, @function
_Z11kRgb2CIELabP6uchar4P6float4ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z11kRgb2CIELabP6uchar4P6float4iiP6uchar4P6float4ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kRgb2CIELabP6uchar4P6float4ii, .-_Z11kRgb2CIELabP6uchar4P6float4ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11kRgb2CIELabP6uchar4P6float4ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kRgb2CIELabP6uchar4P6float4ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kRgb2CIELab.hip"
.globl _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii # -- Begin function _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.p2align 4, 0x90
.type _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii,@function
_Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii: # @_Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, .Lfunc_end0-_Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii,@object # @_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.section .rodata,"a",@progbits
.globl _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.p2align 3, 0x0
_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii:
.quad _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.size _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kRgb2CIELabP15HIP_vector_typeIhLj4EEPS_IfLj4EEii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void PictureKernell(unsigned char * d_Pin, unsigned char * d_Pout, int n, int m ){
int Row = blockIdx.y*blockDim.y + threadIdx.y;
int Col = blockIdx.x*blockDim.x + threadIdx.x;
if ((Row < m)&&(Col < n)){
d_Pout[Row*n + Col] = 2*d_Pin[Row*n+Col];
}
} | code for sm_80
Function : _Z14PictureKernellPhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], R3 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*00d0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0100*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe200007fe4ff */
/*0120*/ IMAD.SHL.U32 R7, R2, 0x2, RZ ; /* 0x0000000202077824 */
/* 0x004fca00078e00ff */
/*0130*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void PictureKernell(unsigned char * d_Pin, unsigned char * d_Pout, int n, int m ){
int Row = blockIdx.y*blockDim.y + threadIdx.y;
int Col = blockIdx.x*blockDim.x + threadIdx.x;
if ((Row < m)&&(Col < n)){
d_Pout[Row*n + Col] = 2*d_Pin[Row*n+Col];
}
} | .file "tmpxft_0013a912_00000000-6_PictureKernell.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii
.type _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii, @function
_Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14PictureKernellPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii, .-_Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii
.globl _Z14PictureKernellPhS_ii
.type _Z14PictureKernellPhS_ii, @function
_Z14PictureKernellPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14PictureKernellPhS_ii, .-_Z14PictureKernellPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14PictureKernellPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14PictureKernellPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void PictureKernell(unsigned char * d_Pin, unsigned char * d_Pout, int n, int m ){
int Row = blockIdx.y*blockDim.y + threadIdx.y;
int Col = blockIdx.x*blockDim.x + threadIdx.x;
if ((Row < m)&&(Col < n)){
d_Pout[Row*n + Col] = 2*d_Pin[Row*n+Col];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PictureKernell(unsigned char * d_Pin, unsigned char * d_Pout, int n, int m ){
int Row = blockIdx.y*blockDim.y + threadIdx.y;
int Col = blockIdx.x*blockDim.x + threadIdx.x;
if ((Row < m)&&(Col < n)){
d_Pout[Row*n + Col] = 2*d_Pin[Row*n+Col];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PictureKernell(unsigned char * d_Pin, unsigned char * d_Pout, int n, int m ){
int Row = blockIdx.y*blockDim.y + threadIdx.y;
int Col = blockIdx.x*blockDim.x + threadIdx.x;
if ((Row < m)&&(Col < n)){
d_Pout[Row*n + Col] = 2*d_Pin[Row*n+Col];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14PictureKernellPhS_ii
.globl _Z14PictureKernellPhS_ii
.p2align 8
.type _Z14PictureKernellPhS_ii,@function
_Z14PictureKernellPhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b16 v4, 1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14PictureKernellPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14PictureKernellPhS_ii, .Lfunc_end0-_Z14PictureKernellPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14PictureKernellPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14PictureKernellPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PictureKernell(unsigned char * d_Pin, unsigned char * d_Pout, int n, int m ){
int Row = blockIdx.y*blockDim.y + threadIdx.y;
int Col = blockIdx.x*blockDim.x + threadIdx.x;
if ((Row < m)&&(Col < n)){
d_Pout[Row*n + Col] = 2*d_Pin[Row*n+Col];
}
} | .text
.file "PictureKernell.hip"
.globl _Z29__device_stub__PictureKernellPhS_ii # -- Begin function _Z29__device_stub__PictureKernellPhS_ii
.p2align 4, 0x90
.type _Z29__device_stub__PictureKernellPhS_ii,@function
_Z29__device_stub__PictureKernellPhS_ii: # @_Z29__device_stub__PictureKernellPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14PictureKernellPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__PictureKernellPhS_ii, .Lfunc_end0-_Z29__device_stub__PictureKernellPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14PictureKernellPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14PictureKernellPhS_ii,@object # @_Z14PictureKernellPhS_ii
.section .rodata,"a",@progbits
.globl _Z14PictureKernellPhS_ii
.p2align 3, 0x0
_Z14PictureKernellPhS_ii:
.quad _Z29__device_stub__PictureKernellPhS_ii
.size _Z14PictureKernellPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14PictureKernellPhS_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__PictureKernellPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14PictureKernellPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14PictureKernellPhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], R3 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*00d0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0100*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe200007fe4ff */
/*0120*/ IMAD.SHL.U32 R7, R2, 0x2, RZ ; /* 0x0000000202077824 */
/* 0x004fca00078e00ff */
/*0130*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14PictureKernellPhS_ii
.globl _Z14PictureKernellPhS_ii
.p2align 8
.type _Z14PictureKernellPhS_ii,@function
_Z14PictureKernellPhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_lshlrev_b16 v4, 1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14PictureKernellPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14PictureKernellPhS_ii, .Lfunc_end0-_Z14PictureKernellPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14PictureKernellPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14PictureKernellPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a912_00000000-6_PictureKernell.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii
.type _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii, @function
_Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14PictureKernellPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii, .-_Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii
.globl _Z14PictureKernellPhS_ii
.type _Z14PictureKernellPhS_ii, @function
_Z14PictureKernellPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14PictureKernellPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14PictureKernellPhS_ii, .-_Z14PictureKernellPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14PictureKernellPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14PictureKernellPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PictureKernell.hip"
.globl _Z29__device_stub__PictureKernellPhS_ii # -- Begin function _Z29__device_stub__PictureKernellPhS_ii
.p2align 4, 0x90
.type _Z29__device_stub__PictureKernellPhS_ii,@function
_Z29__device_stub__PictureKernellPhS_ii: # @_Z29__device_stub__PictureKernellPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14PictureKernellPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__PictureKernellPhS_ii, .Lfunc_end0-_Z29__device_stub__PictureKernellPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14PictureKernellPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14PictureKernellPhS_ii,@object # @_Z14PictureKernellPhS_ii
.section .rodata,"a",@progbits
.globl _Z14PictureKernellPhS_ii
.p2align 3, 0x0
_Z14PictureKernellPhS_ii:
.quad _Z29__device_stub__PictureKernellPhS_ii
.size _Z14PictureKernellPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14PictureKernellPhS_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__PictureKernellPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14PictureKernellPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void f() {}
void kernel() { f<<<1, 1>>>(); } | code for sm_80
Function : _Z1fv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void f() {}
void kernel() { f<<<1, 1>>>(); } | .file "tmpxft_000a77a8_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1fvv
.type _Z19__device_stub__Z1fvv, @function
_Z19__device_stub__Z1fvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1fv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z19__device_stub__Z1fvv, .-_Z19__device_stub__Z1fvv
.globl _Z1fv
.type _Z1fv, @function
_Z1fv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1fvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z1fv, .-_Z1fv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z19__device_stub__Z1fvv
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1fv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1fv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void f() {}
void kernel() { f<<<1, 1>>>(); } | #include <hip/hip_runtime.h>
__global__ void f() {}
void kernel() { f<<<1, 1>>>(); } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void f() {}
void kernel() { f<<<1, 1>>>(); } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1fv
.globl _Z1fv
.p2align 8
.type _Z1fv,@function
_Z1fv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1fv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1fv, .Lfunc_end0-_Z1fv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1fv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z1fv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void f() {}
void kernel() { f<<<1, 1>>>(); } | .text
.file "test.hip"
.globl _Z16__device_stub__fv # -- Begin function _Z16__device_stub__fv
.p2align 4, 0x90
.type _Z16__device_stub__fv,@function
_Z16__device_stub__fv: # @_Z16__device_stub__fv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1fv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__fv, .Lfunc_end0-_Z16__device_stub__fv
.cfi_endproc
# -- End function
.globl _Z6kernelv # -- Begin function _Z6kernelv
.p2align 4, 0x90
.type _Z6kernelv,@function
_Z6kernelv: # @_Z6kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1fv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6kernelv, .Lfunc_end1-_Z6kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1fv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1fv,@object # @_Z1fv
.section .rodata,"a",@progbits
.globl _Z1fv
.p2align 3, 0x0
_Z1fv:
.quad _Z16__device_stub__fv
.size _Z1fv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1fv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__fv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1fv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1fv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1fv
.globl _Z1fv
.p2align 8
.type _Z1fv,@function
_Z1fv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1fv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1fv, .Lfunc_end0-_Z1fv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1fv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z1fv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a77a8_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1fvv
.type _Z19__device_stub__Z1fvv, @function
_Z19__device_stub__Z1fvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1fv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z19__device_stub__Z1fvv, .-_Z19__device_stub__Z1fvv
.globl _Z1fv
.type _Z1fv, @function
_Z1fv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1fvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z1fv, .-_Z1fv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z19__device_stub__Z1fvv
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1fv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1fv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z16__device_stub__fv # -- Begin function _Z16__device_stub__fv
.p2align 4, 0x90
.type _Z16__device_stub__fv,@function
_Z16__device_stub__fv: # @_Z16__device_stub__fv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1fv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__fv, .Lfunc_end0-_Z16__device_stub__fv
.cfi_endproc
# -- End function
.globl _Z6kernelv # -- Begin function _Z6kernelv
.p2align 4, 0x90
.type _Z6kernelv,@function
_Z6kernelv: # @_Z6kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1fv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6kernelv, .Lfunc_end1-_Z6kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1fv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1fv,@object # @_Z1fv
.section .rodata,"a",@progbits
.globl _Z1fv
.p2align 3, 0x0
_Z1fv:
.quad _Z16__device_stub__fv
.size _Z1fv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1fv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__fv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1fv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(cudaError_t err, const char* context) {
if (err != cudaSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< cudaGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, cudaMemcpyKind direction) {
CHECK(cudaMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=8;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
// int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=ic*step+ib*nd+ia;
// int j=jc*step+jb*nd+ja;
// 0<=ia<=nd, 0<=ja<=nd
// if ic>jc , then i>j
if(ic>jc){
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=0;
}
}
}
}else{
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ii=0; ii<nd; ii++){
int i=(ic*nd+ii)*nd+ia;
int j=(jc*nd+ii)*nd+ja;
x[ii]=data[k*new_ny +i];
y[ii]=data[k*new_ny +j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=v[ib][jb];
}
}
}
}
// result[i*ny+j]=temp;
}
__global__ void normalize(int ny, int nx, float*data, int step){
int i = blockIdx.x;
int j = threadIdx.x;
int row=i*step+j;
if (row<ny){
// printf("row is %d \n", row);
//for each row
float temp=0, avg=0, sqrtSqureSum=0;
for (int x=0; x<nx; ++x){
temp+=data[row*nx+x];
}
avg=temp/nx;
for (int x=0; x<nx; ++x){
data[row*nx+x]=data[row*nx+x]-avg;
}
for (int x=0; x<nx; ++x){
sqrtSqureSum+=powf(data[row*nx+x],2);
}
sqrtSqureSum=sqrtf(sqrtSqureSum);
for (int x=0; x<nx; ++x){
data[row*nx+x]/=sqrtSqureSum;
}
}
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*nx+j]:0.0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=8; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(cudaMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(cudaMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(cudaMalloc((void**)&rGPU,ny*ny*sizeof(float)));
cuda_memcpy(dGPU,data,ny*nx,cudaMemcpyHostToDevice);
{
normalize<<<divup(ny,step),step>>>(ny,nx,dGPU,step);
}
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(cudaGetLastError());
}
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(cudaGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, cudaMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(cudaFree(dGPU));
CHECK(cudaFree(padding));
CHECK(cudaFree(rGPU));
// delete[] normalized;
} | .file "tmpxft_000faf67_00000000-6_cp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4039:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.type _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, @function
_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi:
.LFB4061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13correlate_gpuiiPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4061:
.size _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, .-_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.globl _Z13correlate_gpuiiPKfPfi
.type _Z13correlate_gpuiiPKfPfi, @function
_Z13correlate_gpuiiPKfPfi:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _Z13correlate_gpuiiPKfPfi, .-_Z13correlate_gpuiiPKfPfi
.globl _Z31__device_stub__Z9normalizeiiPfiiiPfi
.type _Z31__device_stub__Z9normalizeiiPfiiiPfi, @function
_Z31__device_stub__Z9normalizeiiPfiiiPfi:
.LFB4063:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9normalizeiiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4063:
.size _Z31__device_stub__Z9normalizeiiPfiiiPfi, .-_Z31__device_stub__Z9normalizeiiPfiiiPfi
.globl _Z9normalizeiiPfi
.type _Z9normalizeiiPfi, @function
_Z9normalizeiiPfi:
.LFB4064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9normalizeiiPfiiiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4064:
.size _Z9normalizeiiPfi, .-_Z9normalizeiiPfi
.globl _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.type _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, @function
_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi:
.LFB4065:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17padding_transposeiiPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, .-_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.globl _Z17padding_transposeiiPKfPfi
.type _Z17padding_transposeiiPKfPfi, @function
_Z17padding_transposeiiPKfPfi:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z17padding_transposeiiPKfPfi, .-_Z17padding_transposeiiPKfPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17padding_transposeiiPKfPfi"
.LC1:
.string "_Z9normalizeiiPfi"
.LC2:
.string "_Z13correlate_gpuiiPKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4068:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17padding_transposeiiPKfPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9normalizeiiPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13correlate_gpuiiPKfPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.1,"aMS",@progbits,1
.LC3:
.string "CUDA error: "
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "cudaMemcpy(target, source, num * sizeof(T), direction)"
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.1
.LC5:
.string ": "
.section .text._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind,"axG",@progbits,_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind,comdat
.weak _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
.type _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind, @function
_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind:
.LFB4371:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
salq $2, %rdx
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %ebx
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4371:
.size _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind, .-_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "cudaMalloc((void**)&dGPU,ny*nx*sizeof(float))"
.align 8
.LC7:
.string "cudaMalloc((void**)&padding,new_ny*nx*sizeof(float))"
.align 8
.LC8:
.string "cudaMalloc((void**)&rGPU,ny*ny*sizeof(float))"
.section .rodata.str1.1
.LC9:
.string "cudaGetLastError()"
.LC10:
.string "cudaFree(dGPU)"
.LC11:
.string "cudaFree(padding)"
.LC12:
.string "cudaFree(rGPU)"
.text
.globl _Z9correlateiiPKfPf
.type _Z9correlateiiPKfPf, @function
_Z9correlateiiPKfPf:
.LFB4036:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, 8(%rsp)
movq %rcx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leal 126(%rdi), %ebp
movl %edi, %eax
addl $63, %eax
cmovns %eax, %ebp
movl %ebp, %r15d
sarl $6, %r15d
andl $-64, %ebp
movq $0, 40(%rsp)
movl %edi, %r13d
imull %esi, %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movq $0, 48(%rsp)
movl %r12d, %esi
imull %ebp, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L48
movq $0, 56(%rsp)
movl %ebx, %r14d
imull %ebx, %r14d
movslq %r14d, %r14
leaq 0(,%r14,4), %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, 28(%rsp)
testl %eax, %eax
jne .L49
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
movl $64, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r15d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
movl $64, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L38:
call cudaGetLastError@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L52
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl %r15d, 76(%rsp)
movl %r15d, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L40:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
movl $2, %ecx
movq %r14, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L56
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L57
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %eax, %r14d
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L48:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L49:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl 28(%rsp), %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L50:
movl $64, %ecx
movq 40(%rsp), %rdx
movl %r12d, %esi
movl %ebx, %edi
call _Z31__device_stub__Z9normalizeiiPfiiiPfi
jmp .L37
.L51:
movl %ebp, %r8d
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movl %r12d, %esi
movl %ebx, %edi
call _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
jmp .L38
.L52:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %ebp, %r8d
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl %r12d, %esi
movl %ebx, %edi
call _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
jmp .L40
.L54:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L55:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L56:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L57:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4036:
.size _Z9correlateiiPKfPf, .-_Z9correlateiiPKfPf
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(cudaError_t err, const char* context) {
if (err != cudaSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< cudaGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, cudaMemcpyKind direction) {
CHECK(cudaMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=8;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
// int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=ic*step+ib*nd+ia;
// int j=jc*step+jb*nd+ja;
// 0<=ia<=nd, 0<=ja<=nd
// if ic>jc , then i>j
if(ic>jc){
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=0;
}
}
}
}else{
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ii=0; ii<nd; ii++){
int i=(ic*nd+ii)*nd+ia;
int j=(jc*nd+ii)*nd+ja;
x[ii]=data[k*new_ny +i];
y[ii]=data[k*new_ny +j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=v[ib][jb];
}
}
}
}
// result[i*ny+j]=temp;
}
__global__ void normalize(int ny, int nx, float*data, int step){
int i = blockIdx.x;
int j = threadIdx.x;
int row=i*step+j;
if (row<ny){
// printf("row is %d \n", row);
//for each row
float temp=0, avg=0, sqrtSqureSum=0;
for (int x=0; x<nx; ++x){
temp+=data[row*nx+x];
}
avg=temp/nx;
for (int x=0; x<nx; ++x){
data[row*nx+x]=data[row*nx+x]-avg;
}
for (int x=0; x<nx; ++x){
sqrtSqureSum+=powf(data[row*nx+x],2);
}
sqrtSqureSum=sqrtf(sqrtSqureSum);
for (int x=0; x<nx; ++x){
data[row*nx+x]/=sqrtSqureSum;
}
}
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*nx+j]:0.0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=8; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(cudaMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(cudaMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(cudaMalloc((void**)&rGPU,ny*ny*sizeof(float)));
cuda_memcpy(dGPU,data,ny*nx,cudaMemcpyHostToDevice);
{
normalize<<<divup(ny,step),step>>>(ny,nx,dGPU,step);
}
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(cudaGetLastError());
}
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(cudaGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, cudaMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(cudaFree(dGPU));
CHECK(cudaFree(padding));
CHECK(cudaFree(rGPU));
// delete[] normalized;
} | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(hipError_t err, const char* context) {
if (err != hipSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< hipGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, hipMemcpyKind direction) {
CHECK(hipMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=8;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
// int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=ic*step+ib*nd+ia;
// int j=jc*step+jb*nd+ja;
// 0<=ia<=nd, 0<=ja<=nd
// if ic>jc , then i>j
if(ic>jc){
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=0;
}
}
}
}else{
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ii=0; ii<nd; ii++){
int i=(ic*nd+ii)*nd+ia;
int j=(jc*nd+ii)*nd+ja;
x[ii]=data[k*new_ny +i];
y[ii]=data[k*new_ny +j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=v[ib][jb];
}
}
}
}
// result[i*ny+j]=temp;
}
__global__ void normalize(int ny, int nx, float*data, int step){
int i = blockIdx.x;
int j = threadIdx.x;
int row=i*step+j;
if (row<ny){
// printf("row is %d \n", row);
//for each row
float temp=0, avg=0, sqrtSqureSum=0;
for (int x=0; x<nx; ++x){
temp+=data[row*nx+x];
}
avg=temp/nx;
for (int x=0; x<nx; ++x){
data[row*nx+x]=data[row*nx+x]-avg;
}
for (int x=0; x<nx; ++x){
sqrtSqureSum+=powf(data[row*nx+x],2);
}
sqrtSqureSum=sqrtf(sqrtSqureSum);
for (int x=0; x<nx; ++x){
data[row*nx+x]/=sqrtSqureSum;
}
}
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*nx+j]:0.0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=8; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(hipMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(hipMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(hipMalloc((void**)&rGPU,ny*ny*sizeof(float)));
cuda_memcpy(dGPU,data,ny*nx,hipMemcpyHostToDevice);
{
normalize<<<divup(ny,step),step>>>(ny,nx,dGPU,step);
}
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(hipGetLastError());
}
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(hipGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, hipMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(hipFree(dGPU));
CHECK(hipFree(padding));
CHECK(hipFree(rGPU));
// delete[] normalized;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(hipError_t err, const char* context) {
if (err != hipSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< hipGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, hipMemcpyKind direction) {
CHECK(hipMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=8;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
// int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=ic*step+ib*nd+ia;
// int j=jc*step+jb*nd+ja;
// 0<=ia<=nd, 0<=ja<=nd
// if ic>jc , then i>j
if(ic>jc){
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=0;
}
}
}
}else{
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ii=0; ii<nd; ii++){
int i=(ic*nd+ii)*nd+ia;
int j=(jc*nd+ii)*nd+ja;
x[ii]=data[k*new_ny +i];
y[ii]=data[k*new_ny +j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=v[ib][jb];
}
}
}
}
// result[i*ny+j]=temp;
}
__global__ void normalize(int ny, int nx, float*data, int step){
int i = blockIdx.x;
int j = threadIdx.x;
int row=i*step+j;
if (row<ny){
// printf("row is %d \n", row);
//for each row
float temp=0, avg=0, sqrtSqureSum=0;
for (int x=0; x<nx; ++x){
temp+=data[row*nx+x];
}
avg=temp/nx;
for (int x=0; x<nx; ++x){
data[row*nx+x]=data[row*nx+x]-avg;
}
for (int x=0; x<nx; ++x){
sqrtSqureSum+=powf(data[row*nx+x],2);
}
sqrtSqureSum=sqrtf(sqrtSqureSum);
for (int x=0; x<nx; ++x){
data[row*nx+x]/=sqrtSqureSum;
}
}
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*nx+j]:0.0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=8; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(hipMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(hipMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(hipMalloc((void**)&rGPU,ny*ny*sizeof(float)));
cuda_memcpy(dGPU,data,ny*nx,hipMemcpyHostToDevice);
{
normalize<<<divup(ny,step),step>>>(ny,nx,dGPU,step);
}
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(hipGetLastError());
}
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(hipGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, hipMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(hipFree(dGPU));
CHECK(hipFree(padding));
CHECK(hipFree(rGPU));
// delete[] normalized;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13correlate_gpuiiPKfPfi
.globl _Z13correlate_gpuiiPKfPfi
.p2align 8
.type _Z13correlate_gpuiiPKfPfi,@function
_Z13correlate_gpuiiPKfPfi:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v21, 0x3ff, v0
v_bfe_u32 v20, v0, 10, 10
s_cmp_le_i32 s14, s15
s_mov_b32 s4, -1
s_cbranch_scc0 .LBB0_21
v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
s_mov_b32 s4, 0
.LBB0_2:
s_mov_b32 s5, 0
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s5, v0
s_add_i32 s5, s5, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 32
scratch_store_b32 v2, v1, off
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v0, 32, v0
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 8
s_cbranch_scc0 .LBB0_2
s_load_b32 s7, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_14
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s8, s[0:1], 0x18
v_lshl_add_u32 v22, s15, 6, v20
v_lshl_add_u32 v23, s14, 6, v21
s_mov_b32 s9, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v16, v23
v_mov_b32_e32 v18, v22
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v19, 31, v18
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
v_lshlrev_b64 v[24:25], 2, v[16:17]
v_add_nc_u32_e32 v16, 8, v16
s_cmp_lg_u32 s0, 8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v24, vcc_lo, s4, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
global_load_b32 v17, v[24:25], off
v_lshlrev_b64 v[24:25], 2, v[18:19]
v_add_nc_u32_e32 v18, 8, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v24, vcc_lo, s4, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
s_waitcnt vmcnt(0)
v_movreld_b32_e32 v0, v17
global_load_b32 v17, v[24:25], off
s_waitcnt vmcnt(0)
v_movreld_b32_e32 v8, v17
s_cbranch_scc1 .LBB0_8
v_mov_b32_e32 v16, 16
s_mov_b32 s10, 0
.p2align 6
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 m0, s10
v_mov_b32_e32 v18, v16
v_movrels_b32_e32 v17, v0
s_mov_b64 s[0:1], 0
.LBB0_11:
scratch_load_b32 v19, v18, off
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
v_movrels_b32_e32 v24, v8
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v19, v17, v24
scratch_store_b32 v18, v19, off
v_add_nc_u32_e32 v18, 4, v18
s_cbranch_scc0 .LBB0_11
v_add_nc_u32_e32 v16, 32, v16
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, 8
s_cbranch_scc0 .LBB0_10
v_add_nc_u32_e32 v22, s8, v22
v_add_nc_u32_e32 v23, s8, v23
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s7
s_cbranch_scc0 .LBB0_7
.LBB0_14:
v_lshl_add_u32 v0, s14, 6, v21
v_lshl_add_u32 v2, s15, 6, v20
v_mov_b32_e32 v3, 16
s_lshl_b32 s1, s6, 3
s_mov_b32 s4, 0
v_mul_lo_u32 v1, s6, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_16
.p2align 6
.LBB0_15:
v_add_nc_u32_e32 v1, s1, v1
v_add_nc_u32_e32 v3, 32, v3
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 8
s_cbranch_scc1 .LBB0_20
.LBB0_16:
v_lshl_add_u32 v4, s4, 3, v0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s6, v4
v_mov_b32_e32 v4, v2
s_branch .LBB0_18
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v4, 8, v4
s_add_i32 s5, s5, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 32
s_cbranch_scc1 .LBB0_15
.LBB0_18:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s6, v4
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB0_17
v_add_nc_u32_e32 v5, s5, v3
scratch_load_b32 v7, v5, off
v_add_nc_u32_e32 v5, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v7, off
s_branch .LBB0_17
.LBB0_20:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, 0
.LBB0_21:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_28
v_lshl_add_u32 v0, s14, 6, v21
v_lshl_add_u32 v2, s15, 6, v20
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s1, s6, 3
s_mov_b32 s4, 0
v_mul_lo_u32 v1, s6, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_24
.p2align 6
.LBB0_23:
v_add_nc_u32_e32 v1, s1, v1
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 8
s_cbranch_scc1 .LBB0_28
.LBB0_24:
v_lshl_add_u32 v4, s4, 3, v0
s_mov_b32 s5, 8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s6, v4
v_mov_b32_e32 v4, v2
s_branch .LBB0_26
.p2align 6
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v4, 8, v4
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB0_23
.LBB0_26:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s6, v4
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB0_25
v_add_nc_u32_e32 v5, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_store_b32 v[5:6], v3, off
s_branch .LBB0_25
.LBB0_28:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13correlate_gpuiiPKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 272
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13correlate_gpuiiPKfPfi, .Lfunc_end0-_Z13correlate_gpuiiPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9normalizeiiPfi
.globl _Z9normalizeiiPfi
.p2align 8
.type _Z9normalizeiiPfi,@function
_Z9normalizeiiPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_15
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v1, s4
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v3, 0
s_mov_b32 s0, s4
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
.LBB1_3:
global_load_b32 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
s_cbranch_scc0 .LBB1_3
s_cmp_lt_i32 s4, 1
s_cbranch_scc0 .LBB1_6
s_branch .LBB1_8
.LBB1_5:
v_mov_b32_e32 v3, 0
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_8
.LBB1_6:
v_cvt_f32_i32_e32 v4, s4
s_mov_b32 s0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v4, v4, v3
v_div_scale_f32 v6, vcc_lo, v3, v4, v3
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v1, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v5, v2
v_mul_f32_e32 v5, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v1, v5, v6
v_fmac_f32_e32 v5, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v1, v5, v6
v_ashrrev_i32_e32 v1, 31, v0
v_div_fmas_f32 v5, v6, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_div_fixup_f32 v3, v5, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
.LBB1_7:
global_load_b32 v4, v[1:2], off
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v4, v3
global_store_b32 v[1:2], v4, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cbranch_scc0 .LBB1_7
.LBB1_8:
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_12
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v3, 0
s_mov_b32 s5, 0x3e76c4e1
s_mov_b32 s6, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
.LBB1_10:
global_load_b32 v4, v[1:2], off
s_add_i32 s6, s6, -1
s_waitcnt vmcnt(0)
v_frexp_mant_f32_e64 v5, |v4|
v_frexp_exp_i32_f32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f32 v5, v5, v7
v_cvt_f32_i32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, 1.0, v5
v_dual_add_f32 v8, -1.0, v5 :: v_dual_mul_f32 v11, 0x3f317218, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, -1.0, v7
v_sub_f32_e32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, v6, 0x3f317218, -v11
v_fmac_f32_e32 v10, 0xb102e308, v6
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v12
v_fma_f32 v7, v12, v7, -v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v12, v5
v_add_f32_e32 v5, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v13, v8, v5
v_sub_f32_e32 v8, v8, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v5, v6 :: v_dual_sub_f32 v5, v8, v5
v_sub_f32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v6, v5
v_add_f32_e32 v5, v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v9, v5
v_add_f32_e32 v6, v12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v6, v12
v_dual_mul_f32 v8, v6, v6 :: v_dual_sub_f32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v7, v6, v6, -v8
v_ldexp_f32 v9, v6, 1
v_add_f32_e32 v12, v5, v5
v_ldexp_f32 v13, v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v12
v_add_f32_e32 v12, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v14, s5, v12, 0x3e91f4c4
v_fmaak_f32 v14, v12, v14, 0x3ecccdef
v_sub_f32_e32 v8, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v15, v6, v12 :: v_dual_mul_f32 v16, v12, v14
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v12, v6, -v15
v_fmac_f32_e32 v8, v12, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v12, v14, -v16
v_fmac_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v14
v_add_f32_e32 v7, v16, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v14, v7, v16
v_dual_add_f32 v6, v15, v8 :: v_dual_sub_f32 v5, v5, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v6, v15
v_add_f32_e32 v15, 0x3f2aaaaa, v7
v_dual_add_f32 v5, 0x31739010, v5 :: v_dual_sub_f32 v8, v8, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, 0xbf2aaaaa, v15
v_sub_f32_e32 v7, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v7, v15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v15, v7
v_dual_mul_f32 v14, v6, v7 :: v_dual_add_f32 v5, v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v6, v7, -v14
v_fmac_f32_e32 v12, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v8, v7
v_add_f32_e32 v5, v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v5, v14
v_dual_add_f32 v6, v9, v5 :: v_dual_sub_f32 v7, v12, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v6, v9 :: v_dual_add_f32 v7, v13, v7
v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v7, v5
v_add_f32_e32 v9, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v8, v11 :: v_dual_sub_f32 v6, v9, v6
v_dual_sub_f32 v7, v10, v7 :: v_dual_add_f32 v10, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v11, v10, v8
v_dual_sub_f32 v5, v5, v6 :: v_dual_sub_f32 v6, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v8, v6 :: v_dual_sub_f32 v9, v9, v11
v_dual_add_f32 v11, v7, v5 :: v_dual_add_f32 v6, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v11, v7
v_add_f32_e32 v6, v11, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v11, v8
v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v9
v_sub_f32_e32 v9, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v6, v9 :: v_dual_add_f32 v5, v5, v7
v_add_f32_e32 v5, v5, v6
v_cndmask_b32_e64 v6, 2.0, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v8, v5
v_dual_sub_f32 v8, v7, v8 :: v_dual_mul_f32 v9, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v8
v_fma_f32 v7, v6, v7, -v9
v_cmp_class_f32_e64 vcc_lo, v9, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v5
v_add_f32_e32 v5, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, v5, v9, vcc_lo
v_sub_f32_e32 v5, v5, v9
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v7, v5
v_cndmask_b32_e64 v10, 0, 0x37000000, vcc_lo
v_sub_f32_e32 v11, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, 0x3fb8aa3b, v11
v_fma_f32 v13, v11, 0x3fb8aa3b, -v12
v_rndne_f32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v13, 0x32a5705f, v11 :: v_dual_sub_f32 v12, v12, v14
v_cvt_i32_f32_e32 v9, v14
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v8|
v_trunc_f32_e32 v8, v6
v_add_f32_e32 v12, v12, v13
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_exp_f32_e32 v12, v12
v_add_f32_e32 v5, v10, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v7, v12, v9
v_mul_f32_e32 v9, 0.5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
v_trunc_f32_e32 v12, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v8, v6
v_cmp_neq_f32_e64 s0, v12, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v5, v7, v5, v7
v_cmp_eq_f32_e64 s1, 0x7f800000, v7
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, 1.0, v4, s0
v_cndmask_b32_e64 v5, v5, v7, s1
v_cmp_eq_f32_e64 s1, 0, v4
v_cndmask_b32_e64 v7, 0, v4, s0
v_cmp_class_f32_e64 s0, v4, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_bfi_b32 v5, 0x7fffffff, v5, v6
v_cndmask_b32_e64 v6, 0x7f800000, 0, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v8, 0x7fc00000, v5, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v4
v_bfi_b32 v6, 0x7fffffff, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_or_b32 vcc_lo, s1, s0
s_cmp_eq_u32 s6, 0
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_f32_e32 v3, v3, v4
s_cbranch_scc0 .LBB1_10
s_cmp_lt_i32 s4, 1
s_cbranch_scc0 .LBB1_13
s_branch .LBB1_15
.LBB1_12:
v_mov_b32_e32 v3, 0
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_15
.LBB1_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_cndmask_b32_e32 v2, v3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v1
v_add_nc_u32_e32 v4, 1, v1
v_fma_f32 v5, -v3, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v1, v2
v_cmp_ge_f32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v3, s0
v_cmp_lt_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v1, v4, s0
v_ashrrev_i32_e32 v1, 31, v0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
.p2align 6
.LBB1_14:
global_load_b32 v3, v[0:1], off
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v2, v2, v3
v_div_scale_f32 v7, vcc_lo, v3, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v3, v4, v2, v3
global_store_b32 v[0:1], v3, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc1 .LBB1_14
.LBB1_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9normalizeiiPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9normalizeiiPfi, .Lfunc_end1-_Z9normalizeiiPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17padding_transposeiiPKfPfi
.globl _Z17padding_transposeiiPKfPfi
.p2align 8
.type _Z17padding_transposeiiPKfPfi,@function
_Z17padding_transposeiiPKfPfi:
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB2_7
s_clause 0x2
s_load_b32 s9, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, s15
s_mov_b32 s11, 0
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s15, s9
s_mul_i32 s9, s15, s3
s_cselect_b32 s10, -1, 0
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_2:
v_mad_u64_u32 v[3:4], null, v1, s8, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v2, off
s_load_b32 s15, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s15, s15, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s12, s15
s_cmp_ge_i32 s12, s3
s_cselect_b32 s15, -1, 0
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s15, s15, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s13, s13, s15
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s14, exec_lo, s13
s_or_b32 s11, s14, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB2_7
.LBB2_4:
v_add_nc_u32_e32 v1, s12, v0
s_or_b32 s13, s13, exec_lo
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_3
v_mov_b32_e32 v2, 0
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB2_2
v_add_nc_u32_e32 v2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_branch .LBB2_2
.LBB2_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17padding_transposeiiPKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17padding_transposeiiPKfPfi, .Lfunc_end2-_Z17padding_transposeiiPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13correlate_gpuiiPKfPfi
.private_segment_fixed_size: 272
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13correlate_gpuiiPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9normalizeiiPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9normalizeiiPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17padding_transposeiiPKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17padding_transposeiiPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(hipError_t err, const char* context) {
if (err != hipSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< hipGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, hipMemcpyKind direction) {
CHECK(hipMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=8;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
// int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=ic*step+ib*nd+ia;
// int j=jc*step+jb*nd+ja;
// 0<=ia<=nd, 0<=ja<=nd
// if ic>jc , then i>j
if(ic>jc){
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=0;
}
}
}
}else{
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ii=0; ii<nd; ii++){
int i=(ic*nd+ii)*nd+ia;
int j=(jc*nd+ii)*nd+ja;
x[ii]=data[k*new_ny +i];
y[ii]=data[k*new_ny +j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=(ic*nd+ib)*nd+ia;
int j=(jc*nd+jb)*nd+ja;
if(i<ny&&j<ny){
result[ny*i+j]=v[ib][jb];
}
}
}
}
// result[i*ny+j]=temp;
}
__global__ void normalize(int ny, int nx, float*data, int step){
int i = blockIdx.x;
int j = threadIdx.x;
int row=i*step+j;
if (row<ny){
// printf("row is %d \n", row);
//for each row
float temp=0, avg=0, sqrtSqureSum=0;
for (int x=0; x<nx; ++x){
temp+=data[row*nx+x];
}
avg=temp/nx;
for (int x=0; x<nx; ++x){
data[row*nx+x]=data[row*nx+x]-avg;
}
for (int x=0; x<nx; ++x){
sqrtSqureSum+=powf(data[row*nx+x],2);
}
sqrtSqureSum=sqrtf(sqrtSqureSum);
for (int x=0; x<nx; ++x){
data[row*nx+x]/=sqrtSqureSum;
}
}
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*nx+j]:0.0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=8; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(hipMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(hipMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(hipMalloc((void**)&rGPU,ny*ny*sizeof(float)));
cuda_memcpy(dGPU,data,ny*nx,hipMemcpyHostToDevice);
{
normalize<<<divup(ny,step),step>>>(ny,nx,dGPU,step);
}
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(hipGetLastError());
}
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(hipGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, hipMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(hipFree(dGPU));
CHECK(hipFree(padding));
CHECK(hipFree(rGPU));
// delete[] normalized;
} | .text
.file "cp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__correlate_gpuiiPKfPfi # -- Begin function _Z28__device_stub__correlate_gpuiiPKfPfi
.p2align 4, 0x90
.type _Z28__device_stub__correlate_gpuiiPKfPfi,@function
_Z28__device_stub__correlate_gpuiiPKfPfi: # @_Z28__device_stub__correlate_gpuiiPKfPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13correlate_gpuiiPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__correlate_gpuiiPKfPfi, .Lfunc_end0-_Z28__device_stub__correlate_gpuiiPKfPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__normalizeiiPfi # -- Begin function _Z24__device_stub__normalizeiiPfi
.p2align 4, 0x90
.type _Z24__device_stub__normalizeiiPfi,@function
_Z24__device_stub__normalizeiiPfi: # @_Z24__device_stub__normalizeiiPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizeiiPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__normalizeiiPfi, .Lfunc_end1-_Z24__device_stub__normalizeiiPfi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__padding_transposeiiPKfPfi # -- Begin function _Z32__device_stub__padding_transposeiiPKfPfi
.p2align 4, 0x90
.type _Z32__device_stub__padding_transposeiiPKfPfi,@function
_Z32__device_stub__padding_transposeiiPKfPfi: # @_Z32__device_stub__padding_transposeiiPKfPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17padding_transposeiiPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z32__device_stub__padding_transposeiiPKfPfi, .Lfunc_end2-_Z32__device_stub__padding_transposeiiPKfPfi
.cfi_endproc
# -- End function
.globl _Z9correlateiiPKfPf # -- Begin function _Z9correlateiiPKfPf
.p2align 4, 0x90
.type _Z9correlateiiPKfPf,@function
_Z9correlateiiPKfPf: # @_Z9correlateiiPKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r12
movq %rdx, 176(%rsp) # 8-byte Spill
movl %esi, %r13d
# kill: def $edi killed $edi def $rdi
leal 63(%rdi), %eax
leal 126(%rdi), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
movq $0, 24(%rsp)
movl %esi, %eax
movq %rdi, %rbp
imull %edi, %eax
movslq %eax, %rbx
leaq (,%rbx,4), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_ZL5check10hipError_tPKc.exit
movl %r14d, %eax
andl $-64, %eax
movq $0, 104(%rsp)
movq %rax, 168(%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
movl %r13d, %r15d
imull %r13d, %eax
movslq %eax, %rsi
shlq $2, %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_ZL5check10hipError_tPKc.exit45
movq %r12, 160(%rsp) # 8-byte Spill
movq $0, 96(%rsp)
movl %ebp, %eax
imull %eax, %eax
movq %rax, 152(%rsp) # 8-byte Spill
leaq (,%rax,4), %rsi
leaq 96(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_ZL5check10hipError_tPKc.exit47
sarl $6, %r14d
movabsq $4294967360, %r12 # imm = 0x100000040
movq 24(%rsp), %rdi
movq 176(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
movl %r14d, %ebx
leaq (%rbx,%r12), %rdi
addq $-64, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movl %r15d, %r14d
jne .LBB3_9
# %bb.8:
movq 24(%rsp), %rax
movl %ebp, 32(%rsp)
movl %r14d, 16(%rsp)
movq %rax, 88(%rsp)
movl $64, 12(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9normalizeiiPfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 168(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
shlq $32, %rdi
orq $1, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movl %ebp, 16(%rsp)
movl %r14d, 12(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 20(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17padding_transposeiiPKfPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_12
# %bb.13: # %_ZL5check10hipError_tPKc.exit55
addq $-63, %r12
imulq %rbx, %r12
movabsq $34359738376, %rdx # imm = 0x800000008
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movl %ebp, 16(%rsp)
movl %r14d, 12(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 20(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13correlate_gpuiiPKfPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
callq hipGetLastError
testl %eax, %eax
movq 160(%rsp), %rdi # 8-byte Reload
jne .LBB3_12
# %bb.16: # %_ZL5check10hipError_tPKc.exit63
movq 96(%rsp), %rsi
movq 152(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_17
# %bb.18: # %_ZL5check10hipError_tPKc.exit65
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_19
# %bb.20: # %_ZL5check10hipError_tPKc.exit67
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_21
# %bb.22: # %_ZL5check10hipError_tPKc.exit69
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 240
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.3, %esi
jmp .LBB3_2
.LBB3_1:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
jmp .LBB3_2
.LBB3_4:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
jmp .LBB3_2
.LBB3_6:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
jmp .LBB3_2
.LBB3_17:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
jmp .LBB3_2
.LBB3_19:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
jmp .LBB3_2
.LBB3_21:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
.LBB3_2:
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z9correlateiiPKfPf, .Lfunc_end3-_Z9correlateiiPKfPf
.cfi_endproc
# -- End function
.section .text._Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,"axG",@progbits,_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,comdat
.weak _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind # -- Begin function _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
.p2align 4, 0x90
.type _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,@function
_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind: # @_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
shlq $2, %rdx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_2
# %bb.1: # %_ZL5check10hipError_tPKc.exit
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.9, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind, .Lfunc_end4-_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13correlate_gpuiiPKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9normalizeiiPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17padding_transposeiiPKfPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13correlate_gpuiiPKfPfi,@object # @_Z13correlate_gpuiiPKfPfi
.section .rodata,"a",@progbits
.globl _Z13correlate_gpuiiPKfPfi
.p2align 3, 0x0
_Z13correlate_gpuiiPKfPfi:
.quad _Z28__device_stub__correlate_gpuiiPKfPfi
.size _Z13correlate_gpuiiPKfPfi, 8
.type _Z9normalizeiiPfi,@object # @_Z9normalizeiiPfi
.globl _Z9normalizeiiPfi
.p2align 3, 0x0
_Z9normalizeiiPfi:
.quad _Z24__device_stub__normalizeiiPfi
.size _Z9normalizeiiPfi, 8
.type _Z17padding_transposeiiPKfPfi,@object # @_Z17padding_transposeiiPKfPfi
.globl _Z17padding_transposeiiPKfPfi
.p2align 3, 0x0
_Z17padding_transposeiiPKfPfi:
.quad _Z32__device_stub__padding_transposeiiPKfPfi
.size _Z17padding_transposeiiPKfPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc((void**)&dGPU,ny*nx*sizeof(float))"
.size .L.str, 45
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void**)&padding,new_ny*nx*sizeof(float))"
.size .L.str.1, 52
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc((void**)&rGPU,ny*ny*sizeof(float))"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipGetLastError()"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipFree(dGPU)"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipFree(padding)"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipFree(rGPU)"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA error: "
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz ": "
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMemcpy(target, source, num * sizeof(T), direction)"
.size .L.str.9, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13correlate_gpuiiPKfPfi"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9normalizeiiPfi"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17padding_transposeiiPKfPfi"
.size .L__unnamed_3, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__correlate_gpuiiPKfPfi
.addrsig_sym _Z24__device_stub__normalizeiiPfi
.addrsig_sym _Z32__device_stub__padding_transposeiiPKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13correlate_gpuiiPKfPfi
.addrsig_sym _Z9normalizeiiPfi
.addrsig_sym _Z17padding_transposeiiPKfPfi
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000faf67_00000000-6_cp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4039:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.type _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, @function
_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi:
.LFB4061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13correlate_gpuiiPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4061:
.size _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, .-_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.globl _Z13correlate_gpuiiPKfPfi
.type _Z13correlate_gpuiiPKfPfi, @function
_Z13correlate_gpuiiPKfPfi:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _Z13correlate_gpuiiPKfPfi, .-_Z13correlate_gpuiiPKfPfi
.globl _Z31__device_stub__Z9normalizeiiPfiiiPfi
.type _Z31__device_stub__Z9normalizeiiPfiiiPfi, @function
_Z31__device_stub__Z9normalizeiiPfiiiPfi:
.LFB4063:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9normalizeiiPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4063:
.size _Z31__device_stub__Z9normalizeiiPfiiiPfi, .-_Z31__device_stub__Z9normalizeiiPfiiiPfi
.globl _Z9normalizeiiPfi
.type _Z9normalizeiiPfi, @function
_Z9normalizeiiPfi:
.LFB4064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9normalizeiiPfiiiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4064:
.size _Z9normalizeiiPfi, .-_Z9normalizeiiPfi
.globl _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.type _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, @function
_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi:
.LFB4065:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17padding_transposeiiPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, .-_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.globl _Z17padding_transposeiiPKfPfi
.type _Z17padding_transposeiiPKfPfi, @function
_Z17padding_transposeiiPKfPfi:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z17padding_transposeiiPKfPfi, .-_Z17padding_transposeiiPKfPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17padding_transposeiiPKfPfi"
.LC1:
.string "_Z9normalizeiiPfi"
.LC2:
.string "_Z13correlate_gpuiiPKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4068:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17padding_transposeiiPKfPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9normalizeiiPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13correlate_gpuiiPKfPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.1,"aMS",@progbits,1
.LC3:
.string "CUDA error: "
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "cudaMemcpy(target, source, num * sizeof(T), direction)"
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.1
.LC5:
.string ": "
.section .text._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind,"axG",@progbits,_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind,comdat
.weak _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
.type _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind, @function
_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind:
.LFB4371:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
salq $2, %rdx
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %ebx
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4371:
.size _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind, .-_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "cudaMalloc((void**)&dGPU,ny*nx*sizeof(float))"
.align 8
.LC7:
.string "cudaMalloc((void**)&padding,new_ny*nx*sizeof(float))"
.align 8
.LC8:
.string "cudaMalloc((void**)&rGPU,ny*ny*sizeof(float))"
.section .rodata.str1.1
.LC9:
.string "cudaGetLastError()"
.LC10:
.string "cudaFree(dGPU)"
.LC11:
.string "cudaFree(padding)"
.LC12:
.string "cudaFree(rGPU)"
.text
.globl _Z9correlateiiPKfPf
.type _Z9correlateiiPKfPf, @function
_Z9correlateiiPKfPf:
.LFB4036:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, 8(%rsp)
movq %rcx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leal 126(%rdi), %ebp
movl %edi, %eax
addl $63, %eax
cmovns %eax, %ebp
movl %ebp, %r15d
sarl $6, %r15d
andl $-64, %ebp
movq $0, 40(%rsp)
movl %edi, %r13d
imull %esi, %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movq $0, 48(%rsp)
movl %r12d, %esi
imull %ebp, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L48
movq $0, 56(%rsp)
movl %ebx, %r14d
imull %ebx, %r14d
movslq %r14d, %r14
leaq 0(,%r14,4), %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, 28(%rsp)
testl %eax, %eax
jne .L49
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
movl $64, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r15d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
movl $64, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L38:
call cudaGetLastError@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L52
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl %r15d, 76(%rsp)
movl %r15d, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L40:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
movl $2, %ecx
movq %r14, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L56
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L57
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %eax, %r14d
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L48:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L49:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl 28(%rsp), %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L50:
movl $64, %ecx
movq 40(%rsp), %rdx
movl %r12d, %esi
movl %ebx, %edi
call _Z31__device_stub__Z9normalizeiiPfiiiPfi
jmp .L37
.L51:
movl %ebp, %r8d
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movl %r12d, %esi
movl %ebx, %edi
call _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
jmp .L38
.L52:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %ebp, %r8d
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl %r12d, %esi
movl %ebx, %edi
call _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
jmp .L40
.L54:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L55:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L56:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L57:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4036:
.size _Z9correlateiiPKfPf, .-_Z9correlateiiPKfPf
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__correlate_gpuiiPKfPfi # -- Begin function _Z28__device_stub__correlate_gpuiiPKfPfi
.p2align 4, 0x90
.type _Z28__device_stub__correlate_gpuiiPKfPfi,@function
_Z28__device_stub__correlate_gpuiiPKfPfi: # @_Z28__device_stub__correlate_gpuiiPKfPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13correlate_gpuiiPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__correlate_gpuiiPKfPfi, .Lfunc_end0-_Z28__device_stub__correlate_gpuiiPKfPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__normalizeiiPfi # -- Begin function _Z24__device_stub__normalizeiiPfi
.p2align 4, 0x90
.type _Z24__device_stub__normalizeiiPfi,@function
_Z24__device_stub__normalizeiiPfi: # @_Z24__device_stub__normalizeiiPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizeiiPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__normalizeiiPfi, .Lfunc_end1-_Z24__device_stub__normalizeiiPfi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__padding_transposeiiPKfPfi # -- Begin function _Z32__device_stub__padding_transposeiiPKfPfi
.p2align 4, 0x90
.type _Z32__device_stub__padding_transposeiiPKfPfi,@function
_Z32__device_stub__padding_transposeiiPKfPfi: # @_Z32__device_stub__padding_transposeiiPKfPfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17padding_transposeiiPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z32__device_stub__padding_transposeiiPKfPfi, .Lfunc_end2-_Z32__device_stub__padding_transposeiiPKfPfi
.cfi_endproc
# -- End function
.globl _Z9correlateiiPKfPf # -- Begin function _Z9correlateiiPKfPf
.p2align 4, 0x90
.type _Z9correlateiiPKfPf,@function
_Z9correlateiiPKfPf: # @_Z9correlateiiPKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r12
movq %rdx, 176(%rsp) # 8-byte Spill
movl %esi, %r13d
# kill: def $edi killed $edi def $rdi
leal 63(%rdi), %eax
leal 126(%rdi), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
movq $0, 24(%rsp)
movl %esi, %eax
movq %rdi, %rbp
imull %edi, %eax
movslq %eax, %rbx
leaq (,%rbx,4), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_ZL5check10hipError_tPKc.exit
movl %r14d, %eax
andl $-64, %eax
movq $0, 104(%rsp)
movq %rax, 168(%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
movl %r13d, %r15d
imull %r13d, %eax
movslq %eax, %rsi
shlq $2, %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_ZL5check10hipError_tPKc.exit45
movq %r12, 160(%rsp) # 8-byte Spill
movq $0, 96(%rsp)
movl %ebp, %eax
imull %eax, %eax
movq %rax, 152(%rsp) # 8-byte Spill
leaq (,%rax,4), %rsi
leaq 96(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_ZL5check10hipError_tPKc.exit47
sarl $6, %r14d
movabsq $4294967360, %r12 # imm = 0x100000040
movq 24(%rsp), %rdi
movq 176(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
movl %r14d, %ebx
leaq (%rbx,%r12), %rdi
addq $-64, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movl %r15d, %r14d
jne .LBB3_9
# %bb.8:
movq 24(%rsp), %rax
movl %ebp, 32(%rsp)
movl %r14d, 16(%rsp)
movq %rax, 88(%rsp)
movl $64, 12(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9normalizeiiPfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 168(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
shlq $32, %rdi
orq $1, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movl %ebp, 16(%rsp)
movl %r14d, 12(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 20(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17padding_transposeiiPKfPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_12
# %bb.13: # %_ZL5check10hipError_tPKc.exit55
addq $-63, %r12
imulq %rbx, %r12
movabsq $34359738376, %rdx # imm = 0x800000008
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movl %ebp, 16(%rsp)
movl %r14d, 12(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 20(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13correlate_gpuiiPKfPfi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
callq hipGetLastError
testl %eax, %eax
movq 160(%rsp), %rdi # 8-byte Reload
jne .LBB3_12
# %bb.16: # %_ZL5check10hipError_tPKc.exit63
movq 96(%rsp), %rsi
movq 152(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_17
# %bb.18: # %_ZL5check10hipError_tPKc.exit65
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_19
# %bb.20: # %_ZL5check10hipError_tPKc.exit67
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_21
# %bb.22: # %_ZL5check10hipError_tPKc.exit69
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 240
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.3, %esi
jmp .LBB3_2
.LBB3_1:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
jmp .LBB3_2
.LBB3_4:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
jmp .LBB3_2
.LBB3_6:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
jmp .LBB3_2
.LBB3_17:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
jmp .LBB3_2
.LBB3_19:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
jmp .LBB3_2
.LBB3_21:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
.LBB3_2:
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z9correlateiiPKfPf, .Lfunc_end3-_Z9correlateiiPKfPf
.cfi_endproc
# -- End function
.section .text._Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,"axG",@progbits,_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,comdat
.weak _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind # -- Begin function _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
.p2align 4, 0x90
.type _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind,@function
_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind: # @_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
shlq $2, %rdx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_2
# %bb.1: # %_ZL5check10hipError_tPKc.exit
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.9, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind, .Lfunc_end4-_Z11cuda_memcpyIfEvPT_PKS0_m13hipMemcpyKind
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13correlate_gpuiiPKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9normalizeiiPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17padding_transposeiiPKfPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13correlate_gpuiiPKfPfi,@object # @_Z13correlate_gpuiiPKfPfi
.section .rodata,"a",@progbits
.globl _Z13correlate_gpuiiPKfPfi
.p2align 3, 0x0
_Z13correlate_gpuiiPKfPfi:
.quad _Z28__device_stub__correlate_gpuiiPKfPfi
.size _Z13correlate_gpuiiPKfPfi, 8
.type _Z9normalizeiiPfi,@object # @_Z9normalizeiiPfi
.globl _Z9normalizeiiPfi
.p2align 3, 0x0
_Z9normalizeiiPfi:
.quad _Z24__device_stub__normalizeiiPfi
.size _Z9normalizeiiPfi, 8
.type _Z17padding_transposeiiPKfPfi,@object # @_Z17padding_transposeiiPKfPfi
.globl _Z17padding_transposeiiPKfPfi
.p2align 3, 0x0
_Z17padding_transposeiiPKfPfi:
.quad _Z32__device_stub__padding_transposeiiPKfPfi
.size _Z17padding_transposeiiPKfPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc((void**)&dGPU,ny*nx*sizeof(float))"
.size .L.str, 45
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void**)&padding,new_ny*nx*sizeof(float))"
.size .L.str.1, 52
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc((void**)&rGPU,ny*ny*sizeof(float))"
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipGetLastError()"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipFree(dGPU)"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipFree(padding)"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipFree(rGPU)"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA error: "
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz ": "
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMemcpy(target, source, num * sizeof(T), direction)"
.size .L.str.9, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13correlate_gpuiiPKfPfi"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9normalizeiiPfi"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17padding_transposeiiPKfPfi"
.size .L__unnamed_3, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__correlate_gpuiiPKfPfi
.addrsig_sym _Z24__device_stub__normalizeiiPfi
.addrsig_sym _Z32__device_stub__padding_transposeiiPKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13correlate_gpuiiPKfPfi
.addrsig_sym _Z9normalizeiiPfi
.addrsig_sym _Z17padding_transposeiiPKfPfi
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdlib.h"
#include "stdio.h"
#include <thrust/extrema.h>
#include <thrust/execution_policy.h>
#include <thrust/device_ptr.h>
#include "math.h"
#define BLOCK_SIZE 32
__global__
void swap_cols_kernel(double *a, int col1_idx, int col2_idx, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int offset = gridDim.x * blockDim.x;
for (int row = idx; row < n; row+=offset) {
double tmp = a[n*idx+col1_idx];
a[n*idx+col1_idx] = a[n*idx+col2_idx];
a[n*idx+col2_idx] = tmp;
}
}
__global__
void coef_mul_and_sub_kernel(double *a, int fst_col_idx, int fst_row_idx, double *coefs, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int offset_x = gridDim.x * blockDim.x;
int offset_y = gridDim.y * blockDim.y;
for (int i = fst_col_idx + idx; i < n; i+=offset_x) {
for (int j = fst_row_idx+idy; j < n; j+=offset_y) {
int diag_elem_idx = n*j+fst_col_idx-1;
a[n*j + i] -=coefs[i]*a[diag_elem_idx];
}
}
}
struct compare_abs_value
{
__host__ __device__
bool operator()(double a, double b) {
return (a<0? -a:a) < ( b<0? -b:b);
}
};
void print_matrix(double *a, int n) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++)
printf("%.10e ", a[j*n+i]);
printf("\n");
}
}
__global__
void set_cur_row_elements_kernel(double* a, double* coefs, int n, int row, int fst_col_idx) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
int offset = blockDim.x*gridDim.x;
for (int col = idx+fst_col_idx; col < n; col+=offset) {
coefs[col] = a[n*row+col]/a[n*row+fst_col_idx-1];
a[n*row+col] = coefs[col];
}
}
int main() {
int n;
scanf("%d", &n);
double* a = (double*)malloc(sizeof(double)*n*n);
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++)
scanf("%lf", &a[j*n+i]);
}
int size = sizeof(double)*n*n;
double* d_a;
cudaMalloc(&d_a, size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
int* swap_vector = (int*)malloc(sizeof(int)*n);
double *d_coefs;
double *coefs = (double*)malloc(sizeof(double)*n);
cudaMalloc(&d_coefs, n*sizeof(double));
for (int row = 0; row < n-1; row++) {
thrust::device_ptr<double> d_ptr = thrust::device_pointer_cast(&d_a[row*n+row]);
thrust::device_ptr<double> d_row_begin_ptr = thrust::device_pointer_cast(&d_a[row*n]);
thrust::device_ptr<double> max_elem_ptr = thrust::max_element(d_ptr, d_row_begin_ptr + n, compare_abs_value());
int max_elem_idx = max_elem_ptr - d_row_begin_ptr;
swap_vector[row] = max_elem_idx;
swap_cols_kernel<<<(n+BLOCK_SIZE-1)/BLOCK_SIZE, BLOCK_SIZE>>>(d_a, row, max_elem_idx, n);
set_cur_row_elements_kernel<<<((n-row-1)+BLOCK_SIZE-1)/BLOCK_SIZE, BLOCK_SIZE>>>(d_a, d_coefs, n, row, row+1);
cudaMemcpy(coefs, d_coefs, sizeof(double)*n, cudaMemcpyDeviceToHost);
dim3 dimGrid = dim3(((n-row-1)+BLOCK_SIZE-1)/BLOCK_SIZE, ((n-row-1)+BLOCK_SIZE-1)/BLOCK_SIZE);
dim3 dimBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
coef_mul_and_sub_kernel<<<dimGrid, dimBlock>>>(d_a, row+1, row+1, d_coefs, n);
}
swap_vector[n-1] = n-1;
cudaMemcpy(a, d_a, size, cudaMemcpyDeviceToHost);
print_matrix(a, n);
int* p = (int*)malloc(sizeof(int)*n);
for (int i = 0; i < n; i++)
p[i] = i;
for (int i = n-1; i >= 0; i--) {
int tmp = p[i];
p[i] = p[swap_vector[i]];
p[swap_vector[i]] = tmp;
}
for (int i = 0; i < n; i++)
printf("%d ", p[i]);
cudaFree(d_a);
cudaFree(coefs);
free(a);
free(p);
free(swap_vector);
return 0;
} | #include <hip/hip_runtime.h>
#include "stdlib.h"
#include "stdio.h"
#include <thrust/extrema.h>
#include <thrust/execution_policy.h>
#include <thrust/device_ptr.h>
#include "math.h"
#define BLOCK_SIZE 32
__global__
void swap_cols_kernel(double *a, int col1_idx, int col2_idx, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int offset = gridDim.x * blockDim.x;
for (int row = idx; row < n; row+=offset) {
double tmp = a[n*idx+col1_idx];
a[n*idx+col1_idx] = a[n*idx+col2_idx];
a[n*idx+col2_idx] = tmp;
}
}
__global__
void coef_mul_and_sub_kernel(double *a, int fst_col_idx, int fst_row_idx, double *coefs, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int offset_x = gridDim.x * blockDim.x;
int offset_y = gridDim.y * blockDim.y;
for (int i = fst_col_idx + idx; i < n; i+=offset_x) {
for (int j = fst_row_idx+idy; j < n; j+=offset_y) {
int diag_elem_idx = n*j+fst_col_idx-1;
a[n*j + i] -=coefs[i]*a[diag_elem_idx];
}
}
}
struct compare_abs_value
{
__host__ __device__
bool operator()(double a, double b) {
return (a<0? -a:a) < ( b<0? -b:b);
}
};
void print_matrix(double *a, int n) {
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++)
printf("%.10e ", a[j*n+i]);
printf("\n");
}
}
__global__
void set_cur_row_elements_kernel(double* a, double* coefs, int n, int row, int fst_col_idx) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
int offset = blockDim.x*gridDim.x;
for (int col = idx+fst_col_idx; col < n; col+=offset) {
coefs[col] = a[n*row+col]/a[n*row+fst_col_idx-1];
a[n*row+col] = coefs[col];
}
}
int main() {
int n;
scanf("%d", &n);
double* a = (double*)malloc(sizeof(double)*n*n);
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++)
scanf("%lf", &a[j*n+i]);
}
int size = sizeof(double)*n*n;
double* d_a;
hipMalloc(&d_a, size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
int* swap_vector = (int*)malloc(sizeof(int)*n);
double *d_coefs;
double *coefs = (double*)malloc(sizeof(double)*n);
hipMalloc(&d_coefs, n*sizeof(double));
for (int row = 0; row < n-1; row++) {
thrust::device_ptr<double> d_ptr = thrust::device_pointer_cast(&d_a[row*n+row]);
thrust::device_ptr<double> d_row_begin_ptr = thrust::device_pointer_cast(&d_a[row*n]);
thrust::device_ptr<double> max_elem_ptr = thrust::max_element(d_ptr, d_row_begin_ptr + n, compare_abs_value());
int max_elem_idx = max_elem_ptr - d_row_begin_ptr;
swap_vector[row] = max_elem_idx;
swap_cols_kernel<<<(n+BLOCK_SIZE-1)/BLOCK_SIZE, BLOCK_SIZE>>>(d_a, row, max_elem_idx, n);
set_cur_row_elements_kernel<<<((n-row-1)+BLOCK_SIZE-1)/BLOCK_SIZE, BLOCK_SIZE>>>(d_a, d_coefs, n, row, row+1);
hipMemcpy(coefs, d_coefs, sizeof(double)*n, hipMemcpyDeviceToHost);
dim3 dimGrid = dim3(((n-row-1)+BLOCK_SIZE-1)/BLOCK_SIZE, ((n-row-1)+BLOCK_SIZE-1)/BLOCK_SIZE);
dim3 dimBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
coef_mul_and_sub_kernel<<<dimGrid, dimBlock>>>(d_a, row+1, row+1, d_coefs, n);
}
swap_vector[n-1] = n-1;
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
print_matrix(a, n);
int* p = (int*)malloc(sizeof(int)*n);
for (int i = 0; i < n; i++)
p[i] = i;
for (int i = n-1; i >= 0; i--) {
int tmp = p[i];
p[i] = p[swap_vector[i]];
p[swap_vector[i]] = tmp;
}
for (int i = 0; i < n; i++)
printf("%d ", p[i]);
hipFree(d_a);
hipFree(coefs);
free(a);
free(p);
free(swap_vector);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cstdio>
#include<memory>
#include<vector>
#include<functional>
#include<iostream>
using namespace std;
using fp = void(*)(int*);
__global__ void
test(int *d_data){
printf("hello world\n");
for(int i = 0;i<10;i++)
printf("%d:%d\n",i,d_data[i]);
}
int uniquePtr(){
cout<<"uniquePtr"<<endl;
int *d_data0;
function<void(int*)> lambda = [](int*p){cudaFree(p);};
unique_ptr<int,function<void(int*)>> d_data{nullptr, lambda};
cudaMalloc((void**)&d_data0,sizeof(int)*10);
d_data.reset(d_data0);
//交给unique_ptr做指针维护
// unique_ptr 的生命周期要与cudaDeviceReset一起考虑，
//cudaDeviceReset是将上下文都重置，如果之前并未执行cudaFree则会造成内存泄漏
// 但是，如果不调用cudaDeviceReset,其会在main函数生命周期之后执行
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(d_data.get(),h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(d_data.get());
cudaDeviceSynchronize();
return 0;
}
int uniquePtr1(){
cout<<"uniquePtr1"<<endl;
function<void(int*)> lambda = [](int*p){cudaFree(p);};
vector<unique_ptr<int,function<void(int*)>> > vec;
for(int i=0; i<2;i++){
vec.emplace_back(nullptr,lambda);
int* tmp;
cudaMalloc((void**)&tmp,sizeof(int)*10);
vec[i].reset(tmp);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(vec[i].get(),h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(vec[i].get());
}
cudaDeviceSynchronize();
return 0;
}
int normal(){
cout<<"normal"<<endl;
int *d_data;
// 故意缺少cudaFree，调用cuda-memcheck
cudaMalloc((void**)&d_data,sizeof(int)*10);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(d_data,h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(d_data);
cudaDeviceSynchronize();
return 0;
}
int main(){
#ifdef UNIQUE
uniquePtr();
cout<<"-------------"<<endl;
uniquePtr1();
#else
normal();
#endif
//一定要加上这句，不然底层context会自己帮忙释放未释放的内存，
//显示调用就意味着内存需要手动自己释放
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z4testPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ MOV R19, 0x0 ; /* 0x0000000000137802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0060*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0070*/ IADD3 R18, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001127a10 */
/* 0x000fe20007f1e0ff */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff027624 */
/* 0x000fe400000e06ff */
/*00a0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fcc0000000000 */
/*00b0*/ MOV R3, 0x120 ; /* 0x0000012000037802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0100*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0110*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0120*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fca00078e00ff */
/*0140*/ LDG.E R11, [R16.64] ; /* 0x00000024100b7981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0160*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*01b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*01c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*01d0*/ MOV R3, 0x240 ; /* 0x0000024000037802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R20, 0x1c0 ; /* 0x000001c000147802 */
/* 0x000fc40000000f00 */
/*01f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0210*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0220*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0230*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0240*/ LDG.E R11, [R16.64+0x4] ; /* 0x00000424100b7981 */
/* 0x000ea2000c1e1900 */
/*0250*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0260*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*02b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*02c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*02d0*/ MOV R3, 0x340 ; /* 0x0000034000037802 */
/* 0x000fe40000000f00 */
/*02e0*/ MOV R20, 0x2c0 ; /* 0x000002c000147802 */
/* 0x000fc40000000f00 */
/*02f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0300*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0310*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0320*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0330*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0340*/ LDG.E R11, [R16.64+0x8] ; /* 0x00000824100b7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.MOV.U32 R10, RZ, RZ, 0x2 ; /* 0x00000002ff0a7424 */
/* 0x000fe200078e00ff */
/*0360*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*03a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*03b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*03c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*03d0*/ MOV R3, 0x440 ; /* 0x0000044000037802 */
/* 0x000fe40000000f00 */
/*03e0*/ MOV R20, 0x3c0 ; /* 0x000003c000147802 */
/* 0x000fc40000000f00 */
/*03f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0400*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0410*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0420*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0430*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0440*/ LDG.E R11, [R16.64+0xc] ; /* 0x00000c24100b7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */
/* 0x000fe200078e00ff */
/*0460*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0470*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*04a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*04b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*04c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*04d0*/ MOV R3, 0x540 ; /* 0x0000054000037802 */
/* 0x000fe40000000f00 */
/*04e0*/ MOV R20, 0x4c0 ; /* 0x000004c000147802 */
/* 0x000fc40000000f00 */
/*04f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0500*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0510*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0520*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0530*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0540*/ LDG.E R11, [R16.64+0x10] ; /* 0x00001024100b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*0560*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0580*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*05b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*05c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*05d0*/ MOV R3, 0x640 ; /* 0x0000064000037802 */
/* 0x000fe40000000f00 */
/*05e0*/ MOV R20, 0x5c0 ; /* 0x000005c000147802 */
/* 0x000fc40000000f00 */
/*05f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0600*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0610*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0620*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0630*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0640*/ LDG.E R11, [R16.64+0x14] ; /* 0x00001424100b7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ IMAD.MOV.U32 R10, RZ, RZ, 0x5 ; /* 0x00000005ff0a7424 */
/* 0x000fe200078e00ff */
/*0660*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0670*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0680*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0690*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*06a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*06b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*06c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*06d0*/ MOV R3, 0x740 ; /* 0x0000074000037802 */
/* 0x000fe40000000f00 */
/*06e0*/ MOV R20, 0x6c0 ; /* 0x000006c000147802 */
/* 0x000fc40000000f00 */
/*06f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0700*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0710*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0720*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0730*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0740*/ LDG.E R11, [R16.64+0x18] ; /* 0x00001824100b7981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IMAD.MOV.U32 R10, RZ, RZ, 0x6 ; /* 0x00000006ff0a7424 */
/* 0x000fe200078e00ff */
/*0760*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0770*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0780*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0790*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*07a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*07b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*07c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*07d0*/ MOV R3, 0x840 ; /* 0x0000084000037802 */
/* 0x000fe40000000f00 */
/*07e0*/ MOV R20, 0x7c0 ; /* 0x000007c000147802 */
/* 0x000fc40000000f00 */
/*07f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0800*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0810*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0820*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0830*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0840*/ LDG.E R11, [R16.64+0x1c] ; /* 0x00001c24100b7981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IMAD.MOV.U32 R10, RZ, RZ, 0x7 ; /* 0x00000007ff0a7424 */
/* 0x000fe200078e00ff */
/*0860*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0870*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0880*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0890*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*08a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*08b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*08c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*08d0*/ MOV R3, 0x940 ; /* 0x0000094000037802 */
/* 0x000fe40000000f00 */
/*08e0*/ MOV R20, 0x8c0 ; /* 0x000008c000147802 */
/* 0x000fc40000000f00 */
/*08f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0900*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0910*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0920*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0930*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0940*/ LDG.E R11, [R16.64+0x20] ; /* 0x00002024100b7981 */
/* 0x000ea2000c1e1900 */
/*0950*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fe200078e00ff */
/*0960*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0970*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0980*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0990*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*09a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*09b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*09c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*09d0*/ MOV R3, 0xa40 ; /* 0x00000a4000037802 */
/* 0x000fe40000000f00 */
/*09e0*/ MOV R20, 0x9c0 ; /* 0x000009c000147802 */
/* 0x000fc40000000f00 */
/*09f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0a00*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0a10*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0a20*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0a30*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0a40*/ LDG.E R11, [R16.64+0x24] ; /* 0x00002424100b7981 */
/* 0x000ea2000c1e1900 */
/*0a50*/ IMAD.MOV.U32 R10, RZ, RZ, 0x9 ; /* 0x00000009ff0a7424 */
/* 0x000fe200078e00ff */
/*0a60*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0a70*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0a80*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0a90*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0ab0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*0ac0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe40000000000 */
/*0ad0*/ MOV R11, 0xb40 ; /* 0x00000b40000b7802 */
/* 0x001fe40000000f00 */
/*0ae0*/ MOV R20, 0xac0 ; /* 0x00000ac000147802 */
/* 0x000fc40000000f00 */
/*0af0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0b00*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0b10*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0b20*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0b30*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0b40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cstdio>
#include<memory>
#include<vector>
#include<functional>
#include<iostream>
using namespace std;
using fp = void(*)(int*);
__global__ void
test(int *d_data){
printf("hello world\n");
for(int i = 0;i<10;i++)
printf("%d:%d\n",i,d_data[i]);
}
int uniquePtr(){
cout<<"uniquePtr"<<endl;
int *d_data0;
function<void(int*)> lambda = [](int*p){cudaFree(p);};
unique_ptr<int,function<void(int*)>> d_data{nullptr, lambda};
cudaMalloc((void**)&d_data0,sizeof(int)*10);
d_data.reset(d_data0);
//交给unique_ptr做指针维护
// unique_ptr 的生命周期要与cudaDeviceReset一起考虑，
//cudaDeviceReset是将上下文都重置，如果之前并未执行cudaFree则会造成内存泄漏
// 但是，如果不调用cudaDeviceReset,其会在main函数生命周期之后执行
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(d_data.get(),h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(d_data.get());
cudaDeviceSynchronize();
return 0;
}
int uniquePtr1(){
cout<<"uniquePtr1"<<endl;
function<void(int*)> lambda = [](int*p){cudaFree(p);};
vector<unique_ptr<int,function<void(int*)>> > vec;
for(int i=0; i<2;i++){
vec.emplace_back(nullptr,lambda);
int* tmp;
cudaMalloc((void**)&tmp,sizeof(int)*10);
vec[i].reset(tmp);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(vec[i].get(),h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(vec[i].get());
}
cudaDeviceSynchronize();
return 0;
}
int normal(){
cout<<"normal"<<endl;
int *d_data;
// 故意缺少cudaFree，调用cuda-memcheck
cudaMalloc((void**)&d_data,sizeof(int)*10);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(d_data,h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(d_data);
cudaDeviceSynchronize();
return 0;
}
int main(){
#ifdef UNIQUE
uniquePtr();
cout<<"-------------"<<endl;
uniquePtr1();
#else
normal();
#endif
//一定要加上这句，不然底层context会自己帮忙释放未释放的内存，
//显示调用就意味着内存需要手动自己释放
cudaDeviceReset();
return 0;
} | .file "tmpxft_0011cd0d_00000000-6_uniquePtr.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation, @function
_ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation:
.LFB6066:
.cfi_startproc
endbr64
testl %edx, %edx
je .L2
cmpl $1, %edx
jne .L4
movq %rsi, (%rdi)
jmp .L4
.L2:
leaq _ZTIZ9uniquePtrvEUlPiE_(%rip), %rax
movq %rax, (%rdi)
.L4:
movl $0, %eax
ret
.cfi_endproc
.LFE6066:
.size _ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation, .-_ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation
.type _ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation, @function
_ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation:
.LFB6088:
.cfi_startproc
endbr64
testl %edx, %edx
je .L6
cmpl $1, %edx
jne .L8
movq %rsi, (%rdi)
jmp .L8
.L6:
leaq _ZTIZ10uniquePtr1vEUlPiE_(%rip), %rax
movq %rax, (%rdi)
.L8:
movl $0, %eax
ret
.cfi_endproc
.LFE6088:
.size _ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation, .-_ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation
.type _ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_, @function
_ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_:
.LFB6062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq (%rsi), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6062:
.size _ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_, .-_ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_
.type _ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_, @function
_ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_:
.LFB6085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq (%rsi), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6085:
.size _ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_, .-_ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5510:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5510:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZNSt14_Function_baseD2Ev,"axG",@progbits,_ZNSt14_Function_baseD5Ev,comdat
.align 2
.weak _ZNSt14_Function_baseD2Ev
.type _ZNSt14_Function_baseD2Ev, @function
_ZNSt14_Function_baseD2Ev:
.LFB3665:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3665
endbr64
movq 16(%rdi), %rax
testq %rax, %rax
je .L18
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $3, %edx
movq %rdi, %rsi
call *%rax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L18:
ret
.cfi_endproc
.LFE3665:
.globl __gxx_personality_v0
.section .gcc_except_table._ZNSt14_Function_baseD2Ev,"aG",@progbits,_ZNSt14_Function_baseD5Ev,comdat
.LLSDA3665:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3665-.LLSDACSB3665
.LLSDACSB3665:
.LLSDACSE3665:
.section .text._ZNSt14_Function_baseD2Ev,"axG",@progbits,_ZNSt14_Function_baseD5Ev,comdat
.size _ZNSt14_Function_baseD2Ev, .-_ZNSt14_Function_baseD2Ev
.weak _ZNSt14_Function_baseD1Ev
.set _ZNSt14_Function_baseD1Ev,_ZNSt14_Function_baseD2Ev
.text
.globl _Z23__device_stub__Z4testPiPi
.type _Z23__device_stub__Z4testPiPi, @function
_Z23__device_stub__Z4testPiPi:
.LFB5532:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5532:
.size _Z23__device_stub__Z4testPiPi, .-_Z23__device_stub__Z4testPiPi
.globl _Z4testPi
.type _Z4testPi, @function
_Z4testPi:
.LFB5533:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4testPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5533:
.size _Z4testPi, .-_Z4testPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "uniquePtr"
.text
.globl _Z9uniquePtrv
.type _Z9uniquePtrv, @function
_Z9uniquePtrv:
.LFB5473:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5473
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $184, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $9, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L53
cmpb $0, 56(%rbx)
je .L32
movzbl 67(%rbx), %esi
.L33:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE0:
movq $0, 48(%rsp)
movq $0, 56(%rsp)
leaq _ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_(%rip), %rbp
movq %rbp, 72(%rsp)
leaq _ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation(%rip), %rbx
movq %rbx, 64(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 48(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $2, %edx
call _ZNSt17_Function_handlerIFvPiEZ9uniquePtrvEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation
movq %rbp, 104(%rsp)
movq %rbx, 96(%rsp)
movq $0, 112(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
.LEHB1:
call cudaMalloc@PLT
.LEHE1:
jmp .L54
.L53:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L55
.LEHB2:
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L32:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE2:
movl %eax, %esi
jmp .L33
.L54:
movq 112(%rsp), %rax
movq 8(%rsp), %rdx
movq %rdx, 112(%rsp)
testq %rax, %rax
je .L34
movq %rax, 32(%rsp)
cmpq $0, 96(%rsp)
je .L56
leaq 32(%rsp), %rsi
leaq 80(%rsp), %rdi
call *104(%rsp)
.L34:
movl $1, 128(%rsp)
movl $2, 132(%rsp)
movl $3, 136(%rsp)
movl $4, 140(%rsp)
movl $5, 144(%rsp)
movl $6, 148(%rsp)
movl $7, 152(%rsp)
movl $8, 156(%rsp)
movl $9, 160(%rsp)
movl $10, 164(%rsp)
leaq 128(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 112(%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
.LEHE3:
jmp .L57
.L56:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt25__throw_bad_function_callv@PLT
.L58:
call __stack_chk_fail@PLT
.L57:
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movq 112(%rsp), %rdi
call _Z23__device_stub__Z4testPiPi
.L37:
call cudaDeviceSynchronize@PLT
.LEHE4:
movq 112(%rsp), %rax
testq %rax, %rax
je .L38
movq %rax, 32(%rsp)
cmpq $0, 96(%rsp)
je .L59
leaq 32(%rsp), %rsi
leaq 80(%rsp), %rdi
call *104(%rsp)
.L38:
movq $0, 112(%rsp)
movq 96(%rsp), %rax
testq %rax, %rax
je .L41
leaq 80(%rsp), %rdi
movl $3, %edx
movq %rdi, %rsi
call *%rax
.L41:
movq 64(%rsp), %rax
testq %rax, %rax
je .L42
leaq 48(%rsp), %rdi
movl $3, %edx
movq %rdi, %rsi
call *%rax
.L42:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L61
call _ZSt25__throw_bad_function_callv@PLT
.L61:
call __stack_chk_fail@PLT
.L50:
endbr64
movq %rax, %rbx
movq 112(%rsp), %rax
testq %rax, %rax
je .L44
movq %rax, 32(%rsp)
cmpq $0, 96(%rsp)
jne .L45
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L46
call __stack_chk_fail@PLT
.L46:
call _ZSt25__throw_bad_function_callv@PLT
.L45:
leaq 32(%rsp), %rsi
leaq 80(%rsp), %rdi
call *104(%rsp)
.L44:
movq $0, 112(%rsp)
movq 96(%rsp), %rax
testq %rax, %rax
je .L47
leaq 80(%rsp), %rdi
movl $3, %edx
movq %rdi, %rsi
call *%rax
.L47:
leaq 48(%rsp), %rdi
call _ZNSt14_Function_baseD2Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5473:
.section .gcc_except_table,"a",@progbits
.LLSDA5473:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5473-.LLSDACSB5473
.LLSDACSB5473:
.uleb128 .LEHB0-.LFB5473
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB5473
.uleb128 .LEHE1-.LEHB1
.uleb128 .L50-.LFB5473
.uleb128 0
.uleb128 .LEHB2-.LFB5473
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB5473
.uleb128 .LEHE3-.LEHB3
.uleb128 .L50-.LFB5473
.uleb128 0
.uleb128 .LEHB4-.LFB5473
.uleb128 .LEHE4-.LEHB4
.uleb128 .L50-.LFB5473
.uleb128 0
.uleb128 .LEHB5-.LFB5473
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.LLSDACSE5473:
.text
.size _Z9uniquePtrv, .-_Z9uniquePtrv
.section .rodata.str1.1
.LC1:
.string "normal"
.text
.globl _Z6normalv
.type _Z6normalv, @function
_Z6normalv:
.LFB5506:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $6, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L70
cmpb $0, 56(%rbx)
je .L65
movzbl 67(%rbx), %esi
.L66:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $3, 40(%rsp)
movl $4, 44(%rsp)
movl $5, 48(%rsp)
movl $6, 52(%rsp)
movl $7, 56(%rsp)
movl $8, 60(%rsp)
movl $9, 64(%rsp)
movl $10, 68(%rsp)
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
call cudaDeviceSynchronize@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L72
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L73
call _ZSt16__throw_bad_castv@PLT
.L73:
call __stack_chk_fail@PLT
.L65:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L66
.L71:
movq (%rsp), %rdi
call _Z23__device_stub__Z4testPiPi
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5506:
.size _Z6normalv, .-_Z6normalv
.globl main
.type main, @function
main:
.LFB5507:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z6normalv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5507:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4testPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5535:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5535:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev,"axG",@progbits,_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev
.type _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev, @function
_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev:
.LFB5898:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5898
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq 8(%rdi), %rbp
movq (%rdi), %rbx
cmpq %rbx, %rbp
je .L79
movq %rsp, %r13
jmp .L84
.L90:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt25__throw_bad_function_callv@PLT
.L89:
call __stack_chk_fail@PLT
.L80:
movq $0, 32(%rbx)
movq 16(%rbx), %rax
testq %rax, %rax
je .L83
movl $3, %edx
movq %rbx, %rsi
movq %rbx, %rdi
call *%rax
.L83:
addq $40, %rbx
cmpq %rbx, %rbp
je .L79
.L84:
movq 32(%rbx), %rax
testq %rax, %rax
je .L80
movq %rax, (%rsp)
cmpq $0, 16(%rbx)
je .L90
movq %r13, %rsi
movq %rbx, %rdi
call *24(%rbx)
jmp .L80
.L79:
movq (%r12), %rdi
testq %rdi, %rdi
je .L78
movq 16(%r12), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L78:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L91
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L91:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5898:
.section .gcc_except_table
.LLSDA5898:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5898-.LLSDACSB5898
.LLSDACSB5898:
.LLSDACSE5898:
.section .text._ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev,"axG",@progbits,_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED5Ev,comdat
.size _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev, .-_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev
.weak _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED1Ev
.set _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED1Ev,_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED2Ev
.section .rodata._ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_.str1.1,"aMS",@progbits,1
.LC3:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.type _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, @function
_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_:
.LFB6105:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA6105
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, 16(%rsp)
movq 8(%rdi), %r13
movq (%rdi), %r15
movq %r13, %rax
subq %r15, %rax
sarq $3, %rax
movabsq $-3689348814741910323, %rdx
imulq %rdx, %rax
movabsq $230584300921369395, %rdx
cmpq %rdx, %rax
je .L118
movq %rdi, %r14
movq %rcx, %r12
movq %rsi, %rbp
cmpq %r15, %r13
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L95
movabsq $230584300921369395, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, 24(%rsp)
movq 16(%rsp), %rbx
subq %r15, %rbx
movq $0, 8(%rsp)
testq %rax, %rax
je .L96
jmp .L108
.L118:
leaq .LC3(%rip), %rdi
.LEHB6:
call _ZSt20__throw_length_errorPKc@PLT
.LEHE6:
.L119:
movq 24(%r12), %rax
movq %rax, 24(%rbx)
movq 16(%r12), %rax
movq %rax, 16(%rbx)
.L97:
movq $0, 32(%rbx)
movq %r15, %r12
movq 8(%rsp), %rbx
cmpq %r15, 16(%rsp)
jne .L98
.L99:
addq $40, %rbx
cmpq %r13, 16(%rsp)
jne .L106
.L103:
testq %r15, %r15
je .L107
movq 16(%r14), %rsi
subq %r15, %rsi
movq %r15, %rdi
call _ZdlPvm@PLT
.L107:
movq 8(%rsp), %rcx
movq %rcx, (%r14)
movq %rbx, 8(%r14)
movq 24(%rsp), %rax
leaq (%rax,%rax,4), %rax
leaq (%rcx,%rax,8), %rax
movq %rax, 16(%r14)
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore_state
endbr64
movq %rbx, %rdi
call _ZNSt14_Function_baseD2Ev
call _ZSt9terminatev@PLT
.L102:
addq $40, %r12
addq $40, %rbx
cmpq %r12, %rbp
je .L99
.L98:
pxor %xmm1, %xmm1
movups %xmm1, (%rbx)
movq $0, 16(%rbx)
movq 24(%r12), %rax
movq %rax, 24(%rbx)
movq 16(%r12), %rax
testq %rax, %rax
je .L101
movdqu (%r12), %xmm3
movups %xmm3, (%rbx)
movq %rax, 16(%rbx)
movq $0, 16(%r12)
movq $0, 24(%r12)
.L101:
movq 32(%r12), %rax
movq %rax, 32(%rbx)
movq $0, 32(%r12)
movq 16(%r12), %rax
testq %rax, %rax
je .L102
movl $3, %edx
movq %r12, %rsi
movq %r12, %rdi
call *%rax
jmp .L102
.L105:
addq $40, %rbp
addq $40, %rbx
cmpq %rbp, %r13
je .L103
.L106:
pxor %xmm2, %xmm2
movups %xmm2, (%rbx)
movq $0, 16(%rbx)
movq 24(%rbp), %rax
movq %rax, 24(%rbx)
movq 16(%rbp), %rax
testq %rax, %rax
je .L104
movdqu 0(%rbp), %xmm4
movups %xmm4, (%rbx)
movq %rax, 16(%rbx)
movq $0, 16(%rbp)
movq $0, 24(%rbp)
.L104:
movq 32(%rbp), %rax
movq %rax, 32(%rbx)
movq $0, 32(%rbp)
movq 16(%rbp), %rax
testq %rax, %rax
je .L105
movl $3, %edx
movq %rbp, %rsi
movq %rbp, %rdi
call *%rax
jmp .L105
.L95:
movq 16(%rsp), %rbx
subq %r15, %rbx
movabsq $230584300921369395, %rax
movq %rax, 24(%rsp)
.L108:
movq 24(%rsp), %rax
leaq (%rax,%rax,4), %rdi
salq $3, %rdi
.LEHB7:
call _Znwm@PLT
.LEHE7:
movq %rax, 8(%rsp)
.L96:
movq 8(%rsp), %rax
addq %rax, %rbx
pxor %xmm0, %xmm0
movups %xmm0, (%rbx)
movq $0, 16(%rbx)
movq $0, 24(%rbx)
movq 16(%r12), %rax
testq %rax, %rax
je .L97
movl $2, %edx
movq %r12, %rsi
movq %rbx, %rdi
.LEHB8:
call *%rax
.LEHE8:
jmp .L119
.cfi_endproc
.LFE6105:
.section .gcc_except_table
.LLSDA6105:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE6105-.LLSDACSB6105
.LLSDACSB6105:
.uleb128 .LEHB6-.LFB6105
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB6105
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.uleb128 .LEHB8-.LFB6105
.uleb128 .LEHE8-.LEHB8
.uleb128 .L112-.LFB6105
.uleb128 0
.LLSDACSE6105:
.section .text._ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.size _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, .-_ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.section .rodata.str1.1
.LC4:
.string "uniquePtr1"
.text
.globl _Z10uniquePtr1v
.type _Z10uniquePtr1v, @function
_Z10uniquePtr1v:
.LFB5490:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5490
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $10, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
.LEHB9:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L151
cmpb $0, 56(%rbx)
je .L123
movzbl 67(%rbx), %esi
.L124:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq _ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E9_M_invokeERKSt9_Any_dataOS0_(%rip), %rax
movq %rax, 104(%rsp)
leaq _ZNSt17_Function_handlerIFvPiEZ10uniquePtr1vEUlS0_E_E10_M_managerERSt9_Any_dataRKS4_St18_Manager_operation(%rip), %rax
movq %rax, 96(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $0, %ebp
jmp .L133
.L151:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L152
call _ZSt16__throw_bad_castv@PLT
.L152:
call __stack_chk_fail@PLT
.L123:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE9:
movl %eax, %esi
jmp .L124
.L159:
movq 104(%rsp), %rax
movq %rax, 24(%rbx)
movq 96(%rsp), %rax
movq %rax, 16(%rbx)
.L126:
movq $0, 32(%rbx)
addq $40, %rbx
movq %rbx, 56(%rsp)
.L127:
leaq 8(%rsp), %rdi
movl $40, %esi
.LEHB10:
call cudaMalloc@PLT
jmp .L153
.L146:
endbr64
movq %rbx, %rdi
call _ZNSt14_Function_baseD2Ev
call _ZSt9terminatev@PLT
.L125:
leaq 80(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EE17_M_realloc_insertIJDnRS4_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.LEHE10:
jmp .L127
.L153:
movq 48(%rsp), %r12
leaq (%r12,%rbp), %rbx
movq 32(%rbx), %rax
movq 8(%rsp), %rdx
movq %rdx, 32(%rbx)
testq %rax, %rax
je .L129
movq %rax, 32(%rsp)
cmpq $0, 16(%rbx)
je .L154
leaq 32(%rsp), %rsi
movq %rbx, %rdi
call *24(%rbx)
.L129:
movl $1, 112(%rsp)
movl $2, 116(%rsp)
movl $3, 120(%rsp)
movl $4, 124(%rsp)
movl $5, 128(%rsp)
movl $6, 132(%rsp)
movl $7, 136(%rsp)
movl $8, 140(%rsp)
movl $9, 144(%rsp)
movl $10, 148(%rsp)
leaq 112(%rsp), %rsi
movq 32(%rbx), %rdi
movl $1, %ecx
movl $40, %edx
.LEHB11:
call cudaMemcpy@PLT
.LEHE11:
jmp .L155
.L154:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L156
call _ZSt25__throw_bad_function_callv@PLT
.L156:
call __stack_chk_fail@PLT
.L155:
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
.LEHB12:
call __cudaPushCallConfiguration@PLT
.LEHE12:
testl %eax, %eax
je .L157
.L132:
addq $40, %rbp
cmpq $80, %rbp
je .L158
.L133:
movq $0, 32(%rsp)
movq 56(%rsp), %rbx
cmpq 64(%rsp), %rbx
je .L125
pxor %xmm0, %xmm0
movups %xmm0, (%rbx)
movq $0, 16(%rbx)
movq $0, 24(%rbx)
movq 96(%rsp), %rax
testq %rax, %rax
je .L126
leaq 80(%rsp), %rsi
movl $2, %edx
movq %rbx, %rdi
.LEHB13:
call *%rax
.LEHE13:
jmp .L159
.L157:
movq 32(%rbx), %rdi
.LEHB14:
call _Z23__device_stub__Z4testPiPi
jmp .L132
.L158:
call cudaDeviceSynchronize@PLT
.LEHE14:
movq 56(%rsp), %rbp
cmpq %rbp, %r12
je .L134
movq %r12, %rbx
leaq 32(%rsp), %r13
jmp .L139
.L161:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L160
call _ZSt25__throw_bad_function_callv@PLT
.L160:
call __stack_chk_fail@PLT
.L135:
movq $0, 32(%rbx)
movq 16(%rbx), %rax
testq %rax, %rax
je .L138
movl $3, %edx
movq %rbx, %rsi
movq %rbx, %rdi
call *%rax
.L138:
addq $40, %rbx
cmpq %rbx, %rbp
je .L134
.L139:
movq 32(%rbx), %rax
testq %rax, %rax
je .L135
movq %rax, 32(%rsp)
cmpq $0, 16(%rbx)
je .L161
movq %r13, %rsi
movq %rbx, %rdi
call *24(%rbx)
jmp .L135
.L134:
testq %r12, %r12
je .L140
movq 64(%rsp), %rsi
subq %r12, %rsi
movq %r12, %rdi
call _ZdlPvm@PLT
.L140:
movq 96(%rsp), %rax
testq %rax, %rax
je .L141
leaq 80(%rsp), %rdi
movl $3, %edx
movq %rdi, %rsi
call *%rax
.L141:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L162
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L145:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt6vectorISt10unique_ptrIiSt8functionIFvPiEEESaIS5_EED1Ev
leaq 80(%rsp), %rdi
call _ZNSt14_Function_baseD2Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L143
call __stack_chk_fail@PLT
.L143:
movq %rbx, %rdi
.LEHB15:
call _Unwind_Resume@PLT
.LEHE15:
.L162:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5490:
.section .gcc_except_table
.LLSDA5490:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5490-.LLSDACSB5490
.LLSDACSB5490:
.uleb128 .LEHB9-.LFB5490
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.uleb128 .LEHB10-.LFB5490
.uleb128 .LEHE10-.LEHB10
.uleb128 .L145-.LFB5490
.uleb128 0
.uleb128 .LEHB11-.LFB5490
.uleb128 .LEHE11-.LEHB11
.uleb128 .L145-.LFB5490
.uleb128 0
.uleb128 .LEHB12-.LFB5490
.uleb128 .LEHE12-.LEHB12
.uleb128 .L145-.LFB5490
.uleb128 0
.uleb128 .LEHB13-.LFB5490
.uleb128 .LEHE13-.LEHB13
.uleb128 .L146-.LFB5490
.uleb128 0
.uleb128 .LEHB14-.LFB5490
.uleb128 .LEHE14-.LEHB14
.uleb128 .L145-.LFB5490
.uleb128 0
.uleb128 .LEHB15-.LFB5490
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.LLSDACSE5490:
.text
.size _Z10uniquePtr1v, .-_Z10uniquePtr1v
.section .data.rel.ro,"aw"
.align 8
.type _ZTIZ9uniquePtrvEUlPiE_, @object
.size _ZTIZ9uniquePtrvEUlPiE_, 16
_ZTIZ9uniquePtrvEUlPiE_:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSZ9uniquePtrvEUlPiE_
.section .rodata
.align 16
.type _ZTSZ9uniquePtrvEUlPiE_, @object
.size _ZTSZ9uniquePtrvEUlPiE_, 21
_ZTSZ9uniquePtrvEUlPiE_:
.string "*Z9uniquePtrvEUlPiE_"
.section .data.rel.ro
.align 8
.type _ZTIZ10uniquePtr1vEUlPiE_, @object
.size _ZTIZ10uniquePtr1vEUlPiE_, 16
_ZTIZ10uniquePtr1vEUlPiE_:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSZ10uniquePtr1vEUlPiE_
.section .rodata
.align 16
.type _ZTSZ10uniquePtr1vEUlPiE_, @object
.size _ZTSZ10uniquePtr1vEUlPiE_, 23
_ZTSZ10uniquePtr1vEUlPiE_:
.string "*Z10uniquePtr1vEUlPiE_"
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cstdio>
#include<memory>
#include<vector>
#include<functional>
#include<iostream>
using namespace std;
using fp = void(*)(int*);
__global__ void
test(int *d_data){
printf("hello world\n");
for(int i = 0;i<10;i++)
printf("%d:%d\n",i,d_data[i]);
}
int uniquePtr(){
cout<<"uniquePtr"<<endl;
int *d_data0;
function<void(int*)> lambda = [](int*p){cudaFree(p);};
unique_ptr<int,function<void(int*)>> d_data{nullptr, lambda};
cudaMalloc((void**)&d_data0,sizeof(int)*10);
d_data.reset(d_data0);
//交给unique_ptr做指针维护
// unique_ptr 的生命周期要与cudaDeviceReset一起考虑，
//cudaDeviceReset是将上下文都重置，如果之前并未执行cudaFree则会造成内存泄漏
// 但是，如果不调用cudaDeviceReset,其会在main函数生命周期之后执行
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(d_data.get(),h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(d_data.get());
cudaDeviceSynchronize();
return 0;
}
int uniquePtr1(){
cout<<"uniquePtr1"<<endl;
function<void(int*)> lambda = [](int*p){cudaFree(p);};
vector<unique_ptr<int,function<void(int*)>> > vec;
for(int i=0; i<2;i++){
vec.emplace_back(nullptr,lambda);
int* tmp;
cudaMalloc((void**)&tmp,sizeof(int)*10);
vec[i].reset(tmp);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(vec[i].get(),h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(vec[i].get());
}
cudaDeviceSynchronize();
return 0;
}
int normal(){
cout<<"normal"<<endl;
int *d_data;
// 故意缺少cudaFree，调用cuda-memcheck
cudaMalloc((void**)&d_data,sizeof(int)*10);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
cudaMemcpy(d_data,h_data,sizeof(int)*10,cudaMemcpyHostToDevice);
test<<<1,1>>>(d_data);
cudaDeviceSynchronize();
return 0;
}
int main(){
#ifdef UNIQUE
uniquePtr();
cout<<"-------------"<<endl;
uniquePtr1();
#else
normal();
#endif
//一定要加上这句，不然底层context会自己帮忙释放未释放的内存，
//显示调用就意味着内存需要手动自己释放
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include<cstdio>
#include<memory>
#include<vector>
#include<functional>
#include<iostream>
using namespace std;
using fp = void(*)(int*);
__global__ void
test(int *d_data){
printf("hello world\n");
for(int i = 0;i<10;i++)
printf("%d:%d\n",i,d_data[i]);
}
int uniquePtr(){
cout<<"uniquePtr"<<endl;
int *d_data0;
function<void(int*)> lambda = [](int*p){hipFree(p);};
unique_ptr<int,function<void(int*)>> d_data{nullptr, lambda};
hipMalloc((void**)&d_data0,sizeof(int)*10);
d_data.reset(d_data0);
//交给unique_ptr做指针维护
// unique_ptr 的生命周期要与cudaDeviceReset一起考虑，
//cudaDeviceReset是将上下文都重置，如果之前并未执行cudaFree则会造成内存泄漏
// 但是，如果不调用cudaDeviceReset,其会在main函数生命周期之后执行
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
hipMemcpy(d_data.get(),h_data,sizeof(int)*10,hipMemcpyHostToDevice);
test<<<1,1>>>(d_data.get());
hipDeviceSynchronize();
return 0;
}
int uniquePtr1(){
cout<<"uniquePtr1"<<endl;
function<void(int*)> lambda = [](int*p){hipFree(p);};
vector<unique_ptr<int,function<void(int*)>> > vec;
for(int i=0; i<2;i++){
vec.emplace_back(nullptr,lambda);
int* tmp;
hipMalloc((void**)&tmp,sizeof(int)*10);
vec[i].reset(tmp);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
hipMemcpy(vec[i].get(),h_data,sizeof(int)*10,hipMemcpyHostToDevice);
test<<<1,1>>>(vec[i].get());
}
hipDeviceSynchronize();
return 0;
}
int normal(){
cout<<"normal"<<endl;
int *d_data;
// 故意缺少cudaFree，调用cuda-memcheck
hipMalloc((void**)&d_data,sizeof(int)*10);
int h_data[10] = {1,2,3,4,5,6,7,8,9,10};
hipMemcpy(d_data,h_data,sizeof(int)*10,hipMemcpyHostToDevice);
test<<<1,1>>>(d_data);
hipDeviceSynchronize();
return 0;
}
int main(){
#ifdef UNIQUE
uniquePtr();
cout<<"-------------"<<endl;
uniquePtr1();
#else
normal();
#endif
//一定要加上这句，不然底层context会自己帮忙释放未释放的内存，
//显示调用就意味着内存需要手动自己释放
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define SIZE 8
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]);
int main() {
int vectorA[SIZE];
int vectorB[SIZE];
int vectorAns[SIZE];
int i;
for (i = 0; i < SIZE; i++) {
vectorA[i] = i;
vectorB[i] = SIZE - i;
}
int *d_A;
int *d_B;
int *d_C;
//allocate memmory
cudaMalloc((void **) &d_A, sizeof(int) * SIZE);
cudaMalloc((void **) &d_B, sizeof(int) * SIZE);
cudaMalloc((void **) &d_C, sizeof(int) * SIZE);
//copy inputs from RAM to GPU
cudaMemcpy(d_A, vectorA, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, vectorB, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
//calculation function
addVector<<< 1, SIZE >>> (d_C, d_A, d_B);
//copy back to RAM
cudaMemcpy(vectorAns, d_C, sizeof(int) * SIZE, cudaMemcpyDeviceToHost);
//cuda free
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("Answer is : \n");
for (i = 0; i < SIZE; i++) {
printf("%d ", vectorAns[i]);
}
printf("\n");
return 0;
}
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]) {
int i = threadIdx.x;
vectorAns[i] = vectorA[i] + vectorB[i];
} | code for sm_80
Function : _Z9addVectorPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define SIZE 8
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]);
int main() {
int vectorA[SIZE];
int vectorB[SIZE];
int vectorAns[SIZE];
int i;
for (i = 0; i < SIZE; i++) {
vectorA[i] = i;
vectorB[i] = SIZE - i;
}
int *d_A;
int *d_B;
int *d_C;
//allocate memmory
cudaMalloc((void **) &d_A, sizeof(int) * SIZE);
cudaMalloc((void **) &d_B, sizeof(int) * SIZE);
cudaMalloc((void **) &d_C, sizeof(int) * SIZE);
//copy inputs from RAM to GPU
cudaMemcpy(d_A, vectorA, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, vectorB, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
//calculation function
addVector<<< 1, SIZE >>> (d_C, d_A, d_B);
//copy back to RAM
cudaMemcpy(vectorAns, d_C, sizeof(int) * SIZE, cudaMemcpyDeviceToHost);
//cuda free
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("Answer is : \n");
for (i = 0; i < SIZE; i++) {
printf("%d ", vectorAns[i]);
}
printf("\n");
return 0;
}
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]) {
int i = threadIdx.x;
vectorAns[i] = vectorA[i] + vectorB[i];
} | .file "tmpxft_000217bd_00000000-6_arr_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addVectorPiS_S_PiS_S_
.type _Z32__device_stub__Z9addVectorPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addVectorPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9addVectorPiS_S_PiS_S_, .-_Z32__device_stub__Z9addVectorPiS_S_PiS_S_
.globl _Z9addVectorPiS_S_
.type _Z9addVectorPiS_S_, @function
_Z9addVectorPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addVectorPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addVectorPiS_S_, .-_Z9addVectorPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Answer is : \n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $8, %ecx
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, 80(%rsp,%rax,4)
addq $1, %rax
cmpq $8, %rax
jne .L12
movq %rsp, %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 144(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9addVectorPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9addVectorPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define SIZE 8
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]);
int main() {
int vectorA[SIZE];
int vectorB[SIZE];
int vectorAns[SIZE];
int i;
for (i = 0; i < SIZE; i++) {
vectorA[i] = i;
vectorB[i] = SIZE - i;
}
int *d_A;
int *d_B;
int *d_C;
//allocate memmory
cudaMalloc((void **) &d_A, sizeof(int) * SIZE);
cudaMalloc((void **) &d_B, sizeof(int) * SIZE);
cudaMalloc((void **) &d_C, sizeof(int) * SIZE);
//copy inputs from RAM to GPU
cudaMemcpy(d_A, vectorA, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, vectorB, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
//calculation function
addVector<<< 1, SIZE >>> (d_C, d_A, d_B);
//copy back to RAM
cudaMemcpy(vectorAns, d_C, sizeof(int) * SIZE, cudaMemcpyDeviceToHost);
//cuda free
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("Answer is : \n");
for (i = 0; i < SIZE; i++) {
printf("%d ", vectorAns[i]);
}
printf("\n");
return 0;
}
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]) {
int i = threadIdx.x;
vectorAns[i] = vectorA[i] + vectorB[i];
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 8
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]);
int main() {
int vectorA[SIZE];
int vectorB[SIZE];
int vectorAns[SIZE];
int i;
for (i = 0; i < SIZE; i++) {
vectorA[i] = i;
vectorB[i] = SIZE - i;
}
int *d_A;
int *d_B;
int *d_C;
//allocate memmory
hipMalloc((void **) &d_A, sizeof(int) * SIZE);
hipMalloc((void **) &d_B, sizeof(int) * SIZE);
hipMalloc((void **) &d_C, sizeof(int) * SIZE);
//copy inputs from RAM to GPU
hipMemcpy(d_A, vectorA, sizeof(int) * SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_B, vectorB, sizeof(int) * SIZE, hipMemcpyHostToDevice);
//calculation function
addVector<<< 1, SIZE >>> (d_C, d_A, d_B);
//copy back to RAM
hipMemcpy(vectorAns, d_C, sizeof(int) * SIZE, hipMemcpyDeviceToHost);
//cuda free
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Answer is : \n");
for (i = 0; i < SIZE; i++) {
printf("%d ", vectorAns[i]);
}
printf("\n");
return 0;
}
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]) {
int i = threadIdx.x;
vectorAns[i] = vectorA[i] + vectorB[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 8
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]);
int main() {
int vectorA[SIZE];
int vectorB[SIZE];
int vectorAns[SIZE];
int i;
for (i = 0; i < SIZE; i++) {
vectorA[i] = i;
vectorB[i] = SIZE - i;
}
int *d_A;
int *d_B;
int *d_C;
//allocate memmory
hipMalloc((void **) &d_A, sizeof(int) * SIZE);
hipMalloc((void **) &d_B, sizeof(int) * SIZE);
hipMalloc((void **) &d_C, sizeof(int) * SIZE);
//copy inputs from RAM to GPU
hipMemcpy(d_A, vectorA, sizeof(int) * SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_B, vectorB, sizeof(int) * SIZE, hipMemcpyHostToDevice);
//calculation function
addVector<<< 1, SIZE >>> (d_C, d_A, d_B);
//copy back to RAM
hipMemcpy(vectorAns, d_C, sizeof(int) * SIZE, hipMemcpyDeviceToHost);
//cuda free
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Answer is : \n");
for (i = 0; i < SIZE; i++) {
printf("%d ", vectorAns[i]);
}
printf("\n");
return 0;
}
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]) {
int i = threadIdx.x;
vectorAns[i] = vectorA[i] + vectorB[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPiS_S_
.globl _Z9addVectorPiS_S_
.p2align 8
.type _Z9addVectorPiS_S_,@function
_Z9addVectorPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPiS_S_, .Lfunc_end0-_Z9addVectorPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addVectorPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 8
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]);
int main() {
int vectorA[SIZE];
int vectorB[SIZE];
int vectorAns[SIZE];
int i;
for (i = 0; i < SIZE; i++) {
vectorA[i] = i;
vectorB[i] = SIZE - i;
}
int *d_A;
int *d_B;
int *d_C;
//allocate memmory
hipMalloc((void **) &d_A, sizeof(int) * SIZE);
hipMalloc((void **) &d_B, sizeof(int) * SIZE);
hipMalloc((void **) &d_C, sizeof(int) * SIZE);
//copy inputs from RAM to GPU
hipMemcpy(d_A, vectorA, sizeof(int) * SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_B, vectorB, sizeof(int) * SIZE, hipMemcpyHostToDevice);
//calculation function
addVector<<< 1, SIZE >>> (d_C, d_A, d_B);
//copy back to RAM
hipMemcpy(vectorAns, d_C, sizeof(int) * SIZE, hipMemcpyDeviceToHost);
//cuda free
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("Answer is : \n");
for (i = 0; i < SIZE; i++) {
printf("%d ", vectorAns[i]);
}
printf("\n");
return 0;
}
__global__ void addVector(int vectorAns[SIZE], int vectorA[SIZE], int vectorB[SIZE]) {
int i = threadIdx.x;
vectorAns[i] = vectorA[i] + vectorB[i];
} | .text
.file "arr_add.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
movl $8, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 160(%rsp,%rcx,4)
movl %eax, 128(%rsp,%rcx,4)
incq %rcx
decq %rax
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addVectorPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB0_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addVectorPiS_S_ # -- Begin function _Z24__device_stub__addVectorPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPiS_S_,@function
_Z24__device_stub__addVectorPiS_S_: # @_Z24__device_stub__addVectorPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__addVectorPiS_S_, .Lfunc_end1-_Z24__device_stub__addVectorPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPiS_S_,@object # @_Z9addVectorPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addVectorPiS_S_
.p2align 3, 0x0
_Z9addVectorPiS_S_:
.quad _Z24__device_stub__addVectorPiS_S_
.size _Z9addVectorPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addVectorPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Answer is : "
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addVectorPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPiS_S_
.globl _Z9addVectorPiS_S_
.p2align 8
.type _Z9addVectorPiS_S_,@function
_Z9addVectorPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPiS_S_, .Lfunc_end0-_Z9addVectorPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addVectorPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000217bd_00000000-6_arr_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addVectorPiS_S_PiS_S_
.type _Z32__device_stub__Z9addVectorPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addVectorPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9addVectorPiS_S_PiS_S_, .-_Z32__device_stub__Z9addVectorPiS_S_PiS_S_
.globl _Z9addVectorPiS_S_
.type _Z9addVectorPiS_S_, @function
_Z9addVectorPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addVectorPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addVectorPiS_S_, .-_Z9addVectorPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Answer is : \n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $8, %ecx
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, 80(%rsp,%rax,4)
addq $1, %rax
cmpq $8, %rax
jne .L12
movq %rsp, %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 144(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9addVectorPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9addVectorPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "arr_add.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
movl $8, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 160(%rsp,%rcx,4)
movl %eax, 128(%rsp,%rcx,4)
incq %rcx
decq %rax
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addVectorPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB0_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addVectorPiS_S_ # -- Begin function _Z24__device_stub__addVectorPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPiS_S_,@function
_Z24__device_stub__addVectorPiS_S_: # @_Z24__device_stub__addVectorPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__addVectorPiS_S_, .Lfunc_end1-_Z24__device_stub__addVectorPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPiS_S_,@object # @_Z9addVectorPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addVectorPiS_S_
.p2align 3, 0x0
_Z9addVectorPiS_S_:
.quad _Z24__device_stub__addVectorPiS_S_
.size _Z9addVectorPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addVectorPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Answer is : "
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Implementation of SAXPY accelerated with CUDA.
A CPU implementation is also included for comparison.
No timing calls or error checks in this version, for clarity.
Compile on monk with:
nvcc -arch=sm_20 -O2 saxpy_cuda.cu
*/
#include <cuda.h> /* CUDA runtime API */
#include <cstdio>
void saxpy_cpu(float *vecY, float *vecX, float alpha, int n)
{
int i;
for (i = 0; i < n; i++)
vecY[i] = alpha * vecX[i] + vecY[i];
}
__global__ void saxpy_gpu(float *vecY, float *vecX, float alpha ,int n)
{
int i;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
vecY[i] = alpha * vecX[i] + vecY[i];
}
int main(int argc, char *argv[])
{
float *x_host, *y_host; /* arrays for computation on host*/
float *x_dev, *y_dev; /* arrays for computation on device */
float *y_shadow; /* host-side copy of device results */
int n = 32*1024;
float alpha = 0.5f;
int nerror;
size_t memsize;
int i, blockSize, nBlocks;
memsize = n * sizeof(float);
/* allocate arrays on host */
x_host = (float *)malloc(memsize);
y_host = (float *)malloc(memsize);
y_shadow = (float *)malloc(memsize);
/* allocate arrays on device */
cudaMalloc((void **) &x_dev, memsize);
cudaMalloc((void **) &y_dev, memsize);
/* catch any errors */
/* initialize arrays on host */
for ( i = 0; i < n; i++)
{
x_host[i] = rand() / (float)RAND_MAX;
y_host[i] = rand() / (float)RAND_MAX;
}
/* copy arrays to device memory (synchronous) */
cudaMemcpy(x_dev, x_host, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(y_dev, y_host, memsize, cudaMemcpyHostToDevice);
/* set up device execution configuration */
blockSize = 512;
nBlocks = n / blockSize + (n % blockSize > 0);
/* execute kernel (asynchronous!) */
saxpy_gpu<<<nBlocks, blockSize>>>(y_dev, x_dev, alpha, n);
/* execute host version (i.e. baseline reference results) */
saxpy_cpu(y_host, x_host, alpha, n);
/* retrieve results from device (synchronous) */
cudaMemcpy(y_shadow, y_dev, memsize, cudaMemcpyDeviceToHost);
/* guarantee synchronization */
cudaDeviceSynchronize();
/* check results */
nerror=0;
for(i=0; i < n; i++)
{
if(y_shadow[i]!=y_host[i]) nerror=nerror+1;
}
printf("test comparison shows %d errors\n",nerror);
/* free memory */
cudaFree(x_dev);
cudaFree(y_dev);
free(x_host);
free(y_host);
free(y_shadow);
return 0;
} | code for sm_80
Function : _Z9saxpy_gpuPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Implementation of SAXPY accelerated with CUDA.
A CPU implementation is also included for comparison.
No timing calls or error checks in this version, for clarity.
Compile on monk with:
nvcc -arch=sm_20 -O2 saxpy_cuda.cu
*/
#include <cuda.h> /* CUDA runtime API */
#include <cstdio>
void saxpy_cpu(float *vecY, float *vecX, float alpha, int n)
{
int i;
for (i = 0; i < n; i++)
vecY[i] = alpha * vecX[i] + vecY[i];
}
__global__ void saxpy_gpu(float *vecY, float *vecX, float alpha ,int n)
{
int i;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
vecY[i] = alpha * vecX[i] + vecY[i];
}
int main(int argc, char *argv[])
{
float *x_host, *y_host; /* arrays for computation on host*/
float *x_dev, *y_dev; /* arrays for computation on device */
float *y_shadow; /* host-side copy of device results */
int n = 32*1024;
float alpha = 0.5f;
int nerror;
size_t memsize;
int i, blockSize, nBlocks;
memsize = n * sizeof(float);
/* allocate arrays on host */
x_host = (float *)malloc(memsize);
y_host = (float *)malloc(memsize);
y_shadow = (float *)malloc(memsize);
/* allocate arrays on device */
cudaMalloc((void **) &x_dev, memsize);
cudaMalloc((void **) &y_dev, memsize);
/* catch any errors */
/* initialize arrays on host */
for ( i = 0; i < n; i++)
{
x_host[i] = rand() / (float)RAND_MAX;
y_host[i] = rand() / (float)RAND_MAX;
}
/* copy arrays to device memory (synchronous) */
cudaMemcpy(x_dev, x_host, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(y_dev, y_host, memsize, cudaMemcpyHostToDevice);
/* set up device execution configuration */
blockSize = 512;
nBlocks = n / blockSize + (n % blockSize > 0);
/* execute kernel (asynchronous!) */
saxpy_gpu<<<nBlocks, blockSize>>>(y_dev, x_dev, alpha, n);
/* execute host version (i.e. baseline reference results) */
saxpy_cpu(y_host, x_host, alpha, n);
/* retrieve results from device (synchronous) */
cudaMemcpy(y_shadow, y_dev, memsize, cudaMemcpyDeviceToHost);
/* guarantee synchronization */
cudaDeviceSynchronize();
/* check results */
nerror=0;
for(i=0; i < n; i++)
{
if(y_shadow[i]!=y_host[i]) nerror=nerror+1;
}
printf("test comparison shows %d errors\n",nerror);
/* free memory */
cudaFree(x_dev);
cudaFree(y_dev);
free(x_host);
free(y_host);
free(y_shadow);
return 0;
} | .file "tmpxft_001333b9_00000000-6_saxpy_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9saxpy_cpuPfS_fi
.type _Z9saxpy_cpuPfS_fi, @function
_Z9saxpy_cpuPfS_fi:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L5:
movaps %xmm0, %xmm1
mulss (%rsi,%rax), %xmm1
addss (%rdi,%rax), %xmm1
movss %xmm1, (%rdi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9saxpy_cpuPfS_fi, .-_Z9saxpy_cpuPfS_fi
.globl _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
.type _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi, @function
_Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9saxpy_gpuPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi, .-_Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
.globl _Z9saxpy_gpuPfS_fi
.type _Z9saxpy_gpuPfS_fi, @function
_Z9saxpy_gpuPfS_fi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9saxpy_gpuPfS_fi, .-_Z9saxpy_gpuPfS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "test comparison shows %d errors\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $131072, %edi
call malloc@PLT
movq %rax, %r13
movl $131072, %edi
call malloc@PLT
movq %rax, %rbp
movl $131072, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $131072, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $131072, %rbx
jne .L16
movl $1, %ecx
movl $131072, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $131072, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L17:
movl $32768, %edx
movss .LC1(%rip), %xmm0
movq %r13, %rsi
movq %rbp, %rdi
call _Z9saxpy_cpuPfS_fi
movl $2, %ecx
movl $131072, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
movl $0, %edx
jmp .L20
.L26:
movl $32768, %edx
movss .LC1(%rip), %xmm0
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
jmp .L17
.L22:
addl $1, %edx
.L18:
addq $4, %rax
cmpq $131072, %rax
je .L27
.L20:
movss (%r12,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L22
je .L18
jmp .L22
.L27:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z9saxpy_gpuPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9saxpy_gpuPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Implementation of SAXPY accelerated with CUDA.
A CPU implementation is also included for comparison.
No timing calls or error checks in this version, for clarity.
Compile on monk with:
nvcc -arch=sm_20 -O2 saxpy_cuda.cu
*/
#include <cuda.h> /* CUDA runtime API */
#include <cstdio>
void saxpy_cpu(float *vecY, float *vecX, float alpha, int n)
{
int i;
for (i = 0; i < n; i++)
vecY[i] = alpha * vecX[i] + vecY[i];
}
__global__ void saxpy_gpu(float *vecY, float *vecX, float alpha ,int n)
{
int i;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
vecY[i] = alpha * vecX[i] + vecY[i];
}
int main(int argc, char *argv[])
{
float *x_host, *y_host; /* arrays for computation on host*/
float *x_dev, *y_dev; /* arrays for computation on device */
float *y_shadow; /* host-side copy of device results */
int n = 32*1024;
float alpha = 0.5f;
int nerror;
size_t memsize;
int i, blockSize, nBlocks;
memsize = n * sizeof(float);
/* allocate arrays on host */
x_host = (float *)malloc(memsize);
y_host = (float *)malloc(memsize);
y_shadow = (float *)malloc(memsize);
/* allocate arrays on device */
cudaMalloc((void **) &x_dev, memsize);
cudaMalloc((void **) &y_dev, memsize);
/* catch any errors */
/* initialize arrays on host */
for ( i = 0; i < n; i++)
{
x_host[i] = rand() / (float)RAND_MAX;
y_host[i] = rand() / (float)RAND_MAX;
}
/* copy arrays to device memory (synchronous) */
cudaMemcpy(x_dev, x_host, memsize, cudaMemcpyHostToDevice);
cudaMemcpy(y_dev, y_host, memsize, cudaMemcpyHostToDevice);
/* set up device execution configuration */
blockSize = 512;
nBlocks = n / blockSize + (n % blockSize > 0);
/* execute kernel (asynchronous!) */
saxpy_gpu<<<nBlocks, blockSize>>>(y_dev, x_dev, alpha, n);
/* execute host version (i.e. baseline reference results) */
saxpy_cpu(y_host, x_host, alpha, n);
/* retrieve results from device (synchronous) */
cudaMemcpy(y_shadow, y_dev, memsize, cudaMemcpyDeviceToHost);
/* guarantee synchronization */
cudaDeviceSynchronize();
/* check results */
nerror=0;
for(i=0; i < n; i++)
{
if(y_shadow[i]!=y_host[i]) nerror=nerror+1;
}
printf("test comparison shows %d errors\n",nerror);
/* free memory */
cudaFree(x_dev);
cudaFree(y_dev);
free(x_host);
free(y_host);
free(y_shadow);
return 0;
} | /*
Implementation of SAXPY accelerated with CUDA.
A CPU implementation is also included for comparison.
No timing calls or error checks in this version, for clarity.
Compile on monk with:
nvcc -arch=sm_20 -O2 saxpy_cuda.cu
*/
#include <hip/hip_runtime.h> /* CUDA runtime API */
#include <cstdio>
void saxpy_cpu(float *vecY, float *vecX, float alpha, int n)
{
int i;
for (i = 0; i < n; i++)
vecY[i] = alpha * vecX[i] + vecY[i];
}
__global__ void saxpy_gpu(float *vecY, float *vecX, float alpha ,int n)
{
int i;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
vecY[i] = alpha * vecX[i] + vecY[i];
}
int main(int argc, char *argv[])
{
float *x_host, *y_host; /* arrays for computation on host*/
float *x_dev, *y_dev; /* arrays for computation on device */
float *y_shadow; /* host-side copy of device results */
int n = 32*1024;
float alpha = 0.5f;
int nerror;
size_t memsize;
int i, blockSize, nBlocks;
memsize = n * sizeof(float);
/* allocate arrays on host */
x_host = (float *)malloc(memsize);
y_host = (float *)malloc(memsize);
y_shadow = (float *)malloc(memsize);
/* allocate arrays on device */
hipMalloc((void **) &x_dev, memsize);
hipMalloc((void **) &y_dev, memsize);
/* catch any errors */
/* initialize arrays on host */
for ( i = 0; i < n; i++)
{
x_host[i] = rand() / (float)RAND_MAX;
y_host[i] = rand() / (float)RAND_MAX;
}
/* copy arrays to device memory (synchronous) */
hipMemcpy(x_dev, x_host, memsize, hipMemcpyHostToDevice);
hipMemcpy(y_dev, y_host, memsize, hipMemcpyHostToDevice);
/* set up device execution configuration */
blockSize = 512;
nBlocks = n / blockSize + (n % blockSize > 0);
/* execute kernel (asynchronous!) */
saxpy_gpu<<<nBlocks, blockSize>>>(y_dev, x_dev, alpha, n);
/* execute host version (i.e. baseline reference results) */
saxpy_cpu(y_host, x_host, alpha, n);
/* retrieve results from device (synchronous) */
hipMemcpy(y_shadow, y_dev, memsize, hipMemcpyDeviceToHost);
/* guarantee synchronization */
hipDeviceSynchronize();
/* check results */
nerror=0;
for(i=0; i < n; i++)
{
if(y_shadow[i]!=y_host[i]) nerror=nerror+1;
}
printf("test comparison shows %d errors\n",nerror);
/* free memory */
hipFree(x_dev);
hipFree(y_dev);
free(x_host);
free(y_host);
free(y_shadow);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Implementation of SAXPY accelerated with CUDA.
A CPU implementation is also included for comparison.
No timing calls or error checks in this version, for clarity.
Compile on monk with:
nvcc -arch=sm_20 -O2 saxpy_cuda.cu
*/
#include <hip/hip_runtime.h> /* CUDA runtime API */
#include <cstdio>
void saxpy_cpu(float *vecY, float *vecX, float alpha, int n)
{
int i;
for (i = 0; i < n; i++)
vecY[i] = alpha * vecX[i] + vecY[i];
}
__global__ void saxpy_gpu(float *vecY, float *vecX, float alpha ,int n)
{
int i;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
vecY[i] = alpha * vecX[i] + vecY[i];
}
int main(int argc, char *argv[])
{
float *x_host, *y_host; /* arrays for computation on host*/
float *x_dev, *y_dev; /* arrays for computation on device */
float *y_shadow; /* host-side copy of device results */
int n = 32*1024;
float alpha = 0.5f;
int nerror;
size_t memsize;
int i, blockSize, nBlocks;
memsize = n * sizeof(float);
/* allocate arrays on host */
x_host = (float *)malloc(memsize);
y_host = (float *)malloc(memsize);
y_shadow = (float *)malloc(memsize);
/* allocate arrays on device */
hipMalloc((void **) &x_dev, memsize);
hipMalloc((void **) &y_dev, memsize);
/* catch any errors */
/* initialize arrays on host */
for ( i = 0; i < n; i++)
{
x_host[i] = rand() / (float)RAND_MAX;
y_host[i] = rand() / (float)RAND_MAX;
}
/* copy arrays to device memory (synchronous) */
hipMemcpy(x_dev, x_host, memsize, hipMemcpyHostToDevice);
hipMemcpy(y_dev, y_host, memsize, hipMemcpyHostToDevice);
/* set up device execution configuration */
blockSize = 512;
nBlocks = n / blockSize + (n % blockSize > 0);
/* execute kernel (asynchronous!) */
saxpy_gpu<<<nBlocks, blockSize>>>(y_dev, x_dev, alpha, n);
/* execute host version (i.e. baseline reference results) */
saxpy_cpu(y_host, x_host, alpha, n);
/* retrieve results from device (synchronous) */
hipMemcpy(y_shadow, y_dev, memsize, hipMemcpyDeviceToHost);
/* guarantee synchronization */
hipDeviceSynchronize();
/* check results */
nerror=0;
for(i=0; i < n; i++)
{
if(y_shadow[i]!=y_host[i]) nerror=nerror+1;
}
printf("test comparison shows %d errors\n",nerror);
/* free memory */
hipFree(x_dev);
hipFree(y_dev);
free(x_host);
free(y_host);
free(y_shadow);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9saxpy_gpuPfS_fi
.globl _Z9saxpy_gpuPfS_fi
.p2align 8
.type _Z9saxpy_gpuPfS_fi,@function
_Z9saxpy_gpuPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9saxpy_gpuPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9saxpy_gpuPfS_fi, .Lfunc_end0-_Z9saxpy_gpuPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9saxpy_gpuPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9saxpy_gpuPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Implementation of SAXPY accelerated with CUDA.
A CPU implementation is also included for comparison.
No timing calls or error checks in this version, for clarity.
Compile on monk with:
nvcc -arch=sm_20 -O2 saxpy_cuda.cu
*/
#include <hip/hip_runtime.h> /* CUDA runtime API */
#include <cstdio>
void saxpy_cpu(float *vecY, float *vecX, float alpha, int n)
{
int i;
for (i = 0; i < n; i++)
vecY[i] = alpha * vecX[i] + vecY[i];
}
__global__ void saxpy_gpu(float *vecY, float *vecX, float alpha ,int n)
{
int i;
i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
vecY[i] = alpha * vecX[i] + vecY[i];
}
int main(int argc, char *argv[])
{
float *x_host, *y_host; /* arrays for computation on host*/
float *x_dev, *y_dev; /* arrays for computation on device */
float *y_shadow; /* host-side copy of device results */
int n = 32*1024;
float alpha = 0.5f;
int nerror;
size_t memsize;
int i, blockSize, nBlocks;
memsize = n * sizeof(float);
/* allocate arrays on host */
x_host = (float *)malloc(memsize);
y_host = (float *)malloc(memsize);
y_shadow = (float *)malloc(memsize);
/* allocate arrays on device */
hipMalloc((void **) &x_dev, memsize);
hipMalloc((void **) &y_dev, memsize);
/* catch any errors */
/* initialize arrays on host */
for ( i = 0; i < n; i++)
{
x_host[i] = rand() / (float)RAND_MAX;
y_host[i] = rand() / (float)RAND_MAX;
}
/* copy arrays to device memory (synchronous) */
hipMemcpy(x_dev, x_host, memsize, hipMemcpyHostToDevice);
hipMemcpy(y_dev, y_host, memsize, hipMemcpyHostToDevice);
/* set up device execution configuration */
blockSize = 512;
nBlocks = n / blockSize + (n % blockSize > 0);
/* execute kernel (asynchronous!) */
saxpy_gpu<<<nBlocks, blockSize>>>(y_dev, x_dev, alpha, n);
/* execute host version (i.e. baseline reference results) */
saxpy_cpu(y_host, x_host, alpha, n);
/* retrieve results from device (synchronous) */
hipMemcpy(y_shadow, y_dev, memsize, hipMemcpyDeviceToHost);
/* guarantee synchronization */
hipDeviceSynchronize();
/* check results */
nerror=0;
for(i=0; i < n; i++)
{
if(y_shadow[i]!=y_host[i]) nerror=nerror+1;
}
printf("test comparison shows %d errors\n",nerror);
/* free memory */
hipFree(x_dev);
hipFree(y_dev);
free(x_host);
free(y_host);
free(y_shadow);
return 0;
} | .text
.file "saxpy_cuda.hip"
.globl _Z9saxpy_cpuPfS_fi # -- Begin function _Z9saxpy_cpuPfS_fi
.p2align 4, 0x90
.type _Z9saxpy_cpuPfS_fi,@function
_Z9saxpy_cpuPfS_fi: # @_Z9saxpy_cpuPfS_fi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdi,%rcx,4), %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9saxpy_cpuPfS_fi, .Lfunc_end0-_Z9saxpy_cpuPfS_fi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__saxpy_gpuPfS_fi # -- Begin function _Z24__device_stub__saxpy_gpuPfS_fi
.p2align 4, 0x90
.type _Z24__device_stub__saxpy_gpuPfS_fi,@function
_Z24__device_stub__saxpy_gpuPfS_fi: # @_Z24__device_stub__saxpy_gpuPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9saxpy_gpuPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__saxpy_gpuPfS_fi, .Lfunc_end1-_Z24__device_stub__saxpy_gpuPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r14
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $32768, %r12 # imm = 0x8000
jne .LBB2_1
# %bb.2:
movq 16(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 448(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1056964608, 28(%rsp) # imm = 0x3F000000
movl $32768, 24(%rsp) # imm = 0x8000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9saxpy_gpuPfS_fi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4: # %.lr.ph.i.preheader
xorl %eax, %eax
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%r14,%rax,4), %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB2_5
# %bb.6: # %_Z9saxpy_cpuPfS_fi.exit
movq 8(%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %eax, %eax
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%r15,%rax,4), %xmm0
movd %xmm0, %ecx
subl %ecx, %esi
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB2_7
# %bb.8:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9saxpy_gpuPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9saxpy_gpuPfS_fi,@object # @_Z9saxpy_gpuPfS_fi
.section .rodata,"a",@progbits
.globl _Z9saxpy_gpuPfS_fi
.p2align 3, 0x0
_Z9saxpy_gpuPfS_fi:
.quad _Z24__device_stub__saxpy_gpuPfS_fi
.size _Z9saxpy_gpuPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "test comparison shows %d errors\n"
.size .L.str, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9saxpy_gpuPfS_fi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__saxpy_gpuPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9saxpy_gpuPfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9saxpy_gpuPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9saxpy_gpuPfS_fi
.globl _Z9saxpy_gpuPfS_fi
.p2align 8
.type _Z9saxpy_gpuPfS_fi,@function
_Z9saxpy_gpuPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9saxpy_gpuPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9saxpy_gpuPfS_fi, .Lfunc_end0-_Z9saxpy_gpuPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9saxpy_gpuPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9saxpy_gpuPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001333b9_00000000-6_saxpy_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9saxpy_cpuPfS_fi
.type _Z9saxpy_cpuPfS_fi, @function
_Z9saxpy_cpuPfS_fi:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L5:
movaps %xmm0, %xmm1
mulss (%rsi,%rax), %xmm1
addss (%rdi,%rax), %xmm1
movss %xmm1, (%rdi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9saxpy_cpuPfS_fi, .-_Z9saxpy_cpuPfS_fi
.globl _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
.type _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi, @function
_Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9saxpy_gpuPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi, .-_Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
.globl _Z9saxpy_gpuPfS_fi
.type _Z9saxpy_gpuPfS_fi, @function
_Z9saxpy_gpuPfS_fi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9saxpy_gpuPfS_fi, .-_Z9saxpy_gpuPfS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "test comparison shows %d errors\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $131072, %edi
call malloc@PLT
movq %rax, %r13
movl $131072, %edi
call malloc@PLT
movq %rax, %rbp
movl $131072, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $131072, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $131072, %rbx
jne .L16
movl $1, %ecx
movl $131072, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $131072, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L17:
movl $32768, %edx
movss .LC1(%rip), %xmm0
movq %r13, %rsi
movq %rbp, %rdi
call _Z9saxpy_cpuPfS_fi
movl $2, %ecx
movl $131072, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
movl $0, %edx
jmp .L20
.L26:
movl $32768, %edx
movss .LC1(%rip), %xmm0
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9saxpy_gpuPfS_fiPfS_fi
jmp .L17
.L22:
addl $1, %edx
.L18:
addq $4, %rax
cmpq $131072, %rax
je .L27
.L20:
movss (%r12,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L22
je .L18
jmp .L22
.L27:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z9saxpy_gpuPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9saxpy_gpuPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_cuda.hip"
.globl _Z9saxpy_cpuPfS_fi # -- Begin function _Z9saxpy_cpuPfS_fi
.p2align 4, 0x90
.type _Z9saxpy_cpuPfS_fi,@function
_Z9saxpy_cpuPfS_fi: # @_Z9saxpy_cpuPfS_fi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdi,%rcx,4), %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9saxpy_cpuPfS_fi, .Lfunc_end0-_Z9saxpy_cpuPfS_fi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__saxpy_gpuPfS_fi # -- Begin function _Z24__device_stub__saxpy_gpuPfS_fi
.p2align 4, 0x90
.type _Z24__device_stub__saxpy_gpuPfS_fi,@function
_Z24__device_stub__saxpy_gpuPfS_fi: # @_Z24__device_stub__saxpy_gpuPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9saxpy_gpuPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__saxpy_gpuPfS_fi, .Lfunc_end1-_Z24__device_stub__saxpy_gpuPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r14
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $32768, %r12 # imm = 0x8000
jne .LBB2_1
# %bb.2:
movq 16(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 448(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1056964608, 28(%rsp) # imm = 0x3F000000
movl $32768, 24(%rsp) # imm = 0x8000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9saxpy_gpuPfS_fi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4: # %.lr.ph.i.preheader
xorl %eax, %eax
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%r14,%rax,4), %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB2_5
# %bb.6: # %_Z9saxpy_cpuPfS_fi.exit
movq 8(%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %eax, %eax
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%r15,%rax,4), %xmm0
movd %xmm0, %ecx
subl %ecx, %esi
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB2_7
# %bb.8:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9saxpy_gpuPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9saxpy_gpuPfS_fi,@object # @_Z9saxpy_gpuPfS_fi
.section .rodata,"a",@progbits
.globl _Z9saxpy_gpuPfS_fi
.p2align 3, 0x0
_Z9saxpy_gpuPfS_fi:
.quad _Z24__device_stub__saxpy_gpuPfS_fi
.size _Z9saxpy_gpuPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "test comparison shows %d errors\n"
.size .L.str, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9saxpy_gpuPfS_fi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__saxpy_gpuPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9saxpy_gpuPfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Please write your name and net ID below
*
* Last name: Adam
* First name: Steven
* Net ID: sna219
*
*/
/*
* Compile with:
* nvcc -o genprimes genprimes.cu
*/
#include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <math.h>
__global__ static void init(char* primes) {
primes[0] = 0;
primes[1] = 0;
}
__global__ static void removeEvens(char* primes, int N) {
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 4;
if (index <= N)
primes[index] = 0;
}
__global__ static void removeNonPrimes(char* primes, int N, const int limit) {
// get the starting index, remove odds starting at 3
// block 0: 3, 5, 7, 9, 11, 13, ..., 65
// block 1: 67, 69, 71, 73, 75, 77, ..., 129
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 3;
// make sure index won't go out of bounds, also don't start the execution
// on numbers that are already composite
if (index <= limit && primes[index] == 1) {
for (int j=index*2; j <= N; j+=index) {
primes[j] = 0;
}
}
}
// query the Device and decide on the block size
__host__ int checkDevice() {
int devID = 0; // the default device ID
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devID);
return (deviceProp.major < 2) ? 16 : 32;
}
int main(int argc, char * argv[]) {
unsigned int N;
N = (unsigned int) atoi(argv[1]);
// create array of chars; 1 is prime
// we will set non primes to 0
char* primes = new char[N+1];
for(int j=2; j <= N; j++) {
primes[j] = 1;
}
// allocate device memory
char* d_primes = NULL;
int sizePrimes = sizeof(char) * N;
int limit = floor((N+1)/2); //only need to compute up to this point
cudaMalloc(&d_primes, sizePrimes);
cudaMemset(d_primes, 1, sizePrimes);
int blocksize = checkDevice();
if (blocksize == EXIT_FAILURE)
return 1;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil((limit + dimBlock.x)/(double) dimBlock.x) / (double) 2);
dim3 dimGridEven(ceil((N + dimBlock.x)/(double) dimBlock.x) / (double) 2);
init<<<1,1>>>(d_primes); //init shared memory cells in single GPU thread
removeEvens<<<dimGridEven, dimBlock>>>(d_primes, N);
removeNonPrimes<<<dimGrid, dimBlock>>>(d_primes, N, limit);
cudaMemcpy(primes, d_primes, sizePrimes, cudaMemcpyDeviceToHost);
cudaFree(d_primes);
//print output
std::ofstream f;
std::string filename = std::to_string(N) + ".txt";
f.open (filename);
//skip 0 and 1 are not primes
for(int p=2; p <= N; p++) {
if(primes[p] == 1) {
f << std::to_string(p) << " ";
}
}
f.close();
return 0;
} | code for sm_80
Function : _Z15removeNonPrimesPcii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IADD3 R0, R0, 0x3, R0 ; /* 0x0000000300007810 */
/* 0x001fca0007ffe000 */
/*0060*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x002fca000f8e0200 */
/*0070*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fca00078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f04270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0002 */
/*0130*/ IADD3 R2, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x000fc80007f1e0ff */
/*0140*/ LEA.HI.X.SX32 R3, R5, c[0x0][0x164], 0x1, P0 ; /* 0x0000590005037a11 */
/* 0x000fe200000f0eff */
/*0150*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x000fc800078e0205 */
/*0160*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101104 */
/*0170*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x130 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11removeEvensPci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fc800078e00ff */
/*0040*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R3, R3, 0x4, R3 ; /* 0x0000000403037810 */
/* 0x001fca0007ffe003 */
/*0060*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x002fca000f8e0203 */
/*0070*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4initPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0050*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe2000c101104 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Please write your name and net ID below
*
* Last name: Adam
* First name: Steven
* Net ID: sna219
*
*/
/*
* Compile with:
* nvcc -o genprimes genprimes.cu
*/
#include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <math.h>
__global__ static void init(char* primes) {
primes[0] = 0;
primes[1] = 0;
}
__global__ static void removeEvens(char* primes, int N) {
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 4;
if (index <= N)
primes[index] = 0;
}
__global__ static void removeNonPrimes(char* primes, int N, const int limit) {
// get the starting index, remove odds starting at 3
// block 0: 3, 5, 7, 9, 11, 13, ..., 65
// block 1: 67, 69, 71, 73, 75, 77, ..., 129
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 3;
// make sure index won't go out of bounds, also don't start the execution
// on numbers that are already composite
if (index <= limit && primes[index] == 1) {
for (int j=index*2; j <= N; j+=index) {
primes[j] = 0;
}
}
}
// query the Device and decide on the block size
__host__ int checkDevice() {
int devID = 0; // the default device ID
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devID);
return (deviceProp.major < 2) ? 16 : 32;
}
int main(int argc, char * argv[]) {
unsigned int N;
N = (unsigned int) atoi(argv[1]);
// create array of chars; 1 is prime
// we will set non primes to 0
char* primes = new char[N+1];
for(int j=2; j <= N; j++) {
primes[j] = 1;
}
// allocate device memory
char* d_primes = NULL;
int sizePrimes = sizeof(char) * N;
int limit = floor((N+1)/2); //only need to compute up to this point
cudaMalloc(&d_primes, sizePrimes);
cudaMemset(d_primes, 1, sizePrimes);
int blocksize = checkDevice();
if (blocksize == EXIT_FAILURE)
return 1;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil((limit + dimBlock.x)/(double) dimBlock.x) / (double) 2);
dim3 dimGridEven(ceil((N + dimBlock.x)/(double) dimBlock.x) / (double) 2);
init<<<1,1>>>(d_primes); //init shared memory cells in single GPU thread
removeEvens<<<dimGridEven, dimBlock>>>(d_primes, N);
removeNonPrimes<<<dimGrid, dimBlock>>>(d_primes, N, limit);
cudaMemcpy(primes, d_primes, sizePrimes, cudaMemcpyDeviceToHost);
cudaFree(d_primes);
//print output
std::ofstream f;
std::string filename = std::to_string(N) + ".txt";
f.open (filename);
//skip 0 and 1 are not primes
for(int p=2; p <= N; p++) {
if(primes[p] == 1) {
f << std::to_string(p) << " ";
}
}
f.close();
return 0;
} | .file "tmpxft_00023acd_00000000-6_genprimes.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL4initPc, @function
_ZL4initPc:
.LFB3827:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL4initPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3827:
.size _ZL4initPc, .-_ZL4initPc
.type _ZL11removeEvensPci, @function
_ZL11removeEvensPci:
.LFB3829:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL11removeEvensPci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3829:
.size _ZL11removeEvensPci, .-_ZL11removeEvensPci
.type _ZL15removeNonPrimesPcii, @function
_ZL15removeNonPrimesPcii:
.LFB3831:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, (%rsp)
movl %edx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL15removeNonPrimesPcii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3831:
.size _ZL15removeNonPrimesPcii, .-_ZL15removeNonPrimesPcii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11checkDevicev
.type _Z11checkDevicev, @function
_Z11checkDevicev:
.LFB3800:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $1, 360(%rsp)
movl $32, %eax
movl $16, %edx
cmovle %edx, %eax
movq 1032(%rsp), %rdx
subq %fs:40, %rdx
jne .L26
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size _Z11checkDevicev, .-_Z11checkDevicev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15removeNonPrimesPcii"
.LC1:
.string "_Z11removeEvensPci"
.LC2:
.string "_Z4initPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3833:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15removeNonPrimesPcii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11removeEvensPci(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4initPc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3833:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_,"axG",@progbits,_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_,comdat
.weak _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
.type _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_, @function
_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_:
.LFB3996:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edx, %ecx
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movabsq $3688503277381496880, %rax
movabsq $3976738051646829616, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
movabsq $3544667369688283184, %rax
movabsq $3832902143785906737, %rdx
movq %rax, 16(%rsp)
movq %rdx, 24(%rsp)
movabsq $4121136918051239473, %rax
movabsq $3689066235924983858, %rdx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movabsq $3977301010190316594, %rax
movabsq $3545230328231770162, %rdx
movq %rax, 48(%rsp)
movq %rdx, 56(%rsp)
movabsq $3833465102329393715, %rax
movabsq $4121699876594726451, %rdx
movq %rax, 64(%rsp)
movq %rdx, 72(%rsp)
movabsq $3689629194468470836, %rax
movabsq $3977863968733803572, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movabsq $3545793286775257140, %rax
movabsq $3834028060872880693, %rdx
movq %rax, 96(%rsp)
movq %rdx, 104(%rsp)
movabsq $4122262835138213429, %rax
movabsq $3690192153011957814, %rdx
movq %rax, 112(%rsp)
movq %rdx, 120(%rsp)
movabsq $3978426927277290550, %rax
movabsq $3546356245318744118, %rdx
movq %rax, 128(%rsp)
movq %rdx, 136(%rsp)
movabsq $3834591019416367671, %rax
movabsq $4122825793681700407, %rdx
movq %rax, 144(%rsp)
movq %rdx, 152(%rsp)
movabsq $3690755111555444792, %rax
movabsq $3978989885820777528, %rdx
movq %rax, 160(%rsp)
movq %rdx, 168(%rsp)
movabsq $3546919203862231096, %rax
movabsq $3835153977959854649, %rdx
movq %rax, 176(%rsp)
movq %rdx, 184(%rsp)
movabsq $4122263930388298034, %rax
movabsq $16106987313379638, %rdx
movq %rax, 185(%rsp)
movq %rdx, 193(%rsp)
subl $1, %esi
cmpl $99, %ecx
jbe .L30
.L31:
movl %ecx, %edx
imulq $1374389535, %rdx, %rdx
shrq $37, %rdx
imull $100, %edx, %r8d
movl %ecx, %eax
subl %r8d, %eax
addl %eax, %eax
movl %ecx, %r8d
movl %edx, %ecx
movl %esi, %edx
leal 1(%rax), %r9d
movzbl (%rsp,%r9), %r9d
movb %r9b, (%rdi,%rdx)
leal -1(%rsi), %edx
movl %eax, %eax
movzbl (%rsp,%rax), %eax
movb %al, (%rdi,%rdx)
subl $2, %esi
cmpl $9999, %r8d
ja .L31
.L30:
leal 48(%rcx), %eax
cmpl $9, %ecx
jbe .L33
addl %ecx, %ecx
leal 1(%rcx), %eax
movzbl (%rsp,%rax), %eax
movb %al, 1(%rdi)
movl %ecx, %ecx
movzbl (%rsp,%rcx), %eax
.L33:
movb %al, (%rdi)
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3996:
.size _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_, .-_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
.section .rodata.str1.1
.LC4:
.string ".txt"
.LC5:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3801:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3801
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $712, %rsp
.cfi_def_cfa_offset 768
movq %fs:40, %rax
movq %rax, 696(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 12(%rsp)
movl %eax, %r15d
leal 1(%rax), %r13d
movl %r13d, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %r12
cmpl $1, %ebx
jbe .L39
leaq 2(%rax), %rax
leal -2(%rbx), %edx
leaq 3(%r12,%rdx), %rdx
.L40:
movb $1, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L40
.L39:
movq $0, 40(%rsp)
movslq %ebx, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $1, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
call _Z11checkDevicev
movl %eax, %ebp
cmpl $1, %eax
je .L38
shrl %r13d
movl %eax, 16(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %eax, %eax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
leal 0(%r13,%rbp), %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd %xmm1, 24(%rsp)
divsd %xmm1, %xmm0
call ceil@PLT
mulsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %rax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leal 0(%rbp,%rbx), %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd 24(%rsp), %xmm0
call ceil@PLT
mulsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %rax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L48:
movl 16(%rsp), %eax
movl %eax, 52(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L49:
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L50:
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq 176(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
cmpl $9, %ebx
jbe .L77
cmpl $99, %ebx
jbe .L78
cmpl $999, %ebx
jbe .L79
cmpl $9999, %ebx
jbe .L80
movl %ebx, %eax
movl $1, %esi
movabsq $3777893186295716171, %rcx
.L55:
movl %eax, %eax
mulq %rcx
shrq $11, %rdx
movl %edx, %eax
addl $4, %esi
cmpl $9, %edx
jbe .L51
cmpl $99, %edx
jbe .L52
cmpl $999, %edx
jbe .L53
cmpl $9999, %edx
ja .L55
.L54:
addl $3, %esi
jmp .L51
.L93:
movq 40(%rsp), %rdi
call _ZL4initPc
jmp .L48
.L94:
movl 12(%rsp), %esi
movq 40(%rsp), %rdi
call _ZL11removeEvensPci
jmp .L49
.L95:
movl %r13d, %edx
movl 12(%rsp), %esi
movq 40(%rsp), %rdi
call _ZL15removeNonPrimesPcii
.LEHE0:
jmp .L50
.L78:
movl $1, %esi
.L52:
addl $1, %esi
.L51:
leaq 144(%rsp), %rbp
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movl %esi, %esi
movl $0, %edx
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movl %r15d, %edx
movl 152(%rsp), %esi
movq 144(%rsp), %rdi
call _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc@PLT
.LEHE1:
jmp .L96
.L79:
movl $1, %esi
.L53:
addl $2, %esi
jmp .L51
.L80:
movl $1, %esi
jmp .L54
.L77:
movl $1, %esi
jmp .L51
.L96:
movq %rax, %rsi
leaq 112(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EOS4_@PLT
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 176(%rsp), %rdi
movl $16, %edx
movq %rbp, %rsi
.LEHB2:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@PLT
.LEHE2:
cmpl $1, %ebx
jbe .L59
movl $2, %ebx
leaq 144(%rsp), %rax
movq %rax, 16(%rsp)
leaq 160(%rsp), %rax
movq %rax, 24(%rsp)
movabsq $3777893186295716171, %r13
jmp .L70
.L82:
movl $1, %ebp
.L63:
addl $1, %ebp
.L62:
movq 24(%rsp), %rax
movq %rax, 144(%rsp)
movl 12(%rsp), %eax
leal (%rax,%rbp), %esi
movl $45, %edx
movq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl 12(%rsp), %edi
addq 144(%rsp), %rdi
movl %r14d, %edx
movl %ebp, %esi
call _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_
leaq 176(%rsp), %rdi
movq 152(%rsp), %rdx
movq 144(%rsp), %rsi
.LEHB3:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L97
.L83:
movl $1, %ebp
.L64:
addl $2, %ebp
jmp .L62
.L84:
movl $1, %ebp
jmp .L65
.L81:
movl $1, %ebp
jmp .L62
.L97:
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE3:
movq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L60:
addq $1, %rbx
cmpl %ebx, %r15d
jb .L59
.L70:
cmpb $1, (%r12,%rbx)
jne .L60
movl %ebx, %eax
shrl $31, %eax
movl %eax, 12(%rsp)
movl %ebx, %r14d
negl %r14d
cmovs %ebx, %r14d
cmpl $9, %r14d
jbe .L81
cmpl $99, %r14d
jbe .L82
cmpl $999, %r14d
jbe .L83
cmpl $9999, %r14d
jbe .L84
movl %r14d, %eax
movl $1, %ebp
.L66:
movl %eax, %eax
mulq %r13
shrq $11, %rdx
movl %edx, %eax
addl $4, %ebp
cmpl $9, %edx
jbe .L62
cmpl $99, %edx
jbe .L63
cmpl $999, %edx
jbe .L64
cmpl $9999, %edx
ja .L66
.L65:
addl $3, %ebp
jmp .L62
.L59:
leaq 176(%rsp), %rdi
.LEHB4:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE4:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 176(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movl $0, %ebp
.L38:
movq 696(%rsp), %rax
subq %fs:40, %rax
jne .L98
movl %ebp, %eax
addq $712, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L72:
leaq 176(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 696(%rsp), %rax
subq %fs:40, %rax
je .L75
call __stack_chk_fail@PLT
.L87:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L74:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L72
.L86:
endbr64
movq %rax, %rbx
jmp .L74
.L75:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L98:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3801:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3801-.LLSDACSB3801
.LLSDACSB3801:
.uleb128 .LEHB0-.LFB3801
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3801
.uleb128 .LEHE1-.LEHB1
.uleb128 .L85-.LFB3801
.uleb128 0
.uleb128 .LEHB2-.LFB3801
.uleb128 .LEHE2-.LEHB2
.uleb128 .L86-.LFB3801
.uleb128 0
.uleb128 .LEHB3-.LFB3801
.uleb128 .LEHE3-.LEHB3
.uleb128 .L87-.LFB3801
.uleb128 0
.uleb128 .LEHB4-.LFB3801
.uleb128 .LEHE4-.LEHB4
.uleb128 .L86-.LFB3801
.uleb128 0
.uleb128 .LEHB5-.LFB3801
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.LLSDACSE3801:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1071644672
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Please write your name and net ID below
*
* Last name: Adam
* First name: Steven
* Net ID: sna219
*
*/
/*
* Compile with:
* nvcc -o genprimes genprimes.cu
*/
#include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <math.h>
__global__ static void init(char* primes) {
primes[0] = 0;
primes[1] = 0;
}
__global__ static void removeEvens(char* primes, int N) {
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 4;
if (index <= N)
primes[index] = 0;
}
__global__ static void removeNonPrimes(char* primes, int N, const int limit) {
// get the starting index, remove odds starting at 3
// block 0: 3, 5, 7, 9, 11, 13, ..., 65
// block 1: 67, 69, 71, 73, 75, 77, ..., 129
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 3;
// make sure index won't go out of bounds, also don't start the execution
// on numbers that are already composite
if (index <= limit && primes[index] == 1) {
for (int j=index*2; j <= N; j+=index) {
primes[j] = 0;
}
}
}
// query the Device and decide on the block size
__host__ int checkDevice() {
int devID = 0; // the default device ID
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devID);
return (deviceProp.major < 2) ? 16 : 32;
}
int main(int argc, char * argv[]) {
unsigned int N;
N = (unsigned int) atoi(argv[1]);
// create array of chars; 1 is prime
// we will set non primes to 0
char* primes = new char[N+1];
for(int j=2; j <= N; j++) {
primes[j] = 1;
}
// allocate device memory
char* d_primes = NULL;
int sizePrimes = sizeof(char) * N;
int limit = floor((N+1)/2); //only need to compute up to this point
cudaMalloc(&d_primes, sizePrimes);
cudaMemset(d_primes, 1, sizePrimes);
int blocksize = checkDevice();
if (blocksize == EXIT_FAILURE)
return 1;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil((limit + dimBlock.x)/(double) dimBlock.x) / (double) 2);
dim3 dimGridEven(ceil((N + dimBlock.x)/(double) dimBlock.x) / (double) 2);
init<<<1,1>>>(d_primes); //init shared memory cells in single GPU thread
removeEvens<<<dimGridEven, dimBlock>>>(d_primes, N);
removeNonPrimes<<<dimGrid, dimBlock>>>(d_primes, N, limit);
cudaMemcpy(primes, d_primes, sizePrimes, cudaMemcpyDeviceToHost);
cudaFree(d_primes);
//print output
std::ofstream f;
std::string filename = std::to_string(N) + ".txt";
f.open (filename);
//skip 0 and 1 are not primes
for(int p=2; p <= N; p++) {
if(primes[p] == 1) {
f << std::to_string(p) << " ";
}
}
f.close();
return 0;
} | /*
* Please write your name and net ID below
*
* Last name: Adam
* First name: Steven
* Net ID: sna219
*
*/
/*
* Compile with:
* nvcc -o genprimes genprimes.cu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <math.h>
__global__ static void init(char* primes) {
primes[0] = 0;
primes[1] = 0;
}
__global__ static void removeEvens(char* primes, int N) {
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 4;
if (index <= N)
primes[index] = 0;
}
__global__ static void removeNonPrimes(char* primes, int N, const int limit) {
// get the starting index, remove odds starting at 3
// block 0: 3, 5, 7, 9, 11, 13, ..., 65
// block 1: 67, 69, 71, 73, 75, 77, ..., 129
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 3;
// make sure index won't go out of bounds, also don't start the execution
// on numbers that are already composite
if (index <= limit && primes[index] == 1) {
for (int j=index*2; j <= N; j+=index) {
primes[j] = 0;
}
}
}
// query the Device and decide on the block size
__host__ int checkDevice() {
int devID = 0; // the default device ID
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devID);
return (deviceProp.major < 2) ? 16 : 32;
}
int main(int argc, char * argv[]) {
unsigned int N;
N = (unsigned int) atoi(argv[1]);
// create array of chars; 1 is prime
// we will set non primes to 0
char* primes = new char[N+1];
for(int j=2; j <= N; j++) {
primes[j] = 1;
}
// allocate device memory
char* d_primes = NULL;
int sizePrimes = sizeof(char) * N;
int limit = floor((N+1)/2); //only need to compute up to this point
hipMalloc(&d_primes, sizePrimes);
hipMemset(d_primes, 1, sizePrimes);
int blocksize = checkDevice();
if (blocksize == EXIT_FAILURE)
return 1;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil((limit + dimBlock.x)/(double) dimBlock.x) / (double) 2);
dim3 dimGridEven(ceil((N + dimBlock.x)/(double) dimBlock.x) / (double) 2);
init<<<1,1>>>(d_primes); //init shared memory cells in single GPU thread
removeEvens<<<dimGridEven, dimBlock>>>(d_primes, N);
removeNonPrimes<<<dimGrid, dimBlock>>>(d_primes, N, limit);
hipMemcpy(primes, d_primes, sizePrimes, hipMemcpyDeviceToHost);
hipFree(d_primes);
//print output
std::ofstream f;
std::string filename = std::to_string(N) + ".txt";
f.open (filename);
//skip 0 and 1 are not primes
for(int p=2; p <= N; p++) {
if(primes[p] == 1) {
f << std::to_string(p) << " ";
}
}
f.close();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Please write your name and net ID below
*
* Last name: Adam
* First name: Steven
* Net ID: sna219
*
*/
/*
* Compile with:
* nvcc -o genprimes genprimes.cu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <math.h>
__global__ static void init(char* primes) {
primes[0] = 0;
primes[1] = 0;
}
__global__ static void removeEvens(char* primes, int N) {
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 4;
if (index <= N)
primes[index] = 0;
}
__global__ static void removeNonPrimes(char* primes, int N, const int limit) {
// get the starting index, remove odds starting at 3
// block 0: 3, 5, 7, 9, 11, 13, ..., 65
// block 1: 67, 69, 71, 73, 75, 77, ..., 129
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 3;
// make sure index won't go out of bounds, also don't start the execution
// on numbers that are already composite
if (index <= limit && primes[index] == 1) {
for (int j=index*2; j <= N; j+=index) {
primes[j] = 0;
}
}
}
// query the Device and decide on the block size
__host__ int checkDevice() {
int devID = 0; // the default device ID
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devID);
return (deviceProp.major < 2) ? 16 : 32;
}
int main(int argc, char * argv[]) {
unsigned int N;
N = (unsigned int) atoi(argv[1]);
// create array of chars; 1 is prime
// we will set non primes to 0
char* primes = new char[N+1];
for(int j=2; j <= N; j++) {
primes[j] = 1;
}
// allocate device memory
char* d_primes = NULL;
int sizePrimes = sizeof(char) * N;
int limit = floor((N+1)/2); //only need to compute up to this point
hipMalloc(&d_primes, sizePrimes);
hipMemset(d_primes, 1, sizePrimes);
int blocksize = checkDevice();
if (blocksize == EXIT_FAILURE)
return 1;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil((limit + dimBlock.x)/(double) dimBlock.x) / (double) 2);
dim3 dimGridEven(ceil((N + dimBlock.x)/(double) dimBlock.x) / (double) 2);
init<<<1,1>>>(d_primes); //init shared memory cells in single GPU thread
removeEvens<<<dimGridEven, dimBlock>>>(d_primes, N);
removeNonPrimes<<<dimGrid, dimBlock>>>(d_primes, N, limit);
hipMemcpy(primes, d_primes, sizePrimes, hipMemcpyDeviceToHost);
hipFree(d_primes);
//print output
std::ofstream f;
std::string filename = std::to_string(N) + ".txt";
f.open (filename);
//skip 0 and 1 are not primes
for(int p=2; p <= N; p++) {
if(primes[p] == 1) {
f << std::to_string(p) << " ";
}
}
f.close();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL4initPc,"axG",@progbits,_ZL4initPc,comdat
.globl _ZL4initPc
.p2align 8
.type _ZL4initPc,@function
_ZL4initPc:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b16 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL4initPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL4initPc,"axG",@progbits,_ZL4initPc,comdat
.Lfunc_end0:
.size _ZL4initPc, .Lfunc_end0-_ZL4initPc
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL11removeEvensPci,"axG",@progbits,_ZL11removeEvensPci,comdat
.globl _ZL11removeEvensPci
.p2align 8
.type _ZL11removeEvensPci,@function
_ZL11removeEvensPci:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v1, 1, 4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s3, v0
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11removeEvensPci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11removeEvensPci,"axG",@progbits,_ZL11removeEvensPci,comdat
.Lfunc_end1:
.size _ZL11removeEvensPci, .Lfunc_end1-_ZL11removeEvensPci
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL15removeNonPrimesPcii,"axG",@progbits,_ZL15removeNonPrimesPcii,comdat
.globl _ZL15removeNonPrimesPcii
.p2align 8
.type _ZL15removeNonPrimesPcii,@function
_ZL15removeNonPrimesPcii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 3, v0
v_cmpx_ge_i32_e64 s3, v2
s_cbranch_execz .LBB2_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v2
s_load_b32 s1, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_u8 v4, v[3:4], off
v_lshlrev_b32_e32 v3, 1, v2
v_cmp_ge_i32_e64 s0, s1, v3
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB2_4
v_lshl_add_u32 v1, v1, 2, 4
v_add_nc_u32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_ashrrev_i32_e32 v5, 31, v0
v_add_co_u32 v1, vcc_lo, v1, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, v1, 2
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v6, 0
.LBB2_3:
v_add_nc_u32_e32 v3, v3, v2
global_store_b8 v[0:1], v6, off
v_add_co_u32 v0, s0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, v1, v5, s0
v_cmp_lt_i32_e32 vcc_lo, s1, v3
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB2_3
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL15removeNonPrimesPcii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL15removeNonPrimesPcii,"axG",@progbits,_ZL15removeNonPrimesPcii,comdat
.Lfunc_end2:
.size _ZL15removeNonPrimesPcii, .Lfunc_end2-_ZL15removeNonPrimesPcii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL4initPc
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _ZL4initPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11removeEvensPci
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11removeEvensPci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL15removeNonPrimesPcii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL15removeNonPrimesPcii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Please write your name and net ID below
*
* Last name: Adam
* First name: Steven
* Net ID: sna219
*
*/
/*
* Compile with:
* nvcc -o genprimes genprimes.cu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <math.h>
__global__ static void init(char* primes) {
primes[0] = 0;
primes[1] = 0;
}
__global__ static void removeEvens(char* primes, int N) {
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 4;
if (index <= N)
primes[index] = 0;
}
__global__ static void removeNonPrimes(char* primes, int N, const int limit) {
// get the starting index, remove odds starting at 3
// block 0: 3, 5, 7, 9, 11, 13, ..., 65
// block 1: 67, 69, 71, 73, 75, 77, ..., 129
int index = blockIdx.x * blockDim.x *2 + threadIdx.x + threadIdx.x + 3;
// make sure index won't go out of bounds, also don't start the execution
// on numbers that are already composite
if (index <= limit && primes[index] == 1) {
for (int j=index*2; j <= N; j+=index) {
primes[j] = 0;
}
}
}
// query the Device and decide on the block size
__host__ int checkDevice() {
int devID = 0; // the default device ID
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devID);
return (deviceProp.major < 2) ? 16 : 32;
}
int main(int argc, char * argv[]) {
unsigned int N;
N = (unsigned int) atoi(argv[1]);
// create array of chars; 1 is prime
// we will set non primes to 0
char* primes = new char[N+1];
for(int j=2; j <= N; j++) {
primes[j] = 1;
}
// allocate device memory
char* d_primes = NULL;
int sizePrimes = sizeof(char) * N;
int limit = floor((N+1)/2); //only need to compute up to this point
hipMalloc(&d_primes, sizePrimes);
hipMemset(d_primes, 1, sizePrimes);
int blocksize = checkDevice();
if (blocksize == EXIT_FAILURE)
return 1;
dim3 dimBlock(blocksize);
dim3 dimGrid(ceil((limit + dimBlock.x)/(double) dimBlock.x) / (double) 2);
dim3 dimGridEven(ceil((N + dimBlock.x)/(double) dimBlock.x) / (double) 2);
init<<<1,1>>>(d_primes); //init shared memory cells in single GPU thread
removeEvens<<<dimGridEven, dimBlock>>>(d_primes, N);
removeNonPrimes<<<dimGrid, dimBlock>>>(d_primes, N, limit);
hipMemcpy(primes, d_primes, sizePrimes, hipMemcpyDeviceToHost);
hipFree(d_primes);
//print output
std::ofstream f;
std::string filename = std::to_string(N) + ".txt";
f.open (filename);
//skip 0 and 1 are not primes
for(int p=2; p <= N; p++) {
if(primes[p] == 1) {
f << std::to_string(p) << " ";
}
}
f.close();
return 0;
} | .text
.file "genprimes.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11checkDevicev # -- Begin function _Z11checkDevicev
.p2align 4, 0x90
.type _Z11checkDevicev,@function
_Z11checkDevicev: # @_Z11checkDevicev
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
xorl %eax, %eax
cmpl $2, 368(%rsp)
setge %al
shll $4, %eax
addl $16, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11checkDevicev, .Lfunc_end0-_Z11checkDevicev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r13 # imm = 0x100000000
movq 8(%rsi), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
leal 1(%rax), %r12d
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Znam
movq %rax, %rbx
cmpl $2, %r14d
jb .LBB1_2
# %bb.1: # %.lr.ph.preheader
leaq 2(%rbx), %rdi
leal (%r14,%r13), %edx
decl %edx
.cfi_escape 0x2e, 0x00
movl $1, %esi
callq memset@PLT
.LBB1_2: # %._crit_edge
movq $0, 32(%rsp)
shrl %r12d
movslq %r14d, %r15
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $1, %esi
movq %r15, 136(%rsp) # 8-byte Spill
movq %r15, %rdx
callq hipMemset
.cfi_escape 0x2e, 0x00
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
xorl %eax, %eax
cmpl $2, 504(%rsp)
setge %al
shll $4, %eax
movq %r13, %r15
addq %rax, %r13
addq $16, %r13
leal (%r12,%r13), %eax
cvtsi2sd %rax, %xmm0
movl %r13d, %eax
cvtsi2sd %rax, %xmm1
movsd %xmm1, 128(%rsp) # 8-byte Spill
divsd %xmm1, %xmm0
.cfi_escape 0x2e, 0x00
callq ceil@PLT
mulsd .LCPI1_0(%rip), %xmm0
cvttsd2si %xmm0, %rax
movl %eax, %ebp
movq %r14, 120(%rsp) # 8-byte Spill
leal (%r13,%r14), %eax
movq %r15, %r14
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd 128(%rsp), %xmm0 # 8-byte Folded Reload
.cfi_escape 0x2e, 0x00
callq ceil@PLT
mulsd .LCPI1_0(%rip), %xmm0
cvttsd2si %xmm0, %rax
movl %eax, %r15d
orq %r14, %r15
leaq 1(%r14), %rdi
.cfi_escape 0x2e, 0x00
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq %rax, (%rsp)
movq %rsp, %rax
movq %rax, 48(%rsp)
.cfi_escape 0x2e, 0x00
leaq 144(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 48(%rsp), %r9
movl $_ZL4initPc, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
orq %r14, %rbp
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq %rax, 72(%rsp)
movq 120(%rsp), %rax # 8-byte Reload
movl %eax, 44(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movq %rsp, %rsi
leaq 64(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 144(%rsp), %r9
movl $_ZL11removeEvensPci, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
.cfi_escape 0x2e, 0x00
movl $1, %r14d
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 120(%rsp), %r13 # 8-byte Reload
jne .LBB1_8
# %bb.7:
movq 32(%rsp), %rax
movq %rax, 72(%rsp)
movl %r13d, 44(%rsp)
movl %r12d, 116(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 116(%rsp), %rax
movq %rax, 160(%rsp)
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movq %rsp, %rsi
leaq 64(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 144(%rsp), %r9
movl $_ZL15removeNonPrimesPcii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 32(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq 136(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
leaq 144(%rsp), %rbp
movq %rbp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
cmpl $10, %r13d
jb .LBB1_17
# %bb.9: # %.lr.ph.i.i.preheader
movl $4, %r14d
movl $3518437209, %eax # imm = 0xD1B71759
movl %r13d, %ecx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph.i.i
# =>This Inner Loop Header: Depth=1
cmpl $99, %ecx
jbe .LBB1_11
# %bb.12: # in Loop: Header=BB1_10 Depth=1
cmpl $999, %ecx # imm = 0x3E7
jbe .LBB1_13
# %bb.14: # in Loop: Header=BB1_10 Depth=1
cmpl $10000, %ecx # imm = 0x2710
jb .LBB1_17
# %bb.15: # in Loop: Header=BB1_10 Depth=1
movl %ecx, %edx
imulq %rax, %rdx
shrq $45, %rdx
addl $4, %r14d
cmpl $99999, %ecx # imm = 0x1869F
movl %edx, %ecx
ja .LBB1_10
# %bb.16: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i.loopexit
addl $-3, %r14d
jmp .LBB1_17
.LBB1_11:
addl $-2, %r14d
jmp .LBB1_17
.LBB1_13:
decl %r14d
.LBB1_17: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i
movl %r14d, %r12d
leaq 16(%rsp), %r15
movq %r15, (%rsp)
cmpl $16, %r14d
jb .LBB1_20
# %bb.18:
leaq 1(%r12), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.19: # %.noexc.i
movq %rax, (%rsp)
movq %r12, 16(%rsp)
.LBB1_20:
testq %r12, %r12
je .LBB1_24
# %bb.21:
movq (%rsp), %rdi
cmpl $1, %r12d
jne .LBB1_23
# %bb.22:
movb $0, (%rdi)
jmp .LBB1_24
.LBB1_23:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
.LBB1_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit.i
movq %r12, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%r12)
movq (%rsp), %rax
movl %r13d, %ecx
cmpl $100, %r13d
jb .LBB1_27
# %bb.25: # %.lr.ph.preheader.i.i
movl 8(%rsp), %edx
addl $-2, %edx
movl %r13d, %esi
.p2align 4, 0x90
.LBB1_26: # %.lr.ph.i2.i
# =>This Inner Loop Header: Depth=1
leal 1(%rdx), %edi
movl %esi, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %r8d
movl %esi, %r9d
subl %r8d, %r9d
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%r9,%r9), %r8d
movb %r8b, (%rax,%rdi)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%r9,%r9), %edi
movl %edx, %r8d
movb %dil, (%rax,%r8)
addl $-2, %edx
cmpl $9999, %esi # imm = 0x270F
movl %ecx, %esi
ja .LBB1_26
.LBB1_27: # %._crit_edge.i.i
cmpl $10, %ecx
jb .LBB1_30
# %bb.28:
movl %ecx, %ecx
leaq (%rcx,%rcx), %rdx
movl %edx, %edx
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdx), %edx
movb %dl, 1(%rax)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rcx,%rcx), %ecx
jmp .LBB1_31
.LBB1_30:
orb $48, %cl
.LBB1_31: # %_ZNSt7__cxx119to_stringEj.exit
movb %cl, (%rax)
movq 8(%rsp), %rsi
movq %rsi, %rax
shrq $2, %rax
movabsq $2305843009213693951, %rcx # imm = 0x1FFFFFFFFFFFFFFF
cmpq %rcx, %rax
je .LBB1_32
# %bb.34: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
leaq 4(%rsi), %r14
movq (%rsp), %rax
movl $15, %ecx
cmpq %r15, %rax
je .LBB1_36
# %bb.35: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
movq 16(%rsp), %rcx
.LBB1_36: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
cmpq %rcx, %r14
jbe .LBB1_37
# %bb.38:
.Ltmp3:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $.L.str, %ecx
movl $4, %r8d
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp4:
jmp .LBB1_39
.LBB1_37:
movl $1954051118, (%rax,%rsi) # imm = 0x7478742E
.LBB1_39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc.exit.i
movq %r14, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%r14)
leaq 96(%rsp), %rdi
movq %rdi, 80(%rsp)
movq (%rsp), %rax
cmpq %r15, %rax
je .LBB1_40
# %bb.41: # %.critedge.i.i
movq %rax, 80(%rsp)
movq 16(%rsp), %rax
movq %rax, 96(%rsp)
jmp .LBB1_42
.LBB1_40: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
movq 8(%rsp), %rdx
incq %rdx
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
callq memcpy@PLT
.LBB1_42: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEOS8_PKS5_.exit
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 152(%rsp), %rdi
movq 80(%rsp), %rsi
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp6:
# %bb.43: # %.noexc77
movq 144(%rsp), %rcx
addq -24(%rcx), %rbp
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_45
# %bb.44:
movl 32(%rbp), %esi
orl $4, %esi
.LBB1_45: # %.invoke
.Ltmp7:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp8:
# %bb.46: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode.exit
cmpl $2, %r13d
jae .LBB1_47
.LBB1_53: # %._crit_edge145
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq 152(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp18:
# %bb.54: # %.noexc81
testq %rax, %rax
jne .LBB1_56
# %bb.55:
movq 144(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $144, %rdi
movl 176(%rsp,%rax), %esi
orl $4, %esi
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp20:
.LBB1_56: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_58
# %bb.57: # %.critedge.i.i109
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_58: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit111
.cfi_escape 0x2e, 0x00
leaq 144(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_47: # %.lr.ph144
.cfi_def_cfa_offset 1680
leal 1(%r13), %r12d
movl $2, %r13d
movl $3518437209, %r14d # imm = 0xD1B71759
jmp .LBB1_48
.p2align 4, 0x90
.LBB1_84: # in Loop: Header=BB1_48 Depth=1
incq %r13
cmpq %r12, %r13
je .LBB1_53
.LBB1_48: # =>This Loop Header: Depth=1
# Child Loop BB1_51 Depth 2
# Child Loop BB1_75 Depth 2
cmpb $1, (%rbx,%r13)
jne .LBB1_84
# %bb.49: # in Loop: Header=BB1_48 Depth=1
movl $1, %eax
cmpq $10, %r13
jb .LBB1_66
# %bb.50: # %.lr.ph.i.i86.preheader
# in Loop: Header=BB1_48 Depth=1
movl $4, %eax
movl %r13d, %ecx
.p2align 4, 0x90
.LBB1_51: # %.lr.ph.i.i86
# Parent Loop BB1_48 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $99, %ecx
jbe .LBB1_52
# %bb.61: # in Loop: Header=BB1_51 Depth=2
cmpl $999, %ecx # imm = 0x3E7
jbe .LBB1_62
# %bb.63: # in Loop: Header=BB1_51 Depth=2
cmpl $10000, %ecx # imm = 0x2710
jb .LBB1_66
# %bb.64: # in Loop: Header=BB1_51 Depth=2
movl %ecx, %edx
imulq %r14, %rdx
shrq $45, %rdx
addl $4, %eax
cmpl $99999, %ecx # imm = 0x1869F
movl %edx, %ecx
ja .LBB1_51
# %bb.65: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i89.loopexit
# in Loop: Header=BB1_48 Depth=1
addl $-3, %eax
jmp .LBB1_66
.LBB1_52: # in Loop: Header=BB1_48 Depth=1
addl $-2, %eax
jmp .LBB1_66
.LBB1_62: # in Loop: Header=BB1_48 Depth=1
decl %eax
.p2align 4, 0x90
.LBB1_66: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i89
# in Loop: Header=BB1_48 Depth=1
movl %eax, %ebp
movq %r15, (%rsp)
cmpl $16, %eax
jb .LBB1_69
# %bb.67: # in Loop: Header=BB1_48 Depth=1
leaq 1(%rbp), %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp10:
# %bb.68: # %.noexc.i100
# in Loop: Header=BB1_48 Depth=1
movq %rax, (%rsp)
movq %rbp, 16(%rsp)
.LBB1_69: # in Loop: Header=BB1_48 Depth=1
testq %rbp, %rbp
je .LBB1_73
# %bb.70: # in Loop: Header=BB1_48 Depth=1
movq (%rsp), %rdi
cmpl $1, %ebp
jne .LBB1_72
# %bb.71: # in Loop: Header=BB1_48 Depth=1
movb $45, (%rdi)
jmp .LBB1_73
.LBB1_72: # in Loop: Header=BB1_48 Depth=1
.cfi_escape 0x2e, 0x00
movl $45, %esi
movq %rbp, %rdx
callq memset@PLT
.LBB1_73: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit.i93
# in Loop: Header=BB1_48 Depth=1
movq %rbp, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbp)
movq (%rsp), %rax
movl %r13d, %ecx
cmpq $100, %r13
jb .LBB1_76
# %bb.74: # %.lr.ph.preheader.i.i97
# in Loop: Header=BB1_48 Depth=1
addl $-2, %ebp
movl %r13d, %edx
.p2align 4, 0x90
.LBB1_75: # %.lr.ph.i11.i
# Parent Loop BB1_48 Depth=1
# => This Inner Loop Header: Depth=2
leal 1(%rbp), %esi
movl %edx, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %edi
movl %edx, %r8d
subl %edi, %r8d
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%r8,%r8), %edi
movb %dil, (%rax,%rsi)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%r8,%r8), %esi
movl %ebp, %edi
movb %sil, (%rax,%rdi)
addl $-2, %ebp
cmpl $9999, %edx # imm = 0x270F
movl %ecx, %edx
ja .LBB1_75
.LBB1_76: # %._crit_edge.i.i94
# in Loop: Header=BB1_48 Depth=1
cmpl $10, %ecx
jb .LBB1_79
# %bb.77: # in Loop: Header=BB1_48 Depth=1
movl %ecx, %ecx
leaq (%rcx,%rcx), %rdx
movl %edx, %edx
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdx), %edx
movb %dl, 1(%rax)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rcx,%rcx), %ecx
jmp .LBB1_80
.p2align 4, 0x90
.LBB1_79: # in Loop: Header=BB1_48 Depth=1
orb $48, %cl
.LBB1_80: # %_ZNSt7__cxx119to_stringEi.exit
# in Loop: Header=BB1_48 Depth=1
movb %cl, (%rax)
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 144(%rsp), %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.81: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# in Loop: Header=BB1_48 Depth=1
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp15:
# %bb.82: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_48 Depth=1
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB1_84
# %bb.83: # %.critedge.i.i103
# in Loop: Header=BB1_48 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB1_84
.LBB1_32:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp23:
# %bb.33: # %.noexc
.LBB1_29:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_59:
.Ltmp24:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB1_91
# %bb.60: # %.critedge.i.i83
.cfi_escape 0x2e, 0x00
jmp .LBB1_90
.LBB1_87:
.Ltmp21:
movq %rax, %rbx
jmp .LBB1_88
.LBB1_78:
.Ltmp11:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_85:
.Ltmp16:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB1_88
# %bb.86: # %.critedge.i.i106
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_88:
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_91
# %bb.89: # %.critedge.i.i112
.cfi_escape 0x2e, 0x00
.LBB1_90: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit114
callq _ZdlPv
.LBB1_91: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit114
.cfi_escape 0x2e, 0x00
leaq 144(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp20-.Ltmp5 # Call between .Ltmp5 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp15-.Ltmp12 # Call between .Ltmp12 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Lfunc_end1-.Ltmp23 # Call between .Ltmp23 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZL19__device_stub__initPc
.type _ZL19__device_stub__initPc,@function
_ZL19__device_stub__initPc: # @_ZL19__device_stub__initPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_ZL4initPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _ZL19__device_stub__initPc, .Lfunc_end2-_ZL19__device_stub__initPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__removeEvensPci
.type _ZL26__device_stub__removeEvensPci,@function
_ZL26__device_stub__removeEvensPci: # @_ZL26__device_stub__removeEvensPci
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL11removeEvensPci, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _ZL26__device_stub__removeEvensPci, .Lfunc_end3-_ZL26__device_stub__removeEvensPci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL30__device_stub__removeNonPrimesPcii
.type _ZL30__device_stub__removeNonPrimesPcii,@function
_ZL30__device_stub__removeNonPrimesPcii: # @_ZL30__device_stub__removeNonPrimesPcii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL15removeNonPrimesPcii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _ZL30__device_stub__removeNonPrimesPcii, .Lfunc_end4-_ZL30__device_stub__removeNonPrimesPcii
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end5:
.size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB6_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB6_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB6_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB6_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB6_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB6_6:
movq %rbp, %rdi
incq %rdi
js .LBB6_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB6_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB6_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB6_11
.LBB6_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB6_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB6_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB6_18
# %bb.13:
je .LBB6_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB6_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB6_17
.LBB6_16:
callq memcpy@PLT
.LBB6_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB6_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB6_23
# %bb.19:
subq %r14, %r12
je .LBB6_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB6_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB6_23
.LBB6_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB6_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB6_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB6_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB6_26:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end6:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end6-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL4initPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11removeEvensPci, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL15removeNonPrimesPcii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL4initPc,@object # @_ZL4initPc
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL4initPc:
.quad _ZL19__device_stub__initPc
.size _ZL4initPc, 8
.type _ZL11removeEvensPci,@object # @_ZL11removeEvensPci
.p2align 3, 0x0
_ZL11removeEvensPci:
.quad _ZL26__device_stub__removeEvensPci
.size _ZL11removeEvensPci, 8
.type _ZL15removeNonPrimesPcii,@object # @_ZL15removeNonPrimesPcii
.p2align 3, 0x0
_ZL15removeNonPrimesPcii:
.quad _ZL30__device_stub__removeNonPrimesPcii
.size _ZL15removeNonPrimesPcii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ".txt"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string::append"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits,@object # @__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits:
.asciz "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899"
.size .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits, 201
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL4initPc"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL11removeEvensPci"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_ZL15removeNonPrimesPcii"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL19__device_stub__initPc
.addrsig_sym _ZL26__device_stub__removeEvensPci
.addrsig_sym _ZL30__device_stub__removeNonPrimesPcii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZL4initPc
.addrsig_sym _ZL11removeEvensPci
.addrsig_sym _ZL15removeNonPrimesPcii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15removeNonPrimesPcii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IADD3 R0, R0, 0x3, R0 ; /* 0x0000000300007810 */
/* 0x001fca0007ffe000 */
/*0060*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x002fca000f8e0200 */
/*0070*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fca00078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f04270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0002 */
/*0130*/ IADD3 R2, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x000fc80007f1e0ff */
/*0140*/ LEA.HI.X.SX32 R3, R5, c[0x0][0x164], 0x1, P0 ; /* 0x0000590005037a11 */
/* 0x000fe200000f0eff */
/*0150*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x000fc800078e0205 */
/*0160*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101104 */
/*0170*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x130 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11removeEvensPci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fc800078e00ff */
/*0040*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R3, R3, 0x4, R3 ; /* 0x0000000403037810 */
/* 0x001fca0007ffe003 */
/*0060*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x002fca000f8e0203 */
/*0070*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4initPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0050*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe2000c101104 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL4initPc,"axG",@progbits,_ZL4initPc,comdat
.globl _ZL4initPc
.p2align 8
.type _ZL4initPc,@function
_ZL4initPc:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b16 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL4initPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL4initPc,"axG",@progbits,_ZL4initPc,comdat
.Lfunc_end0:
.size _ZL4initPc, .Lfunc_end0-_ZL4initPc
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL11removeEvensPci,"axG",@progbits,_ZL11removeEvensPci,comdat
.globl _ZL11removeEvensPci
.p2align 8
.type _ZL11removeEvensPci,@function
_ZL11removeEvensPci:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v0, v1, 1, 4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s3, v0
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11removeEvensPci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11removeEvensPci,"axG",@progbits,_ZL11removeEvensPci,comdat
.Lfunc_end1:
.size _ZL11removeEvensPci, .Lfunc_end1-_ZL11removeEvensPci
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL15removeNonPrimesPcii,"axG",@progbits,_ZL15removeNonPrimesPcii,comdat
.globl _ZL15removeNonPrimesPcii
.p2align 8
.type _ZL15removeNonPrimesPcii,@function
_ZL15removeNonPrimesPcii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 3, v0
v_cmpx_ge_i32_e64 s3, v2
s_cbranch_execz .LBB2_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v2
s_load_b32 s1, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_u8 v4, v[3:4], off
v_lshlrev_b32_e32 v3, 1, v2
v_cmp_ge_i32_e64 s0, s1, v3
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB2_4
v_lshl_add_u32 v1, v1, 2, 4
v_add_nc_u32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_ashrrev_i32_e32 v5, 31, v0
v_add_co_u32 v1, vcc_lo, v1, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, v1, 2
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v6, 0
.LBB2_3:
v_add_nc_u32_e32 v3, v3, v2
global_store_b8 v[0:1], v6, off
v_add_co_u32 v0, s0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, v1, v5, s0
v_cmp_lt_i32_e32 vcc_lo, s1, v3
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB2_3
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL15removeNonPrimesPcii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL15removeNonPrimesPcii,"axG",@progbits,_ZL15removeNonPrimesPcii,comdat
.Lfunc_end2:
.size _ZL15removeNonPrimesPcii, .Lfunc_end2-_ZL15removeNonPrimesPcii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL4initPc
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _ZL4initPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11removeEvensPci
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11removeEvensPci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL15removeNonPrimesPcii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL15removeNonPrimesPcii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // This example introduces CUDA's heterogeneous model of memory
// by demonstrating the difference between the "host" and "device"
// memory spaces.
// #include stdlib.h for malloc/free
#include <stdlib.h>
// #include stdio.h for printf
#include <stdio.h>
// nvcc automatically #includes headers needed for cudaMalloc, cudaFree, cudaMemcpy, & cudaMemset
int main(void)
{
// create arrays of 16 elements
int num_elements = 16;
// compute the size of the arrays in bytes
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int*)malloc(num_bytes);
// cudaMalloc a device array
// we pass cudaMalloc a pointer to the device_array pointer
cudaMalloc((void**)&device_array, num_bytes);
// if either memory allocation failed, report an error message
if(host_array == 0 || device_array == 0)
{
printf("couldn't allocate memory\n");
return 1;
}
// zero out the device array with cudaMemset
cudaMemset(device_array, 0, num_bytes);
// we can't dereference elements of device_array from the host directly:
// that will likely cause a crash. instead, we must explicitly copy from
// device memory to host memory to access the result
// copy the contents of the device array to the host array to inspect the result
// use cudaMemcpyDeviceToHost to indicate the direction of the copy
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
// print out the result element by element
for(int i=0; i < num_elements; ++i)
{
printf("%d ", host_array[i]);
}
printf("\n");
// use free to free the host array
free(host_array);
// use cudaFree to free the device array
cudaFree(device_array);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // This example introduces CUDA's heterogeneous model of memory
// by demonstrating the difference between the "host" and "device"
// memory spaces.
// #include stdlib.h for malloc/free
#include <stdlib.h>
// #include stdio.h for printf
#include <stdio.h>
// nvcc automatically #includes headers needed for cudaMalloc, cudaFree, cudaMemcpy, & cudaMemset
int main(void)
{
// create arrays of 16 elements
int num_elements = 16;
// compute the size of the arrays in bytes
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int*)malloc(num_bytes);
// cudaMalloc a device array
// we pass cudaMalloc a pointer to the device_array pointer
cudaMalloc((void**)&device_array, num_bytes);
// if either memory allocation failed, report an error message
if(host_array == 0 || device_array == 0)
{
printf("couldn't allocate memory\n");
return 1;
}
// zero out the device array with cudaMemset
cudaMemset(device_array, 0, num_bytes);
// we can't dereference elements of device_array from the host directly:
// that will likely cause a crash. instead, we must explicitly copy from
// device memory to host memory to access the result
// copy the contents of the device array to the host array to inspect the result
// use cudaMemcpyDeviceToHost to indicate the direction of the copy
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
// print out the result element by element
for(int i=0; i < num_elements; ++i)
{
printf("%d ", host_array[i]);
}
printf("\n");
// use free to free the host array
free(host_array);
// use cudaFree to free the device array
cudaFree(device_array);
} | .file "tmpxft_0005afe4_00000000-6_cuda_memory_model.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "couldn't allocate memory\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
testq %r13, %r13
je .L4
movq (%rsp), %rdi
testq %rdi, %rdi
je .L4
movl $64, %edx
movl $0, %esi
call cudaMemset@PLT
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 64(%r13), %r12
leaq .LC1(%rip), %rbp
.L7:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L7
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // This example introduces CUDA's heterogeneous model of memory
// by demonstrating the difference between the "host" and "device"
// memory spaces.
// #include stdlib.h for malloc/free
#include <stdlib.h>
// #include stdio.h for printf
#include <stdio.h>
// nvcc automatically #includes headers needed for cudaMalloc, cudaFree, cudaMemcpy, & cudaMemset
int main(void)
{
// create arrays of 16 elements
int num_elements = 16;
// compute the size of the arrays in bytes
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int*)malloc(num_bytes);
// cudaMalloc a device array
// we pass cudaMalloc a pointer to the device_array pointer
cudaMalloc((void**)&device_array, num_bytes);
// if either memory allocation failed, report an error message
if(host_array == 0 || device_array == 0)
{
printf("couldn't allocate memory\n");
return 1;
}
// zero out the device array with cudaMemset
cudaMemset(device_array, 0, num_bytes);
// we can't dereference elements of device_array from the host directly:
// that will likely cause a crash. instead, we must explicitly copy from
// device memory to host memory to access the result
// copy the contents of the device array to the host array to inspect the result
// use cudaMemcpyDeviceToHost to indicate the direction of the copy
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
// print out the result element by element
for(int i=0; i < num_elements; ++i)
{
printf("%d ", host_array[i]);
}
printf("\n");
// use free to free the host array
free(host_array);
// use cudaFree to free the device array
cudaFree(device_array);
} | // This example introduces CUDA's heterogeneous model of memory
// by demonstrating the difference between the "host" and "device"
// memory spaces.
// #include stdlib.h for malloc/free
#include <hip/hip_runtime.h>
#include <stdlib.h>
// #include stdio.h for printf
#include <stdio.h>
// nvcc automatically #includes headers needed for cudaMalloc, cudaFree, cudaMemcpy, & cudaMemset
int main(void)
{
// create arrays of 16 elements
int num_elements = 16;
// compute the size of the arrays in bytes
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int*)malloc(num_bytes);
// cudaMalloc a device array
// we pass cudaMalloc a pointer to the device_array pointer
hipMalloc((void**)&device_array, num_bytes);
// if either memory allocation failed, report an error message
if(host_array == 0 || device_array == 0)
{
printf("couldn't allocate memory\n");
return 1;
}
// zero out the device array with cudaMemset
hipMemset(device_array, 0, num_bytes);
// we can't dereference elements of device_array from the host directly:
// that will likely cause a crash. instead, we must explicitly copy from
// device memory to host memory to access the result
// copy the contents of the device array to the host array to inspect the result
// use cudaMemcpyDeviceToHost to indicate the direction of the copy
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
// print out the result element by element
for(int i=0; i < num_elements; ++i)
{
printf("%d ", host_array[i]);
}
printf("\n");
// use free to free the host array
free(host_array);
// use cudaFree to free the device array
hipFree(device_array);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // This example introduces CUDA's heterogeneous model of memory
// by demonstrating the difference between the "host" and "device"
// memory spaces.
// #include stdlib.h for malloc/free
#include <hip/hip_runtime.h>
#include <stdlib.h>
// #include stdio.h for printf
#include <stdio.h>
// nvcc automatically #includes headers needed for cudaMalloc, cudaFree, cudaMemcpy, & cudaMemset
int main(void)
{
// create arrays of 16 elements
int num_elements = 16;
// compute the size of the arrays in bytes
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int*)malloc(num_bytes);
// cudaMalloc a device array
// we pass cudaMalloc a pointer to the device_array pointer
hipMalloc((void**)&device_array, num_bytes);
// if either memory allocation failed, report an error message
if(host_array == 0 || device_array == 0)
{
printf("couldn't allocate memory\n");
return 1;
}
// zero out the device array with cudaMemset
hipMemset(device_array, 0, num_bytes);
// we can't dereference elements of device_array from the host directly:
// that will likely cause a crash. instead, we must explicitly copy from
// device memory to host memory to access the result
// copy the contents of the device array to the host array to inspect the result
// use cudaMemcpyDeviceToHost to indicate the direction of the copy
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
// print out the result element by element
for(int i=0; i < num_elements; ++i)
{
printf("%d ", host_array[i]);
}
printf("\n");
// use free to free the host array
free(host_array);
// use cudaFree to free the device array
hipFree(device_array);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // This example introduces CUDA's heterogeneous model of memory
// by demonstrating the difference between the "host" and "device"
// memory spaces.
// #include stdlib.h for malloc/free
#include <hip/hip_runtime.h>
#include <stdlib.h>
// #include stdio.h for printf
#include <stdio.h>
// nvcc automatically #includes headers needed for cudaMalloc, cudaFree, cudaMemcpy, & cudaMemset
int main(void)
{
// create arrays of 16 elements
int num_elements = 16;
// compute the size of the arrays in bytes
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int*)malloc(num_bytes);
// cudaMalloc a device array
// we pass cudaMalloc a pointer to the device_array pointer
hipMalloc((void**)&device_array, num_bytes);
// if either memory allocation failed, report an error message
if(host_array == 0 || device_array == 0)
{
printf("couldn't allocate memory\n");
return 1;
}
// zero out the device array with cudaMemset
hipMemset(device_array, 0, num_bytes);
// we can't dereference elements of device_array from the host directly:
// that will likely cause a crash. instead, we must explicitly copy from
// device memory to host memory to access the result
// copy the contents of the device array to the host array to inspect the result
// use cudaMemcpyDeviceToHost to indicate the direction of the copy
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
// print out the result element by element
for(int i=0; i < num_elements; ++i)
{
printf("%d ", host_array[i]);
}
printf("\n");
// use free to free the host array
free(host_array);
// use cudaFree to free the device array
hipFree(device_array);
} | .text
.file "cuda_memory_model.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, (%rsp)
movl $64, %edi
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
testq %rbx, %rbx
je .LBB0_2
# %bb.1:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_2
# %bb.3:
movl $64, %edx
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB0_4
# %bb.5:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB0_6
.LBB0_2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005afe4_00000000-6_cuda_memory_model.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "couldn't allocate memory\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
testq %r13, %r13
je .L4
movq (%rsp), %rdi
testq %rdi, %rdi
je .L4
movl $64, %edx
movl $0, %esi
call cudaMemset@PLT
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 64(%r13), %r12
leaq .LC1(%rip), %rbp
.L7:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L7
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_memory_model.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, (%rsp)
movl $64, %edi
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
testq %rbx, %rbx
je .LBB0_2
# %bb.1:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_2
# %bb.3:
movl $64, %edx
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB0_4
# %bb.5:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB0_6
.LBB0_2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
#include <algorithm>
#include "../graph_parser/parse.h"
#include "../graph_parser/util.h"
#include "kernel.cu"
#ifdef GEM5_FUSION
#include <stdint.h>
extern "C" {
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
}
#endif
#define RANGE 2048
void dump2file(int *adjmatrix, int num_nodes);
void print_vector(int *vector, int num);
void print_vectorf(float *vector, int num);
int main(int argc, char **argv)
{
char *tmpchar;
int num_nodes;
int num_edges;
int file_format = 1;
bool directed = 0;
cudaError_t err = cudaSuccess;
// Input arguments
if (argc == 3) {
tmpchar = argv[1]; // Graph inputfile
file_format = atoi(argv[2]); // Choose file format
} else {
fprintf(stderr, "You did something wrong!\n");
exit(1);
}
srand(7);
// Allocate the csr array
csr_array *csr;
// Parse the graph into the csr structure
if (file_format == 1) {
csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
} else if (file_format == 0) {
csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
} else {
fprintf(stderr, "reserve for future");
exit(1);
}
// Allocate the node value array
int *node_value = (int *)malloc(num_nodes * sizeof(int));
if (!node_value) fprintf(stderr, "malloc failed node_value\n");
// Allocate the set array
int *s_array = (int *)malloc(num_nodes * sizeof(int));
if (!s_array) fprintf(stderr, "malloc failed node_value\n");
// Randomize the node values
for (int i = 0; i < num_nodes; i++) {
node_value[i] = rand() % RANGE;
}
// Create device side buffers
int *row_d;
int *col_d;
int *c_array_d;
int *c_array_u_d;
int *s_array_d;
int *node_value_d;
int *min_array_d;
int *stop_d;
// Allocate the device-side buffers for the graph
err = cudaMalloc(&row_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc row_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&col_d, num_edges * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc col_d (size:%d) => %s\n", num_edges , cudaGetErrorString(err));
return -1;
}
// Termination variable
err = cudaMalloc(&stop_d, sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc stop_d (size:%d) => %s\n", 1, cudaGetErrorString(err));
return -1;
}
// Allocate the device-side buffers for mis
err = cudaMalloc(&min_array_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc min_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&c_array_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc c_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&c_array_u_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc c_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&s_array_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc s_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&node_value_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc node_value_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
double time1 = gettime();
#ifdef GEM5_FUSION
m5_work_begin(0, 0);
#endif
// Copy data to device-side buffers
err = cudaMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy row_d (size:%d) => %s\n", num_nodes, cudaGetErrorString(err));
return -1;
}
err = cudaMemcpy(col_d, csr->col_array, num_edges * sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy col_d (size:%d) => %s\n", num_nodes, cudaGetErrorString(err));
return -1;
}
err = cudaMemcpy(node_value_d, node_value, num_nodes * sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy feature_d (size:%d) => %s\n", num_nodes, cudaGetErrorString(err));
return -1;
}
// Work dimensions
int block_size = 128;
int num_blocks = (num_nodes + block_size - 1) / block_size;
dim3 threads(block_size, 1, 1);
dim3 grid(num_blocks, 1, 1);
// Launch the initialization kernel
init <<<grid, threads>>>(s_array_d, c_array_d, c_array_u_d,
num_nodes, num_edges);
cudaThreadSynchronize();
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: init kernel (%s)\n", cudaGetErrorString(err));
return -1;
}
// Termination variable
int stop = 1;
int iterations = 0;
while (stop) {
stop = 0;
// Copy the termination variable to the device
err = cudaMemcpy(stop_d, &stop, sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: write stop_d variable (%s)\n", cudaGetErrorString(err));
return -1;
}
// Launch mis1
mis1 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, min_array_d, stop_d, num_nodes,
num_edges);
// Launch mis2
mis2 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, c_array_u_d, min_array_d, num_nodes,
num_edges);
// Launch mis3
mis3 <<<grid, threads>>>(c_array_u_d, c_array_d, num_nodes);
// Copy the termination variable back
err = cudaMemcpy(&stop, stop_d, sizeof(int), cudaMemcpyDeviceToHost);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: read stop_d variable (%s)\n", cudaGetErrorString(err));
return -1;
}
iterations++;
}
cudaThreadSynchronize();
err = cudaMemcpy(s_array, s_array_d, num_nodes * sizeof(int), cudaMemcpyDeviceToHost);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy s_array_d failed (%s)\n", cudaGetErrorString(err));
return -1;
}
#ifdef GEM5_FUSION
m5_work_end(0, 0);
#endif
double time2 = gettime();
// Print out the timing characterisitics
printf("number of iterations: %d\n", iterations);
printf("kernel + memcpy time %f ms\n", (time2 - time1) * 1000);
#if 0
// Print the set array
print_vector(s_array, num_nodes);
#endif
// Clean up the host-side arrays
free(node_value);
free(s_array);
csr->freeArrays();
free(csr);
// Clean up the device-side arrays
cudaFree(row_d);
cudaFree(col_d);
cudaFree(c_array_d);
cudaFree(s_array_d);
cudaFree(node_value_d);
cudaFree(min_array_d);
cudaFree(stop_d);
return 0;
}
void print_vector(int *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%d\n", vector[i]);
}
fclose(fp);
}
void print_vectorf(float *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%f\n", vector[i]);
}
fclose(fp);
} | .file "tmpxft_000438c6_00000000-6_mis.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2343:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2343:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "result.out"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "ERROR: unable to open result.txt\n"
.section .rodata.str1.1
.LC3:
.string "%d\n"
.text
.globl _Z12print_vectorPii
.type _Z12print_vectorPii, @function
_Z12print_vectorPii:
.LFB2339:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movl %esi, %r12d
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L9
.L4:
testl %r12d, %r12d
jle .L5
movq %r13, %rbx
movslq %r12d, %r12
leaq 0(%r13,%r12,4), %r13
leaq .LC3(%rip), %r12
.L6:
movl (%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L6
.L5:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.cfi_endproc
.LFE2339:
.size _Z12print_vectorPii, .-_Z12print_vectorPii
.section .rodata.str1.1
.LC4:
.string "%f\n"
.text
.globl _Z13print_vectorfPfi
.type _Z13print_vectorfPfi, @function
_Z13print_vectorfPfi:
.LFB2340:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movl %esi, %r12d
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L16
.L11:
testl %r12d, %r12d
jle .L12
movq %r13, %rbx
movslq %r12d, %r12
leaq 0(%r13,%r12,4), %r13
leaq .LC4(%rip), %r12
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L13
.L12:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.cfi_endproc
.LFE2340:
.size _Z13print_vectorfPfi, .-_Z13print_vectorfPfi
.globl _Z29__device_stub__Z4initPiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4initPiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4initPiS_S_iiPiS_S_ii:
.LFB2365:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4initPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2365:
.size _Z29__device_stub__Z4initPiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4initPiS_S_iiPiS_S_ii
.globl _Z4initPiS_S_ii
.type _Z4initPiS_S_ii, @function
_Z4initPiS_S_ii:
.LFB2366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4initPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2366:
.size _Z4initPiS_S_ii, .-_Z4initPiS_S_ii
.globl _Z37__device_stub__Z4mis1PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
.type _Z37__device_stub__Z4mis1PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii, @function
_Z37__device_stub__Z4mis1PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii:
.LFB2367:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z4mis1PiS_S_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2367:
.size _Z37__device_stub__Z4mis1PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii, .-_Z37__device_stub__Z4mis1PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
.globl _Z4mis1PiS_S_S_S_S_S_ii
.type _Z4mis1PiS_S_S_S_S_S_ii, @function
_Z4mis1PiS_S_S_S_S_S_ii:
.LFB2368:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z4mis1PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2368:
.size _Z4mis1PiS_S_S_S_S_S_ii, .-_Z4mis1PiS_S_S_S_S_S_ii
.globl _Z37__device_stub__Z4mis2PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
.type _Z37__device_stub__Z4mis2PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii, @function
_Z37__device_stub__Z4mis2PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii:
.LFB2369:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z4mis2PiS_S_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2369:
.size _Z37__device_stub__Z4mis2PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii, .-_Z37__device_stub__Z4mis2PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
.globl _Z4mis2PiS_S_S_S_S_S_ii
.type _Z4mis2PiS_S_S_S_S_S_ii, @function
_Z4mis2PiS_S_S_S_S_S_ii:
.LFB2370:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z4mis2PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2370:
.size _Z4mis2PiS_S_S_S_S_S_ii, .-_Z4mis2PiS_S_S_S_S_S_ii
.globl _Z26__device_stub__Z4mis3PiS_iPiS_i
.type _Z26__device_stub__Z4mis3PiS_iPiS_i, @function
_Z26__device_stub__Z4mis3PiS_iPiS_i:
.LFB2371:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mis3PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2371:
.size _Z26__device_stub__Z4mis3PiS_iPiS_i, .-_Z26__device_stub__Z4mis3PiS_iPiS_i
.globl _Z4mis3PiS_i
.type _Z4mis3PiS_i, @function
_Z4mis3PiS_i:
.LFB2372:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4mis3PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2372:
.size _Z4mis3PiS_i, .-_Z4mis3PiS_i
.section .rodata.str1.1
.LC5:
.string "You did something wrong!\n"
.LC6:
.string "reserve for future"
.LC7:
.string "malloc failed node_value\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "ERROR: cudaMalloc row_d (size:%d) => %s\n"
.align 8
.LC9:
.string "ERROR: cudaMalloc col_d (size:%d) => %s\n"
.align 8
.LC10:
.string "ERROR: cudaMalloc stop_d (size:%d) => %s\n"
.align 8
.LC11:
.string "ERROR: cudaMalloc min_array_d (size:%d) => %s\n"
.align 8
.LC12:
.string "ERROR: cudaMalloc c_array_d (size:%d) => %s\n"
.align 8
.LC13:
.string "ERROR: cudaMalloc s_array_d (size:%d) => %s\n"
.align 8
.LC14:
.string "ERROR: cudaMalloc node_value_d (size:%d) => %s\n"
.align 8
.LC15:
.string "ERROR: cudaMemcpy row_d (size:%d) => %s\n"
.align 8
.LC16:
.string "ERROR: cudaMemcpy col_d (size:%d) => %s\n"
.align 8
.LC17:
.string "ERROR: cudaMemcpy feature_d (size:%d) => %s\n"
.section .rodata.str1.1
.LC18:
.string "ERROR: init kernel (%s)\n"
.section .rodata.str1.8
.align 8
.LC19:
.string "ERROR: write stop_d variable (%s)\n"
.align 8
.LC20:
.string "ERROR: read stop_d variable (%s)\n"
.align 8
.LC21:
.string "ERROR: cudaMemcpy s_array_d failed (%s)\n"
.section .rodata.str1.1
.LC22:
.string "number of iterations: %d\n"
.LC24:
.string "kernel + memcpy time %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2338:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L50
movq 8(%rsi), %rbp
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $7, %edi
call srand@PLT
cmpl $1, %ebx
je .L89
testl %ebx, %ebx
jne .L54
leaq 24(%rsp), %rdx
leaq 20(%rsp), %rsi
movl $0, %ecx
movq %rbp, %rdi
call _Z8parseCOOPcPiS0_b@PLT
movq %rax, %r12
.L53:
movslq 20(%rsp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L90
.L55:
movslq 20(%rsp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L91
.L56:
movl 20(%rsp), %esi
testl %esi, %esi
jle .L57
movl $0, %ebx
.L58:
call rand@PLT
cltd
shrl $21, %edx
addl %edx, %eax
andl $2047, %eax
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
movl 20(%rsp), %esi
addq $1, %rbx
cmpl %ebx, %esi
jg .L58
.L57:
movslq %esi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L92
movslq 24(%rsp), %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L93
leaq 88(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L94
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L95
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L96
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L97
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L98
movslq 20(%rsp), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L99
call _Z7gettimev@PLT
movsd %xmm0, (%rsp)
movslq 20(%rsp), %rdx
salq $2, %rdx
movq (%r12), %rsi
movl $1, %ecx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L100
movslq 24(%rsp), %rdx
salq $2, %rdx
movq 8(%r12), %rsi
movl $1, %ecx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L101
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L102
movl 20(%rsp), %edx
leal 254(%rdx), %eax
addl $127, %edx
cmovns %edx, %eax
sarl $7, %eax
movl $128, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %eax, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 108(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L103
.L71:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L104
movl $0, %r14d
leaq 28(%rsp), %rbx
jmp .L72
.L50:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
leaq 24(%rsp), %rdx
leaq 20(%rsp), %rsi
movl $0, %ecx
movq %rbp, %rdi
call _Z10parseMetisPcPiS0_b@PLT
movq %rax, %r12
jmp .L53
.L54:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L55
.L91:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L56
.L92:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L93:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 24(%rsp), %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L94:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $1, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L95:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L96:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L97:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L98:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L99:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L100:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L101:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L102:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl 20(%rsp), %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L103:
movl 24(%rsp), %r8d
movl 20(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z29__device_stub__Z4initPiS_S_iiPiS_S_ii
jmp .L71
.L104:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L107:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L108:
subq $8, %rsp
.cfi_def_cfa_offset 200
movl 32(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 208
movl 36(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 216
pushq 112(%rsp)
.cfi_def_cfa_offset 224
movq 112(%rsp), %r9
movq 80(%rsp), %r8
movq 96(%rsp), %rcx
movq 104(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z37__device_stub__Z4mis1PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
addq $32, %rsp
.cfi_def_cfa_offset 192
jmp .L74
.L109:
subq $8, %rsp
.cfi_def_cfa_offset 200
movl 32(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 208
movl 36(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 216
pushq 104(%rsp)
.cfi_def_cfa_offset 224
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq 96(%rsp), %rcx
movq 104(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z37__device_stub__Z4mis2PiS_S_S_S_S_S_iiPiS_S_S_S_S_S_ii
addq $32, %rsp
.cfi_def_cfa_offset 192
jmp .L75
.L76:
movl $2, %ecx
movl $4, %edx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L105
addl $1, %r14d
movl 28(%rsp), %r15d
testl %r15d, %r15d
je .L106
.L72:
movl $0, 28(%rsp)
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L107
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L108
.L74:
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L75:
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L76
movl 20(%rsp), %edx
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z26__device_stub__Z4mis3PiS_iPiS_i
jmp .L76
.L105:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L106:
call cudaThreadSynchronize@PLT
movslq 20(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 64(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L110
call _Z7gettimev@PLT
movsd %xmm0, 8(%rsp)
movl %r14d, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
mulsd .LC23(%rip), %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%r12), %rdi
testq %rdi, %rdi
je .L79
call free@PLT
.L79:
movq 8(%r12), %rdi
testq %rdi, %rdi
je .L80
call free@PLT
.L80:
movq 16(%r12), %rdi
testq %rdi, %rdi
je .L81
call free@PLT
.L81:
movq 24(%r12), %rdi
testq %rdi, %rdi
je .L82
call free@PLT
.L82:
movq %r12, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
.L49:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L111
movl %r15d, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %r15d
jmp .L49
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2338:
.size main, .-main
.section .rodata.str1.1
.LC25:
.string "_Z4mis3PiS_i"
.LC26:
.string "_Z4mis2PiS_S_S_S_S_S_ii"
.LC27:
.string "_Z4mis1PiS_S_S_S_S_S_ii"
.LC28:
.string "_Z4initPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2374:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mis3PiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mis2PiS_S_S_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mis1PiS_S_S_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2374:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC23:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
#include <algorithm>
#include "../graph_parser/parse.h"
#include "../graph_parser/util.h"
#include "kernel.cu"
#ifdef GEM5_FUSION
#include <stdint.h>
extern "C" {
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
}
#endif
#define RANGE 2048
void dump2file(int *adjmatrix, int num_nodes);
void print_vector(int *vector, int num);
void print_vectorf(float *vector, int num);
int main(int argc, char **argv)
{
char *tmpchar;
int num_nodes;
int num_edges;
int file_format = 1;
bool directed = 0;
cudaError_t err = cudaSuccess;
// Input arguments
if (argc == 3) {
tmpchar = argv[1]; // Graph inputfile
file_format = atoi(argv[2]); // Choose file format
} else {
fprintf(stderr, "You did something wrong!\n");
exit(1);
}
srand(7);
// Allocate the csr array
csr_array *csr;
// Parse the graph into the csr structure
if (file_format == 1) {
csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
} else if (file_format == 0) {
csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
} else {
fprintf(stderr, "reserve for future");
exit(1);
}
// Allocate the node value array
int *node_value = (int *)malloc(num_nodes * sizeof(int));
if (!node_value) fprintf(stderr, "malloc failed node_value\n");
// Allocate the set array
int *s_array = (int *)malloc(num_nodes * sizeof(int));
if (!s_array) fprintf(stderr, "malloc failed node_value\n");
// Randomize the node values
for (int i = 0; i < num_nodes; i++) {
node_value[i] = rand() % RANGE;
}
// Create device side buffers
int *row_d;
int *col_d;
int *c_array_d;
int *c_array_u_d;
int *s_array_d;
int *node_value_d;
int *min_array_d;
int *stop_d;
// Allocate the device-side buffers for the graph
err = cudaMalloc(&row_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc row_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&col_d, num_edges * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc col_d (size:%d) => %s\n", num_edges , cudaGetErrorString(err));
return -1;
}
// Termination variable
err = cudaMalloc(&stop_d, sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc stop_d (size:%d) => %s\n", 1, cudaGetErrorString(err));
return -1;
}
// Allocate the device-side buffers for mis
err = cudaMalloc(&min_array_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc min_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&c_array_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc c_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&c_array_u_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc c_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&s_array_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc s_array_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
err = cudaMalloc(&node_value_d, num_nodes * sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMalloc node_value_d (size:%d) => %s\n", num_nodes , cudaGetErrorString(err));
return -1;
}
double time1 = gettime();
#ifdef GEM5_FUSION
m5_work_begin(0, 0);
#endif
// Copy data to device-side buffers
err = cudaMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy row_d (size:%d) => %s\n", num_nodes, cudaGetErrorString(err));
return -1;
}
err = cudaMemcpy(col_d, csr->col_array, num_edges * sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy col_d (size:%d) => %s\n", num_nodes, cudaGetErrorString(err));
return -1;
}
err = cudaMemcpy(node_value_d, node_value, num_nodes * sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy feature_d (size:%d) => %s\n", num_nodes, cudaGetErrorString(err));
return -1;
}
// Work dimensions
int block_size = 128;
int num_blocks = (num_nodes + block_size - 1) / block_size;
dim3 threads(block_size, 1, 1);
dim3 grid(num_blocks, 1, 1);
// Launch the initialization kernel
init <<<grid, threads>>>(s_array_d, c_array_d, c_array_u_d,
num_nodes, num_edges);
cudaThreadSynchronize();
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: init kernel (%s)\n", cudaGetErrorString(err));
return -1;
}
// Termination variable
int stop = 1;
int iterations = 0;
while (stop) {
stop = 0;
// Copy the termination variable to the device
err = cudaMemcpy(stop_d, &stop, sizeof(int), cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: write stop_d variable (%s)\n", cudaGetErrorString(err));
return -1;
}
// Launch mis1
mis1 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, min_array_d, stop_d, num_nodes,
num_edges);
// Launch mis2
mis2 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, c_array_u_d, min_array_d, num_nodes,
num_edges);
// Launch mis3
mis3 <<<grid, threads>>>(c_array_u_d, c_array_d, num_nodes);
// Copy the termination variable back
err = cudaMemcpy(&stop, stop_d, sizeof(int), cudaMemcpyDeviceToHost);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: read stop_d variable (%s)\n", cudaGetErrorString(err));
return -1;
}
iterations++;
}
cudaThreadSynchronize();
err = cudaMemcpy(s_array, s_array_d, num_nodes * sizeof(int), cudaMemcpyDeviceToHost);
if (err != cudaSuccess) {
fprintf(stderr, "ERROR: cudaMemcpy s_array_d failed (%s)\n", cudaGetErrorString(err));
return -1;
}
#ifdef GEM5_FUSION
m5_work_end(0, 0);
#endif
double time2 = gettime();
// Print out the timing characterisitics
printf("number of iterations: %d\n", iterations);
printf("kernel + memcpy time %f ms\n", (time2 - time1) * 1000);
#if 0
// Print the set array
print_vector(s_array, num_nodes);
#endif
// Clean up the host-side arrays
free(node_value);
free(s_array);
csr->freeArrays();
free(csr);
// Clean up the device-side arrays
cudaFree(row_d);
cudaFree(col_d);
cudaFree(c_array_d);
cudaFree(s_array_d);
cudaFree(node_value_d);
cudaFree(min_array_d);
cudaFree(stop_d);
return 0;
}
void print_vector(int *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%d\n", vector[i]);
}
fclose(fp);
}
void print_vectorf(float *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%f\n", vector[i]);
}
fclose(fp);
} | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
#include <algorithm>
#include "../graph_parser/parse.h"
#include "../graph_parser/util.h"
#include "kernel.cu"
#ifdef GEM5_FUSION
#include <stdint.h>
extern "C" {
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
}
#endif
#define RANGE 2048
void dump2file(int *adjmatrix, int num_nodes);
void print_vector(int *vector, int num);
void print_vectorf(float *vector, int num);
int main(int argc, char **argv)
{
char *tmpchar;
int num_nodes;
int num_edges;
int file_format = 1;
bool directed = 0;
hipError_t err = hipSuccess;
// Input arguments
if (argc == 3) {
tmpchar = argv[1]; // Graph inputfile
file_format = atoi(argv[2]); // Choose file format
} else {
fprintf(stderr, "You did something wrong!\n");
exit(1);
}
srand(7);
// Allocate the csr array
csr_array *csr;
// Parse the graph into the csr structure
if (file_format == 1) {
csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
} else if (file_format == 0) {
csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
} else {
fprintf(stderr, "reserve for future");
exit(1);
}
// Allocate the node value array
int *node_value = (int *)malloc(num_nodes * sizeof(int));
if (!node_value) fprintf(stderr, "malloc failed node_value\n");
// Allocate the set array
int *s_array = (int *)malloc(num_nodes * sizeof(int));
if (!s_array) fprintf(stderr, "malloc failed node_value\n");
// Randomize the node values
for (int i = 0; i < num_nodes; i++) {
node_value[i] = rand() % RANGE;
}
// Create device side buffers
int *row_d;
int *col_d;
int *c_array_d;
int *c_array_u_d;
int *s_array_d;
int *node_value_d;
int *min_array_d;
int *stop_d;
// Allocate the device-side buffers for the graph
err = hipMalloc(&row_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&col_d, num_edges * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc col_d (size:%d) => %s\n", num_edges , hipGetErrorString(err));
return -1;
}
// Termination variable
err = hipMalloc(&stop_d, sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1, hipGetErrorString(err));
return -1;
}
// Allocate the device-side buffers for mis
err = hipMalloc(&min_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc min_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&c_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&c_array_u_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&s_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc s_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&node_value_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc node_value_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
double time1 = gettime();
#ifdef GEM5_FUSION
m5_work_begin(0, 0);
#endif
// Copy data to device-side buffers
err = hipMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
err = hipMemcpy(node_value_d, node_value, num_nodes * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy feature_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
// Work dimensions
int block_size = 128;
int num_blocks = (num_nodes + block_size - 1) / block_size;
dim3 threads(block_size, 1, 1);
dim3 grid(num_blocks, 1, 1);
// Launch the initialization kernel
init <<<grid, threads>>>(s_array_d, c_array_d, c_array_u_d,
num_nodes, num_edges);
hipDeviceSynchronize();
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr, "ERROR: init kernel (%s)\n", hipGetErrorString(err));
return -1;
}
// Termination variable
int stop = 1;
int iterations = 0;
while (stop) {
stop = 0;
// Copy the termination variable to the device
err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: write stop_d variable (%s)\n", hipGetErrorString(err));
return -1;
}
// Launch mis1
mis1 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, min_array_d, stop_d, num_nodes,
num_edges);
// Launch mis2
mis2 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, c_array_u_d, min_array_d, num_nodes,
num_edges);
// Launch mis3
mis3 <<<grid, threads>>>(c_array_u_d, c_array_d, num_nodes);
// Copy the termination variable back
err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: read stop_d variable (%s)\n", hipGetErrorString(err));
return -1;
}
iterations++;
}
hipDeviceSynchronize();
err = hipMemcpy(s_array, s_array_d, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy s_array_d failed (%s)\n", hipGetErrorString(err));
return -1;
}
#ifdef GEM5_FUSION
m5_work_end(0, 0);
#endif
double time2 = gettime();
// Print out the timing characterisitics
printf("number of iterations: %d\n", iterations);
printf("kernel + memcpy time %f ms\n", (time2 - time1) * 1000);
#if 0
// Print the set array
print_vector(s_array, num_nodes);
#endif
// Clean up the host-side arrays
free(node_value);
free(s_array);
csr->freeArrays();
free(csr);
// Clean up the device-side arrays
hipFree(row_d);
hipFree(col_d);
hipFree(c_array_d);
hipFree(s_array_d);
hipFree(node_value_d);
hipFree(min_array_d);
hipFree(stop_d);
return 0;
}
void print_vector(int *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%d\n", vector[i]);
}
fclose(fp);
}
void print_vectorf(float *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%f\n", vector[i]);
}
fclose(fp);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
#include <algorithm>
#include "../graph_parser/parse.h"
#include "../graph_parser/util.h"
#include "kernel.cu"
#ifdef GEM5_FUSION
#include <stdint.h>
extern "C" {
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
}
#endif
#define RANGE 2048
void dump2file(int *adjmatrix, int num_nodes);
void print_vector(int *vector, int num);
void print_vectorf(float *vector, int num);
int main(int argc, char **argv)
{
char *tmpchar;
int num_nodes;
int num_edges;
int file_format = 1;
bool directed = 0;
hipError_t err = hipSuccess;
// Input arguments
if (argc == 3) {
tmpchar = argv[1]; // Graph inputfile
file_format = atoi(argv[2]); // Choose file format
} else {
fprintf(stderr, "You did something wrong!\n");
exit(1);
}
srand(7);
// Allocate the csr array
csr_array *csr;
// Parse the graph into the csr structure
if (file_format == 1) {
csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
} else if (file_format == 0) {
csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
} else {
fprintf(stderr, "reserve for future");
exit(1);
}
// Allocate the node value array
int *node_value = (int *)malloc(num_nodes * sizeof(int));
if (!node_value) fprintf(stderr, "malloc failed node_value\n");
// Allocate the set array
int *s_array = (int *)malloc(num_nodes * sizeof(int));
if (!s_array) fprintf(stderr, "malloc failed node_value\n");
// Randomize the node values
for (int i = 0; i < num_nodes; i++) {
node_value[i] = rand() % RANGE;
}
// Create device side buffers
int *row_d;
int *col_d;
int *c_array_d;
int *c_array_u_d;
int *s_array_d;
int *node_value_d;
int *min_array_d;
int *stop_d;
// Allocate the device-side buffers for the graph
err = hipMalloc(&row_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&col_d, num_edges * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc col_d (size:%d) => %s\n", num_edges , hipGetErrorString(err));
return -1;
}
// Termination variable
err = hipMalloc(&stop_d, sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1, hipGetErrorString(err));
return -1;
}
// Allocate the device-side buffers for mis
err = hipMalloc(&min_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc min_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&c_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&c_array_u_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&s_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc s_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&node_value_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc node_value_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
double time1 = gettime();
#ifdef GEM5_FUSION
m5_work_begin(0, 0);
#endif
// Copy data to device-side buffers
err = hipMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
err = hipMemcpy(node_value_d, node_value, num_nodes * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy feature_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
// Work dimensions
int block_size = 128;
int num_blocks = (num_nodes + block_size - 1) / block_size;
dim3 threads(block_size, 1, 1);
dim3 grid(num_blocks, 1, 1);
// Launch the initialization kernel
init <<<grid, threads>>>(s_array_d, c_array_d, c_array_u_d,
num_nodes, num_edges);
hipDeviceSynchronize();
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr, "ERROR: init kernel (%s)\n", hipGetErrorString(err));
return -1;
}
// Termination variable
int stop = 1;
int iterations = 0;
while (stop) {
stop = 0;
// Copy the termination variable to the device
err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: write stop_d variable (%s)\n", hipGetErrorString(err));
return -1;
}
// Launch mis1
mis1 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, min_array_d, stop_d, num_nodes,
num_edges);
// Launch mis2
mis2 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, c_array_u_d, min_array_d, num_nodes,
num_edges);
// Launch mis3
mis3 <<<grid, threads>>>(c_array_u_d, c_array_d, num_nodes);
// Copy the termination variable back
err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: read stop_d variable (%s)\n", hipGetErrorString(err));
return -1;
}
iterations++;
}
hipDeviceSynchronize();
err = hipMemcpy(s_array, s_array_d, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy s_array_d failed (%s)\n", hipGetErrorString(err));
return -1;
}
#ifdef GEM5_FUSION
m5_work_end(0, 0);
#endif
double time2 = gettime();
// Print out the timing characterisitics
printf("number of iterations: %d\n", iterations);
printf("kernel + memcpy time %f ms\n", (time2 - time1) * 1000);
#if 0
// Print the set array
print_vector(s_array, num_nodes);
#endif
// Clean up the host-side arrays
free(node_value);
free(s_array);
csr->freeArrays();
free(csr);
// Clean up the device-side arrays
hipFree(row_d);
hipFree(col_d);
hipFree(c_array_d);
hipFree(s_array_d);
hipFree(node_value_d);
hipFree(min_array_d);
hipFree(stop_d);
return 0;
}
void print_vector(int *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%d\n", vector[i]);
}
fclose(fp);
}
void print_vectorf(float *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%f\n", vector[i]);
}
fclose(fp);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4initPiS_S_ii
.globl _Z4initPiS_S_ii
.p2align 8
.type _Z4initPiS_S_ii,@function
_Z4initPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v6, -1 :: v_dual_mov_b32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v6, off
global_store_b32 v[0:1], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4initPiS_S_ii, .Lfunc_end0-_Z4initPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4mis1PiS_S_S_S_S_S_ii
.globl _Z4mis1PiS_S_S_S_S_S_ii
.p2align 8
.type _Z4mis1PiS_S_S_S_S_S_ii,@function
_Z4mis1PiS_S_S_S_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s4, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_11
s_load_b64 s[8:9], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_11
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x30
s_load_b32 s5, s[0:1], 0x3c
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v0, v5, s[6:7]
v_mov_b32_e32 v0, s5
global_load_b32 v3, v[3:4], off
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v4
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v0, v[4:5], off
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v8, 0x5f5e0ff
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v0
s_cbranch_execz .LBB1_10
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v8, 0x5f5e0ff
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_mov_b32 s4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_7
.p2align 6
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v4, s2, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s2, 0, v5, s2
v_cmp_ge_i32_e32 vcc_lo, v3, v0
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB1_9
.LBB1_7:
global_load_b32 v6, v[4:5], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v9, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v7, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v9
s_cbranch_execz .LBB1_6
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v8, v6, v8
s_branch .LBB1_6
.LBB1_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
.LBB1_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mis1PiS_S_S_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4mis1PiS_S_S_S_S_S_ii, .Lfunc_end1-_Z4mis1PiS_S_S_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4mis2PiS_S_S_S_S_S_ii
.globl _Z4mis2PiS_S_S_S_S_S_ii
.p2align 8
.type _Z4mis2PiS_S_S_S_S_S_ii,@function
_Z4mis2PiS_S_S_S_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s6, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB2_10
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_10
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_10
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_dual_mov_b32 v0, 2 :: v_dual_add_nc_u32 v1, 1, v1
s_load_b32 s7, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_store_b32 v[7:8], v0, off
v_cmp_gt_i32_e32 vcc_lo, s6, v1
global_load_b32 v0, v[5:6], off
v_mov_b32_e32 v5, s7
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB2_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v5, v[1:2], off
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v6, -2
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v0, v5
global_store_b32 v[3:4], v6, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_10
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x28
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_8
.p2align 6
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, s0, v1, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v5
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB2_10
.LBB2_8:
global_load_b32 v3, v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v7, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v7
s_cbranch_execz .LBB2_7
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[3:4], v6, off
s_branch .LBB2_7
.LBB2_10:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mis2PiS_S_S_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z4mis2PiS_S_S_S_S_S_ii, .Lfunc_end2-_Z4mis2PiS_S_S_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4mis3PiS_i
.globl _Z4mis3PiS_i
.p2align 8
.type _Z4mis3PiS_i,@function
_Z4mis3PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_3
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_3
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, -2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mis3PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z4mis3PiS_i, .Lfunc_end3-_Z4mis3PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4initPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mis1PiS_S_S_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4mis1PiS_S_S_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mis2PiS_S_S_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4mis2PiS_S_S_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mis3PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4mis3PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /************************************************************************************\
* *
* Copyright � 2014 Advanced Micro Devices, Inc. *
* Copyright (c) 2015 Mark D. Hill and David A. Wood *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following are met: *
* *
* You must reproduce the above copyright notice. *
* *
* Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software *
* without specific, prior, written permission from at least the copyright holder. *
* *
* You must include the following terms in your license and/or other materials *
* provided with the software. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, AND FITNESS FOR A *
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER *
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING *
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY *
* OF SUCH DAMAGE. *
* *
* Without limiting the foregoing, the software may implement third party *
* technologies for which you must obtain licenses from parties other than AMD. *
* You agree that AMD has not obtained or conveyed to you, and that you shall *
* be responsible for obtaining the rights to use and/or distribute the applicable *
* underlying intellectual property rights related to the third party technologies. *
* These third party technologies are not licensed hereunder. *
* *
* If you use the software (in whole or in part), you shall adhere to all *
* applicable U.S., European, and other export laws, including but not limited to *
* the U.S. Export Administration Regulations ("EAR") (15 C.F.R Sections 730-774), *
* and E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant *
* to Section 740.6 of the EAR, you hereby certify that, except pursuant to a *
* license granted by the United States Department of Commerce Bureau of Industry *
* and Security or as otherwise permitted pursuant to a License Exception under *
* the U.S. Export Administration Regulations ("EAR"), you will not (1) export, *
* re-export or release to a national of a country in Country Groups D:1, E:1 or *
* E:2 any restricted technology, software, or source code you receive hereunder, *
* or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such *
* technology or software, if such foreign produced direct product is subject to *
* national security controls as identified on the Commerce Control List (currently *
* found in Supplement 1 to Part 774 of EAR). For the most current Country Group *
* listings, or for additional information about the EAR or your obligations under *
* those regulations, please refer to the U.S. Bureau of Industry and Security's *
* website at http://www.bis.doc.gov/. *
* *
\************************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
#include <algorithm>
#include "../graph_parser/parse.h"
#include "../graph_parser/util.h"
#include "kernel.cu"
#ifdef GEM5_FUSION
#include <stdint.h>
extern "C" {
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
}
#endif
#define RANGE 2048
void dump2file(int *adjmatrix, int num_nodes);
void print_vector(int *vector, int num);
void print_vectorf(float *vector, int num);
int main(int argc, char **argv)
{
char *tmpchar;
int num_nodes;
int num_edges;
int file_format = 1;
bool directed = 0;
hipError_t err = hipSuccess;
// Input arguments
if (argc == 3) {
tmpchar = argv[1]; // Graph inputfile
file_format = atoi(argv[2]); // Choose file format
} else {
fprintf(stderr, "You did something wrong!\n");
exit(1);
}
srand(7);
// Allocate the csr array
csr_array *csr;
// Parse the graph into the csr structure
if (file_format == 1) {
csr = parseMetis(tmpchar, &num_nodes, &num_edges, directed);
} else if (file_format == 0) {
csr = parseCOO(tmpchar, &num_nodes, &num_edges, directed);
} else {
fprintf(stderr, "reserve for future");
exit(1);
}
// Allocate the node value array
int *node_value = (int *)malloc(num_nodes * sizeof(int));
if (!node_value) fprintf(stderr, "malloc failed node_value\n");
// Allocate the set array
int *s_array = (int *)malloc(num_nodes * sizeof(int));
if (!s_array) fprintf(stderr, "malloc failed node_value\n");
// Randomize the node values
for (int i = 0; i < num_nodes; i++) {
node_value[i] = rand() % RANGE;
}
// Create device side buffers
int *row_d;
int *col_d;
int *c_array_d;
int *c_array_u_d;
int *s_array_d;
int *node_value_d;
int *min_array_d;
int *stop_d;
// Allocate the device-side buffers for the graph
err = hipMalloc(&row_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc row_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&col_d, num_edges * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc col_d (size:%d) => %s\n", num_edges , hipGetErrorString(err));
return -1;
}
// Termination variable
err = hipMalloc(&stop_d, sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc stop_d (size:%d) => %s\n", 1, hipGetErrorString(err));
return -1;
}
// Allocate the device-side buffers for mis
err = hipMalloc(&min_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc min_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&c_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&c_array_u_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc c_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&s_array_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc s_array_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
err = hipMalloc(&node_value_d, num_nodes * sizeof(int));
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMalloc node_value_d (size:%d) => %s\n", num_nodes , hipGetErrorString(err));
return -1;
}
double time1 = gettime();
#ifdef GEM5_FUSION
m5_work_begin(0, 0);
#endif
// Copy data to device-side buffers
err = hipMemcpy(row_d, csr->row_array, num_nodes * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy row_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
err = hipMemcpy(col_d, csr->col_array, num_edges * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy col_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
err = hipMemcpy(node_value_d, node_value, num_nodes * sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy feature_d (size:%d) => %s\n", num_nodes, hipGetErrorString(err));
return -1;
}
// Work dimensions
int block_size = 128;
int num_blocks = (num_nodes + block_size - 1) / block_size;
dim3 threads(block_size, 1, 1);
dim3 grid(num_blocks, 1, 1);
// Launch the initialization kernel
init <<<grid, threads>>>(s_array_d, c_array_d, c_array_u_d,
num_nodes, num_edges);
hipDeviceSynchronize();
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr, "ERROR: init kernel (%s)\n", hipGetErrorString(err));
return -1;
}
// Termination variable
int stop = 1;
int iterations = 0;
while (stop) {
stop = 0;
// Copy the termination variable to the device
err = hipMemcpy(stop_d, &stop, sizeof(int), hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: write stop_d variable (%s)\n", hipGetErrorString(err));
return -1;
}
// Launch mis1
mis1 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, min_array_d, stop_d, num_nodes,
num_edges);
// Launch mis2
mis2 <<<grid, threads>>>(row_d, col_d, node_value_d, s_array_d,
c_array_d, c_array_u_d, min_array_d, num_nodes,
num_edges);
// Launch mis3
mis3 <<<grid, threads>>>(c_array_u_d, c_array_d, num_nodes);
// Copy the termination variable back
err = hipMemcpy(&stop, stop_d, sizeof(int), hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: read stop_d variable (%s)\n", hipGetErrorString(err));
return -1;
}
iterations++;
}
hipDeviceSynchronize();
err = hipMemcpy(s_array, s_array_d, num_nodes * sizeof(int), hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr, "ERROR: hipMemcpy s_array_d failed (%s)\n", hipGetErrorString(err));
return -1;
}
#ifdef GEM5_FUSION
m5_work_end(0, 0);
#endif
double time2 = gettime();
// Print out the timing characterisitics
printf("number of iterations: %d\n", iterations);
printf("kernel + memcpy time %f ms\n", (time2 - time1) * 1000);
#if 0
// Print the set array
print_vector(s_array, num_nodes);
#endif
// Clean up the host-side arrays
free(node_value);
free(s_array);
csr->freeArrays();
free(csr);
// Clean up the device-side arrays
hipFree(row_d);
hipFree(col_d);
hipFree(c_array_d);
hipFree(s_array_d);
hipFree(node_value_d);
hipFree(min_array_d);
hipFree(stop_d);
return 0;
}
void print_vector(int *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%d\n", vector[i]);
}
fclose(fp);
}
void print_vectorf(float *vector, int num)
{
FILE * fp = fopen("result.out", "w");
if (!fp) {
printf("ERROR: unable to open result.txt\n");
}
for (int i = 0; i < num; i++) {
fprintf(fp, "%f\n", vector[i]);
}
fclose(fp);
} | .text
.file "mis.hip"
.globl _Z19__device_stub__initPiS_S_ii # -- Begin function _Z19__device_stub__initPiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__initPiS_S_ii,@function
_Z19__device_stub__initPiS_S_ii: # @_Z19__device_stub__initPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__initPiS_S_ii, .Lfunc_end0-_Z19__device_stub__initPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__mis1PiS_S_S_S_S_S_ii # -- Begin function _Z19__device_stub__mis1PiS_S_S_S_S_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__mis1PiS_S_S_S_S_S_ii,@function
_Z19__device_stub__mis1PiS_S_S_S_S_S_ii: # @_Z19__device_stub__mis1PiS_S_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4mis1PiS_S_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z19__device_stub__mis1PiS_S_S_S_S_S_ii, .Lfunc_end1-_Z19__device_stub__mis1PiS_S_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__mis2PiS_S_S_S_S_S_ii # -- Begin function _Z19__device_stub__mis2PiS_S_S_S_S_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__mis2PiS_S_S_S_S_S_ii,@function
_Z19__device_stub__mis2PiS_S_S_S_S_S_ii: # @_Z19__device_stub__mis2PiS_S_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4mis2PiS_S_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z19__device_stub__mis2PiS_S_S_S_S_S_ii, .Lfunc_end2-_Z19__device_stub__mis2PiS_S_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__mis3PiS_i # -- Begin function _Z19__device_stub__mis3PiS_i
.p2align 4, 0x90
.type _Z19__device_stub__mis3PiS_i,@function
_Z19__device_stub__mis3PiS_i: # @_Z19__device_stub__mis3PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mis3PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z19__device_stub__mis3PiS_i, .Lfunc_end3-_Z19__device_stub__mis3PiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB4_65
# %bb.1:
movq 8(%rsi), %rbx
movq 16(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $7, %edi
callq srand
testl %r14d, %r14d
je .LBB4_4
# %bb.2:
cmpl $1, %r14d
jne .LBB4_66
# %bb.3:
movq %rsp, %rsi
leaq 4(%rsp), %rdx
movq %rbx, %rdi
xorl %ecx, %ecx
callq _Z10parseMetisPcPiS0_b
jmp .LBB4_5
.LBB4_4:
movq %rsp, %rsi
leaq 4(%rsp), %rdx
movq %rbx, %rdi
xorl %ecx, %ecx
callq _Z8parseCOOPcPiS0_b
.LBB4_5:
movq %rax, %r15
movslq (%rsp), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
testq %rax, %rax
je .LBB4_45
.LBB4_6:
movslq (%rsp), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r12
testq %rax, %rax
je .LBB4_46
.LBB4_7:
movl (%rsp), %eax
testl %eax, %eax
jle .LBB4_10
# %bb.8: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 2047(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-2048, %ecx # imm = 0xF800
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
movslq (%rsp), %rax
cmpq %rax, %rbx
jl .LBB4_9
.LBB4_10: # %._crit_edge
movslq %eax, %rsi
shlq $2, %rsi
leaq 152(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_47
# %bb.11:
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 144(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_48
# %bb.12:
leaq 128(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_49
# %bb.13:
movslq (%rsp), %rsi
shlq $2, %rsi
leaq 160(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_50
# %bb.14:
movslq (%rsp), %rsi
shlq $2, %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_44
# %bb.15:
movslq (%rsp), %rsi
shlq $2, %rsi
leaq 168(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_44
# %bb.16:
movslq (%rsp), %rsi
shlq $2, %rsi
leaq 96(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_51
# %bb.17:
movslq (%rsp), %rsi
shlq $2, %rsi
leaq 136(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_52
# %bb.18:
callq _Z7gettimev
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 152(%rsp), %rdi
movq (%r15), %rsi
movslq (%rsp), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_53
# %bb.19:
movq 144(%rsp), %rdi
movq 8(%r15), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movslq (%rsp), %rdx
testl %eax, %eax
jne .LBB4_54
# %bb.20:
movq 136(%rsp), %rdi
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_55
# %bb.21:
movq %r12, 280(%rsp) # 8-byte Spill
movabsq $4294967424, %r12 # imm = 0x100000080
movl (%rsp), %eax
leal 127(%rax), %ecx
addl $254, %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $7, %eax
leaq (%rax,%r12), %r13
addq $-128, %r13
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq 168(%rsp), %rdx
movl (%rsp), %esi
movl 4(%rsp), %edi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 24(%rsp)
movl %esi, 120(%rsp)
movl %edi, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rax
movq %rax, 216(%rsp)
leaq 112(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z4initPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB4_60
# %bb.24: # %.lr.ph172
movq %r15, 272(%rsp) # 8-byte Spill
movl $1, 84(%rsp)
xorl %ebp, %ebp
leaq 84(%rsp), %r15
leaq 192(%rsp), %rbx
.p2align 4, 0x90
.LBB4_25: # =>This Inner Loop Header: Depth=1
movl $0, 84(%rsp)
movq 128(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_61
# %bb.26: # in Loop: Header=BB4_25 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_28
# %bb.27: # in Loop: Header=BB4_25 Depth=1
movq 152(%rsp), %rax
movq %rax, 72(%rsp)
movq 144(%rsp), %rax
movq %rax, 64(%rsp)
movq 136(%rsp), %rax
movq %rax, 24(%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
movq 104(%rsp), %rax
movq %rax, 8(%rsp)
movq 160(%rsp), %rax
movq %rax, 120(%rsp)
movq 128(%rsp), %rax
movq %rax, 112(%rsp)
movl (%rsp), %eax
movl %eax, 92(%rsp)
movl 4(%rsp), %eax
movl %eax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
leaq 120(%rsp), %rax
movq %rax, 232(%rsp)
leaq 112(%rsp), %rax
movq %rax, 240(%rsp)
leaq 92(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z4mis1PiS_S_S_S_S_S_ii, %edi
movq %rbx, %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_28: # in Loop: Header=BB4_25 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_30
# %bb.29: # in Loop: Header=BB4_25 Depth=1
movq 152(%rsp), %rax
movq %rax, 72(%rsp)
movq 144(%rsp), %rax
movq %rax, 64(%rsp)
movq 136(%rsp), %rax
movq %rax, 24(%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
movq 104(%rsp), %rax
movq %rax, 8(%rsp)
movq 168(%rsp), %rax
movq %rax, 120(%rsp)
movq 160(%rsp), %rax
movq %rax, 112(%rsp)
movl (%rsp), %eax
movl %eax, 92(%rsp)
movl 4(%rsp), %eax
movl %eax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
leaq 120(%rsp), %rax
movq %rax, 232(%rsp)
leaq 112(%rsp), %rax
movq %rax, 240(%rsp)
leaq 92(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z4mis2PiS_S_S_S_S_S_ii, %edi
movq %rbx, %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_30: # in Loop: Header=BB4_25 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_32
# %bb.31: # in Loop: Header=BB4_25 Depth=1
movq 168(%rsp), %rax
movq 104(%rsp), %rcx
movl (%rsp), %edx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z4mis3PiS_i, %edi
movq %rbx, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_32: # in Loop: Header=BB4_25 Depth=1
movq 128(%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_62
# %bb.33: # in Loop: Header=BB4_25 Depth=1
incl %ebp
cmpl $0, 84(%rsp)
jne .LBB4_25
# %bb.34: # %._crit_edge173
callq hipDeviceSynchronize
movq 96(%rsp), %rsi
movslq (%rsp), %rdx
shlq $2, %rdx
movq 280(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_63
# %bb.35:
callq _Z7gettimev
movsd %xmm0, 264(%rsp) # 8-byte Spill
movl $.L.str.17, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 288(%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI4_0(%rip), %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq 272(%rsp), %rbx # 8-byte Reload
movq (%rbx), %rdi
testq %rdi, %rdi
je .LBB4_37
# %bb.36:
callq free
movq $0, (%rbx)
.LBB4_37:
movq 8(%rbx), %rdi
testq %rdi, %rdi
je .LBB4_39
# %bb.38:
callq free
movq $0, 8(%rbx)
.LBB4_39:
movq 16(%rbx), %rdi
testq %rdi, %rdi
je .LBB4_41
# %bb.40:
callq free
movq $0, 16(%rbx)
.LBB4_41:
movq 24(%rbx), %rdi
testq %rdi, %rdi
je .LBB4_43
# %bb.42:
callq free
movq $0, 24(%rbx)
.LBB4_43: # %_ZN12csr_arrays_t10freeArraysEv.exit
movq %rbx, %rdi
callq free
movq 152(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB4_59
.LBB4_44:
movq stderr(%rip), %rbx
movl (%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB4_56
.LBB4_45:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_6
.LBB4_46:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_7
.LBB4_47:
movq stderr(%rip), %rbx
movl (%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB4_56
.LBB4_48:
movq stderr(%rip), %rbx
movl 4(%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB4_56
.LBB4_49:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movl $1, %edx
jmp .LBB4_57
.LBB4_50:
movq stderr(%rip), %rbx
movl (%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB4_56
.LBB4_51:
movq stderr(%rip), %rbx
movl (%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB4_56
.LBB4_52:
movq stderr(%rip), %rbx
movl (%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB4_56
.LBB4_53:
movq stderr(%rip), %rbx
movl (%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB4_56
.LBB4_54:
movq stderr(%rip), %rbx
movl %eax, %edi
movq %rdx, %r14
callq hipGetErrorString
movl $.L.str.11, %esi
movq %rbx, %rdi
movl %r14d, %edx
jmp .LBB4_57
.LBB4_55:
movq stderr(%rip), %rbx
movl (%rsp), %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
.LBB4_56:
movq %rbx, %rdi
movl %ebp, %edx
.LBB4_57:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
.LBB4_58:
movl $-1, %eax
.LBB4_59:
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_60:
.cfi_def_cfa_offset 352
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB4_64
.LBB4_61:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %esi
jmp .LBB4_64
.LBB4_62:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB4_64
.LBB4_63:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
.LBB4_64:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB4_58
.LBB4_65:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $25, %esi
jmp .LBB4_67
.LBB4_66:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $18, %esi
.LBB4_67:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.globl _Z12print_vectorPii # -- Begin function _Z12print_vectorPii
.p2align 4, 0x90
.type _Z12print_vectorPii,@function
_Z12print_vectorPii: # @_Z12print_vectorPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str.19, %edi
movl $.L.str.20, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB5_2
# %bb.1:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB5_2:
testl %ebp, %ebp
jle .LBB5_5
# %bb.3: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl $.L.str.22, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB5_4
.LBB5_5: # %._crit_edge
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end5:
.size _Z12print_vectorPii, .Lfunc_end5-_Z12print_vectorPii
.cfi_endproc
# -- End function
.globl _Z13print_vectorfPfi # -- Begin function _Z13print_vectorfPfi
.p2align 4, 0x90
.type _Z13print_vectorfPfi,@function
_Z13print_vectorfPfi: # @_Z13print_vectorfPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str.19, %edi
movl $.L.str.20, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB6_2
# %bb.1:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB6_2:
testl %ebp, %ebp
jle .LBB6_5
# %bb.3: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.23, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r15
jne .LBB6_4
.LBB6_5: # %._crit_edge
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end6:
.size _Z13print_vectorfPfi, .Lfunc_end6-_Z13print_vectorfPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mis1PiS_S_S_S_S_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mis2PiS_S_S_S_S_S_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mis3PiS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initPiS_S_ii,@object # @_Z4initPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z4initPiS_S_ii
.p2align 3, 0x0
_Z4initPiS_S_ii:
.quad _Z19__device_stub__initPiS_S_ii
.size _Z4initPiS_S_ii, 8
.type _Z4mis1PiS_S_S_S_S_S_ii,@object # @_Z4mis1PiS_S_S_S_S_S_ii
.globl _Z4mis1PiS_S_S_S_S_S_ii
.p2align 3, 0x0
_Z4mis1PiS_S_S_S_S_S_ii:
.quad _Z19__device_stub__mis1PiS_S_S_S_S_S_ii
.size _Z4mis1PiS_S_S_S_S_S_ii, 8
.type _Z4mis2PiS_S_S_S_S_S_ii,@object # @_Z4mis2PiS_S_S_S_S_S_ii
.globl _Z4mis2PiS_S_S_S_S_S_ii
.p2align 3, 0x0
_Z4mis2PiS_S_S_S_S_S_ii:
.quad _Z19__device_stub__mis2PiS_S_S_S_S_S_ii
.size _Z4mis2PiS_S_S_S_S_S_ii, 8
.type _Z4mis3PiS_i,@object # @_Z4mis3PiS_i
.globl _Z4mis3PiS_i
.p2align 3, 0x0
_Z4mis3PiS_i:
.quad _Z19__device_stub__mis3PiS_i
.size _Z4mis3PiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "You did something wrong!\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "reserve for future"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "malloc failed node_value\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ERROR: hipMalloc row_d (size:%d) => %s\n"
.size .L.str.3, 40
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "ERROR: hipMalloc col_d (size:%d) => %s\n"
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ERROR: hipMalloc stop_d (size:%d) => %s\n"
.size .L.str.5, 41
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "ERROR: hipMalloc min_array_d (size:%d) => %s\n"
.size .L.str.6, 46
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "ERROR: hipMalloc c_array_d (size:%d) => %s\n"
.size .L.str.7, 44
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ERROR: hipMalloc s_array_d (size:%d) => %s\n"
.size .L.str.8, 44
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "ERROR: hipMalloc node_value_d (size:%d) => %s\n"
.size .L.str.9, 47
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "ERROR: hipMemcpy row_d (size:%d) => %s\n"
.size .L.str.10, 40
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "ERROR: hipMemcpy col_d (size:%d) => %s\n"
.size .L.str.11, 40
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "ERROR: hipMemcpy feature_d (size:%d) => %s\n"
.size .L.str.12, 44
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "ERROR: init kernel (%s)\n"
.size .L.str.13, 25
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "ERROR: write stop_d variable (%s)\n"
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "ERROR: read stop_d variable (%s)\n"
.size .L.str.15, 34
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "ERROR: hipMemcpy s_array_d failed (%s)\n"
.size .L.str.16, 40
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "number of iterations: %d\n"
.size .L.str.17, 26
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "kernel + memcpy time %f ms\n"
.size .L.str.18, 28
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "result.out"
.size .L.str.19, 11
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "w"
.size .L.str.20, 2
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "%d\n"
.size .L.str.22, 4
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "%f\n"
.size .L.str.23, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initPiS_S_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4mis1PiS_S_S_S_S_S_ii"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z4mis2PiS_S_S_S_S_S_ii"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z4mis3PiS_i"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "ERROR: unable to open result.txt"
.size .Lstr.1, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initPiS_S_ii
.addrsig_sym _Z19__device_stub__mis1PiS_S_S_S_S_S_ii
.addrsig_sym _Z19__device_stub__mis2PiS_S_S_S_S_S_ii
.addrsig_sym _Z19__device_stub__mis3PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initPiS_S_ii
.addrsig_sym _Z4mis1PiS_S_S_S_S_S_ii
.addrsig_sym _Z4mis2PiS_S_S_S_S_S_ii
.addrsig_sym _Z4mis3PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
/**
* Tempo sequencial: 0m0.404s
* Tempo CUDA: 0m1.970s (overhead de copiar os dados para a GPU)
*/
__global__ void scan_cuda(double* a, double *s, int width) {
// kernel scan
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Cria vetor na memória local.
__shared__ double partial[1024];
// Carrega elementos do vetor da memória global para a local.
if (block + thread < width) {
partial[thread] = a[block + thread];
}
// espera que todas as threads tenham carregado seus elementos
__syncthreads();
// Realiza o scan em log n passos.
for (int i = 1; i < blockDim.x; i *= 2) {
// Se thread ainda participa, atribui a soma para
// uma variável temporária.
double temp = 0;
if (thread >= i) {
temp = partial[thread] + partial[thread - i];
// Espera todas as threads fazerem as somas.
__syncthreads();
// Copia o valor calculado em definitivo para o
// vetor local.
partial[thread] = temp;
}
__syncthreads();
}
// Copia da memória local para a global.
if (block + thread < width) {
a[block + thread] = partial[thread];
}
// Se for a última thread do block, copia o seu valor
// para o vetor de saída.
if (thread == blockDim.x - 1) {
s[blockIdx.x + 1] = a[block + thread];
}
}
__global__ void add_cuda(double *a, double *s, int width) {
// kernel soma
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Adiciona o somatório do último elemento do bloco anterior
// ao elemento atual.
if (block + thread < width) {
a[block + thread] += s[blockIdx.x];
}
}
int main()
{
int width = 40000000;
int size = width * sizeof(double);
int block_size = 1024;
int num_blocks = (width-1)/block_size + 1;
int s_size = (num_blocks * sizeof(double));
double *a = (double*) malloc (size);
double *s = (double*) malloc (s_size);
for(int i = 0; i < width; i++)
a[i] = i;
double *d_a, *d_s;
// alocar vetores "a" e "s" no device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_s, s_size);
// copiar vetor "a" para o device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
// definição do número de blocos e threads (dimGrid e dimBlock)
dim3 dimGrid(num_blocks, 1, 1);
dim3 dimBlock(block_size, 1, 1);
// chamada do kernel scan
scan_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar vetor "s" para o host
cudaMemcpy(s, d_s, s_size, cudaMemcpyDeviceToHost);
// scan no host (já implementado)
s[0] = 0;
for (int i = 1; i < num_blocks; i++)
s[i] += s[i-1];
// copiar vetor "s" para o device
cudaMemcpy(d_s, s, s_size, cudaMemcpyHostToDevice);
// chamada do kernel da soma
add_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar o vetor "a" para o host
cudaMemcpy(a, d_a, size, cudaMemcpyDeviceToHost);
printf("\na[%d] = %f\n", width-1, a[width-1]);
cudaFree(d_a);
cudaFree(d_s);
} | code for sm_80
Function : _Z8add_cudaPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R3, R5, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ DADD R6, R6, R2 ; /* 0x0000000006067229 */
/* 0x004e0e0000000002 */
/*00d0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9scan_cudaPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0xf0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*0080*/ IMAD R2, R8, c[0x0][0x0], R9 ; /* 0x0000000008027a24 */
/* 0x001fca00078e0209 */
/*0090*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x040fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0203 */
/*00b0*/ @P0 BRA 0xe0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ STS.64 [R9.X8], R4 ; /* 0x0000000409007388 */
/* 0x0041e40000008a00 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @!P1 BRA 0x1e0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*0120*/ ISETP.GE.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f26270 */
/*0130*/ @P1 IMAD.IADD R6, R9, 0x1, -R0 ; /* 0x0000000109061824 */
/* 0x000fe200078e0a00 */
/*0140*/ @P1 LDS.64 R4, [R9.X8] ; /* 0x0000000009041984 */
/* 0x001fe20000008a00 */
/*0150*/ @P1 WARPSYNC 0xffffffff ; /* 0xffffffff00001948 */
/* 0x000fe20003800000 */
/*0160*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc600000006ff */
/*0170*/ @P1 LDS.64 R6, [R6.X8] ; /* 0x0000000006061984 */
/* 0x000e240000008a00 */
/*0180*/ @P1 DADD R4, R4, R6 ; /* 0x0000000004041229 */
/* 0x001e240000000006 */
/*0190*/ @P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000001b1d */
/* 0x000fec0000010000 */
/*01a0*/ @P1 STS.64 [R9.X8], R4 ; /* 0x0000000409001388 */
/* 0x0011e80000008a00 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f26070 */
/*01d0*/ @!P1 BRA 0x120 ; /* 0xffffff4000009947 */
/* 0x001fea000383ffff */
/*01e0*/ @!P0 LDS.64 R4, [R9.X8] ; /* 0x0000000009048984 */
/* 0x001e220000008a00 */
/*01f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0200*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0210*/ ISETP.NE.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf25270 */
/*0220*/ @!P0 STG.E.64 [R2.64], R4 ; /* 0x0000000402008986 */
/* 0x0011d8000c101b06 */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0240*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x001ea2000c1e1b00 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0270*/ STG.E.64 [R4.64+0x8], R2 ; /* 0x0000080204007986 */
/* 0x004fe2000c101b06 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
/**
* Tempo sequencial: 0m0.404s
* Tempo CUDA: 0m1.970s (overhead de copiar os dados para a GPU)
*/
__global__ void scan_cuda(double* a, double *s, int width) {
// kernel scan
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Cria vetor na memória local.
__shared__ double partial[1024];
// Carrega elementos do vetor da memória global para a local.
if (block + thread < width) {
partial[thread] = a[block + thread];
}
// espera que todas as threads tenham carregado seus elementos
__syncthreads();
// Realiza o scan em log n passos.
for (int i = 1; i < blockDim.x; i *= 2) {
// Se thread ainda participa, atribui a soma para
// uma variável temporária.
double temp = 0;
if (thread >= i) {
temp = partial[thread] + partial[thread - i];
// Espera todas as threads fazerem as somas.
__syncthreads();
// Copia o valor calculado em definitivo para o
// vetor local.
partial[thread] = temp;
}
__syncthreads();
}
// Copia da memória local para a global.
if (block + thread < width) {
a[block + thread] = partial[thread];
}
// Se for a última thread do block, copia o seu valor
// para o vetor de saída.
if (thread == blockDim.x - 1) {
s[blockIdx.x + 1] = a[block + thread];
}
}
__global__ void add_cuda(double *a, double *s, int width) {
// kernel soma
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Adiciona o somatório do último elemento do bloco anterior
// ao elemento atual.
if (block + thread < width) {
a[block + thread] += s[blockIdx.x];
}
}
int main()
{
int width = 40000000;
int size = width * sizeof(double);
int block_size = 1024;
int num_blocks = (width-1)/block_size + 1;
int s_size = (num_blocks * sizeof(double));
double *a = (double*) malloc (size);
double *s = (double*) malloc (s_size);
for(int i = 0; i < width; i++)
a[i] = i;
double *d_a, *d_s;
// alocar vetores "a" e "s" no device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_s, s_size);
// copiar vetor "a" para o device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
// definição do número de blocos e threads (dimGrid e dimBlock)
dim3 dimGrid(num_blocks, 1, 1);
dim3 dimBlock(block_size, 1, 1);
// chamada do kernel scan
scan_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar vetor "s" para o host
cudaMemcpy(s, d_s, s_size, cudaMemcpyDeviceToHost);
// scan no host (já implementado)
s[0] = 0;
for (int i = 1; i < num_blocks; i++)
s[i] += s[i-1];
// copiar vetor "s" para o device
cudaMemcpy(d_s, s, s_size, cudaMemcpyHostToDevice);
// chamada do kernel da soma
add_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar o vetor "a" para o host
cudaMemcpy(a, d_a, size, cudaMemcpyDeviceToHost);
printf("\na[%d] = %f\n", width-1, a[width-1]);
cudaFree(d_a);
cudaFree(d_s);
} | .file "tmpxft_00132f60_00000000-6_scan_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9scan_cudaPdS_iPdS_i
.type _Z31__device_stub__Z9scan_cudaPdS_iPdS_i, @function
_Z31__device_stub__Z9scan_cudaPdS_iPdS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9scan_cudaPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9scan_cudaPdS_iPdS_i, .-_Z31__device_stub__Z9scan_cudaPdS_iPdS_i
.globl _Z9scan_cudaPdS_i
.type _Z9scan_cudaPdS_i, @function
_Z9scan_cudaPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9scan_cudaPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9scan_cudaPdS_i, .-_Z9scan_cudaPdS_i
.globl _Z30__device_stub__Z8add_cudaPdS_iPdS_i
.type _Z30__device_stub__Z8add_cudaPdS_iPdS_i, @function
_Z30__device_stub__Z8add_cudaPdS_iPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8add_cudaPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z8add_cudaPdS_iPdS_i, .-_Z30__device_stub__Z8add_cudaPdS_iPdS_i
.globl _Z8add_cudaPdS_i
.type _Z8add_cudaPdS_i, @function
_Z8add_cudaPdS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8add_cudaPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8add_cudaPdS_i, .-_Z8add_cudaPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\na[%d] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $320000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $312504, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $40000000, %rax
jne .L20
movq %rsp, %rdi
movl $320000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $312504, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $320000000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $39063, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
movl $2, %ecx
movl $312504, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq $0x000000000, 0(%rbp)
leaq 8(%rbp), %rax
leaq 312504(%rbp), %rdx
.L22:
movsd (%rax), %xmm0
addsd -8(%rax), %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L22
movl $1, %ecx
movl $312504, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L23:
movl $2, %ecx
movl $320000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movsd 319999992(%rbx), %xmm0
movl $39999999, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $40000000, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z9scan_cudaPdS_iPdS_i
jmp .L21
.L29:
movl $40000000, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z8add_cudaPdS_iPdS_i
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z8add_cudaPdS_i"
.LC3:
.string "_Z9scan_cudaPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8add_cudaPdS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9scan_cudaPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
/**
* Tempo sequencial: 0m0.404s
* Tempo CUDA: 0m1.970s (overhead de copiar os dados para a GPU)
*/
__global__ void scan_cuda(double* a, double *s, int width) {
// kernel scan
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Cria vetor na memória local.
__shared__ double partial[1024];
// Carrega elementos do vetor da memória global para a local.
if (block + thread < width) {
partial[thread] = a[block + thread];
}
// espera que todas as threads tenham carregado seus elementos
__syncthreads();
// Realiza o scan em log n passos.
for (int i = 1; i < blockDim.x; i *= 2) {
// Se thread ainda participa, atribui a soma para
// uma variável temporária.
double temp = 0;
if (thread >= i) {
temp = partial[thread] + partial[thread - i];
// Espera todas as threads fazerem as somas.
__syncthreads();
// Copia o valor calculado em definitivo para o
// vetor local.
partial[thread] = temp;
}
__syncthreads();
}
// Copia da memória local para a global.
if (block + thread < width) {
a[block + thread] = partial[thread];
}
// Se for a última thread do block, copia o seu valor
// para o vetor de saída.
if (thread == blockDim.x - 1) {
s[blockIdx.x + 1] = a[block + thread];
}
}
__global__ void add_cuda(double *a, double *s, int width) {
// kernel soma
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Adiciona o somatório do último elemento do bloco anterior
// ao elemento atual.
if (block + thread < width) {
a[block + thread] += s[blockIdx.x];
}
}
int main()
{
int width = 40000000;
int size = width * sizeof(double);
int block_size = 1024;
int num_blocks = (width-1)/block_size + 1;
int s_size = (num_blocks * sizeof(double));
double *a = (double*) malloc (size);
double *s = (double*) malloc (s_size);
for(int i = 0; i < width; i++)
a[i] = i;
double *d_a, *d_s;
// alocar vetores "a" e "s" no device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_s, s_size);
// copiar vetor "a" para o device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
// definição do número de blocos e threads (dimGrid e dimBlock)
dim3 dimGrid(num_blocks, 1, 1);
dim3 dimBlock(block_size, 1, 1);
// chamada do kernel scan
scan_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar vetor "s" para o host
cudaMemcpy(s, d_s, s_size, cudaMemcpyDeviceToHost);
// scan no host (já implementado)
s[0] = 0;
for (int i = 1; i < num_blocks; i++)
s[i] += s[i-1];
// copiar vetor "s" para o device
cudaMemcpy(d_s, s, s_size, cudaMemcpyHostToDevice);
// chamada do kernel da soma
add_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar o vetor "a" para o host
cudaMemcpy(a, d_a, size, cudaMemcpyDeviceToHost);
printf("\na[%d] = %f\n", width-1, a[width-1]);
cudaFree(d_a);
cudaFree(d_s);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Tempo sequencial: 0m0.404s
* Tempo CUDA: 0m1.970s (overhead de copiar os dados para a GPU)
*/
__global__ void scan_cuda(double* a, double *s, int width) {
// kernel scan
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Cria vetor na memória local.
__shared__ double partial[1024];
// Carrega elementos do vetor da memória global para a local.
if (block + thread < width) {
partial[thread] = a[block + thread];
}
// espera que todas as threads tenham carregado seus elementos
__syncthreads();
// Realiza o scan em log n passos.
for (int i = 1; i < blockDim.x; i *= 2) {
// Se thread ainda participa, atribui a soma para
// uma variável temporária.
double temp = 0;
if (thread >= i) {
temp = partial[thread] + partial[thread - i];
// Espera todas as threads fazerem as somas.
__syncthreads();
// Copia o valor calculado em definitivo para o
// vetor local.
partial[thread] = temp;
}
__syncthreads();
}
// Copia da memória local para a global.
if (block + thread < width) {
a[block + thread] = partial[thread];
}
// Se for a última thread do block, copia o seu valor
// para o vetor de saída.
if (thread == blockDim.x - 1) {
s[blockIdx.x + 1] = a[block + thread];
}
}
__global__ void add_cuda(double *a, double *s, int width) {
// kernel soma
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Adiciona o somatório do último elemento do bloco anterior
// ao elemento atual.
if (block + thread < width) {
a[block + thread] += s[blockIdx.x];
}
}
int main()
{
int width = 40000000;
int size = width * sizeof(double);
int block_size = 1024;
int num_blocks = (width-1)/block_size + 1;
int s_size = (num_blocks * sizeof(double));
double *a = (double*) malloc (size);
double *s = (double*) malloc (s_size);
for(int i = 0; i < width; i++)
a[i] = i;
double *d_a, *d_s;
// alocar vetores "a" e "s" no device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_s, s_size);
// copiar vetor "a" para o device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
// definição do número de blocos e threads (dimGrid e dimBlock)
dim3 dimGrid(num_blocks, 1, 1);
dim3 dimBlock(block_size, 1, 1);
// chamada do kernel scan
scan_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar vetor "s" para o host
hipMemcpy(s, d_s, s_size, hipMemcpyDeviceToHost);
// scan no host (já implementado)
s[0] = 0;
for (int i = 1; i < num_blocks; i++)
s[i] += s[i-1];
// copiar vetor "s" para o device
hipMemcpy(d_s, s, s_size, hipMemcpyHostToDevice);
// chamada do kernel da soma
add_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar o vetor "a" para o host
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
printf("\na[%d] = %f\n", width-1, a[width-1]);
hipFree(d_a);
hipFree(d_s);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Tempo sequencial: 0m0.404s
* Tempo CUDA: 0m1.970s (overhead de copiar os dados para a GPU)
*/
__global__ void scan_cuda(double* a, double *s, int width) {
// kernel scan
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Cria vetor na memória local.
__shared__ double partial[1024];
// Carrega elementos do vetor da memória global para a local.
if (block + thread < width) {
partial[thread] = a[block + thread];
}
// espera que todas as threads tenham carregado seus elementos
__syncthreads();
// Realiza o scan em log n passos.
for (int i = 1; i < blockDim.x; i *= 2) {
// Se thread ainda participa, atribui a soma para
// uma variável temporária.
double temp = 0;
if (thread >= i) {
temp = partial[thread] + partial[thread - i];
// Espera todas as threads fazerem as somas.
__syncthreads();
// Copia o valor calculado em definitivo para o
// vetor local.
partial[thread] = temp;
}
__syncthreads();
}
// Copia da memória local para a global.
if (block + thread < width) {
a[block + thread] = partial[thread];
}
// Se for a última thread do block, copia o seu valor
// para o vetor de saída.
if (thread == blockDim.x - 1) {
s[blockIdx.x + 1] = a[block + thread];
}
}
__global__ void add_cuda(double *a, double *s, int width) {
// kernel soma
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Adiciona o somatório do último elemento do bloco anterior
// ao elemento atual.
if (block + thread < width) {
a[block + thread] += s[blockIdx.x];
}
}
int main()
{
int width = 40000000;
int size = width * sizeof(double);
int block_size = 1024;
int num_blocks = (width-1)/block_size + 1;
int s_size = (num_blocks * sizeof(double));
double *a = (double*) malloc (size);
double *s = (double*) malloc (s_size);
for(int i = 0; i < width; i++)
a[i] = i;
double *d_a, *d_s;
// alocar vetores "a" e "s" no device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_s, s_size);
// copiar vetor "a" para o device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
// definição do número de blocos e threads (dimGrid e dimBlock)
dim3 dimGrid(num_blocks, 1, 1);
dim3 dimBlock(block_size, 1, 1);
// chamada do kernel scan
scan_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar vetor "s" para o host
hipMemcpy(s, d_s, s_size, hipMemcpyDeviceToHost);
// scan no host (já implementado)
s[0] = 0;
for (int i = 1; i < num_blocks; i++)
s[i] += s[i-1];
// copiar vetor "s" para o device
hipMemcpy(d_s, s, s_size, hipMemcpyHostToDevice);
// chamada do kernel da soma
add_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar o vetor "a" para o host
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
printf("\na[%d] = %f\n", width-1, a[width-1]);
hipFree(d_a);
hipFree(d_s);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9scan_cudaPdS_i
.globl _Z9scan_cudaPdS_i
.p2align 8
.type _Z9scan_cudaPdS_i,@function
_Z9scan_cudaPdS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s6, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b32_e32 v5, 3, v0
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[3:4]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s6, 1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s6, s6, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s6, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_mov_b32 s7, exec_lo
v_cmpx_le_u32_e64 s6, v0
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v4, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 3, v4
ds_load_b64 v[4:5], v3
ds_load_b64 v[6:7], v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_f64 v[4:5], v[4:5], v[6:7]
ds_store_b64 v3, v[4:5]
s_branch .LBB0_4
.LBB0_7:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v3, 3, v0
v_lshlrev_b64 v[5:6], 3, v[1:2]
ds_load_b64 v[3:4], v3
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s3, s3, -1
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s3, v0
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s2, s15, 1
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[2:3], 3
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9scan_cudaPdS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9scan_cudaPdS_i, .Lfunc_end0-_Z9scan_cudaPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8add_cudaPdS_i
.globl _Z8add_cudaPdS_i
.p2align 8
.type _Z8add_cudaPdS_i,@function
_Z8add_cudaPdS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 3
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[2:3], s[0:1], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_cudaPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8add_cudaPdS_i, .Lfunc_end1-_Z8add_cudaPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9scan_cudaPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9scan_cudaPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_cudaPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8add_cudaPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Tempo sequencial: 0m0.404s
* Tempo CUDA: 0m1.970s (overhead de copiar os dados para a GPU)
*/
__global__ void scan_cuda(double* a, double *s, int width) {
// kernel scan
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Cria vetor na memória local.
__shared__ double partial[1024];
// Carrega elementos do vetor da memória global para a local.
if (block + thread < width) {
partial[thread] = a[block + thread];
}
// espera que todas as threads tenham carregado seus elementos
__syncthreads();
// Realiza o scan em log n passos.
for (int i = 1; i < blockDim.x; i *= 2) {
// Se thread ainda participa, atribui a soma para
// uma variável temporária.
double temp = 0;
if (thread >= i) {
temp = partial[thread] + partial[thread - i];
// Espera todas as threads fazerem as somas.
__syncthreads();
// Copia o valor calculado em definitivo para o
// vetor local.
partial[thread] = temp;
}
__syncthreads();
}
// Copia da memória local para a global.
if (block + thread < width) {
a[block + thread] = partial[thread];
}
// Se for a última thread do block, copia o seu valor
// para o vetor de saída.
if (thread == blockDim.x - 1) {
s[blockIdx.x + 1] = a[block + thread];
}
}
__global__ void add_cuda(double *a, double *s, int width) {
// kernel soma
int thread = threadIdx.x;
int block = blockIdx.x * blockDim.x;
// Adiciona o somatório do último elemento do bloco anterior
// ao elemento atual.
if (block + thread < width) {
a[block + thread] += s[blockIdx.x];
}
}
int main()
{
int width = 40000000;
int size = width * sizeof(double);
int block_size = 1024;
int num_blocks = (width-1)/block_size + 1;
int s_size = (num_blocks * sizeof(double));
double *a = (double*) malloc (size);
double *s = (double*) malloc (s_size);
for(int i = 0; i < width; i++)
a[i] = i;
double *d_a, *d_s;
// alocar vetores "a" e "s" no device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_s, s_size);
// copiar vetor "a" para o device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
// definição do número de blocos e threads (dimGrid e dimBlock)
dim3 dimGrid(num_blocks, 1, 1);
dim3 dimBlock(block_size, 1, 1);
// chamada do kernel scan
scan_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar vetor "s" para o host
hipMemcpy(s, d_s, s_size, hipMemcpyDeviceToHost);
// scan no host (já implementado)
s[0] = 0;
for (int i = 1; i < num_blocks; i++)
s[i] += s[i-1];
// copiar vetor "s" para o device
hipMemcpy(d_s, s, s_size, hipMemcpyHostToDevice);
// chamada do kernel da soma
add_cuda<<<dimGrid, dimBlock>>>(d_a, d_s, width);
// copiar o vetor "a" para o host
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
printf("\na[%d] = %f\n", width-1, a[width-1]);
hipFree(d_a);
hipFree(d_s);
} | .text
.file "scan_cuda.hip"
.globl _Z24__device_stub__scan_cudaPdS_i # -- Begin function _Z24__device_stub__scan_cudaPdS_i
.p2align 4, 0x90
.type _Z24__device_stub__scan_cudaPdS_i,@function
_Z24__device_stub__scan_cudaPdS_i: # @_Z24__device_stub__scan_cudaPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9scan_cudaPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__scan_cudaPdS_i, .Lfunc_end0-_Z24__device_stub__scan_cudaPdS_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__add_cudaPdS_i # -- Begin function _Z23__device_stub__add_cudaPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__add_cudaPdS_i,@function
_Z23__device_stub__add_cudaPdS_i: # @_Z23__device_stub__add_cudaPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8add_cudaPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__add_cudaPdS_i, .Lfunc_end1-_Z23__device_stub__add_cudaPdS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $320000000, %edi # imm = 0x1312D000
callq malloc
movq %rax, %rbx
movl $312504, %edi # imm = 0x4C4B8
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq $40000000, %rax # imm = 0x2625A00
jne .LBB2_1
# %bb.2:
movabsq $4294968320, %r15 # imm = 0x100000400
leaq 24(%rsp), %rdi
movl $320000000, %esi # imm = 0x1312D000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $312504, %esi # imm = 0x4C4B8
callq hipMalloc
movq 24(%rsp), %rdi
movl $320000000, %edx # imm = 0x1312D000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 38039(%r15), %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $40000000, 12(%rsp) # imm = 0x2625A00
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9scan_cudaPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 16(%rsp), %rsi
movl $312504, %edx # imm = 0x4C4B8
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq $0, (%r14)
movl $1, %eax
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
addsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $39063, %rax # imm = 0x9897
jne .LBB2_5
# %bb.6:
movq 16(%rsp), %rdi
movl $312504, %edx # imm = 0x4C4B8
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $40000000, 12(%rsp) # imm = 0x2625A00
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8add_cudaPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 24(%rsp), %rsi
movl $320000000, %edx # imm = 0x1312D000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movsd 319999992(%rbx), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movl $39999999, %esi # imm = 0x26259FF
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9scan_cudaPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8add_cudaPdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9scan_cudaPdS_i,@object # @_Z9scan_cudaPdS_i
.section .rodata,"a",@progbits
.globl _Z9scan_cudaPdS_i
.p2align 3, 0x0
_Z9scan_cudaPdS_i:
.quad _Z24__device_stub__scan_cudaPdS_i
.size _Z9scan_cudaPdS_i, 8
.type _Z8add_cudaPdS_i,@object # @_Z8add_cudaPdS_i
.globl _Z8add_cudaPdS_i
.p2align 3, 0x0
_Z8add_cudaPdS_i:
.quad _Z23__device_stub__add_cudaPdS_i
.size _Z8add_cudaPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\na[%d] = %f\n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9scan_cudaPdS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8add_cudaPdS_i"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__scan_cudaPdS_i
.addrsig_sym _Z23__device_stub__add_cudaPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9scan_cudaPdS_i
.addrsig_sym _Z8add_cudaPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8add_cudaPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R3, R5, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ DADD R6, R6, R2 ; /* 0x0000000006067229 */
/* 0x004e0e0000000002 */
/*00d0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9scan_cudaPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0xf0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*0080*/ IMAD R2, R8, c[0x0][0x0], R9 ; /* 0x0000000008027a24 */
/* 0x001fca00078e0209 */
/*0090*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x040fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0203 */
/*00b0*/ @P0 BRA 0xe0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ STS.64 [R9.X8], R4 ; /* 0x0000000409007388 */
/* 0x0041e40000008a00 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @!P1 BRA 0x1e0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*0120*/ ISETP.GE.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f26270 */
/*0130*/ @P1 IMAD.IADD R6, R9, 0x1, -R0 ; /* 0x0000000109061824 */
/* 0x000fe200078e0a00 */
/*0140*/ @P1 LDS.64 R4, [R9.X8] ; /* 0x0000000009041984 */
/* 0x001fe20000008a00 */
/*0150*/ @P1 WARPSYNC 0xffffffff ; /* 0xffffffff00001948 */
/* 0x000fe20003800000 */
/*0160*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc600000006ff */
/*0170*/ @P1 LDS.64 R6, [R6.X8] ; /* 0x0000000006061984 */
/* 0x000e240000008a00 */
/*0180*/ @P1 DADD R4, R4, R6 ; /* 0x0000000004041229 */
/* 0x001e240000000006 */
/*0190*/ @P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000001b1d */
/* 0x000fec0000010000 */
/*01a0*/ @P1 STS.64 [R9.X8], R4 ; /* 0x0000000409001388 */
/* 0x0011e80000008a00 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f26070 */
/*01d0*/ @!P1 BRA 0x120 ; /* 0xffffff4000009947 */
/* 0x001fea000383ffff */
/*01e0*/ @!P0 LDS.64 R4, [R9.X8] ; /* 0x0000000009048984 */
/* 0x001e220000008a00 */
/*01f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0200*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0210*/ ISETP.NE.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf25270 */
/*0220*/ @!P0 STG.E.64 [R2.64], R4 ; /* 0x0000000402008986 */
/* 0x0011d8000c101b06 */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0240*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x001ea2000c1e1b00 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0270*/ STG.E.64 [R4.64+0x8], R2 ; /* 0x0000080204007986 */
/* 0x004fe2000c101b06 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9scan_cudaPdS_i
.globl _Z9scan_cudaPdS_i
.p2align 8
.type _Z9scan_cudaPdS_i,@function
_Z9scan_cudaPdS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s6, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b32_e32 v5, 3, v0
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[3:4]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s6, 1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s6, s6, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s6, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_mov_b32 s7, exec_lo
v_cmpx_le_u32_e64 s6, v0
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v4, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 3, v4
ds_load_b64 v[4:5], v3
ds_load_b64 v[6:7], v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_f64 v[4:5], v[4:5], v[6:7]
ds_store_b64 v3, v[4:5]
s_branch .LBB0_4
.LBB0_7:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v3, 3, v0
v_lshlrev_b64 v[5:6], 3, v[1:2]
ds_load_b64 v[3:4], v3
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s3, s3, -1
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s3, v0
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s2, s15, 1
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[2:3], 3
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9scan_cudaPdS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9scan_cudaPdS_i, .Lfunc_end0-_Z9scan_cudaPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8add_cudaPdS_i
.globl _Z8add_cudaPdS_i
.p2align 8
.type _Z8add_cudaPdS_i,@function
_Z8add_cudaPdS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 3
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[2:3], s[0:1], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_cudaPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8add_cudaPdS_i, .Lfunc_end1-_Z8add_cudaPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9scan_cudaPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9scan_cudaPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_cudaPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8add_cudaPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00132f60_00000000-6_scan_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9scan_cudaPdS_iPdS_i
.type _Z31__device_stub__Z9scan_cudaPdS_iPdS_i, @function
_Z31__device_stub__Z9scan_cudaPdS_iPdS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9scan_cudaPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9scan_cudaPdS_iPdS_i, .-_Z31__device_stub__Z9scan_cudaPdS_iPdS_i
.globl _Z9scan_cudaPdS_i
.type _Z9scan_cudaPdS_i, @function
_Z9scan_cudaPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9scan_cudaPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9scan_cudaPdS_i, .-_Z9scan_cudaPdS_i
.globl _Z30__device_stub__Z8add_cudaPdS_iPdS_i
.type _Z30__device_stub__Z8add_cudaPdS_iPdS_i, @function
_Z30__device_stub__Z8add_cudaPdS_iPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8add_cudaPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z8add_cudaPdS_iPdS_i, .-_Z30__device_stub__Z8add_cudaPdS_iPdS_i
.globl _Z8add_cudaPdS_i
.type _Z8add_cudaPdS_i, @function
_Z8add_cudaPdS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8add_cudaPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8add_cudaPdS_i, .-_Z8add_cudaPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\na[%d] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $320000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $312504, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $40000000, %rax
jne .L20
movq %rsp, %rdi
movl $320000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $312504, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $320000000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $39063, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
movl $2, %ecx
movl $312504, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq $0x000000000, 0(%rbp)
leaq 8(%rbp), %rax
leaq 312504(%rbp), %rdx
.L22:
movsd (%rax), %xmm0
addsd -8(%rax), %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L22
movl $1, %ecx
movl $312504, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L23:
movl $2, %ecx
movl $320000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movsd 319999992(%rbx), %xmm0
movl $39999999, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $40000000, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z9scan_cudaPdS_iPdS_i
jmp .L21
.L29:
movl $40000000, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z8add_cudaPdS_iPdS_i
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z8add_cudaPdS_i"
.LC3:
.string "_Z9scan_cudaPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8add_cudaPdS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9scan_cudaPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan_cuda.hip"
.globl _Z24__device_stub__scan_cudaPdS_i # -- Begin function _Z24__device_stub__scan_cudaPdS_i
.p2align 4, 0x90
.type _Z24__device_stub__scan_cudaPdS_i,@function
_Z24__device_stub__scan_cudaPdS_i: # @_Z24__device_stub__scan_cudaPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9scan_cudaPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__scan_cudaPdS_i, .Lfunc_end0-_Z24__device_stub__scan_cudaPdS_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__add_cudaPdS_i # -- Begin function _Z23__device_stub__add_cudaPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__add_cudaPdS_i,@function
_Z23__device_stub__add_cudaPdS_i: # @_Z23__device_stub__add_cudaPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8add_cudaPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__add_cudaPdS_i, .Lfunc_end1-_Z23__device_stub__add_cudaPdS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $320000000, %edi # imm = 0x1312D000
callq malloc
movq %rax, %rbx
movl $312504, %edi # imm = 0x4C4B8
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq $40000000, %rax # imm = 0x2625A00
jne .LBB2_1
# %bb.2:
movabsq $4294968320, %r15 # imm = 0x100000400
leaq 24(%rsp), %rdi
movl $320000000, %esi # imm = 0x1312D000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $312504, %esi # imm = 0x4C4B8
callq hipMalloc
movq 24(%rsp), %rdi
movl $320000000, %edx # imm = 0x1312D000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 38039(%r15), %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $40000000, 12(%rsp) # imm = 0x2625A00
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9scan_cudaPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 16(%rsp), %rsi
movl $312504, %edx # imm = 0x4C4B8
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq $0, (%r14)
movl $1, %eax
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
addsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $39063, %rax # imm = 0x9897
jne .LBB2_5
# %bb.6:
movq 16(%rsp), %rdi
movl $312504, %edx # imm = 0x4C4B8
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $40000000, 12(%rsp) # imm = 0x2625A00
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8add_cudaPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 24(%rsp), %rsi
movl $320000000, %edx # imm = 0x1312D000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movsd 319999992(%rbx), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movl $39999999, %esi # imm = 0x26259FF
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9scan_cudaPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8add_cudaPdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9scan_cudaPdS_i,@object # @_Z9scan_cudaPdS_i
.section .rodata,"a",@progbits
.globl _Z9scan_cudaPdS_i
.p2align 3, 0x0
_Z9scan_cudaPdS_i:
.quad _Z24__device_stub__scan_cudaPdS_i
.size _Z9scan_cudaPdS_i, 8
.type _Z8add_cudaPdS_i,@object # @_Z8add_cudaPdS_i
.globl _Z8add_cudaPdS_i
.p2align 3, 0x0
_Z8add_cudaPdS_i:
.quad _Z23__device_stub__add_cudaPdS_i
.size _Z8add_cudaPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\na[%d] = %f\n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9scan_cudaPdS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8add_cudaPdS_i"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__scan_cudaPdS_i
.addrsig_sym _Z23__device_stub__add_cudaPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9scan_cudaPdS_i
.addrsig_sym _Z8add_cudaPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void hello_cuda()
{
printf("Hello World from CUDA!\n");
}
/*
int main()
{
int nx = 16, ny = 4;
//Limit for block size x <= 65536, y <= 2^32-1, z <= 65536
dim3 block(8, 2); //Number of Dimension 3 blocks/threads within each grid
//Limit for grid size x <= 1024, y <= 1024, z <= 64
//AND
//Limit for grid size x * y * z <= 1024
dim3 grid(nx / block.x, ny / block.y); //Number of Dimension 3 grids on the GPU
hello_cuda <<<grid, block>>>();
cudaDeviceSynchronize(); //Call above is async without this function call!
cudaDeviceReset();
return 0;
}
*/ | code for sm_80
Function : _Z10hello_cudav
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void hello_cuda()
{
printf("Hello World from CUDA!\n");
}
/*
int main()
{
int nx = 16, ny = 4;
//Limit for block size x <= 65536, y <= 2^32-1, z <= 65536
dim3 block(8, 2); //Number of Dimension 3 blocks/threads within each grid
//Limit for grid size x <= 1024, y <= 1024, z <= 64
//AND
//Limit for grid size x * y * z <= 1024
dim3 grid(nx / block.x, ny / block.y); //Number of Dimension 3 grids on the GPU
hello_cuda <<<grid, block>>>();
cudaDeviceSynchronize(); //Call above is async without this function call!
cudaDeviceReset();
return 0;
}
*/ | .file "tmpxft_00073497_00000000-6_1.Hello_World.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10hello_cudavv
.type _Z29__device_stub__Z10hello_cudavv, @function
_Z29__device_stub__Z10hello_cudavv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10hello_cudav(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z29__device_stub__Z10hello_cudavv, .-_Z29__device_stub__Z10hello_cudavv
.globl _Z10hello_cudav
.type _Z10hello_cudav, @function
_Z10hello_cudav:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10hello_cudavv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10hello_cudav, .-_Z10hello_cudav
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10hello_cudav"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hello_cudav(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void hello_cuda()
{
printf("Hello World from CUDA!\n");
}
/*
int main()
{
int nx = 16, ny = 4;
//Limit for block size x <= 65536, y <= 2^32-1, z <= 65536
dim3 block(8, 2); //Number of Dimension 3 blocks/threads within each grid
//Limit for grid size x <= 1024, y <= 1024, z <= 64
//AND
//Limit for grid size x * y * z <= 1024
dim3 grid(nx / block.x, ny / block.y); //Number of Dimension 3 grids on the GPU
hello_cuda <<<grid, block>>>();
cudaDeviceSynchronize(); //Call above is async without this function call!
cudaDeviceReset();
return 0;
}
*/ | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void hello_cuda()
{
printf("Hello World from CUDA!\n");
}
/*
int main()
{
int nx = 16, ny = 4;
//Limit for block size x <= 65536, y <= 2^32-1, z <= 65536
dim3 block(8, 2); //Number of Dimension 3 blocks/threads within each grid
//Limit for grid size x <= 1024, y <= 1024, z <= 64
//AND
//Limit for grid size x * y * z <= 1024
dim3 grid(nx / block.x, ny / block.y); //Number of Dimension 3 grids on the GPU
hello_cuda <<<grid, block>>>();
cudaDeviceSynchronize(); //Call above is async without this function call!
cudaDeviceReset();
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void hello_cuda()
{
printf("Hello World from CUDA!\n");
}
/*
int main()
{
int nx = 16, ny = 4;
//Limit for block size x <= 65536, y <= 2^32-1, z <= 65536
dim3 block(8, 2); //Number of Dimension 3 blocks/threads within each grid
//Limit for grid size x <= 1024, y <= 1024, z <= 64
//AND
//Limit for grid size x * y * z <= 1024
dim3 grid(nx / block.x, ny / block.y); //Number of Dimension 3 grids on the GPU
hello_cuda <<<grid, block>>>();
cudaDeviceSynchronize(); //Call above is async without this function call!
cudaDeviceReset();
return 0;
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10hello_cudav
.globl _Z10hello_cudav
.p2align 8
.type _Z10hello_cudav,@function
_Z10hello_cudav:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 24
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10hello_cudav
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10hello_cudav, .Lfunc_end0-_Z10hello_cudav
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from CUDA!\n"
.size .str, 24
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10hello_cudav
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10hello_cudav.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void hello_cuda()
{
printf("Hello World from CUDA!\n");
}
/*
int main()
{
int nx = 16, ny = 4;
//Limit for block size x <= 65536, y <= 2^32-1, z <= 65536
dim3 block(8, 2); //Number of Dimension 3 blocks/threads within each grid
//Limit for grid size x <= 1024, y <= 1024, z <= 64
//AND
//Limit for grid size x * y * z <= 1024
dim3 grid(nx / block.x, ny / block.y); //Number of Dimension 3 grids on the GPU
hello_cuda <<<grid, block>>>();
cudaDeviceSynchronize(); //Call above is async without this function call!
cudaDeviceReset();
return 0;
}
*/ | .text
.file "1.Hello_World.hip"
.globl _Z25__device_stub__hello_cudav # -- Begin function _Z25__device_stub__hello_cudav
.p2align 4, 0x90
.type _Z25__device_stub__hello_cudav,@function
_Z25__device_stub__hello_cudav: # @_Z25__device_stub__hello_cudav
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__hello_cudav, .Lfunc_end0-_Z25__device_stub__hello_cudav
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10hello_cudav, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10hello_cudav,@object # @_Z10hello_cudav
.section .rodata,"a",@progbits
.globl _Z10hello_cudav
.p2align 3, 0x0
_Z10hello_cudav:
.quad _Z25__device_stub__hello_cudav
.size _Z10hello_cudav, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10hello_cudav"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__hello_cudav
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10hello_cudav
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10hello_cudav
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10hello_cudav
.globl _Z10hello_cudav
.p2align 8
.type _Z10hello_cudav,@function
_Z10hello_cudav:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 24
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10hello_cudav
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10hello_cudav, .Lfunc_end0-_Z10hello_cudav
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from CUDA!\n"
.size .str, 24
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10hello_cudav
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10hello_cudav.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00073497_00000000-6_1.Hello_World.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10hello_cudavv
.type _Z29__device_stub__Z10hello_cudavv, @function
_Z29__device_stub__Z10hello_cudavv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10hello_cudav(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z29__device_stub__Z10hello_cudavv, .-_Z29__device_stub__Z10hello_cudavv
.globl _Z10hello_cudav
.type _Z10hello_cudav, @function
_Z10hello_cudav:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10hello_cudavv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10hello_cudav, .-_Z10hello_cudav
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10hello_cudav"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hello_cudav(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1.Hello_World.hip"
.globl _Z25__device_stub__hello_cudav # -- Begin function _Z25__device_stub__hello_cudav
.p2align 4, 0x90
.type _Z25__device_stub__hello_cudav,@function
_Z25__device_stub__hello_cudav: # @_Z25__device_stub__hello_cudav
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__hello_cudav, .Lfunc_end0-_Z25__device_stub__hello_cudav
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10hello_cudav, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10hello_cudav,@object # @_Z10hello_cudav
.section .rodata,"a",@progbits
.globl _Z10hello_cudav
.p2align 3, 0x0
_Z10hello_cudav:
.quad _Z25__device_stub__hello_cudav
.size _Z10hello_cudav, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10hello_cudav"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__hello_cudav
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10hello_cudav
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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