system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void BackwardCrossEntropy(float *output, float *labels, int nColsOutput, float *dOutput)
{
int col = blockIdx.x;
dOutput[col] = (labels[col] / output[col] - (1 - labels[col]) /
(1 - output[col])) * -1;
} | code for sm_80
Function : _Z20BackwardCrossEntropyPfS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x001fcc00078e0207 */
/*0050*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fca00078e0207 */
/*0070*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ee2000c1e1900 */
/*0080*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x004e300000001000 */
/*0090*/ FCHK P0, R2, R5 ; /* 0x0000000502007302 */
/* 0x008e620000000000 */
/*00a0*/ FFMA R3, -R5, R8, 1 ; /* 0x3f80000005037423 */
/* 0x001fc80000000108 */
/*00b0*/ FFMA R3, R8, R3, R8 ; /* 0x0000000308037223 */
/* 0x000fc80000000008 */
/*00c0*/ FFMA R8, R2, R3, RZ ; /* 0x0000000302087223 */
/* 0x000fc800000000ff */
/*00d0*/ FFMA R9, -R5, R8, R2 ; /* 0x0000000805097223 */
/* 0x000fc80000000102 */
/*00e0*/ FFMA R3, R3, R9, R8 ; /* 0x0000000903037223 */
/* 0x000fe20000000008 */
/*00f0*/ @!P0 BRA 0x130 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0100*/ MOV R4, 0x120 ; /* 0x0000012000047802 */
/* 0x000fe40000000f00 */
/*0110*/ CALL.REL.NOINC 0x260 ; /* 0x0000014000007944 */
/* 0x000fea0003c00000 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*0130*/ FADD R5, -R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe40000000100 */
/*0140*/ FADD R2, -R2, 1 ; /* 0x3f80000002027421 */
/* 0x000fe40000000100 */
/*0150*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e300000001000 */
/*0160*/ FCHK P0, R2, R5 ; /* 0x0000000502007302 */
/* 0x000e620000000000 */
/*0170*/ FFMA R7, -R5, R4, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000104 */
/*0180*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fc80000000004 */
/*0190*/ FFMA R4, R2, R7, RZ ; /* 0x0000000702047223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R6, -R5, R4, R2 ; /* 0x0000000405067223 */
/* 0x000fc80000000102 */
/*01b0*/ FFMA R4, R7, R6, R4 ; /* 0x0000000607047223 */
/* 0x000fe20000000004 */
/*01c0*/ @!P0 BRA 0x200 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*01d0*/ MOV R4, 0x1f0 ; /* 0x000001f000047802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x260 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0008 */
/*0200*/ FADD R3, -R4, R3 ; /* 0x0000000304037221 */
/* 0x000fe40000000100 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0220*/ FADD R5, -R3, -RZ ; /* 0x800000ff03057221 */
/* 0x000fe40000000100 */
/*0230*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0207 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe40000011605 */
/*0270*/ SHF.R.U32.HI R6, RZ, 0x17, R2.reuse ; /* 0x00000017ff067819 */
/* 0x100fe40000011602 */
/*0280*/ LOP3.LUT R14, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070e7812 */
/* 0x000fe200078ec0ff */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*02a0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*02c0*/ IADD3 R10, R14, -0x1, RZ ; /* 0xffffffff0e0a7810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R9, R12, -0x1, RZ ; /* 0xffffffff0c097810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*02f0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*0300*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0310*/ @!P0 BRA 0x490 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f1c200 */
/*0330*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0340*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0350*/ @P0 BRA 0x870 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0370*/ @!P0 BRA 0x850 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P2, PT, |R2|.reuse, +INF , PT ; /* 0x7f8000000200780b */
/* 0x040fe40003f5d200 */
/*0390*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*03a0*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fd60003f1d200 */
/*03b0*/ @!P1 BRA !P2, 0x850 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*03c0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*03d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03e0*/ @P1 BRA 0x830 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0400*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0410*/ @P0 BRA 0x800 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0430*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0440*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0460*/ @!P0 FFMA R6, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002068823 */
/* 0x000fe400000000ff */
/*0470*/ @!P1 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005079823 */
/* 0x000fe200000000ff */
/*0480*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LEA R10, R14, 0xc0800000, 0x17 ; /* 0xc08000000e0a7811 */
/* 0x000fca00078eb8ff */
/*04a0*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*04b0*/ IADD3 R7, R12, -0x7f, RZ ; /* 0xffffff810c077810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ MUFU.RCP R9, R10 ; /* 0x0000000a00097308 */
/* 0x000e220000001000 */
/*04d0*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fe40000010100 */
/*04e0*/ IMAD R6, R7, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x000fe400078e0206 */
/*04f0*/ FFMA R12, R9, R11, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000b */
/*0500*/ FFMA R13, R9, R12, R9 ; /* 0x0000000c090d7223 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R9, R6, R13, RZ ; /* 0x0000000d06097223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R12, R11, R9, R6 ; /* 0x000000090b0c7223 */
/* 0x000fc80000000006 */
/*0530*/ FFMA R12, R13, R12, R9 ; /* 0x0000000c0d0c7223 */
/* 0x000fe20000000009 */
/*0540*/ IADD3 R9, R7, 0x7f, -R14 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80e */
/*0550*/ FFMA R11, R11, R12, R6 ; /* 0x0000000c0b0b7223 */
/* 0x000fe40000000006 */
/*0560*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fe400078e0208 */
/*0570*/ FFMA R6, R13, R11, R12 ; /* 0x0000000b0d067223 */
/* 0x000fca000000000c */
/*0580*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*0590*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*05a0*/ IMAD.IADD R14, R7, 0x1, R9 ; /* 0x00000001070e7824 */
/* 0x000fca00078e0209 */
/*05b0*/ IADD3 R7, R14, -0x1, RZ ; /* 0xffffffff0e077810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*05d0*/ @!P0 BRA 0x7e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*05f0*/ @P0 BRA 0x7b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0610*/ @P0 BRA 0x880 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0630*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0640*/ @!P0 BRA 0x880 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0650*/ FFMA.RZ R7, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000c00c */
/*0660*/ IADD3 R10, R14.reuse, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x040fe20007ffe0ff */
/*0670*/ FFMA.RM R8, R13, R11.reuse, R12.reuse ; /* 0x0000000b0d087223 */
/* 0x180fe2000000400c */
/*0680*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0690*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*06a0*/ FFMA.RP R7, R13, R11, R12 ; /* 0x0000000b0d077223 */
/* 0x000fe2000000800c */
/*06b0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*06c0*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0e */
/*06d0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*06f0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0700*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0710*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0720*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0740*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0750*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0760*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0770*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fca00078e0207 */
/*0790*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x880 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*07c0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x880 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe200078e0206 */
/*07f0*/ BRA 0x880 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*0810*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0820*/ BRA 0x880 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*0840*/ BRA 0x880 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0850*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0860*/ BRA 0x880 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0870*/ FADD.FTZ R6, R2, R5 ; /* 0x0000000502067221 */
/* 0x000fc80000010000 */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*0890*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*08a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*08b0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff74006007950 */
/* 0x000fea0003c3ffff */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void BackwardCrossEntropy(float *output, float *labels, int nColsOutput, float *dOutput)
{
int col = blockIdx.x;
dOutput[col] = (labels[col] / output[col] - (1 - labels[col]) /
(1 - output[col])) * -1;
} | .file "tmpxft_000eb899_00000000-6_BackwardCrossEntropy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_
.type _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_, @function
_Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20BackwardCrossEntropyPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_, .-_Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_
.globl _Z20BackwardCrossEntropyPfS_iS_
.type _Z20BackwardCrossEntropyPfS_iS_, @function
_Z20BackwardCrossEntropyPfS_iS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20BackwardCrossEntropyPfS_iS_, .-_Z20BackwardCrossEntropyPfS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20BackwardCrossEntropyPfS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20BackwardCrossEntropyPfS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void BackwardCrossEntropy(float *output, float *labels, int nColsOutput, float *dOutput)
{
int col = blockIdx.x;
dOutput[col] = (labels[col] / output[col] - (1 - labels[col]) /
(1 - output[col])) * -1;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BackwardCrossEntropy(float *output, float *labels, int nColsOutput, float *dOutput)
{
int col = blockIdx.x;
dOutput[col] = (labels[col] / output[col] - (1 - labels[col]) /
(1 - output[col])) * -1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BackwardCrossEntropy(float *output, float *labels, int nColsOutput, float *dOutput)
{
int col = blockIdx.x;
dOutput[col] = (labels[col] / output[col] - (1 - labels[col]) /
(1 - output[col])) * -1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20BackwardCrossEntropyPfS_iS_
.globl _Z20BackwardCrossEntropyPfS_iS_
.p2align 8
.type _Z20BackwardCrossEntropyPfS_iS_,@function
_Z20BackwardCrossEntropyPfS_iS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s6, s2
s_addc_u32 s1, s7, s3
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_load_b32 s1, s[0:1], 0x0
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v0, 1.0, s1
v_sub_f32_e64 v1, 1.0, s4
v_div_scale_f32 v2, null, s4, s4, s1
v_div_scale_f32 v8, vcc_lo, s1, s4, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v3, null, v1, v1, v0
v_rcp_f32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v4, 1.0
v_fma_f32 v7, -v3, v5, 1.0
v_fmac_f32_e32 v4, v6, v4
v_div_scale_f32 v6, s0, v0, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v5, v7, v5
v_mul_f32_e32 v7, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v6, v5
v_fma_f32 v10, -v2, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v3, v9, v6
v_fmac_f32_e32 v7, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v7, v8
v_div_fmas_f32 v2, v2, v4, v7
s_mov_b32 vcc_lo, s0
s_add_u32 s0, s8, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v2, s4, s1
v_fmac_f32_e32 v9, v11, v5
s_addc_u32 s1, s9, s3
v_fma_f32 v3, -v3, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v5, v9
v_div_fixup_f32 v0, v3, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, 0 :: v_dual_sub_f32 v0, v2, v0
v_xor_b32_e32 v0, 0x80000000, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20BackwardCrossEntropyPfS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20BackwardCrossEntropyPfS_iS_, .Lfunc_end0-_Z20BackwardCrossEntropyPfS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20BackwardCrossEntropyPfS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20BackwardCrossEntropyPfS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BackwardCrossEntropy(float *output, float *labels, int nColsOutput, float *dOutput)
{
int col = blockIdx.x;
dOutput[col] = (labels[col] / output[col] - (1 - labels[col]) /
(1 - output[col])) * -1;
} | .text
.file "BackwardCrossEntropy.hip"
.globl _Z35__device_stub__BackwardCrossEntropyPfS_iS_ # -- Begin function _Z35__device_stub__BackwardCrossEntropyPfS_iS_
.p2align 4, 0x90
.type _Z35__device_stub__BackwardCrossEntropyPfS_iS_,@function
_Z35__device_stub__BackwardCrossEntropyPfS_iS_: # @_Z35__device_stub__BackwardCrossEntropyPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20BackwardCrossEntropyPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__BackwardCrossEntropyPfS_iS_, .Lfunc_end0-_Z35__device_stub__BackwardCrossEntropyPfS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20BackwardCrossEntropyPfS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20BackwardCrossEntropyPfS_iS_,@object # @_Z20BackwardCrossEntropyPfS_iS_
.section .rodata,"a",@progbits
.globl _Z20BackwardCrossEntropyPfS_iS_
.p2align 3, 0x0
_Z20BackwardCrossEntropyPfS_iS_:
.quad _Z35__device_stub__BackwardCrossEntropyPfS_iS_
.size _Z20BackwardCrossEntropyPfS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20BackwardCrossEntropyPfS_iS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__BackwardCrossEntropyPfS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20BackwardCrossEntropyPfS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20BackwardCrossEntropyPfS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x001fcc00078e0207 */
/*0050*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fca00078e0207 */
/*0070*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ee2000c1e1900 */
/*0080*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x004e300000001000 */
/*0090*/ FCHK P0, R2, R5 ; /* 0x0000000502007302 */
/* 0x008e620000000000 */
/*00a0*/ FFMA R3, -R5, R8, 1 ; /* 0x3f80000005037423 */
/* 0x001fc80000000108 */
/*00b0*/ FFMA R3, R8, R3, R8 ; /* 0x0000000308037223 */
/* 0x000fc80000000008 */
/*00c0*/ FFMA R8, R2, R3, RZ ; /* 0x0000000302087223 */
/* 0x000fc800000000ff */
/*00d0*/ FFMA R9, -R5, R8, R2 ; /* 0x0000000805097223 */
/* 0x000fc80000000102 */
/*00e0*/ FFMA R3, R3, R9, R8 ; /* 0x0000000903037223 */
/* 0x000fe20000000008 */
/*00f0*/ @!P0 BRA 0x130 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0100*/ MOV R4, 0x120 ; /* 0x0000012000047802 */
/* 0x000fe40000000f00 */
/*0110*/ CALL.REL.NOINC 0x260 ; /* 0x0000014000007944 */
/* 0x000fea0003c00000 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*0130*/ FADD R5, -R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe40000000100 */
/*0140*/ FADD R2, -R2, 1 ; /* 0x3f80000002027421 */
/* 0x000fe40000000100 */
/*0150*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e300000001000 */
/*0160*/ FCHK P0, R2, R5 ; /* 0x0000000502007302 */
/* 0x000e620000000000 */
/*0170*/ FFMA R7, -R5, R4, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000104 */
/*0180*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fc80000000004 */
/*0190*/ FFMA R4, R2, R7, RZ ; /* 0x0000000702047223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R6, -R5, R4, R2 ; /* 0x0000000405067223 */
/* 0x000fc80000000102 */
/*01b0*/ FFMA R4, R7, R6, R4 ; /* 0x0000000607047223 */
/* 0x000fe20000000004 */
/*01c0*/ @!P0 BRA 0x200 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*01d0*/ MOV R4, 0x1f0 ; /* 0x000001f000047802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x260 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0008 */
/*0200*/ FADD R3, -R4, R3 ; /* 0x0000000304037221 */
/* 0x000fe40000000100 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0220*/ FADD R5, -R3, -RZ ; /* 0x800000ff03057221 */
/* 0x000fe40000000100 */
/*0230*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0207 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe40000011605 */
/*0270*/ SHF.R.U32.HI R6, RZ, 0x17, R2.reuse ; /* 0x00000017ff067819 */
/* 0x100fe40000011602 */
/*0280*/ LOP3.LUT R14, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070e7812 */
/* 0x000fe200078ec0ff */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*02a0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*02c0*/ IADD3 R10, R14, -0x1, RZ ; /* 0xffffffff0e0a7810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R9, R12, -0x1, RZ ; /* 0xffffffff0c097810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*02f0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*0300*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0310*/ @!P0 BRA 0x490 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f1c200 */
/*0330*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0340*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0350*/ @P0 BRA 0x870 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0370*/ @!P0 BRA 0x850 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P2, PT, |R2|.reuse, +INF , PT ; /* 0x7f8000000200780b */
/* 0x040fe40003f5d200 */
/*0390*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*03a0*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fd60003f1d200 */
/*03b0*/ @!P1 BRA !P2, 0x850 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*03c0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*03d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03e0*/ @P1 BRA 0x830 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0400*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0410*/ @P0 BRA 0x800 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0430*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0440*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0460*/ @!P0 FFMA R6, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002068823 */
/* 0x000fe400000000ff */
/*0470*/ @!P1 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005079823 */
/* 0x000fe200000000ff */
/*0480*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LEA R10, R14, 0xc0800000, 0x17 ; /* 0xc08000000e0a7811 */
/* 0x000fca00078eb8ff */
/*04a0*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*04b0*/ IADD3 R7, R12, -0x7f, RZ ; /* 0xffffff810c077810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ MUFU.RCP R9, R10 ; /* 0x0000000a00097308 */
/* 0x000e220000001000 */
/*04d0*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fe40000010100 */
/*04e0*/ IMAD R6, R7, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x000fe400078e0206 */
/*04f0*/ FFMA R12, R9, R11, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000b */
/*0500*/ FFMA R13, R9, R12, R9 ; /* 0x0000000c090d7223 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R9, R6, R13, RZ ; /* 0x0000000d06097223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R12, R11, R9, R6 ; /* 0x000000090b0c7223 */
/* 0x000fc80000000006 */
/*0530*/ FFMA R12, R13, R12, R9 ; /* 0x0000000c0d0c7223 */
/* 0x000fe20000000009 */
/*0540*/ IADD3 R9, R7, 0x7f, -R14 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80e */
/*0550*/ FFMA R11, R11, R12, R6 ; /* 0x0000000c0b0b7223 */
/* 0x000fe40000000006 */
/*0560*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fe400078e0208 */
/*0570*/ FFMA R6, R13, R11, R12 ; /* 0x0000000b0d067223 */
/* 0x000fca000000000c */
/*0580*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*0590*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*05a0*/ IMAD.IADD R14, R7, 0x1, R9 ; /* 0x00000001070e7824 */
/* 0x000fca00078e0209 */
/*05b0*/ IADD3 R7, R14, -0x1, RZ ; /* 0xffffffff0e077810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*05d0*/ @!P0 BRA 0x7e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*05f0*/ @P0 BRA 0x7b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0610*/ @P0 BRA 0x880 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0630*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0640*/ @!P0 BRA 0x880 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0650*/ FFMA.RZ R7, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000c00c */
/*0660*/ IADD3 R10, R14.reuse, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x040fe20007ffe0ff */
/*0670*/ FFMA.RM R8, R13, R11.reuse, R12.reuse ; /* 0x0000000b0d087223 */
/* 0x180fe2000000400c */
/*0680*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0690*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*06a0*/ FFMA.RP R7, R13, R11, R12 ; /* 0x0000000b0d077223 */
/* 0x000fe2000000800c */
/*06b0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*06c0*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0e */
/*06d0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*06f0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0700*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0710*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0720*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0740*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0750*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0760*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0770*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fca00078e0207 */
/*0790*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x880 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*07c0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x880 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe200078e0206 */
/*07f0*/ BRA 0x880 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*0810*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0820*/ BRA 0x880 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*0840*/ BRA 0x880 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0850*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0860*/ BRA 0x880 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0870*/ FADD.FTZ R6, R2, R5 ; /* 0x0000000502067221 */
/* 0x000fc80000010000 */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*0890*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*08a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*08b0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff74006007950 */
/* 0x000fea0003c3ffff */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20BackwardCrossEntropyPfS_iS_
.globl _Z20BackwardCrossEntropyPfS_iS_
.p2align 8
.type _Z20BackwardCrossEntropyPfS_iS_,@function
_Z20BackwardCrossEntropyPfS_iS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s6, s2
s_addc_u32 s1, s7, s3
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_load_b32 s1, s[0:1], 0x0
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v0, 1.0, s1
v_sub_f32_e64 v1, 1.0, s4
v_div_scale_f32 v2, null, s4, s4, s1
v_div_scale_f32 v8, vcc_lo, s1, s4, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v3, null, v1, v1, v0
v_rcp_f32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v4, 1.0
v_fma_f32 v7, -v3, v5, 1.0
v_fmac_f32_e32 v4, v6, v4
v_div_scale_f32 v6, s0, v0, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v5, v7, v5
v_mul_f32_e32 v7, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v6, v5
v_fma_f32 v10, -v2, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v3, v9, v6
v_fmac_f32_e32 v7, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v7, v8
v_div_fmas_f32 v2, v2, v4, v7
s_mov_b32 vcc_lo, s0
s_add_u32 s0, s8, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v2, s4, s1
v_fmac_f32_e32 v9, v11, v5
s_addc_u32 s1, s9, s3
v_fma_f32 v3, -v3, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v5, v9
v_div_fixup_f32 v0, v3, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, 0 :: v_dual_sub_f32 v0, v2, v0
v_xor_b32_e32 v0, 0x80000000, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20BackwardCrossEntropyPfS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20BackwardCrossEntropyPfS_iS_, .Lfunc_end0-_Z20BackwardCrossEntropyPfS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20BackwardCrossEntropyPfS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20BackwardCrossEntropyPfS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eb899_00000000-6_BackwardCrossEntropy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_
.type _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_, @function
_Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20BackwardCrossEntropyPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_, .-_Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_
.globl _Z20BackwardCrossEntropyPfS_iS_
.type _Z20BackwardCrossEntropyPfS_iS_, @function
_Z20BackwardCrossEntropyPfS_iS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20BackwardCrossEntropyPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20BackwardCrossEntropyPfS_iS_, .-_Z20BackwardCrossEntropyPfS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20BackwardCrossEntropyPfS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20BackwardCrossEntropyPfS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BackwardCrossEntropy.hip"
.globl _Z35__device_stub__BackwardCrossEntropyPfS_iS_ # -- Begin function _Z35__device_stub__BackwardCrossEntropyPfS_iS_
.p2align 4, 0x90
.type _Z35__device_stub__BackwardCrossEntropyPfS_iS_,@function
_Z35__device_stub__BackwardCrossEntropyPfS_iS_: # @_Z35__device_stub__BackwardCrossEntropyPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20BackwardCrossEntropyPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__BackwardCrossEntropyPfS_iS_, .Lfunc_end0-_Z35__device_stub__BackwardCrossEntropyPfS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20BackwardCrossEntropyPfS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20BackwardCrossEntropyPfS_iS_,@object # @_Z20BackwardCrossEntropyPfS_iS_
.section .rodata,"a",@progbits
.globl _Z20BackwardCrossEntropyPfS_iS_
.p2align 3, 0x0
_Z20BackwardCrossEntropyPfS_iS_:
.quad _Z35__device_stub__BackwardCrossEntropyPfS_iS_
.size _Z20BackwardCrossEntropyPfS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20BackwardCrossEntropyPfS_iS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__BackwardCrossEntropyPfS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20BackwardCrossEntropyPfS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* calculate how much memory can be really allocated (which is not the same as free)
https://stackoverflow.com/a/8923966/9201239
*/
#include <stdio.h>
#include <cuda.h>
#include <unistd.h>
const size_t Mb = 1<<20; // Assuming a 1Mb page size here
int main() {
size_t total;
size_t avail;
cudaError_t cuda_status = cudaMemGetInfo(&avail, &total);
if ( cudaSuccess != cuda_status ) {
printf("Error: cudaMemGetInfo fails, %s \n", cudaGetErrorString(cuda_status) );
exit(EXIT_FAILURE);
}
printf("free: %.f, total %.f\n", (double)avail/Mb, (double)total/Mb);
int *buf_d = 0;
size_t nwords = total / sizeof(int);
size_t words_per_Mb = Mb / sizeof(int);
while (cudaMalloc((void**)&buf_d, nwords * sizeof(int)) == cudaErrorMemoryAllocation) {
cudaFree(buf_d);
nwords -= words_per_Mb;
if (nwords < words_per_Mb) {
// signal no free memory
break;
}
}
cudaFree(buf_d);
printf("can allocate: %.fMB\n", (double)nwords/words_per_Mb);
//sleep(1000); /* keep consuming RAM */
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* calculate how much memory can be really allocated (which is not the same as free)
https://stackoverflow.com/a/8923966/9201239
*/
#include <stdio.h>
#include <cuda.h>
#include <unistd.h>
const size_t Mb = 1<<20; // Assuming a 1Mb page size here
int main() {
size_t total;
size_t avail;
cudaError_t cuda_status = cudaMemGetInfo(&avail, &total);
if ( cudaSuccess != cuda_status ) {
printf("Error: cudaMemGetInfo fails, %s \n", cudaGetErrorString(cuda_status) );
exit(EXIT_FAILURE);
}
printf("free: %.f, total %.f\n", (double)avail/Mb, (double)total/Mb);
int *buf_d = 0;
size_t nwords = total / sizeof(int);
size_t words_per_Mb = Mb / sizeof(int);
while (cudaMalloc((void**)&buf_d, nwords * sizeof(int)) == cudaErrorMemoryAllocation) {
cudaFree(buf_d);
nwords -= words_per_Mb;
if (nwords < words_per_Mb) {
// signal no free memory
break;
}
}
cudaFree(buf_d);
printf("can allocate: %.fMB\n", (double)nwords/words_per_Mb);
//sleep(1000); /* keep consuming RAM */
return 0;
} | .file "tmpxft_001a8728_00000000-6_max_real_avail.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: cudaMemGetInfo fails, %s \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "free: %.f, total %.f\n"
.LC4:
.string "can allocate: %.fMB\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq 8(%rsp), %rdi
call cudaMemGetInfo@PLT
testl %eax, %eax
jne .L16
movq (%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
.L6:
mulsd .LC1(%rip), %xmm1
movq 8(%rsp), %rax
testq %rax, %rax
js .L7
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L8:
mulsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq $0, 16(%rsp)
movq (%rsp), %rbx
shrq $2, %rbx
leaq 16(%rsp), %rbp
.L9:
leaq 0(,%rbx,4), %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
cmpl $2, %eax
jne .L10
movq 16(%rsp), %rdi
call cudaFree@PLT
subq $262144, %rbx
cmpq $262143, %rbx
ja .L9
.L10:
movq 16(%rsp), %rdi
call cudaFree@PLT
testq %rbx, %rbx
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L13:
mulsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
addsd %xmm1, %xmm1
jmp .L6
.L7:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L8
.L12:
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1051721728
.align 8
.LC3:
.long 0
.long 1053818880
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* calculate how much memory can be really allocated (which is not the same as free)
https://stackoverflow.com/a/8923966/9201239
*/
#include <stdio.h>
#include <cuda.h>
#include <unistd.h>
const size_t Mb = 1<<20; // Assuming a 1Mb page size here
int main() {
size_t total;
size_t avail;
cudaError_t cuda_status = cudaMemGetInfo(&avail, &total);
if ( cudaSuccess != cuda_status ) {
printf("Error: cudaMemGetInfo fails, %s \n", cudaGetErrorString(cuda_status) );
exit(EXIT_FAILURE);
}
printf("free: %.f, total %.f\n", (double)avail/Mb, (double)total/Mb);
int *buf_d = 0;
size_t nwords = total / sizeof(int);
size_t words_per_Mb = Mb / sizeof(int);
while (cudaMalloc((void**)&buf_d, nwords * sizeof(int)) == cudaErrorMemoryAllocation) {
cudaFree(buf_d);
nwords -= words_per_Mb;
if (nwords < words_per_Mb) {
// signal no free memory
break;
}
}
cudaFree(buf_d);
printf("can allocate: %.fMB\n", (double)nwords/words_per_Mb);
//sleep(1000); /* keep consuming RAM */
return 0;
} | /* calculate how much memory can be really allocated (which is not the same as free)
https://stackoverflow.com/a/8923966/9201239
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
const size_t Mb = 1<<20; // Assuming a 1Mb page size here
int main() {
size_t total;
size_t avail;
hipError_t cuda_status = hipMemGetInfo(&avail, &total);
if ( hipSuccess != cuda_status ) {
printf("Error: hipMemGetInfo fails, %s \n", hipGetErrorString(cuda_status) );
exit(EXIT_FAILURE);
}
printf("free: %.f, total %.f\n", (double)avail/Mb, (double)total/Mb);
int *buf_d = 0;
size_t nwords = total / sizeof(int);
size_t words_per_Mb = Mb / sizeof(int);
while (hipMalloc((void**)&buf_d, nwords * sizeof(int)) == hipErrorOutOfMemory) {
hipFree(buf_d);
nwords -= words_per_Mb;
if (nwords < words_per_Mb) {
// signal no free memory
break;
}
}
hipFree(buf_d);
printf("can allocate: %.fMB\n", (double)nwords/words_per_Mb);
//sleep(1000); /* keep consuming RAM */
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* calculate how much memory can be really allocated (which is not the same as free)
https://stackoverflow.com/a/8923966/9201239
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
const size_t Mb = 1<<20; // Assuming a 1Mb page size here
int main() {
size_t total;
size_t avail;
hipError_t cuda_status = hipMemGetInfo(&avail, &total);
if ( hipSuccess != cuda_status ) {
printf("Error: hipMemGetInfo fails, %s \n", hipGetErrorString(cuda_status) );
exit(EXIT_FAILURE);
}
printf("free: %.f, total %.f\n", (double)avail/Mb, (double)total/Mb);
int *buf_d = 0;
size_t nwords = total / sizeof(int);
size_t words_per_Mb = Mb / sizeof(int);
while (hipMalloc((void**)&buf_d, nwords * sizeof(int)) == hipErrorOutOfMemory) {
hipFree(buf_d);
nwords -= words_per_Mb;
if (nwords < words_per_Mb) {
// signal no free memory
break;
}
}
hipFree(buf_d);
printf("can allocate: %.fMB\n", (double)nwords/words_per_Mb);
//sleep(1000); /* keep consuming RAM */
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* calculate how much memory can be really allocated (which is not the same as free)
https://stackoverflow.com/a/8923966/9201239
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
const size_t Mb = 1<<20; // Assuming a 1Mb page size here
int main() {
size_t total;
size_t avail;
hipError_t cuda_status = hipMemGetInfo(&avail, &total);
if ( hipSuccess != cuda_status ) {
printf("Error: hipMemGetInfo fails, %s \n", hipGetErrorString(cuda_status) );
exit(EXIT_FAILURE);
}
printf("free: %.f, total %.f\n", (double)avail/Mb, (double)total/Mb);
int *buf_d = 0;
size_t nwords = total / sizeof(int);
size_t words_per_Mb = Mb / sizeof(int);
while (hipMalloc((void**)&buf_d, nwords * sizeof(int)) == hipErrorOutOfMemory) {
hipFree(buf_d);
nwords -= words_per_Mb;
if (nwords < words_per_Mb) {
// signal no free memory
break;
}
}
hipFree(buf_d);
printf("can allocate: %.fMB\n", (double)nwords/words_per_Mb);
//sleep(1000); /* keep consuming RAM */
return 0;
} | .text
.file "max_real_avail.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3eb0000000000000 # double 9.5367431640625E-7
.LCPI0_3:
.quad 0x3ed0000000000000 # double 3.814697265625E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq hipMemGetInfo
testl %eax, %eax
jne .LBB0_5
# %bb.1:
movsd 24(%rsp), %xmm1 # xmm1 = mem[0],zero
movapd .LCPI0_0(%rip), %xmm2 # xmm2 = [1127219200,1160773632,0,0]
unpcklps %xmm2, %xmm1 # xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
movapd .LCPI0_1(%rip), %xmm3 # xmm3 = [4.503599627370496E+15,1.9342813113834067E+25]
subpd %xmm3, %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd .LCPI0_2(%rip), %xmm4 # xmm4 = mem[0],zero
mulsd %xmm4, %xmm0
movsd 16(%rsp), %xmm5 # xmm5 = mem[0],zero
unpcklps %xmm2, %xmm5 # xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
subpd %xmm3, %xmm5
movapd %xmm5, %xmm1
unpckhpd %xmm5, %xmm1 # xmm1 = xmm1[1],xmm5[1]
addsd %xmm5, %xmm1
mulsd %xmm4, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
movq $0, 8(%rsp)
movq 16(%rsp), %rbx
movq %rbx, %r15
shrq $2, %r15
andq $-4, %rbx
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
cmpl $2, %eax
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movq 8(%rsp), %rdi
callq hipFree
addq $-262144, %r15 # imm = 0xFFFC0000
addq $-1048576, %rbx # imm = 0xFFF00000
cmpq $262143, %r15 # imm = 0x3FFFF
ja .LBB0_2
.LBB0_4:
movq 8(%rsp), %rdi
callq hipFree
movq %r15, %xmm1
punpckldq .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_3(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 64
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: hipMemGetInfo fails, %s \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "free: %.f, total %.f\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "can allocate: %.fMB\n"
.size .L.str.2, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a8728_00000000-6_max_real_avail.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: cudaMemGetInfo fails, %s \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "free: %.f, total %.f\n"
.LC4:
.string "can allocate: %.fMB\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq 8(%rsp), %rdi
call cudaMemGetInfo@PLT
testl %eax, %eax
jne .L16
movq (%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
.L6:
mulsd .LC1(%rip), %xmm1
movq 8(%rsp), %rax
testq %rax, %rax
js .L7
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L8:
mulsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq $0, 16(%rsp)
movq (%rsp), %rbx
shrq $2, %rbx
leaq 16(%rsp), %rbp
.L9:
leaq 0(,%rbx,4), %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
cmpl $2, %eax
jne .L10
movq 16(%rsp), %rdi
call cudaFree@PLT
subq $262144, %rbx
cmpq $262143, %rbx
ja .L9
.L10:
movq 16(%rsp), %rdi
call cudaFree@PLT
testq %rbx, %rbx
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L13:
mulsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
addsd %xmm1, %xmm1
jmp .L6
.L7:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L8
.L12:
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1051721728
.align 8
.LC3:
.long 0
.long 1053818880
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "max_real_avail.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3eb0000000000000 # double 9.5367431640625E-7
.LCPI0_3:
.quad 0x3ed0000000000000 # double 3.814697265625E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq hipMemGetInfo
testl %eax, %eax
jne .LBB0_5
# %bb.1:
movsd 24(%rsp), %xmm1 # xmm1 = mem[0],zero
movapd .LCPI0_0(%rip), %xmm2 # xmm2 = [1127219200,1160773632,0,0]
unpcklps %xmm2, %xmm1 # xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
movapd .LCPI0_1(%rip), %xmm3 # xmm3 = [4.503599627370496E+15,1.9342813113834067E+25]
subpd %xmm3, %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd .LCPI0_2(%rip), %xmm4 # xmm4 = mem[0],zero
mulsd %xmm4, %xmm0
movsd 16(%rsp), %xmm5 # xmm5 = mem[0],zero
unpcklps %xmm2, %xmm5 # xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
subpd %xmm3, %xmm5
movapd %xmm5, %xmm1
unpckhpd %xmm5, %xmm1 # xmm1 = xmm1[1],xmm5[1]
addsd %xmm5, %xmm1
mulsd %xmm4, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
movq $0, 8(%rsp)
movq 16(%rsp), %rbx
movq %rbx, %r15
shrq $2, %r15
andq $-4, %rbx
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
cmpl $2, %eax
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movq 8(%rsp), %rdi
callq hipFree
addq $-262144, %r15 # imm = 0xFFFC0000
addq $-1048576, %rbx # imm = 0xFFF00000
cmpq $262143, %r15 # imm = 0x3FFFF
ja .LBB0_2
.LBB0_4:
movq 8(%rsp), %rdi
callq hipFree
movq %r15, %xmm1
punpckldq .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_3(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 64
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: hipMemGetInfo fails, %s \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "free: %.f, total %.f\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "can allocate: %.fMB\n"
.size .L.str.2, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "pgm.cuh"
#include <cstdio>
#include <cstdlib>
#include <cctype>
/*
Source for some of the parsing code:
http://ugurkoltuk.wordpress.com/2010/03/04/an-extreme-simple-pgm-io-api/
*/
void skipFileComments(FILE *fp);
float* loadPGM(const char *filename, int *width, int *height) {
printf("Loading image %s\n", filename);
FILE *pgmFile;
char version[3];
pgmFile = fopen(filename, "rb");
if (pgmFile == NULL) {
printf("pgmparse error: can't open file!\n");
exit(-1);
}
fgets(version, sizeof(version), pgmFile);
if (strcmp(version, "P5")) {
fprintf(stderr, "Wrong filetype?\n");
exit(-1);
}
int rows, cols;
int maxGrey = 0;
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &cols);
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &rows);
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &maxGrey);
fgetc(pgmFile); // Skip a newline(?)
int bytesNeeded = sizeof(float)*rows*cols;
printf("Rows: %d and Cols: %d\n", rows, cols);
printf("Bytes needed: %d\n", bytesNeeded);
printf("Max greyscale color: %d\n", maxGrey);
float *imageData = (float*) malloc(bytesNeeded);
int i,j, lo, hi;
if (maxGrey > 255) {
for(i = 0; i < rows; ++i) {
for(j = 0; j < cols; ++j) {
hi = fgetc(pgmFile);
lo = fgetc(pgmFile);
imageData[i*rows+j] = (float)((hi<<8)+lo);
}
printf("\n");
}
} else {
for(i = 0; i < rows; ++i) {
for(j = 0; j < cols; ++j) {
lo = fgetc(pgmFile);
imageData[i*cols+j] = lo/255.0;
}
}
}
fclose(pgmFile);
*width = cols;
*height = rows;
return imageData;
}
void savePGM(const char *filename, float* imageData, int width, int height) {
printf("Saving image %s\n", filename);
int i,j;
FILE *file;
file = fopen(filename, "w");
if (file == NULL) {
printf("Error creating file\n");
exit(-1);
} else {
fprintf(file,"P5\n%d %d\n255\n", width, height);
for(i = 0; i < height; ++i) {
for(j = 0; j < width; ++j)
fputc(255*imageData[i*width + j],file);
}
fclose(file);
}
}
void skipFileComments(FILE *fp)
{
int ch;
char line[100];
while ((ch = fgetc(fp)) != EOF && isspace(ch))
;
if (ch == '#') {
fgets(line, sizeof(line), fp);
skipFileComments(fp);
} else
fseek(fp, -1, SEEK_CUR);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "pgm.cuh"
#include <cstdio>
#include <cstdlib>
#include <cctype>
/*
Source for some of the parsing code:
http://ugurkoltuk.wordpress.com/2010/03/04/an-extreme-simple-pgm-io-api/
*/
void skipFileComments(FILE *fp);
float* loadPGM(const char *filename, int *width, int *height) {
printf("Loading image %s\n", filename);
FILE *pgmFile;
char version[3];
pgmFile = fopen(filename, "rb");
if (pgmFile == NULL) {
printf("pgmparse error: can't open file!\n");
exit(-1);
}
fgets(version, sizeof(version), pgmFile);
if (strcmp(version, "P5")) {
fprintf(stderr, "Wrong filetype?\n");
exit(-1);
}
int rows, cols;
int maxGrey = 0;
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &cols);
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &rows);
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &maxGrey);
fgetc(pgmFile); // Skip a newline(?)
int bytesNeeded = sizeof(float)*rows*cols;
printf("Rows: %d and Cols: %d\n", rows, cols);
printf("Bytes needed: %d\n", bytesNeeded);
printf("Max greyscale color: %d\n", maxGrey);
float *imageData = (float*) malloc(bytesNeeded);
int i,j, lo, hi;
if (maxGrey > 255) {
for(i = 0; i < rows; ++i) {
for(j = 0; j < cols; ++j) {
hi = fgetc(pgmFile);
lo = fgetc(pgmFile);
imageData[i*rows+j] = (float)((hi<<8)+lo);
}
printf("\n");
}
} else {
for(i = 0; i < rows; ++i) {
for(j = 0; j < cols; ++j) {
lo = fgetc(pgmFile);
imageData[i*cols+j] = lo/255.0;
}
}
}
fclose(pgmFile);
*width = cols;
*height = rows;
return imageData;
}
void savePGM(const char *filename, float* imageData, int width, int height) {
printf("Saving image %s\n", filename);
int i,j;
FILE *file;
file = fopen(filename, "w");
if (file == NULL) {
printf("Error creating file\n");
exit(-1);
} else {
fprintf(file,"P5\n%d %d\n255\n", width, height);
for(i = 0; i < height; ++i) {
for(j = 0; j < width; ++j)
fputc(255*imageData[i*width + j],file);
}
fclose(file);
}
}
void skipFileComments(FILE *fp)
{
int ch;
char line[100];
while ((ch = fgetc(fp)) != EOF && isspace(ch))
;
if (ch == '#') {
fgets(line, sizeof(line), fp);
skipFileComments(fp);
} else
fseek(fp, -1, SEEK_CUR);
} | .file "tmpxft_0009ee4c_00000000-6_pgm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Saving image %s\n"
.LC1:
.string "w"
.LC2:
.string "Error creating file\n"
.LC3:
.string "P5\n%d %d\n255\n"
.text
.globl _Z7savePGMPKcPfii
.type _Z7savePGMPKcPfii, @function
_Z7savePGMPKcPfii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movl %edx, %r13d
movl %ecx, 4(%rsp)
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
testq %rax, %rax
je .L12
movq %rax, %r12
movl 4(%rsp), %ebx
movl %ebx, %r8d
movl %r13d, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
testl %ebx, %ebx
jle .L5
movl $0, %r15d
movl $0, %r14d
jmp .L6
.L12:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
movslq %r15d, %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r13d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L7:
movss (%rbx), %xmm0
mulss .LC4(%rip), %xmm0
cvttss2sil %xmm0, %edi
movq %r12, %rsi
call fputc@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
.L9:
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, 4(%rsp)
je .L5
.L6:
testl %r13d, %r13d
jg .L8
jmp .L9
.L5:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7savePGMPKcPfii, .-_Z7savePGMPKcPfii
.globl _Z16skipFileCommentsP8_IO_FILE
.type _Z16skipFileCommentsP8_IO_FILE, @function
_Z16skipFileCommentsP8_IO_FILE:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
.L15:
movq %rbp, %rdi
call fgetc@PLT
movl %eax, %ebx
cmpl $-1, %eax
je .L14
call __ctype_b_loc@PLT
movq %rax, %rdx
movslq %ebx, %rax
movq (%rdx), %rdx
testb $32, 1(%rdx,%rax,2)
jne .L15
cmpl $35, %ebx
jne .L14
movq %rsp, %rdi
movq %rbp, %rcx
movl $100, %edx
movl $100, %esi
call __fgets_chk@PLT
movq %rbp, %rdi
call _Z16skipFileCommentsP8_IO_FILE
jmp .L13
.L14:
movl $1, %edx
movq $-1, %rsi
movq %rbp, %rdi
call fseek@PLT
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z16skipFileCommentsP8_IO_FILE, .-_Z16skipFileCommentsP8_IO_FILE
.section .rodata.str1.1
.LC5:
.string "Loading image %s\n"
.LC6:
.string "rb"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "pgmparse error: can't open file!\n"
.section .rodata.str1.1
.LC8:
.string "P5"
.LC9:
.string "Wrong filetype?\n"
.LC10:
.string "%d"
.LC11:
.string "Rows: %d and Cols: %d\n"
.LC12:
.string "Bytes needed: %d\n"
.LC13:
.string "Max greyscale color: %d\n"
.LC14:
.string "\n"
.text
.globl _Z7loadPGMPKcPiS1_
.type _Z7loadPGMPKcPiS1_, @function
_Z7loadPGMPKcPiS1_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rdi, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
testq %rax, %rax
je .L44
movq %rax, %r12
leaq 37(%rsp), %rbx
movq %rax, %rcx
movl $3, %edx
movl $3, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L45
movl $0, 32(%rsp)
movq %r12, %rdi
call _Z16skipFileCommentsP8_IO_FILE
leaq 28(%rsp), %rdx
leaq .LC10(%rip), %rbx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call _Z16skipFileCommentsP8_IO_FILE
leaq 24(%rsp), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call _Z16skipFileCommentsP8_IO_FILE
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call fgetc@PLT
movl 24(%rsp), %edx
movl 28(%rsp), %ecx
movl %edx, %ebx
imull %ecx, %ebx
sall $2, %ebx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rdi
call malloc@PLT
movq %rax, %r13
cmpl $255, 32(%rsp)
jg .L24
movl %r15d, %ebp
cmpl $0, 24(%rsp)
jg .L25
.L26:
movq %r12, %rdi
call fclose@PLT
movl 28(%rsp), %eax
movq (%rsp), %rsi
movl %eax, (%rsi)
movl 24(%rsp), %eax
movq 8(%rsp), %rsi
movl %eax, (%rsi)
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L46
movq %r13, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
movl %r15d, %r14d
cmpl $0, 24(%rsp)
jg .L27
jmp .L26
.L28:
movq %r12, %rdi
call fgetc@PLT
movl %eax, %ebx
movq %r12, %rdi
call fgetc@PLT
movl %eax, %edx
movl %r14d, %eax
imull 24(%rsp), %eax
addl %ebp, %eax
cltq
sall $8, %ebx
addl %edx, %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addl $1, %ebp
cmpl %ebp, 28(%rsp)
jg .L28
.L29:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl %r14d, 24(%rsp)
jle .L26
.L27:
movl %r15d, %ebp
cmpl $0, 28(%rsp)
jg .L28
jmp .L29
.L30:
movq %r12, %rdi
call fgetc@PLT
movl %eax, %ecx
movl 28(%rsp), %edx
movl %edx, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
divsd .LC15(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jg .L30
.L31:
addl $1, %ebp
cmpl %ebp, 24(%rsp)
jle .L26
.L25:
movl %r15d, %ebx
cmpl $0, 28(%rsp)
jg .L30
jmp .L31
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7loadPGMPKcPiS1_, .-_Z7loadPGMPKcPiS1_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1132396544
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC15:
.long 0
.long 1081073664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "pgm.cuh"
#include <cstdio>
#include <cstdlib>
#include <cctype>
/*
Source for some of the parsing code:
http://ugurkoltuk.wordpress.com/2010/03/04/an-extreme-simple-pgm-io-api/
*/
void skipFileComments(FILE *fp);
float* loadPGM(const char *filename, int *width, int *height) {
printf("Loading image %s\n", filename);
FILE *pgmFile;
char version[3];
pgmFile = fopen(filename, "rb");
if (pgmFile == NULL) {
printf("pgmparse error: can't open file!\n");
exit(-1);
}
fgets(version, sizeof(version), pgmFile);
if (strcmp(version, "P5")) {
fprintf(stderr, "Wrong filetype?\n");
exit(-1);
}
int rows, cols;
int maxGrey = 0;
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &cols);
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &rows);
skipFileComments(pgmFile);
fscanf(pgmFile, "%d", &maxGrey);
fgetc(pgmFile); // Skip a newline(?)
int bytesNeeded = sizeof(float)*rows*cols;
printf("Rows: %d and Cols: %d\n", rows, cols);
printf("Bytes needed: %d\n", bytesNeeded);
printf("Max greyscale color: %d\n", maxGrey);
float *imageData = (float*) malloc(bytesNeeded);
int i,j, lo, hi;
if (maxGrey > 255) {
for(i = 0; i < rows; ++i) {
for(j = 0; j < cols; ++j) {
hi = fgetc(pgmFile);
lo = fgetc(pgmFile);
imageData[i*rows+j] = (float)((hi<<8)+lo);
}
printf("\n");
}
} else {
for(i = 0; i < rows; ++i) {
for(j = 0; j < cols; ++j) {
lo = fgetc(pgmFile);
imageData[i*cols+j] = lo/255.0;
}
}
}
fclose(pgmFile);
*width = cols;
*height = rows;
return imageData;
}
void savePGM(const char *filename, float* imageData, int width, int height) {
printf("Saving image %s\n", filename);
int i,j;
FILE *file;
file = fopen(filename, "w");
if (file == NULL) {
printf("Error creating file\n");
exit(-1);
} else {
fprintf(file,"P5\n%d %d\n255\n", width, height);
for(i = 0; i < height; ++i) {
for(j = 0; j < width; ++j)
fputc(255*imageData[i*width + j],file);
}
fclose(file);
}
}
void skipFileComments(FILE *fp)
{
int ch;
char line[100];
while ((ch = fgetc(fp)) != EOF && isspace(ch))
;
if (ch == '#') {
fgets(line, sizeof(line), fp);
skipFileComments(fp);
} else
fseek(fp, -1, SEEK_CUR);
} | #ifndef LCUDA_PGM_H_
#define LCUDA_PGM_H_
float* loadPGM(const char *filename, int *width, int *height);
///[BUGFIX] Õâ¸öº¯ÊýòËÆ»áÍùÎļþÀï¶àдµã¶«Î÷
void savePGM(const char *filename, float* imageData, int width, int height);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef LCUDA_PGM_H_
#define LCUDA_PGM_H_
float* loadPGM(const char *filename, int *width, int *height);
///[BUGFIX] Õâ¸öº¯ÊýòËÆ»áÍùÎļþÀï¶àдµã¶«Î÷
void savePGM(const char *filename, float* imageData, int width, int height);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef LCUDA_PGM_H_
#define LCUDA_PGM_H_
float* loadPGM(const char *filename, int *width, int *height);
///[BUGFIX] Õâ¸öº¯ÊýòËÆ»áÍùÎļþÀï¶àдµã¶«Î÷
void savePGM(const char *filename, float* imageData, int width, int height);
#endif | .text
.file "pgm.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009ee4c_00000000-6_pgm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Saving image %s\n"
.LC1:
.string "w"
.LC2:
.string "Error creating file\n"
.LC3:
.string "P5\n%d %d\n255\n"
.text
.globl _Z7savePGMPKcPfii
.type _Z7savePGMPKcPfii, @function
_Z7savePGMPKcPfii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movl %edx, %r13d
movl %ecx, 4(%rsp)
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
testq %rax, %rax
je .L12
movq %rax, %r12
movl 4(%rsp), %ebx
movl %ebx, %r8d
movl %r13d, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
testl %ebx, %ebx
jle .L5
movl $0, %r15d
movl $0, %r14d
jmp .L6
.L12:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
movslq %r15d, %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r13d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L7:
movss (%rbx), %xmm0
mulss .LC4(%rip), %xmm0
cvttss2sil %xmm0, %edi
movq %r12, %rsi
call fputc@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
.L9:
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, 4(%rsp)
je .L5
.L6:
testl %r13d, %r13d
jg .L8
jmp .L9
.L5:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7savePGMPKcPfii, .-_Z7savePGMPKcPfii
.globl _Z16skipFileCommentsP8_IO_FILE
.type _Z16skipFileCommentsP8_IO_FILE, @function
_Z16skipFileCommentsP8_IO_FILE:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
.L15:
movq %rbp, %rdi
call fgetc@PLT
movl %eax, %ebx
cmpl $-1, %eax
je .L14
call __ctype_b_loc@PLT
movq %rax, %rdx
movslq %ebx, %rax
movq (%rdx), %rdx
testb $32, 1(%rdx,%rax,2)
jne .L15
cmpl $35, %ebx
jne .L14
movq %rsp, %rdi
movq %rbp, %rcx
movl $100, %edx
movl $100, %esi
call __fgets_chk@PLT
movq %rbp, %rdi
call _Z16skipFileCommentsP8_IO_FILE
jmp .L13
.L14:
movl $1, %edx
movq $-1, %rsi
movq %rbp, %rdi
call fseek@PLT
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z16skipFileCommentsP8_IO_FILE, .-_Z16skipFileCommentsP8_IO_FILE
.section .rodata.str1.1
.LC5:
.string "Loading image %s\n"
.LC6:
.string "rb"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "pgmparse error: can't open file!\n"
.section .rodata.str1.1
.LC8:
.string "P5"
.LC9:
.string "Wrong filetype?\n"
.LC10:
.string "%d"
.LC11:
.string "Rows: %d and Cols: %d\n"
.LC12:
.string "Bytes needed: %d\n"
.LC13:
.string "Max greyscale color: %d\n"
.LC14:
.string "\n"
.text
.globl _Z7loadPGMPKcPiS1_
.type _Z7loadPGMPKcPiS1_, @function
_Z7loadPGMPKcPiS1_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rdi, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
testq %rax, %rax
je .L44
movq %rax, %r12
leaq 37(%rsp), %rbx
movq %rax, %rcx
movl $3, %edx
movl $3, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L45
movl $0, 32(%rsp)
movq %r12, %rdi
call _Z16skipFileCommentsP8_IO_FILE
leaq 28(%rsp), %rdx
leaq .LC10(%rip), %rbx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call _Z16skipFileCommentsP8_IO_FILE
leaq 24(%rsp), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call _Z16skipFileCommentsP8_IO_FILE
leaq 32(%rsp), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %r12, %rdi
call fgetc@PLT
movl 24(%rsp), %edx
movl 28(%rsp), %ecx
movl %edx, %ebx
imull %ecx, %ebx
sall $2, %ebx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rdi
call malloc@PLT
movq %rax, %r13
cmpl $255, 32(%rsp)
jg .L24
movl %r15d, %ebp
cmpl $0, 24(%rsp)
jg .L25
.L26:
movq %r12, %rdi
call fclose@PLT
movl 28(%rsp), %eax
movq (%rsp), %rsi
movl %eax, (%rsi)
movl 24(%rsp), %eax
movq 8(%rsp), %rsi
movl %eax, (%rsi)
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L46
movq %r13, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
movl %r15d, %r14d
cmpl $0, 24(%rsp)
jg .L27
jmp .L26
.L28:
movq %r12, %rdi
call fgetc@PLT
movl %eax, %ebx
movq %r12, %rdi
call fgetc@PLT
movl %eax, %edx
movl %r14d, %eax
imull 24(%rsp), %eax
addl %ebp, %eax
cltq
sall $8, %ebx
addl %edx, %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addl $1, %ebp
cmpl %ebp, 28(%rsp)
jg .L28
.L29:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl %r14d, 24(%rsp)
jle .L26
.L27:
movl %r15d, %ebp
cmpl $0, 28(%rsp)
jg .L28
jmp .L29
.L30:
movq %r12, %rdi
call fgetc@PLT
movl %eax, %ecx
movl 28(%rsp), %edx
movl %edx, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
divsd .LC15(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jg .L30
.L31:
addl $1, %ebp
cmpl %ebp, 24(%rsp)
jle .L26
.L25:
movl %r15d, %ebx
cmpl $0, 28(%rsp)
jg .L30
jmp .L31
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7loadPGMPKcPiS1_, .-_Z7loadPGMPKcPiS1_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1132396544
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC15:
.long 0
.long 1081073664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pgm.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float* var_7,float* var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
if (comp <= var_1 + var_2 + -0.0f) {
comp = sinf((+1.4539E-41f * (var_4 + var_5 * (+0.0f * var_6))));
for (int i=0; i < var_3; ++i) {
var_7[i] = cosf((var_9 * sinf(-1.0267E26f / +1.2468E23f)));
var_8[i] = -1.2872E-42f;
comp += var_8[i] * var_7[i] - -0.0f - var_10;
}
if (comp == (var_11 * logf(+1.6407E19f))) {
float tmp_1 = (var_12 / var_13 - sqrtf((+1.0377E-37f - +1.5482E-44f + -1.5813E-35f * (-0.0f - -0.0f))));
float tmp_2 = (-1.6053E26f * +1.1100E-37f - ceilf(+1.9220E36f / ceilf(var_14 + (+1.6144E-36f / var_15 * (-1.8990E34f / (+1.5194E24f - -0.0f))))));
float tmp_3 = +0.0f;
comp = tmp_3 / tmp_2 / tmp_1 / var_16 / var_17 / var_18 + -1.0775E35f / sinhf(var_19 * -1.0626E-35f);
}
if (comp < var_20 * -1.6531E-42f * -0.0f) {
float tmp_4 = -0.0f;
comp = tmp_4 - +0.0f / (var_21 / -1.5219E-44f - var_22);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float* tmp_8 = initPointer( atof(argv[8]) );
float* tmp_9 = initPointer( atof(argv[9]) );
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00014f13_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
.type _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff, @function
_Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 60(%rsp)
movss %xmm1, 56(%rsp)
movss %xmm2, 52(%rsp)
movl %edi, 48(%rsp)
movss %xmm3, 44(%rsp)
movss %xmm4, 40(%rsp)
movss %xmm5, 36(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 376(%rsp), %rax
movq %rax, 256(%rsp)
leaq 384(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
leaq 400(%rsp), %rax
movq %rax, 280(%rsp)
leaq 408(%rsp), %rax
movq %rax, 288(%rsp)
leaq 416(%rsp), %rax
movq %rax, 296(%rsp)
leaq 424(%rsp), %rax
movq %rax, 304(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 344
pushq 72(%rsp)
.cfi_def_cfa_offset 352
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefffifffPfS_ffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff, .-_Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
.globl _Z7computefffifffPfS_ffffffffffffff
.type _Z7computefffifffPfS_ffffffffffffff, @function
_Z7computefffifffPfS_ffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 200(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffifffPfS_ffffffffffffff, .-_Z7computefffifffPfS_ffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -96(%rsp), %rsp
.cfi_def_cfa_offset 336
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
movq %r13, %rdx
movq %r12, %rsi
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
movl %ebp, %edi
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
call _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffifffPfS_ffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffifffPfS_ffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float* var_7,float* var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
if (comp <= var_1 + var_2 + -0.0f) {
comp = sinf((+1.4539E-41f * (var_4 + var_5 * (+0.0f * var_6))));
for (int i=0; i < var_3; ++i) {
var_7[i] = cosf((var_9 * sinf(-1.0267E26f / +1.2468E23f)));
var_8[i] = -1.2872E-42f;
comp += var_8[i] * var_7[i] - -0.0f - var_10;
}
if (comp == (var_11 * logf(+1.6407E19f))) {
float tmp_1 = (var_12 / var_13 - sqrtf((+1.0377E-37f - +1.5482E-44f + -1.5813E-35f * (-0.0f - -0.0f))));
float tmp_2 = (-1.6053E26f * +1.1100E-37f - ceilf(+1.9220E36f / ceilf(var_14 + (+1.6144E-36f / var_15 * (-1.8990E34f / (+1.5194E24f - -0.0f))))));
float tmp_3 = +0.0f;
comp = tmp_3 / tmp_2 / tmp_1 / var_16 / var_17 / var_18 + -1.0775E35f / sinhf(var_19 * -1.0626E-35f);
}
if (comp < var_20 * -1.6531E-42f * -0.0f) {
float tmp_4 = -0.0f;
comp = tmp_4 - +0.0f / (var_21 / -1.5219E-44f - var_22);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float* tmp_8 = initPointer( atof(argv[8]) );
float* tmp_9 = initPointer( atof(argv[9]) );
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float* var_7,float* var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
if (comp <= var_1 + var_2 + -0.0f) {
comp = sinf((+1.4539E-41f * (var_4 + var_5 * (+0.0f * var_6))));
for (int i=0; i < var_3; ++i) {
var_7[i] = cosf((var_9 * sinf(-1.0267E26f / +1.2468E23f)));
var_8[i] = -1.2872E-42f;
comp += var_8[i] * var_7[i] - -0.0f - var_10;
}
if (comp == (var_11 * logf(+1.6407E19f))) {
float tmp_1 = (var_12 / var_13 - sqrtf((+1.0377E-37f - +1.5482E-44f + -1.5813E-35f * (-0.0f - -0.0f))));
float tmp_2 = (-1.6053E26f * +1.1100E-37f - ceilf(+1.9220E36f / ceilf(var_14 + (+1.6144E-36f / var_15 * (-1.8990E34f / (+1.5194E24f - -0.0f))))));
float tmp_3 = +0.0f;
comp = tmp_3 / tmp_2 / tmp_1 / var_16 / var_17 / var_18 + -1.0775E35f / sinhf(var_19 * -1.0626E-35f);
}
if (comp < var_20 * -1.6531E-42f * -0.0f) {
float tmp_4 = -0.0f;
comp = tmp_4 - +0.0f / (var_21 / -1.5219E-44f - var_22);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float* tmp_8 = initPointer( atof(argv[8]) );
float* tmp_9 = initPointer( atof(argv[9]) );
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float* var_7,float* var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
if (comp <= var_1 + var_2 + -0.0f) {
comp = sinf((+1.4539E-41f * (var_4 + var_5 * (+0.0f * var_6))));
for (int i=0; i < var_3; ++i) {
var_7[i] = cosf((var_9 * sinf(-1.0267E26f / +1.2468E23f)));
var_8[i] = -1.2872E-42f;
comp += var_8[i] * var_7[i] - -0.0f - var_10;
}
if (comp == (var_11 * logf(+1.6407E19f))) {
float tmp_1 = (var_12 / var_13 - sqrtf((+1.0377E-37f - +1.5482E-44f + -1.5813E-35f * (-0.0f - -0.0f))));
float tmp_2 = (-1.6053E26f * +1.1100E-37f - ceilf(+1.9220E36f / ceilf(var_14 + (+1.6144E-36f / var_15 * (-1.8990E34f / (+1.5194E24f - -0.0f))))));
float tmp_3 = +0.0f;
comp = tmp_3 / tmp_2 / tmp_1 / var_16 / var_17 / var_18 + -1.0775E35f / sinhf(var_19 * -1.0626E-35f);
}
if (comp < var_20 * -1.6531E-42f * -0.0f) {
float tmp_4 = -0.0f;
comp = tmp_4 - +0.0f / (var_21 / -1.5219E-44f - var_22);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float* tmp_8 = initPointer( atof(argv[8]) );
float* tmp_9 = initPointer( atof(argv[9]) );
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefffifffPfS_ffffffffffffff # -- Begin function _Z22__device_stub__computefffifffPfS_ffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefffifffPfS_ffffffffffffff,@function
_Z22__device_stub__computefffifffPfS_ffffffffffffff: # @_Z22__device_stub__computefffifffPfS_ffffffffffffff
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movl %edi, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movq %rsi, 104(%rsp)
movq %rdx, 96(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 304(%rsp), %rax
movq %rax, 200(%rsp)
leaq 312(%rsp), %rax
movq %rax, 208(%rsp)
leaq 320(%rsp), %rax
movq %rax, 216(%rsp)
leaq 328(%rsp), %rax
movq %rax, 224(%rsp)
leaq 336(%rsp), %rax
movq %rax, 232(%rsp)
leaq 344(%rsp), %rax
movq %rax, 240(%rsp)
leaq 352(%rsp), %rax
movq %rax, 248(%rsp)
leaq 360(%rsp), %rax
movq %rax, 256(%rsp)
leaq 368(%rsp), %rax
movq %rax, 264(%rsp)
leaq 376(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 392(%rsp), %rax
movq %rax, 288(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefffifffPfS_ffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffifffPfS_ffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffifffPfS_ffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 96(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 72(%r14), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 96(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit50
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 176(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 184(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 88(%rsp)
movss %xmm9, 80(%rsp)
movss %xmm10, 72(%rsp)
movss %xmm11, 64(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm13, 48(%rsp)
movss %xmm14, 40(%rsp)
movss %xmm15, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movss 120(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movq %r15, %rsi
movq %r12, %rdx
movss 96(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 104(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefffifffPfS_ffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffifffPfS_ffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffifffPfS_ffffffffffffff,@object # @_Z7computefffifffPfS_ffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefffifffPfS_ffffffffffffff
.p2align 3, 0x0
_Z7computefffifffPfS_ffffffffffffff:
.quad _Z22__device_stub__computefffifffPfS_ffffffffffffff
.size _Z7computefffifffPfS_ffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffifffPfS_ffffffffffffff"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffifffPfS_ffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffifffPfS_ffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00014f13_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
.type _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff, @function
_Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 60(%rsp)
movss %xmm1, 56(%rsp)
movss %xmm2, 52(%rsp)
movl %edi, 48(%rsp)
movss %xmm3, 44(%rsp)
movss %xmm4, 40(%rsp)
movss %xmm5, 36(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 376(%rsp), %rax
movq %rax, 256(%rsp)
leaq 384(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
leaq 400(%rsp), %rax
movq %rax, 280(%rsp)
leaq 408(%rsp), %rax
movq %rax, 288(%rsp)
leaq 416(%rsp), %rax
movq %rax, 296(%rsp)
leaq 424(%rsp), %rax
movq %rax, 304(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 344
pushq 72(%rsp)
.cfi_def_cfa_offset 352
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefffifffPfS_ffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff, .-_Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
.globl _Z7computefffifffPfS_ffffffffffffff
.type _Z7computefffifffPfS_ffffffffffffff, @function
_Z7computefffifffPfS_ffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss 200(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffifffPfS_ffffffffffffff, .-_Z7computefffifffPfS_ffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 180(%rsp), %rdx
movl $1, %ecx
movq 168(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 152(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -96(%rsp), %rsp
.cfi_def_cfa_offset 336
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 192(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 200(%rsp), %xmm6
movq %r13, %rdx
movq %r12, %rsi
pxor %xmm5, %xmm5
cvtsd2ss 208(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 216(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 224(%rsp), %xmm3
movl %ebp, %edi
pxor %xmm2, %xmm2
cvtsd2ss 232(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
call _Z49__device_stub__Z7computefffifffPfS_fffffffffffffffffifffPfS_ffffffffffffff
addq $96, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffifffPfS_ffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffifffPfS_ffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefffifffPfS_ffffffffffffff # -- Begin function _Z22__device_stub__computefffifffPfS_ffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefffifffPfS_ffffffffffffff,@function
_Z22__device_stub__computefffifffPfS_ffffffffffffff: # @_Z22__device_stub__computefffifffPfS_ffffffffffffff
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movl %edi, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movq %rsi, 104(%rsp)
movq %rdx, 96(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 304(%rsp), %rax
movq %rax, 200(%rsp)
leaq 312(%rsp), %rax
movq %rax, 208(%rsp)
leaq 320(%rsp), %rax
movq %rax, 216(%rsp)
leaq 328(%rsp), %rax
movq %rax, 224(%rsp)
leaq 336(%rsp), %rax
movq %rax, 232(%rsp)
leaq 344(%rsp), %rax
movq %rax, 240(%rsp)
leaq 352(%rsp), %rax
movq %rax, 248(%rsp)
leaq 360(%rsp), %rax
movq %rax, 256(%rsp)
leaq 368(%rsp), %rax
movq %rax, 264(%rsp)
leaq 376(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 392(%rsp), %rax
movq %rax, 288(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefffifffPfS_ffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffifffPfS_ffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffifffPfS_ffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 96(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 72(%r14), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 96(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit50
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 176(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 184(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 96(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 88(%rsp)
movss %xmm9, 80(%rsp)
movss %xmm10, 72(%rsp)
movss %xmm11, 64(%rsp)
movss %xmm12, 56(%rsp)
movss %xmm13, 48(%rsp)
movss %xmm14, 40(%rsp)
movss %xmm15, 32(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, (%rsp)
movl %ebx, %edi
movss 120(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movq %r15, %rsi
movq %r12, %rdx
movss 96(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 104(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefffifffPfS_ffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffifffPfS_ffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffifffPfS_ffffffffffffff,@object # @_Z7computefffifffPfS_ffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefffifffPfS_ffffffffffffff
.p2align 3, 0x0
_Z7computefffifffPfS_ffffffffffffff:
.quad _Z22__device_stub__computefffifffPfS_ffffffffffffff
.size _Z7computefffifffPfS_ffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffifffPfS_ffffffffffffff"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffifffPfS_ffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffifffPfS_ffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __device__ void kernel(int* result) { *result = 1; } | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __device__ void kernel(int* result) { *result = 1; } | .file "tmpxft_0011f461_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl kernel
.type kernel, @function
kernel:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size kernel, .-kernel
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __device__ void kernel(int* result) { *result = 1; } | #include <hip/hip_runtime.h>
extern "C" __device__ void kernel(int* result) { *result = 1; } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __device__ void kernel(int* result) { *result = 1; } | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __device__ void kernel(int* result) { *result = 1; } | .text
.file "test.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011f461_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl kernel
.type kernel, @function
kernel:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size kernel, .-kernel
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void leakyrelu_kernel(float* output,
float* input,
float slope,
int dim_xw,
int dim_xh){
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float input_s[1024];
// if(tid < 1024){
if(idx < dim_xw *dim_xh){
input_s[tid] = input[idx];
}
if(tid < 1024){
input_s[tid] = fmaxf(0,input_s[tid]) + slope * fminf(0,input_s[tid]);
}
if(idx < dim_xw *dim_xh){
output[idx] = input_s[tid];
}
}
void launch_leakyrelu(float* output_y,
float *input_X,
float slope,
int dim_xw,
int dim_xh
){
int num_element = dim_xw * dim_xh;
dim3 gridSize((num_element+1023)/1024);
dim3 blockSize(1024);
leakyrelu_kernel<<<gridSize, blockSize>>>(output_y, \
input_X, \
slope, \
dim_xw,\
dim_xh);
} | code for sm_80
Function : _Z16leakyrelu_kernelPfS_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0080*/ ISETP.GT.AND P0, PT, R5, 0x3ff, PT ; /* 0x000003ff0500780c */
/* 0x000fc80003f04270 */
/*0090*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00b0*/ @P1 BRA 0x100 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ @!P0 LDS R3, [R5.X4] ; /* 0x0000000005038984 */
/* 0x000e640000004800 */
/*0120*/ @!P0 FMNMX R2, RZ, R3.reuse, !PT ; /* 0x00000003ff028209 */
/* 0x083fe40007800000 */
/*0130*/ @!P0 FMNMX R3, RZ, R3, PT ; /* 0x00000003ff038209 */
/* 0x000fca0003800000 */
/*0140*/ @!P0 FFMA R2, R3, c[0x0][0x170], R2 ; /* 0x00005c0003028a23 */
/* 0x000fca0000000002 */
/*0150*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x0001e20000004800 */
/*0160*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0170*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x001e220000004800 */
/*0180*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void leakyrelu_kernel(float* output,
float* input,
float slope,
int dim_xw,
int dim_xh){
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float input_s[1024];
// if(tid < 1024){
if(idx < dim_xw *dim_xh){
input_s[tid] = input[idx];
}
if(tid < 1024){
input_s[tid] = fmaxf(0,input_s[tid]) + slope * fminf(0,input_s[tid]);
}
if(idx < dim_xw *dim_xh){
output[idx] = input_s[tid];
}
}
void launch_leakyrelu(float* output_y,
float *input_X,
float slope,
int dim_xw,
int dim_xh
){
int num_element = dim_xw * dim_xh;
dim3 gridSize((num_element+1023)/1024);
dim3 blockSize(1024);
leakyrelu_kernel<<<gridSize, blockSize>>>(output_y, \
input_X, \
slope, \
dim_xw,\
dim_xh);
} | .file "tmpxft_00016e72_00000000-6_leakyrelu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
.type _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii, @function
_Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16leakyrelu_kernelPfS_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii, .-_Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
.globl _Z16leakyrelu_kernelPfS_fii
.type _Z16leakyrelu_kernelPfS_fii, @function
_Z16leakyrelu_kernelPfS_fii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16leakyrelu_kernelPfS_fii, .-_Z16leakyrelu_kernelPfS_fii
.globl _Z16launch_leakyreluPfS_fii
.type _Z16launch_leakyreluPfS_fii, @function
_Z16launch_leakyreluPfS_fii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movss %xmm0, 12(%rsp)
movl %edx, %ebx
movl %ecx, %ebp
imull %ecx, %edx
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movss 12(%rsp), %xmm0
movq %r13, %rsi
movq %r12, %rdi
call _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z16launch_leakyreluPfS_fii, .-_Z16launch_leakyreluPfS_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16leakyrelu_kernelPfS_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16leakyrelu_kernelPfS_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void leakyrelu_kernel(float* output,
float* input,
float slope,
int dim_xw,
int dim_xh){
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float input_s[1024];
// if(tid < 1024){
if(idx < dim_xw *dim_xh){
input_s[tid] = input[idx];
}
if(tid < 1024){
input_s[tid] = fmaxf(0,input_s[tid]) + slope * fminf(0,input_s[tid]);
}
if(idx < dim_xw *dim_xh){
output[idx] = input_s[tid];
}
}
void launch_leakyrelu(float* output_y,
float *input_X,
float slope,
int dim_xw,
int dim_xh
){
int num_element = dim_xw * dim_xh;
dim3 gridSize((num_element+1023)/1024);
dim3 blockSize(1024);
leakyrelu_kernel<<<gridSize, blockSize>>>(output_y, \
input_X, \
slope, \
dim_xw,\
dim_xh);
} | #include <hip/hip_runtime.h>
__global__ void leakyrelu_kernel(float* output,
float* input,
float slope,
int dim_xw,
int dim_xh){
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float input_s[1024];
// if(tid < 1024){
if(idx < dim_xw *dim_xh){
input_s[tid] = input[idx];
}
if(tid < 1024){
input_s[tid] = fmaxf(0,input_s[tid]) + slope * fminf(0,input_s[tid]);
}
if(idx < dim_xw *dim_xh){
output[idx] = input_s[tid];
}
}
void launch_leakyrelu(float* output_y,
float *input_X,
float slope,
int dim_xw,
int dim_xh
){
int num_element = dim_xw * dim_xh;
dim3 gridSize((num_element+1023)/1024);
dim3 blockSize(1024);
leakyrelu_kernel<<<gridSize, blockSize>>>(output_y, \
input_X, \
slope, \
dim_xw,\
dim_xh);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void leakyrelu_kernel(float* output,
float* input,
float slope,
int dim_xw,
int dim_xh){
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float input_s[1024];
// if(tid < 1024){
if(idx < dim_xw *dim_xh){
input_s[tid] = input[idx];
}
if(tid < 1024){
input_s[tid] = fmaxf(0,input_s[tid]) + slope * fminf(0,input_s[tid]);
}
if(idx < dim_xw *dim_xh){
output[idx] = input_s[tid];
}
}
void launch_leakyrelu(float* output_y,
float *input_X,
float slope,
int dim_xw,
int dim_xh
){
int num_element = dim_xw * dim_xh;
dim3 gridSize((num_element+1023)/1024);
dim3 blockSize(1024);
leakyrelu_kernel<<<gridSize, blockSize>>>(output_y, \
input_X, \
slope, \
dim_xw,\
dim_xh);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16leakyrelu_kernelPfS_fii
.globl _Z16leakyrelu_kernelPfS_fii
.p2align 8
.type _Z16leakyrelu_kernelPfS_fii,@function
_Z16leakyrelu_kernelPfS_fii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v3, 2, v0
s_load_b32 s2, s[0:1], 0x10
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
v_max_f32_e32 v4, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_f32_e32 v0, 0, v4
v_min_f32_e32 v4, 0, v4
v_fmac_f32_e32 v0, s2, v4
ds_store_b32 v3, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16leakyrelu_kernelPfS_fii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16leakyrelu_kernelPfS_fii, .Lfunc_end0-_Z16leakyrelu_kernelPfS_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16leakyrelu_kernelPfS_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16leakyrelu_kernelPfS_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void leakyrelu_kernel(float* output,
float* input,
float slope,
int dim_xw,
int dim_xh){
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float input_s[1024];
// if(tid < 1024){
if(idx < dim_xw *dim_xh){
input_s[tid] = input[idx];
}
if(tid < 1024){
input_s[tid] = fmaxf(0,input_s[tid]) + slope * fminf(0,input_s[tid]);
}
if(idx < dim_xw *dim_xh){
output[idx] = input_s[tid];
}
}
void launch_leakyrelu(float* output_y,
float *input_X,
float slope,
int dim_xw,
int dim_xh
){
int num_element = dim_xw * dim_xh;
dim3 gridSize((num_element+1023)/1024);
dim3 blockSize(1024);
leakyrelu_kernel<<<gridSize, blockSize>>>(output_y, \
input_X, \
slope, \
dim_xw,\
dim_xh);
} | .text
.file "leakyrelu_kernel.hip"
.globl _Z31__device_stub__leakyrelu_kernelPfS_fii # -- Begin function _Z31__device_stub__leakyrelu_kernelPfS_fii
.p2align 4, 0x90
.type _Z31__device_stub__leakyrelu_kernelPfS_fii,@function
_Z31__device_stub__leakyrelu_kernelPfS_fii: # @_Z31__device_stub__leakyrelu_kernelPfS_fii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16leakyrelu_kernelPfS_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__leakyrelu_kernelPfS_fii, .Lfunc_end0-_Z31__device_stub__leakyrelu_kernelPfS_fii
.cfi_endproc
# -- End function
.globl _Z16launch_leakyreluPfS_fii # -- Begin function _Z16launch_leakyreluPfS_fii
.p2align 4, 0x90
.type _Z16launch_leakyreluPfS_fii,@function
_Z16launch_leakyreluPfS_fii: # @_Z16launch_leakyreluPfS_fii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movss %xmm0, (%rsp) # 4-byte Spill
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %edi
imull %edx, %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp)
movl %ebp, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16leakyrelu_kernelPfS_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16launch_leakyreluPfS_fii, .Lfunc_end1-_Z16launch_leakyreluPfS_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16leakyrelu_kernelPfS_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16leakyrelu_kernelPfS_fii,@object # @_Z16leakyrelu_kernelPfS_fii
.section .rodata,"a",@progbits
.globl _Z16leakyrelu_kernelPfS_fii
.p2align 3, 0x0
_Z16leakyrelu_kernelPfS_fii:
.quad _Z31__device_stub__leakyrelu_kernelPfS_fii
.size _Z16leakyrelu_kernelPfS_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16leakyrelu_kernelPfS_fii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__leakyrelu_kernelPfS_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16leakyrelu_kernelPfS_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16leakyrelu_kernelPfS_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0080*/ ISETP.GT.AND P0, PT, R5, 0x3ff, PT ; /* 0x000003ff0500780c */
/* 0x000fc80003f04270 */
/*0090*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00b0*/ @P1 BRA 0x100 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ @!P0 LDS R3, [R5.X4] ; /* 0x0000000005038984 */
/* 0x000e640000004800 */
/*0120*/ @!P0 FMNMX R2, RZ, R3.reuse, !PT ; /* 0x00000003ff028209 */
/* 0x083fe40007800000 */
/*0130*/ @!P0 FMNMX R3, RZ, R3, PT ; /* 0x00000003ff038209 */
/* 0x000fca0003800000 */
/*0140*/ @!P0 FFMA R2, R3, c[0x0][0x170], R2 ; /* 0x00005c0003028a23 */
/* 0x000fca0000000002 */
/*0150*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */
/* 0x0001e20000004800 */
/*0160*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0170*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x001e220000004800 */
/*0180*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16leakyrelu_kernelPfS_fii
.globl _Z16leakyrelu_kernelPfS_fii
.p2align 8
.type _Z16leakyrelu_kernelPfS_fii,@function
_Z16leakyrelu_kernelPfS_fii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v3, 2, v0
s_load_b32 s2, s[0:1], 0x10
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
v_max_f32_e32 v4, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_f32_e32 v0, 0, v4
v_min_f32_e32 v4, 0, v4
v_fmac_f32_e32 v0, s2, v4
ds_store_b32 v3, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16leakyrelu_kernelPfS_fii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16leakyrelu_kernelPfS_fii, .Lfunc_end0-_Z16leakyrelu_kernelPfS_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16leakyrelu_kernelPfS_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16leakyrelu_kernelPfS_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00016e72_00000000-6_leakyrelu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
.type _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii, @function
_Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16leakyrelu_kernelPfS_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii, .-_Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
.globl _Z16leakyrelu_kernelPfS_fii
.type _Z16leakyrelu_kernelPfS_fii, @function
_Z16leakyrelu_kernelPfS_fii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16leakyrelu_kernelPfS_fii, .-_Z16leakyrelu_kernelPfS_fii
.globl _Z16launch_leakyreluPfS_fii
.type _Z16launch_leakyreluPfS_fii, @function
_Z16launch_leakyreluPfS_fii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movss %xmm0, 12(%rsp)
movl %edx, %ebx
movl %ecx, %ebp
imull %ecx, %edx
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movss 12(%rsp), %xmm0
movq %r13, %rsi
movq %r12, %rdi
call _Z41__device_stub__Z16leakyrelu_kernelPfS_fiiPfS_fii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z16launch_leakyreluPfS_fii, .-_Z16launch_leakyreluPfS_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16leakyrelu_kernelPfS_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16leakyrelu_kernelPfS_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "leakyrelu_kernel.hip"
.globl _Z31__device_stub__leakyrelu_kernelPfS_fii # -- Begin function _Z31__device_stub__leakyrelu_kernelPfS_fii
.p2align 4, 0x90
.type _Z31__device_stub__leakyrelu_kernelPfS_fii,@function
_Z31__device_stub__leakyrelu_kernelPfS_fii: # @_Z31__device_stub__leakyrelu_kernelPfS_fii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16leakyrelu_kernelPfS_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__leakyrelu_kernelPfS_fii, .Lfunc_end0-_Z31__device_stub__leakyrelu_kernelPfS_fii
.cfi_endproc
# -- End function
.globl _Z16launch_leakyreluPfS_fii # -- Begin function _Z16launch_leakyreluPfS_fii
.p2align 4, 0x90
.type _Z16launch_leakyreluPfS_fii,@function
_Z16launch_leakyreluPfS_fii: # @_Z16launch_leakyreluPfS_fii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movss %xmm0, (%rsp) # 4-byte Spill
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %edi
imull %edx, %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp)
movl %ebp, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16leakyrelu_kernelPfS_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16launch_leakyreluPfS_fii, .Lfunc_end1-_Z16launch_leakyreluPfS_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16leakyrelu_kernelPfS_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16leakyrelu_kernelPfS_fii,@object # @_Z16leakyrelu_kernelPfS_fii
.section .rodata,"a",@progbits
.globl _Z16leakyrelu_kernelPfS_fii
.p2align 3, 0x0
_Z16leakyrelu_kernelPfS_fii:
.quad _Z31__device_stub__leakyrelu_kernelPfS_fii
.size _Z16leakyrelu_kernelPfS_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16leakyrelu_kernelPfS_fii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__leakyrelu_kernelPfS_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16leakyrelu_kernelPfS_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //ïîäêëþ÷åíèå áèáëèîòåê
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iomanip>
#include <time.h>
#include <iostream>
using namespace std;
#define N 1000
#define S 2
#define BLOCK_SIZE 1
__global__ void zeta(float* c)
{
int tid = threadIdx.x;
int idx = blockIdx.x;
int ind = blockDim.x * idx + tid + blockDim.y * blockIdx.y + threadIdx.y;
if (ind > N - 1) return;
float res = float(1) / pow(double(ind + 1), S);
c[ind] = res;
}
int homeWork3() {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* host_c;
float* dev_c;
cout << endl;
host_c = (float*)malloc(N * sizeof(float));
cudaMalloc((void**)& dev_c, N * sizeof(float));
cudaEventRecord(start, 0);
dim3 threadPerBlock = dim3(N / BLOCK_SIZE, 1);
dim3 blockPerGrid = dim3(BLOCK_SIZE, BLOCK_SIZE);
zeta << <blockPerGrid, threadPerBlock >> > (dev_c);
// Âðåìÿ ðàáîòû ÿäðà
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float KernelTime;
cudaEventElapsedTime(&KernelTime, start, stop);
printf("KernelTme: %f millseconds\n", KernelTime);
// Ïðîâåðêà íà îøèáêó âûïîëíåíèÿ ïðîãðàììû íà äåâàéñå
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("%s ", cudaGetErrorString(err));
cudaMemcpy(host_c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
float sum = 0;
for (int i = 0; i < N; i++)
{
//cout << host_c[i] << " ";
sum += host_c[i];
}
cout << endl;
cout << "Value Zeta Function: " << sum << " ";
float error = abs(4 * atan(1) * 4 * atan(1) / float(6) - sum);
printf("\nError: %f\n", error);
cudaFree(dev_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z4zetaPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002600 */
/*0050*/ IMAD.IADD R0, R0, 0x1, R7 ; /* 0x0000000100007824 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fc800078e0200 */
/*0070*/ IMAD R2, R5, c[0x0][0x4], R0 ; /* 0x0000010005027a24 */
/* 0x004fca00078e0200 */
/*0080*/ ISETP.GT.AND P0, PT, R2, 0x3e7, PT ; /* 0x000003e70200780c */
/* 0x000fda0003f04270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ BSSY B0, 0x100 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*00c0*/ MOV R0, 0xf0 ; /* 0x000000f000007802 */
/* 0x000fe40000000f00 */
/*00d0*/ I2F.F64 R4, R3 ; /* 0x0000000300047312 */
/* 0x00006a0000201c00 */
/*00e0*/ CALL.REL.NOINC 0x670 ; /* 0x0000058000007944 */
/* 0x003fea0003c00000 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ DADD R6, R4, 2 ; /* 0x4000000004067429 */
/* 0x000e220000000000 */
/*0110*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0120*/ BSSY B0, 0x240 ; /* 0x0000011000007945 */
/* 0x000ff00003800000 */
/*0130*/ LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007067812 */
/* 0x001fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fc600078e000f */
/*0150*/ ISETP.NE.AND P1, PT, R6, 0x7ff00000, PT ; /* 0x7ff000000600780c */
/* 0x000fe20003f25270 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000e */
/*0170*/ @!P0 CS2R R6, SRZ ; /* 0x0000000000068805 */
/* 0x000fd6000001ff00 */
/*0180*/ @P1 BRA 0x230 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0190*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e1c0003f0c200 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*01c0*/ LOP3.LUT R4, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05047812 */
/* 0x000fc800078ec0ff */
/*01d0*/ ISETP.NE.OR P0, PT, R4, 0x7ff00000, P0 ; /* 0x7ff000000400780c */
/* 0x000fda0000705670 */
/*01e0*/ @P0 BRA 0x230 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff077424 */
/* 0x000fe200078e00ff */
/*0210*/ BRA 0x230 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0220*/ DADD R6, R4, 2 ; /* 0x4000000004067429 */
/* 0x00004c0000000000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ MUFU.RCP64H R5, R7 ; /* 0x0000000700057308 */
/* 0x003e220000001800 */
/*0250*/ IADD3 R4, R7, 0x300402, RZ ; /* 0x0030040207047810 */
/* 0x000fe20007ffe0ff */
/*0260*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0270*/ BSSY B0, 0x360 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0280*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*0290*/ DFMA R8, R4, -R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000806 */
/*02a0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*02b0*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*02c0*/ DFMA R10, R8, -R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000806 */
/*02d0*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x0010620000000008 */
/*02e0*/ @P0 BRA 0x350 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fe200078ec0ff */
/*0300*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0310*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0320*/ IADD3 R8, R0, -0x100000, RZ ; /* 0xfff0000000087810 */
/* 0x002fe40007ffe0ff */
/*0330*/ MOV R0, 0x350 ; /* 0x0000035000007802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000008000007944 */
/* 0x001fea0003c00000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x002e620000301000 */
/*0370*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*03a0*/ FSEL R5, R8, 1, P0 ; /* 0x3f80000008057808 */
/* 0x002fca0000000000 */
/*03b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e220003f0c200 */
/*03e0*/ BSSY B1, 0x620 ; /* 0x0000023000017945 */
/* 0x000fda0003800000 */
/*03f0*/ @P0 BRA 0x5f0 ; /* 0x000001f000000947 */
/* 0x001fea0003800000 */
/*0400*/ LOP3.LUT R9, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05097812 */
/* 0x000fc800078ec0ff */
/*0410*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R3, 0x7fefffff, PT ; /* 0x7fefffff0300780c */
/* 0x000fda0003f06070 */
/*0430*/ @P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000005070812 */
/* 0x000fe200078e3cff */
/*0440*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe200078e00ff */
/*0450*/ @P0 BRA 0x610 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0460*/ ISETP.GE.U32.AND P0, PT, R9, 0x1000001, PT ; /* 0x010000010900780c */
/* 0x000fda0003f06070 */
/*0470*/ @!P0 BRA 0x550 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R7, R5, -0x3fe00000, RZ ; /* 0xc020000005077810 */
/* 0x000fe20007ffe0ff */
/*0490*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*04a0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x000e260000001800 */
/*04b0*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*04c0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*04d0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*04e0*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*04f0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0500*/ DMUL R8, R8, 2.2250738585072013831e-308 ; /* 0x0010000008087828 */
/* 0x001e0c0000000000 */
/*0510*/ DFMA R4, -R4, R8, 1 ; /* 0x3ff000000404742b */
/* 0x001e0c0000000108 */
/*0520*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0530*/ DFMA R6, R8, R4, R8 ; /* 0x000000040806722b */
/* 0x0010620000000008 */
/*0540*/ BRA 0x610 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0550*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0560*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0008 */
/*0570*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*0580*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0590*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*05a0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*05b0*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*05c0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*05d0*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x001e220000000000 */
/*05e0*/ BRA 0x610 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*05f0*/ LOP3.LUT R7, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005077812 */
/* 0x000fe200078efcff */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0610*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0000 */
/*0630*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x002fe400078e0006 */
/*0650*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*0660*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff99004007950 */
/* 0x000fec0003c3ffff */
/*0670*/ DADD R8, -RZ, |R4| ; /* 0x00000000ff087229 */
/* 0x000e220000000504 */
/*0680*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc400078e00ff */
/*0690*/ IMAD.MOV.U32 R12, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff0c7424 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff0d7424 */
/* 0x000fca00078e00ff */
/*06b0*/ SHF.R.U32.HI R26, RZ, 0x14, R9 ; /* 0x00000014ff1a7819 */
/* 0x001fc80000011609 */
/*06c0*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fda0003f05270 */
/*06d0*/ @!P0 DMUL R6, R8, 1.80143985094819840000e+16 ; /* 0x4350000008068828 */
/* 0x000e140000000000 */
/*06e0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff098224 */
/* 0x001fe200078e0007 */
/*06f0*/ @!P0 LEA.HI R26, R7, 0xffffffca, RZ, 0xc ; /* 0xffffffca071a8811 */
/* 0x000fe200078f60ff */
/*0700*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff088224 */
/* 0x000fe400078e0006 */
/*0710*/ IMAD.MOV.U32 R7, RZ, RZ, 0x43300000 ; /* 0x43300000ff077424 */
/* 0x000fe200078e00ff */
/*0720*/ LOP3.LUT R9, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09097812 */
/* 0x000fe200078ec0ff */
/*0730*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0740*/ IADD3 R6, R26, -0x3ff, RZ ; /* 0xfffffc011a067810 */
/* 0x000fe40007ffe0ff */
/*0750*/ LOP3.LUT R15, R9, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff00000090f7812 */
/* 0x000fc800078efcff */
/*0760*/ ISETP.GE.U32.AND P1, PT, R15, 0x3ff6a09f, PT ; /* 0x3ff6a09f0f00780c */
/* 0x000fda0003f26070 */
/*0770*/ @P1 IADD3 R9, R15, -0x100000, RZ ; /* 0xfff000000f091810 */
/* 0x000fe40007ffe0ff */
/*0780*/ @P1 IADD3 R6, R26, -0x3fe, RZ ; /* 0xfffffc021a061810 */
/* 0x000fc60007ffe0ff */
/*0790*/ @P1 IMAD.MOV.U32 R15, RZ, RZ, R9 ; /* 0x000000ffff0f1224 */
/* 0x000fe200078e0009 */
/*07a0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000006067812 */
/* 0x000fca00078e3cff */
/*07b0*/ DADD R10, R14, 1 ; /* 0x3ff000000e0a7429 */
/* 0x000e080000000000 */
/*07c0*/ DADD R14, R14, -1 ; /* 0xbff000000e0e7429 */
/* 0x000fe40000000000 */
/*07d0*/ MUFU.RCP64H R17, R11 ; /* 0x0000000b00117308 */
/* 0x001e240000001800 */
/*07e0*/ DFMA R8, -R10, R16, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000110 */
/*07f0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0800*/ DFMA R16, R16, R8, R16 ; /* 0x000000081010722b */
/* 0x001e0c0000000010 */
/*0810*/ DMUL R8, R16, R14 ; /* 0x0000000e10087228 */
/* 0x001e0c0000000000 */
/*0820*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x001e0c0000000008 */
/*0830*/ DMUL R18, R8, R8 ; /* 0x0000000808127228 */
/* 0x001e080000000000 */
/*0840*/ DADD R22, R14, -R8 ; /* 0x000000000e167229 */
/* 0x000e480000000808 */
/*0850*/ DFMA R12, R18, R12, c[0x2][0x0] ; /* 0x00800000120c762b */
/* 0x001e08000000000c */
/*0860*/ DADD R22, R22, R22 ; /* 0x0000000016167229 */
/* 0x002e480000000016 */
/*0870*/ DFMA R12, R18, R12, c[0x2][0x8] ; /* 0x00800200120c762b */
/* 0x001e08000000000c */
/*0880*/ DFMA R14, R14, -R8, R22 ; /* 0x800000080e0e722b */
/* 0x002fc80000000016 */
/*0890*/ DFMA R12, R18, R12, c[0x2][0x10] ; /* 0x00800400120c762b */
/* 0x001e08000000000c */
/*08a0*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x000fc80000000000 */
/*08b0*/ DFMA R12, R18, R12, c[0x2][0x18] ; /* 0x00800600120c762b */
/* 0x001e08000000000c */
/*08c0*/ DMUL R14, R16, R14 ; /* 0x0000000e100e7228 */
/* 0x000fc80000000000 */
/*08d0*/ DFMA R12, R18, R12, c[0x2][0x20] ; /* 0x00800800120c762b */
/* 0x001e08000000000c */
/*08e0*/ DFMA R16, R8, R8, -R10 ; /* 0x000000080810722b */
/* 0x000fc8000000080a */
/*08f0*/ DFMA R20, R18, R12, c[0x2][0x28] ; /* 0x00800a001214762b */
/* 0x001e0c000000000c */
/*0900*/ DFMA R12, R18, R20, c[0x2][0x30] ; /* 0x00800c00120c762b */
/* 0x001e0c0000000014 */
/*0910*/ DADD R22, -R12, c[0x2][0x30] ; /* 0x00800c000c167629 */
/* 0x001e0c0000000100 */
/*0920*/ DFMA R22, R18, R20, R22 ; /* 0x000000141216722b */
/* 0x001e080000000016 */
/*0930*/ DMUL R18, R8, R10 ; /* 0x0000000a08127228 */
/* 0x000e480000000000 */
/*0940*/ DADD R24, RZ, R22 ; /* 0x00000000ff187229 */
/* 0x0010a40000000016 */
/*0950*/ IADD3 R23, R15, 0x100000, RZ ; /* 0x001000000f177810 */
/* 0x001fe20007ffe0ff */
/*0960*/ IMAD.MOV.U32 R22, RZ, RZ, R14 ; /* 0x000000ffff167224 */
/* 0x000fe200078e000e */
/*0970*/ DFMA R20, R8, R10, -R18 ; /* 0x0000000a0814722b */
/* 0x002e080000000812 */
/*0980*/ DADD R24, R24, c[0x2][0x38] ; /* 0x00800e0018187629 */
/* 0x004e480000000000 */
/*0990*/ DFMA R20, R14, R10, R20 ; /* 0x0000000a0e14722b */
/* 0x001fc80000000014 */
/*09a0*/ DFMA R16, R8, R22, R16 ; /* 0x000000160810722b */
/* 0x000e080000000010 */
/*09b0*/ DADD R10, R12, R24 ; /* 0x000000000c0a7229 */
/* 0x002e480000000018 */
/*09c0*/ DFMA R20, R8, R16, R20 ; /* 0x000000100814722b */
/* 0x001fc80000000014 */
/*09d0*/ DMUL R16, R10, R18 ; /* 0x000000120a107228 */
/* 0x002e080000000000 */
/*09e0*/ DADD R22, R12, -R10 ; /* 0x000000000c167229 */
/* 0x000e48000000080a */
/*09f0*/ DFMA R12, R10, R18, -R16 ; /* 0x000000120a0c722b */
/* 0x001e080000000810 */
/*0a00*/ DADD R22, R24, R22 ; /* 0x0000000018167229 */
/* 0x002fc80000000016 */
/*0a10*/ DFMA R12, R10, R20, R12 ; /* 0x000000140a0c722b */
/* 0x001e0c000000000c */
/*0a20*/ DFMA R22, R22, R18, R12 ; /* 0x000000121616722b */
/* 0x001064000000000c */
/*0a30*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x001fe400078e00ff */
/*0a40*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fe400078e00ff */
/*0a50*/ DADD R12, R16, R22 ; /* 0x00000000100c7229 */
/* 0x002e0c0000000016 */
/*0a60*/ DADD R10, R8, R12 ; /* 0x00000000080a7229 */
/* 0x001e08000000000c */
/*0a70*/ DADD R16, R16, -R12 ; /* 0x0000000010107229 */
/* 0x000e48000000080c */
/*0a80*/ DADD R8, R8, -R10 ; /* 0x0000000008087229 */
/* 0x001e08000000080a */
/*0a90*/ DADD R16, R22, R16 ; /* 0x0000000016107229 */
/* 0x002fc80000000010 */
/*0aa0*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x001e0c0000000008 */
/*0ab0*/ DADD R8, R16, R8 ; /* 0x0000000010087229 */
/* 0x001e0c0000000008 */
/*0ac0*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e080000000008 */
/*0ad0*/ DADD R14, R6, c[0x2][0x40] ; /* 0x00801000060e7629 */
/* 0x000fc80000000000 */
/*0ae0*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x001e0c0000000008 */
/*0af0*/ DFMA R6, R14, c[0x2][0x48], R12 ; /* 0x008012000e067a2b */
/* 0x001e08000000000c */
/*0b00*/ DADD R10, R10, -R12 ; /* 0x000000000a0a7229 */
/* 0x000e48000000080c */
/*0b10*/ DFMA R16, -R14, c[0x2][0x48], R6 ; /* 0x008012000e107a2b */
/* 0x001e080000000106 */
/*0b20*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x002fc8000000000a */
/*0b30*/ DADD R16, -R12, R16 ; /* 0x000000000c107229 */
/* 0x001e0c0000000110 */
/*0b40*/ DADD R10, R10, -R16 ; /* 0x000000000a0a7229 */
/* 0x001e0c0000000810 */
/*0b50*/ DFMA R10, R14, c[0x2][0x50], R10 ; /* 0x008014000e0a7a2b */
/* 0x001e0c000000000a */
/*0b60*/ DADD R8, R6, R10 ; /* 0x0000000006087229 */
/* 0x001e0c000000000a */
/*0b70*/ DADD R12, R6, -R8 ; /* 0x00000000060c7229 */
/* 0x001e080000000808 */
/*0b80*/ DMUL R6, R8, 2 ; /* 0x4000000008067828 */
/* 0x000e480000000000 */
/*0b90*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x001fc8000000000c */
/*0ba0*/ DFMA R8, R8, 2, -R6 ; /* 0x400000000808782b */
/* 0x002e0c0000000806 */
/*0bb0*/ DFMA R8, R12, 2, R8 ; /* 0x400000000c08782b */
/* 0x0010640000000008 */
/*0bc0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe400078e00ff */
/*0bd0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fe400078e00ff */
/*0be0*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x002e0c0000000008 */
/*0bf0*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*0c00*/ FSETP.GEU.AND P0, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f0e200 */
/*0c10*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*0c20*/ DFMA R16, R14, c[0x2][0x58], R10 ; /* 0x008016000e107a2b */
/* 0x001e0c000000000a */
/*0c30*/ DFMA R14, R14, c[0x2][0x60], R16 ; /* 0x008018000e0e7a2b */
/* 0x001e0c0000000010 */
/*0c40*/ DFMA R16, R14, R18, c[0x2][0x68] ; /* 0x00801a000e10762b */
/* 0x001e0c0000000012 */
/*0c50*/ DFMA R16, R14, R16, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000010 */
/*0c60*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*0c70*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0c80*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*0c90*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*0ca0*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*0cb0*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*0cc0*/ DFMA R16, R14, R16, c[0x2][0xa8] ; /* 0x00802a000e10762b */
/* 0x001e0c0000000010 */
/*0cd0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0ce0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*0cf0*/ IMAD R15, R12, 0x100000, R17 ; /* 0x001000000c0f7824 */
/* 0x001fe400078e0211 */
/*0d00*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*0d10*/ @!P0 BRA 0xdf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0d20*/ FSETP.GEU.AND P1, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f2e200 */
/*0d30*/ DADD R14, R10, +INF ; /* 0x7ff000000a0e7429 */
/* 0x000fc80000000000 */
/*0d40*/ DSETP.GEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f0e000 */
/*0d50*/ FSEL R14, R14, RZ, P0 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000000000 */
/*0d60*/ @!P1 LEA.HI R13, R12, R12, RZ, 0x1 ; /* 0x0000000c0c0d9211 */
/* 0x000fe400078f08ff */
/*0d70*/ FSEL R15, R15, RZ, P0 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000000000 */
/*0d80*/ @!P1 SHF.R.S32.HI R13, RZ, 0x1, R13 ; /* 0x00000001ff0d9819 */
/* 0x000fca000001140d */
/*0d90*/ @!P1 IMAD.IADD R12, R12, 0x1, -R13 ; /* 0x000000010c0c9824 */
/* 0x000fe400078e0a0d */
/*0da0*/ @!P1 IMAD R13, R13, 0x100000, R17 ; /* 0x001000000d0d9824 */
/* 0x000fc600078e0211 */
/*0db0*/ @!P1 LEA R17, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c119811 */
/* 0x000fe200078ea0ff */
/*0dc0*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c9224 */
/* 0x000fe400078e0010 */
/*0dd0*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff109224 */
/* 0x000fcc00078e00ff */
/*0de0*/ @!P1 DMUL R14, R12, R16 ; /* 0x000000100c0e9228 */
/* 0x0000540000000000 */
/*0df0*/ LOP3.LUT R12, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f0c7812 */
/* 0x003fe200078ec0ff */
/*0e00*/ DADD R6, R6, -R10 ; /* 0x0000000006067229 */
/* 0x000e06000000080a */
/*0e10*/ ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fc60003f05270 */
/*0e20*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x001e220000000006 */
/*0e30*/ ISETP.EQ.AND P0, PT, R14, RZ, !P0 ; /* 0x000000ff0e00720c */
/* 0x000fda0004702270 */
/*0e40*/ @!P0 DFMA R14, R6, R14, R14 ; /* 0x0000000e060e822b */
/* 0x001064000000000e */
/*0e50*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0000 */
/*0e60*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0e70*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff18006007950 */
/* 0x002fea0003c3ffff */
/*0e80*/ BRA 0xe80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //ïîäêëþ÷åíèå áèáëèîòåê
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iomanip>
#include <time.h>
#include <iostream>
using namespace std;
#define N 1000
#define S 2
#define BLOCK_SIZE 1
__global__ void zeta(float* c)
{
int tid = threadIdx.x;
int idx = blockIdx.x;
int ind = blockDim.x * idx + tid + blockDim.y * blockIdx.y + threadIdx.y;
if (ind > N - 1) return;
float res = float(1) / pow(double(ind + 1), S);
c[ind] = res;
}
int homeWork3() {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* host_c;
float* dev_c;
cout << endl;
host_c = (float*)malloc(N * sizeof(float));
cudaMalloc((void**)& dev_c, N * sizeof(float));
cudaEventRecord(start, 0);
dim3 threadPerBlock = dim3(N / BLOCK_SIZE, 1);
dim3 blockPerGrid = dim3(BLOCK_SIZE, BLOCK_SIZE);
zeta << <blockPerGrid, threadPerBlock >> > (dev_c);
// Âðåìÿ ðàáîòû ÿäðà
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float KernelTime;
cudaEventElapsedTime(&KernelTime, start, stop);
printf("KernelTme: %f millseconds\n", KernelTime);
// Ïðîâåðêà íà îøèáêó âûïîëíåíèÿ ïðîãðàììû íà äåâàéñå
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("%s ", cudaGetErrorString(err));
cudaMemcpy(host_c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
float sum = 0;
for (int i = 0; i < N; i++)
{
//cout << host_c[i] << " ";
sum += host_c[i];
}
cout << endl;
cout << "Value Zeta Function: " << sum << " ";
float error = abs(4 * atan(1) * 4 * atan(1) / float(6) - sum);
printf("\nError: %f\n", error);
cudaFree(dev_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_00080ba9_00000000-6_home-work3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4zetaPfPf
.type _Z23__device_stub__Z4zetaPfPf, @function
_Z23__device_stub__Z4zetaPfPf:
.LFB3975:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4zetaPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z23__device_stub__Z4zetaPfPf, .-_Z23__device_stub__Z4zetaPfPf
.globl _Z4zetaPf
.type _Z4zetaPf, @function
_Z4zetaPf:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4zetaPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z4zetaPf, .-_Z4zetaPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "KernelTme: %f millseconds\n"
.LC2:
.string "%s "
.LC3:
.string "Value Zeta Function: "
.LC4:
.string " "
.LC7:
.string "\nError: %f\n"
.text
.globl _Z9homeWork3v
.type _Z9homeWork3v, @function
_Z9homeWork3v:
.LFB3949:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L26
cmpb $0, 56(%rbx)
je .L14
movzbl 67(%rbx), %eax
.L15:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $4000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1000, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L28
.L17:
movl $2, %ecx
movl $4000, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4000(%rbx), %rdx
movl $0x00000000, 8(%rsp)
.L18:
movss 8(%rsp), %xmm1
addss (%rax), %xmm1
movss %xmm1, 8(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L29
cmpb $0, 56(%rbx)
je .L21
movzbl 67(%rbx), %eax
.L22:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $21, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm2, %xmm2
cvtss2sd 8(%rsp), %xmm2
movsd %xmm2, 8(%rsp)
movapd %xmm2, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd .LC5(%rip), %xmm0
subsd 8(%rsp), %xmm0
andpd .LC6(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
call _ZSt16__throw_bad_castv@PLT
.L31:
call __stack_chk_fail@PLT
.L14:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L15
.L27:
movq 40(%rsp), %rdi
call _Z23__device_stub__Z4zetaPfPf
jmp .L16
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L29:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z9homeWork3v, .-_Z9homeWork3v
.section .rodata.str1.1
.LC8:
.string "_Z4zetaPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4zetaPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 1649608659
.long 1073369510
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //ïîäêëþ÷åíèå áèáëèîòåê
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <iomanip>
#include <time.h>
#include <iostream>
using namespace std;
#define N 1000
#define S 2
#define BLOCK_SIZE 1
__global__ void zeta(float* c)
{
int tid = threadIdx.x;
int idx = blockIdx.x;
int ind = blockDim.x * idx + tid + blockDim.y * blockIdx.y + threadIdx.y;
if (ind > N - 1) return;
float res = float(1) / pow(double(ind + 1), S);
c[ind] = res;
}
int homeWork3() {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float* host_c;
float* dev_c;
cout << endl;
host_c = (float*)malloc(N * sizeof(float));
cudaMalloc((void**)& dev_c, N * sizeof(float));
cudaEventRecord(start, 0);
dim3 threadPerBlock = dim3(N / BLOCK_SIZE, 1);
dim3 blockPerGrid = dim3(BLOCK_SIZE, BLOCK_SIZE);
zeta << <blockPerGrid, threadPerBlock >> > (dev_c);
// Âðåìÿ ðàáîòû ÿäðà
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float KernelTime;
cudaEventElapsedTime(&KernelTime, start, stop);
printf("KernelTme: %f millseconds\n", KernelTime);
// Ïðîâåðêà íà îøèáêó âûïîëíåíèÿ ïðîãðàììû íà äåâàéñå
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("%s ", cudaGetErrorString(err));
cudaMemcpy(host_c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
float sum = 0;
for (int i = 0; i < N; i++)
{
//cout << host_c[i] << " ";
sum += host_c[i];
}
cout << endl;
cout << "Value Zeta Function: " << sum << " ";
float error = abs(4 * atan(1) * 4 * atan(1) / float(6) - sum);
printf("\nError: %f\n", error);
cudaFree(dev_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #ifndef homeWork3_def
#define homeWork3_def
int homeWork3();
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef homeWork3_def
#define homeWork3_def
int homeWork3();
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef homeWork3_def
#define homeWork3_def
int homeWork3();
#endif | .text
.file "home-work3.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4zetaPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002600 */
/*0050*/ IMAD.IADD R0, R0, 0x1, R7 ; /* 0x0000000100007824 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fc800078e0200 */
/*0070*/ IMAD R2, R5, c[0x0][0x4], R0 ; /* 0x0000010005027a24 */
/* 0x004fca00078e0200 */
/*0080*/ ISETP.GT.AND P0, PT, R2, 0x3e7, PT ; /* 0x000003e70200780c */
/* 0x000fda0003f04270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ BSSY B0, 0x100 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*00c0*/ MOV R0, 0xf0 ; /* 0x000000f000007802 */
/* 0x000fe40000000f00 */
/*00d0*/ I2F.F64 R4, R3 ; /* 0x0000000300047312 */
/* 0x00006a0000201c00 */
/*00e0*/ CALL.REL.NOINC 0x670 ; /* 0x0000058000007944 */
/* 0x003fea0003c00000 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ DADD R6, R4, 2 ; /* 0x4000000004067429 */
/* 0x000e220000000000 */
/*0110*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0120*/ BSSY B0, 0x240 ; /* 0x0000011000007945 */
/* 0x000ff00003800000 */
/*0130*/ LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007067812 */
/* 0x001fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fc600078e000f */
/*0150*/ ISETP.NE.AND P1, PT, R6, 0x7ff00000, PT ; /* 0x7ff000000600780c */
/* 0x000fe20003f25270 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000e */
/*0170*/ @!P0 CS2R R6, SRZ ; /* 0x0000000000068805 */
/* 0x000fd6000001ff00 */
/*0180*/ @P1 BRA 0x230 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0190*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e1c0003f0c200 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*01c0*/ LOP3.LUT R4, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05047812 */
/* 0x000fc800078ec0ff */
/*01d0*/ ISETP.NE.OR P0, PT, R4, 0x7ff00000, P0 ; /* 0x7ff000000400780c */
/* 0x000fda0000705670 */
/*01e0*/ @P0 BRA 0x230 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff077424 */
/* 0x000fe200078e00ff */
/*0210*/ BRA 0x230 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0220*/ DADD R6, R4, 2 ; /* 0x4000000004067429 */
/* 0x00004c0000000000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ MUFU.RCP64H R5, R7 ; /* 0x0000000700057308 */
/* 0x003e220000001800 */
/*0250*/ IADD3 R4, R7, 0x300402, RZ ; /* 0x0030040207047810 */
/* 0x000fe20007ffe0ff */
/*0260*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0270*/ BSSY B0, 0x360 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0280*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*0290*/ DFMA R8, R4, -R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000806 */
/*02a0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*02b0*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*02c0*/ DFMA R10, R8, -R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000806 */
/*02d0*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x0010620000000008 */
/*02e0*/ @P0 BRA 0x350 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fe200078ec0ff */
/*0300*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0310*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0320*/ IADD3 R8, R0, -0x100000, RZ ; /* 0xfff0000000087810 */
/* 0x002fe40007ffe0ff */
/*0330*/ MOV R0, 0x350 ; /* 0x0000035000007802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000008000007944 */
/* 0x001fea0003c00000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x002e620000301000 */
/*0370*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*03a0*/ FSEL R5, R8, 1, P0 ; /* 0x3f80000008057808 */
/* 0x002fca0000000000 */
/*03b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e220003f0c200 */
/*03e0*/ BSSY B1, 0x620 ; /* 0x0000023000017945 */
/* 0x000fda0003800000 */
/*03f0*/ @P0 BRA 0x5f0 ; /* 0x000001f000000947 */
/* 0x001fea0003800000 */
/*0400*/ LOP3.LUT R9, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05097812 */
/* 0x000fc800078ec0ff */
/*0410*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R3, 0x7fefffff, PT ; /* 0x7fefffff0300780c */
/* 0x000fda0003f06070 */
/*0430*/ @P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000005070812 */
/* 0x000fe200078e3cff */
/*0440*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe200078e00ff */
/*0450*/ @P0 BRA 0x610 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0460*/ ISETP.GE.U32.AND P0, PT, R9, 0x1000001, PT ; /* 0x010000010900780c */
/* 0x000fda0003f06070 */
/*0470*/ @!P0 BRA 0x550 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R7, R5, -0x3fe00000, RZ ; /* 0xc020000005077810 */
/* 0x000fe20007ffe0ff */
/*0490*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*04a0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x000e260000001800 */
/*04b0*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*04c0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*04d0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*04e0*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*04f0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0500*/ DMUL R8, R8, 2.2250738585072013831e-308 ; /* 0x0010000008087828 */
/* 0x001e0c0000000000 */
/*0510*/ DFMA R4, -R4, R8, 1 ; /* 0x3ff000000404742b */
/* 0x001e0c0000000108 */
/*0520*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0530*/ DFMA R6, R8, R4, R8 ; /* 0x000000040806722b */
/* 0x0010620000000008 */
/*0540*/ BRA 0x610 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0550*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0560*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0008 */
/*0570*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*0580*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0590*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*05a0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*05b0*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*05c0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*05d0*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x001e220000000000 */
/*05e0*/ BRA 0x610 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*05f0*/ LOP3.LUT R7, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005077812 */
/* 0x000fe200078efcff */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0610*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0000 */
/*0630*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x002fe400078e0006 */
/*0650*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*0660*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff99004007950 */
/* 0x000fec0003c3ffff */
/*0670*/ DADD R8, -RZ, |R4| ; /* 0x00000000ff087229 */
/* 0x000e220000000504 */
/*0680*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc400078e00ff */
/*0690*/ IMAD.MOV.U32 R12, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff0c7424 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff0d7424 */
/* 0x000fca00078e00ff */
/*06b0*/ SHF.R.U32.HI R26, RZ, 0x14, R9 ; /* 0x00000014ff1a7819 */
/* 0x001fc80000011609 */
/*06c0*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fda0003f05270 */
/*06d0*/ @!P0 DMUL R6, R8, 1.80143985094819840000e+16 ; /* 0x4350000008068828 */
/* 0x000e140000000000 */
/*06e0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff098224 */
/* 0x001fe200078e0007 */
/*06f0*/ @!P0 LEA.HI R26, R7, 0xffffffca, RZ, 0xc ; /* 0xffffffca071a8811 */
/* 0x000fe200078f60ff */
/*0700*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff088224 */
/* 0x000fe400078e0006 */
/*0710*/ IMAD.MOV.U32 R7, RZ, RZ, 0x43300000 ; /* 0x43300000ff077424 */
/* 0x000fe200078e00ff */
/*0720*/ LOP3.LUT R9, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09097812 */
/* 0x000fe200078ec0ff */
/*0730*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0740*/ IADD3 R6, R26, -0x3ff, RZ ; /* 0xfffffc011a067810 */
/* 0x000fe40007ffe0ff */
/*0750*/ LOP3.LUT R15, R9, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff00000090f7812 */
/* 0x000fc800078efcff */
/*0760*/ ISETP.GE.U32.AND P1, PT, R15, 0x3ff6a09f, PT ; /* 0x3ff6a09f0f00780c */
/* 0x000fda0003f26070 */
/*0770*/ @P1 IADD3 R9, R15, -0x100000, RZ ; /* 0xfff000000f091810 */
/* 0x000fe40007ffe0ff */
/*0780*/ @P1 IADD3 R6, R26, -0x3fe, RZ ; /* 0xfffffc021a061810 */
/* 0x000fc60007ffe0ff */
/*0790*/ @P1 IMAD.MOV.U32 R15, RZ, RZ, R9 ; /* 0x000000ffff0f1224 */
/* 0x000fe200078e0009 */
/*07a0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000006067812 */
/* 0x000fca00078e3cff */
/*07b0*/ DADD R10, R14, 1 ; /* 0x3ff000000e0a7429 */
/* 0x000e080000000000 */
/*07c0*/ DADD R14, R14, -1 ; /* 0xbff000000e0e7429 */
/* 0x000fe40000000000 */
/*07d0*/ MUFU.RCP64H R17, R11 ; /* 0x0000000b00117308 */
/* 0x001e240000001800 */
/*07e0*/ DFMA R8, -R10, R16, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000110 */
/*07f0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0800*/ DFMA R16, R16, R8, R16 ; /* 0x000000081010722b */
/* 0x001e0c0000000010 */
/*0810*/ DMUL R8, R16, R14 ; /* 0x0000000e10087228 */
/* 0x001e0c0000000000 */
/*0820*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x001e0c0000000008 */
/*0830*/ DMUL R18, R8, R8 ; /* 0x0000000808127228 */
/* 0x001e080000000000 */
/*0840*/ DADD R22, R14, -R8 ; /* 0x000000000e167229 */
/* 0x000e480000000808 */
/*0850*/ DFMA R12, R18, R12, c[0x2][0x0] ; /* 0x00800000120c762b */
/* 0x001e08000000000c */
/*0860*/ DADD R22, R22, R22 ; /* 0x0000000016167229 */
/* 0x002e480000000016 */
/*0870*/ DFMA R12, R18, R12, c[0x2][0x8] ; /* 0x00800200120c762b */
/* 0x001e08000000000c */
/*0880*/ DFMA R14, R14, -R8, R22 ; /* 0x800000080e0e722b */
/* 0x002fc80000000016 */
/*0890*/ DFMA R12, R18, R12, c[0x2][0x10] ; /* 0x00800400120c762b */
/* 0x001e08000000000c */
/*08a0*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x000fc80000000000 */
/*08b0*/ DFMA R12, R18, R12, c[0x2][0x18] ; /* 0x00800600120c762b */
/* 0x001e08000000000c */
/*08c0*/ DMUL R14, R16, R14 ; /* 0x0000000e100e7228 */
/* 0x000fc80000000000 */
/*08d0*/ DFMA R12, R18, R12, c[0x2][0x20] ; /* 0x00800800120c762b */
/* 0x001e08000000000c */
/*08e0*/ DFMA R16, R8, R8, -R10 ; /* 0x000000080810722b */
/* 0x000fc8000000080a */
/*08f0*/ DFMA R20, R18, R12, c[0x2][0x28] ; /* 0x00800a001214762b */
/* 0x001e0c000000000c */
/*0900*/ DFMA R12, R18, R20, c[0x2][0x30] ; /* 0x00800c00120c762b */
/* 0x001e0c0000000014 */
/*0910*/ DADD R22, -R12, c[0x2][0x30] ; /* 0x00800c000c167629 */
/* 0x001e0c0000000100 */
/*0920*/ DFMA R22, R18, R20, R22 ; /* 0x000000141216722b */
/* 0x001e080000000016 */
/*0930*/ DMUL R18, R8, R10 ; /* 0x0000000a08127228 */
/* 0x000e480000000000 */
/*0940*/ DADD R24, RZ, R22 ; /* 0x00000000ff187229 */
/* 0x0010a40000000016 */
/*0950*/ IADD3 R23, R15, 0x100000, RZ ; /* 0x001000000f177810 */
/* 0x001fe20007ffe0ff */
/*0960*/ IMAD.MOV.U32 R22, RZ, RZ, R14 ; /* 0x000000ffff167224 */
/* 0x000fe200078e000e */
/*0970*/ DFMA R20, R8, R10, -R18 ; /* 0x0000000a0814722b */
/* 0x002e080000000812 */
/*0980*/ DADD R24, R24, c[0x2][0x38] ; /* 0x00800e0018187629 */
/* 0x004e480000000000 */
/*0990*/ DFMA R20, R14, R10, R20 ; /* 0x0000000a0e14722b */
/* 0x001fc80000000014 */
/*09a0*/ DFMA R16, R8, R22, R16 ; /* 0x000000160810722b */
/* 0x000e080000000010 */
/*09b0*/ DADD R10, R12, R24 ; /* 0x000000000c0a7229 */
/* 0x002e480000000018 */
/*09c0*/ DFMA R20, R8, R16, R20 ; /* 0x000000100814722b */
/* 0x001fc80000000014 */
/*09d0*/ DMUL R16, R10, R18 ; /* 0x000000120a107228 */
/* 0x002e080000000000 */
/*09e0*/ DADD R22, R12, -R10 ; /* 0x000000000c167229 */
/* 0x000e48000000080a */
/*09f0*/ DFMA R12, R10, R18, -R16 ; /* 0x000000120a0c722b */
/* 0x001e080000000810 */
/*0a00*/ DADD R22, R24, R22 ; /* 0x0000000018167229 */
/* 0x002fc80000000016 */
/*0a10*/ DFMA R12, R10, R20, R12 ; /* 0x000000140a0c722b */
/* 0x001e0c000000000c */
/*0a20*/ DFMA R22, R22, R18, R12 ; /* 0x000000121616722b */
/* 0x001064000000000c */
/*0a30*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x001fe400078e00ff */
/*0a40*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fe400078e00ff */
/*0a50*/ DADD R12, R16, R22 ; /* 0x00000000100c7229 */
/* 0x002e0c0000000016 */
/*0a60*/ DADD R10, R8, R12 ; /* 0x00000000080a7229 */
/* 0x001e08000000000c */
/*0a70*/ DADD R16, R16, -R12 ; /* 0x0000000010107229 */
/* 0x000e48000000080c */
/*0a80*/ DADD R8, R8, -R10 ; /* 0x0000000008087229 */
/* 0x001e08000000080a */
/*0a90*/ DADD R16, R22, R16 ; /* 0x0000000016107229 */
/* 0x002fc80000000010 */
/*0aa0*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x001e0c0000000008 */
/*0ab0*/ DADD R8, R16, R8 ; /* 0x0000000010087229 */
/* 0x001e0c0000000008 */
/*0ac0*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e080000000008 */
/*0ad0*/ DADD R14, R6, c[0x2][0x40] ; /* 0x00801000060e7629 */
/* 0x000fc80000000000 */
/*0ae0*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x001e0c0000000008 */
/*0af0*/ DFMA R6, R14, c[0x2][0x48], R12 ; /* 0x008012000e067a2b */
/* 0x001e08000000000c */
/*0b00*/ DADD R10, R10, -R12 ; /* 0x000000000a0a7229 */
/* 0x000e48000000080c */
/*0b10*/ DFMA R16, -R14, c[0x2][0x48], R6 ; /* 0x008012000e107a2b */
/* 0x001e080000000106 */
/*0b20*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x002fc8000000000a */
/*0b30*/ DADD R16, -R12, R16 ; /* 0x000000000c107229 */
/* 0x001e0c0000000110 */
/*0b40*/ DADD R10, R10, -R16 ; /* 0x000000000a0a7229 */
/* 0x001e0c0000000810 */
/*0b50*/ DFMA R10, R14, c[0x2][0x50], R10 ; /* 0x008014000e0a7a2b */
/* 0x001e0c000000000a */
/*0b60*/ DADD R8, R6, R10 ; /* 0x0000000006087229 */
/* 0x001e0c000000000a */
/*0b70*/ DADD R12, R6, -R8 ; /* 0x00000000060c7229 */
/* 0x001e080000000808 */
/*0b80*/ DMUL R6, R8, 2 ; /* 0x4000000008067828 */
/* 0x000e480000000000 */
/*0b90*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x001fc8000000000c */
/*0ba0*/ DFMA R8, R8, 2, -R6 ; /* 0x400000000808782b */
/* 0x002e0c0000000806 */
/*0bb0*/ DFMA R8, R12, 2, R8 ; /* 0x400000000c08782b */
/* 0x0010640000000008 */
/*0bc0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe400078e00ff */
/*0bd0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fe400078e00ff */
/*0be0*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x002e0c0000000008 */
/*0bf0*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*0c00*/ FSETP.GEU.AND P0, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f0e200 */
/*0c10*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*0c20*/ DFMA R16, R14, c[0x2][0x58], R10 ; /* 0x008016000e107a2b */
/* 0x001e0c000000000a */
/*0c30*/ DFMA R14, R14, c[0x2][0x60], R16 ; /* 0x008018000e0e7a2b */
/* 0x001e0c0000000010 */
/*0c40*/ DFMA R16, R14, R18, c[0x2][0x68] ; /* 0x00801a000e10762b */
/* 0x001e0c0000000012 */
/*0c50*/ DFMA R16, R14, R16, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000010 */
/*0c60*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*0c70*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0c80*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*0c90*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*0ca0*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*0cb0*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*0cc0*/ DFMA R16, R14, R16, c[0x2][0xa8] ; /* 0x00802a000e10762b */
/* 0x001e0c0000000010 */
/*0cd0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0ce0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*0cf0*/ IMAD R15, R12, 0x100000, R17 ; /* 0x001000000c0f7824 */
/* 0x001fe400078e0211 */
/*0d00*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*0d10*/ @!P0 BRA 0xdf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0d20*/ FSETP.GEU.AND P1, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f2e200 */
/*0d30*/ DADD R14, R10, +INF ; /* 0x7ff000000a0e7429 */
/* 0x000fc80000000000 */
/*0d40*/ DSETP.GEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f0e000 */
/*0d50*/ FSEL R14, R14, RZ, P0 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000000000 */
/*0d60*/ @!P1 LEA.HI R13, R12, R12, RZ, 0x1 ; /* 0x0000000c0c0d9211 */
/* 0x000fe400078f08ff */
/*0d70*/ FSEL R15, R15, RZ, P0 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000000000 */
/*0d80*/ @!P1 SHF.R.S32.HI R13, RZ, 0x1, R13 ; /* 0x00000001ff0d9819 */
/* 0x000fca000001140d */
/*0d90*/ @!P1 IMAD.IADD R12, R12, 0x1, -R13 ; /* 0x000000010c0c9824 */
/* 0x000fe400078e0a0d */
/*0da0*/ @!P1 IMAD R13, R13, 0x100000, R17 ; /* 0x001000000d0d9824 */
/* 0x000fc600078e0211 */
/*0db0*/ @!P1 LEA R17, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c119811 */
/* 0x000fe200078ea0ff */
/*0dc0*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c9224 */
/* 0x000fe400078e0010 */
/*0dd0*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff109224 */
/* 0x000fcc00078e00ff */
/*0de0*/ @!P1 DMUL R14, R12, R16 ; /* 0x000000100c0e9228 */
/* 0x0000540000000000 */
/*0df0*/ LOP3.LUT R12, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f0c7812 */
/* 0x003fe200078ec0ff */
/*0e00*/ DADD R6, R6, -R10 ; /* 0x0000000006067229 */
/* 0x000e06000000080a */
/*0e10*/ ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fc60003f05270 */
/*0e20*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x001e220000000006 */
/*0e30*/ ISETP.EQ.AND P0, PT, R14, RZ, !P0 ; /* 0x000000ff0e00720c */
/* 0x000fda0004702270 */
/*0e40*/ @!P0 DFMA R14, R6, R14, R14 ; /* 0x0000000e060e822b */
/* 0x001064000000000e */
/*0e50*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0000 */
/*0e60*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0e70*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff18006007950 */
/* 0x002fea0003c3ffff */
/*0e80*/ BRA 0xe80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00080ba9_00000000-6_home-work3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4zetaPfPf
.type _Z23__device_stub__Z4zetaPfPf, @function
_Z23__device_stub__Z4zetaPfPf:
.LFB3975:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4zetaPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z23__device_stub__Z4zetaPfPf, .-_Z23__device_stub__Z4zetaPfPf
.globl _Z4zetaPf
.type _Z4zetaPf, @function
_Z4zetaPf:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4zetaPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z4zetaPf, .-_Z4zetaPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "KernelTme: %f millseconds\n"
.LC2:
.string "%s "
.LC3:
.string "Value Zeta Function: "
.LC4:
.string " "
.LC7:
.string "\nError: %f\n"
.text
.globl _Z9homeWork3v
.type _Z9homeWork3v, @function
_Z9homeWork3v:
.LFB3949:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L26
cmpb $0, 56(%rbx)
je .L14
movzbl 67(%rbx), %eax
.L15:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $4000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1000, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L28
.L17:
movl $2, %ecx
movl $4000, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4000(%rbx), %rdx
movl $0x00000000, 8(%rsp)
.L18:
movss 8(%rsp), %xmm1
addss (%rax), %xmm1
movss %xmm1, 8(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L29
cmpb $0, 56(%rbx)
je .L21
movzbl 67(%rbx), %eax
.L22:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $21, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm2, %xmm2
cvtss2sd 8(%rsp), %xmm2
movsd %xmm2, 8(%rsp)
movapd %xmm2, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd .LC5(%rip), %xmm0
subsd 8(%rsp), %xmm0
andpd .LC6(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
call _ZSt16__throw_bad_castv@PLT
.L31:
call __stack_chk_fail@PLT
.L14:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L15
.L27:
movq 40(%rsp), %rdi
call _Z23__device_stub__Z4zetaPfPf
jmp .L16
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L29:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z9homeWork3v, .-_Z9homeWork3v
.section .rodata.str1.1
.LC8:
.string "_Z4zetaPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4zetaPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 1649608659
.long 1073369510
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "home-work3.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements:";
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=rand()%n;
cout<<a[i]<<"\t";
}
cudaEvent_t start1,end1;
cudaEventCreate(&start1);
cudaEventCreate(&end1);
cudaEventRecord(start1);
int sum1=0;
for(int i=0;i<n;i++)
{
sum1+=a[i];
}
float mean1=0.0f;
mean1=sum1/(n*1.0f);
cudaEventRecord(end1);
cudaEventSynchronize(end1);
float time1=0;
cudaEventElapsedTime(&time1,start1,end1);
cout<<"\nSequential Processing:";
cout<<"\nSum="<<sum1;
cout<<"\nMean="<<mean1;
cout<<"\nSequential time="<<time1;
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
cudaEvent_t start,end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
cudaEventRecord(end);
cudaEventSynchronize(end);
float time=0;
cudaEventElapsedTime(&time,start,end);
int add[2];
n=p;
cudaMemcpy(add,ad,4,cudaMemcpyDeviceToHost);
cout<<"\nSum="<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"Mean="<<mean<<endl;
cout<<"Parallel time="<<time<<endl;
} | code for sm_80
Function : _Z3sumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.SHL.U32 R5, R0, 0x100, RZ ; /* 0x0000010000057824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R2, R5, 0x100, RZ ; /* 0x0000010005027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX R2, R2, c[0x0][0x170], PT ; /* 0x00005c0002027a17 */
/* 0x000fc80003800200 */
/*0070*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x730 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, -R5, -0x101, RZ ; /* 0xfffffeff05037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R3, -R5, -0x2, -R8 ; /* 0xfffffffe05037810 */
/* 0x000fe40007ffe908 */
/*00e0*/ LOP3.LUT R2, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff027212 */
/* 0x000fe400078e33ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fc60003f06070 */
/*0100*/ IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102027824 */
/* 0x000fca00078e0a05 */
/*0110*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fca00078ec0ff */
/*0120*/ @!P0 BRA 0x660 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, R4, R8, R5 ; /* 0x0000000804077210 */
/* 0x000fe20007ffe005 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a07 */
/*0170*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc600078e0202 */
/*0180*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x580 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x400 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000e8000c1e1900 */
/*0240*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R21, [R2.64+0x18] ; /* 0x0000180402157981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R23, [R2.64+0x20] ; /* 0x0000200402177981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240402167981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R12, R12, R13, R6 ; /* 0x0000000d0c0c7210 */
/* 0x004fe40007ffe006 */
/*0350*/ IADD3 R13, P2, R2, 0x40, RZ ; /* 0x00000040020d7810 */
/* 0x000fca0007f5e0ff */
/*0360*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0370*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*0390*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*03a0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*03b0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*03c0*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*03d0*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*03e0*/ IADD3 R6, R8, R9, R10 ; /* 0x0000000908067210 */
/* 0x000fe20007ffe00a */
/*03f0*/ @P1 BRA 0x210 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0400*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0410*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0420*/ @!P1 BRA 0x560 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*0460*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e8000c1e1900 */
/*0470*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*04a0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000162000c1e1900 */
/*04b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04c0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R8, R8, R9, R6 ; /* 0x0000000908087210 */
/* 0x004fe40007ffe006 */
/*04f0*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fca0007f3e0ff */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0510*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0520*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0530*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0540*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*0550*/ IADD3 R6, R14, R15, R8 ; /* 0x0000000f0e067210 */
/* 0x020fe40007ffe008 */
/*0560*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0570*/ @!P0 BRA 0x660 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x0000a8000c1e1900 */
/*0590*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*05b0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e2000c1e1900 */
/*05c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*05d0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05e0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*05f0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0630*/ IADD3 R6, R8, R9, R6 ; /* 0x0000000908067210 */
/* 0x004fc80007ffe006 */
/*0640*/ IADD3 R6, R10, R11, R6 ; /* 0x0000000b0a067210 */
/* 0x008fe20007ffe006 */
/*0650*/ @P0 BRA 0x580 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0660*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0670*/ @!P0 BRA 0x730 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0003 */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0005 */
/*06c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*06f0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0700*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0710*/ IMAD.IADD R6, R3, 0x1, R6 ; /* 0x0000000103067824 */
/* 0x004fc800078e0206 */
/*0720*/ @P0 BRA 0x6b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0750*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements:";
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=rand()%n;
cout<<a[i]<<"\t";
}
cudaEvent_t start1,end1;
cudaEventCreate(&start1);
cudaEventCreate(&end1);
cudaEventRecord(start1);
int sum1=0;
for(int i=0;i<n;i++)
{
sum1+=a[i];
}
float mean1=0.0f;
mean1=sum1/(n*1.0f);
cudaEventRecord(end1);
cudaEventSynchronize(end1);
float time1=0;
cudaEventElapsedTime(&time1,start1,end1);
cout<<"\nSequential Processing:";
cout<<"\nSum="<<sum1;
cout<<"\nMean="<<mean1;
cout<<"\nSequential time="<<time1;
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
cudaEvent_t start,end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
cudaEventRecord(end);
cudaEventSynchronize(end);
float time=0;
cudaEventElapsedTime(&time,start,end);
int add[2];
n=p;
cudaMemcpy(add,ad,4,cudaMemcpyDeviceToHost);
cout<<"\nSum="<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"Mean="<<mean<<endl;
cout<<"Parallel time="<<time<<endl;
} | .file "tmpxft_0004a119_00000000-6_a13.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3sumPiS_iPiS_i
.type _Z25__device_stub__Z3sumPiS_iPiS_i, @function
_Z25__device_stub__Z3sumPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3sumPiS_iPiS_i, .-_Z25__device_stub__Z3sumPiS_iPiS_i
.globl _Z3sumPiS_i
.type _Z3sumPiS_i, @function
_Z3sumPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3sumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumPiS_i, .-_Z3sumPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the no of elements:"
.LC1:
.string "\t"
.LC3:
.string "\nSequential Processing:"
.LC4:
.string "\nSum="
.LC5:
.string "\nMean="
.LC6:
.string "\nSequential time="
.LC11:
.string "Mean="
.LC12:
.string "Parallel time="
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
addq $-128, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -132(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -132(%rbp), %edx
movslq %edx, %rax
leaq 15(,%rax,4), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L12:
cmpq %rcx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %r12
testl %edx, %edx
jle .L15
movl $0, %ebx
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
.L16:
call rand@PLT
cltd
idivl -132(%rbp)
movl %edx, %esi
movl %edx, (%r12,%rbx,4)
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, -132(%rbp)
jg .L16
.L15:
leaq -120(%rbp), %rdi
call cudaEventCreate@PLT
leaq -112(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -120(%rbp), %rdi
call cudaEventRecord@PLT
movl -132(%rbp), %ecx
testl %ecx, %ecx
jle .L25
movq %r12, %rax
movslq %ecx, %rdx
leaq (%r12,%rdx,4), %rdx
movl $0, %ebx
.L18:
addl (%rax), %ebx
addq $4, %rax
cmpq %rax, %rdx
jne .L18
.L17:
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
divss %xmm0, %xmm1
movss %xmm1, -148(%rbp)
movl $0, %esi
movq -112(%rbp), %rdi
call cudaEventRecord@PLT
movq -112(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -128(%rbp)
leaq -128(%rbp), %rdi
movq -112(%rbp), %rdx
movq -120(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -148(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC6(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -128(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movl -132(%rbp), %eax
leal 0(,%rax,4), %ebx
movslq %ebx, %rbx
leaq -104(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl -132(%rbp), %xmm0
mulss .LC7(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC13(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC8(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L19
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC10(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L19:
cvttss2sil %xmm3, %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq -96(%rbp), %rdi
call cudaMalloc@PLT
movl %ebx, -72(%rbp)
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $1, -52(%rbp)
movl -132(%rbp), %ebx
leaq -88(%rbp), %rdi
call cudaEventCreate@PLT
leaq -80(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -88(%rbp), %rdi
call cudaEventRecord@PLT
cmpl $1, -132(%rbp)
jg .L23
.L20:
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
movq -80(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -124(%rbp)
leaq -124(%rbp), %rdi
movq -80(%rbp), %rdx
movq -88(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl %ebx, -132(%rbp)
leaq -48(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -104(%rbp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -48(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -48(%rbp), %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl -132(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -148(%rbp)
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -148(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -124(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L25:
.cfi_restore_state
movl $0, %ebx
jmp .L17
.L31:
movl -132(%rbp), %edx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z25__device_stub__Z3sumPiS_iPiS_i
jmp .L21
.L22:
cvttss2sil %xmm2, %edx
movl %edx, -132(%rbp)
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $1, -132(%rbp)
jle .L20
.L23:
movl -52(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -60(%rbp), %rdx
movq -72(%rbp), %rdi
movl -64(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
pxor %xmm0, %xmm0
cvtsi2ssl -132(%rbp), %xmm0
mulss .LC7(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC13(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC8(%rip), %xmm5
ucomiss %xmm1, %xmm5
jbe .L22
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC10(%rip), %xmm6
andps %xmm6, %xmm2
addss %xmm2, %xmm1
movss .LC13(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z3sumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 998244352
.align 4
.LC8:
.long 1258291200
.align 4
.LC10:
.long 1065353216
.align 4
.LC13:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements:";
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=rand()%n;
cout<<a[i]<<"\t";
}
cudaEvent_t start1,end1;
cudaEventCreate(&start1);
cudaEventCreate(&end1);
cudaEventRecord(start1);
int sum1=0;
for(int i=0;i<n;i++)
{
sum1+=a[i];
}
float mean1=0.0f;
mean1=sum1/(n*1.0f);
cudaEventRecord(end1);
cudaEventSynchronize(end1);
float time1=0;
cudaEventElapsedTime(&time1,start1,end1);
cout<<"\nSequential Processing:";
cout<<"\nSum="<<sum1;
cout<<"\nMean="<<mean1;
cout<<"\nSequential time="<<time1;
int *ad,*bd;
int size=n*sizeof(int);
cudaMalloc(&ad,size);
cudaMemcpy(ad,a,size,cudaMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
cudaMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
cudaEvent_t start,end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
cudaMemcpy(ad,bd,n*sizeof(int),cudaMemcpyDeviceToDevice);
}
cudaEventRecord(end);
cudaEventSynchronize(end);
float time=0;
cudaEventElapsedTime(&time,start,end);
int add[2];
n=p;
cudaMemcpy(add,ad,4,cudaMemcpyDeviceToHost);
cout<<"\nSum="<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"Mean="<<mean<<endl;
cout<<"Parallel time="<<time<<endl;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements:";
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=rand()%n;
cout<<a[i]<<"\t";
}
hipEvent_t start1,end1;
hipEventCreate(&start1);
hipEventCreate(&end1);
hipEventRecord(start1);
int sum1=0;
for(int i=0;i<n;i++)
{
sum1+=a[i];
}
float mean1=0.0f;
mean1=sum1/(n*1.0f);
hipEventRecord(end1);
hipEventSynchronize(end1);
float time1=0;
hipEventElapsedTime(&time1,start1,end1);
cout<<"\nSequential Processing:";
cout<<"\nSum="<<sum1;
cout<<"\nMean="<<mean1;
cout<<"\nSequential time="<<time1;
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
hipEventRecord(end);
hipEventSynchronize(end);
float time=0;
hipEventElapsedTime(&time,start,end);
int add[2];
n=p;
hipMemcpy(add,ad,4,hipMemcpyDeviceToHost);
cout<<"\nSum="<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"Mean="<<mean<<endl;
cout<<"Parallel time="<<time<<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements:";
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=rand()%n;
cout<<a[i]<<"\t";
}
hipEvent_t start1,end1;
hipEventCreate(&start1);
hipEventCreate(&end1);
hipEventRecord(start1);
int sum1=0;
for(int i=0;i<n;i++)
{
sum1+=a[i];
}
float mean1=0.0f;
mean1=sum1/(n*1.0f);
hipEventRecord(end1);
hipEventSynchronize(end1);
float time1=0;
hipEventElapsedTime(&time1,start1,end1);
cout<<"\nSequential Processing:";
cout<<"\nSum="<<sum1;
cout<<"\nMean="<<mean1;
cout<<"\nSequential time="<<time1;
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
hipEventRecord(end);
hipEventSynchronize(end);
float time=0;
hipEventElapsedTime(&time,start,end);
int add[2];
n=p;
hipMemcpy(add,ad,4,hipMemcpyDeviceToHost);
cout<<"\nSum="<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"Mean="<<mean<<endl;
cout<<"Parallel time="<<time<<endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_i
.globl _Z3sumPiS_i
.p2align 8
.type _Z3sumPiS_i,@function
_Z3sumPiS_i:
s_load_b32 s3, s[0:1], 0x10
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, s15
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s3
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
s_add_i32 s10, s4, 0x100
s_lshl_b64 s[8:9], s[4:5], 2
s_min_i32 s3, s10, s3
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
.LBB0_2:
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s8, s5
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_ge_i32 s4, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_i, .Lfunc_end0-_Z3sumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstdio>
using namespace std;
__global__ void sum(int *a,int *b,int n)
{
int block=256*blockIdx.x;
int sum=0;
for(int i=block;i<min(block+256,n);i++)
{
sum=sum+a[i];
}
b[blockIdx.x]=sum;
}
int main()
{
cout<<"Enter the no of elements:";
int n;
cin>>n;
int a[n];
for(int i=0;i<n;i++)
{
a[i]=rand()%n;
cout<<a[i]<<"\t";
}
hipEvent_t start1,end1;
hipEventCreate(&start1);
hipEventCreate(&end1);
hipEventRecord(start1);
int sum1=0;
for(int i=0;i<n;i++)
{
sum1+=a[i];
}
float mean1=0.0f;
mean1=sum1/(n*1.0f);
hipEventRecord(end1);
hipEventSynchronize(end1);
float time1=0;
hipEventElapsedTime(&time1,start1,end1);
cout<<"\nSequential Processing:";
cout<<"\nSum="<<sum1;
cout<<"\nMean="<<mean1;
cout<<"\nSequential time="<<time1;
int *ad,*bd;
int size=n*sizeof(int);
hipMalloc(&ad,size);
hipMemcpy(ad,a,size,hipMemcpyHostToDevice);
int grids=ceil(n*1.0f/256.0f);
hipMalloc(&bd,grids*sizeof(int));
dim3 grid(grids,1);
dim3 block(1,1);
int p=n;
hipEvent_t start,end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
while(n>1)
{
sum<<<grid,block>>>(ad,bd,n);
n=ceil(n*1.0f/256.0f);
hipMemcpy(ad,bd,n*sizeof(int),hipMemcpyDeviceToDevice);
}
hipEventRecord(end);
hipEventSynchronize(end);
float time=0;
hipEventElapsedTime(&time,start,end);
int add[2];
n=p;
hipMemcpy(add,ad,4,hipMemcpyDeviceToHost);
cout<<"\nSum="<<add[0]<<endl;
float mean=0.0f;
mean=add[0]/(n*1.0f);
cout<<"Mean="<<mean<<endl;
cout<<"Parallel time="<<time<<endl;
} | .text
.file "a13.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumPiS_i # -- Begin function _Z18__device_stub__sumPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_i,@function
_Z18__device_stub__sumPiS_i: # @_Z18__device_stub__sumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiS_i, .Lfunc_end0-_Z18__device_stub__sumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $184, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, -168(%rbp) # 8-byte Spill
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
cmpl $0, -44(%rbp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl -44(%rbp)
movl %edx, (%rbx,%r14,4)
movl $_ZSt4cout, %edi
movl %edx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
movslq -44(%rbp), %rax
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq -128(%rbp), %rdi
callq hipEventCreate
leaq -80(%rbp), %rdi
callq hipEventCreate
movq -128(%rbp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph43.preheader
xorl %ecx, %ecx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph43
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %r14d
incq %rcx
cmpq %rcx, %rax
jne .LBB1_5
.LBB1_6: # %._crit_edge44
cvtsi2ss %r14d, %xmm1
cvtsi2ss %eax, %xmm0
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp) # 4-byte Spill
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -80(%rbp), %rdi
callq hipEventSynchronize
movl $0, -52(%rbp)
movq -128(%rbp), %rsi
movq -80(%rbp), %rdx
leaq -52(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -52(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl -44(%rbp), %eax
shll $2, %eax
movslq %eax, %r14
leaq -64(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -64(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movslq %ebx, %rsi
shlq $2, %rsi
leaq -120(%rbp), %rdi
callq hipMalloc
movl -44(%rbp), %eax
movl %eax, -48(%rbp) # 4-byte Spill
leaq -112(%rbp), %rdi
callq hipEventCreate
leaq -72(%rbp), %rdi
callq hipEventCreate
movq -112(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $2, -44(%rbp)
jl .LBB1_11
# %bb.7:
movabsq $4294967296, %r14 # imm = 0x100000000
orq %r14, %rbx
incq %r14
leaq -184(%rbp), %r13
leaq -176(%rbp), %r15
leaq -160(%rbp), %r12
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_8 Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movl %eax, -44(%rbp)
movq -64(%rbp), %rdi
movq -120(%rbp), %rsi
movslq %eax, %rdx
shlq $2, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, -44(%rbp)
jle .LBB1_11
.LBB1_8: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_8 Depth=1
movq -64(%rbp), %rax
movq -120(%rbp), %rcx
movl -44(%rbp), %edx
movq %rax, -216(%rbp)
movq %rcx, -208(%rbp)
movl %edx, -100(%rbp)
leaq -216(%rbp), %rax
movq %rax, -160(%rbp)
leaq -208(%rbp), %rax
movq %rax, -152(%rbp)
leaq -100(%rbp), %rax
movq %rax, -144(%rbp)
leaq -96(%rbp), %rdi
leaq -200(%rbp), %rsi
movq %r13, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -200(%rbp), %rcx
movl -192(%rbp), %r8d
movl $_Z3sumPiS_i, %edi
movq %r12, %r9
pushq -176(%rbp)
pushq -184(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_10
.LBB1_11: # %._crit_edge48
movq -72(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -72(%rbp), %rdi
callq hipEventSynchronize
movl $0, -96(%rbp)
movq -112(%rbp), %rsi
movq -72(%rbp), %rdx
leaq -96(%rbp), %rdi
callq hipEventElapsedTime
movl -48(%rbp), %eax # 4-byte Reload
movl %eax, -44(%rbp)
movq -64(%rbp), %rsi
leaq -160(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -160(%rbp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cvtsi2ssl -160(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
cmpb $0, 56(%rbx)
je .LBB1_18
# %bb.17:
movzbl 67(%rbx), %ecx
jmp .LBB1_19
.LBB1_18:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -96(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33
cmpb $0, 56(%rbx)
je .LBB1_22
# %bb.21:
movzbl 67(%rbx), %ecx
jmp .LBB1_23
.LBB1_22:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -168(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_24:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiS_i,@object # @_Z3sumPiS_i
.section .rodata,"a",@progbits
.globl _Z3sumPiS_i
.p2align 3, 0x0
_Z3sumPiS_i:
.quad _Z18__device_stub__sumPiS_i
.size _Z3sumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the no of elements:"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nSequential Processing:"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nSum="
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nMean="
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nSequential time="
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Mean="
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Parallel time="
.size .L.str.7, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPiS_i"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.SHL.U32 R5, R0, 0x100, RZ ; /* 0x0000010000057824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R2, R5, 0x100, RZ ; /* 0x0000010005027810 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX R2, R2, c[0x0][0x170], PT ; /* 0x00005c0002027a17 */
/* 0x000fc80003800200 */
/*0070*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x730 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, -R5, -0x101, RZ ; /* 0xfffffeff05037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R3, -R5, -0x2, -R8 ; /* 0xfffffffe05037810 */
/* 0x000fe40007ffe908 */
/*00e0*/ LOP3.LUT R2, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff027212 */
/* 0x000fe400078e33ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fc60003f06070 */
/*0100*/ IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102027824 */
/* 0x000fca00078e0a05 */
/*0110*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fca00078ec0ff */
/*0120*/ @!P0 BRA 0x660 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, R4, R8, R5 ; /* 0x0000000804077210 */
/* 0x000fe20007ffe005 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a07 */
/*0170*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc600078e0202 */
/*0180*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x580 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x400 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000e8000c1e1900 */
/*0240*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R21, [R2.64+0x18] ; /* 0x0000180402157981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R23, [R2.64+0x20] ; /* 0x0000200402177981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240402167981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340402087981 */
/* 0x000162000c1e1900 */
/*0310*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R12, R12, R13, R6 ; /* 0x0000000d0c0c7210 */
/* 0x004fe40007ffe006 */
/*0350*/ IADD3 R13, P2, R2, 0x40, RZ ; /* 0x00000040020d7810 */
/* 0x000fca0007f5e0ff */
/*0360*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0370*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*0390*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*03a0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*03b0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*03c0*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*03d0*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*03e0*/ IADD3 R6, R8, R9, R10 ; /* 0x0000000908067210 */
/* 0x000fe20007ffe00a */
/*03f0*/ @P1 BRA 0x210 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0400*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0410*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0420*/ @!P1 BRA 0x560 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*0460*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e8000c1e1900 */
/*0470*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*04a0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000162000c1e1900 */
/*04b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04c0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R8, R8, R9, R6 ; /* 0x0000000908087210 */
/* 0x004fe40007ffe006 */
/*04f0*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fca0007f3e0ff */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0510*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0520*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0530*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0540*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*0550*/ IADD3 R6, R14, R15, R8 ; /* 0x0000000f0e067210 */
/* 0x020fe40007ffe008 */
/*0560*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0570*/ @!P0 BRA 0x660 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x0000a8000c1e1900 */
/*0590*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*05b0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x0000e2000c1e1900 */
/*05c0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*05d0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05e0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*05f0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0630*/ IADD3 R6, R8, R9, R6 ; /* 0x0000000908067210 */
/* 0x004fc80007ffe006 */
/*0640*/ IADD3 R6, R10, R11, R6 ; /* 0x0000000b0a067210 */
/* 0x008fe20007ffe006 */
/*0650*/ @P0 BRA 0x580 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0660*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0670*/ @!P0 BRA 0x730 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0003 */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0005 */
/*06c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*06f0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0700*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0710*/ IMAD.IADD R6, R3, 0x1, R6 ; /* 0x0000000103067824 */
/* 0x004fc800078e0206 */
/*0720*/ @P0 BRA 0x6b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0750*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_i
.globl _Z3sumPiS_i
.p2align 8
.type _Z3sumPiS_i,@function
_Z3sumPiS_i:
s_load_b32 s3, s[0:1], 0x10
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, s15
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s3
s_cbranch_scc1 .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
s_add_i32 s10, s4, 0x100
s_lshl_b64 s[8:9], s[4:5], 2
s_min_i32 s3, s10, s3
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
.LBB0_2:
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s8, s5
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_ge_i32 s4, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_i, .Lfunc_end0-_Z3sumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004a119_00000000-6_a13.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3sumPiS_iPiS_i
.type _Z25__device_stub__Z3sumPiS_iPiS_i, @function
_Z25__device_stub__Z3sumPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3sumPiS_iPiS_i, .-_Z25__device_stub__Z3sumPiS_iPiS_i
.globl _Z3sumPiS_i
.type _Z3sumPiS_i, @function
_Z3sumPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3sumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumPiS_i, .-_Z3sumPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the no of elements:"
.LC1:
.string "\t"
.LC3:
.string "\nSequential Processing:"
.LC4:
.string "\nSum="
.LC5:
.string "\nMean="
.LC6:
.string "\nSequential time="
.LC11:
.string "Mean="
.LC12:
.string "Parallel time="
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
addq $-128, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -132(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -132(%rbp), %edx
movslq %edx, %rax
leaq 15(,%rax,4), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L12:
cmpq %rcx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %r12
testl %edx, %edx
jle .L15
movl $0, %ebx
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
.L16:
call rand@PLT
cltd
idivl -132(%rbp)
movl %edx, %esi
movl %edx, (%r12,%rbx,4)
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, -132(%rbp)
jg .L16
.L15:
leaq -120(%rbp), %rdi
call cudaEventCreate@PLT
leaq -112(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -120(%rbp), %rdi
call cudaEventRecord@PLT
movl -132(%rbp), %ecx
testl %ecx, %ecx
jle .L25
movq %r12, %rax
movslq %ecx, %rdx
leaq (%r12,%rdx,4), %rdx
movl $0, %ebx
.L18:
addl (%rax), %ebx
addq $4, %rax
cmpq %rax, %rdx
jne .L18
.L17:
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
divss %xmm0, %xmm1
movss %xmm1, -148(%rbp)
movl $0, %esi
movq -112(%rbp), %rdi
call cudaEventRecord@PLT
movq -112(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -128(%rbp)
leaq -128(%rbp), %rdi
movq -112(%rbp), %rdx
movq -120(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -148(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC6(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -128(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movl -132(%rbp), %eax
leal 0(,%rax,4), %ebx
movslq %ebx, %rbx
leaq -104(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl -132(%rbp), %xmm0
mulss .LC7(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC13(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC8(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L19
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC10(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L19:
cvttss2sil %xmm3, %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq -96(%rbp), %rdi
call cudaMalloc@PLT
movl %ebx, -72(%rbp)
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $1, -52(%rbp)
movl -132(%rbp), %ebx
leaq -88(%rbp), %rdi
call cudaEventCreate@PLT
leaq -80(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -88(%rbp), %rdi
call cudaEventRecord@PLT
cmpl $1, -132(%rbp)
jg .L23
.L20:
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
movq -80(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -124(%rbp)
leaq -124(%rbp), %rdi
movq -80(%rbp), %rdx
movq -88(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl %ebx, -132(%rbp)
leaq -48(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -104(%rbp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -48(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -48(%rbp), %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl -132(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -148(%rbp)
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -148(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -124(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L25:
.cfi_restore_state
movl $0, %ebx
jmp .L17
.L31:
movl -132(%rbp), %edx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z25__device_stub__Z3sumPiS_iPiS_i
jmp .L21
.L22:
cvttss2sil %xmm2, %edx
movl %edx, -132(%rbp)
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq -96(%rbp), %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $1, -132(%rbp)
jle .L20
.L23:
movl -52(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -60(%rbp), %rdx
movq -72(%rbp), %rdi
movl -64(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
pxor %xmm0, %xmm0
cvtsi2ssl -132(%rbp), %xmm0
mulss .LC7(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC13(%rip), %xmm1
andps %xmm0, %xmm1
movss .LC8(%rip), %xmm5
ucomiss %xmm1, %xmm5
jbe .L22
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC10(%rip), %xmm6
andps %xmm6, %xmm2
addss %xmm2, %xmm1
movss .LC13(%rip), %xmm2
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z3sumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 998244352
.align 4
.LC8:
.long 1258291200
.align 4
.LC10:
.long 1065353216
.align 4
.LC13:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "a13.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumPiS_i # -- Begin function _Z18__device_stub__sumPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_i,@function
_Z18__device_stub__sumPiS_i: # @_Z18__device_stub__sumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiS_i, .Lfunc_end0-_Z18__device_stub__sumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $184, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, -168(%rbp) # 8-byte Spill
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
cmpl $0, -44(%rbp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl -44(%rbp)
movl %edx, (%rbx,%r14,4)
movl $_ZSt4cout, %edi
movl %edx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
movslq -44(%rbp), %rax
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq -128(%rbp), %rdi
callq hipEventCreate
leaq -80(%rbp), %rdi
callq hipEventCreate
movq -128(%rbp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph43.preheader
xorl %ecx, %ecx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph43
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %r14d
incq %rcx
cmpq %rcx, %rax
jne .LBB1_5
.LBB1_6: # %._crit_edge44
cvtsi2ss %r14d, %xmm1
cvtsi2ss %eax, %xmm0
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp) # 4-byte Spill
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -80(%rbp), %rdi
callq hipEventSynchronize
movl $0, -52(%rbp)
movq -128(%rbp), %rsi
movq -80(%rbp), %rdx
leaq -52(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -52(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl -44(%rbp), %eax
shll $2, %eax
movslq %eax, %r14
leaq -64(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movq -64(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movslq %ebx, %rsi
shlq $2, %rsi
leaq -120(%rbp), %rdi
callq hipMalloc
movl -44(%rbp), %eax
movl %eax, -48(%rbp) # 4-byte Spill
leaq -112(%rbp), %rdi
callq hipEventCreate
leaq -72(%rbp), %rdi
callq hipEventCreate
movq -112(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $2, -44(%rbp)
jl .LBB1_11
# %bb.7:
movabsq $4294967296, %r14 # imm = 0x100000000
orq %r14, %rbx
incq %r14
leaq -184(%rbp), %r13
leaq -176(%rbp), %r15
leaq -160(%rbp), %r12
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_8 Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movl %eax, -44(%rbp)
movq -64(%rbp), %rdi
movq -120(%rbp), %rsi
movslq %eax, %rdx
shlq $2, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, -44(%rbp)
jle .LBB1_11
.LBB1_8: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_8 Depth=1
movq -64(%rbp), %rax
movq -120(%rbp), %rcx
movl -44(%rbp), %edx
movq %rax, -216(%rbp)
movq %rcx, -208(%rbp)
movl %edx, -100(%rbp)
leaq -216(%rbp), %rax
movq %rax, -160(%rbp)
leaq -208(%rbp), %rax
movq %rax, -152(%rbp)
leaq -100(%rbp), %rax
movq %rax, -144(%rbp)
leaq -96(%rbp), %rdi
leaq -200(%rbp), %rsi
movq %r13, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq -96(%rbp), %rsi
movl -88(%rbp), %edx
movq -200(%rbp), %rcx
movl -192(%rbp), %r8d
movl $_Z3sumPiS_i, %edi
movq %r12, %r9
pushq -176(%rbp)
pushq -184(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_10
.LBB1_11: # %._crit_edge48
movq -72(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -72(%rbp), %rdi
callq hipEventSynchronize
movl $0, -96(%rbp)
movq -112(%rbp), %rsi
movq -72(%rbp), %rdx
leaq -96(%rbp), %rdi
callq hipEventElapsedTime
movl -48(%rbp), %eax # 4-byte Reload
movl %eax, -44(%rbp)
movq -64(%rbp), %rsi
leaq -160(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -160(%rbp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cvtsi2ssl -160(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
cmpb $0, 56(%rbx)
je .LBB1_18
# %bb.17:
movzbl 67(%rbx), %ecx
jmp .LBB1_19
.LBB1_18:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -96(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33
cmpb $0, 56(%rbx)
je .LBB1_22
# %bb.21:
movzbl 67(%rbx), %ecx
jmp .LBB1_23
.LBB1_22:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -168(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_24:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiS_i,@object # @_Z3sumPiS_i
.section .rodata,"a",@progbits
.globl _Z3sumPiS_i
.p2align 3, 0x0
_Z3sumPiS_i:
.quad _Z18__device_stub__sumPiS_i
.size _Z3sumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the no of elements:"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nSequential Processing:"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nSum="
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nMean="
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nSequential time="
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Mean="
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Parallel time="
.size .L.str.7, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPiS_i"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ComputeInternalEnergy_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Eneint, float *Bx, float *By, float *Bz, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid >= size)
return;
// compute internal energy
Eneint[igrid] = Etot[igrid] - 0.5*(Vx[igrid]*Vx[igrid] + Vy[igrid]*Vy[igrid] + Vz[igrid]*Vz[igrid]) -
0.5*(Bx[igrid]*Bx[igrid] + By[igrid]*By[igrid] + Bz[igrid]*Bz[igrid])/Rho[igrid];
} | code for sm_80
Function : _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R0, R3, 0x40, R0 ; /* 0x0000004003007824 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R5, 0xa000, R0 ; /* 0x0000a00005007824 */
/* 0x002fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x1a8], PT ; /* 0x00006a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R17, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0211 */
/*00b0*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x0000a2000c1e1900 */
/*00c0*/ IMAD.WIDE R8, R0, R17, c[0x0][0x198] ; /* 0x0000660000087625 */
/* 0x000fc800078e0211 */
/*00d0*/ IMAD.WIDE R4, R0.reuse, R17.reuse, c[0x0][0x190] ; /* 0x0000640000047625 */
/* 0x0c0fe200078e0211 */
/*00e0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0004e6000c1e1900 */
/*00f0*/ IMAD.WIDE R18, R0.reuse, R17.reuse, c[0x0][0x1a0] ; /* 0x0000680000127625 */
/* 0x0c0fe200078e0211 */
/*0100*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x00032a000c1e1900 */
/*0110*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1900 */
/*0120*/ IMAD.WIDE R14, R0, R17, c[0x0][0x170] ; /* 0x00005c00000e7625 */
/* 0x000fc800078e0211 */
/*0130*/ IMAD.WIDE R12, R0.reuse, R17.reuse, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x0c0fe200078e0211 */
/*0140*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000f66000c1e1900 */
/*0150*/ IMAD.WIDE R6, R0.reuse, R17.reuse, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x0c0fe200078e0211 */
/*0160*/ LDG.E R3, [R12.64] ; /* 0x000000040c037981 */
/* 0x001f66000c1e1900 */
/*0170*/ IMAD.WIDE R16, R0, R17, c[0x0][0x178] ; /* 0x00005e0000107625 */
/* 0x000fe200078e0211 */
/*0180*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000168000c1e1900 */
/*0190*/ LDG.E R2, [R16.64] ; /* 0x0000000410027981 */
/* 0x000f62000c1e1900 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x002fe200078e00ff */
/*01b0*/ BSSY B0, 0x3a0 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*01c0*/ F2F.F64.F32 R8, R22 ; /* 0x0000001600087310 */
/* 0x004e620000201800 */
/*01d0*/ FMUL R21, R21, R21 ; /* 0x0000001515157220 */
/* 0x008fc80000400000 */
/*01e0*/ FFMA R21, R20, R20, R21 ; /* 0x0000001414157223 */
/* 0x010fc80000000015 */
/*01f0*/ FFMA R21, R18, R18, R21 ; /* 0x0000001212157223 */
/* 0x020fe20000000015 */
/*0200*/ MUFU.RCP64H R5, R9 ; /* 0x0000000900057308 */
/* 0x002e620000001800 */
/*0210*/ FMUL R10, R10, R10 ; /* 0x0000000a0a0a7220 */
/* 0x000fce0000400000 */
/*0220*/ F2F.F64.F32 R6, R21 ; /* 0x0000001500067310 */
/* 0x001e220000201800 */
/*0230*/ FFMA R3, R3, R3, R10 ; /* 0x0000000303037223 */
/* 0x000fe2000000000a */
/*0240*/ DFMA R14, -R8, R4, 1 ; /* 0x3ff00000080e742b */
/* 0x002e460000000104 */
/*0250*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc60000000003 */
/*0260*/ F2F.F64.F32 R10, R11 ; /* 0x0000000b000a7310 */
/* 0x000fe20000201800 */
/*0270*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x002e48000000000e */
/*0280*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001fc80000000000 */
/*0290*/ DFMA R4, R4, R14, R4 ; /* 0x0000000e0404722b */
/* 0x002e0c0000000004 */
/*02a0*/ DFMA R12, -R8, R4, 1 ; /* 0x3ff00000080c742b */
/* 0x001e220000000104 */
/*02b0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*02c0*/ DFMA R4, R4, R12, R4 ; /* 0x0000000c0404722b */
/* 0x001e0c0000000004 */
/*02d0*/ DMUL R12, R6, R4 ; /* 0x00000004060c7228 */
/* 0x001e0c0000000000 */
/*02e0*/ DFMA R14, -R8, R12, R6 ; /* 0x0000000c080e722b */
/* 0x001e0c0000000106 */
/*02f0*/ DFMA R12, R4, R14, R12 ; /* 0x0000000e040c722b */
/* 0x001064000000000c */
/*0300*/ F2F.F64.F32 R4, R3 ; /* 0x0000000300047310 */
/* 0x001e300000201800 */
/*0310*/ FFMA R2, RZ, R9, R13 ; /* 0x00000009ff027223 */
/* 0x002fca000000000d */
/*0320*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fe20003f04200 */
/*0330*/ DFMA R4, R4, -0.5, R10 ; /* 0xbfe000000404782b */
/* 0x001058000000000a */
/*0340*/ @P0 BRA P1, 0x390 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0350*/ MOV R12, 0x370 ; /* 0x00000370000c7802 */
/* 0x003fe40000000f00 */
/*0360*/ CALL.REL.NOINC 0x400 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0012 */
/*0380*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0013 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*03a0*/ DADD R4, R4, -R12 ; /* 0x0000000004047229 */
/* 0x000e22000000080c */
/*03b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x188] ; /* 0x0000620000027625 */
/* 0x000fca00078e0203 */
/*03d0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*03e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0410*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0420*/ LOP3.LUT R2, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09027812 */
/* 0x000fe200078ec0ff */
/*0430*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0440*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0450*/ BSSY B1, 0x9a0 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0460*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0470*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0480*/ LOP3.LUT R13, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070d7812 */
/* 0x000fc400078ec0ff */
/*0490*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x000fc600078ec0ff */
/*04a0*/ @!P0 DMUL R2, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008028828 */
/* 0x000e220000000000 */
/*04b0*/ ISETP.GE.U32.AND P1, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fc60003f26070 */
/*04c0*/ @!P2 LOP3.LUT R10, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090aa812 */
/* 0x000fe200078ec0ff */
/*04d0*/ @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff16a224 */
/* 0x000fe200078e00ff */
/*04e0*/ MUFU.RCP64H R17, R3 ; /* 0x0000000300117308 */
/* 0x001e220000001800 */
/*04f0*/ SEL R11, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e0b7807 */
/* 0x040fe40004800000 */
/*0500*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R10, PT ; /* 0x0000000a0d00a20c */
/* 0x000fe20003f66070 */
/*0510*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0520*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fe400078ef807 */
/*0530*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0540*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef807 */
/*0550*/ @!P2 LOP3.LUT R23, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f17a812 */
/* 0x000fe200078efcff */
/*0560*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e220000000802 */
/*0570*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0580*/ @!P2 DFMA R10, R10, 2, -R22 ; /* 0x400000000a0aa82b */
/* 0x0003e40000000816 */
/*0590*/ IMAD.MOV.U32 R22, RZ, RZ, R18 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0012 */
/*05a0*/ @!P0 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003168812 */
/* 0x000fe200078ec0ff */
/*05b0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e060000000014 */
/*05c0*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x001e220000000010 */
/*05e0*/ @!P2 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0fa812 */
/* 0x000fca00078ec0ff */
/*05f0*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e0c0000000802 */
/*0600*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x0010640000000010 */
/*0610*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x001fc80007ffe0ff */
/*0620*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0630*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x002e060000000000 */
/*0640*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fc60000704470 */
/*0650*/ DFMA R20, R18, -R2, R10 ; /* 0x800000021214722b */
/* 0x001e0c000000000a */
/*0660*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010480000000012 */
/*0670*/ @P0 BRA 0x840 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x003fc800078ec0ff */
/*0690*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*06a0*/ IMAD.IADD R6, R13, 0x1, -R18 ; /* 0x000000010d067824 */
/* 0x000fc600078e0a12 */
/*06b0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*06c0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*06d0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*06e0*/ IMAD.IADD R13, R6, 0x1, -R13 ; /* 0x00000001060d7824 */
/* 0x000fe400078e0a0d */
/*06f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0700*/ IADD3 R7, R13, 0x7fe00000, RZ ; /* 0x7fe000000d077810 */
/* 0x000fcc0007ffe0ff */
/*0710*/ DMUL R18, R16, R6 ; /* 0x0000000610127228 */
/* 0x000e140000000000 */
/*0720*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0730*/ @P0 BRA 0x990 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0740*/ DFMA R2, R16, -R2, R10 ; /* 0x800000021002722b */
/* 0x000e22000000000a */
/*0750*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0760*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0770*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0780*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0790*/ @!P0 BRA 0x990 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*07a0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*07b0*/ DMUL.RP R6, R16, R6 ; /* 0x0000000610067228 */
/* 0x000e220000008000 */
/*07c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*07d0*/ IADD3 R13, -R13, -0x43300000, RZ ; /* 0xbcd000000d0d7810 */
/* 0x000fca0007ffe1ff */
/*07e0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*07f0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fce00078e3cff */
/*0800*/ FSETP.NEU.AND P0, PT, |R3|, R13, PT ; /* 0x0000000d0300720b */
/* 0x002fc80003f0d200 */
/*0810*/ FSEL R18, R6, R18, !P0 ; /* 0x0000001206127208 */
/* 0x000fe40004000000 */
/*0820*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0830*/ BRA 0x990 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0840*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0850*/ @P0 BRA 0x970 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0860*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0870*/ @P0 BRA 0x940 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0880*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0890*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x000fe400078e00ff */
/*08a0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*08b0*/ @!P0 BRA 0x990 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*08d0*/ LOP3.LUT R19, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007137812 */
/* 0x000fe400078e4809 */
/*08e0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*08f0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0900*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0910*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0920*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0930*/ BRA 0x990 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x000fe200078efcff */
/*0950*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0960*/ BRA 0x990 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x000fe200078efcff */
/*0980*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0990*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fc800078e00ff */
/*09b0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff6400c007950 */
/* 0x000fea0003c3ffff */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeInternalEnergy_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Eneint, float *Bx, float *By, float *Bz, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid >= size)
return;
// compute internal energy
Eneint[igrid] = Etot[igrid] - 0.5*(Vx[igrid]*Vx[igrid] + Vy[igrid]*Vy[igrid] + Vz[igrid]*Vz[igrid]) -
0.5*(Bx[igrid]*Bx[igrid] + By[igrid]*By[igrid] + Bz[igrid]*Bz[igrid])/Rho[igrid];
} | .file "tmpxft_00101241_00000000-6_ComputeInternalEnergy_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i
.type _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i, @function
_Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i, .-_Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i
.globl _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.type _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, @function
_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, .-_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeInternalEnergy_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Eneint, float *Bx, float *By, float *Bz, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid >= size)
return;
// compute internal energy
Eneint[igrid] = Etot[igrid] - 0.5*(Vx[igrid]*Vx[igrid] + Vy[igrid]*Vy[igrid] + Vz[igrid]*Vz[igrid]) -
0.5*(Bx[igrid]*Bx[igrid] + By[igrid]*By[igrid] + Bz[igrid]*Bz[igrid])/Rho[igrid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeInternalEnergy_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Eneint, float *Bx, float *By, float *Bz, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid >= size)
return;
// compute internal energy
Eneint[igrid] = Etot[igrid] - 0.5*(Vx[igrid]*Vx[igrid] + Vy[igrid]*Vy[igrid] + Vz[igrid]*Vz[igrid]) -
0.5*(Bx[igrid]*Bx[igrid] + By[igrid]*By[igrid] + Bz[igrid]*Bz[igrid])/Rho[igrid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeInternalEnergy_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Eneint, float *Bx, float *By, float *Bz, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid >= size)
return;
// compute internal energy
Eneint[igrid] = Etot[igrid] - 0.5*(Vx[igrid]*Vx[igrid] + Vy[igrid]*Vy[igrid] + Vz[igrid]*Vz[igrid]) -
0.5*(Bx[igrid]*Bx[igrid] + By[igrid]*By[igrid] + Bz[igrid]*Bz[igrid])/Rho[igrid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.globl _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.p2align 8
.type _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i,@function
_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i:
s_load_b32 s2, s[0:1], 0x48
s_lshl_b32 s3, s14, 6
s_mul_i32 s15, s15, 0xa000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s3, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x40
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_load_b256 s[8:15], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(3)
v_mul_f32_e32 v2, v6, v6
v_add_co_u32 v6, vcc_lo, s12, v0
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v4, v4
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v2, v5, v5
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v7
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
global_load_b32 v14, v[6:7], off
v_add_co_u32 v6, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v1, vcc_lo
global_load_b32 v15, v[8:9], off
v_add_co_u32 v8, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
global_load_b32 v16, v[6:7], off
global_load_b32 v17, v[8:9], off
v_mul_f64 v[2:3], v[2:3], -0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_waitcnt vmcnt(3)
v_mul_f32_e32 v14, v14, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v14, v15, v15
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v16, v16
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v17
v_cvt_f64_f32_e32 v[14:15], v14
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[8:9], v[14:15], -0.5, v[10:11]
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[8:9], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 76
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, .Lfunc_end0-_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 76
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeInternalEnergy_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Eneint, float *Bx, float *By, float *Bz, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid >= size)
return;
// compute internal energy
Eneint[igrid] = Etot[igrid] - 0.5*(Vx[igrid]*Vx[igrid] + Vy[igrid]*Vy[igrid] + Vz[igrid]*Vz[igrid]) -
0.5*(Bx[igrid]*Bx[igrid] + By[igrid]*By[igrid] + Bz[igrid]*Bz[igrid])/Rho[igrid];
} | .text
.file "ComputeInternalEnergy_kernel.hip"
.globl _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i # -- Begin function _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i,@function
_Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i: # @_Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, .Lfunc_end0-_Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i,@object # @_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i:
.quad _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.size _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R0, R3, 0x40, R0 ; /* 0x0000004003007824 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R5, 0xa000, R0 ; /* 0x0000a00005007824 */
/* 0x002fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x1a8], PT ; /* 0x00006a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R17, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0211 */
/*00b0*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x0000a2000c1e1900 */
/*00c0*/ IMAD.WIDE R8, R0, R17, c[0x0][0x198] ; /* 0x0000660000087625 */
/* 0x000fc800078e0211 */
/*00d0*/ IMAD.WIDE R4, R0.reuse, R17.reuse, c[0x0][0x190] ; /* 0x0000640000047625 */
/* 0x0c0fe200078e0211 */
/*00e0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0004e6000c1e1900 */
/*00f0*/ IMAD.WIDE R18, R0.reuse, R17.reuse, c[0x0][0x1a0] ; /* 0x0000680000127625 */
/* 0x0c0fe200078e0211 */
/*0100*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x00032a000c1e1900 */
/*0110*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1900 */
/*0120*/ IMAD.WIDE R14, R0, R17, c[0x0][0x170] ; /* 0x00005c00000e7625 */
/* 0x000fc800078e0211 */
/*0130*/ IMAD.WIDE R12, R0.reuse, R17.reuse, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x0c0fe200078e0211 */
/*0140*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000f66000c1e1900 */
/*0150*/ IMAD.WIDE R6, R0.reuse, R17.reuse, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x0c0fe200078e0211 */
/*0160*/ LDG.E R3, [R12.64] ; /* 0x000000040c037981 */
/* 0x001f66000c1e1900 */
/*0170*/ IMAD.WIDE R16, R0, R17, c[0x0][0x178] ; /* 0x00005e0000107625 */
/* 0x000fe200078e0211 */
/*0180*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000168000c1e1900 */
/*0190*/ LDG.E R2, [R16.64] ; /* 0x0000000410027981 */
/* 0x000f62000c1e1900 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x002fe200078e00ff */
/*01b0*/ BSSY B0, 0x3a0 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*01c0*/ F2F.F64.F32 R8, R22 ; /* 0x0000001600087310 */
/* 0x004e620000201800 */
/*01d0*/ FMUL R21, R21, R21 ; /* 0x0000001515157220 */
/* 0x008fc80000400000 */
/*01e0*/ FFMA R21, R20, R20, R21 ; /* 0x0000001414157223 */
/* 0x010fc80000000015 */
/*01f0*/ FFMA R21, R18, R18, R21 ; /* 0x0000001212157223 */
/* 0x020fe20000000015 */
/*0200*/ MUFU.RCP64H R5, R9 ; /* 0x0000000900057308 */
/* 0x002e620000001800 */
/*0210*/ FMUL R10, R10, R10 ; /* 0x0000000a0a0a7220 */
/* 0x000fce0000400000 */
/*0220*/ F2F.F64.F32 R6, R21 ; /* 0x0000001500067310 */
/* 0x001e220000201800 */
/*0230*/ FFMA R3, R3, R3, R10 ; /* 0x0000000303037223 */
/* 0x000fe2000000000a */
/*0240*/ DFMA R14, -R8, R4, 1 ; /* 0x3ff00000080e742b */
/* 0x002e460000000104 */
/*0250*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc60000000003 */
/*0260*/ F2F.F64.F32 R10, R11 ; /* 0x0000000b000a7310 */
/* 0x000fe20000201800 */
/*0270*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x002e48000000000e */
/*0280*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001fc80000000000 */
/*0290*/ DFMA R4, R4, R14, R4 ; /* 0x0000000e0404722b */
/* 0x002e0c0000000004 */
/*02a0*/ DFMA R12, -R8, R4, 1 ; /* 0x3ff00000080c742b */
/* 0x001e220000000104 */
/*02b0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*02c0*/ DFMA R4, R4, R12, R4 ; /* 0x0000000c0404722b */
/* 0x001e0c0000000004 */
/*02d0*/ DMUL R12, R6, R4 ; /* 0x00000004060c7228 */
/* 0x001e0c0000000000 */
/*02e0*/ DFMA R14, -R8, R12, R6 ; /* 0x0000000c080e722b */
/* 0x001e0c0000000106 */
/*02f0*/ DFMA R12, R4, R14, R12 ; /* 0x0000000e040c722b */
/* 0x001064000000000c */
/*0300*/ F2F.F64.F32 R4, R3 ; /* 0x0000000300047310 */
/* 0x001e300000201800 */
/*0310*/ FFMA R2, RZ, R9, R13 ; /* 0x00000009ff027223 */
/* 0x002fca000000000d */
/*0320*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fe20003f04200 */
/*0330*/ DFMA R4, R4, -0.5, R10 ; /* 0xbfe000000404782b */
/* 0x001058000000000a */
/*0340*/ @P0 BRA P1, 0x390 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0350*/ MOV R12, 0x370 ; /* 0x00000370000c7802 */
/* 0x003fe40000000f00 */
/*0360*/ CALL.REL.NOINC 0x400 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0012 */
/*0380*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0013 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*03a0*/ DADD R4, R4, -R12 ; /* 0x0000000004047229 */
/* 0x000e22000000080c */
/*03b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x188] ; /* 0x0000620000027625 */
/* 0x000fca00078e0203 */
/*03d0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*03e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0410*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0420*/ LOP3.LUT R2, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09027812 */
/* 0x000fe200078ec0ff */
/*0430*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0440*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0450*/ BSSY B1, 0x9a0 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0460*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0470*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0480*/ LOP3.LUT R13, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070d7812 */
/* 0x000fc400078ec0ff */
/*0490*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x000fc600078ec0ff */
/*04a0*/ @!P0 DMUL R2, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008028828 */
/* 0x000e220000000000 */
/*04b0*/ ISETP.GE.U32.AND P1, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fc60003f26070 */
/*04c0*/ @!P2 LOP3.LUT R10, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090aa812 */
/* 0x000fe200078ec0ff */
/*04d0*/ @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff16a224 */
/* 0x000fe200078e00ff */
/*04e0*/ MUFU.RCP64H R17, R3 ; /* 0x0000000300117308 */
/* 0x001e220000001800 */
/*04f0*/ SEL R11, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e0b7807 */
/* 0x040fe40004800000 */
/*0500*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R10, PT ; /* 0x0000000a0d00a20c */
/* 0x000fe20003f66070 */
/*0510*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0520*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fe400078ef807 */
/*0530*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0540*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef807 */
/*0550*/ @!P2 LOP3.LUT R23, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f17a812 */
/* 0x000fe200078efcff */
/*0560*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e220000000802 */
/*0570*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0580*/ @!P2 DFMA R10, R10, 2, -R22 ; /* 0x400000000a0aa82b */
/* 0x0003e40000000816 */
/*0590*/ IMAD.MOV.U32 R22, RZ, RZ, R18 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0012 */
/*05a0*/ @!P0 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003168812 */
/* 0x000fe200078ec0ff */
/*05b0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e060000000014 */
/*05c0*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x001e220000000010 */
/*05e0*/ @!P2 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0fa812 */
/* 0x000fca00078ec0ff */
/*05f0*/ DFMA R20, R16, -R2, 1 ; /* 0x3ff000001014742b */
/* 0x001e0c0000000802 */
/*0600*/ DFMA R16, R16, R20, R16 ; /* 0x000000141010722b */
/* 0x0010640000000010 */
/*0610*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x001fc80007ffe0ff */
/*0620*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0630*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x002e060000000000 */
/*0640*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fc60000704470 */
/*0650*/ DFMA R20, R18, -R2, R10 ; /* 0x800000021214722b */
/* 0x001e0c000000000a */
/*0660*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010480000000012 */
/*0670*/ @P0 BRA 0x840 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x003fc800078ec0ff */
/*0690*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*06a0*/ IMAD.IADD R6, R13, 0x1, -R18 ; /* 0x000000010d067824 */
/* 0x000fc600078e0a12 */
/*06b0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*06c0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*06d0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*06e0*/ IMAD.IADD R13, R6, 0x1, -R13 ; /* 0x00000001060d7824 */
/* 0x000fe400078e0a0d */
/*06f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0700*/ IADD3 R7, R13, 0x7fe00000, RZ ; /* 0x7fe000000d077810 */
/* 0x000fcc0007ffe0ff */
/*0710*/ DMUL R18, R16, R6 ; /* 0x0000000610127228 */
/* 0x000e140000000000 */
/*0720*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0730*/ @P0 BRA 0x990 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0740*/ DFMA R2, R16, -R2, R10 ; /* 0x800000021002722b */
/* 0x000e22000000000a */
/*0750*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0760*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0770*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0780*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0790*/ @!P0 BRA 0x990 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*07a0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*07b0*/ DMUL.RP R6, R16, R6 ; /* 0x0000000610067228 */
/* 0x000e220000008000 */
/*07c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*07d0*/ IADD3 R13, -R13, -0x43300000, RZ ; /* 0xbcd000000d0d7810 */
/* 0x000fca0007ffe1ff */
/*07e0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*07f0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fce00078e3cff */
/*0800*/ FSETP.NEU.AND P0, PT, |R3|, R13, PT ; /* 0x0000000d0300720b */
/* 0x002fc80003f0d200 */
/*0810*/ FSEL R18, R6, R18, !P0 ; /* 0x0000001206127208 */
/* 0x000fe40004000000 */
/*0820*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0830*/ BRA 0x990 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0840*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0850*/ @P0 BRA 0x970 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0860*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0870*/ @P0 BRA 0x940 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0880*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0890*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x000fe400078e00ff */
/*08a0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*08b0*/ @!P0 BRA 0x990 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*08d0*/ LOP3.LUT R19, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007137812 */
/* 0x000fe400078e4809 */
/*08e0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*08f0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0900*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0910*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0920*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0930*/ BRA 0x990 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x000fe200078efcff */
/*0950*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0960*/ BRA 0x990 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x000fe200078efcff */
/*0980*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0990*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fc800078e00ff */
/*09b0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff6400c007950 */
/* 0x000fea0003c3ffff */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.globl _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.p2align 8
.type _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i,@function
_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i:
s_load_b32 s2, s[0:1], 0x48
s_lshl_b32 s3, s14, 6
s_mul_i32 s15, s15, 0xa000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s3, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x40
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_load_b256 s[8:15], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(3)
v_mul_f32_e32 v2, v6, v6
v_add_co_u32 v6, vcc_lo, s12, v0
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v4, v4
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v2, v5, v5
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v7
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
global_load_b32 v14, v[6:7], off
v_add_co_u32 v6, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v1, vcc_lo
global_load_b32 v15, v[8:9], off
v_add_co_u32 v8, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
global_load_b32 v16, v[6:7], off
global_load_b32 v17, v[8:9], off
v_mul_f64 v[2:3], v[2:3], -0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_waitcnt vmcnt(3)
v_mul_f32_e32 v14, v14, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v14, v15, v15
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v16, v16
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v17
v_cvt_f64_f32_e32 v[14:15], v14
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[8:9], v[14:15], -0.5, v[10:11]
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[8:9], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 76
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, .Lfunc_end0-_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 76
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00101241_00000000-6_ComputeInternalEnergy_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i
.type _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i, @function
_Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i, .-_Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i
.globl _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.type _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, @function
_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z65__device_stub__Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_iPfS_S_S_S_S_S_S_S_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, .-_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ComputeInternalEnergy_kernel.hip"
.globl _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i # -- Begin function _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.p2align 4, 0x90
.type _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i,@function
_Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i: # @_Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, .Lfunc_end0-_Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i,@object # @_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.p2align 3, 0x0
_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i:
.quad _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.size _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28ComputeInternalEnergy_kernelPfS_S_S_S_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*--------------------------------------------------------------------------------------------------*/
/* */
/* Alberto Quesada Aranda */
/* Åbo Akademi University */
/* Advanced Computer Graphics and Graphics Hardware */
/* */
/* Two-Point angula correlation code */
/* Input: two list of galaxies */
/* Output: .txt file with the data for generate the histogram */
/* */
/* Base code taken from: https://github.com/djbard/ccogs/tree/master/angular_correlation */
/* */
/*--------------------------------------------------------------------------------------------------*/
#include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include<unistd.h>
#include<cuda_runtime.h>
#include<time.h>
using namespace std;
#define SUBMATRIX_SIZE 16384 // parallel threads: 32 blocks * 512 threads/block = 16384 threads
#define DEFAULT_NBINS 256 // num of bins for the histogram
#define arcm_to_rad 1/3437.7468 // (1/60)*(pi/180), convert from arcm to rad
#define conv_angle 57.2957795; // 180/pi, convert from rad to degrees
// variables for calculate the execution time
static clock_t start_time;
static double elapsed;
/*------------------------------------------------------------------
Kernel to calculate angular distances
-------------------------------------------------------------------*/
__global__ void distance(volatile float *a0, volatile float *d0, volatile float *a1, volatile float *d1, int xind, int yind, int max_xind, int max_yind, volatile int *dev_hist, float hist_min, float hist_max, int nbins, float bin_width, bool two_different_files=1) {
int idx = blockIdx.x * blockDim.x + threadIdx.x; // idx is the thread id, it must range to 32blocks * 512threads/block = 16384 threads
idx += xind; // allow the thread to know which submatrix has to calculate
// printf("%d %d %d\n", blockIdx.x, threadIdx.x, blockDim.x);
// blockIdx.x [0-31]
// blockDim.x 512
// threadIdx.x [0-511]
__shared__ int shared_hist[DEFAULT_NBINS+2]; // shared vector for save the results within a block of threads
// initialize it only once in each block
if(threadIdx.x==0)
{
for (int i=0;i<nbins+2;i++)
shared_hist[i] = 0;
}
// before starting the calculations we need to be sure that the shared_hist is initialized; if not, we take the risk
// of loss calculations because we don't know the order in which the threads are executed and is possible that a thread
// performs the calculations and write the results in shared_hist before the thread 0 has initialized it.
__syncthreads();
// if NUM_GALAXIES0 % SUBMATRIX_SIZE != 0 in the last submatrix we will have more threads than needed calculations, therefore
// we won't perform calculations with those threads.
if (idx<max_xind) {
float dist, alpha1, delta1, a_diff;
float alpha0 = a0[idx];
float delta0 = d0[idx];
bool do_calc = 1;
int bin_index = 0;
// each kernel will calculate the angle between one galaxy of the first input data (idx) and all the galaxies within [yind-ymax]
int ymax = yind + SUBMATRIX_SIZE; // ymax will be the end of the submatrix that we are calculating of the second galaxies input
// we have to take care and if ymax > NUM_GALAXIES1, we stop the calculations bucle at that point
if (ymax>max_yind)
ymax = max_yind;
// we will perform the same calculation between input0[idx] and every input1[] (range [yind-ymax])
for(int i=yind; i<ymax; i++)
{
// if the two input files are different (DR case) we have to perform all N*N calculations
if (two_different_files) {
do_calc = 1;
}
// if the two input files are the same (DD, RR cases) we have to perform N*(N-1)/2 calculations
else {
if (xind != yind) {
do_calc = 1;
}
else {
if(idx > i)
do_calc=1;
else
do_calc=0;
}
}
if (do_calc)
{
alpha1 = a1[i];
delta1 = d1[i];
a_diff = alpha0 - alpha1;
dist = acos(sin(delta0)*sin(delta1) + cos(alpha0)*cos(alpha1)*cos(a_diff));
dist *= conv_angle; // convert from rad to degrees
// check in which bin we have to include the angle calculated
if(dist < hist_min) // underflow
bin_index = 0;
else if(dist >= hist_max) // overflow
bin_index = nbins + 1;
else {
bin_index = int((dist-hist_min)/bin_width) + 1;
}
// more than one thread could try to write its result in the shared_hist at the same time and in the same memory
// location. We need an atomic operation for prevent the loss of data
atomicAdd(&shared_hist[bin_index],1); // increment by one the corresponding histogram bin
}
}
}
// before copy the results of each block to the global histogram we have to be sure that all the threads within the block have
// ended its calculations
__syncthreads();
// only one thread (0) will write the results of the block to which it belongs to the global histogram
// for avoid the need of another atomic operation, our global histogram save the result of each block successively :
// [block[0], block[1] .... block [31]]
if(threadIdx.x==0)
{
for(int i=0;i<nbins+2;i++)
dev_hist[i+(blockIdx.x*(nbins+2))]=shared_hist[i];
}
}
/*------------------------------------------------------------------
Calculations and call to kernel
-------------------------------------------------------------------*/
int calc(FILE *infile0, FILE *infile1, FILE *outfile, int nbins, float hist_lower_range, float hist_upper_range, float hist_bin_width, bool two_different_files){
//d_ means device -> GPU, h_ means host -> CPU
float *d_alpha0, *d_delta0, *d_alpha1, *d_delta1;
float *h_alpha0, *h_delta0, *h_alpha1, *h_delta1;
int NUM_GALAXIES0, NUM_GALAXIES1;
// reading the data of the input files
// first we read the number of galaxies of each file
fscanf(infile0, "%d", &NUM_GALAXIES0);
fscanf(infile1, "%d", &NUM_GALAXIES1);
// calculate the size of the array needed for save in memory all the galaxies
int size_of_galaxy_array0 = NUM_GALAXIES0 * sizeof(float);
int size_of_galaxy_array1 = NUM_GALAXIES1 * sizeof(float);
printf("SIZE 0 # GALAXIES: %d\n",NUM_GALAXIES0);
printf("SIZE 1 # GALAXIES: %d\n",NUM_GALAXIES1);
// allocate space for the galaxies data in global memory
h_alpha0 = (float*)malloc(size_of_galaxy_array0);
h_delta0 = (float*)malloc(size_of_galaxy_array0);
h_alpha1 = (float*)malloc(size_of_galaxy_array1);
h_delta1 = (float*)malloc(size_of_galaxy_array1);
float temp0, temp1;
// reading and saving the galaxies data in radians
for(int i=0; i<NUM_GALAXIES0; i++)
{
fscanf(infile0, "%f %f", &temp0, &temp1);
h_alpha0[i] = temp0 * arcm_to_rad;
h_delta0[i] = temp1 * arcm_to_rad;
}
for(int i=0; i<NUM_GALAXIES1; i++)
{
fscanf(infile1, "%f %f", &temp0, &temp1);
h_alpha1[i] = temp0 * arcm_to_rad;
h_delta1[i] = temp1 * arcm_to_rad;
}
// defining dimensions for the grid and block
dim3 grid, block;
grid.x = 8192/(DEFAULT_NBINS); // number of blocks = 32
block.x = SUBMATRIX_SIZE/grid.x; // number of threads/block = 512
// allocating the histograms
/* I will need 3 arrays for the histograms:
- hist : for each submatrix, save the results of each thread block seccuentially (global memory)
- dev_hist : the same as hist, but in GPU memory
- hist_array : save the global result of all the submatrix in global memory
*/
int *hist, *dev_hist;
int size_hist = grid.x * (nbins+2); // I use +2, one for underflow and other for overflow
int size_hist_bytes = size_hist*sizeof(int);
// allocating and initializing to 0 hist in global mem
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
// allocating and initializing to 0 dev_hist in GPU mem
cudaMalloc((void **) &dev_hist, (size_hist_bytes));
cudaMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
// allocating and initializing to 0 the array for the final histogram (the sum of each submatrix partial result)
int hist_array_size = (nbins+2) * sizeof(unsigned long);
hist_array = (unsigned long*)malloc(hist_array_size);
memset(hist_array,0,hist_array_size);
// allocating memory in GPU for save the galaxies data
cudaMalloc((void **) &d_alpha0, size_of_galaxy_array0 );
cudaMalloc((void **) &d_delta0, size_of_galaxy_array0 );
cudaMalloc((void **) &d_alpha1, size_of_galaxy_array1 );
cudaMalloc((void **) &d_delta1, size_of_galaxy_array1 );
// check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate enough memory in GPU\n");
return 1;
}
// initialize array to all 0's
/*cudaMemset(d_alpha0,0,size_of_galaxy_array0);
cudaMemset(d_delta0,0,size_of_galaxy_array0);
cudaMemset(d_alpha1,0,size_of_galaxy_array1);
cudaMemset(d_delta1,0,size_of_galaxy_array1);*/
// copy galaxies data to GPU
cudaMemcpy(d_alpha0, h_alpha0, size_of_galaxy_array0, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta0, h_delta0, size_of_galaxy_array0, cudaMemcpyHostToDevice );
cudaMemcpy(d_alpha1, h_alpha1, size_of_galaxy_array1, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta1, h_delta1, size_of_galaxy_array1, cudaMemcpyHostToDevice );
int x, y;
int num_submatrices_x = NUM_GALAXIES0 / SUBMATRIX_SIZE;
int num_submatrices_y = NUM_GALAXIES1 / SUBMATRIX_SIZE;
// if NUM_GALAXIES % SUBMATRIX_SIZE != 0, we will need one submatrix more (not the whole submatrix) for perform all the calculations
if (NUM_GALAXIES0%SUBMATRIX_SIZE != 0) {
num_submatrices_x += 1;
}
if (NUM_GALAXIES1%SUBMATRIX_SIZE != 0) {
num_submatrices_y += 1;
}
int bin_index = 0;
// explanation of the iterations in the documentation
for(int k = 0; k < num_submatrices_y; k++)
{
y = k*SUBMATRIX_SIZE;
int jmax = 0;
// if the two files are the same, then only loop over the upper half of the matrix of operations
if (two_different_files == 0)
jmax = k;
for(int j = jmax; j < num_submatrices_x; j++)
{
x = j*SUBMATRIX_SIZE;
// set the histogram to all zeros each time.
cudaMemset(dev_hist,0,size_hist_bytes);
// call to the kernel
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, NUM_GALAXIES0, NUM_GALAXIES1, dev_hist, hist_lower_range, hist_upper_range, nbins, hist_bin_width, two_different_files);
// copy the results from GPU memory to global mem
cudaMemcpy(hist, dev_hist, size_hist_bytes, cudaMemcpyDeviceToHost);
// add together the results of each block in a single histogram
for(int m=0; m<size_hist; m++)
{
bin_index = m%(nbins+2); // range it to [0-258]
hist_array[bin_index] += hist[m];
}
}
}
unsigned long total = 0;
// write in the output file the range of the bin of the histogram and the number of galaxies included in that range
// start in k = 1 and finish before nbins+1 for avoid the over/underflow
float lo = hist_lower_range;
float hi = 0;
for(int k=1; k<nbins+1; k++)
{
hi = lo + hist_bin_width;
fprintf(outfile, "%.3e %.3e %lu \n",lo,hi,hist_array[k]);
total += hist_array[k];
lo = hi;
}
printf("total: %lu \n", total);
// close opened files
fclose(infile0);
fclose(infile1);
fclose(outfile);
// free global memory
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
// free GPU memory
cudaFree(d_alpha0);
cudaFree(d_delta0);
cudaFree(d_alpha1);
cudaFree(d_delta1);
cudaFree(dev_hist);
return 0;
}
/*------------------------------------------------------------------
MAIN
-------------------------------------------------------------------*/
int main(int argc, char **argv) {
start_time = clock(); // start the timer
int nbins = DEFAULT_NBINS; // 256 bins --> 0-64º --> 64/0.25 = 256
float bin_width = 0.25;
float lower_range = 0.0000001;
float upper_range = nbins * bin_width; // 256 * 0.25 = 64
bool different_files = 1;
if (argc != 3) {
printf("\nMust pass two input files.\n");
exit(1);
}
// opening the input files and creating the output file
FILE *infile0, *infile1, *outfile;
infile0 = fopen(argv[optind],"r");
infile1 = fopen(argv[optind+1],"r");
outfile = fopen("output.txt", "w");
// if the input files are the same (DD, RR) the calculations needed are different from the DR case
if (strcmp(argv[optind],argv[optind+1]) == 0) {
different_files = 0;
printf("Input files are the same!\n");
}
calc(infile0, infile1, outfile, nbins, lower_range, upper_range, bin_width, different_files);
// total time
elapsed = clock() - start_time;
elapsed = elapsed / CLOCKS_PER_SEC;
printf("Execution time: %f \n", elapsed);
return 0;
} | .file "tmpxft_00009041_00000000-6_project.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
.type _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb, @function
_Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb:
.LFB2096:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq 288(%rsp), %rax
movq %rax, 16(%rsp)
movl 304(%rsp), %eax
movb %al, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 4(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8distancePVfS0_S0_S0_iiiiPViffifb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb, .-_Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
.globl _Z8distancePVfS0_S0_S0_iiiiPViffifb
.type _Z8distancePVfS0_S0_S0_iiiiPViffifb, @function
_Z8distancePVfS0_S0_S0_iiiiPViffifb:
.LFB2097:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movzbl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8distancePVfS0_S0_S0_iiiiPViffifb, .-_Z8distancePVfS0_S0_S0_iiiiPViffifb
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "SIZE 0 # GALAXIES: %d\n"
.LC2:
.string "SIZE 1 # GALAXIES: %d\n"
.LC3:
.string "%f %f"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "couldn't allocate enough memory in GPU\n"
.section .rodata.str1.1
.LC6:
.string "%.3e %.3e %lu \n"
.LC7:
.string "total: %lu \n"
.text
.globl _Z4calcP8_IO_FILES0_S0_ifffb
.type _Z4calcP8_IO_FILES0_S0_ifffb, @function
_Z4calcP8_IO_FILES0_S0_ifffb:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 32(%rsp)
movq %rsi, %r14
movq %rsi, 40(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 48(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 52(%rsp)
movss %xmm2, 20(%rsp)
movb %r8b, 75(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rdx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call __isoc23_fscanf@PLT
leaq 124(%rsp), %rdx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 120(%rsp), %ebp
movl 124(%rsp), %eax
leal 0(,%rax,4), %r15d
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 124(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
sall $2, %ebp
movslq %ebp, %rbx
movq %rbx, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 104(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 80(%rsp)
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 88(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, 96(%rsp)
cmpl $0, 120(%rsp)
jle .L12
movl $0, %ebx
leaq 132(%rsp), %r13
leaq 128(%rsp), %r12
leaq .LC3(%rip), %rbp
movq %r15, 24(%rsp)
movq 80(%rsp), %r15
.L13:
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
pxor %xmm0, %xmm0
cvtss2sd 128(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%rbx,4)
pxor %xmm0, %xmm0
cvtss2sd 132(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx,4)
addq $1, %rbx
cmpl %ebx, 120(%rsp)
jg .L13
movq 24(%rsp), %r15
.L12:
cmpl $0, 124(%rsp)
jle .L14
movl $0, %ebx
leaq 132(%rsp), %r13
leaq 128(%rsp), %r12
leaq .LC3(%rip), %rbp
movq %r15, 24(%rsp)
movq 88(%rsp), %r14
movq 96(%rsp), %r15
.L15:
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
pxor %xmm0, %xmm0
cvtss2sd 128(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%rbx,4)
pxor %xmm0, %xmm0
cvtss2sd 132(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx,4)
addq $1, %rbx
cmpl %ebx, 124(%rsp)
jg .L15
movq 24(%rsp), %r15
.L14:
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
movl $512, 188(%rsp)
movl 48(%rsp), %eax
leal 2(%rax), %ebp
movl %ebp, %r13d
sall $5, %r13d
movl %ebp, %r14d
sall $7, %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rcx
movq %r14, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 168(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq 168(%rsp), %rdi
call cudaMemset@PLT
leal 0(,%rbp,8), %eax
cltq
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movq 24(%rsp), %rdx
movq %rdx, %rcx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 136(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 152(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 160(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq 136(%rsp), %rdi
testq %rdi, %rdi
je .L16
cmpq $0, 144(%rsp)
je .L16
cmpq $0, 152(%rsp)
je .L16
cmpq $0, 160(%rsp)
je .L16
cmpq $0, 168(%rsp)
je .L16
movl $1, %ecx
movq 8(%rsp), %rdx
movq 104(%rsp), %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movq 8(%rsp), %rdx
movq 80(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 88(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 96(%rsp), %rsi
movq 160(%rsp), %rdi
call cudaMemcpy@PLT
movl 120(%rsp), %edx
leal 16383(%rdx), %esi
testl %edx, %edx
cmovns %edx, %esi
sarl $14, %esi
movl 124(%rsp), %eax
leal 16383(%rax), %ecx
testl %eax, %eax
cmovns %eax, %ecx
sarl $14, %ecx
andl $16383, %edx
cmpl $1, %edx
sbbl $-1, %esi
movl %esi, 8(%rsp)
andl $16383, %eax
cmpl $1, %eax
sbbl $-1, %ecx
movl %ecx, 76(%rsp)
testl %ecx, %ecx
jle .L21
movl $0, %edx
movzbl 75(%rsp), %eax
movl %eax, 56(%rsp)
jmp .L28
.L16:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L11:
movq 200(%rsp), %rdx
subq %fs:40, %rdx
jne .L41
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $2, %ecx
movq %r14, %rdx
movq 168(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L25
movl $0, %ecx
.L26:
movl %ecx, %eax
cltd
idivl %ebp
movslq %edx, %rdx
movslq (%r12,%rcx,4), %rax
addq %rax, (%rbx,%rdx,8)
addq $1, %rcx
cmpl %ecx, %r13d
jg .L26
.L25:
addl $1, %r15d
cmpl %r15d, 8(%rsp)
je .L42
.L27:
movq %r14, %rdx
movl $0, %esi
movq 168(%rsp), %rdi
call cudaMemset@PLT
movl $32, 176(%rsp)
movl 196(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 188(%rsp), %rdx
movq 176(%rsp), %rdi
movl 184(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L24
subq $8, %rsp
.cfi_def_cfa_offset 280
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 288
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 296
pushq 192(%rsp)
.cfi_def_cfa_offset 304
movl 156(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 312
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 320
movss 68(%rsp), %xmm2
movss 100(%rsp), %xmm1
movss 64(%rsp), %xmm0
movl 72(%rsp), %r9d
movl %r15d, %r8d
sall $14, %r8d
movq 208(%rsp), %rcx
movq 200(%rsp), %rdx
movq 192(%rsp), %rsi
movq 184(%rsp), %rdi
call _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
addq $48, %rsp
.cfi_def_cfa_offset 272
jmp .L24
.L42:
movl 60(%rsp), %edx
.L23:
addl $1, %edx
cmpl %edx, 76(%rsp)
je .L21
.L28:
movl %edx, %eax
sall $14, %eax
movl %eax, 24(%rsp)
cmpb $0, 75(%rsp)
movl $0, %r15d
cmove %edx, %r15d
movl 8(%rsp), %eax
cmpl %eax, %r15d
jge .L23
movl %edx, 60(%rsp)
jmp .L27
.L21:
movl 48(%rsp), %r13d
testl %r13d, %r13d
jle .L33
movl $1, %ebp
movl $0, %r14d
leaq .LC6(%rip), %r15
movq %r12, 8(%rsp)
.L30:
movss 16(%rsp), %xmm3
movaps %xmm3, %xmm0
addss 20(%rsp), %xmm3
movss %xmm3, 16(%rsp)
movq (%rbx,%rbp,8), %r12
cvtss2sd %xmm0, %xmm0
movq %r12, %rcx
pxor %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movq %r15, %rdx
movl $2, %esi
movq 64(%rsp), %rdi
movl $2, %eax
call __fprintf_chk@PLT
addq %r12, %r14
addq $1, %rbp
cmpl %ebp, %r13d
jge .L30
movq 8(%rsp), %r12
.L29:
movq %r14, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call fclose@PLT
movq 40(%rsp), %rdi
call fclose@PLT
movq 64(%rsp), %rdi
call fclose@PLT
movq 104(%rsp), %rdi
call free@PLT
movq 80(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rdi
call free@PLT
movq 96(%rsp), %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 160(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L11
.L33:
movl $0, %r14d
jmp .L29
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z4calcP8_IO_FILES0_S0_ifffb, .-_Z4calcP8_IO_FILES0_S0_ifffb
.section .rodata.str1.1
.LC8:
.string "\nMust pass two input files.\n"
.LC9:
.string "r"
.LC10:
.string "w"
.LC11:
.string "output.txt"
.LC12:
.string "Input files are the same!\n"
.LC17:
.string "Execution time: %f \n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movq %rsi, %rbx
call clock@PLT
movq %rax, _ZL10start_time(%rip)
cmpl $3, %ebp
jne .L48
movslq optind(%rip), %rax
movq (%rbx,%rax,8), %rdi
leaq .LC9(%rip), %r12
movq %r12, %rsi
call fopen@PLT
movq %rax, %rbp
movslq optind(%rip), %rax
movq 8(%rbx,%rax,8), %rdi
movq %r12, %rsi
call fopen@PLT
movq %rax, %r12
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movslq optind(%rip), %rax
addq $1, %rax
movq (%rbx,%rax,8), %rsi
movq -8(%rbx,%rax,8), %rdi
call strcmp@PLT
movl $1, %r8d
testl %eax, %eax
je .L49
.L45:
andl $1, %r8d
movss .LC13(%rip), %xmm2
movss .LC14(%rip), %xmm1
movss .LC15(%rip), %xmm0
movl $256, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z4calcP8_IO_FILES0_S0_ifffb
call clock@PLT
subq _ZL10start_time(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC16(%rip), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
leaq .LC12(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %r8d
jmp .L45
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z8distancePVfS0_S0_S0_iiiiPViffifb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z8distancePVfS0_S0_S0_iiiiPViffifb(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
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_ZL15__fatDeviceText:
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.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 1553060174
.long 1084939134
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1048576000
.align 4
.LC14:
.long 1115684864
.align 4
.LC15:
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.section .rodata.cst8
.align 8
.LC16:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*--------------------------------------------------------------------------------------------------*/
/* */
/* Alberto Quesada Aranda */
/* Åbo Akademi University */
/* Advanced Computer Graphics and Graphics Hardware */
/* */
/* Two-Point angula correlation code */
/* Input: two list of galaxies */
/* Output: .txt file with the data for generate the histogram */
/* */
/* Base code taken from: https://github.com/djbard/ccogs/tree/master/angular_correlation */
/* */
/*--------------------------------------------------------------------------------------------------*/
#include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include<unistd.h>
#include<cuda_runtime.h>
#include<time.h>
using namespace std;
#define SUBMATRIX_SIZE 16384 // parallel threads: 32 blocks * 512 threads/block = 16384 threads
#define DEFAULT_NBINS 256 // num of bins for the histogram
#define arcm_to_rad 1/3437.7468 // (1/60)*(pi/180), convert from arcm to rad
#define conv_angle 57.2957795; // 180/pi, convert from rad to degrees
// variables for calculate the execution time
static clock_t start_time;
static double elapsed;
/*------------------------------------------------------------------
Kernel to calculate angular distances
-------------------------------------------------------------------*/
__global__ void distance(volatile float *a0, volatile float *d0, volatile float *a1, volatile float *d1, int xind, int yind, int max_xind, int max_yind, volatile int *dev_hist, float hist_min, float hist_max, int nbins, float bin_width, bool two_different_files=1) {
int idx = blockIdx.x * blockDim.x + threadIdx.x; // idx is the thread id, it must range to 32blocks * 512threads/block = 16384 threads
idx += xind; // allow the thread to know which submatrix has to calculate
// printf("%d %d %d\n", blockIdx.x, threadIdx.x, blockDim.x);
// blockIdx.x [0-31]
// blockDim.x 512
// threadIdx.x [0-511]
__shared__ int shared_hist[DEFAULT_NBINS+2]; // shared vector for save the results within a block of threads
// initialize it only once in each block
if(threadIdx.x==0)
{
for (int i=0;i<nbins+2;i++)
shared_hist[i] = 0;
}
// before starting the calculations we need to be sure that the shared_hist is initialized; if not, we take the risk
// of loss calculations because we don't know the order in which the threads are executed and is possible that a thread
// performs the calculations and write the results in shared_hist before the thread 0 has initialized it.
__syncthreads();
// if NUM_GALAXIES0 % SUBMATRIX_SIZE != 0 in the last submatrix we will have more threads than needed calculations, therefore
// we won't perform calculations with those threads.
if (idx<max_xind) {
float dist, alpha1, delta1, a_diff;
float alpha0 = a0[idx];
float delta0 = d0[idx];
bool do_calc = 1;
int bin_index = 0;
// each kernel will calculate the angle between one galaxy of the first input data (idx) and all the galaxies within [yind-ymax]
int ymax = yind + SUBMATRIX_SIZE; // ymax will be the end of the submatrix that we are calculating of the second galaxies input
// we have to take care and if ymax > NUM_GALAXIES1, we stop the calculations bucle at that point
if (ymax>max_yind)
ymax = max_yind;
// we will perform the same calculation between input0[idx] and every input1[] (range [yind-ymax])
for(int i=yind; i<ymax; i++)
{
// if the two input files are different (DR case) we have to perform all N*N calculations
if (two_different_files) {
do_calc = 1;
}
// if the two input files are the same (DD, RR cases) we have to perform N*(N-1)/2 calculations
else {
if (xind != yind) {
do_calc = 1;
}
else {
if(idx > i)
do_calc=1;
else
do_calc=0;
}
}
if (do_calc)
{
alpha1 = a1[i];
delta1 = d1[i];
a_diff = alpha0 - alpha1;
dist = acos(sin(delta0)*sin(delta1) + cos(alpha0)*cos(alpha1)*cos(a_diff));
dist *= conv_angle; // convert from rad to degrees
// check in which bin we have to include the angle calculated
if(dist < hist_min) // underflow
bin_index = 0;
else if(dist >= hist_max) // overflow
bin_index = nbins + 1;
else {
bin_index = int((dist-hist_min)/bin_width) + 1;
}
// more than one thread could try to write its result in the shared_hist at the same time and in the same memory
// location. We need an atomic operation for prevent the loss of data
atomicAdd(&shared_hist[bin_index],1); // increment by one the corresponding histogram bin
}
}
}
// before copy the results of each block to the global histogram we have to be sure that all the threads within the block have
// ended its calculations
__syncthreads();
// only one thread (0) will write the results of the block to which it belongs to the global histogram
// for avoid the need of another atomic operation, our global histogram save the result of each block successively :
// [block[0], block[1] .... block [31]]
if(threadIdx.x==0)
{
for(int i=0;i<nbins+2;i++)
dev_hist[i+(blockIdx.x*(nbins+2))]=shared_hist[i];
}
}
/*------------------------------------------------------------------
Calculations and call to kernel
-------------------------------------------------------------------*/
int calc(FILE *infile0, FILE *infile1, FILE *outfile, int nbins, float hist_lower_range, float hist_upper_range, float hist_bin_width, bool two_different_files){
//d_ means device -> GPU, h_ means host -> CPU
float *d_alpha0, *d_delta0, *d_alpha1, *d_delta1;
float *h_alpha0, *h_delta0, *h_alpha1, *h_delta1;
int NUM_GALAXIES0, NUM_GALAXIES1;
// reading the data of the input files
// first we read the number of galaxies of each file
fscanf(infile0, "%d", &NUM_GALAXIES0);
fscanf(infile1, "%d", &NUM_GALAXIES1);
// calculate the size of the array needed for save in memory all the galaxies
int size_of_galaxy_array0 = NUM_GALAXIES0 * sizeof(float);
int size_of_galaxy_array1 = NUM_GALAXIES1 * sizeof(float);
printf("SIZE 0 # GALAXIES: %d\n",NUM_GALAXIES0);
printf("SIZE 1 # GALAXIES: %d\n",NUM_GALAXIES1);
// allocate space for the galaxies data in global memory
h_alpha0 = (float*)malloc(size_of_galaxy_array0);
h_delta0 = (float*)malloc(size_of_galaxy_array0);
h_alpha1 = (float*)malloc(size_of_galaxy_array1);
h_delta1 = (float*)malloc(size_of_galaxy_array1);
float temp0, temp1;
// reading and saving the galaxies data in radians
for(int i=0; i<NUM_GALAXIES0; i++)
{
fscanf(infile0, "%f %f", &temp0, &temp1);
h_alpha0[i] = temp0 * arcm_to_rad;
h_delta0[i] = temp1 * arcm_to_rad;
}
for(int i=0; i<NUM_GALAXIES1; i++)
{
fscanf(infile1, "%f %f", &temp0, &temp1);
h_alpha1[i] = temp0 * arcm_to_rad;
h_delta1[i] = temp1 * arcm_to_rad;
}
// defining dimensions for the grid and block
dim3 grid, block;
grid.x = 8192/(DEFAULT_NBINS); // number of blocks = 32
block.x = SUBMATRIX_SIZE/grid.x; // number of threads/block = 512
// allocating the histograms
/* I will need 3 arrays for the histograms:
- hist : for each submatrix, save the results of each thread block seccuentially (global memory)
- dev_hist : the same as hist, but in GPU memory
- hist_array : save the global result of all the submatrix in global memory
*/
int *hist, *dev_hist;
int size_hist = grid.x * (nbins+2); // I use +2, one for underflow and other for overflow
int size_hist_bytes = size_hist*sizeof(int);
// allocating and initializing to 0 hist in global mem
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
// allocating and initializing to 0 dev_hist in GPU mem
cudaMalloc((void **) &dev_hist, (size_hist_bytes));
cudaMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
// allocating and initializing to 0 the array for the final histogram (the sum of each submatrix partial result)
int hist_array_size = (nbins+2) * sizeof(unsigned long);
hist_array = (unsigned long*)malloc(hist_array_size);
memset(hist_array,0,hist_array_size);
// allocating memory in GPU for save the galaxies data
cudaMalloc((void **) &d_alpha0, size_of_galaxy_array0 );
cudaMalloc((void **) &d_delta0, size_of_galaxy_array0 );
cudaMalloc((void **) &d_alpha1, size_of_galaxy_array1 );
cudaMalloc((void **) &d_delta1, size_of_galaxy_array1 );
// check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate enough memory in GPU\n");
return 1;
}
// initialize array to all 0's
/*cudaMemset(d_alpha0,0,size_of_galaxy_array0);
cudaMemset(d_delta0,0,size_of_galaxy_array0);
cudaMemset(d_alpha1,0,size_of_galaxy_array1);
cudaMemset(d_delta1,0,size_of_galaxy_array1);*/
// copy galaxies data to GPU
cudaMemcpy(d_alpha0, h_alpha0, size_of_galaxy_array0, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta0, h_delta0, size_of_galaxy_array0, cudaMemcpyHostToDevice );
cudaMemcpy(d_alpha1, h_alpha1, size_of_galaxy_array1, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta1, h_delta1, size_of_galaxy_array1, cudaMemcpyHostToDevice );
int x, y;
int num_submatrices_x = NUM_GALAXIES0 / SUBMATRIX_SIZE;
int num_submatrices_y = NUM_GALAXIES1 / SUBMATRIX_SIZE;
// if NUM_GALAXIES % SUBMATRIX_SIZE != 0, we will need one submatrix more (not the whole submatrix) for perform all the calculations
if (NUM_GALAXIES0%SUBMATRIX_SIZE != 0) {
num_submatrices_x += 1;
}
if (NUM_GALAXIES1%SUBMATRIX_SIZE != 0) {
num_submatrices_y += 1;
}
int bin_index = 0;
// explanation of the iterations in the documentation
for(int k = 0; k < num_submatrices_y; k++)
{
y = k*SUBMATRIX_SIZE;
int jmax = 0;
// if the two files are the same, then only loop over the upper half of the matrix of operations
if (two_different_files == 0)
jmax = k;
for(int j = jmax; j < num_submatrices_x; j++)
{
x = j*SUBMATRIX_SIZE;
// set the histogram to all zeros each time.
cudaMemset(dev_hist,0,size_hist_bytes);
// call to the kernel
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, NUM_GALAXIES0, NUM_GALAXIES1, dev_hist, hist_lower_range, hist_upper_range, nbins, hist_bin_width, two_different_files);
// copy the results from GPU memory to global mem
cudaMemcpy(hist, dev_hist, size_hist_bytes, cudaMemcpyDeviceToHost);
// add together the results of each block in a single histogram
for(int m=0; m<size_hist; m++)
{
bin_index = m%(nbins+2); // range it to [0-258]
hist_array[bin_index] += hist[m];
}
}
}
unsigned long total = 0;
// write in the output file the range of the bin of the histogram and the number of galaxies included in that range
// start in k = 1 and finish before nbins+1 for avoid the over/underflow
float lo = hist_lower_range;
float hi = 0;
for(int k=1; k<nbins+1; k++)
{
hi = lo + hist_bin_width;
fprintf(outfile, "%.3e %.3e %lu \n",lo,hi,hist_array[k]);
total += hist_array[k];
lo = hi;
}
printf("total: %lu \n", total);
// close opened files
fclose(infile0);
fclose(infile1);
fclose(outfile);
// free global memory
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
// free GPU memory
cudaFree(d_alpha0);
cudaFree(d_delta0);
cudaFree(d_alpha1);
cudaFree(d_delta1);
cudaFree(dev_hist);
return 0;
}
/*------------------------------------------------------------------
MAIN
-------------------------------------------------------------------*/
int main(int argc, char **argv) {
start_time = clock(); // start the timer
int nbins = DEFAULT_NBINS; // 256 bins --> 0-64º --> 64/0.25 = 256
float bin_width = 0.25;
float lower_range = 0.0000001;
float upper_range = nbins * bin_width; // 256 * 0.25 = 64
bool different_files = 1;
if (argc != 3) {
printf("\nMust pass two input files.\n");
exit(1);
}
// opening the input files and creating the output file
FILE *infile0, *infile1, *outfile;
infile0 = fopen(argv[optind],"r");
infile1 = fopen(argv[optind+1],"r");
outfile = fopen("output.txt", "w");
// if the input files are the same (DD, RR) the calculations needed are different from the DR case
if (strcmp(argv[optind],argv[optind+1]) == 0) {
different_files = 0;
printf("Input files are the same!\n");
}
calc(infile0, infile1, outfile, nbins, lower_range, upper_range, bin_width, different_files);
// total time
elapsed = clock() - start_time;
elapsed = elapsed / CLOCKS_PER_SEC;
printf("Execution time: %f \n", elapsed);
return 0;
} | /*--------------------------------------------------------------------------------------------------*/
/* */
/* Alberto Quesada Aranda */
/* Åbo Akademi University */
/* Advanced Computer Graphics and Graphics Hardware */
/* */
/* Two-Point angula correlation code */
/* Input: two list of galaxies */
/* Output: .txt file with the data for generate the histogram */
/* */
/* Base code taken from: https://github.com/djbard/ccogs/tree/master/angular_correlation */
/* */
/*--------------------------------------------------------------------------------------------------*/
#include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include<unistd.h>
#include<hip/hip_runtime.h>
#include<time.h>
using namespace std;
#define SUBMATRIX_SIZE 16384 // parallel threads: 32 blocks * 512 threads/block = 16384 threads
#define DEFAULT_NBINS 256 // num of bins for the histogram
#define arcm_to_rad 1/3437.7468 // (1/60)*(pi/180), convert from arcm to rad
#define conv_angle 57.2957795; // 180/pi, convert from rad to degrees
// variables for calculate the execution time
static clock_t start_time;
static double elapsed;
/*------------------------------------------------------------------
Kernel to calculate angular distances
-------------------------------------------------------------------*/
__global__ void distance(volatile float *a0, volatile float *d0, volatile float *a1, volatile float *d1, int xind, int yind, int max_xind, int max_yind, volatile int *dev_hist, float hist_min, float hist_max, int nbins, float bin_width, bool two_different_files=1) {
int idx = blockIdx.x * blockDim.x + threadIdx.x; // idx is the thread id, it must range to 32blocks * 512threads/block = 16384 threads
idx += xind; // allow the thread to know which submatrix has to calculate
// printf("%d %d %d\n", blockIdx.x, threadIdx.x, blockDim.x);
// blockIdx.x [0-31]
// blockDim.x 512
// threadIdx.x [0-511]
__shared__ int shared_hist[DEFAULT_NBINS+2]; // shared vector for save the results within a block of threads
// initialize it only once in each block
if(threadIdx.x==0)
{
for (int i=0;i<nbins+2;i++)
shared_hist[i] = 0;
}
// before starting the calculations we need to be sure that the shared_hist is initialized; if not, we take the risk
// of loss calculations because we don't know the order in which the threads are executed and is possible that a thread
// performs the calculations and write the results in shared_hist before the thread 0 has initialized it.
__syncthreads();
// if NUM_GALAXIES0 % SUBMATRIX_SIZE != 0 in the last submatrix we will have more threads than needed calculations, therefore
// we won't perform calculations with those threads.
if (idx<max_xind) {
float dist, alpha1, delta1, a_diff;
float alpha0 = a0[idx];
float delta0 = d0[idx];
bool do_calc = 1;
int bin_index = 0;
// each kernel will calculate the angle between one galaxy of the first input data (idx) and all the galaxies within [yind-ymax]
int ymax = yind + SUBMATRIX_SIZE; // ymax will be the end of the submatrix that we are calculating of the second galaxies input
// we have to take care and if ymax > NUM_GALAXIES1, we stop the calculations bucle at that point
if (ymax>max_yind)
ymax = max_yind;
// we will perform the same calculation between input0[idx] and every input1[] (range [yind-ymax])
for(int i=yind; i<ymax; i++)
{
// if the two input files are different (DR case) we have to perform all N*N calculations
if (two_different_files) {
do_calc = 1;
}
// if the two input files are the same (DD, RR cases) we have to perform N*(N-1)/2 calculations
else {
if (xind != yind) {
do_calc = 1;
}
else {
if(idx > i)
do_calc=1;
else
do_calc=0;
}
}
if (do_calc)
{
alpha1 = a1[i];
delta1 = d1[i];
a_diff = alpha0 - alpha1;
dist = acos(sin(delta0)*sin(delta1) + cos(alpha0)*cos(alpha1)*cos(a_diff));
dist *= conv_angle; // convert from rad to degrees
// check in which bin we have to include the angle calculated
if(dist < hist_min) // underflow
bin_index = 0;
else if(dist >= hist_max) // overflow
bin_index = nbins + 1;
else {
bin_index = int((dist-hist_min)/bin_width) + 1;
}
// more than one thread could try to write its result in the shared_hist at the same time and in the same memory
// location. We need an atomic operation for prevent the loss of data
atomicAdd(&shared_hist[bin_index],1); // increment by one the corresponding histogram bin
}
}
}
// before copy the results of each block to the global histogram we have to be sure that all the threads within the block have
// ended its calculations
__syncthreads();
// only one thread (0) will write the results of the block to which it belongs to the global histogram
// for avoid the need of another atomic operation, our global histogram save the result of each block successively :
// [block[0], block[1] .... block [31]]
if(threadIdx.x==0)
{
for(int i=0;i<nbins+2;i++)
dev_hist[i+(blockIdx.x*(nbins+2))]=shared_hist[i];
}
}
/*------------------------------------------------------------------
Calculations and call to kernel
-------------------------------------------------------------------*/
int calc(FILE *infile0, FILE *infile1, FILE *outfile, int nbins, float hist_lower_range, float hist_upper_range, float hist_bin_width, bool two_different_files){
//d_ means device -> GPU, h_ means host -> CPU
float *d_alpha0, *d_delta0, *d_alpha1, *d_delta1;
float *h_alpha0, *h_delta0, *h_alpha1, *h_delta1;
int NUM_GALAXIES0, NUM_GALAXIES1;
// reading the data of the input files
// first we read the number of galaxies of each file
fscanf(infile0, "%d", &NUM_GALAXIES0);
fscanf(infile1, "%d", &NUM_GALAXIES1);
// calculate the size of the array needed for save in memory all the galaxies
int size_of_galaxy_array0 = NUM_GALAXIES0 * sizeof(float);
int size_of_galaxy_array1 = NUM_GALAXIES1 * sizeof(float);
printf("SIZE 0 # GALAXIES: %d\n",NUM_GALAXIES0);
printf("SIZE 1 # GALAXIES: %d\n",NUM_GALAXIES1);
// allocate space for the galaxies data in global memory
h_alpha0 = (float*)malloc(size_of_galaxy_array0);
h_delta0 = (float*)malloc(size_of_galaxy_array0);
h_alpha1 = (float*)malloc(size_of_galaxy_array1);
h_delta1 = (float*)malloc(size_of_galaxy_array1);
float temp0, temp1;
// reading and saving the galaxies data in radians
for(int i=0; i<NUM_GALAXIES0; i++)
{
fscanf(infile0, "%f %f", &temp0, &temp1);
h_alpha0[i] = temp0 * arcm_to_rad;
h_delta0[i] = temp1 * arcm_to_rad;
}
for(int i=0; i<NUM_GALAXIES1; i++)
{
fscanf(infile1, "%f %f", &temp0, &temp1);
h_alpha1[i] = temp0 * arcm_to_rad;
h_delta1[i] = temp1 * arcm_to_rad;
}
// defining dimensions for the grid and block
dim3 grid, block;
grid.x = 8192/(DEFAULT_NBINS); // number of blocks = 32
block.x = SUBMATRIX_SIZE/grid.x; // number of threads/block = 512
// allocating the histograms
/* I will need 3 arrays for the histograms:
- hist : for each submatrix, save the results of each thread block seccuentially (global memory)
- dev_hist : the same as hist, but in GPU memory
- hist_array : save the global result of all the submatrix in global memory
*/
int *hist, *dev_hist;
int size_hist = grid.x * (nbins+2); // I use +2, one for underflow and other for overflow
int size_hist_bytes = size_hist*sizeof(int);
// allocating and initializing to 0 hist in global mem
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
// allocating and initializing to 0 dev_hist in GPU mem
hipMalloc((void **) &dev_hist, (size_hist_bytes));
hipMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
// allocating and initializing to 0 the array for the final histogram (the sum of each submatrix partial result)
int hist_array_size = (nbins+2) * sizeof(unsigned long);
hist_array = (unsigned long*)malloc(hist_array_size);
memset(hist_array,0,hist_array_size);
// allocating memory in GPU for save the galaxies data
hipMalloc((void **) &d_alpha0, size_of_galaxy_array0 );
hipMalloc((void **) &d_delta0, size_of_galaxy_array0 );
hipMalloc((void **) &d_alpha1, size_of_galaxy_array1 );
hipMalloc((void **) &d_delta1, size_of_galaxy_array1 );
// check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate enough memory in GPU\n");
return 1;
}
// initialize array to all 0's
/*cudaMemset(d_alpha0,0,size_of_galaxy_array0);
cudaMemset(d_delta0,0,size_of_galaxy_array0);
cudaMemset(d_alpha1,0,size_of_galaxy_array1);
cudaMemset(d_delta1,0,size_of_galaxy_array1);*/
// copy galaxies data to GPU
hipMemcpy(d_alpha0, h_alpha0, size_of_galaxy_array0, hipMemcpyHostToDevice );
hipMemcpy(d_delta0, h_delta0, size_of_galaxy_array0, hipMemcpyHostToDevice );
hipMemcpy(d_alpha1, h_alpha1, size_of_galaxy_array1, hipMemcpyHostToDevice );
hipMemcpy(d_delta1, h_delta1, size_of_galaxy_array1, hipMemcpyHostToDevice );
int x, y;
int num_submatrices_x = NUM_GALAXIES0 / SUBMATRIX_SIZE;
int num_submatrices_y = NUM_GALAXIES1 / SUBMATRIX_SIZE;
// if NUM_GALAXIES % SUBMATRIX_SIZE != 0, we will need one submatrix more (not the whole submatrix) for perform all the calculations
if (NUM_GALAXIES0%SUBMATRIX_SIZE != 0) {
num_submatrices_x += 1;
}
if (NUM_GALAXIES1%SUBMATRIX_SIZE != 0) {
num_submatrices_y += 1;
}
int bin_index = 0;
// explanation of the iterations in the documentation
for(int k = 0; k < num_submatrices_y; k++)
{
y = k*SUBMATRIX_SIZE;
int jmax = 0;
// if the two files are the same, then only loop over the upper half of the matrix of operations
if (two_different_files == 0)
jmax = k;
for(int j = jmax; j < num_submatrices_x; j++)
{
x = j*SUBMATRIX_SIZE;
// set the histogram to all zeros each time.
hipMemset(dev_hist,0,size_hist_bytes);
// call to the kernel
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, NUM_GALAXIES0, NUM_GALAXIES1, dev_hist, hist_lower_range, hist_upper_range, nbins, hist_bin_width, two_different_files);
// copy the results from GPU memory to global mem
hipMemcpy(hist, dev_hist, size_hist_bytes, hipMemcpyDeviceToHost);
// add together the results of each block in a single histogram
for(int m=0; m<size_hist; m++)
{
bin_index = m%(nbins+2); // range it to [0-258]
hist_array[bin_index] += hist[m];
}
}
}
unsigned long total = 0;
// write in the output file the range of the bin of the histogram and the number of galaxies included in that range
// start in k = 1 and finish before nbins+1 for avoid the over/underflow
float lo = hist_lower_range;
float hi = 0;
for(int k=1; k<nbins+1; k++)
{
hi = lo + hist_bin_width;
fprintf(outfile, "%.3e %.3e %lu \n",lo,hi,hist_array[k]);
total += hist_array[k];
lo = hi;
}
printf("total: %lu \n", total);
// close opened files
fclose(infile0);
fclose(infile1);
fclose(outfile);
// free global memory
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
// free GPU memory
hipFree(d_alpha0);
hipFree(d_delta0);
hipFree(d_alpha1);
hipFree(d_delta1);
hipFree(dev_hist);
return 0;
}
/*------------------------------------------------------------------
MAIN
-------------------------------------------------------------------*/
int main(int argc, char **argv) {
start_time = clock(); // start the timer
int nbins = DEFAULT_NBINS; // 256 bins --> 0-64º --> 64/0.25 = 256
float bin_width = 0.25;
float lower_range = 0.0000001;
float upper_range = nbins * bin_width; // 256 * 0.25 = 64
bool different_files = 1;
if (argc != 3) {
printf("\nMust pass two input files.\n");
exit(1);
}
// opening the input files and creating the output file
FILE *infile0, *infile1, *outfile;
infile0 = fopen(argv[optind],"r");
infile1 = fopen(argv[optind+1],"r");
outfile = fopen("output.txt", "w");
// if the input files are the same (DD, RR) the calculations needed are different from the DR case
if (strcmp(argv[optind],argv[optind+1]) == 0) {
different_files = 0;
printf("Input files are the same!\n");
}
calc(infile0, infile1, outfile, nbins, lower_range, upper_range, bin_width, different_files);
// total time
elapsed = clock() - start_time;
elapsed = elapsed / CLOCKS_PER_SEC;
printf("Execution time: %f \n", elapsed);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*--------------------------------------------------------------------------------------------------*/
/* */
/* Alberto Quesada Aranda */
/* Åbo Akademi University */
/* Advanced Computer Graphics and Graphics Hardware */
/* */
/* Two-Point angula correlation code */
/* Input: two list of galaxies */
/* Output: .txt file with the data for generate the histogram */
/* */
/* Base code taken from: https://github.com/djbard/ccogs/tree/master/angular_correlation */
/* */
/*--------------------------------------------------------------------------------------------------*/
#include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include<unistd.h>
#include<hip/hip_runtime.h>
#include<time.h>
using namespace std;
#define SUBMATRIX_SIZE 16384 // parallel threads: 32 blocks * 512 threads/block = 16384 threads
#define DEFAULT_NBINS 256 // num of bins for the histogram
#define arcm_to_rad 1/3437.7468 // (1/60)*(pi/180), convert from arcm to rad
#define conv_angle 57.2957795; // 180/pi, convert from rad to degrees
// variables for calculate the execution time
static clock_t start_time;
static double elapsed;
/*------------------------------------------------------------------
Kernel to calculate angular distances
-------------------------------------------------------------------*/
__global__ void distance(volatile float *a0, volatile float *d0, volatile float *a1, volatile float *d1, int xind, int yind, int max_xind, int max_yind, volatile int *dev_hist, float hist_min, float hist_max, int nbins, float bin_width, bool two_different_files=1) {
int idx = blockIdx.x * blockDim.x + threadIdx.x; // idx is the thread id, it must range to 32blocks * 512threads/block = 16384 threads
idx += xind; // allow the thread to know which submatrix has to calculate
// printf("%d %d %d\n", blockIdx.x, threadIdx.x, blockDim.x);
// blockIdx.x [0-31]
// blockDim.x 512
// threadIdx.x [0-511]
__shared__ int shared_hist[DEFAULT_NBINS+2]; // shared vector for save the results within a block of threads
// initialize it only once in each block
if(threadIdx.x==0)
{
for (int i=0;i<nbins+2;i++)
shared_hist[i] = 0;
}
// before starting the calculations we need to be sure that the shared_hist is initialized; if not, we take the risk
// of loss calculations because we don't know the order in which the threads are executed and is possible that a thread
// performs the calculations and write the results in shared_hist before the thread 0 has initialized it.
__syncthreads();
// if NUM_GALAXIES0 % SUBMATRIX_SIZE != 0 in the last submatrix we will have more threads than needed calculations, therefore
// we won't perform calculations with those threads.
if (idx<max_xind) {
float dist, alpha1, delta1, a_diff;
float alpha0 = a0[idx];
float delta0 = d0[idx];
bool do_calc = 1;
int bin_index = 0;
// each kernel will calculate the angle between one galaxy of the first input data (idx) and all the galaxies within [yind-ymax]
int ymax = yind + SUBMATRIX_SIZE; // ymax will be the end of the submatrix that we are calculating of the second galaxies input
// we have to take care and if ymax > NUM_GALAXIES1, we stop the calculations bucle at that point
if (ymax>max_yind)
ymax = max_yind;
// we will perform the same calculation between input0[idx] and every input1[] (range [yind-ymax])
for(int i=yind; i<ymax; i++)
{
// if the two input files are different (DR case) we have to perform all N*N calculations
if (two_different_files) {
do_calc = 1;
}
// if the two input files are the same (DD, RR cases) we have to perform N*(N-1)/2 calculations
else {
if (xind != yind) {
do_calc = 1;
}
else {
if(idx > i)
do_calc=1;
else
do_calc=0;
}
}
if (do_calc)
{
alpha1 = a1[i];
delta1 = d1[i];
a_diff = alpha0 - alpha1;
dist = acos(sin(delta0)*sin(delta1) + cos(alpha0)*cos(alpha1)*cos(a_diff));
dist *= conv_angle; // convert from rad to degrees
// check in which bin we have to include the angle calculated
if(dist < hist_min) // underflow
bin_index = 0;
else if(dist >= hist_max) // overflow
bin_index = nbins + 1;
else {
bin_index = int((dist-hist_min)/bin_width) + 1;
}
// more than one thread could try to write its result in the shared_hist at the same time and in the same memory
// location. We need an atomic operation for prevent the loss of data
atomicAdd(&shared_hist[bin_index],1); // increment by one the corresponding histogram bin
}
}
}
// before copy the results of each block to the global histogram we have to be sure that all the threads within the block have
// ended its calculations
__syncthreads();
// only one thread (0) will write the results of the block to which it belongs to the global histogram
// for avoid the need of another atomic operation, our global histogram save the result of each block successively :
// [block[0], block[1] .... block [31]]
if(threadIdx.x==0)
{
for(int i=0;i<nbins+2;i++)
dev_hist[i+(blockIdx.x*(nbins+2))]=shared_hist[i];
}
}
/*------------------------------------------------------------------
Calculations and call to kernel
-------------------------------------------------------------------*/
int calc(FILE *infile0, FILE *infile1, FILE *outfile, int nbins, float hist_lower_range, float hist_upper_range, float hist_bin_width, bool two_different_files){
//d_ means device -> GPU, h_ means host -> CPU
float *d_alpha0, *d_delta0, *d_alpha1, *d_delta1;
float *h_alpha0, *h_delta0, *h_alpha1, *h_delta1;
int NUM_GALAXIES0, NUM_GALAXIES1;
// reading the data of the input files
// first we read the number of galaxies of each file
fscanf(infile0, "%d", &NUM_GALAXIES0);
fscanf(infile1, "%d", &NUM_GALAXIES1);
// calculate the size of the array needed for save in memory all the galaxies
int size_of_galaxy_array0 = NUM_GALAXIES0 * sizeof(float);
int size_of_galaxy_array1 = NUM_GALAXIES1 * sizeof(float);
printf("SIZE 0 # GALAXIES: %d\n",NUM_GALAXIES0);
printf("SIZE 1 # GALAXIES: %d\n",NUM_GALAXIES1);
// allocate space for the galaxies data in global memory
h_alpha0 = (float*)malloc(size_of_galaxy_array0);
h_delta0 = (float*)malloc(size_of_galaxy_array0);
h_alpha1 = (float*)malloc(size_of_galaxy_array1);
h_delta1 = (float*)malloc(size_of_galaxy_array1);
float temp0, temp1;
// reading and saving the galaxies data in radians
for(int i=0; i<NUM_GALAXIES0; i++)
{
fscanf(infile0, "%f %f", &temp0, &temp1);
h_alpha0[i] = temp0 * arcm_to_rad;
h_delta0[i] = temp1 * arcm_to_rad;
}
for(int i=0; i<NUM_GALAXIES1; i++)
{
fscanf(infile1, "%f %f", &temp0, &temp1);
h_alpha1[i] = temp0 * arcm_to_rad;
h_delta1[i] = temp1 * arcm_to_rad;
}
// defining dimensions for the grid and block
dim3 grid, block;
grid.x = 8192/(DEFAULT_NBINS); // number of blocks = 32
block.x = SUBMATRIX_SIZE/grid.x; // number of threads/block = 512
// allocating the histograms
/* I will need 3 arrays for the histograms:
- hist : for each submatrix, save the results of each thread block seccuentially (global memory)
- dev_hist : the same as hist, but in GPU memory
- hist_array : save the global result of all the submatrix in global memory
*/
int *hist, *dev_hist;
int size_hist = grid.x * (nbins+2); // I use +2, one for underflow and other for overflow
int size_hist_bytes = size_hist*sizeof(int);
// allocating and initializing to 0 hist in global mem
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
// allocating and initializing to 0 dev_hist in GPU mem
hipMalloc((void **) &dev_hist, (size_hist_bytes));
hipMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
// allocating and initializing to 0 the array for the final histogram (the sum of each submatrix partial result)
int hist_array_size = (nbins+2) * sizeof(unsigned long);
hist_array = (unsigned long*)malloc(hist_array_size);
memset(hist_array,0,hist_array_size);
// allocating memory in GPU for save the galaxies data
hipMalloc((void **) &d_alpha0, size_of_galaxy_array0 );
hipMalloc((void **) &d_delta0, size_of_galaxy_array0 );
hipMalloc((void **) &d_alpha1, size_of_galaxy_array1 );
hipMalloc((void **) &d_delta1, size_of_galaxy_array1 );
// check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate enough memory in GPU\n");
return 1;
}
// initialize array to all 0's
/*cudaMemset(d_alpha0,0,size_of_galaxy_array0);
cudaMemset(d_delta0,0,size_of_galaxy_array0);
cudaMemset(d_alpha1,0,size_of_galaxy_array1);
cudaMemset(d_delta1,0,size_of_galaxy_array1);*/
// copy galaxies data to GPU
hipMemcpy(d_alpha0, h_alpha0, size_of_galaxy_array0, hipMemcpyHostToDevice );
hipMemcpy(d_delta0, h_delta0, size_of_galaxy_array0, hipMemcpyHostToDevice );
hipMemcpy(d_alpha1, h_alpha1, size_of_galaxy_array1, hipMemcpyHostToDevice );
hipMemcpy(d_delta1, h_delta1, size_of_galaxy_array1, hipMemcpyHostToDevice );
int x, y;
int num_submatrices_x = NUM_GALAXIES0 / SUBMATRIX_SIZE;
int num_submatrices_y = NUM_GALAXIES1 / SUBMATRIX_SIZE;
// if NUM_GALAXIES % SUBMATRIX_SIZE != 0, we will need one submatrix more (not the whole submatrix) for perform all the calculations
if (NUM_GALAXIES0%SUBMATRIX_SIZE != 0) {
num_submatrices_x += 1;
}
if (NUM_GALAXIES1%SUBMATRIX_SIZE != 0) {
num_submatrices_y += 1;
}
int bin_index = 0;
// explanation of the iterations in the documentation
for(int k = 0; k < num_submatrices_y; k++)
{
y = k*SUBMATRIX_SIZE;
int jmax = 0;
// if the two files are the same, then only loop over the upper half of the matrix of operations
if (two_different_files == 0)
jmax = k;
for(int j = jmax; j < num_submatrices_x; j++)
{
x = j*SUBMATRIX_SIZE;
// set the histogram to all zeros each time.
hipMemset(dev_hist,0,size_hist_bytes);
// call to the kernel
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, NUM_GALAXIES0, NUM_GALAXIES1, dev_hist, hist_lower_range, hist_upper_range, nbins, hist_bin_width, two_different_files);
// copy the results from GPU memory to global mem
hipMemcpy(hist, dev_hist, size_hist_bytes, hipMemcpyDeviceToHost);
// add together the results of each block in a single histogram
for(int m=0; m<size_hist; m++)
{
bin_index = m%(nbins+2); // range it to [0-258]
hist_array[bin_index] += hist[m];
}
}
}
unsigned long total = 0;
// write in the output file the range of the bin of the histogram and the number of galaxies included in that range
// start in k = 1 and finish before nbins+1 for avoid the over/underflow
float lo = hist_lower_range;
float hi = 0;
for(int k=1; k<nbins+1; k++)
{
hi = lo + hist_bin_width;
fprintf(outfile, "%.3e %.3e %lu \n",lo,hi,hist_array[k]);
total += hist_array[k];
lo = hi;
}
printf("total: %lu \n", total);
// close opened files
fclose(infile0);
fclose(infile1);
fclose(outfile);
// free global memory
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
// free GPU memory
hipFree(d_alpha0);
hipFree(d_delta0);
hipFree(d_alpha1);
hipFree(d_delta1);
hipFree(dev_hist);
return 0;
}
/*------------------------------------------------------------------
MAIN
-------------------------------------------------------------------*/
int main(int argc, char **argv) {
start_time = clock(); // start the timer
int nbins = DEFAULT_NBINS; // 256 bins --> 0-64º --> 64/0.25 = 256
float bin_width = 0.25;
float lower_range = 0.0000001;
float upper_range = nbins * bin_width; // 256 * 0.25 = 64
bool different_files = 1;
if (argc != 3) {
printf("\nMust pass two input files.\n");
exit(1);
}
// opening the input files and creating the output file
FILE *infile0, *infile1, *outfile;
infile0 = fopen(argv[optind],"r");
infile1 = fopen(argv[optind+1],"r");
outfile = fopen("output.txt", "w");
// if the input files are the same (DD, RR) the calculations needed are different from the DR case
if (strcmp(argv[optind],argv[optind+1]) == 0) {
different_files = 0;
printf("Input files are the same!\n");
}
calc(infile0, infile1, outfile, nbins, lower_range, upper_range, bin_width, different_files);
// total time
elapsed = clock() - start_time;
elapsed = elapsed / CLOCKS_PER_SEC;
printf("Execution time: %f \n", elapsed);
return 0;
} | .text
.file "project.hip"
.globl _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb # -- Begin function _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.p2align 4, 0x90
.type _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb,@function
_Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb: # @_Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movzbl 272(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movb %al, 11(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 11(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8distancePVfS0_S0_S0_iiiiPViffifb, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb, .Lfunc_end0-_Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4calcP8_IO_FILES0_S0_ifffb
.LCPI1_0:
.quad 0x40aadb7e5c91d14e # double 3437.7467999999999
.text
.globl _Z4calcP8_IO_FILES0_S0_ifffb
.p2align 4, 0x90
.type _Z4calcP8_IO_FILES0_S0_ifffb,@function
_Z4calcP8_IO_FILES0_S0_ifffb: # @_Z4calcP8_IO_FILES0_S0_ifffb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 48(%rsp) # 4-byte Spill
movss %xmm2, 52(%rsp) # 4-byte Spill
movss %xmm1, 120(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
movq %rcx, 96(%rsp) # 8-byte Spill
movq %rdx, 192(%rsp) # 8-byte Spill
movq %rsi, %rbx
movq %rdi, %r14
leaq 12(%rsp), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 4(%rsp), %rdx
movl $.L.str, %esi
movq %rbx, 184(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %esi
leal (,%rsi,4), %ebp
movl 4(%rsp), %ebx
shll $2, %ebx
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl 4(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movslq %ebp, %r15
movq %r14, %rbp
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, 56(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r13
movslq %ebx, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 176(%rsp) # 8-byte Spill
movq %rbx, 32(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 20(%rsp), %rbx
leaq 16(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%r15,4)
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%r15,4)
incq %r15
movslq 12(%rsp), %rax
cmpq %rax, %r15
jl .LBB1_2
.LBB1_3: # %.preheader136
movq %r13, 160(%rsp) # 8-byte Spill
movq %r12, 168(%rsp) # 8-byte Spill
movq %rbp, 200(%rsp) # 8-byte Spill
cmpl $0, 4(%rsp)
movq 176(%rsp), %r12 # 8-byte Reload
movq 88(%rsp), %r13 # 8-byte Reload
movq 184(%rsp), %rbp # 8-byte Reload
jle .LBB1_6
# %bb.4: # %.lr.ph139.preheader
leaq 20(%rsp), %rbx
leaq 16(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph139
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%r15,4)
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%r15,4)
incq %r15
movslq 4(%rsp), %rax
cmpq %rax, %r15
jl .LBB1_5
.LBB1_6: # %._crit_edge
movq 96(%rsp), %r14 # 8-byte Reload
leal 2(%r14), %r15d
movl %r15d, %eax
shll $7, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
leal 16(,%r14,8), %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %rax, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
leaq 104(%rsp), %rdi
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_11
# %bb.7: # %._crit_edge
cmpq $0, 80(%rsp)
je .LBB1_11
# %bb.8: # %._crit_edge
cmpq $0, 72(%rsp)
je .LBB1_11
# %bb.9: # %._crit_edge
cmpq $0, 64(%rsp)
je .LBB1_11
# %bb.10: # %._crit_edge
cmpq $0, 24(%rsp)
je .LBB1_11
# %bb.12:
movq 168(%rsp), %rsi # 8-byte Reload
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq 160(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movq %r12, %rsi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
leal 16383(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $14, %esi
movl 4(%rsp), %ecx
leal 16383(%rcx), %edx
testl %ecx, %ecx
cmovnsl %ecx, %edx
sarl $14, %edx
andl $16383, %eax # imm = 0x3FFF
cmpl $1, %eax
sbbl $-1, %esi
movl %esi, 32(%rsp) # 4-byte Spill
xorl %eax, %eax
testl $16383, %ecx # imm = 0x3FFF
setne %al
addl %edx, %eax
movl %eax, 116(%rsp) # 4-byte Spill
jle .LBB1_23
# %bb.13: # %.lr.ph150
movl %r15d, %eax
shll $5, %eax
movabsq $4294967328, %rcx # imm = 0x100000020
movl %eax, 56(%rsp) # 4-byte Spill
movl %eax, %r14d
leaq 480(%rcx), %rax
movq %rax, 208(%rsp) # 8-byte Spill
xorl %r12d, %r12d
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_22: # %._crit_edge147
# in Loop: Header=BB1_14 Depth=1
movl 44(%rsp), %r12d # 4-byte Reload
incl %r12d
cmpl 116(%rsp), %r12d # 4-byte Folded Reload
je .LBB1_23
.LBB1_14: # =>This Loop Header: Depth=1
# Child Loop BB1_16 Depth 2
# Child Loop BB1_20 Depth 3
cmpb $0, 48(%rsp) # 1-byte Folded Reload
movl %r12d, 44(%rsp) # 4-byte Spill
movl $0, %eax
cmovnel %eax, %r12d
cmpl 32(%rsp), %r12d # 4-byte Folded Reload
jge .LBB1_22
# %bb.15: # in Loop: Header=BB1_14 Depth=1
movl 44(%rsp), %eax # 4-byte Reload
shll $14, %eax
movl %eax, 124(%rsp) # 4-byte Spill
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_21: # %._crit_edge143
# in Loop: Header=BB1_16 Depth=2
incl %r12d
cmpl 32(%rsp), %r12d # 4-byte Folded Reload
je .LBB1_22
.LBB1_16: # %.lr.ph146
# Parent Loop BB1_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_20 Depth 3
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movabsq $4294967328, %rdi # imm = 0x100000020
movl $1, %esi
movq 208(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_18
# %bb.17: # in Loop: Header=BB1_16 Depth=2
movq 104(%rsp), %rax
movq %rax, 296(%rsp)
movq 80(%rsp), %rax
movq %rax, 288(%rsp)
movq 72(%rsp), %rax
movq %rax, 280(%rsp)
movq 64(%rsp), %rax
movq %rax, 272(%rsp)
movl %r12d, %eax
shll $14, %eax
movl %eax, 156(%rsp)
movl 12(%rsp), %eax
movl %eax, 148(%rsp)
movl 4(%rsp), %eax
movl %eax, 144(%rsp)
movq 24(%rsp), %rax
movq %rax, 264(%rsp)
movl 124(%rsp), %eax # 4-byte Reload
movl %eax, 152(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 140(%rsp)
movss 120(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 136(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 132(%rsp)
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 128(%rsp)
movl 48(%rsp), %eax # 4-byte Reload
movb %al, 3(%rsp)
leaq 296(%rsp), %rax
movq %rax, 304(%rsp)
leaq 288(%rsp), %rax
movq %rax, 312(%rsp)
leaq 280(%rsp), %rax
movq %rax, 320(%rsp)
leaq 272(%rsp), %rax
movq %rax, 328(%rsp)
leaq 156(%rsp), %rax
movq %rax, 336(%rsp)
leaq 152(%rsp), %rax
movq %rax, 344(%rsp)
leaq 148(%rsp), %rax
movq %rax, 352(%rsp)
leaq 144(%rsp), %rax
movq %rax, 360(%rsp)
leaq 264(%rsp), %rax
movq %rax, 368(%rsp)
leaq 140(%rsp), %rax
movq %rax, 376(%rsp)
leaq 136(%rsp), %rax
movq %rax, 384(%rsp)
leaq 132(%rsp), %rax
movq %rax, 392(%rsp)
leaq 128(%rsp), %rax
movq %rax, 400(%rsp)
leaq 3(%rsp), %rax
movq %rax, 408(%rsp)
leaq 248(%rsp), %rdi
leaq 232(%rsp), %rsi
leaq 224(%rsp), %rdx
leaq 216(%rsp), %rcx
callq __hipPopCallConfiguration
movq 248(%rsp), %rsi
movl 256(%rsp), %edx
movq 232(%rsp), %rcx
movl 240(%rsp), %r8d
movl $_Z8distancePVfS0_S0_S0_iiiiPViffifb, %edi
leaq 304(%rsp), %r9
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_18: # in Loop: Header=BB1_16 Depth=2
movq 24(%rsp), %rsi
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 56(%rsp) # 4-byte Folded Reload
jle .LBB1_21
# %bb.19: # %.lr.ph142.preheader
# in Loop: Header=BB1_16 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_20: # %.lr.ph142
# Parent Loop BB1_14 Depth=1
# Parent Loop BB1_16 Depth=2
# => This Inner Loop Header: Depth=3
movl %ecx, %eax
cltd
idivl %r15d
# kill: def $edx killed $edx def $rdx
movslq (%r13,%rcx,4), %rax
addq %rax, (%rbp,%rdx,8)
incq %rcx
cmpq %rcx, %r14
jne .LBB1_20
jmp .LBB1_21
.LBB1_11:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
jmp .LBB1_28
.LBB1_23: # %.preheader
movq 96(%rsp), %rbx # 8-byte Reload
testl %ebx, %ebx
jle .LBB1_24
# %bb.25: # %.lr.ph155.preheader
incl %ebx
movl $1, %r12d
xorl %r14d, %r14d
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_26: # %.lr.ph155
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
addss 52(%rsp), %xmm1 # 4-byte Folded Reload
movss %xmm1, 8(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movq (%rbp,%r12,8), %r15
movl $.L.str.5, %esi
movq 192(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movb $2, %al
callq fprintf
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addq %r15, %r14
incq %r12
cmpq %r12, %rbx
jne .LBB1_26
jmp .LBB1_27
.LBB1_24:
xorl %r14d, %r14d
.LBB1_27: # %._crit_edge156
movl $.L.str.6, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movq 200(%rsp), %rdi # 8-byte Reload
callq fclose
movq 184(%rsp), %rdi # 8-byte Reload
callq fclose
movq 192(%rsp), %rdi # 8-byte Reload
callq fclose
movq 168(%rsp), %rdi # 8-byte Reload
callq free
movq 160(%rsp), %rdi # 8-byte Reload
callq free
movq 176(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 104(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB1_28:
# kill: def $eax killed $eax killed $rax
addq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4calcP8_IO_FILES0_S0_ifffb, .Lfunc_end1-_Z4calcP8_IO_FILES0_S0_ifffb
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x33d6bf95 # float 1.00000001E-7
.LCPI2_1:
.long 0x42800000 # float 64
.LCPI2_2:
.long 0x3e800000 # float 0.25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %ebp
callq clock
cmpl $3, %ebp
jne .LBB2_4
# %bb.1:
movq %rax, %rbx
movslq optind(%rip), %rax
movq (%r15,%rax,8), %rdi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r14
movslq optind(%rip), %rax
movq 8(%r15,%rax,8), %rdi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r12
movl $.L.str.9, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r13
movslq optind(%rip), %rax
movq (%r15,%rax,8), %rdi
movq 8(%r15,%rax,8), %rsi
callq strcmp
movl %eax, %ebp
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB2_3:
xorl %r8d, %r8d
testl %ebp, %ebp
setne %r8b
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $256, %ecx # imm = 0x100
callq _Z4calcP8_IO_FILES0_S0_ifffb
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_3(%rip), %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 64
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8distancePVfS0_S0_S0_iiiiPViffifb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8distancePVfS0_S0_S0_iiiiPViffifb,@object # @_Z8distancePVfS0_S0_S0_iiiiPViffifb
.section .rodata,"a",@progbits
.globl _Z8distancePVfS0_S0_S0_iiiiPViffifb
.p2align 3, 0x0
_Z8distancePVfS0_S0_S0_iiiiPViffifb:
.quad _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.size _Z8distancePVfS0_S0_S0_iiiiPViffifb, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "SIZE 0 # GALAXIES: %d\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "SIZE 1 # GALAXIES: %d\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f %f"
.size .L.str.3, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%.3e %.3e %lu \n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "total: %lu \n"
.size .L.str.6, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "r"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "output.txt"
.size .L.str.9, 11
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "w"
.size .L.str.10, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Execution time: %f \n"
.size .L.str.12, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8distancePVfS0_S0_S0_iiiiPViffifb"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate enough memory in GPU"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Input files are the same!"
.size .Lstr.1, 26
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nMust pass two input files."
.size .Lstr.2, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8distancePVfS0_S0_S0_iiiiPViffifb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00009041_00000000-6_project.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
.type _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb, @function
_Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb:
.LFB2096:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq 288(%rsp), %rax
movq %rax, 16(%rsp)
movl 304(%rsp), %eax
movb %al, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 4(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8distancePVfS0_S0_S0_iiiiPViffifb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb, .-_Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
.globl _Z8distancePVfS0_S0_S0_iiiiPViffifb
.type _Z8distancePVfS0_S0_S0_iiiiPViffifb, @function
_Z8distancePVfS0_S0_S0_iiiiPViffifb:
.LFB2097:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movzbl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8distancePVfS0_S0_S0_iiiiPViffifb, .-_Z8distancePVfS0_S0_S0_iiiiPViffifb
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "SIZE 0 # GALAXIES: %d\n"
.LC2:
.string "SIZE 1 # GALAXIES: %d\n"
.LC3:
.string "%f %f"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "couldn't allocate enough memory in GPU\n"
.section .rodata.str1.1
.LC6:
.string "%.3e %.3e %lu \n"
.LC7:
.string "total: %lu \n"
.text
.globl _Z4calcP8_IO_FILES0_S0_ifffb
.type _Z4calcP8_IO_FILES0_S0_ifffb, @function
_Z4calcP8_IO_FILES0_S0_ifffb:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 32(%rsp)
movq %rsi, %r14
movq %rsi, 40(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 48(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 52(%rsp)
movss %xmm2, 20(%rsp)
movb %r8b, 75(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rdx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call __isoc23_fscanf@PLT
leaq 124(%rsp), %rdx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 120(%rsp), %ebp
movl 124(%rsp), %eax
leal 0(,%rax,4), %r15d
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 124(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
sall $2, %ebp
movslq %ebp, %rbx
movq %rbx, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 104(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 80(%rsp)
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 88(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, 96(%rsp)
cmpl $0, 120(%rsp)
jle .L12
movl $0, %ebx
leaq 132(%rsp), %r13
leaq 128(%rsp), %r12
leaq .LC3(%rip), %rbp
movq %r15, 24(%rsp)
movq 80(%rsp), %r15
.L13:
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
pxor %xmm0, %xmm0
cvtss2sd 128(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%rbx,4)
pxor %xmm0, %xmm0
cvtss2sd 132(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx,4)
addq $1, %rbx
cmpl %ebx, 120(%rsp)
jg .L13
movq 24(%rsp), %r15
.L12:
cmpl $0, 124(%rsp)
jle .L14
movl $0, %ebx
leaq 132(%rsp), %r13
leaq 128(%rsp), %r12
leaq .LC3(%rip), %rbp
movq %r15, 24(%rsp)
movq 88(%rsp), %r14
movq 96(%rsp), %r15
.L15:
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
pxor %xmm0, %xmm0
cvtss2sd 128(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%rbx,4)
pxor %xmm0, %xmm0
cvtss2sd 132(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx,4)
addq $1, %rbx
cmpl %ebx, 124(%rsp)
jg .L15
movq 24(%rsp), %r15
.L14:
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
movl $512, 188(%rsp)
movl 48(%rsp), %eax
leal 2(%rax), %ebp
movl %ebp, %r13d
sall $5, %r13d
movl %ebp, %r14d
sall $7, %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rcx
movq %r14, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 168(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq 168(%rsp), %rdi
call cudaMemset@PLT
leal 0(,%rbp,8), %eax
cltq
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movq 24(%rsp), %rdx
movq %rdx, %rcx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 136(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 152(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 160(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq 136(%rsp), %rdi
testq %rdi, %rdi
je .L16
cmpq $0, 144(%rsp)
je .L16
cmpq $0, 152(%rsp)
je .L16
cmpq $0, 160(%rsp)
je .L16
cmpq $0, 168(%rsp)
je .L16
movl $1, %ecx
movq 8(%rsp), %rdx
movq 104(%rsp), %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movq 8(%rsp), %rdx
movq 80(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 88(%rsp), %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 96(%rsp), %rsi
movq 160(%rsp), %rdi
call cudaMemcpy@PLT
movl 120(%rsp), %edx
leal 16383(%rdx), %esi
testl %edx, %edx
cmovns %edx, %esi
sarl $14, %esi
movl 124(%rsp), %eax
leal 16383(%rax), %ecx
testl %eax, %eax
cmovns %eax, %ecx
sarl $14, %ecx
andl $16383, %edx
cmpl $1, %edx
sbbl $-1, %esi
movl %esi, 8(%rsp)
andl $16383, %eax
cmpl $1, %eax
sbbl $-1, %ecx
movl %ecx, 76(%rsp)
testl %ecx, %ecx
jle .L21
movl $0, %edx
movzbl 75(%rsp), %eax
movl %eax, 56(%rsp)
jmp .L28
.L16:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L11:
movq 200(%rsp), %rdx
subq %fs:40, %rdx
jne .L41
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $2, %ecx
movq %r14, %rdx
movq 168(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L25
movl $0, %ecx
.L26:
movl %ecx, %eax
cltd
idivl %ebp
movslq %edx, %rdx
movslq (%r12,%rcx,4), %rax
addq %rax, (%rbx,%rdx,8)
addq $1, %rcx
cmpl %ecx, %r13d
jg .L26
.L25:
addl $1, %r15d
cmpl %r15d, 8(%rsp)
je .L42
.L27:
movq %r14, %rdx
movl $0, %esi
movq 168(%rsp), %rdi
call cudaMemset@PLT
movl $32, 176(%rsp)
movl 196(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 188(%rsp), %rdx
movq 176(%rsp), %rdi
movl 184(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L24
subq $8, %rsp
.cfi_def_cfa_offset 280
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 288
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 296
pushq 192(%rsp)
.cfi_def_cfa_offset 304
movl 156(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 312
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 320
movss 68(%rsp), %xmm2
movss 100(%rsp), %xmm1
movss 64(%rsp), %xmm0
movl 72(%rsp), %r9d
movl %r15d, %r8d
sall $14, %r8d
movq 208(%rsp), %rcx
movq 200(%rsp), %rdx
movq 192(%rsp), %rsi
movq 184(%rsp), %rdi
call _Z49__device_stub__Z8distancePVfS0_S0_S0_iiiiPViffifbPVfS0_S0_S0_iiiiPViffifb
addq $48, %rsp
.cfi_def_cfa_offset 272
jmp .L24
.L42:
movl 60(%rsp), %edx
.L23:
addl $1, %edx
cmpl %edx, 76(%rsp)
je .L21
.L28:
movl %edx, %eax
sall $14, %eax
movl %eax, 24(%rsp)
cmpb $0, 75(%rsp)
movl $0, %r15d
cmove %edx, %r15d
movl 8(%rsp), %eax
cmpl %eax, %r15d
jge .L23
movl %edx, 60(%rsp)
jmp .L27
.L21:
movl 48(%rsp), %r13d
testl %r13d, %r13d
jle .L33
movl $1, %ebp
movl $0, %r14d
leaq .LC6(%rip), %r15
movq %r12, 8(%rsp)
.L30:
movss 16(%rsp), %xmm3
movaps %xmm3, %xmm0
addss 20(%rsp), %xmm3
movss %xmm3, 16(%rsp)
movq (%rbx,%rbp,8), %r12
cvtss2sd %xmm0, %xmm0
movq %r12, %rcx
pxor %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movq %r15, %rdx
movl $2, %esi
movq 64(%rsp), %rdi
movl $2, %eax
call __fprintf_chk@PLT
addq %r12, %r14
addq $1, %rbp
cmpl %ebp, %r13d
jge .L30
movq 8(%rsp), %r12
.L29:
movq %r14, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call fclose@PLT
movq 40(%rsp), %rdi
call fclose@PLT
movq 64(%rsp), %rdi
call fclose@PLT
movq 104(%rsp), %rdi
call free@PLT
movq 80(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rdi
call free@PLT
movq 96(%rsp), %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 160(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L11
.L33:
movl $0, %r14d
jmp .L29
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z4calcP8_IO_FILES0_S0_ifffb, .-_Z4calcP8_IO_FILES0_S0_ifffb
.section .rodata.str1.1
.LC8:
.string "\nMust pass two input files.\n"
.LC9:
.string "r"
.LC10:
.string "w"
.LC11:
.string "output.txt"
.LC12:
.string "Input files are the same!\n"
.LC17:
.string "Execution time: %f \n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movq %rsi, %rbx
call clock@PLT
movq %rax, _ZL10start_time(%rip)
cmpl $3, %ebp
jne .L48
movslq optind(%rip), %rax
movq (%rbx,%rax,8), %rdi
leaq .LC9(%rip), %r12
movq %r12, %rsi
call fopen@PLT
movq %rax, %rbp
movslq optind(%rip), %rax
movq 8(%rbx,%rax,8), %rdi
movq %r12, %rsi
call fopen@PLT
movq %rax, %r12
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movslq optind(%rip), %rax
addq $1, %rax
movq (%rbx,%rax,8), %rsi
movq -8(%rbx,%rax,8), %rdi
call strcmp@PLT
movl $1, %r8d
testl %eax, %eax
je .L49
.L45:
andl $1, %r8d
movss .LC13(%rip), %xmm2
movss .LC14(%rip), %xmm1
movss .LC15(%rip), %xmm0
movl $256, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z4calcP8_IO_FILES0_S0_ifffb
call clock@PLT
subq _ZL10start_time(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC16(%rip), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
leaq .LC12(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %r8d
jmp .L45
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z8distancePVfS0_S0_S0_iiiiPViffifb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z8distancePVfS0_S0_S0_iiiiPViffifb(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10start_time
.comm _ZL10start_time,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 1553060174
.long 1084939134
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1048576000
.align 4
.LC14:
.long 1115684864
.align 4
.LC15:
.long 869711765
.section .rodata.cst8
.align 8
.LC16:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "project.hip"
.globl _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb # -- Begin function _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.p2align 4, 0x90
.type _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb,@function
_Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb: # @_Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movzbl 272(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movb %al, 11(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 11(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8distancePVfS0_S0_S0_iiiiPViffifb, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb, .Lfunc_end0-_Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4calcP8_IO_FILES0_S0_ifffb
.LCPI1_0:
.quad 0x40aadb7e5c91d14e # double 3437.7467999999999
.text
.globl _Z4calcP8_IO_FILES0_S0_ifffb
.p2align 4, 0x90
.type _Z4calcP8_IO_FILES0_S0_ifffb,@function
_Z4calcP8_IO_FILES0_S0_ifffb: # @_Z4calcP8_IO_FILES0_S0_ifffb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 48(%rsp) # 4-byte Spill
movss %xmm2, 52(%rsp) # 4-byte Spill
movss %xmm1, 120(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
movq %rcx, 96(%rsp) # 8-byte Spill
movq %rdx, 192(%rsp) # 8-byte Spill
movq %rsi, %rbx
movq %rdi, %r14
leaq 12(%rsp), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 4(%rsp), %rdx
movl $.L.str, %esi
movq %rbx, 184(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %esi
leal (,%rsi,4), %ebp
movl 4(%rsp), %ebx
shll $2, %ebx
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl 4(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movslq %ebp, %r15
movq %r14, %rbp
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, 56(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r13
movslq %ebx, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 176(%rsp) # 8-byte Spill
movq %rbx, 32(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 20(%rsp), %rbx
leaq 16(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%r15,4)
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%r15,4)
incq %r15
movslq 12(%rsp), %rax
cmpq %rax, %r15
jl .LBB1_2
.LBB1_3: # %.preheader136
movq %r13, 160(%rsp) # 8-byte Spill
movq %r12, 168(%rsp) # 8-byte Spill
movq %rbp, 200(%rsp) # 8-byte Spill
cmpl $0, 4(%rsp)
movq 176(%rsp), %r12 # 8-byte Reload
movq 88(%rsp), %r13 # 8-byte Reload
movq 184(%rsp), %rbp # 8-byte Reload
jle .LBB1_6
# %bb.4: # %.lr.ph139.preheader
leaq 20(%rsp), %rbx
leaq 16(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph139
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %rbp, %rdi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%r15,4)
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%r15,4)
incq %r15
movslq 4(%rsp), %rax
cmpq %rax, %r15
jl .LBB1_5
.LBB1_6: # %._crit_edge
movq 96(%rsp), %r14 # 8-byte Reload
leal 2(%r14), %r15d
movl %r15d, %eax
shll $7, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
leal 16(,%r14,8), %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %rax, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
leaq 104(%rsp), %rdi
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_11
# %bb.7: # %._crit_edge
cmpq $0, 80(%rsp)
je .LBB1_11
# %bb.8: # %._crit_edge
cmpq $0, 72(%rsp)
je .LBB1_11
# %bb.9: # %._crit_edge
cmpq $0, 64(%rsp)
je .LBB1_11
# %bb.10: # %._crit_edge
cmpq $0, 24(%rsp)
je .LBB1_11
# %bb.12:
movq 168(%rsp), %rsi # 8-byte Reload
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq 160(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movq %r12, %rsi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
leal 16383(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $14, %esi
movl 4(%rsp), %ecx
leal 16383(%rcx), %edx
testl %ecx, %ecx
cmovnsl %ecx, %edx
sarl $14, %edx
andl $16383, %eax # imm = 0x3FFF
cmpl $1, %eax
sbbl $-1, %esi
movl %esi, 32(%rsp) # 4-byte Spill
xorl %eax, %eax
testl $16383, %ecx # imm = 0x3FFF
setne %al
addl %edx, %eax
movl %eax, 116(%rsp) # 4-byte Spill
jle .LBB1_23
# %bb.13: # %.lr.ph150
movl %r15d, %eax
shll $5, %eax
movabsq $4294967328, %rcx # imm = 0x100000020
movl %eax, 56(%rsp) # 4-byte Spill
movl %eax, %r14d
leaq 480(%rcx), %rax
movq %rax, 208(%rsp) # 8-byte Spill
xorl %r12d, %r12d
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_22: # %._crit_edge147
# in Loop: Header=BB1_14 Depth=1
movl 44(%rsp), %r12d # 4-byte Reload
incl %r12d
cmpl 116(%rsp), %r12d # 4-byte Folded Reload
je .LBB1_23
.LBB1_14: # =>This Loop Header: Depth=1
# Child Loop BB1_16 Depth 2
# Child Loop BB1_20 Depth 3
cmpb $0, 48(%rsp) # 1-byte Folded Reload
movl %r12d, 44(%rsp) # 4-byte Spill
movl $0, %eax
cmovnel %eax, %r12d
cmpl 32(%rsp), %r12d # 4-byte Folded Reload
jge .LBB1_22
# %bb.15: # in Loop: Header=BB1_14 Depth=1
movl 44(%rsp), %eax # 4-byte Reload
shll $14, %eax
movl %eax, 124(%rsp) # 4-byte Spill
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_21: # %._crit_edge143
# in Loop: Header=BB1_16 Depth=2
incl %r12d
cmpl 32(%rsp), %r12d # 4-byte Folded Reload
je .LBB1_22
.LBB1_16: # %.lr.ph146
# Parent Loop BB1_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_20 Depth 3
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movabsq $4294967328, %rdi # imm = 0x100000020
movl $1, %esi
movq 208(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_18
# %bb.17: # in Loop: Header=BB1_16 Depth=2
movq 104(%rsp), %rax
movq %rax, 296(%rsp)
movq 80(%rsp), %rax
movq %rax, 288(%rsp)
movq 72(%rsp), %rax
movq %rax, 280(%rsp)
movq 64(%rsp), %rax
movq %rax, 272(%rsp)
movl %r12d, %eax
shll $14, %eax
movl %eax, 156(%rsp)
movl 12(%rsp), %eax
movl %eax, 148(%rsp)
movl 4(%rsp), %eax
movl %eax, 144(%rsp)
movq 24(%rsp), %rax
movq %rax, 264(%rsp)
movl 124(%rsp), %eax # 4-byte Reload
movl %eax, 152(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 140(%rsp)
movss 120(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 136(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 132(%rsp)
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 128(%rsp)
movl 48(%rsp), %eax # 4-byte Reload
movb %al, 3(%rsp)
leaq 296(%rsp), %rax
movq %rax, 304(%rsp)
leaq 288(%rsp), %rax
movq %rax, 312(%rsp)
leaq 280(%rsp), %rax
movq %rax, 320(%rsp)
leaq 272(%rsp), %rax
movq %rax, 328(%rsp)
leaq 156(%rsp), %rax
movq %rax, 336(%rsp)
leaq 152(%rsp), %rax
movq %rax, 344(%rsp)
leaq 148(%rsp), %rax
movq %rax, 352(%rsp)
leaq 144(%rsp), %rax
movq %rax, 360(%rsp)
leaq 264(%rsp), %rax
movq %rax, 368(%rsp)
leaq 140(%rsp), %rax
movq %rax, 376(%rsp)
leaq 136(%rsp), %rax
movq %rax, 384(%rsp)
leaq 132(%rsp), %rax
movq %rax, 392(%rsp)
leaq 128(%rsp), %rax
movq %rax, 400(%rsp)
leaq 3(%rsp), %rax
movq %rax, 408(%rsp)
leaq 248(%rsp), %rdi
leaq 232(%rsp), %rsi
leaq 224(%rsp), %rdx
leaq 216(%rsp), %rcx
callq __hipPopCallConfiguration
movq 248(%rsp), %rsi
movl 256(%rsp), %edx
movq 232(%rsp), %rcx
movl 240(%rsp), %r8d
movl $_Z8distancePVfS0_S0_S0_iiiiPViffifb, %edi
leaq 304(%rsp), %r9
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_18: # in Loop: Header=BB1_16 Depth=2
movq 24(%rsp), %rsi
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 56(%rsp) # 4-byte Folded Reload
jle .LBB1_21
# %bb.19: # %.lr.ph142.preheader
# in Loop: Header=BB1_16 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_20: # %.lr.ph142
# Parent Loop BB1_14 Depth=1
# Parent Loop BB1_16 Depth=2
# => This Inner Loop Header: Depth=3
movl %ecx, %eax
cltd
idivl %r15d
# kill: def $edx killed $edx def $rdx
movslq (%r13,%rcx,4), %rax
addq %rax, (%rbp,%rdx,8)
incq %rcx
cmpq %rcx, %r14
jne .LBB1_20
jmp .LBB1_21
.LBB1_11:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
jmp .LBB1_28
.LBB1_23: # %.preheader
movq 96(%rsp), %rbx # 8-byte Reload
testl %ebx, %ebx
jle .LBB1_24
# %bb.25: # %.lr.ph155.preheader
incl %ebx
movl $1, %r12d
xorl %r14d, %r14d
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_26: # %.lr.ph155
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
addss 52(%rsp), %xmm1 # 4-byte Folded Reload
movss %xmm1, 8(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movq (%rbp,%r12,8), %r15
movl $.L.str.5, %esi
movq 192(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movb $2, %al
callq fprintf
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addq %r15, %r14
incq %r12
cmpq %r12, %rbx
jne .LBB1_26
jmp .LBB1_27
.LBB1_24:
xorl %r14d, %r14d
.LBB1_27: # %._crit_edge156
movl $.L.str.6, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movq 200(%rsp), %rdi # 8-byte Reload
callq fclose
movq 184(%rsp), %rdi # 8-byte Reload
callq fclose
movq 192(%rsp), %rdi # 8-byte Reload
callq fclose
movq 168(%rsp), %rdi # 8-byte Reload
callq free
movq 160(%rsp), %rdi # 8-byte Reload
callq free
movq 176(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 104(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB1_28:
# kill: def $eax killed $eax killed $rax
addq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4calcP8_IO_FILES0_S0_ifffb, .Lfunc_end1-_Z4calcP8_IO_FILES0_S0_ifffb
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x33d6bf95 # float 1.00000001E-7
.LCPI2_1:
.long 0x42800000 # float 64
.LCPI2_2:
.long 0x3e800000 # float 0.25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %ebp
callq clock
cmpl $3, %ebp
jne .LBB2_4
# %bb.1:
movq %rax, %rbx
movslq optind(%rip), %rax
movq (%r15,%rax,8), %rdi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r14
movslq optind(%rip), %rax
movq 8(%r15,%rax,8), %rdi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r12
movl $.L.str.9, %edi
movl $.L.str.10, %esi
callq fopen
movq %rax, %r13
movslq optind(%rip), %rax
movq (%r15,%rax,8), %rdi
movq 8(%r15,%rax,8), %rsi
callq strcmp
movl %eax, %ebp
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB2_3:
xorl %r8d, %r8d
testl %ebp, %ebp
setne %r8b
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $256, %ecx # imm = 0x100
callq _Z4calcP8_IO_FILES0_S0_ifffb
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_3(%rip), %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 64
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8distancePVfS0_S0_S0_iiiiPViffifb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8distancePVfS0_S0_S0_iiiiPViffifb,@object # @_Z8distancePVfS0_S0_S0_iiiiPViffifb
.section .rodata,"a",@progbits
.globl _Z8distancePVfS0_S0_S0_iiiiPViffifb
.p2align 3, 0x0
_Z8distancePVfS0_S0_S0_iiiiPViffifb:
.quad _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.size _Z8distancePVfS0_S0_S0_iiiiPViffifb, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "SIZE 0 # GALAXIES: %d\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "SIZE 1 # GALAXIES: %d\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f %f"
.size .L.str.3, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%.3e %.3e %lu \n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "total: %lu \n"
.size .L.str.6, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "r"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "output.txt"
.size .L.str.9, 11
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "w"
.size .L.str.10, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Execution time: %f \n"
.size .L.str.12, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8distancePVfS0_S0_S0_iiiiPViffifb"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate enough memory in GPU"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Input files are the same!"
.size .Lstr.1, 26
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nMust pass two input files."
.size .Lstr.2, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__distancePVfS0_S0_S0_iiiiPViffifb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8distancePVfS0_S0_S0_iiiiPViffifb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void mapToNumb(
const int N, //Number of whole threads
const int M, //Length of subseq that one thread handles
char* seq,
int* numb_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, letter;
if(idx < N*M) {
for(i=0; i < M; i++) {
letter = seq[idx+i];
if(letter == 'A') {
numb_seq[idx+i] = 0;
} else {
if(letter == 'C') {
numb_seq[idx+i] = 1;
} else {
if(letter == 'G') {
numb_seq[idx+i] = 2;
} else {
if(letter == 'U') {
numb_seq[idx+i] = 3;
} else {
numb_seq[idx+i] = (-1) * (int)(powf(4, (float)3));
}
}
}
}
}
}
}
__global__ void genNumbCodon(
const int N,
const int M,
int* numb_seq,
int* codon_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, k;
int codon_numb, loc_idx, numb, base;
for(i=0; i < M; i++) {
codon_numb = 0;
loc_idx = idx + i;
if(loc_idx <= N*M -3 + 1) {
for(k=0; k<3; k++) {
numb = numb_seq[loc_idx];
base = (int)powf(4, (float)(2-k));
codon_numb += numb * base;
}
codon_seq[loc_idx] = codon_numb;
}
}
}
__global__ void mapToAA(
const int N,
const int M,
char* rna_codon_tab,
int* codon_seq,
char* aa_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int codon_idx, loc_idx;
int i;
for(i=0; i < M; i++) {
loc_idx = idx + i;
codon_idx = codon_seq[loc_idx];
if(loc_idx <= N*M -3 + 1) {
if(codon_idx >= 0) {
aa_seq[loc_idx] = rna_codon_tab[codon_idx];
}
}
}
} | .file "tmpxft_000c0d36_00000000-6_proteinTrans.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi
.type _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi, @function
_Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mapToNumbiiPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi, .-_Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi
.globl _Z9mapToNumbiiPcPi
.type _Z9mapToNumbiiPcPi, @function
_Z9mapToNumbiiPcPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9mapToNumbiiPcPi, .-_Z9mapToNumbiiPcPi
.globl _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_
.type _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_, @function
_Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12genNumbCodoniiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_, .-_Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_
.globl _Z12genNumbCodoniiPiS_
.type _Z12genNumbCodoniiPiS_, @function
_Z12genNumbCodoniiPiS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z12genNumbCodoniiPiS_, .-_Z12genNumbCodoniiPiS_
.globl _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_
.type _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_, @function
_Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mapToAAiiPcPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_, .-_Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_
.globl _Z7mapToAAiiPcPiS_
.type _Z7mapToAAiiPcPiS_, @function
_Z7mapToAAiiPcPiS_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7mapToAAiiPcPiS_, .-_Z7mapToAAiiPcPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7mapToAAiiPcPiS_"
.LC1:
.string "_Z12genNumbCodoniiPiS_"
.LC2:
.string "_Z9mapToNumbiiPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mapToAAiiPcPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12genNumbCodoniiPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mapToNumbiiPcPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void mapToNumb(
const int N, //Number of whole threads
const int M, //Length of subseq that one thread handles
char* seq,
int* numb_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, letter;
if(idx < N*M) {
for(i=0; i < M; i++) {
letter = seq[idx+i];
if(letter == 'A') {
numb_seq[idx+i] = 0;
} else {
if(letter == 'C') {
numb_seq[idx+i] = 1;
} else {
if(letter == 'G') {
numb_seq[idx+i] = 2;
} else {
if(letter == 'U') {
numb_seq[idx+i] = 3;
} else {
numb_seq[idx+i] = (-1) * (int)(powf(4, (float)3));
}
}
}
}
}
}
}
__global__ void genNumbCodon(
const int N,
const int M,
int* numb_seq,
int* codon_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, k;
int codon_numb, loc_idx, numb, base;
for(i=0; i < M; i++) {
codon_numb = 0;
loc_idx = idx + i;
if(loc_idx <= N*M -3 + 1) {
for(k=0; k<3; k++) {
numb = numb_seq[loc_idx];
base = (int)powf(4, (float)(2-k));
codon_numb += numb * base;
}
codon_seq[loc_idx] = codon_numb;
}
}
}
__global__ void mapToAA(
const int N,
const int M,
char* rna_codon_tab,
int* codon_seq,
char* aa_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int codon_idx, loc_idx;
int i;
for(i=0; i < M; i++) {
loc_idx = idx + i;
codon_idx = codon_seq[loc_idx];
if(loc_idx <= N*M -3 + 1) {
if(codon_idx >= 0) {
aa_seq[loc_idx] = rna_codon_tab[codon_idx];
}
}
}
} | #include <hip/hip_runtime.h>
__global__ void mapToNumb(
const int N, //Number of whole threads
const int M, //Length of subseq that one thread handles
char* seq,
int* numb_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, letter;
if(idx < N*M) {
for(i=0; i < M; i++) {
letter = seq[idx+i];
if(letter == 'A') {
numb_seq[idx+i] = 0;
} else {
if(letter == 'C') {
numb_seq[idx+i] = 1;
} else {
if(letter == 'G') {
numb_seq[idx+i] = 2;
} else {
if(letter == 'U') {
numb_seq[idx+i] = 3;
} else {
numb_seq[idx+i] = (-1) * (int)(powf(4, (float)3));
}
}
}
}
}
}
}
__global__ void genNumbCodon(
const int N,
const int M,
int* numb_seq,
int* codon_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, k;
int codon_numb, loc_idx, numb, base;
for(i=0; i < M; i++) {
codon_numb = 0;
loc_idx = idx + i;
if(loc_idx <= N*M -3 + 1) {
for(k=0; k<3; k++) {
numb = numb_seq[loc_idx];
base = (int)powf(4, (float)(2-k));
codon_numb += numb * base;
}
codon_seq[loc_idx] = codon_numb;
}
}
}
__global__ void mapToAA(
const int N,
const int M,
char* rna_codon_tab,
int* codon_seq,
char* aa_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int codon_idx, loc_idx;
int i;
for(i=0; i < M; i++) {
loc_idx = idx + i;
codon_idx = codon_seq[loc_idx];
if(loc_idx <= N*M -3 + 1) {
if(codon_idx >= 0) {
aa_seq[loc_idx] = rna_codon_tab[codon_idx];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void mapToNumb(
const int N, //Number of whole threads
const int M, //Length of subseq that one thread handles
char* seq,
int* numb_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, letter;
if(idx < N*M) {
for(i=0; i < M; i++) {
letter = seq[idx+i];
if(letter == 'A') {
numb_seq[idx+i] = 0;
} else {
if(letter == 'C') {
numb_seq[idx+i] = 1;
} else {
if(letter == 'G') {
numb_seq[idx+i] = 2;
} else {
if(letter == 'U') {
numb_seq[idx+i] = 3;
} else {
numb_seq[idx+i] = (-1) * (int)(powf(4, (float)3));
}
}
}
}
}
}
}
__global__ void genNumbCodon(
const int N,
const int M,
int* numb_seq,
int* codon_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, k;
int codon_numb, loc_idx, numb, base;
for(i=0; i < M; i++) {
codon_numb = 0;
loc_idx = idx + i;
if(loc_idx <= N*M -3 + 1) {
for(k=0; k<3; k++) {
numb = numb_seq[loc_idx];
base = (int)powf(4, (float)(2-k));
codon_numb += numb * base;
}
codon_seq[loc_idx] = codon_numb;
}
}
}
__global__ void mapToAA(
const int N,
const int M,
char* rna_codon_tab,
int* codon_seq,
char* aa_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int codon_idx, loc_idx;
int i;
for(i=0; i < M; i++) {
loc_idx = idx + i;
codon_idx = codon_seq[loc_idx];
if(loc_idx <= N*M -3 + 1) {
if(codon_idx >= 0) {
aa_seq[loc_idx] = rna_codon_tab[codon_idx];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mapToNumbiiPcPi
.globl _Z9mapToNumbiiPcPi
.p2align 8
.type _Z9mapToNumbiiPcPi,@function
_Z9mapToNumbiiPcPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cmp_gt_i32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s3
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_23
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
s_cbranch_scc0 .LBB0_23
.LBB0_3:
global_load_u8 v5, v[0:1], off
s_mov_b32 s0, 0
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0x46, v5
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_13
s_mov_b32 s2, exec_lo
v_cmpx_lt_i16_e32 0x54, v5
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_8
s_mov_b32 s0, -1
s_mov_b32 s5, exec_lo
v_cmpx_eq_u16_e32 0x55, v5
s_mov_b32 s4, 3
s_xor_b32 s0, exec_lo, -1
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
.LBB0_8:
s_or_saveexec_b32 s2, s2
v_mov_b32_e32 v4, s4
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_12
s_mov_b32 s4, -1
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0x47, v5
s_mov_b32 s5, 2
s_xor_b32 s4, exec_lo, -1
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, s5
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s4, s4, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s4
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
.LBB0_13:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_21
s_mov_b32 s2, s0
s_mov_b32 s5, exec_lo
v_cmpx_lt_i16_e32 0x42, v5
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_18
s_mov_b32 s2, -1
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0x43, v5
s_mov_b32 s4, 1
s_xor_b32 s2, exec_lo, -1
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s6, s0, exec_lo
s_and_b32 s2, s2, exec_lo
s_or_b32 s2, s6, s2
.LBB0_18:
s_or_saveexec_b32 s5, s5
v_mov_b32_e32 v4, s4
s_xor_b32 exec_lo, exec_lo, s5
v_cmp_ne_u16_e32 vcc_lo, 0x41, v5
v_mov_b32_e32 v4, 0
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s4
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, s2, exec_lo
s_or_b32 s0, s0, s2
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, 0xffffffc0
s_branch .LBB0_2
.LBB0_23:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mapToNumbiiPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mapToNumbiiPcPi, .Lfunc_end0-_Z9mapToNumbiiPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12genNumbCodoniiPiS_
.globl _Z12genNumbCodoniiPiS_
.p2align 8
.type _Z12genNumbCodoniiPiS_,@function
_Z12genNumbCodoniiPiS_:
s_load_b32 s4, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_7
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
s_mov_b32 s7, 0x3e76c4e1
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mul_i32 s5, s4, s6
s_mov_b32 s6, 0
s_add_i32 s5, s5, -2
v_mul_lo_u32 v5, v1, s4
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, s4
s_cbranch_scc0 .LBB1_7
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s6, v5
s_mov_b32 s8, exec_lo
v_cmpx_ge_i32_e64 s5, v0
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s9, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v6, v[2:3], off
v_mov_b32_e32 v2, 0
.LBB1_5:
s_cmp_eq_u32 s9, 0
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 4.0, 1.0, s10
v_frexp_mant_f32_e32 v4, v3
v_frexp_exp_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v4, v4, v7
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, 1.0, v4
v_dual_add_f32 v8, -1.0, v4 :: v_dual_mul_f32 v11, 0x3f317218, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, -1.0, v7
v_sub_f32_e32 v4, v4, v10
v_rcp_f32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f32 v10, v3, 0x3f317218, -v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, v8, v9
v_dual_fmac_f32 v10, 0xb102e308, v3 :: v_dual_mul_f32 v3, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v12, v7, -v3
v_fmac_f32_e32 v7, v12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v3, v7
v_sub_f32_e32 v13, v8, v4
v_sub_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v8, v8, v13
v_sub_f32_e32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v3, v13, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v9, v3
v_add_f32_e32 v4, v12, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v4, v12
v_dual_mul_f32 v8, v4, v4 :: v_dual_sub_f32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, v4, v4, -v8
v_add_f32_e32 v12, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v4, v12
v_add_f32_e32 v12, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmaak_f32 v14, s7, v12, 0x3e91f4c4
v_sub_f32_e32 v8, v12, v8
v_ldexp_f32 v13, v3, 1
v_dual_fmaak_f32 v14, v12, v14, 0x3ecccdef :: v_dual_sub_f32 v7, v7, v8
v_mul_f32_e32 v15, v4, v12
v_ldexp_f32 v9, v4, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v16, v12, v14
v_fma_f32 v8, v12, v4, -v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v8, v12, v3
v_fma_f32 v3, v12, v14, -v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v7, v14
v_dual_fmac_f32 v8, v7, v4 :: v_dual_add_f32 v7, v16, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v15, v8
v_sub_f32_e32 v12, v4, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v15, 0x3f2aaaaa, v7 :: v_dual_sub_f32 v14, v7, v16
v_sub_f32_e32 v3, v3, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v3, 0x31739010, v3 :: v_dual_sub_f32 v8, v8, v12
v_add_f32_e32 v12, 0xbf2aaaaa, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v12
v_add_f32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v15, v3
v_sub_f32_e32 v12, v15, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v14, v4, v7 :: v_dual_add_f32 v3, v3, v12
v_fma_f32 v12, v4, v7, -v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v4, v3
v_fmac_f32_e32 v12, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v14, v12
v_dual_add_f32 v4, v9, v3 :: v_dual_sub_f32 v7, v3, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v4, v9
v_sub_f32_e32 v7, v12, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v8
v_dual_add_f32 v8, v11, v10 :: v_dual_add_f32 v7, v13, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v7, v3
v_sub_f32_e32 v7, v8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v4, v3
v_dual_sub_f32 v7, v10, v7 :: v_dual_add_f32 v10, v8, v9
v_sub_f32_e32 v4, v9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v11, v10, v8
v_dual_sub_f32 v3, v3, v4 :: v_dual_sub_f32 v4, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v9, v11 :: v_dual_sub_f32 v4, v8, v4
v_dual_add_f32 v11, v7, v3 :: v_dual_add_f32 v4, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v11, v7
v_add_f32_e32 v4, v11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v11, v8
v_sub_f32_e32 v3, v3, v8
v_dual_add_f32 v8, v10, v4 :: v_dual_sub_f32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v8, v10
v_dual_add_f32 v3, v3, v7 :: v_dual_sub_f32 v4, v4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v3, v3, v4
v_cvt_f32_i32_e32 v4, s9
s_add_i32 s9, s9, -1
s_cmp_lg_u32 s9, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v8, v3
v_sub_f32_e32 v8, v7, v8
v_mul_f32_e32 v9, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v8
v_fma_f32 v7, v4, v7, -v9
v_cmp_class_f32_e64 vcc_lo, v9, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v4, v3
v_add_f32_e32 v3, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v3, v9, vcc_lo
v_sub_f32_e32 v3, v3, v9
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v7, v3
v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
v_dual_sub_f32 v10, v4, v8 :: v_dual_cndmask_b32 v3, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, 0x3fb8aa3b, v10
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
v_add_f32_e32 v3, v8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v12, v10, 0x3fb8aa3b, -v11
v_rndne_f32_e32 v13, v11
v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13
v_cvt_i32_f32_e32 v9, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v11, v12
v_exp_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v7, v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v3, v4, v3, v4
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v4
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e64 v7, |v3|
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v6, v7, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v3
s_cbranch_scc1 .LBB1_5
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_branch .LBB1_2
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12genNumbCodoniiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12genNumbCodoniiPiS_, .Lfunc_end1-_Z12genNumbCodoniiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mapToAAiiPcPiS_
.globl _Z7mapToAAiiPcPiS_
.p2align 8
.type _Z7mapToAAiiPcPiS_,@function
_Z7mapToAAiiPcPiS_:
s_load_b32 s8, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB2_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b32 s9, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_mul_lo_u32 v0, v1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, s9
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_add_i32 s1, s1, -2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 0
s_cbranch_scc0 .LBB2_5
.LBB2_3:
global_load_b32 v4, v[2:3], off
v_cmp_ge_i32_e32 vcc_lo, s1, v0
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s0
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB2_2
global_load_u8 v6, v4, s[4:5]
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v6, off
s_branch .LBB2_2
.LBB2_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mapToAAiiPcPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7mapToAAiiPcPiS_, .Lfunc_end2-_Z7mapToAAiiPcPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mapToNumbiiPcPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mapToNumbiiPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12genNumbCodoniiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12genNumbCodoniiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mapToAAiiPcPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mapToAAiiPcPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void mapToNumb(
const int N, //Number of whole threads
const int M, //Length of subseq that one thread handles
char* seq,
int* numb_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, letter;
if(idx < N*M) {
for(i=0; i < M; i++) {
letter = seq[idx+i];
if(letter == 'A') {
numb_seq[idx+i] = 0;
} else {
if(letter == 'C') {
numb_seq[idx+i] = 1;
} else {
if(letter == 'G') {
numb_seq[idx+i] = 2;
} else {
if(letter == 'U') {
numb_seq[idx+i] = 3;
} else {
numb_seq[idx+i] = (-1) * (int)(powf(4, (float)3));
}
}
}
}
}
}
}
__global__ void genNumbCodon(
const int N,
const int M,
int* numb_seq,
int* codon_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int i, k;
int codon_numb, loc_idx, numb, base;
for(i=0; i < M; i++) {
codon_numb = 0;
loc_idx = idx + i;
if(loc_idx <= N*M -3 + 1) {
for(k=0; k<3; k++) {
numb = numb_seq[loc_idx];
base = (int)powf(4, (float)(2-k));
codon_numb += numb * base;
}
codon_seq[loc_idx] = codon_numb;
}
}
}
__global__ void mapToAA(
const int N,
const int M,
char* rna_codon_tab,
int* codon_seq,
char* aa_seq
)
{
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int idx = gid * M;
int codon_idx, loc_idx;
int i;
for(i=0; i < M; i++) {
loc_idx = idx + i;
codon_idx = codon_seq[loc_idx];
if(loc_idx <= N*M -3 + 1) {
if(codon_idx >= 0) {
aa_seq[loc_idx] = rna_codon_tab[codon_idx];
}
}
}
} | .text
.file "proteinTrans.hip"
.globl _Z24__device_stub__mapToNumbiiPcPi # -- Begin function _Z24__device_stub__mapToNumbiiPcPi
.p2align 4, 0x90
.type _Z24__device_stub__mapToNumbiiPcPi,@function
_Z24__device_stub__mapToNumbiiPcPi: # @_Z24__device_stub__mapToNumbiiPcPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mapToNumbiiPcPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__mapToNumbiiPcPi, .Lfunc_end0-_Z24__device_stub__mapToNumbiiPcPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__genNumbCodoniiPiS_ # -- Begin function _Z27__device_stub__genNumbCodoniiPiS_
.p2align 4, 0x90
.type _Z27__device_stub__genNumbCodoniiPiS_,@function
_Z27__device_stub__genNumbCodoniiPiS_: # @_Z27__device_stub__genNumbCodoniiPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12genNumbCodoniiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__genNumbCodoniiPiS_, .Lfunc_end1-_Z27__device_stub__genNumbCodoniiPiS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mapToAAiiPcPiS_ # -- Begin function _Z22__device_stub__mapToAAiiPcPiS_
.p2align 4, 0x90
.type _Z22__device_stub__mapToAAiiPcPiS_,@function
_Z22__device_stub__mapToAAiiPcPiS_: # @_Z22__device_stub__mapToAAiiPcPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mapToAAiiPcPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__mapToAAiiPcPiS_, .Lfunc_end2-_Z22__device_stub__mapToAAiiPcPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mapToNumbiiPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12genNumbCodoniiPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mapToAAiiPcPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mapToNumbiiPcPi,@object # @_Z9mapToNumbiiPcPi
.section .rodata,"a",@progbits
.globl _Z9mapToNumbiiPcPi
.p2align 3, 0x0
_Z9mapToNumbiiPcPi:
.quad _Z24__device_stub__mapToNumbiiPcPi
.size _Z9mapToNumbiiPcPi, 8
.type _Z12genNumbCodoniiPiS_,@object # @_Z12genNumbCodoniiPiS_
.globl _Z12genNumbCodoniiPiS_
.p2align 3, 0x0
_Z12genNumbCodoniiPiS_:
.quad _Z27__device_stub__genNumbCodoniiPiS_
.size _Z12genNumbCodoniiPiS_, 8
.type _Z7mapToAAiiPcPiS_,@object # @_Z7mapToAAiiPcPiS_
.globl _Z7mapToAAiiPcPiS_
.p2align 3, 0x0
_Z7mapToAAiiPcPiS_:
.quad _Z22__device_stub__mapToAAiiPcPiS_
.size _Z7mapToAAiiPcPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9mapToNumbiiPcPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12genNumbCodoniiPiS_"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7mapToAAiiPcPiS_"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mapToNumbiiPcPi
.addrsig_sym _Z27__device_stub__genNumbCodoniiPiS_
.addrsig_sym _Z22__device_stub__mapToAAiiPcPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mapToNumbiiPcPi
.addrsig_sym _Z12genNumbCodoniiPiS_
.addrsig_sym _Z7mapToAAiiPcPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c0d36_00000000-6_proteinTrans.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi
.type _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi, @function
_Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mapToNumbiiPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi, .-_Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi
.globl _Z9mapToNumbiiPcPi
.type _Z9mapToNumbiiPcPi, @function
_Z9mapToNumbiiPcPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9mapToNumbiiPcPiiiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9mapToNumbiiPcPi, .-_Z9mapToNumbiiPcPi
.globl _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_
.type _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_, @function
_Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12genNumbCodoniiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_, .-_Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_
.globl _Z12genNumbCodoniiPiS_
.type _Z12genNumbCodoniiPiS_, @function
_Z12genNumbCodoniiPiS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12genNumbCodoniiPiS_iiPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z12genNumbCodoniiPiS_, .-_Z12genNumbCodoniiPiS_
.globl _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_
.type _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_, @function
_Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mapToAAiiPcPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_, .-_Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_
.globl _Z7mapToAAiiPcPiS_
.type _Z7mapToAAiiPcPiS_, @function
_Z7mapToAAiiPcPiS_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7mapToAAiiPcPiS_iiPcPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7mapToAAiiPcPiS_, .-_Z7mapToAAiiPcPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7mapToAAiiPcPiS_"
.LC1:
.string "_Z12genNumbCodoniiPiS_"
.LC2:
.string "_Z9mapToNumbiiPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mapToAAiiPcPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12genNumbCodoniiPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mapToNumbiiPcPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "proteinTrans.hip"
.globl _Z24__device_stub__mapToNumbiiPcPi # -- Begin function _Z24__device_stub__mapToNumbiiPcPi
.p2align 4, 0x90
.type _Z24__device_stub__mapToNumbiiPcPi,@function
_Z24__device_stub__mapToNumbiiPcPi: # @_Z24__device_stub__mapToNumbiiPcPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mapToNumbiiPcPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__mapToNumbiiPcPi, .Lfunc_end0-_Z24__device_stub__mapToNumbiiPcPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__genNumbCodoniiPiS_ # -- Begin function _Z27__device_stub__genNumbCodoniiPiS_
.p2align 4, 0x90
.type _Z27__device_stub__genNumbCodoniiPiS_,@function
_Z27__device_stub__genNumbCodoniiPiS_: # @_Z27__device_stub__genNumbCodoniiPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12genNumbCodoniiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__genNumbCodoniiPiS_, .Lfunc_end1-_Z27__device_stub__genNumbCodoniiPiS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mapToAAiiPcPiS_ # -- Begin function _Z22__device_stub__mapToAAiiPcPiS_
.p2align 4, 0x90
.type _Z22__device_stub__mapToAAiiPcPiS_,@function
_Z22__device_stub__mapToAAiiPcPiS_: # @_Z22__device_stub__mapToAAiiPcPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mapToAAiiPcPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__mapToAAiiPcPiS_, .Lfunc_end2-_Z22__device_stub__mapToAAiiPcPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mapToNumbiiPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12genNumbCodoniiPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mapToAAiiPcPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9mapToNumbiiPcPi,@object # @_Z9mapToNumbiiPcPi
.section .rodata,"a",@progbits
.globl _Z9mapToNumbiiPcPi
.p2align 3, 0x0
_Z9mapToNumbiiPcPi:
.quad _Z24__device_stub__mapToNumbiiPcPi
.size _Z9mapToNumbiiPcPi, 8
.type _Z12genNumbCodoniiPiS_,@object # @_Z12genNumbCodoniiPiS_
.globl _Z12genNumbCodoniiPiS_
.p2align 3, 0x0
_Z12genNumbCodoniiPiS_:
.quad _Z27__device_stub__genNumbCodoniiPiS_
.size _Z12genNumbCodoniiPiS_, 8
.type _Z7mapToAAiiPcPiS_,@object # @_Z7mapToAAiiPcPiS_
.globl _Z7mapToAAiiPcPiS_
.p2align 3, 0x0
_Z7mapToAAiiPcPiS_:
.quad _Z22__device_stub__mapToAAiiPcPiS_
.size _Z7mapToAAiiPcPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9mapToNumbiiPcPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12genNumbCodoniiPiS_"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7mapToAAiiPcPiS_"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mapToNumbiiPcPi
.addrsig_sym _Z27__device_stub__genNumbCodoniiPiS_
.addrsig_sym _Z22__device_stub__mapToAAiiPcPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mapToNumbiiPcPi
.addrsig_sym _Z12genNumbCodoniiPiS_
.addrsig_sym _Z7mapToAAiiPcPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*Vector sum in CPU*/
#include <stdio.h>
#define N 10
void add(int *a, int *b, int *c)
{
int tid=0;
while(tid < N){
c[tid]=a[tid]+b[tid];
tid+=1;
}
}
int main(void)
{
int a[N],b[N],c[N];
for (int i = 0; i<N; i++)
{
a[i]=-i;
b[i]=i*i;
}
add(a,b,c);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n", a[i],b[i],c[i] );
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*Vector sum in CPU*/
#include <stdio.h>
#define N 10
void add(int *a, int *b, int *c)
{
int tid=0;
while(tid < N){
c[tid]=a[tid]+b[tid];
tid+=1;
}
}
int main(void)
{
int a[N],b[N],c[N];
for (int i = 0; i<N; i++)
{
a[i]=-i;
b[i]=i*i;
}
add(a,b,c);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n", a[i],b[i],c[i] );
}
return 0;
} | .file "tmpxft_00036f24_00000000-6_vectorSumCPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d+%d=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
.L7:
movl %eax, %edx
negl %edx
movl %edx, (%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L7
leaq 96(%rsp), %rdx
leaq 48(%rsp), %rsi
movq %rsp, %rdi
call _Z3addPiS_S_
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L8:
movl 48(%rsp,%rbx), %ecx
movl (%rsp,%rbx), %edx
movl 96(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L8
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*Vector sum in CPU*/
#include <stdio.h>
#define N 10
void add(int *a, int *b, int *c)
{
int tid=0;
while(tid < N){
c[tid]=a[tid]+b[tid];
tid+=1;
}
}
int main(void)
{
int a[N],b[N],c[N];
for (int i = 0; i<N; i++)
{
a[i]=-i;
b[i]=i*i;
}
add(a,b,c);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n", a[i],b[i],c[i] );
}
return 0;
} | /*Vector sum in CPU*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
void add(int *a, int *b, int *c)
{
int tid=0;
while(tid < N){
c[tid]=a[tid]+b[tid];
tid+=1;
}
}
int main(void)
{
int a[N],b[N],c[N];
for (int i = 0; i<N; i++)
{
a[i]=-i;
b[i]=i*i;
}
add(a,b,c);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n", a[i],b[i],c[i] );
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*Vector sum in CPU*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
void add(int *a, int *b, int *c)
{
int tid=0;
while(tid < N){
c[tid]=a[tid]+b[tid];
tid+=1;
}
}
int main(void)
{
int a[N],b[N],c[N];
for (int i = 0; i<N; i++)
{
a[i]=-i;
b[i]=i*i;
}
add(a,b,c);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n", a[i],b[i],c[i] );
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*Vector sum in CPU*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
void add(int *a, int *b, int *c)
{
int tid=0;
while(tid < N){
c[tid]=a[tid]+b[tid];
tid+=1;
}
}
int main(void)
{
int a[N],b[N],c[N];
for (int i = 0; i<N; i++)
{
a[i]=-i;
b[i]=i*i;
}
add(a,b,c);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n", a[i],b[i],c[i] );
}
return 0;
} | .text
.file "vectorSumCPU.hip"
.globl _Z3addPiS_S_ # -- Begin function _Z3addPiS_S_
.p2align 4, 0x90
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: # @_Z3addPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl (%rsi,%rax,4), %ecx
addl (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 48(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, (%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rsp,%rax,4), %ecx
addl 48(%rsp,%rax,4), %ecx
movl %ecx, 96(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_3
# %bb.4: # %_Z3addPiS_S_.exit.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %_Z3addPiS_S_.exit
# =>This Inner Loop Header: Depth=1
movl 48(%rsp,%rbx,4), %esi
movl (%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d+%d=%d\n"
.size .L.str, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00036f24_00000000-6_vectorSumCPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d+%d=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
.L7:
movl %eax, %edx
negl %edx
movl %edx, (%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L7
leaq 96(%rsp), %rdx
leaq 48(%rsp), %rsi
movq %rsp, %rdi
call _Z3addPiS_S_
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L8:
movl 48(%rsp,%rbx), %ecx
movl (%rsp,%rbx), %edx
movl 96(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L8
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorSumCPU.hip"
.globl _Z3addPiS_S_ # -- Begin function _Z3addPiS_S_
.p2align 4, 0x90
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: # @_Z3addPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl (%rsi,%rax,4), %ecx
addl (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 48(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, (%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rsp,%rax,4), %ecx
addl 48(%rsp,%rax,4), %ecx
movl %ecx, 96(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_3
# %bb.4: # %_Z3addPiS_S_.exit.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %_Z3addPiS_S_.exit
# =>This Inner Loop Header: Depth=1
movl 48(%rsp,%rbx,4), %esi
movl (%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d+%d=%d\n"
.size .L.str, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <stdbool.h>
static int grid_array[5]={5,9,16,23,30};
static int block_array[5]={2,3,5,10,12};
static FILE *pointerToFile;
__device__
static void calculate(int *readingArray, int* writingArray, double *weights, int n ,int current,int xAxes, int yAxes){
double Sum = 0;
if(current < n*n)
{
// loop through all the points that affect
for(int p=-2;p<3;p++){
for(int q=-2;q<3;q++){
Sum += weights[(p+2)*5+(q+2)] * readingArray[((p + yAxes + n) % n) * n + ( q + xAxes + n) % n];
// index properly in order to include the wrap points
// add the weight to Sum
}
}
// check to decide which value the current spin should take
if(Sum > 0.00001)// set to 0.000001 in order to take into account
// floating points
writingArray[current] = 1;
else if(Sum < -0.00001)
writingArray[current] = -1;
else // if it is zero then let the value remain the same
writingArray[current] = readingArray[current];
}
}
// cuda function to parallelize the spin calculation
__global__ void spinCalculation(int n, double * gpuWeights,int *gpuG,int *gpuGTemp,int i,int block,int looper) {
// variable to hold the sum of the weights
int current = blockIdx.x * block * block + threadIdx.x; // calculation of the current index
int xAxes;
int yAxes;
for(int q=0;q<looper;q++)
{
// switch the i%2 which is the current number of iretarion
// so periodically we will be writing to gpuGTemp and then to gpuG
switch (i%2) {
case 0:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuG,gpuGTemp,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
// here everything is the same with the difference that is reading from the gpuGTemp array
// and write to the gpuG
case 1:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuGTemp,gpuG,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
}
}
}
void takeBinData(int *array, FILE *file,int n){
if (file==NULL)
{
printf("error opening file");
exit(1);
}
fread(array,sizeof(int),n*n,file);
fclose(file);
}
void ising (int *G, double *w, int k, int n,int grid ,int block)
{
int looper= n*n/(grid*grid*block*block) + 1;
double *weights;
cudaMalloc(&weights,sizeof(double)*25);
cudaMemcpy(weights,w,25*sizeof(double),cudaMemcpyHostToDevice);
int *tempG=(int *) malloc(sizeof(int)*n*n);
memcpy(tempG,G,n*n*sizeof(int));
int *gpuTempG;
cudaMalloc(&gpuTempG,n*n*sizeof(int));
int *gpuG;
cudaMalloc(&gpuG,n*n*sizeof(int));
cudaMemcpy(gpuTempG,tempG,n*n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(gpuG,G,n*n*sizeof(int),cudaMemcpyHostToDevice);
for(int i=0;i<k;i++){
spinCalculation<<<grid*grid,block*block>>>(n,weights,gpuG,gpuTempG,i,block,looper);
cudaDeviceSynchronize();
}
if(k%2==1){
cudaMemcpy(G,gpuTempG,n*n*sizeof(int),cudaMemcpyDeviceToHost);
}
else{
cudaMemcpy(G,gpuG,n*n*sizeof(int),cudaMemcpyDeviceToHost);
}
cudaFree(gpuG);
cudaFree(gpuTempG);
free(tempG);
}
void checkCorrectness(int *G, int *expectedState,int n,int k){
bool noMistake=true;
int counter=0;
for(int i=0;i<n*n;i++)
{
if(expectedState[i]!=G[i])
{
//printf("wrong in index %d\n",i );
counter++;
noMistake=false;
}
}
if (noMistake) {
printf("ising for k=%d is correct\n",k );
}
else{
printf("ising for k=%d is wrong\n",k );
}
printf("%d\n",counter );
}
int main(){
int n=517;
int grid,block;
for(int i=0;i<5;i++){
for(int j=0;j<5;j++)
{
grid=grid_array[i];
block=block_array[j];
int *initialG=(int *) malloc(sizeof(int)*n*n);
int *G=(int *)malloc(sizeof(int)*n*n);
int *expectedState=(int *)malloc(sizeof(int)*n*n);
FILE *file;
file= fopen("conf-init.bin","rb");
takeBinData(initialG,file,n);
memcpy(G,initialG,sizeof(int)*n*n);
double weights[] = {0.004, 0.016, 0.026, 0.016, 0.004,
0.016, 0.071, 0.117, 0.071, 0.016,
0.026, 0.117, 0, 0.117, 0.026,
0.016, 0.071, 0.117, 0.071, 0.016,
0.004, 0.016, 0.026, 0.016, 0.004};
clock_t start,end;
start=clock();
ising(G,weights,1,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC);
file=fopen("conf-1.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,1);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,4,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-4.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,4);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,11,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-11.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,11);
}
}
return 0;
} | .file "tmpxft_0019ebf5_00000000-6_V2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "error opening file"
.text
.globl _Z11takeBinDataPiP8_IO_FILEi
.type _Z11takeBinDataPiP8_IO_FILEi, @function
_Z11takeBinDataPiP8_IO_FILEi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
testq %rsi, %rsi
je .L6
movq %rsi, %rbx
imull %edx, %edx
movslq %edx, %rcx
movq %rsi, %r8
movl $4, %edx
movq $-1, %rsi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11takeBinDataPiP8_IO_FILEi, .-_Z11takeBinDataPiP8_IO_FILEi
.section .rodata.str1.1
.LC1:
.string "ising for k=%d is correct\n"
.LC2:
.string "ising for k=%d is wrong\n"
.LC3:
.string "%d\n"
.text
.globl _Z16checkCorrectnessPiS_ii
.type _Z16checkCorrectnessPiS_ii, @function
_Z16checkCorrectnessPiS_ii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
imull %edx, %edx
testl %edx, %edx
jle .L13
movq %rdi, %r8
movslq %edx, %rdx
leaq 0(,%rdx,4), %rdi
movl $0, %eax
movl $0, %ebx
movl $1, %r9d
movl $0, %r10d
jmp .L10
.L9:
addq $4, %rax
cmpq %rax, %rdi
je .L16
.L10:
movl (%r8,%rax), %edx
cmpl %edx, (%rsi,%rax)
je .L9
addl $1, %ebx
movl %r10d, %r9d
jmp .L9
.L16:
testb %r9b, %r9b
jne .L8
movl %ecx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L13:
movl $0, %ebx
.L8:
movl %ecx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z16checkCorrectnessPiS_ii, .-_Z16checkCorrectnessPiS_ii
.globl _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
.type _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii, @function
_Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15spinCalculationiPdPiS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii, .-_Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
.globl _Z15spinCalculationiPdPiS0_iii
.type _Z15spinCalculationiPdPiS0_iii, @function
_Z15spinCalculationiPdPiS0_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15spinCalculationiPdPiS0_iii, .-_Z15spinCalculationiPdPiS0_iii
.globl _Z5isingPiPdiiii
.type _Z5isingPiPdiiii, @function
_Z5isingPiPdiiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, %rbx
movl %edx, %r13d
movl %ecx, %r15d
movl %ecx, 16(%rsp)
movl %r9d, %r14d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
imull %r8d, %r8d
movl %r8d, %r12d
movl %ecx, %eax
imull %ecx, %eax
movl %r8d, %ecx
imull %r9d, %ecx
imull %r9d, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 20(%rsp)
leaq 40(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq %r15d, %rbp
imulq %rbp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movq (%rsp), %r15
movq %r15, %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L26
movl %r14d, %r15d
imull %r14d, %r15d
movl $0, %ebx
movq %rbp, 24(%rsp)
movl 20(%rsp), %ebp
jmp .L28
.L27:
call cudaDeviceSynchronize@PLT
addl $1, %ebx
cmpl %ebx, %r13d
je .L33
.L28:
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rbp
.cfi_def_cfa_offset 176
movl %r14d, %r9d
movl %ebx, %r8d
movq 64(%rsp), %rcx
movq 72(%rsp), %rdx
movq 56(%rsp), %rsi
movl 32(%rsp), %edi
call _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L33:
movq 24(%rsp), %rbp
movl %ebx, %eax
shrl $31, %eax
addl %eax, %ebx
andl $1, %ebx
subl %eax, %ebx
cmpl $1, %ebx
je .L34
.L26:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
.L29:
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
jmp .L29
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z5isingPiPdiiii, .-_Z5isingPiPdiiii
.section .rodata.str1.1
.LC4:
.string "rb"
.LC5:
.string "conf-init.bin"
.LC13:
.string "%lf\n"
.LC14:
.string "conf-1.bin"
.LC15:
.string "conf-4.bin"
.LC16:
.string "conf-11.bin"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq _ZL10grid_array(%rip), %rdx
movq .LC7(%rip), %r14
.L37:
leaq _ZL11block_array(%rip), %r13
movq %rdx, 40(%rsp)
.L38:
movq 40(%rsp), %rax
movl (%rax), %eax
movl %eax, 8(%rsp)
movl 0(%r13), %ecx
movl %ecx, 12(%rsp)
movl $1069156, %edi
call malloc@PLT
movq %rax, %r12
movl $1069156, %edi
call malloc@PLT
movq %rax, %rbx
movl $1069156, %edi
call malloc@PLT
movq %rax, %rbp
leaq .LC4(%rip), %r15
movq %r15, %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %r12, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $1069156, %edx
movq %r12, 16(%rsp)
movq %r12, %rsi
movq %rbx, %rdi
call memcpy@PLT
movq .LC6(%rip), %rdx
movq %rdx, 48(%rsp)
movq %r14, 56(%rsp)
movq .LC8(%rip), %rdx
movq %rdx, 64(%rsp)
movq %r14, 72(%rsp)
movq .LC6(%rip), %rdx
movq %rdx, 80(%rsp)
movq %r14, 88(%rsp)
movq .LC9(%rip), %rdx
movq %rdx, 96(%rsp)
movsd .LC10(%rip), %xmm0
movsd %xmm0, 104(%rsp)
movq %rdx, 112(%rsp)
movq %r14, 120(%rsp)
movq .LC8(%rip), %rdx
movq %rdx, 128(%rsp)
movsd %xmm0, 136(%rsp)
movq $0x000000000, 144(%rsp)
movsd %xmm0, 152(%rsp)
movq %rdx, 160(%rsp)
movq %r14, 168(%rsp)
movq .LC9(%rip), %rdx
movq %rdx, 176(%rsp)
movsd %xmm0, 184(%rsp)
movq %rdx, 192(%rsp)
movq %r14, 200(%rsp)
movq .LC6(%rip), %rdx
movq %rdx, 208(%rsp)
movq %r14, 216(%rsp)
movq .LC8(%rip), %rdi
movq %rdi, 224(%rsp)
movq %r14, 232(%rsp)
movq %rdx, 240(%rsp)
call clock@PLT
movq %rax, %r12
leaq 48(%rsp), %rdi
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl $517, %ecx
movl $1, %edx
movq %rdi, 24(%rsp)
movq %rdi, %rsi
movq %rbx, %rdi
call _Z5isingPiPdiiii
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC13(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %rbp, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $1, %ecx
movl $517, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16checkCorrectnessPiS_ii
movl $1069156, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call memcpy@PLT
call clock@PLT
movq %rax, 32(%rsp)
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl $517, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call _Z5isingPiPdiiii
call clock@PLT
movq 32(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rsi
leaq .LC15(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %rbp, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $4, %ecx
movl $517, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16checkCorrectnessPiS_ii
movl $1069156, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call memcpy@PLT
call clock@PLT
movq %rax, 16(%rsp)
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl $517, %ecx
movl $11, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call _Z5isingPiPdiiii
call clock@PLT
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rsi
leaq .LC16(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %rbp, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $11, %ecx
movl $517, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16checkCorrectnessPiS_ii
addq $4, %r13
leaq 20+_ZL11block_array(%rip), %rax
cmpq %rax, %r13
jne .L38
movq 40(%rsp), %rdx
addq $4, %rdx
leaq 20+_ZL10grid_array(%rip), %rax
cmpq %rax, %rdx
jne .L37
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC17:
.string "_Z15spinCalculationiPdPiS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z15spinCalculationiPdPiS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 16
.type _ZL11block_array, @object
.size _ZL11block_array, 20
_ZL11block_array:
.long 2
.long 3
.long 5
.long 10
.long 12
.align 16
.type _ZL10grid_array, @object
.size _ZL10grid_array, 20
_ZL10grid_array:
.long 5
.long 9
.long 16
.long 23
.long 30
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -755914244
.long 1064329805
.align 8
.LC7:
.long -755914244
.long 1066426957
.align 8
.LC8:
.long 1992864825
.long 1067098046
.align 8
.LC9:
.long 1443109011
.long 1068641550
.align 8
.LC10:
.long 1168231105
.long 1069413302
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <stdbool.h>
static int grid_array[5]={5,9,16,23,30};
static int block_array[5]={2,3,5,10,12};
static FILE *pointerToFile;
__device__
static void calculate(int *readingArray, int* writingArray, double *weights, int n ,int current,int xAxes, int yAxes){
double Sum = 0;
if(current < n*n)
{
// loop through all the points that affect
for(int p=-2;p<3;p++){
for(int q=-2;q<3;q++){
Sum += weights[(p+2)*5+(q+2)] * readingArray[((p + yAxes + n) % n) * n + ( q + xAxes + n) % n];
// index properly in order to include the wrap points
// add the weight to Sum
}
}
// check to decide which value the current spin should take
if(Sum > 0.00001)// set to 0.000001 in order to take into account
// floating points
writingArray[current] = 1;
else if(Sum < -0.00001)
writingArray[current] = -1;
else // if it is zero then let the value remain the same
writingArray[current] = readingArray[current];
}
}
// cuda function to parallelize the spin calculation
__global__ void spinCalculation(int n, double * gpuWeights,int *gpuG,int *gpuGTemp,int i,int block,int looper) {
// variable to hold the sum of the weights
int current = blockIdx.x * block * block + threadIdx.x; // calculation of the current index
int xAxes;
int yAxes;
for(int q=0;q<looper;q++)
{
// switch the i%2 which is the current number of iretarion
// so periodically we will be writing to gpuGTemp and then to gpuG
switch (i%2) {
case 0:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuG,gpuGTemp,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
// here everything is the same with the difference that is reading from the gpuGTemp array
// and write to the gpuG
case 1:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuGTemp,gpuG,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
}
}
}
void takeBinData(int *array, FILE *file,int n){
if (file==NULL)
{
printf("error opening file");
exit(1);
}
fread(array,sizeof(int),n*n,file);
fclose(file);
}
void ising (int *G, double *w, int k, int n,int grid ,int block)
{
int looper= n*n/(grid*grid*block*block) + 1;
double *weights;
cudaMalloc(&weights,sizeof(double)*25);
cudaMemcpy(weights,w,25*sizeof(double),cudaMemcpyHostToDevice);
int *tempG=(int *) malloc(sizeof(int)*n*n);
memcpy(tempG,G,n*n*sizeof(int));
int *gpuTempG;
cudaMalloc(&gpuTempG,n*n*sizeof(int));
int *gpuG;
cudaMalloc(&gpuG,n*n*sizeof(int));
cudaMemcpy(gpuTempG,tempG,n*n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(gpuG,G,n*n*sizeof(int),cudaMemcpyHostToDevice);
for(int i=0;i<k;i++){
spinCalculation<<<grid*grid,block*block>>>(n,weights,gpuG,gpuTempG,i,block,looper);
cudaDeviceSynchronize();
}
if(k%2==1){
cudaMemcpy(G,gpuTempG,n*n*sizeof(int),cudaMemcpyDeviceToHost);
}
else{
cudaMemcpy(G,gpuG,n*n*sizeof(int),cudaMemcpyDeviceToHost);
}
cudaFree(gpuG);
cudaFree(gpuTempG);
free(tempG);
}
void checkCorrectness(int *G, int *expectedState,int n,int k){
bool noMistake=true;
int counter=0;
for(int i=0;i<n*n;i++)
{
if(expectedState[i]!=G[i])
{
//printf("wrong in index %d\n",i );
counter++;
noMistake=false;
}
}
if (noMistake) {
printf("ising for k=%d is correct\n",k );
}
else{
printf("ising for k=%d is wrong\n",k );
}
printf("%d\n",counter );
}
int main(){
int n=517;
int grid,block;
for(int i=0;i<5;i++){
for(int j=0;j<5;j++)
{
grid=grid_array[i];
block=block_array[j];
int *initialG=(int *) malloc(sizeof(int)*n*n);
int *G=(int *)malloc(sizeof(int)*n*n);
int *expectedState=(int *)malloc(sizeof(int)*n*n);
FILE *file;
file= fopen("conf-init.bin","rb");
takeBinData(initialG,file,n);
memcpy(G,initialG,sizeof(int)*n*n);
double weights[] = {0.004, 0.016, 0.026, 0.016, 0.004,
0.016, 0.071, 0.117, 0.071, 0.016,
0.026, 0.117, 0, 0.117, 0.026,
0.016, 0.071, 0.117, 0.071, 0.016,
0.004, 0.016, 0.026, 0.016, 0.004};
clock_t start,end;
start=clock();
ising(G,weights,1,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC);
file=fopen("conf-1.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,1);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,4,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-4.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,4);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,11,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-11.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,11);
}
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <stdbool.h>
static int grid_array[5]={5,9,16,23,30};
static int block_array[5]={2,3,5,10,12};
static FILE *pointerToFile;
__device__
static void calculate(int *readingArray, int* writingArray, double *weights, int n ,int current,int xAxes, int yAxes){
double Sum = 0;
if(current < n*n)
{
// loop through all the points that affect
for(int p=-2;p<3;p++){
for(int q=-2;q<3;q++){
Sum += weights[(p+2)*5+(q+2)] * readingArray[((p + yAxes + n) % n) * n + ( q + xAxes + n) % n];
// index properly in order to include the wrap points
// add the weight to Sum
}
}
// check to decide which value the current spin should take
if(Sum > 0.00001)// set to 0.000001 in order to take into account
// floating points
writingArray[current] = 1;
else if(Sum < -0.00001)
writingArray[current] = -1;
else // if it is zero then let the value remain the same
writingArray[current] = readingArray[current];
}
}
// cuda function to parallelize the spin calculation
__global__ void spinCalculation(int n, double * gpuWeights,int *gpuG,int *gpuGTemp,int i,int block,int looper) {
// variable to hold the sum of the weights
int current = blockIdx.x * block * block + threadIdx.x; // calculation of the current index
int xAxes;
int yAxes;
for(int q=0;q<looper;q++)
{
// switch the i%2 which is the current number of iretarion
// so periodically we will be writing to gpuGTemp and then to gpuG
switch (i%2) {
case 0:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuG,gpuGTemp,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
// here everything is the same with the difference that is reading from the gpuGTemp array
// and write to the gpuG
case 1:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuGTemp,gpuG,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
}
}
}
void takeBinData(int *array, FILE *file,int n){
if (file==NULL)
{
printf("error opening file");
exit(1);
}
fread(array,sizeof(int),n*n,file);
fclose(file);
}
void ising (int *G, double *w, int k, int n,int grid ,int block)
{
int looper= n*n/(grid*grid*block*block) + 1;
double *weights;
hipMalloc(&weights,sizeof(double)*25);
hipMemcpy(weights,w,25*sizeof(double),hipMemcpyHostToDevice);
int *tempG=(int *) malloc(sizeof(int)*n*n);
memcpy(tempG,G,n*n*sizeof(int));
int *gpuTempG;
hipMalloc(&gpuTempG,n*n*sizeof(int));
int *gpuG;
hipMalloc(&gpuG,n*n*sizeof(int));
hipMemcpy(gpuTempG,tempG,n*n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(gpuG,G,n*n*sizeof(int),hipMemcpyHostToDevice);
for(int i=0;i<k;i++){
spinCalculation<<<grid*grid,block*block>>>(n,weights,gpuG,gpuTempG,i,block,looper);
hipDeviceSynchronize();
}
if(k%2==1){
hipMemcpy(G,gpuTempG,n*n*sizeof(int),hipMemcpyDeviceToHost);
}
else{
hipMemcpy(G,gpuG,n*n*sizeof(int),hipMemcpyDeviceToHost);
}
hipFree(gpuG);
hipFree(gpuTempG);
free(tempG);
}
void checkCorrectness(int *G, int *expectedState,int n,int k){
bool noMistake=true;
int counter=0;
for(int i=0;i<n*n;i++)
{
if(expectedState[i]!=G[i])
{
//printf("wrong in index %d\n",i );
counter++;
noMistake=false;
}
}
if (noMistake) {
printf("ising for k=%d is correct\n",k );
}
else{
printf("ising for k=%d is wrong\n",k );
}
printf("%d\n",counter );
}
int main(){
int n=517;
int grid,block;
for(int i=0;i<5;i++){
for(int j=0;j<5;j++)
{
grid=grid_array[i];
block=block_array[j];
int *initialG=(int *) malloc(sizeof(int)*n*n);
int *G=(int *)malloc(sizeof(int)*n*n);
int *expectedState=(int *)malloc(sizeof(int)*n*n);
FILE *file;
file= fopen("conf-init.bin","rb");
takeBinData(initialG,file,n);
memcpy(G,initialG,sizeof(int)*n*n);
double weights[] = {0.004, 0.016, 0.026, 0.016, 0.004,
0.016, 0.071, 0.117, 0.071, 0.016,
0.026, 0.117, 0, 0.117, 0.026,
0.016, 0.071, 0.117, 0.071, 0.016,
0.004, 0.016, 0.026, 0.016, 0.004};
clock_t start,end;
start=clock();
ising(G,weights,1,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC);
file=fopen("conf-1.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,1);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,4,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-4.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,4);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,11,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-11.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,11);
}
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <stdbool.h>
static int grid_array[5]={5,9,16,23,30};
static int block_array[5]={2,3,5,10,12};
static FILE *pointerToFile;
__device__
static void calculate(int *readingArray, int* writingArray, double *weights, int n ,int current,int xAxes, int yAxes){
double Sum = 0;
if(current < n*n)
{
// loop through all the points that affect
for(int p=-2;p<3;p++){
for(int q=-2;q<3;q++){
Sum += weights[(p+2)*5+(q+2)] * readingArray[((p + yAxes + n) % n) * n + ( q + xAxes + n) % n];
// index properly in order to include the wrap points
// add the weight to Sum
}
}
// check to decide which value the current spin should take
if(Sum > 0.00001)// set to 0.000001 in order to take into account
// floating points
writingArray[current] = 1;
else if(Sum < -0.00001)
writingArray[current] = -1;
else // if it is zero then let the value remain the same
writingArray[current] = readingArray[current];
}
}
// cuda function to parallelize the spin calculation
__global__ void spinCalculation(int n, double * gpuWeights,int *gpuG,int *gpuGTemp,int i,int block,int looper) {
// variable to hold the sum of the weights
int current = blockIdx.x * block * block + threadIdx.x; // calculation of the current index
int xAxes;
int yAxes;
for(int q=0;q<looper;q++)
{
// switch the i%2 which is the current number of iretarion
// so periodically we will be writing to gpuGTemp and then to gpuG
switch (i%2) {
case 0:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuG,gpuGTemp,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
// here everything is the same with the difference that is reading from the gpuGTemp array
// and write to the gpuG
case 1:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuGTemp,gpuG,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
}
}
}
void takeBinData(int *array, FILE *file,int n){
if (file==NULL)
{
printf("error opening file");
exit(1);
}
fread(array,sizeof(int),n*n,file);
fclose(file);
}
void ising (int *G, double *w, int k, int n,int grid ,int block)
{
int looper= n*n/(grid*grid*block*block) + 1;
double *weights;
hipMalloc(&weights,sizeof(double)*25);
hipMemcpy(weights,w,25*sizeof(double),hipMemcpyHostToDevice);
int *tempG=(int *) malloc(sizeof(int)*n*n);
memcpy(tempG,G,n*n*sizeof(int));
int *gpuTempG;
hipMalloc(&gpuTempG,n*n*sizeof(int));
int *gpuG;
hipMalloc(&gpuG,n*n*sizeof(int));
hipMemcpy(gpuTempG,tempG,n*n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(gpuG,G,n*n*sizeof(int),hipMemcpyHostToDevice);
for(int i=0;i<k;i++){
spinCalculation<<<grid*grid,block*block>>>(n,weights,gpuG,gpuTempG,i,block,looper);
hipDeviceSynchronize();
}
if(k%2==1){
hipMemcpy(G,gpuTempG,n*n*sizeof(int),hipMemcpyDeviceToHost);
}
else{
hipMemcpy(G,gpuG,n*n*sizeof(int),hipMemcpyDeviceToHost);
}
hipFree(gpuG);
hipFree(gpuTempG);
free(tempG);
}
void checkCorrectness(int *G, int *expectedState,int n,int k){
bool noMistake=true;
int counter=0;
for(int i=0;i<n*n;i++)
{
if(expectedState[i]!=G[i])
{
//printf("wrong in index %d\n",i );
counter++;
noMistake=false;
}
}
if (noMistake) {
printf("ising for k=%d is correct\n",k );
}
else{
printf("ising for k=%d is wrong\n",k );
}
printf("%d\n",counter );
}
int main(){
int n=517;
int grid,block;
for(int i=0;i<5;i++){
for(int j=0;j<5;j++)
{
grid=grid_array[i];
block=block_array[j];
int *initialG=(int *) malloc(sizeof(int)*n*n);
int *G=(int *)malloc(sizeof(int)*n*n);
int *expectedState=(int *)malloc(sizeof(int)*n*n);
FILE *file;
file= fopen("conf-init.bin","rb");
takeBinData(initialG,file,n);
memcpy(G,initialG,sizeof(int)*n*n);
double weights[] = {0.004, 0.016, 0.026, 0.016, 0.004,
0.016, 0.071, 0.117, 0.071, 0.016,
0.026, 0.117, 0, 0.117, 0.026,
0.016, 0.071, 0.117, 0.071, 0.016,
0.004, 0.016, 0.026, 0.016, 0.004};
clock_t start,end;
start=clock();
ising(G,weights,1,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC);
file=fopen("conf-1.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,1);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,4,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-4.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,4);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,11,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-11.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,11);
}
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15spinCalculationiPdPiS0_iii
.globl _Z15spinCalculationiPdPiS0_iii
.p2align 8
.type _Z15spinCalculationiPdPiS0_iii,@function
_Z15spinCalculationiPdPiS0_iii:
s_load_b32 s9, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_36
s_load_b32 s8, s[0:1], 0x0
s_mov_b32 s18, 0
s_mov_b32 s11, 0xbee4f8b5
v_mov_b32_e32 v7, 1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s16, s8, 31
s_mul_i32 s19, s8, s8
s_add_i32 s2, s8, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s17, s2, s16
s_load_b256 s[0:7], s[0:1], 0x8
v_cvt_f32_u32_e32 v1, s17
s_sub_i32 s10, 0, s17
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s15, s15, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_lshr_b32 s7, s6, 31
v_mul_lo_u32 v4, s10, v3
s_add_i32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 s7, s7, -2
v_mul_lo_u32 v5, v1, s9
s_sub_i32 s20, s6, s7
s_mov_b32 s7, 0x3ee4f8b5
s_mov_b32 s6, 0x88e368f1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v4
v_mov_b32_e32 v4, -1
v_add_nc_u32_e32 v6, v3, v0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s21
.LBB0_3:
s_add_i32 s18, s18, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, s9
s_cbranch_scc1 .LBB0_36
.LBB0_4:
s_cmp_lt_i32 s20, 1
s_mov_b32 s10, -1
s_cbranch_scc1 .LBB0_21
s_cmp_eq_u32 s20, 1
s_cbranch_scc0 .LBB0_20
v_add_nc_u32_e32 v0, s18, v5
s_mov_b32 s21, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s19, v0
s_cbranch_execz .LBB0_19
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s10, -2
s_mov_b64 s[12:13], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v0, v1
v_xor_b32_e32 v2, v2, v1
v_xor_b32_e32 v1, s16, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v6
v_mul_lo_u32 v8, v3, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v8
v_add_nc_u32_e32 v8, 1, v3
v_subrev_nc_u32_e32 v9, s17, v2
v_cmp_le_u32_e32 vcc_lo, s17, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v8 :: v_dual_cndmask_b32 v2, v2, v9
v_add_nc_u32_e32 v8, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s17, v2
v_cndmask_b32_e32 v2, v3, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v3, v1, v2
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, s8, v3, s[8:9]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s8, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v8, v0, v8, -2
.LBB0_8:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, s10, v1
s_mov_b64 s[14:15], 0
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v9, v10
v_xor_b32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v11, v9, v6
v_mul_lo_u32 v11, v11, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v9, v11
v_subrev_nc_u32_e32 v11, s17, v9
v_cmp_le_u32_e32 vcc_lo, s17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v9, v11, vcc_lo
v_subrev_nc_u32_e32 v11, s17, v9
v_cmp_le_u32_e32 vcc_lo, s17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v9, v11, vcc_lo
v_xor_b32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, v9, v10
v_mov_b32_e32 v10, v8
v_mul_lo_u32 v9, v9, s8
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_9:
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
s_add_u32 s22, s12, s14
s_addc_u32 s23, s13, s15
s_add_u32 s14, s14, 8
s_load_b64 s[22:23], s[22:23], 0x0
v_add_nc_u32_e32 v12, v10, v11
v_add_nc_u32_e32 v10, 1, v10
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s14, 40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v12, v12, v11
v_mul_hi_u32 v13, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, v13, s17
v_sub_nc_u32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s17, v12
v_cmp_le_u32_e32 vcc_lo, s17, v12
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s17, v12
v_cmp_le_u32_e32 vcc_lo, s17, v12
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v12, v12, v11
v_sub_nc_u32_e32 v11, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v11, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[11:12], v11
s_waitcnt lgkmcnt(0)
v_fma_f64 v[2:3], s[22:23], v[11:12], v[2:3]
s_cbranch_scc0 .LBB0_9
s_set_inst_prefetch_distance 0x2
s_add_i32 s10, s10, 1
s_add_u32 s12, s12, 40
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s10, 3
s_cbranch_scc0 .LBB0_8
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_nlt_f64_e32 s[6:7], v[2:3]
s_xor_b32 s12, exec_lo, s10
s_cbranch_execz .LBB0_17
s_mov_b32 s10, s6
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cmp_ngt_f64_e32 vcc_lo, s[10:11], v[2:3]
s_and_saveexec_b32 s10, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_14
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_14:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_16
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s10
.LBB0_17:
s_and_not1_saveexec_b32 s10, s12
s_cbranch_execz .LBB0_19
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v7, off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s21
.LBB0_20:
s_mov_b32 s10, 0
.LBB0_21:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_3
s_cmp_lg_u32 s20, 0
s_cbranch_scc1 .LBB0_3
v_add_nc_u32_e32 v0, s18, v5
s_mov_b32 s21, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s19, v0
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s10, -2
s_mov_b64 s[12:13], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v0, v1
v_xor_b32_e32 v2, v2, v1
v_xor_b32_e32 v1, s16, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v6
v_mul_lo_u32 v8, v3, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v8
v_add_nc_u32_e32 v8, 1, v3
v_subrev_nc_u32_e32 v9, s17, v2
v_cmp_le_u32_e32 vcc_lo, s17, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v8 :: v_dual_cndmask_b32 v2, v2, v9
v_add_nc_u32_e32 v8, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s17, v2
v_cndmask_b32_e32 v2, v3, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v3, v1, v2
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, s8, v3, s[8:9]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s8, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v8, v0, v8, -2
.LBB0_25:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, s10, v1
s_mov_b64 s[14:15], 0
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v9, v10
v_xor_b32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v11, v9, v6
v_mul_lo_u32 v11, v11, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v9, v11
v_subrev_nc_u32_e32 v11, s17, v9
v_cmp_le_u32_e32 vcc_lo, s17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v9, v11, vcc_lo
v_subrev_nc_u32_e32 v11, s17, v9
v_cmp_le_u32_e32 vcc_lo, s17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v9, v11, vcc_lo
v_xor_b32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, v9, v10
v_mov_b32_e32 v10, v8
v_mul_lo_u32 v9, v9, s8
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_26:
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
s_add_u32 s22, s12, s14
s_addc_u32 s23, s13, s15
s_add_u32 s14, s14, 8
s_load_b64 s[22:23], s[22:23], 0x0
v_add_nc_u32_e32 v12, v10, v11
v_add_nc_u32_e32 v10, 1, v10
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s14, 40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v12, v12, v11
v_mul_hi_u32 v13, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, v13, s17
v_sub_nc_u32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s17, v12
v_cmp_le_u32_e32 vcc_lo, s17, v12
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s17, v12
v_cmp_le_u32_e32 vcc_lo, s17, v12
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v12, v12, v11
v_sub_nc_u32_e32 v11, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v11, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[11:12], v11
s_waitcnt lgkmcnt(0)
v_fma_f64 v[2:3], s[22:23], v[11:12], v[2:3]
s_cbranch_scc0 .LBB0_26
s_set_inst_prefetch_distance 0x2
s_add_i32 s10, s10, 1
s_add_u32 s12, s12, 40
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s10, 3
s_cbranch_scc0 .LBB0_25
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_nlt_f64_e32 s[6:7], v[2:3]
s_xor_b32 s12, exec_lo, s10
s_cbranch_execz .LBB0_34
s_mov_b32 s10, s6
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cmp_ngt_f64_e32 vcc_lo, s[10:11], v[2:3]
s_and_saveexec_b32 s10, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_31
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_31:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_33
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s10
.LBB0_34:
s_and_not1_saveexec_b32 s10, s12
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v7, off
s_branch .LBB0_2
.LBB0_36:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15spinCalculationiPdPiS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15spinCalculationiPdPiS0_iii, .Lfunc_end0-_Z15spinCalculationiPdPiS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15spinCalculationiPdPiS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z15spinCalculationiPdPiS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <stdbool.h>
static int grid_array[5]={5,9,16,23,30};
static int block_array[5]={2,3,5,10,12};
static FILE *pointerToFile;
__device__
static void calculate(int *readingArray, int* writingArray, double *weights, int n ,int current,int xAxes, int yAxes){
double Sum = 0;
if(current < n*n)
{
// loop through all the points that affect
for(int p=-2;p<3;p++){
for(int q=-2;q<3;q++){
Sum += weights[(p+2)*5+(q+2)] * readingArray[((p + yAxes + n) % n) * n + ( q + xAxes + n) % n];
// index properly in order to include the wrap points
// add the weight to Sum
}
}
// check to decide which value the current spin should take
if(Sum > 0.00001)// set to 0.000001 in order to take into account
// floating points
writingArray[current] = 1;
else if(Sum < -0.00001)
writingArray[current] = -1;
else // if it is zero then let the value remain the same
writingArray[current] = readingArray[current];
}
}
// cuda function to parallelize the spin calculation
__global__ void spinCalculation(int n, double * gpuWeights,int *gpuG,int *gpuGTemp,int i,int block,int looper) {
// variable to hold the sum of the weights
int current = blockIdx.x * block * block + threadIdx.x; // calculation of the current index
int xAxes;
int yAxes;
for(int q=0;q<looper;q++)
{
// switch the i%2 which is the current number of iretarion
// so periodically we will be writing to gpuGTemp and then to gpuG
switch (i%2) {
case 0:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuG,gpuGTemp,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
// here everything is the same with the difference that is reading from the gpuGTemp array
// and write to the gpuG
case 1:
xAxes=(current*looper+q)%n;
yAxes=(current*looper+q)/n;
calculate(gpuGTemp,gpuG,gpuWeights,n,current*looper+q,xAxes,yAxes);
break;
}
}
}
void takeBinData(int *array, FILE *file,int n){
if (file==NULL)
{
printf("error opening file");
exit(1);
}
fread(array,sizeof(int),n*n,file);
fclose(file);
}
void ising (int *G, double *w, int k, int n,int grid ,int block)
{
int looper= n*n/(grid*grid*block*block) + 1;
double *weights;
hipMalloc(&weights,sizeof(double)*25);
hipMemcpy(weights,w,25*sizeof(double),hipMemcpyHostToDevice);
int *tempG=(int *) malloc(sizeof(int)*n*n);
memcpy(tempG,G,n*n*sizeof(int));
int *gpuTempG;
hipMalloc(&gpuTempG,n*n*sizeof(int));
int *gpuG;
hipMalloc(&gpuG,n*n*sizeof(int));
hipMemcpy(gpuTempG,tempG,n*n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(gpuG,G,n*n*sizeof(int),hipMemcpyHostToDevice);
for(int i=0;i<k;i++){
spinCalculation<<<grid*grid,block*block>>>(n,weights,gpuG,gpuTempG,i,block,looper);
hipDeviceSynchronize();
}
if(k%2==1){
hipMemcpy(G,gpuTempG,n*n*sizeof(int),hipMemcpyDeviceToHost);
}
else{
hipMemcpy(G,gpuG,n*n*sizeof(int),hipMemcpyDeviceToHost);
}
hipFree(gpuG);
hipFree(gpuTempG);
free(tempG);
}
void checkCorrectness(int *G, int *expectedState,int n,int k){
bool noMistake=true;
int counter=0;
for(int i=0;i<n*n;i++)
{
if(expectedState[i]!=G[i])
{
//printf("wrong in index %d\n",i );
counter++;
noMistake=false;
}
}
if (noMistake) {
printf("ising for k=%d is correct\n",k );
}
else{
printf("ising for k=%d is wrong\n",k );
}
printf("%d\n",counter );
}
int main(){
int n=517;
int grid,block;
for(int i=0;i<5;i++){
for(int j=0;j<5;j++)
{
grid=grid_array[i];
block=block_array[j];
int *initialG=(int *) malloc(sizeof(int)*n*n);
int *G=(int *)malloc(sizeof(int)*n*n);
int *expectedState=(int *)malloc(sizeof(int)*n*n);
FILE *file;
file= fopen("conf-init.bin","rb");
takeBinData(initialG,file,n);
memcpy(G,initialG,sizeof(int)*n*n);
double weights[] = {0.004, 0.016, 0.026, 0.016, 0.004,
0.016, 0.071, 0.117, 0.071, 0.016,
0.026, 0.117, 0, 0.117, 0.026,
0.016, 0.071, 0.117, 0.071, 0.016,
0.004, 0.016, 0.026, 0.016, 0.004};
clock_t start,end;
start=clock();
ising(G,weights,1,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC);
file=fopen("conf-1.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,1);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,4,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-4.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,4);
memcpy(G,initialG,sizeof(int)*n*n);
start=clock();
ising(G,weights,11,n,grid,block);
end=clock();
printf("%lf\n",((double)(end-start))/CLOCKS_PER_SEC );
file =fopen("conf-11.bin","rb");
takeBinData(expectedState,file,n);
checkCorrectness(G,expectedState,n,11);
}
}
return 0;
} | .text
.file "V2.hip"
.globl _Z30__device_stub__spinCalculationiPdPiS0_iii # -- Begin function _Z30__device_stub__spinCalculationiPdPiS0_iii
.p2align 4, 0x90
.type _Z30__device_stub__spinCalculationiPdPiS0_iii,@function
_Z30__device_stub__spinCalculationiPdPiS0_iii: # @_Z30__device_stub__spinCalculationiPdPiS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15spinCalculationiPdPiS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__spinCalculationiPdPiS0_iii, .Lfunc_end0-_Z30__device_stub__spinCalculationiPdPiS0_iii
.cfi_endproc
# -- End function
.globl _Z11takeBinDataPiP8_IO_FILEi # -- Begin function _Z11takeBinDataPiP8_IO_FILEi
.p2align 4, 0x90
.type _Z11takeBinDataPiP8_IO_FILEi,@function
_Z11takeBinDataPiP8_IO_FILEi: # @_Z11takeBinDataPiP8_IO_FILEi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
# kill: def $edx killed $edx def $rdx
testq %rsi, %rsi
je .LBB1_1
# %bb.2:
movq %rsi, %rbx
imull %edx, %edx
movl $4, %esi
movq %rbx, %rcx
callq fread
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11takeBinDataPiP8_IO_FILEi, .Lfunc_end1-_Z11takeBinDataPiP8_IO_FILEi
.cfi_endproc
# -- End function
.globl _Z5isingPiPdiiii # -- Begin function _Z5isingPiPdiiii
.p2align 4, 0x90
.type _Z5isingPiPdiiii,@function
_Z5isingPiPdiiii: # @_Z5isingPiPdiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movl %edx, %ebp
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, %r14
movl %ecx, %ebx
imull %ebx, %ebx
imull %r8d, %r8d
movl %r9d, 44(%rsp) # 4-byte Spill
movl %r9d, %r13d
imull %r13d, %r13d
movl %r13d, %ecx
movl %r8d, 36(%rsp) # 4-byte Spill
imull %r8d, %ecx
xorl %r12d, %r12d
movl %ebx, %eax
xorl %edx, %edx
idivl %ecx
movl %eax, 40(%rsp) # 4-byte Spill
leaq 64(%rsp), %rdi
movl $200, %esi
callq hipMalloc
movq 64(%rsp), %rdi
movl $200, %edx
movq 24(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl %r15d, 24(%rsp) # 4-byte Spill
movslq %r15d, %rdi
imulq %rdi, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r15
shlq $2, %rbx
movq %rax, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, 72(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movl 40(%rsp), %r14d # 4-byte Reload
movq %rsi, 80(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %ebp, %ebp
jle .LBB2_5
# %bb.1: # %.lr.ph
incl %r14d
movl 36(%rsp), %r15d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
orq %rax, %r13
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
callq hipDeviceSynchronize
incl %r12d
cmpl %r12d, %ebp
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq 64(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movl 24(%rsp), %esi # 4-byte Reload
movl %esi, 60(%rsp)
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r12d, 56(%rsp)
movl 44(%rsp), %eax # 4-byte Reload
movl %eax, 52(%rsp)
movl %r14d, 48(%rsp)
leaq 60(%rsp), %rax
movq %rax, 160(%rsp)
leaq 152(%rsp), %rax
movq %rax, 168(%rsp)
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 52(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z15spinCalculationiPdPiS0_iii, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_5: # %._crit_edge
andl $-2147483647, %ebp # imm = 0x80000001
cmpl $1, %ebp
leaq 16(%rsp), %rax
leaq 8(%rsp), %rcx
cmoveq %rax, %rcx
movq (%rcx), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi # 8-byte Reload
callq free
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5isingPiPdiiii, .Lfunc_end2-_Z5isingPiPdiiii
.cfi_endproc
# -- End function
.globl _Z16checkCorrectnessPiS_ii # -- Begin function _Z16checkCorrectnessPiS_ii
.p2align 4, 0x90
.type _Z16checkCorrectnessPiS_ii,@function
_Z16checkCorrectnessPiS_ii: # @_Z16checkCorrectnessPiS_ii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
# kill: def $edx killed $edx def $rdx
testl %edx, %edx
je .LBB3_1
# %bb.4: # %.lr.ph.preheader
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
movb $1, %al
xorl %r8d, %r8d
xorl %r9d, %r9d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%r9,4), %r10d
xorl %r11d, %r11d
cmpl (%rdi,%r9,4), %r10d
movzbl %al, %eax
cmovnel %r8d, %eax
setne %r11b
addl %r11d, %ebx
incq %r9
cmpq %r9, %rdx
jne .LBB3_5
# %bb.2: # %._crit_edge.loopexit
testb $1, %al
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
jmp .LBB3_3
.LBB3_1:
xorl %ebx, %ebx
movl $.L.str.1, %edi
.LBB3_3: # %._crit_edge
movl %ecx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z16checkCorrectnessPiS_ii, .Lfunc_end3-_Z16checkCorrectnessPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebp, %ebp
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_8 Depth 3
# Child Loop BB4_11 Depth 3
# Child Loop BB4_14 Depth 3
movq %rax, 16(%rsp) # 8-byte Spill
movl _ZL10grid_array(,%rax,4), %eax
movl %eax, (%rsp) # 4-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_8 Depth 3
# Child Loop BB4_11 Depth 3
# Child Loop BB4_14 Depth 3
movl _ZL11block_array(,%r12,4), %eax
movl %eax, 4(%rsp) # 4-byte Spill
movl $1069156, %edi # imm = 0x105064
callq malloc
movq %rax, %r13
movl $1069156, %edi # imm = 0x105064
callq malloc
movq %rax, %r14
movl $1069156, %edi # imm = 0x105064
callq malloc
movq %rax, %r15
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.6: # %_Z11takeBinDataPiP8_IO_FILEi.exit
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movq %r12, 24(%rsp) # 8-byte Spill
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r13, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movl $1069156, %edx # imm = 0x105064
movq %r14, %rdi
movq %r13, 8(%rsp) # 8-byte Spill
movq %r13, %rsi
callq memcpy@PLT
movl $.L__const.main.weights, %esi
movl $200, %edx
leaq 32(%rsp), %r12
movq %r12, %rdi
callq memcpy@PLT
callq clock
movq %rax, %rbx
movq %r14, %rdi
movq %r12, %rsi
movl $1, %edx
movl $517, %ecx # imm = 0x205
movl (%rsp), %r8d # 4-byte Reload
movl 4(%rsp), %r13d # 4-byte Reload
movl %r13d, %r9d
callq _Z5isingPiPdiiii
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.7: # %_Z11takeBinDataPiP8_IO_FILEi.exit64
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movl %r13d, %r12d
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r15, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movb $1, %al
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_8: # %.lr.ph.i
# Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%rcx,4), %edx
xorl %esi, %esi
cmpl (%r14,%rcx,4), %edx
movzbl %al, %eax
cmovnel %ebp, %eax
setne %sil
addl %esi, %ebx
incq %rcx
cmpq $267289, %rcx # imm = 0x41419
jne .LBB4_8
# %bb.9: # %._crit_edge.loopexit.i
# in Loop: Header=BB4_2 Depth=2
testb $1, %al
movl $.L.str.1, %edi
movl $.L.str.2, %r13d
cmoveq %r13, %rdi
movl $1, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $1069156, %edx # imm = 0x105064
movq %r14, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
callq memcpy@PLT
callq clock
movq %rax, %rbx
movq %r14, %rdi
leaq 32(%rsp), %rsi
movl $4, %edx
movl $517, %ecx # imm = 0x205
movl (%rsp), %r8d # 4-byte Reload
movl %r12d, %r9d
callq _Z5isingPiPdiiii
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.8, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.10: # %_Z11takeBinDataPiP8_IO_FILEi.exit65
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r15, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movb $1, %al
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_11: # %.lr.ph.i66
# Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%rcx,4), %edx
xorl %esi, %esi
cmpl (%r14,%rcx,4), %edx
movzbl %al, %eax
cmovnel %ebp, %eax
setne %sil
addl %esi, %ebx
incq %rcx
cmpq $267289, %rcx # imm = 0x41419
jne .LBB4_11
# %bb.12: # %._crit_edge.loopexit.i75
# in Loop: Header=BB4_2 Depth=2
testb $1, %al
movl $.L.str.1, %edi
cmoveq %r13, %rdi
movl $4, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $1069156, %edx # imm = 0x105064
movq %r14, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
callq memcpy@PLT
callq clock
movq %rax, %rbx
movq %r14, %rdi
leaq 32(%rsp), %rsi
movl $11, %edx
movl $517, %ecx # imm = 0x205
movl (%rsp), %r8d # 4-byte Reload
movl %r12d, %r9d
callq _Z5isingPiPdiiii
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.9, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.13: # %_Z11takeBinDataPiP8_IO_FILEi.exit77
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r15, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movb $1, %al
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_14: # %.lr.ph.i78
# Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%rcx,4), %edx
xorl %esi, %esi
cmpl (%r14,%rcx,4), %edx
movzbl %al, %eax
cmovnel %ebp, %eax
setne %sil
addl %esi, %ebx
incq %rcx
cmpq $267289, %rcx # imm = 0x41419
jne .LBB4_14
# %bb.15: # %._crit_edge.loopexit.i87
# in Loop: Header=BB4_2 Depth=2
testb $1, %al
movl $.L.str.1, %edi
cmoveq %r13, %rdi
movl $11, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %r12 # 8-byte Reload
incq %r12
cmpq $5, %r12
jne .LBB4_2
# %bb.4: # in Loop: Header=BB4_1 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
incq %rax
cmpq $5, %rax
jne .LBB4_1
# %bb.5:
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 288
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15spinCalculationiPdPiS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15spinCalculationiPdPiS0_iii,@object # @_Z15spinCalculationiPdPiS0_iii
.section .rodata,"a",@progbits
.globl _Z15spinCalculationiPdPiS0_iii
.p2align 3, 0x0
_Z15spinCalculationiPdPiS0_iii:
.quad _Z30__device_stub__spinCalculationiPdPiS0_iii
.size _Z15spinCalculationiPdPiS0_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error opening file"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ising for k=%d is correct\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ising for k=%d is wrong\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type _ZL10grid_array,@object # @_ZL10grid_array
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL10grid_array:
.long 5 # 0x5
.long 9 # 0x9
.long 16 # 0x10
.long 23 # 0x17
.long 30 # 0x1e
.size _ZL10grid_array, 20
.type _ZL11block_array,@object # @_ZL11block_array
.p2align 4, 0x0
_ZL11block_array:
.long 2 # 0x2
.long 3 # 0x3
.long 5 # 0x5
.long 10 # 0xa
.long 12 # 0xc
.size _ZL11block_array, 20
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "conf-init.bin"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L__const.main.weights,@object # @__const.main.weights
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.weights:
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x0000000000000000 # double 0
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.size .L__const.main.weights, 200
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%lf\n"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "conf-1.bin"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "conf-4.bin"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "conf-11.bin"
.size .L.str.9, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15spinCalculationiPdPiS0_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__spinCalculationiPdPiS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15spinCalculationiPdPiS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019ebf5_00000000-6_V2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "error opening file"
.text
.globl _Z11takeBinDataPiP8_IO_FILEi
.type _Z11takeBinDataPiP8_IO_FILEi, @function
_Z11takeBinDataPiP8_IO_FILEi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
testq %rsi, %rsi
je .L6
movq %rsi, %rbx
imull %edx, %edx
movslq %edx, %rcx
movq %rsi, %r8
movl $4, %edx
movq $-1, %rsi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11takeBinDataPiP8_IO_FILEi, .-_Z11takeBinDataPiP8_IO_FILEi
.section .rodata.str1.1
.LC1:
.string "ising for k=%d is correct\n"
.LC2:
.string "ising for k=%d is wrong\n"
.LC3:
.string "%d\n"
.text
.globl _Z16checkCorrectnessPiS_ii
.type _Z16checkCorrectnessPiS_ii, @function
_Z16checkCorrectnessPiS_ii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
imull %edx, %edx
testl %edx, %edx
jle .L13
movq %rdi, %r8
movslq %edx, %rdx
leaq 0(,%rdx,4), %rdi
movl $0, %eax
movl $0, %ebx
movl $1, %r9d
movl $0, %r10d
jmp .L10
.L9:
addq $4, %rax
cmpq %rax, %rdi
je .L16
.L10:
movl (%r8,%rax), %edx
cmpl %edx, (%rsi,%rax)
je .L9
addl $1, %ebx
movl %r10d, %r9d
jmp .L9
.L16:
testb %r9b, %r9b
jne .L8
movl %ecx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L13:
movl $0, %ebx
.L8:
movl %ecx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z16checkCorrectnessPiS_ii, .-_Z16checkCorrectnessPiS_ii
.globl _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
.type _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii, @function
_Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15spinCalculationiPdPiS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii, .-_Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
.globl _Z15spinCalculationiPdPiS0_iii
.type _Z15spinCalculationiPdPiS0_iii, @function
_Z15spinCalculationiPdPiS0_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15spinCalculationiPdPiS0_iii, .-_Z15spinCalculationiPdPiS0_iii
.globl _Z5isingPiPdiiii
.type _Z5isingPiPdiiii, @function
_Z5isingPiPdiiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, %rbx
movl %edx, %r13d
movl %ecx, %r15d
movl %ecx, 16(%rsp)
movl %r9d, %r14d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
imull %r8d, %r8d
movl %r8d, %r12d
movl %ecx, %eax
imull %ecx, %eax
movl %r8d, %ecx
imull %r9d, %ecx
imull %r9d, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 20(%rsp)
leaq 40(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq %r15d, %rbp
imulq %rbp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movq (%rsp), %r15
movq %r15, %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L26
movl %r14d, %r15d
imull %r14d, %r15d
movl $0, %ebx
movq %rbp, 24(%rsp)
movl 20(%rsp), %ebp
jmp .L28
.L27:
call cudaDeviceSynchronize@PLT
addl $1, %ebx
cmpl %ebx, %r13d
je .L33
.L28:
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rbp
.cfi_def_cfa_offset 176
movl %r14d, %r9d
movl %ebx, %r8d
movq 64(%rsp), %rcx
movq 72(%rsp), %rdx
movq 56(%rsp), %rsi
movl 32(%rsp), %edi
call _Z44__device_stub__Z15spinCalculationiPdPiS0_iiiiPdPiS0_iii
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L33:
movq 24(%rsp), %rbp
movl %ebx, %eax
shrl $31, %eax
addl %eax, %ebx
andl $1, %ebx
subl %eax, %ebx
cmpl $1, %ebx
je .L34
.L26:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
.L29:
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
jmp .L29
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z5isingPiPdiiii, .-_Z5isingPiPdiiii
.section .rodata.str1.1
.LC4:
.string "rb"
.LC5:
.string "conf-init.bin"
.LC13:
.string "%lf\n"
.LC14:
.string "conf-1.bin"
.LC15:
.string "conf-4.bin"
.LC16:
.string "conf-11.bin"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq _ZL10grid_array(%rip), %rdx
movq .LC7(%rip), %r14
.L37:
leaq _ZL11block_array(%rip), %r13
movq %rdx, 40(%rsp)
.L38:
movq 40(%rsp), %rax
movl (%rax), %eax
movl %eax, 8(%rsp)
movl 0(%r13), %ecx
movl %ecx, 12(%rsp)
movl $1069156, %edi
call malloc@PLT
movq %rax, %r12
movl $1069156, %edi
call malloc@PLT
movq %rax, %rbx
movl $1069156, %edi
call malloc@PLT
movq %rax, %rbp
leaq .LC4(%rip), %r15
movq %r15, %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %r12, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $1069156, %edx
movq %r12, 16(%rsp)
movq %r12, %rsi
movq %rbx, %rdi
call memcpy@PLT
movq .LC6(%rip), %rdx
movq %rdx, 48(%rsp)
movq %r14, 56(%rsp)
movq .LC8(%rip), %rdx
movq %rdx, 64(%rsp)
movq %r14, 72(%rsp)
movq .LC6(%rip), %rdx
movq %rdx, 80(%rsp)
movq %r14, 88(%rsp)
movq .LC9(%rip), %rdx
movq %rdx, 96(%rsp)
movsd .LC10(%rip), %xmm0
movsd %xmm0, 104(%rsp)
movq %rdx, 112(%rsp)
movq %r14, 120(%rsp)
movq .LC8(%rip), %rdx
movq %rdx, 128(%rsp)
movsd %xmm0, 136(%rsp)
movq $0x000000000, 144(%rsp)
movsd %xmm0, 152(%rsp)
movq %rdx, 160(%rsp)
movq %r14, 168(%rsp)
movq .LC9(%rip), %rdx
movq %rdx, 176(%rsp)
movsd %xmm0, 184(%rsp)
movq %rdx, 192(%rsp)
movq %r14, 200(%rsp)
movq .LC6(%rip), %rdx
movq %rdx, 208(%rsp)
movq %r14, 216(%rsp)
movq .LC8(%rip), %rdi
movq %rdi, 224(%rsp)
movq %r14, 232(%rsp)
movq %rdx, 240(%rsp)
call clock@PLT
movq %rax, %r12
leaq 48(%rsp), %rdi
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl $517, %ecx
movl $1, %edx
movq %rdi, 24(%rsp)
movq %rdi, %rsi
movq %rbx, %rdi
call _Z5isingPiPdiiii
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
leaq .LC13(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %rbp, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $1, %ecx
movl $517, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16checkCorrectnessPiS_ii
movl $1069156, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call memcpy@PLT
call clock@PLT
movq %rax, 32(%rsp)
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl $517, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call _Z5isingPiPdiiii
call clock@PLT
movq 32(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rsi
leaq .LC15(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %rbp, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $4, %ecx
movl $517, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16checkCorrectnessPiS_ii
movl $1069156, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call memcpy@PLT
call clock@PLT
movq %rax, 16(%rsp)
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl $517, %ecx
movl $11, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call _Z5isingPiPdiiii
call clock@PLT
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rsi
leaq .LC16(%rip), %rdi
call fopen@PLT
movq %rax, %rsi
movl $517, %edx
movq %rbp, %rdi
call _Z11takeBinDataPiP8_IO_FILEi
movl $11, %ecx
movl $517, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16checkCorrectnessPiS_ii
addq $4, %r13
leaq 20+_ZL11block_array(%rip), %rax
cmpq %rax, %r13
jne .L38
movq 40(%rsp), %rdx
addq $4, %rdx
leaq 20+_ZL10grid_array(%rip), %rax
cmpq %rax, %rdx
jne .L37
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC17:
.string "_Z15spinCalculationiPdPiS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z15spinCalculationiPdPiS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 16
.type _ZL11block_array, @object
.size _ZL11block_array, 20
_ZL11block_array:
.long 2
.long 3
.long 5
.long 10
.long 12
.align 16
.type _ZL10grid_array, @object
.size _ZL10grid_array, 20
_ZL10grid_array:
.long 5
.long 9
.long 16
.long 23
.long 30
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -755914244
.long 1064329805
.align 8
.LC7:
.long -755914244
.long 1066426957
.align 8
.LC8:
.long 1992864825
.long 1067098046
.align 8
.LC9:
.long 1443109011
.long 1068641550
.align 8
.LC10:
.long 1168231105
.long 1069413302
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "V2.hip"
.globl _Z30__device_stub__spinCalculationiPdPiS0_iii # -- Begin function _Z30__device_stub__spinCalculationiPdPiS0_iii
.p2align 4, 0x90
.type _Z30__device_stub__spinCalculationiPdPiS0_iii,@function
_Z30__device_stub__spinCalculationiPdPiS0_iii: # @_Z30__device_stub__spinCalculationiPdPiS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15spinCalculationiPdPiS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__spinCalculationiPdPiS0_iii, .Lfunc_end0-_Z30__device_stub__spinCalculationiPdPiS0_iii
.cfi_endproc
# -- End function
.globl _Z11takeBinDataPiP8_IO_FILEi # -- Begin function _Z11takeBinDataPiP8_IO_FILEi
.p2align 4, 0x90
.type _Z11takeBinDataPiP8_IO_FILEi,@function
_Z11takeBinDataPiP8_IO_FILEi: # @_Z11takeBinDataPiP8_IO_FILEi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
# kill: def $edx killed $edx def $rdx
testq %rsi, %rsi
je .LBB1_1
# %bb.2:
movq %rsi, %rbx
imull %edx, %edx
movl $4, %esi
movq %rbx, %rcx
callq fread
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11takeBinDataPiP8_IO_FILEi, .Lfunc_end1-_Z11takeBinDataPiP8_IO_FILEi
.cfi_endproc
# -- End function
.globl _Z5isingPiPdiiii # -- Begin function _Z5isingPiPdiiii
.p2align 4, 0x90
.type _Z5isingPiPdiiii,@function
_Z5isingPiPdiiii: # @_Z5isingPiPdiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movl %edx, %ebp
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, %r14
movl %ecx, %ebx
imull %ebx, %ebx
imull %r8d, %r8d
movl %r9d, 44(%rsp) # 4-byte Spill
movl %r9d, %r13d
imull %r13d, %r13d
movl %r13d, %ecx
movl %r8d, 36(%rsp) # 4-byte Spill
imull %r8d, %ecx
xorl %r12d, %r12d
movl %ebx, %eax
xorl %edx, %edx
idivl %ecx
movl %eax, 40(%rsp) # 4-byte Spill
leaq 64(%rsp), %rdi
movl $200, %esi
callq hipMalloc
movq 64(%rsp), %rdi
movl $200, %edx
movq 24(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl %r15d, 24(%rsp) # 4-byte Spill
movslq %r15d, %rdi
imulq %rdi, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r15
shlq $2, %rbx
movq %rax, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, 72(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movl 40(%rsp), %r14d # 4-byte Reload
movq %rsi, 80(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %ebp, %ebp
jle .LBB2_5
# %bb.1: # %.lr.ph
incl %r14d
movl 36(%rsp), %r15d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
orq %rax, %r13
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
callq hipDeviceSynchronize
incl %r12d
cmpl %r12d, %ebp
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq 64(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movl 24(%rsp), %esi # 4-byte Reload
movl %esi, 60(%rsp)
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r12d, 56(%rsp)
movl 44(%rsp), %eax # 4-byte Reload
movl %eax, 52(%rsp)
movl %r14d, 48(%rsp)
leaq 60(%rsp), %rax
movq %rax, 160(%rsp)
leaq 152(%rsp), %rax
movq %rax, 168(%rsp)
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 52(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z15spinCalculationiPdPiS0_iii, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_5: # %._crit_edge
andl $-2147483647, %ebp # imm = 0x80000001
cmpl $1, %ebp
leaq 16(%rsp), %rax
leaq 8(%rsp), %rcx
cmoveq %rax, %rcx
movq (%rcx), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi # 8-byte Reload
callq free
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5isingPiPdiiii, .Lfunc_end2-_Z5isingPiPdiiii
.cfi_endproc
# -- End function
.globl _Z16checkCorrectnessPiS_ii # -- Begin function _Z16checkCorrectnessPiS_ii
.p2align 4, 0x90
.type _Z16checkCorrectnessPiS_ii,@function
_Z16checkCorrectnessPiS_ii: # @_Z16checkCorrectnessPiS_ii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
# kill: def $edx killed $edx def $rdx
testl %edx, %edx
je .LBB3_1
# %bb.4: # %.lr.ph.preheader
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
movb $1, %al
xorl %r8d, %r8d
xorl %r9d, %r9d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%r9,4), %r10d
xorl %r11d, %r11d
cmpl (%rdi,%r9,4), %r10d
movzbl %al, %eax
cmovnel %r8d, %eax
setne %r11b
addl %r11d, %ebx
incq %r9
cmpq %r9, %rdx
jne .LBB3_5
# %bb.2: # %._crit_edge.loopexit
testb $1, %al
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
jmp .LBB3_3
.LBB3_1:
xorl %ebx, %ebx
movl $.L.str.1, %edi
.LBB3_3: # %._crit_edge
movl %ecx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z16checkCorrectnessPiS_ii, .Lfunc_end3-_Z16checkCorrectnessPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebp, %ebp
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_8 Depth 3
# Child Loop BB4_11 Depth 3
# Child Loop BB4_14 Depth 3
movq %rax, 16(%rsp) # 8-byte Spill
movl _ZL10grid_array(,%rax,4), %eax
movl %eax, (%rsp) # 4-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_8 Depth 3
# Child Loop BB4_11 Depth 3
# Child Loop BB4_14 Depth 3
movl _ZL11block_array(,%r12,4), %eax
movl %eax, 4(%rsp) # 4-byte Spill
movl $1069156, %edi # imm = 0x105064
callq malloc
movq %rax, %r13
movl $1069156, %edi # imm = 0x105064
callq malloc
movq %rax, %r14
movl $1069156, %edi # imm = 0x105064
callq malloc
movq %rax, %r15
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.6: # %_Z11takeBinDataPiP8_IO_FILEi.exit
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movq %r12, 24(%rsp) # 8-byte Spill
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r13, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movl $1069156, %edx # imm = 0x105064
movq %r14, %rdi
movq %r13, 8(%rsp) # 8-byte Spill
movq %r13, %rsi
callq memcpy@PLT
movl $.L__const.main.weights, %esi
movl $200, %edx
leaq 32(%rsp), %r12
movq %r12, %rdi
callq memcpy@PLT
callq clock
movq %rax, %rbx
movq %r14, %rdi
movq %r12, %rsi
movl $1, %edx
movl $517, %ecx # imm = 0x205
movl (%rsp), %r8d # 4-byte Reload
movl 4(%rsp), %r13d # 4-byte Reload
movl %r13d, %r9d
callq _Z5isingPiPdiiii
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.7: # %_Z11takeBinDataPiP8_IO_FILEi.exit64
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movl %r13d, %r12d
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r15, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movb $1, %al
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_8: # %.lr.ph.i
# Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%rcx,4), %edx
xorl %esi, %esi
cmpl (%r14,%rcx,4), %edx
movzbl %al, %eax
cmovnel %ebp, %eax
setne %sil
addl %esi, %ebx
incq %rcx
cmpq $267289, %rcx # imm = 0x41419
jne .LBB4_8
# %bb.9: # %._crit_edge.loopexit.i
# in Loop: Header=BB4_2 Depth=2
testb $1, %al
movl $.L.str.1, %edi
movl $.L.str.2, %r13d
cmoveq %r13, %rdi
movl $1, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $1069156, %edx # imm = 0x105064
movq %r14, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
callq memcpy@PLT
callq clock
movq %rax, %rbx
movq %r14, %rdi
leaq 32(%rsp), %rsi
movl $4, %edx
movl $517, %ecx # imm = 0x205
movl (%rsp), %r8d # 4-byte Reload
movl %r12d, %r9d
callq _Z5isingPiPdiiii
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.8, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.10: # %_Z11takeBinDataPiP8_IO_FILEi.exit65
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r15, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movb $1, %al
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_11: # %.lr.ph.i66
# Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%rcx,4), %edx
xorl %esi, %esi
cmpl (%r14,%rcx,4), %edx
movzbl %al, %eax
cmovnel %ebp, %eax
setne %sil
addl %esi, %ebx
incq %rcx
cmpq $267289, %rcx # imm = 0x41419
jne .LBB4_11
# %bb.12: # %._crit_edge.loopexit.i75
# in Loop: Header=BB4_2 Depth=2
testb $1, %al
movl $.L.str.1, %edi
cmoveq %r13, %rdi
movl $4, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $1069156, %edx # imm = 0x105064
movq %r14, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
callq memcpy@PLT
callq clock
movq %rax, %rbx
movq %r14, %rdi
leaq 32(%rsp), %rsi
movl $11, %edx
movl $517, %ecx # imm = 0x205
movl (%rsp), %r8d # 4-byte Reload
movl %r12d, %r9d
callq _Z5isingPiPdiiii
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.9, %edi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.13: # %_Z11takeBinDataPiP8_IO_FILEi.exit77
# in Loop: Header=BB4_2 Depth=2
movq %rax, %rbx
movl $4, %esi
movl $267289, %edx # imm = 0x41419
movq %r15, %rdi
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movb $1, %al
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_14: # %.lr.ph.i78
# Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15,%rcx,4), %edx
xorl %esi, %esi
cmpl (%r14,%rcx,4), %edx
movzbl %al, %eax
cmovnel %ebp, %eax
setne %sil
addl %esi, %ebx
incq %rcx
cmpq $267289, %rcx # imm = 0x41419
jne .LBB4_14
# %bb.15: # %._crit_edge.loopexit.i87
# in Loop: Header=BB4_2 Depth=2
testb $1, %al
movl $.L.str.1, %edi
cmoveq %r13, %rdi
movl $11, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %r12 # 8-byte Reload
incq %r12
cmpq $5, %r12
jne .LBB4_2
# %bb.4: # in Loop: Header=BB4_1 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
incq %rax
cmpq $5, %rax
jne .LBB4_1
# %bb.5:
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 288
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15spinCalculationiPdPiS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15spinCalculationiPdPiS0_iii,@object # @_Z15spinCalculationiPdPiS0_iii
.section .rodata,"a",@progbits
.globl _Z15spinCalculationiPdPiS0_iii
.p2align 3, 0x0
_Z15spinCalculationiPdPiS0_iii:
.quad _Z30__device_stub__spinCalculationiPdPiS0_iii
.size _Z15spinCalculationiPdPiS0_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error opening file"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ising for k=%d is correct\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ising for k=%d is wrong\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type _ZL10grid_array,@object # @_ZL10grid_array
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL10grid_array:
.long 5 # 0x5
.long 9 # 0x9
.long 16 # 0x10
.long 23 # 0x17
.long 30 # 0x1e
.size _ZL10grid_array, 20
.type _ZL11block_array,@object # @_ZL11block_array
.p2align 4, 0x0
_ZL11block_array:
.long 2 # 0x2
.long 3 # 0x3
.long 5 # 0x5
.long 10 # 0xa
.long 12 # 0xc
.size _ZL11block_array, 20
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "conf-init.bin"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L__const.main.weights,@object # @__const.main.weights
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.weights:
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x0000000000000000 # double 0
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3fbdf3b645a1cac1 # double 0.11700000000000001
.quad 0x3fb22d0e56041893 # double 0.070999999999999994
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f9a9fbe76c8b439 # double 0.025999999999999999
.quad 0x3f90624dd2f1a9fc # double 0.016
.quad 0x3f70624dd2f1a9fc # double 0.0040000000000000001
.size .L__const.main.weights, 200
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%lf\n"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "conf-1.bin"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "conf-4.bin"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "conf-11.bin"
.size .L.str.9, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15spinCalculationiPdPiS0_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__spinCalculationiPdPiS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15spinCalculationiPdPiS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<limits.h>
#include<stdlib.h>
#include"cuda.h"
void print_matrix(int* mat, int rows, int cols) {
for(int i=0; i<rows; i++) {
for(int j=0; j<cols; j++) {
printf("%d ", mat[i*cols + j]);
}
printf("\n");
}
}
__global__ void sumRandC(int* mat, int n, int m, int k) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int index = tid*k;
// printf("%d\n", index);
int orig_row = index / m;
int orig_col = index % m;
int last_row = n*(m+1);
int row=orig_row, col=orig_col;
if (orig_row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
// printf("%d %d\n", row, col);
int val = mat[row*(m+1)+col];
atomicAdd(&mat[row*(m+1) + m], val);
atomicAdd(&mat[last_row + col], val);
}
}
}
// Min value to be added to each element
__device__ int min_el = INT_MAX;
__global__ void findMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int orig_index = tid*k;
int val = INT_MAX;
int index = orig_index;
int thread_min = INT_MAX;
for (int i=0; i<k; i++) {
index = orig_index + i;
if (index < n) {
// Check in last col of each row
val = mat[index*(m+1) + m];
}
else if (index < n+m) {
// Check in last row
val = mat[n*(m+1) + (index-n)];
}
else
return;
if (thread_min > val)
thread_min = val;
}
atomicMin(&min_el, thread_min);
}
__global__ void updateMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int index = tid*k;
int orig_row = index / m;
int orig_col = index % m;
int row=orig_row, col=orig_col;
if (row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
mat[row*(m+1)+col]+=min_el;
}
}
if(tid==0) {
mat[n*(m+1)+m] = min_el;
}
}
int main() {
int n,m,k;
scanf("%d %d %d", &n, &m, &k);
int *mat, *dmat;
mat = (int*)calloc((n+1)*(m+1), sizeof(int));
cudaMalloc(&dmat, (n+1)*(m+1)*sizeof(int));
cudaMemset(dmat, 0, (n+1)*(m+1)*sizeof(int));
for(int i=0; i<n; i++) {
int row = i*(m+1);
for(int j=0; j<m; j++) {
scanf("%d", &mat[row+j]);
}
}
// Initialize matrix
// for(int i=0; i<n; i++) {
// for(int j=0; j<m; j++) {
// mat[i*(m+1) + j] = rand()%9 + 1;
// }
// }
cudaMemcpy(dmat, mat, (n+1)*(m+1)*sizeof(int), cudaMemcpyHostToDevice);
int gridDim = ceil((float)(n*m) / (1024*k) );
sumRandC<<<gridDim, 1024>>>(dmat, n, m, k);
cudaDeviceSynchronize();
gridDim = ceil((float)(n+m)/(1024*k));
findMin<<<gridDim, 1024>>>(dmat, n, m, k);
cudaDeviceSynchronize();
gridDim = ceil((float)(n*m) / (1024*k) );
updateMin<<<gridDim, 1024>>>(dmat, n, m, k);
cudaMemcpy(mat, dmat, (n+1)*(m+1)*sizeof(int), cudaMemcpyDeviceToHost);
print_matrix(mat,n+1,m+1);
return 0;
} | .file "tmpxft_00166560_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPiii
.type _Z12print_matrixPiii, @function
_Z12print_matrixPiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPiii, .-_Z12print_matrixPiii
.globl _Z30__device_stub__Z8sumRandCPiiiiPiiii
.type _Z30__device_stub__Z8sumRandCPiiiiPiiii, @function
_Z30__device_stub__Z8sumRandCPiiiiPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8sumRandCPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z8sumRandCPiiiiPiiii, .-_Z30__device_stub__Z8sumRandCPiiiiPiiii
.globl _Z8sumRandCPiiii
.type _Z8sumRandCPiiii, @function
_Z8sumRandCPiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8sumRandCPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8sumRandCPiiii, .-_Z8sumRandCPiiii
.globl _Z29__device_stub__Z7findMinPiiiiPiiii
.type _Z29__device_stub__Z7findMinPiiiiPiiii, @function
_Z29__device_stub__Z7findMinPiiiiPiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7findMinPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z7findMinPiiiiPiiii, .-_Z29__device_stub__Z7findMinPiiiiPiiii
.globl _Z7findMinPiiii
.type _Z7findMinPiiii, @function
_Z7findMinPiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7findMinPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7findMinPiiii, .-_Z7findMinPiiii
.globl _Z31__device_stub__Z9updateMinPiiiiPiiii
.type _Z31__device_stub__Z9updateMinPiiiiPiiii, @function
_Z31__device_stub__Z9updateMinPiiiiPiiii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9updateMinPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z9updateMinPiiiiPiiii, .-_Z31__device_stub__Z9updateMinPiiiiPiiii
.globl _Z9updateMinPiiii
.type _Z9updateMinPiiii, @function
_Z9updateMinPiiii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9updateMinPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9updateMinPiiii, .-_Z9updateMinPiiii
.section .rodata.str1.1
.LC2:
.string "%d %d %d"
.LC3:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
leaq .LC2(%rip), %rdi
call __isoc23_scanf@PLT
movl 12(%rsp), %eax
leal 1(%rax), %ebx
movl 16(%rsp), %eax
addl $1, %eax
imull %eax, %ebx
movslq %ebx, %rbx
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r14
leaq 0(,%rbx,4), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 1(%rax), %edx
movl 16(%rsp), %eax
addl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .L36
movl $0, %r13d
leaq .LC3(%rip), %r12
.L39:
movl 16(%rsp), %edx
leal 1(%rdx), %eax
imull %r13d, %eax
testl %edx, %edx
jle .L37
cltq
leaq (%r14,%rax,4), %rbp
movl $0, %ebx
.L38:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 16(%rsp)
jg .L38
.L37:
addl $1, %r13d
movl 12(%rsp), %eax
cmpl %r13d, %eax
jg .L39
.L36:
movl 16(%rsp), %ecx
leal 1(%rcx), %edx
addl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 20(%rsp), %eax
sall $10, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L40
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L40:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L41:
call cudaDeviceSynchronize@PLT
movl 16(%rsp), %eax
addl 12(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 20(%rsp), %eax
sall $10, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L42
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L42:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L43:
call cudaDeviceSynchronize@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 20(%rsp), %eax
sall $10, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L44
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L44:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L45:
movl 12(%rsp), %eax
leal 1(%rax), %edx
movl 16(%rsp), %eax
addl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
leal 1(%rax), %edx
movl 12(%rsp), %eax
leal 1(%rax), %esi
movq %r14, %rdi
call _Z12print_matrixPiii
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8sumRandCPiiiiPiiii
jmp .L41
.L51:
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7findMinPiiiiPiiii
jmp .L43
.L52:
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z9updateMinPiiiiPiiii
jmp .L45
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9updateMinPiiii"
.LC9:
.string "_Z7findMinPiiii"
.LC10:
.string "_Z8sumRandCPiiii"
.LC11:
.string "min_el"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9updateMinPiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7findMinPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sumRandCPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6min_el(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6min_el
.comm _ZL6min_el,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<limits.h>
#include<stdlib.h>
#include"cuda.h"
void print_matrix(int* mat, int rows, int cols) {
for(int i=0; i<rows; i++) {
for(int j=0; j<cols; j++) {
printf("%d ", mat[i*cols + j]);
}
printf("\n");
}
}
__global__ void sumRandC(int* mat, int n, int m, int k) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int index = tid*k;
// printf("%d\n", index);
int orig_row = index / m;
int orig_col = index % m;
int last_row = n*(m+1);
int row=orig_row, col=orig_col;
if (orig_row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
// printf("%d %d\n", row, col);
int val = mat[row*(m+1)+col];
atomicAdd(&mat[row*(m+1) + m], val);
atomicAdd(&mat[last_row + col], val);
}
}
}
// Min value to be added to each element
__device__ int min_el = INT_MAX;
__global__ void findMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int orig_index = tid*k;
int val = INT_MAX;
int index = orig_index;
int thread_min = INT_MAX;
for (int i=0; i<k; i++) {
index = orig_index + i;
if (index < n) {
// Check in last col of each row
val = mat[index*(m+1) + m];
}
else if (index < n+m) {
// Check in last row
val = mat[n*(m+1) + (index-n)];
}
else
return;
if (thread_min > val)
thread_min = val;
}
atomicMin(&min_el, thread_min);
}
__global__ void updateMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int index = tid*k;
int orig_row = index / m;
int orig_col = index % m;
int row=orig_row, col=orig_col;
if (row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
mat[row*(m+1)+col]+=min_el;
}
}
if(tid==0) {
mat[n*(m+1)+m] = min_el;
}
}
int main() {
int n,m,k;
scanf("%d %d %d", &n, &m, &k);
int *mat, *dmat;
mat = (int*)calloc((n+1)*(m+1), sizeof(int));
cudaMalloc(&dmat, (n+1)*(m+1)*sizeof(int));
cudaMemset(dmat, 0, (n+1)*(m+1)*sizeof(int));
for(int i=0; i<n; i++) {
int row = i*(m+1);
for(int j=0; j<m; j++) {
scanf("%d", &mat[row+j]);
}
}
// Initialize matrix
// for(int i=0; i<n; i++) {
// for(int j=0; j<m; j++) {
// mat[i*(m+1) + j] = rand()%9 + 1;
// }
// }
cudaMemcpy(dmat, mat, (n+1)*(m+1)*sizeof(int), cudaMemcpyHostToDevice);
int gridDim = ceil((float)(n*m) / (1024*k) );
sumRandC<<<gridDim, 1024>>>(dmat, n, m, k);
cudaDeviceSynchronize();
gridDim = ceil((float)(n+m)/(1024*k));
findMin<<<gridDim, 1024>>>(dmat, n, m, k);
cudaDeviceSynchronize();
gridDim = ceil((float)(n*m) / (1024*k) );
updateMin<<<gridDim, 1024>>>(dmat, n, m, k);
cudaMemcpy(mat, dmat, (n+1)*(m+1)*sizeof(int), cudaMemcpyDeviceToHost);
print_matrix(mat,n+1,m+1);
return 0;
} | #include<stdio.h>
#include<limits.h>
#include<stdlib.h>
#include"hip/hip_runtime.h"
void print_matrix(int* mat, int rows, int cols) {
for(int i=0; i<rows; i++) {
for(int j=0; j<cols; j++) {
printf("%d ", mat[i*cols + j]);
}
printf("\n");
}
}
__global__ void sumRandC(int* mat, int n, int m, int k) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int index = tid*k;
// printf("%d\n", index);
int orig_row = index / m;
int orig_col = index % m;
int last_row = n*(m+1);
int row=orig_row, col=orig_col;
if (orig_row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
// printf("%d %d\n", row, col);
int val = mat[row*(m+1)+col];
atomicAdd(&mat[row*(m+1) + m], val);
atomicAdd(&mat[last_row + col], val);
}
}
}
// Min value to be added to each element
__device__ int min_el = INT_MAX;
__global__ void findMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int orig_index = tid*k;
int val = INT_MAX;
int index = orig_index;
int thread_min = INT_MAX;
for (int i=0; i<k; i++) {
index = orig_index + i;
if (index < n) {
// Check in last col of each row
val = mat[index*(m+1) + m];
}
else if (index < n+m) {
// Check in last row
val = mat[n*(m+1) + (index-n)];
}
else
return;
if (thread_min > val)
thread_min = val;
}
atomicMin(&min_el, thread_min);
}
__global__ void updateMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int index = tid*k;
int orig_row = index / m;
int orig_col = index % m;
int row=orig_row, col=orig_col;
if (row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
mat[row*(m+1)+col]+=min_el;
}
}
if(tid==0) {
mat[n*(m+1)+m] = min_el;
}
}
int main() {
int n,m,k;
scanf("%d %d %d", &n, &m, &k);
int *mat, *dmat;
mat = (int*)calloc((n+1)*(m+1), sizeof(int));
hipMalloc(&dmat, (n+1)*(m+1)*sizeof(int));
hipMemset(dmat, 0, (n+1)*(m+1)*sizeof(int));
for(int i=0; i<n; i++) {
int row = i*(m+1);
for(int j=0; j<m; j++) {
scanf("%d", &mat[row+j]);
}
}
// Initialize matrix
// for(int i=0; i<n; i++) {
// for(int j=0; j<m; j++) {
// mat[i*(m+1) + j] = rand()%9 + 1;
// }
// }
hipMemcpy(dmat, mat, (n+1)*(m+1)*sizeof(int), hipMemcpyHostToDevice);
int gridDim = ceil((float)(n*m) / (1024*k) );
sumRandC<<<gridDim, 1024>>>(dmat, n, m, k);
hipDeviceSynchronize();
gridDim = ceil((float)(n+m)/(1024*k));
findMin<<<gridDim, 1024>>>(dmat, n, m, k);
hipDeviceSynchronize();
gridDim = ceil((float)(n*m) / (1024*k) );
updateMin<<<gridDim, 1024>>>(dmat, n, m, k);
hipMemcpy(mat, dmat, (n+1)*(m+1)*sizeof(int), hipMemcpyDeviceToHost);
print_matrix(mat,n+1,m+1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<limits.h>
#include<stdlib.h>
#include"hip/hip_runtime.h"
void print_matrix(int* mat, int rows, int cols) {
for(int i=0; i<rows; i++) {
for(int j=0; j<cols; j++) {
printf("%d ", mat[i*cols + j]);
}
printf("\n");
}
}
__global__ void sumRandC(int* mat, int n, int m, int k) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int index = tid*k;
// printf("%d\n", index);
int orig_row = index / m;
int orig_col = index % m;
int last_row = n*(m+1);
int row=orig_row, col=orig_col;
if (orig_row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
// printf("%d %d\n", row, col);
int val = mat[row*(m+1)+col];
atomicAdd(&mat[row*(m+1) + m], val);
atomicAdd(&mat[last_row + col], val);
}
}
}
// Min value to be added to each element
__device__ int min_el = INT_MAX;
__global__ void findMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int orig_index = tid*k;
int val = INT_MAX;
int index = orig_index;
int thread_min = INT_MAX;
for (int i=0; i<k; i++) {
index = orig_index + i;
if (index < n) {
// Check in last col of each row
val = mat[index*(m+1) + m];
}
else if (index < n+m) {
// Check in last row
val = mat[n*(m+1) + (index-n)];
}
else
return;
if (thread_min > val)
thread_min = val;
}
atomicMin(&min_el, thread_min);
}
__global__ void updateMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int index = tid*k;
int orig_row = index / m;
int orig_col = index % m;
int row=orig_row, col=orig_col;
if (row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
mat[row*(m+1)+col]+=min_el;
}
}
if(tid==0) {
mat[n*(m+1)+m] = min_el;
}
}
int main() {
int n,m,k;
scanf("%d %d %d", &n, &m, &k);
int *mat, *dmat;
mat = (int*)calloc((n+1)*(m+1), sizeof(int));
hipMalloc(&dmat, (n+1)*(m+1)*sizeof(int));
hipMemset(dmat, 0, (n+1)*(m+1)*sizeof(int));
for(int i=0; i<n; i++) {
int row = i*(m+1);
for(int j=0; j<m; j++) {
scanf("%d", &mat[row+j]);
}
}
// Initialize matrix
// for(int i=0; i<n; i++) {
// for(int j=0; j<m; j++) {
// mat[i*(m+1) + j] = rand()%9 + 1;
// }
// }
hipMemcpy(dmat, mat, (n+1)*(m+1)*sizeof(int), hipMemcpyHostToDevice);
int gridDim = ceil((float)(n*m) / (1024*k) );
sumRandC<<<gridDim, 1024>>>(dmat, n, m, k);
hipDeviceSynchronize();
gridDim = ceil((float)(n+m)/(1024*k));
findMin<<<gridDim, 1024>>>(dmat, n, m, k);
hipDeviceSynchronize();
gridDim = ceil((float)(n*m) / (1024*k) );
updateMin<<<gridDim, 1024>>>(dmat, n, m, k);
hipMemcpy(mat, dmat, (n+1)*(m+1)*sizeof(int), hipMemcpyDeviceToHost);
print_matrix(mat,n+1,m+1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8sumRandCPiiii
.globl _Z8sumRandCPiiii
.p2align 8
.type _Z8sumRandCPiiii,@function
_Z8sumRandCPiiii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s3, 31
s_and_b32 s7, s7, 0xffff
s_add_i32 s6, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s5
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_sub_i32 s7, 0, s6
s_cmp_gt_i32 s4, 0
v_mul_lo_u32 v2, v1, s4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_ashrrev_i32_e32 v3, 31, v2
v_mul_lo_u32 v1, s7, v0
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v1, v0, v1
v_xor_b32_e32 v3, s5, v3
v_add_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v4, v0
v_mul_lo_u32 v5, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v1
v_subrev_nc_u32_e32 v6, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v4, v4, v6
v_add_nc_u32_e32 v5, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v3
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 s7, vcc_lo, s7
s_and_saveexec_b32 s8, s7
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v3, v1, s3
s_add_i32 s7, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s7, s2
v_sub_nc_u32_e32 v2, v2, v3
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s4, -1
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v0
v_mul_lo_u32 v6, v5, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v6
v_subrev_nc_u32_e32 v6, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 1, v5
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_add_nc_u32_e32 v6, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v6, vcc_lo
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v4, v3
v_mul_lo_u32 v4, v3, s3
v_add_nc_u32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v5, v3, s7
v_sub_nc_u32_e32 v6, v2, v4
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v5, v6
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
v_add_nc_u32_e32 v3, s3, v5
v_add_nc_u32_e32 v5, s2, v6
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x1
global_atomic_add_u32 v[3:4], v7, off
global_atomic_add_u32 v[5:6], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8sumRandCPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8sumRandCPiiii, .Lfunc_end0-_Z8sumRandCPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7findMinPiiii
.globl _Z7findMinPiiii
.p2align 8
.type _Z7findMinPiiii,@function
_Z7findMinPiiii:
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB1_13
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s8, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_bfrev_b32_e32 v2, -2
s_mov_b32 s4, s3
s_add_i32 s3, s3, s2
s_mul_i32 s6, s4, s2
s_add_i32 s9, s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v1, s5
v_mov_b32_e32 v4, v3
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s13
s_xor_b32 s11, s11, -1
s_and_b32 s12, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s12, s8
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s11, s11, exec_lo
s_or_b32 s7, s7, s11
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB1_11
.LBB1_3:
s_mov_b32 s12, 0
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s2, v4
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB1_7
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e64 s3, v4
s_xor_b32 s11, exec_lo, s11
s_mov_b32 s12, exec_lo
v_add_nc_u32_e32 v0, s6, v4
s_or_b32 exec_lo, exec_lo, s11
s_mov_b32 s11, -1
s_and_b32 s12, s12, exec_lo
.LBB1_7:
s_and_not1_saveexec_b32 s13, s13
v_add_nc_u32_e32 v5, s10, v3
s_or_b32 s12, s12, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v5, s9, s[4:5]
s_or_b32 exec_lo, exec_lo, s13
s_mov_b32 s14, -1
s_and_saveexec_b32 s13, s12
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, -1
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s5, 0
v_add_nc_u32_e32 v4, 1, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_cselect_b32 s12, -1, 0
s_and_not1_b32 s11, s11, exec_lo
s_or_not1_b32 s14, s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v2, v2, v0
s_branch .LBB1_2
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s0, s7
s_cbranch_execnz .LBB1_14
.LBB1_12:
s_endpgm
.LBB1_13:
v_bfrev_b32_e32 v2, -2
s_mov_b32 s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s7
s_cbranch_execz .LBB1_12
.LBB1_14:
s_mov_b32 s1, exec_lo
s_brev_b32 s0, -2
.LBB1_15:
s_ctz_i32_b32 s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s3, v2, s2
s_lshl_b32 s2, 1, s2
s_and_not1_b32 s1, s1, s2
s_delay_alu instid0(VALU_DEP_1)
s_min_i32 s0, s0, s3
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB1_15
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB1_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, min_el@rel32@lo+4
s_addc_u32 s3, s3, min_el@rel32@hi+12
global_atomic_min_i32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7findMinPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7findMinPiiii, .Lfunc_end1-_Z7findMinPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9updateMinPiiii
.globl _Z9updateMinPiiii
.p2align 8
.type _Z9updateMinPiiii,@function
_Z9updateMinPiiii:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_ashr_i32 s1, s7, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s7, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s1
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_cmp_gt_i32 s0, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v3
v_mul_lo_u32 v3, v1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v5, v3, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_xor_b32_e32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s3, v0
v_xor_b32_e32 v4, s1, v4
s_cselect_b32 s3, -1, 0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v2, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v2, s2
v_sub_nc_u32_e32 v5, v5, v6
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s2, v5
v_cmp_le_u32_e32 vcc_lo, s2, v5
v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v5
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_cmp_gt_i32_e32 vcc_lo, s6, v2
s_and_b32 s8, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s8
s_cbranch_execz .LBB2_3
v_mul_lo_u32 v4, v2, s7
s_add_i32 s8, s7, 1
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, min_el@rel32@lo+4
s_addc_u32 s11, s11, min_el@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v4
v_mov_b32_e32 v4, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v5, 31, v3
s_add_i32 s0, s0, -1
s_cmp_lg_u32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v3, v5
v_xor_b32_e32 v6, v6, v5
v_xor_b32_e32 v5, s1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v7, v6, v0
v_mul_lo_u32 v8, v7, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v6, v8
v_subrev_nc_u32_e32 v8, s2, v6
v_cmp_le_u32_e32 vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v8 :: v_dual_add_nc_u32 v9, 1, v7
v_cndmask_b32_e32 v7, v7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v6
v_add_nc_u32_e32 v8, 1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v7, v8, vcc_lo
v_xor_b32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v6, v5
v_mul_lo_u32 v6, v5, s7
v_add_nc_u32_e32 v8, v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v3, v6
v_add_nc_u32_e32 v3, 1, v3
v_mad_u64_u32 v[6:7], null, v8, s8, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[5:6], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v7, v4, s[10:11]
global_load_b32 v8, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v8, v7
global_store_b32 v[5:6], v7, off
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB2_5
v_mov_b32_e32 v0, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, min_el@rel32@lo+4
s_addc_u32 s1, s1, min_el@rel32@hi+12
global_load_b32 v1, v0, s[0:1]
s_add_i32 s0, s7, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s6
s_add_i32 s0, s0, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9updateMinPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9updateMinPiiii, .Lfunc_end2-_Z9updateMinPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected min_el
.type min_el,@object
.data
.globl min_el
.p2align 2, 0x0
min_el:
.long 2147483647
.size min_el, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym min_el
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8sumRandCPiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8sumRandCPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7findMinPiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7findMinPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9updateMinPiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9updateMinPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<limits.h>
#include<stdlib.h>
#include"hip/hip_runtime.h"
void print_matrix(int* mat, int rows, int cols) {
for(int i=0; i<rows; i++) {
for(int j=0; j<cols; j++) {
printf("%d ", mat[i*cols + j]);
}
printf("\n");
}
}
__global__ void sumRandC(int* mat, int n, int m, int k) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int index = tid*k;
// printf("%d\n", index);
int orig_row = index / m;
int orig_col = index % m;
int last_row = n*(m+1);
int row=orig_row, col=orig_col;
if (orig_row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
// printf("%d %d\n", row, col);
int val = mat[row*(m+1)+col];
atomicAdd(&mat[row*(m+1) + m], val);
atomicAdd(&mat[last_row + col], val);
}
}
}
// Min value to be added to each element
__device__ int min_el = INT_MAX;
__global__ void findMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int orig_index = tid*k;
int val = INT_MAX;
int index = orig_index;
int thread_min = INT_MAX;
for (int i=0; i<k; i++) {
index = orig_index + i;
if (index < n) {
// Check in last col of each row
val = mat[index*(m+1) + m];
}
else if (index < n+m) {
// Check in last row
val = mat[n*(m+1) + (index-n)];
}
else
return;
if (thread_min > val)
thread_min = val;
}
atomicMin(&min_el, thread_min);
}
__global__ void updateMin(int* mat, int n, int m, int k) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int index = tid*k;
int orig_row = index / m;
int orig_col = index % m;
int row=orig_row, col=orig_col;
if (row < n) {
for(int i=0; i<k; i++) {
int oc_plus_i = orig_col+i;
col = oc_plus_i%m;
row = orig_row + (oc_plus_i/m);
mat[row*(m+1)+col]+=min_el;
}
}
if(tid==0) {
mat[n*(m+1)+m] = min_el;
}
}
int main() {
int n,m,k;
scanf("%d %d %d", &n, &m, &k);
int *mat, *dmat;
mat = (int*)calloc((n+1)*(m+1), sizeof(int));
hipMalloc(&dmat, (n+1)*(m+1)*sizeof(int));
hipMemset(dmat, 0, (n+1)*(m+1)*sizeof(int));
for(int i=0; i<n; i++) {
int row = i*(m+1);
for(int j=0; j<m; j++) {
scanf("%d", &mat[row+j]);
}
}
// Initialize matrix
// for(int i=0; i<n; i++) {
// for(int j=0; j<m; j++) {
// mat[i*(m+1) + j] = rand()%9 + 1;
// }
// }
hipMemcpy(dmat, mat, (n+1)*(m+1)*sizeof(int), hipMemcpyHostToDevice);
int gridDim = ceil((float)(n*m) / (1024*k) );
sumRandC<<<gridDim, 1024>>>(dmat, n, m, k);
hipDeviceSynchronize();
gridDim = ceil((float)(n+m)/(1024*k));
findMin<<<gridDim, 1024>>>(dmat, n, m, k);
hipDeviceSynchronize();
gridDim = ceil((float)(n*m) / (1024*k) );
updateMin<<<gridDim, 1024>>>(dmat, n, m, k);
hipMemcpy(mat, dmat, (n+1)*(m+1)*sizeof(int), hipMemcpyDeviceToHost);
print_matrix(mat,n+1,m+1);
return 0;
} | .text
.file "main.hip"
.globl _Z12print_matrixPiii # -- Begin function _Z12print_matrixPiii
.p2align 4, 0x90
.type _Z12print_matrixPiii,@function
_Z12print_matrixPiii: # @_Z12print_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12print_matrixPiii, .Lfunc_end0-_Z12print_matrixPiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__sumRandCPiiii # -- Begin function _Z23__device_stub__sumRandCPiiii
.p2align 4, 0x90
.type _Z23__device_stub__sumRandCPiiii,@function
_Z23__device_stub__sumRandCPiiii: # @_Z23__device_stub__sumRandCPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8sumRandCPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__sumRandCPiiii, .Lfunc_end1-_Z23__device_stub__sumRandCPiiii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__findMinPiiii # -- Begin function _Z22__device_stub__findMinPiiii
.p2align 4, 0x90
.type _Z22__device_stub__findMinPiiii,@function
_Z22__device_stub__findMinPiiii: # @_Z22__device_stub__findMinPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7findMinPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__findMinPiiii, .Lfunc_end2-_Z22__device_stub__findMinPiiii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__updateMinPiiii # -- Begin function _Z24__device_stub__updateMinPiiii
.p2align 4, 0x90
.type _Z24__device_stub__updateMinPiiii,@function
_Z24__device_stub__updateMinPiiii: # @_Z24__device_stub__updateMinPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateMinPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z24__device_stub__updateMinPiiii, .Lfunc_end3-_Z24__device_stub__updateMinPiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rsi
leaq 8(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rax
incq %rax
movslq 8(%rsp), %r14
incq %r14
imulq %rax, %r14
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %r12
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 12(%rsp), %rax
incq %rax
movslq 8(%rsp), %rdx
incq %rdx
imulq %rax, %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB4_6
# %bb.1: # %.lr.ph58.preheader
xorl %ebp, %ebp
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incl %ebp
movl 12(%rsp), %eax
cmpl %eax, %ebp
jge .LBB4_6
.LBB4_2: # %.lr.ph58
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB4_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
incl %eax
imull %ebp, %eax
leaq (%r12,%rax,4), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.3, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movslq 8(%rsp), %rax
addq $4, %r14
cmpq %rax, %rbx
jl .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge59
movabsq $4294967296, %r15 # imm = 0x100000000
movq 32(%rsp), %rdi
cltq
incq %rax
movslq 8(%rsp), %rdx
incq %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cvtsi2ss %eax, %xmm0
movl 16(%rsp), %eax
shll $10, %eax
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r15, %rdi
leaq 1024(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 32(%rsp), %rax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, 88(%rsp)
movl %ecx, 28(%rsp)
movl %edx, 24(%rsp)
movl %esi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8sumRandCPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movl 8(%rsp), %eax
addl 12(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl 16(%rsp), %eax
shll $10, %eax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r15, %rdi
leaq 1024(%r15), %r14
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 32(%rsp), %rax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, 88(%rsp)
movl %ecx, 28(%rsp)
movl %edx, 24(%rsp)
movl %esi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7findMinPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
movl 8(%rsp), %eax
imull 12(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl 16(%rsp), %eax
shll $10, %eax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 32(%rsp), %rax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, 88(%rsp)
movl %ecx, 28(%rsp)
movl %edx, 24(%rsp)
movl %esi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9updateMinPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 32(%rsp), %rsi
movslq 12(%rsp), %rax
incq %rax
movslq 8(%rsp), %rdx
incq %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, 136(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movq %rax, 128(%rsp) # 8-byte Spill
testl %eax, %eax
js .LBB4_18
# %bb.13: # %.preheader.lr.ph.i
movl 8(%rsp), %eax
movq %rax, 144(%rsp) # 8-byte Spill
leal 1(%rax), %ebp
incq 128(%rsp) # 8-byte Folded Spill
movl %ebp, %r12d
xorl %r13d, %r13d
xorl %ebx, %ebx
jmp .LBB4_14
.p2align 4, 0x90
.LBB4_17: # %._crit_edge.i
# in Loop: Header=BB4_14 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
addl %ebp, %r13d
cmpq 128(%rsp), %rbx # 8-byte Folded Reload
je .LBB4_18
.LBB4_14: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_16 Depth 2
cmpl $0, 144(%rsp) # 4-byte Folded Reload
js .LBB4_17
# %bb.15: # %.lr.ph.i
# in Loop: Header=BB4_14 Depth=1
movl %r13d, %eax
movq 136(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_16: # Parent Loop BB4_14 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB4_16
jmp .LBB4_17
.LBB4_18: # %_Z12print_matrixPiii.exit
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sumRandCPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7findMinPiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9updateMinPiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $min_el, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type _Z8sumRandCPiiii,@object # @_Z8sumRandCPiiii
.section .rodata,"a",@progbits
.globl _Z8sumRandCPiiii
.p2align 3, 0x0
_Z8sumRandCPiiii:
.quad _Z23__device_stub__sumRandCPiiii
.size _Z8sumRandCPiiii, 8
.type min_el,@object # @min_el
.local min_el
.comm min_el,4,4
.type _Z7findMinPiiii,@object # @_Z7findMinPiiii
.globl _Z7findMinPiiii
.p2align 3, 0x0
_Z7findMinPiiii:
.quad _Z22__device_stub__findMinPiiii
.size _Z7findMinPiiii, 8
.type _Z9updateMinPiiii,@object # @_Z9updateMinPiiii
.globl _Z9updateMinPiiii
.p2align 3, 0x0
_Z9updateMinPiiii:
.quad _Z24__device_stub__updateMinPiiii
.size _Z9updateMinPiiii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d %d %d"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8sumRandCPiiii"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7findMinPiiii"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9updateMinPiiii"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "min_el"
.size .L__unnamed_4, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sumRandCPiiii
.addrsig_sym _Z22__device_stub__findMinPiiii
.addrsig_sym _Z24__device_stub__updateMinPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sumRandCPiiii
.addrsig_sym min_el
.addrsig_sym _Z7findMinPiiii
.addrsig_sym _Z9updateMinPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00166560_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPiii
.type _Z12print_matrixPiii, @function
_Z12print_matrixPiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPiii, .-_Z12print_matrixPiii
.globl _Z30__device_stub__Z8sumRandCPiiiiPiiii
.type _Z30__device_stub__Z8sumRandCPiiiiPiiii, @function
_Z30__device_stub__Z8sumRandCPiiiiPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8sumRandCPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z8sumRandCPiiiiPiiii, .-_Z30__device_stub__Z8sumRandCPiiiiPiiii
.globl _Z8sumRandCPiiii
.type _Z8sumRandCPiiii, @function
_Z8sumRandCPiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8sumRandCPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8sumRandCPiiii, .-_Z8sumRandCPiiii
.globl _Z29__device_stub__Z7findMinPiiiiPiiii
.type _Z29__device_stub__Z7findMinPiiiiPiiii, @function
_Z29__device_stub__Z7findMinPiiiiPiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7findMinPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z7findMinPiiiiPiiii, .-_Z29__device_stub__Z7findMinPiiiiPiiii
.globl _Z7findMinPiiii
.type _Z7findMinPiiii, @function
_Z7findMinPiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7findMinPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7findMinPiiii, .-_Z7findMinPiiii
.globl _Z31__device_stub__Z9updateMinPiiiiPiiii
.type _Z31__device_stub__Z9updateMinPiiiiPiiii, @function
_Z31__device_stub__Z9updateMinPiiiiPiiii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9updateMinPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z9updateMinPiiiiPiiii, .-_Z31__device_stub__Z9updateMinPiiiiPiiii
.globl _Z9updateMinPiiii
.type _Z9updateMinPiiii, @function
_Z9updateMinPiiii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9updateMinPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9updateMinPiiii, .-_Z9updateMinPiiii
.section .rodata.str1.1
.LC2:
.string "%d %d %d"
.LC3:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
leaq .LC2(%rip), %rdi
call __isoc23_scanf@PLT
movl 12(%rsp), %eax
leal 1(%rax), %ebx
movl 16(%rsp), %eax
addl $1, %eax
imull %eax, %ebx
movslq %ebx, %rbx
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r14
leaq 0(,%rbx,4), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 1(%rax), %edx
movl 16(%rsp), %eax
addl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .L36
movl $0, %r13d
leaq .LC3(%rip), %r12
.L39:
movl 16(%rsp), %edx
leal 1(%rdx), %eax
imull %r13d, %eax
testl %edx, %edx
jle .L37
cltq
leaq (%r14,%rax,4), %rbp
movl $0, %ebx
.L38:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 16(%rsp)
jg .L38
.L37:
addl $1, %r13d
movl 12(%rsp), %eax
cmpl %r13d, %eax
jg .L39
.L36:
movl 16(%rsp), %ecx
leal 1(%rcx), %edx
addl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 20(%rsp), %eax
sall $10, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L40
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L40:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L41:
call cudaDeviceSynchronize@PLT
movl 16(%rsp), %eax
addl 12(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 20(%rsp), %eax
sall $10, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L42
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L42:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L43:
call cudaDeviceSynchronize@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 20(%rsp), %eax
sall $10, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC7(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC4(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L44
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L44:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L45:
movl 12(%rsp), %eax
leal 1(%rax), %edx
movl 16(%rsp), %eax
addl $1, %eax
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %eax
leal 1(%rax), %edx
movl 12(%rsp), %eax
leal 1(%rax), %esi
movq %r14, %rdi
call _Z12print_matrixPiii
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8sumRandCPiiiiPiiii
jmp .L41
.L51:
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7findMinPiiiiPiiii
jmp .L43
.L52:
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z9updateMinPiiiiPiiii
jmp .L45
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9updateMinPiiii"
.LC9:
.string "_Z7findMinPiiii"
.LC10:
.string "_Z8sumRandCPiiii"
.LC11:
.string "min_el"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9updateMinPiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7findMinPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sumRandCPiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6min_el(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6min_el
.comm _ZL6min_el,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z12print_matrixPiii # -- Begin function _Z12print_matrixPiii
.p2align 4, 0x90
.type _Z12print_matrixPiii,@function
_Z12print_matrixPiii: # @_Z12print_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12print_matrixPiii, .Lfunc_end0-_Z12print_matrixPiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__sumRandCPiiii # -- Begin function _Z23__device_stub__sumRandCPiiii
.p2align 4, 0x90
.type _Z23__device_stub__sumRandCPiiii,@function
_Z23__device_stub__sumRandCPiiii: # @_Z23__device_stub__sumRandCPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8sumRandCPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__sumRandCPiiii, .Lfunc_end1-_Z23__device_stub__sumRandCPiiii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__findMinPiiii # -- Begin function _Z22__device_stub__findMinPiiii
.p2align 4, 0x90
.type _Z22__device_stub__findMinPiiii,@function
_Z22__device_stub__findMinPiiii: # @_Z22__device_stub__findMinPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7findMinPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__findMinPiiii, .Lfunc_end2-_Z22__device_stub__findMinPiiii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__updateMinPiiii # -- Begin function _Z24__device_stub__updateMinPiiii
.p2align 4, 0x90
.type _Z24__device_stub__updateMinPiiii,@function
_Z24__device_stub__updateMinPiiii: # @_Z24__device_stub__updateMinPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateMinPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z24__device_stub__updateMinPiiii, .Lfunc_end3-_Z24__device_stub__updateMinPiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rsi
leaq 8(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rax
incq %rax
movslq 8(%rsp), %r14
incq %r14
imulq %rax, %r14
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %r12
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 12(%rsp), %rax
incq %rax
movslq 8(%rsp), %rdx
incq %rdx
imulq %rax, %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB4_6
# %bb.1: # %.lr.ph58.preheader
xorl %ebp, %ebp
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incl %ebp
movl 12(%rsp), %eax
cmpl %eax, %ebp
jge .LBB4_6
.LBB4_2: # %.lr.ph58
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB4_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
incl %eax
imull %ebp, %eax
leaq (%r12,%rax,4), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.3, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movslq 8(%rsp), %rax
addq $4, %r14
cmpq %rax, %rbx
jl .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge59
movabsq $4294967296, %r15 # imm = 0x100000000
movq 32(%rsp), %rdi
cltq
incq %rax
movslq 8(%rsp), %rdx
incq %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cvtsi2ss %eax, %xmm0
movl 16(%rsp), %eax
shll $10, %eax
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r15, %rdi
leaq 1024(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 32(%rsp), %rax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, 88(%rsp)
movl %ecx, 28(%rsp)
movl %edx, 24(%rsp)
movl %esi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8sumRandCPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movl 8(%rsp), %eax
addl 12(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl 16(%rsp), %eax
shll $10, %eax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r15, %rdi
leaq 1024(%r15), %r14
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 32(%rsp), %rax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, 88(%rsp)
movl %ecx, 28(%rsp)
movl %edx, 24(%rsp)
movl %esi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7findMinPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
movl 8(%rsp), %eax
imull 12(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl 16(%rsp), %eax
shll $10, %eax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
orq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 32(%rsp), %rax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, 88(%rsp)
movl %ecx, 28(%rsp)
movl %edx, 24(%rsp)
movl %esi, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9updateMinPiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 32(%rsp), %rsi
movslq 12(%rsp), %rax
incq %rax
movslq 8(%rsp), %rdx
incq %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, 136(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movq %rax, 128(%rsp) # 8-byte Spill
testl %eax, %eax
js .LBB4_18
# %bb.13: # %.preheader.lr.ph.i
movl 8(%rsp), %eax
movq %rax, 144(%rsp) # 8-byte Spill
leal 1(%rax), %ebp
incq 128(%rsp) # 8-byte Folded Spill
movl %ebp, %r12d
xorl %r13d, %r13d
xorl %ebx, %ebx
jmp .LBB4_14
.p2align 4, 0x90
.LBB4_17: # %._crit_edge.i
# in Loop: Header=BB4_14 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
addl %ebp, %r13d
cmpq 128(%rsp), %rbx # 8-byte Folded Reload
je .LBB4_18
.LBB4_14: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_16 Depth 2
cmpl $0, 144(%rsp) # 4-byte Folded Reload
js .LBB4_17
# %bb.15: # %.lr.ph.i
# in Loop: Header=BB4_14 Depth=1
movl %r13d, %eax
movq 136(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_16: # Parent Loop BB4_14 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB4_16
jmp .LBB4_17
.LBB4_18: # %_Z12print_matrixPiii.exit
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sumRandCPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7findMinPiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9updateMinPiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $min_el, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type _Z8sumRandCPiiii,@object # @_Z8sumRandCPiiii
.section .rodata,"a",@progbits
.globl _Z8sumRandCPiiii
.p2align 3, 0x0
_Z8sumRandCPiiii:
.quad _Z23__device_stub__sumRandCPiiii
.size _Z8sumRandCPiiii, 8
.type min_el,@object # @min_el
.local min_el
.comm min_el,4,4
.type _Z7findMinPiiii,@object # @_Z7findMinPiiii
.globl _Z7findMinPiiii
.p2align 3, 0x0
_Z7findMinPiiii:
.quad _Z22__device_stub__findMinPiiii
.size _Z7findMinPiiii, 8
.type _Z9updateMinPiiii,@object # @_Z9updateMinPiiii
.globl _Z9updateMinPiiii
.p2align 3, 0x0
_Z9updateMinPiiii:
.quad _Z24__device_stub__updateMinPiiii
.size _Z9updateMinPiiii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d %d %d"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8sumRandCPiiii"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7findMinPiiii"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9updateMinPiiii"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "min_el"
.size .L__unnamed_4, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sumRandCPiiii
.addrsig_sym _Z22__device_stub__findMinPiiii
.addrsig_sym _Z24__device_stub__updateMinPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sumRandCPiiii
.addrsig_sym min_el
.addrsig_sym _Z7findMinPiiii
.addrsig_sym _Z9updateMinPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <float.h>
// ****************************************************************************
// DEVICE FUNCTIONS
// ****************************************************************************
// vector calculations
__device__ float getVectorLength(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
__device__ float getVectorAngle(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
__device__ float getAngleBetween(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
}
// ****************************************************************************
// HOST FUNCTIONS
// ****************************************************************************
// vector calculations
float getVectorLengthSerial(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
float getVectorAngleSerial(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
float getAngleBetweenSerial(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <float.h>
// ****************************************************************************
// DEVICE FUNCTIONS
// ****************************************************************************
// vector calculations
__device__ float getVectorLength(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
__device__ float getVectorAngle(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
__device__ float getAngleBetween(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
}
// ****************************************************************************
// HOST FUNCTIONS
// ****************************************************************************
// vector calculations
float getVectorLengthSerial(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
float getVectorAngleSerial(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
float getAngleBetweenSerial(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
} | .file "tmpxft_0002e4b2_00000000-6_vector_calculations.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15getVectorLengthff
.type _Z15getVectorLengthff, @function
_Z15getVectorLengthff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15getVectorLengthff, .-_Z15getVectorLengthff
.globl _Z14getVectorAngleff
.type _Z14getVectorAngleff, @function
_Z14getVectorAngleff:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z14getVectorAngleff, .-_Z14getVectorAngleff
.globl _Z15getAngleBetweenffff
.type _Z15getAngleBetweenffff, @function
_Z15getAngleBetweenffff:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z15getAngleBetweenffff, .-_Z15getAngleBetweenffff
.globl _Z21getVectorLengthSerialff
.type _Z21getVectorLengthSerialff, @function
_Z21getVectorLengthSerialff:
.LFB2030:
.cfi_startproc
endbr64
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
ret
.cfi_endproc
.LFE2030:
.size _Z21getVectorLengthSerialff, .-_Z21getVectorLengthSerialff
.globl _Z20getVectorAngleSerialff
.type _Z20getVectorAngleSerialff, @function
_Z20getVectorAngleSerialff:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movaps %xmm1, %xmm2
movaps %xmm0, %xmm1
movaps %xmm2, %xmm0
call atan2f@PLT
cvtss2sd %xmm0, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _Z20getVectorAngleSerialff, .-_Z20getVectorAngleSerialff
.globl _Z21getAngleBetweenSerialffff
.type _Z21getAngleBetweenSerialffff, @function
_Z21getAngleBetweenSerialffff:
.LFB2032:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps %xmm0, %xmm6
movaps %xmm1, %xmm5
movaps %xmm2, %xmm1
movaps %xmm0, %xmm4
mulss %xmm0, %xmm4
movaps %xmm5, %xmm0
mulss %xmm5, %xmm0
addss %xmm0, %xmm4
sqrtss %xmm4, %xmm4
movss .LC2(%rip), %xmm0
addss %xmm0, %xmm4
divss %xmm4, %xmm6
movss %xmm6, 4(%rsp)
divss %xmm4, %xmm5
movss %xmm5, 8(%rsp)
movaps %xmm2, %xmm4
mulss %xmm2, %xmm4
movaps %xmm3, %xmm2
mulss %xmm3, %xmm2
addss %xmm2, %xmm4
sqrtss %xmm4, %xmm4
addss %xmm0, %xmm4
divss %xmm4, %xmm3
movaps %xmm3, %xmm0
divss %xmm4, %xmm1
call atan2f@PLT
movss %xmm0, 12(%rsp)
movss 4(%rsp), %xmm1
movss 8(%rsp), %xmm0
call atan2f@PLT
movaps %xmm0, %xmm1
movss 12(%rsp), %xmm0
subss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss .LC3(%rip), %xmm1
comiss %xmm0, %xmm1
jbe .L19
addss .LC4(%rip), %xmm0
.L12:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
comiss .LC5(%rip), %xmm0
jbe .L12
subss .LC4(%rip), %xmm0
jmp .L12
.cfi_endproc
.LFE2032:
.size _Z21getAngleBetweenSerialffff, .-_Z21getAngleBetweenSerialffff
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1074340347
.align 8
.LC1:
.long 0
.long 1080459264
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 872415232
.align 4
.LC3:
.long -1020002304
.align 4
.LC4:
.long 1135869952
.align 4
.LC5:
.long 1127481344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <float.h>
// ****************************************************************************
// DEVICE FUNCTIONS
// ****************************************************************************
// vector calculations
__device__ float getVectorLength(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
__device__ float getVectorAngle(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
__device__ float getAngleBetween(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
}
// ****************************************************************************
// HOST FUNCTIONS
// ****************************************************************************
// vector calculations
float getVectorLengthSerial(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
float getVectorAngleSerial(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
float getAngleBetweenSerial(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <float.h>
// ****************************************************************************
// DEVICE FUNCTIONS
// ****************************************************************************
// vector calculations
__device__ float getVectorLength(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
__device__ float getVectorAngle(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
__device__ float getAngleBetween(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
}
// ****************************************************************************
// HOST FUNCTIONS
// ****************************************************************************
// vector calculations
float getVectorLengthSerial(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
float getVectorAngleSerial(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
float getAngleBetweenSerial(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <float.h>
// ****************************************************************************
// DEVICE FUNCTIONS
// ****************************************************************************
// vector calculations
__device__ float getVectorLength(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
__device__ float getVectorAngle(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
__device__ float getAngleBetween(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
}
// ****************************************************************************
// HOST FUNCTIONS
// ****************************************************************************
// vector calculations
float getVectorLengthSerial(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
float getVectorAngleSerial(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
float getAngleBetweenSerial(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <float.h>
// ****************************************************************************
// DEVICE FUNCTIONS
// ****************************************************************************
// vector calculations
__device__ float getVectorLength(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
__device__ float getVectorAngle(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
__device__ float getAngleBetween(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
}
// ****************************************************************************
// HOST FUNCTIONS
// ****************************************************************************
// vector calculations
float getVectorLengthSerial(float xCoord, float yCoord) {
return (float) sqrt(xCoord * xCoord + yCoord * yCoord);
}
// return the angle of the vector
float getVectorAngleSerial(float xCoord, float yCoord) {
float angleRad = atan2(yCoord, xCoord);
float angleDeg = (angleRad / M_PI) * 180.0f;
return angleDeg;
}
float getAngleBetweenSerial(float x1, float y1, float x2, float y2) {
// normalize vectors
float lenght1 = sqrt(x1 * x1 + y1 * y1) + FLT_EPSILON;
float normX1 = x1 / lenght1;
float normY1 = y1 / lenght1;
float lenght2 = sqrt(x2 * x2 + y2 * y2) + FLT_EPSILON;
float normX2 = x2 / lenght2;
float normY2 = y2 / lenght2;
// calculate angle
float angle = (atan2(normY2, normX2) - atan2(normY1, normX1)) / M_PI * 180.0f;
// correct angle at 180°-overflow
if (angle < -180.0f)
angle += 360.0f;
if (angle > 180.0f)
angle -= 360.0f;
return angle;
} | .text
.file "vector_calculations.hip"
.globl _Z21getVectorLengthSerialff # -- Begin function _Z21getVectorLengthSerialff
.p2align 4, 0x90
.type _Z21getVectorLengthSerialff,@function
_Z21getVectorLengthSerialff: # @_Z21getVectorLengthSerialff
.cfi_startproc
# %bb.0:
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
jb .LBB0_2
# %bb.1: # %.split
xorps %xmm0, %xmm0
sqrtss %xmm1, %xmm0
retq
.LBB0_2: # %call.sqrt
movaps %xmm1, %xmm0
jmp sqrtf # TAILCALL
.Lfunc_end0:
.size _Z21getVectorLengthSerialff, .Lfunc_end0-_Z21getVectorLengthSerialff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z20getVectorAngleSerialff
.LCPI1_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_1:
.quad 0x4066800000000000 # double 180
.text
.globl _Z20getVectorAngleSerialff
.p2align 4, 0x90
.type _Z20getVectorAngleSerialff,@function
_Z20getVectorAngleSerialff: # @_Z20getVectorAngleSerialff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movaps %xmm0, %xmm2
movaps %xmm1, %xmm0
movaps %xmm2, %xmm1
callq atan2f
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20getVectorAngleSerialff, .Lfunc_end1-_Z20getVectorAngleSerialff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21getAngleBetweenSerialffff
.LCPI2_0:
.long 0x34000000 # float 1.1920929E-7
.LCPI2_3:
.long 0x43b40000 # float 360
.LCPI2_4:
.long 0xc3340000 # float -180
.LCPI2_5:
.long 0xc3b40000 # float -360
.LCPI2_6:
.long 0x43340000 # float 180
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_2:
.quad 0x4066800000000000 # double 180
.text
.globl _Z21getAngleBetweenSerialffff
.p2align 4, 0x90
.type _Z21getAngleBetweenSerialffff,@function
_Z21getAngleBetweenSerialffff: # @_Z21getAngleBetweenSerialffff
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps %xmm3, %xmm5
movaps %xmm2, %xmm4
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
mulss %xmm0, %xmm3
movaps %xmm1, %xmm0
mulss %xmm1, %xmm0
addss %xmm3, %xmm0
xorps %xmm3, %xmm3
ucomiss %xmm3, %xmm0
movss %xmm4, 8(%rsp) # 4-byte Spill
movss %xmm5, 20(%rsp) # 4-byte Spill
jb .LBB2_2
# %bb.1:
sqrtss %xmm0, %xmm0
jmp .LBB2_3
.LBB2_2: # %call.sqrt
movss %xmm2, 16(%rsp) # 4-byte Spill
movss %xmm1, 12(%rsp) # 4-byte Spill
callq sqrtf
xorps %xmm3, %xmm3
movss 20(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
.LBB2_3: # %.split
addss .LCPI2_0(%rip), %xmm0
divss %xmm0, %xmm2
movss %xmm2, 16(%rsp) # 4-byte Spill
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
movaps %xmm4, %xmm1
mulss %xmm4, %xmm1
movaps %xmm5, %xmm0
mulss %xmm5, %xmm0
addss %xmm1, %xmm0
ucomiss %xmm3, %xmm0
jb .LBB2_5
# %bb.4:
sqrtss %xmm0, %xmm0
jmp .LBB2_6
.LBB2_5: # %call.sqrt27
callq sqrtf
movss 20(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
.LBB2_6: # %.split.split
addss .LCPI2_0(%rip), %xmm0
divss %xmm0, %xmm4
divss %xmm0, %xmm5
movaps %xmm5, %xmm0
movaps %xmm4, %xmm1
callq atan2f
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
callq atan2f
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
divsd .LCPI2_1(%rip), %xmm0
mulsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss .LCPI2_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
cmpltss .LCPI2_4(%rip), %xmm2
addss %xmm0, %xmm1
andps %xmm2, %xmm1
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
movss .LCPI2_5(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm2, %xmm1
movss .LCPI2_6(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpltss %xmm2, %xmm0
andps %xmm0, %xmm1
andnps %xmm2, %xmm0
orps %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21getAngleBetweenSerialffff, .Lfunc_end2-_Z21getAngleBetweenSerialffff
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002e4b2_00000000-6_vector_calculations.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15getVectorLengthff
.type _Z15getVectorLengthff, @function
_Z15getVectorLengthff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15getVectorLengthff, .-_Z15getVectorLengthff
.globl _Z14getVectorAngleff
.type _Z14getVectorAngleff, @function
_Z14getVectorAngleff:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z14getVectorAngleff, .-_Z14getVectorAngleff
.globl _Z15getAngleBetweenffff
.type _Z15getAngleBetweenffff, @function
_Z15getAngleBetweenffff:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z15getAngleBetweenffff, .-_Z15getAngleBetweenffff
.globl _Z21getVectorLengthSerialff
.type _Z21getVectorLengthSerialff, @function
_Z21getVectorLengthSerialff:
.LFB2030:
.cfi_startproc
endbr64
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
ret
.cfi_endproc
.LFE2030:
.size _Z21getVectorLengthSerialff, .-_Z21getVectorLengthSerialff
.globl _Z20getVectorAngleSerialff
.type _Z20getVectorAngleSerialff, @function
_Z20getVectorAngleSerialff:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movaps %xmm1, %xmm2
movaps %xmm0, %xmm1
movaps %xmm2, %xmm0
call atan2f@PLT
cvtss2sd %xmm0, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _Z20getVectorAngleSerialff, .-_Z20getVectorAngleSerialff
.globl _Z21getAngleBetweenSerialffff
.type _Z21getAngleBetweenSerialffff, @function
_Z21getAngleBetweenSerialffff:
.LFB2032:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps %xmm0, %xmm6
movaps %xmm1, %xmm5
movaps %xmm2, %xmm1
movaps %xmm0, %xmm4
mulss %xmm0, %xmm4
movaps %xmm5, %xmm0
mulss %xmm5, %xmm0
addss %xmm0, %xmm4
sqrtss %xmm4, %xmm4
movss .LC2(%rip), %xmm0
addss %xmm0, %xmm4
divss %xmm4, %xmm6
movss %xmm6, 4(%rsp)
divss %xmm4, %xmm5
movss %xmm5, 8(%rsp)
movaps %xmm2, %xmm4
mulss %xmm2, %xmm4
movaps %xmm3, %xmm2
mulss %xmm3, %xmm2
addss %xmm2, %xmm4
sqrtss %xmm4, %xmm4
addss %xmm0, %xmm4
divss %xmm4, %xmm3
movaps %xmm3, %xmm0
divss %xmm4, %xmm1
call atan2f@PLT
movss %xmm0, 12(%rsp)
movss 4(%rsp), %xmm1
movss 8(%rsp), %xmm0
call atan2f@PLT
movaps %xmm0, %xmm1
movss 12(%rsp), %xmm0
subss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss .LC3(%rip), %xmm1
comiss %xmm0, %xmm1
jbe .L19
addss .LC4(%rip), %xmm0
.L12:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
comiss .LC5(%rip), %xmm0
jbe .L12
subss .LC4(%rip), %xmm0
jmp .L12
.cfi_endproc
.LFE2032:
.size _Z21getAngleBetweenSerialffff, .-_Z21getAngleBetweenSerialffff
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1074340347
.align 8
.LC1:
.long 0
.long 1080459264
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 872415232
.align 4
.LC3:
.long -1020002304
.align 4
.LC4:
.long 1135869952
.align 4
.LC5:
.long 1127481344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_calculations.hip"
.globl _Z21getVectorLengthSerialff # -- Begin function _Z21getVectorLengthSerialff
.p2align 4, 0x90
.type _Z21getVectorLengthSerialff,@function
_Z21getVectorLengthSerialff: # @_Z21getVectorLengthSerialff
.cfi_startproc
# %bb.0:
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
jb .LBB0_2
# %bb.1: # %.split
xorps %xmm0, %xmm0
sqrtss %xmm1, %xmm0
retq
.LBB0_2: # %call.sqrt
movaps %xmm1, %xmm0
jmp sqrtf # TAILCALL
.Lfunc_end0:
.size _Z21getVectorLengthSerialff, .Lfunc_end0-_Z21getVectorLengthSerialff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z20getVectorAngleSerialff
.LCPI1_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_1:
.quad 0x4066800000000000 # double 180
.text
.globl _Z20getVectorAngleSerialff
.p2align 4, 0x90
.type _Z20getVectorAngleSerialff,@function
_Z20getVectorAngleSerialff: # @_Z20getVectorAngleSerialff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movaps %xmm0, %xmm2
movaps %xmm1, %xmm0
movaps %xmm2, %xmm1
callq atan2f
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20getVectorAngleSerialff, .Lfunc_end1-_Z20getVectorAngleSerialff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21getAngleBetweenSerialffff
.LCPI2_0:
.long 0x34000000 # float 1.1920929E-7
.LCPI2_3:
.long 0x43b40000 # float 360
.LCPI2_4:
.long 0xc3340000 # float -180
.LCPI2_5:
.long 0xc3b40000 # float -360
.LCPI2_6:
.long 0x43340000 # float 180
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_2:
.quad 0x4066800000000000 # double 180
.text
.globl _Z21getAngleBetweenSerialffff
.p2align 4, 0x90
.type _Z21getAngleBetweenSerialffff,@function
_Z21getAngleBetweenSerialffff: # @_Z21getAngleBetweenSerialffff
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps %xmm3, %xmm5
movaps %xmm2, %xmm4
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
mulss %xmm0, %xmm3
movaps %xmm1, %xmm0
mulss %xmm1, %xmm0
addss %xmm3, %xmm0
xorps %xmm3, %xmm3
ucomiss %xmm3, %xmm0
movss %xmm4, 8(%rsp) # 4-byte Spill
movss %xmm5, 20(%rsp) # 4-byte Spill
jb .LBB2_2
# %bb.1:
sqrtss %xmm0, %xmm0
jmp .LBB2_3
.LBB2_2: # %call.sqrt
movss %xmm2, 16(%rsp) # 4-byte Spill
movss %xmm1, 12(%rsp) # 4-byte Spill
callq sqrtf
xorps %xmm3, %xmm3
movss 20(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
.LBB2_3: # %.split
addss .LCPI2_0(%rip), %xmm0
divss %xmm0, %xmm2
movss %xmm2, 16(%rsp) # 4-byte Spill
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
movaps %xmm4, %xmm1
mulss %xmm4, %xmm1
movaps %xmm5, %xmm0
mulss %xmm5, %xmm0
addss %xmm1, %xmm0
ucomiss %xmm3, %xmm0
jb .LBB2_5
# %bb.4:
sqrtss %xmm0, %xmm0
jmp .LBB2_6
.LBB2_5: # %call.sqrt27
callq sqrtf
movss 20(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
.LBB2_6: # %.split.split
addss .LCPI2_0(%rip), %xmm0
divss %xmm0, %xmm4
divss %xmm0, %xmm5
movaps %xmm5, %xmm0
movaps %xmm4, %xmm1
callq atan2f
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
callq atan2f
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
divsd .LCPI2_1(%rip), %xmm0
mulsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss .LCPI2_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
cmpltss .LCPI2_4(%rip), %xmm2
addss %xmm0, %xmm1
andps %xmm2, %xmm1
andnps %xmm0, %xmm2
orps %xmm1, %xmm2
movss .LCPI2_5(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm2, %xmm1
movss .LCPI2_6(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpltss %xmm2, %xmm0
andps %xmm0, %xmm1
andnps %xmm2, %xmm0
orps %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21getAngleBetweenSerialffff, .Lfunc_end2-_Z21getAngleBetweenSerialffff
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void create_combined_escape_carry_newline_count_index(char *file, long n, char *escape_carry_index, int *newline_count_index) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long normal_chars_per_thread = max((n+stride-1) / stride, 64L);
long chars_per_thread = ((normal_chars_per_thread + 64 - 1) / 64) * 64;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
// There are essentially two cases:
// - The last character in the previous block is an escape character.
// - The last character in the previous block is not an escape character.
// However, we don't know in advance which one it is, because
// we are not sequential. So, here we'll basically
// calculate the carry of each thread assuming the initial
// carry is 0.
char carry = 0;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
char value = file[i];
if (value == '\\') {
carry = 1 ^ carry;
} else {
carry = 0;
}
if (value == '\n') {
count += 1;
}
}
escape_carry_index[index] = carry;
newline_count_index[index] = count;
} | .file "tmpxft_0013e97e_00000000-6_create_combined_escape_carry_newline_count_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi
.type _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi, @function
_Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z48create_combined_escape_carry_newline_count_indexPclS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi, .-_Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi
.globl _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.type _Z48create_combined_escape_carry_newline_count_indexPclS_Pi, @function
_Z48create_combined_escape_carry_newline_count_indexPclS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z48create_combined_escape_carry_newline_count_indexPclS_Pi, .-_Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z48create_combined_escape_carry_newline_count_indexPclS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z48create_combined_escape_carry_newline_count_indexPclS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void create_combined_escape_carry_newline_count_index(char *file, long n, char *escape_carry_index, int *newline_count_index) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long normal_chars_per_thread = max((n+stride-1) / stride, 64L);
long chars_per_thread = ((normal_chars_per_thread + 64 - 1) / 64) * 64;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
// There are essentially two cases:
// - The last character in the previous block is an escape character.
// - The last character in the previous block is not an escape character.
// However, we don't know in advance which one it is, because
// we are not sequential. So, here we'll basically
// calculate the carry of each thread assuming the initial
// carry is 0.
char carry = 0;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
char value = file[i];
if (value == '\\') {
carry = 1 ^ carry;
} else {
carry = 0;
}
if (value == '\n') {
count += 1;
}
}
escape_carry_index[index] = carry;
newline_count_index[index] = count;
} | #include <hip/hip_runtime.h>
__global__ void create_combined_escape_carry_newline_count_index(char *file, long n, char *escape_carry_index, int *newline_count_index) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long normal_chars_per_thread = max((n+stride-1) / stride, 64L);
long chars_per_thread = ((normal_chars_per_thread + 64 - 1) / 64) * 64;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
// There are essentially two cases:
// - The last character in the previous block is an escape character.
// - The last character in the previous block is not an escape character.
// However, we don't know in advance which one it is, because
// we are not sequential. So, here we'll basically
// calculate the carry of each thread assuming the initial
// carry is 0.
char carry = 0;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
char value = file[i];
if (value == '\\') {
carry = 1 ^ carry;
} else {
carry = 0;
}
if (value == '\n') {
count += 1;
}
}
escape_carry_index[index] = carry;
newline_count_index[index] = count;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void create_combined_escape_carry_newline_count_index(char *file, long n, char *escape_carry_index, int *newline_count_index) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long normal_chars_per_thread = max((n+stride-1) / stride, 64L);
long chars_per_thread = ((normal_chars_per_thread + 64 - 1) / 64) * 64;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
// There are essentially two cases:
// - The last character in the previous block is an escape character.
// - The last character in the previous block is not an escape character.
// However, we don't know in advance which one it is, because
// we are not sequential. So, here we'll basically
// calculate the carry of each thread assuming the initial
// carry is 0.
char carry = 0;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
char value = file[i];
if (value == '\\') {
carry = 1 ^ carry;
} else {
carry = 0;
}
if (value == '\n') {
count += 1;
}
}
escape_carry_index[index] = carry;
newline_count_index[index] = count;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.globl _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.p2align 8
.type _Z48create_combined_escape_carry_newline_count_indexPclS_Pi,@function
_Z48create_combined_escape_carry_newline_count_indexPclS_Pi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s14
s_ashr_i32 s5, s4, 31
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
s_add_u32 s6, s6, -1
s_addc_u32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b64 s[8:9], s[6:7], s[4:5]
s_mov_b32 s8, 0
s_cmp_lg_u64 s[8:9], 0
s_cbranch_scc0 .LBB0_8
s_add_u32 s12, s4, s5
s_mov_b32 s10, s5
s_mov_b32 s11, s5
s_addc_u32 s13, s5, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[12:13], s[12:13], s[10:11]
v_cvt_f32_u32_e32 v1, s12
v_cvt_f32_u32_e32 v2, s13
s_sub_u32 s16, 0, s12
s_subb_u32 s17, 0, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0x4f800000, v1
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s5, v2
v_readfirstlane_b32 s9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s18, s16, s5
s_mul_hi_u32 s20, s16, s9
s_mul_i32 s19, s17, s9
s_add_i32 s18, s20, s18
s_mul_i32 s21, s16, s9
s_add_i32 s18, s18, s19
s_mul_hi_u32 s20, s9, s21
s_mul_hi_u32 s22, s5, s21
s_mul_i32 s19, s5, s21
s_mul_hi_u32 s21, s9, s18
s_mul_i32 s9, s9, s18
s_mul_hi_u32 s23, s5, s18
s_add_u32 s9, s20, s9
s_addc_u32 s20, 0, s21
s_add_u32 s9, s9, s19
s_mul_i32 s18, s5, s18
s_addc_u32 s9, s20, s22
s_addc_u32 s19, s23, 0
s_add_u32 s9, s9, s18
s_addc_u32 s18, 0, s19
v_add_co_u32 v1, s9, v1, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s9, 0
s_addc_u32 s5, s5, s18
v_readfirstlane_b32 s9, v1
s_mul_i32 s18, s16, s5
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s19, s16, s9
s_mul_i32 s17, s17, s9
s_add_i32 s18, s19, s18
s_mul_i32 s16, s16, s9
s_add_i32 s18, s18, s17
s_mul_hi_u32 s19, s5, s16
s_mul_i32 s20, s5, s16
s_mul_hi_u32 s16, s9, s16
s_mul_hi_u32 s21, s9, s18
s_mul_i32 s9, s9, s18
s_mul_hi_u32 s17, s5, s18
s_add_u32 s9, s16, s9
s_addc_u32 s16, 0, s21
s_add_u32 s9, s9, s20
s_mul_i32 s18, s5, s18
s_addc_u32 s9, s16, s19
s_addc_u32 s16, s17, 0
s_add_u32 s9, s9, s18
s_addc_u32 s16, 0, s16
v_add_co_u32 v1, s9, v1, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s9, 0
s_addc_u32 s5, s5, s16
s_ashr_i32 s16, s7, 31
s_add_u32 s18, s6, s16
s_addc_u32 s19, s7, s16
v_readfirstlane_b32 s7, v1
s_mov_b32 s17, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[18:19], s[18:19], s[16:17]
s_mul_i32 s20, s18, s5
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s21, s18, s7
s_mul_hi_u32 s9, s18, s5
s_mul_hi_u32 s23, s19, s7
s_mul_i32 s7, s19, s7
s_add_u32 s20, s21, s20
s_addc_u32 s9, 0, s9
s_mul_hi_u32 s22, s19, s5
s_add_u32 s7, s20, s7
s_mul_i32 s5, s19, s5
s_addc_u32 s7, s9, s23
s_addc_u32 s9, s22, 0
s_add_u32 s5, s7, s5
s_addc_u32 s7, 0, s9
s_mul_i32 s22, s12, s5
s_mul_hi_u32 s9, s12, s5
s_mul_i32 s21, s12, s7
v_sub_co_u32 v1, s18, s18, s22
s_mul_i32 s20, s13, s5
s_add_i32 s9, s9, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s9, s9, s20
v_sub_co_u32 v2, s21, v1, s12
s_sub_i32 s20, s19, s9
s_cmp_lg_u32 s18, 0
s_subb_u32 s20, s20, s13
s_cmp_lg_u32 s21, 0
v_readfirstlane_b32 s21, v2
s_subb_u32 s20, s20, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_ge_u32 s20, s13
s_cselect_b32 s22, -1, 0
s_cmp_ge_u32 s21, s12
s_cselect_b32 s21, -1, 0
s_cmp_eq_u32 s20, s13
s_cselect_b32 s20, s21, s22
s_add_u32 s21, s5, 1
s_addc_u32 s22, s7, 0
s_add_u32 s23, s5, 2
s_addc_u32 s24, s7, 0
s_cmp_lg_u32 s20, 0
s_cselect_b32 s20, s23, s21
s_cselect_b32 s21, s24, s22
s_cmp_lg_u32 s18, 0
v_readfirstlane_b32 s18, v1
s_subb_u32 s9, s19, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_ge_u32 s9, s13
s_cselect_b32 s19, -1, 0
s_cmp_ge_u32 s18, s12
s_cselect_b32 s12, -1, 0
s_cmp_eq_u32 s9, s13
s_cselect_b32 s9, s12, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s9, 0
s_cselect_b32 s13, s21, s7
s_cselect_b32 s12, s20, s5
s_xor_b64 s[10:11], s[16:17], s[10:11]
s_xor_b64 s[12:13], s[12:13], s[10:11]
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_u32 s10, s12, s10
s_subb_u32 s11, s13, s11
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_3
.LBB0_2:
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s7, 0, s4
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v1
s_mul_i32 s7, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s5, s7
s_add_i32 s5, s5, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s6, s5
s_mul_i32 s7, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s6, s6, s7
s_add_i32 s7, s5, 1
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s5, s7, s5
s_cselect_b32 s6, s8, s6
s_add_i32 s7, s5, 1
s_cmp_ge_u32 s6, s4
s_cselect_b32 s10, s7, s5
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cmp_gt_i64_e64 s4, s[10:11], 64
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
s_mov_b32 s6, 0
v_mov_b32_e32 v7, 0
s_and_b32 s4, s4, exec_lo
s_cselect_b32 s5, s10, 64
s_cselect_b32 s4, s11, 0
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
s_add_u32 s5, s5, 63
s_addc_u32 s4, s4, 0
s_and_not1_b32 s5, s5, 63
s_bitset0_b32 s4, 31
v_mul_lo_u32 v0, s5, v2
v_mad_u64_u32 v[3:4], null, s5, v1, 0
v_mul_lo_u32 v5, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v4, v4, v0, v5
v_add_co_u32 v5, vcc_lo, v3, s5
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s4, v4, vcc_lo
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[5:6]
v_cndmask_b32_e32 v6, s3, v6, vcc_lo
v_cndmask_b32_e32 v5, s2, v5, vcc_lo
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i64_e64 v[3:4], v[5:6]
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v0, 0
.p2align 6
.LBB0_5:
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 1
v_xor_b32_e32 v7, 1, v7
global_load_u8 v8, v[8:9], off
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_ge_i64_e32 vcc_lo, v[3:4], v[5:6]
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s2, 0x5c, v8
v_cndmask_b32_e64 v7, 0, v7, s2
v_cmp_eq_u16_e64 s2, 10, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v0, s2, 0, v0, s2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b128 s[0:3], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b8 v[1:2], v7, off
global_store_b32 v[3:4], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_8:
s_branch .LBB0_2
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z48create_combined_escape_carry_newline_count_indexPclS_Pi, .Lfunc_end0-_Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z48create_combined_escape_carry_newline_count_indexPclS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void create_combined_escape_carry_newline_count_index(char *file, long n, char *escape_carry_index, int *newline_count_index) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long normal_chars_per_thread = max((n+stride-1) / stride, 64L);
long chars_per_thread = ((normal_chars_per_thread + 64 - 1) / 64) * 64;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
// There are essentially two cases:
// - The last character in the previous block is an escape character.
// - The last character in the previous block is not an escape character.
// However, we don't know in advance which one it is, because
// we are not sequential. So, here we'll basically
// calculate the carry of each thread assuming the initial
// carry is 0.
char carry = 0;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
char value = file[i];
if (value == '\\') {
carry = 1 ^ carry;
} else {
carry = 0;
}
if (value == '\n') {
count += 1;
}
}
escape_carry_index[index] = carry;
newline_count_index[index] = count;
} | .text
.file "create_combined_escape_carry_newline_count_index.hip"
.globl _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi # -- Begin function _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.p2align 4, 0x90
.type _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi,@function
_Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi: # @_Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z48create_combined_escape_carry_newline_count_indexPclS_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi, .Lfunc_end0-_Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z48create_combined_escape_carry_newline_count_indexPclS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z48create_combined_escape_carry_newline_count_indexPclS_Pi,@object # @_Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.section .rodata,"a",@progbits
.globl _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.p2align 3, 0x0
_Z48create_combined_escape_carry_newline_count_indexPclS_Pi:
.quad _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.size _Z48create_combined_escape_carry_newline_count_indexPclS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z48create_combined_escape_carry_newline_count_indexPclS_Pi"
.size .L__unnamed_1, 60
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013e97e_00000000-6_create_combined_escape_carry_newline_count_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi
.type _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi, @function
_Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z48create_combined_escape_carry_newline_count_indexPclS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi, .-_Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi
.globl _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.type _Z48create_combined_escape_carry_newline_count_indexPclS_Pi, @function
_Z48create_combined_escape_carry_newline_count_indexPclS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z73__device_stub__Z48create_combined_escape_carry_newline_count_indexPclS_PiPclS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z48create_combined_escape_carry_newline_count_indexPclS_Pi, .-_Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z48create_combined_escape_carry_newline_count_indexPclS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z48create_combined_escape_carry_newline_count_indexPclS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "create_combined_escape_carry_newline_count_index.hip"
.globl _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi # -- Begin function _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.p2align 4, 0x90
.type _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi,@function
_Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi: # @_Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z48create_combined_escape_carry_newline_count_indexPclS_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi, .Lfunc_end0-_Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z48create_combined_escape_carry_newline_count_indexPclS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z48create_combined_escape_carry_newline_count_indexPclS_Pi,@object # @_Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.section .rodata,"a",@progbits
.globl _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.p2align 3, 0x0
_Z48create_combined_escape_carry_newline_count_indexPclS_Pi:
.quad _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.size _Z48create_combined_escape_carry_newline_count_indexPclS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z48create_combined_escape_carry_newline_count_indexPclS_Pi"
.size .L__unnamed_1, 60
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z63__device_stub__create_combined_escape_carry_newline_count_indexPclS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z48create_combined_escape_carry_newline_count_indexPclS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel(float *output, float *input, float *target, int nframe, int dim, int sizeaverage, float *positiveWeight)
{
__shared__ float buffer[MULTIMARGIN_THREADS];
int k = blockIdx.x;
float *input_k = input + k*dim;
float *output_k = output + k;
int target_k = ((int)target[k])-1;
int i_start = threadIdx.x;
int i_end = dim;
int i_step = blockDim.x;
buffer[threadIdx.x] = 0;
for(int i = i_start; i < i_end; i += i_step)
{
float y = (i==target_k) ? 1.0 : -1.0;
float z = 1 - input_k[i]*y;
if(z > 0){
float weight = (i==target_k) ? positiveWeight[i] : 1.0;
buffer[threadIdx.x] += z*weight;
}
}
__syncthreads();
// reduce
if (threadIdx.x == 0)
{
float sum = 0;
for (int i=0; i<blockDim.x; i++)
sum += buffer[i];
if(sizeaverage)
*output_k = sum/dim;
else
*output_k = sum;
}
} | .file "tmpxft_0012fc8c_00000000-6_cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_
.type _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_, @function
_Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_, .-_Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_
.globl _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.type _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, @function
_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z82__device_stub__Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_PfS_S_iiiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_, .-_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z53cunn_OneVsAllMultiMarginCriterion_updateOutput_kernelPfS_S_iiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel(float *output, float *input, float *target, int nframe, int dim, int sizeaverage, float *positiveWeight)
{
__shared__ float buffer[MULTIMARGIN_THREADS];
int k = blockIdx.x;
float *input_k = input + k*dim;
float *output_k = output + k;
int target_k = ((int)target[k])-1;
int i_start = threadIdx.x;
int i_end = dim;
int i_step = blockDim.x;
buffer[threadIdx.x] = 0;
for(int i = i_start; i < i_end; i += i_step)
{
float y = (i==target_k) ? 1.0 : -1.0;
float z = 1 - input_k[i]*y;
if(z > 0){
float weight = (i==target_k) ? positiveWeight[i] : 1.0;
buffer[threadIdx.x] += z*weight;
}
}
__syncthreads();
// reduce
if (threadIdx.x == 0)
{
float sum = 0;
for (int i=0; i<blockDim.x; i++)
sum += buffer[i];
if(sizeaverage)
*output_k = sum/dim;
else
*output_k = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunn_OneVsAllMultiMarginCriterion_updateOutput_kernel(float *output, float *input, float *target, int nframe, int dim, int sizeaverage, float *positiveWeight)
{
__shared__ float buffer[MULTIMARGIN_THREADS];
int k = blockIdx.x;
float *input_k = input + k*dim;
float *output_k = output + k;
int target_k = ((int)target[k])-1;
int i_start = threadIdx.x;
int i_end = dim;
int i_step = blockDim.x;
buffer[threadIdx.x] = 0;
for(int i = i_start; i < i_end; i += i_step)
{
float y = (i==target_k) ? 1.0 : -1.0;
float z = 1 - input_k[i]*y;
if(z > 0){
float weight = (i==target_k) ? positiveWeight[i] : 1.0;
buffer[threadIdx.x] += z*weight;
}
}
__syncthreads();
// reduce
if (threadIdx.x == 0)
{
float sum = 0;
for (int i=0; i<blockDim.x; i++)
sum += buffer[i];
if(sizeaverage)
*output_k = sum/dim;
else
*output_k = sum;
}
} |
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