system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <memory>
#include <cuda_runtime.h>
/** 设备属性
* 了解 GPU 硬件设备的各项属性，有利于高效的利用 GPU 资源。
* 针对特定的硬件设备 GPU，为应用程序开发分配合理的资源。
* 具体使用的时候，需要查 CUDA 编程手册以及对应 GPU 硬件资源信息。
*
* D:\Nvidia\Samples\1_Utilities\deviceQuery\deviceQuery.cpp
*/
int main(int argc, char **argv)
{
int device_count = 0; // 可用设备数量
int device; // 设备名称编号
int driver_version; // CUDA 驱动版本号
int runtime_version; // 运行时引擎版本
// 通过查询 cudaDeviceProp 结构体来找到每个设备的相关信息，该结构体返回所有设备的属性。
// 如果有多个可用设备，可使用 for 循环遍历所有设备属性。
// get count of the avaiable CUDA hardware device in system.
cudaGetDeviceCount(&device_count);
// This function returns count of number of CUDA enable devices and 0 if there are no CUDA capable devices.
if (device_count == 0)
{
// printf("There are no available devices that support CUDA.\n");
std::cout << "There are no available devices that support CUDA.\n";
}
else
{
// printf("Detected %d CUDA Capable devices.\n", device_count);
std::cout << "Detected " << device_count << " CUDA Capable devices.\n";
}
/**通用设备信息
* cudaDeviceProp 结构体提供可以用来识别设备以及确认使用的版本信息的属性，name属性以字符串形式返回设备名称。
* cudaDriverGetVersion 获取设备使用的 CUDA Driver。
* cudaRuntimeGetVersion 获取设备运行时引擎的版本。
* clockRate属性获取 GPU 的时钟速率。
* multiProcessorCount属性用于判断设备上流多处理器的个数。
*/
// 获取设备名称编号
cudaGetDevice(&device);
// printf("ID of device: %d\n", device);
std::cout << "ID of device: " << device << std::endl;
// 获取设备结构体信息
cudaDeviceProp device_property;
cudaGetDeviceProperties(&device_property, device);
// printf("\nDevice %s: \n", device_property.name);
// device_property.name 获取 GPU 型号
std::cout << "The type of hardware GPU is: " << device_property.name << std::endl;
// 获取 CUDA 驱动版本号
cudaDriverGetVersion(&driver_version);
std::cout << "CUDA Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// 获取运行时引擎版本
cudaRuntimeGetVersion(&runtime_version);
std::cout << "CUDA Runtime Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// GPU 显存容量
// printf("Total amount of global memory: %.0f MBytes (%llu bytes)\n", (float)device_property.totalGlobalMem / 1048576.0f,
// (unsigned long long)device_property.totalGlobalMem);
std::cout << "Total amount of global memory: " << (float)device_property.totalGlobalMem / 1048576.0f << " MBytes" << std::endl;
// 具有最多流处理器的设备,如果有多个设备
printf(" (%2d) mutilprocessors\n", device_property.multiProcessorCount);
// std::cout << device_property.mutilProcessorCount << "mutilprocessors" << std::endl;
// GPU 时钟速率，以 KHz 为单位进行返回
// printf("GPU max clock rate: %.0f MHz (%.2f GHz)\n", device_property.clockRate * 1e-3f, device_property.clockRate * 1e-6f);
std::cout << "GPU max clock rate: " << device_property.clockRate * 1e-6f << " GHz" << std::endl;
// 显存频率
// printf("Memory clock rate: %.0f MHz\n", device_property.memoryClockRate * 1e-3f);
std::cout << "Memory clock rate: " << device_property.memoryClockRate * 1e-3f << " MHz" << std::endl;
// 显存位宽
// printf("Memory Bus Width: %d-bit\n", device_property.memoryBusWidth);
std::cout << "Memory Bus Width: " << device_property.memoryBusWidth << "-bit" << std::endl;
// L2 缓存
if (device_property.l2CacheSize)
{
// printf("L2 Cache size: %d bytes\n", device_property.l2CacheSize);
std::cout << "L2 Cache size: " << device_property.l2CacheSize << " bytes" << std::endl;
}
// 常量内存
// printf("Toal amount of constant memory: %lu bytes\n", device_property.totalConstMem);
std::cout << "Toal amount of constant memory: " << device_property.totalConstMem << " bytes" << std::endl;
// 共享内存
// printf("Toal amount of shared memory per block: %lu bytes\n", device_property.sharedMemPerBlock);
std::cout << "Toal amount of shared memory per block: " << device_property.sharedMemPerBlock << " bytes" << std::endl;
// 每一个块可用寄存器总数
// printf("Toal amount of registers available per block: %d\n", device_property.regsPerBlock);
std::cout << "Toal amount of registers available per block: " << device_property.regsPerBlock << std::endl;
// 网格grid 块block 线程thread 可以时多维的，每一个维度中可用并行启动多少个线程和块
// 这对于内核参数的配置十分重要
// printf("Maximum number of threads per multiprocessor: %d\n", device_property.maxThreadsPerMutilProcessor);
// std::cout << "Maximum number of threads per multiprocessor: " << device_property.maxThreadsPerMutilProcessor << std::endl;
// printf("Maximum number of threads per block: %d\n", device_property.maxThreadsPerBlock);
std::cout << "Maximum number of threads per block: " << device_property.maxThreadsPerBlock << std::endl;
// printf("Max dimension size of a thread block (x, y, z): (%d, %d, %d)\n",
// device_property.maxThreadsDim[0],
// device_property.maxThreadsDim[1],
// device_property.maxThreadsDim[2]);
std::cout << "Max dimension size of a thread block (x, y, z): " << "(" <<
device_property.maxThreadsDim[0] << "," <<
device_property.maxThreadsDim[1] << "," <<
device_property.maxThreadsDim[2] << ")" << std::endl;
// printf("Max dimension size of a grid size (x, y, z): (%d, %d, %d)\n",
// device_property.maxGridSize[0],
// device_property.maxGridSize[1],
// device_property.maxGridSize[2]);
std::cout << "Max dimension size of a grid size (x, y, z): " << "(" <<
device_property.maxGridSize[0] << "," <<
device_property.maxGridSize[1] << "," <<
device_property.maxGridSize[2] << ")" << std::endl;
// 查看设备是否支持双精度浮点操作，并为应用程序设置该设备
memset(&device_property, 0, sizeof(cudaDeviceProp));
// if major > 1 and minor > 3, then the device supports double precision.
device_property.major = 1;
device_property.minor = 3;
// 选择特定属性的设备
cudaChooseDevice(&device, &device_property);
// printf("ID of device which supports double precision is: %d\n", device);
std::cout << "ID of device which supports double precision is: " << device << std::endl;
// 设置设备为应用程序所用设备
cudaSetDevice(device);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <memory>
#include <cuda_runtime.h>
/** 设备属性
* 了解 GPU 硬件设备的各项属性，有利于高效的利用 GPU 资源。
* 针对特定的硬件设备 GPU，为应用程序开发分配合理的资源。
* 具体使用的时候，需要查 CUDA 编程手册以及对应 GPU 硬件资源信息。
*
* D:\Nvidia\Samples\1_Utilities\deviceQuery\deviceQuery.cpp
*/
int main(int argc, char **argv)
{
int device_count = 0; // 可用设备数量
int device; // 设备名称编号
int driver_version; // CUDA 驱动版本号
int runtime_version; // 运行时引擎版本
// 通过查询 cudaDeviceProp 结构体来找到每个设备的相关信息，该结构体返回所有设备的属性。
// 如果有多个可用设备，可使用 for 循环遍历所有设备属性。
// get count of the avaiable CUDA hardware device in system.
cudaGetDeviceCount(&device_count);
// This function returns count of number of CUDA enable devices and 0 if there are no CUDA capable devices.
if (device_count == 0)
{
// printf("There are no available devices that support CUDA.\n");
std::cout << "There are no available devices that support CUDA.\n";
}
else
{
// printf("Detected %d CUDA Capable devices.\n", device_count);
std::cout << "Detected " << device_count << " CUDA Capable devices.\n";
}
/**通用设备信息
* cudaDeviceProp 结构体提供可以用来识别设备以及确认使用的版本信息的属性，name属性以字符串形式返回设备名称。
* cudaDriverGetVersion 获取设备使用的 CUDA Driver。
* cudaRuntimeGetVersion 获取设备运行时引擎的版本。
* clockRate属性获取 GPU 的时钟速率。
* multiProcessorCount属性用于判断设备上流多处理器的个数。
*/
// 获取设备名称编号
cudaGetDevice(&device);
// printf("ID of device: %d\n", device);
std::cout << "ID of device: " << device << std::endl;
// 获取设备结构体信息
cudaDeviceProp device_property;
cudaGetDeviceProperties(&device_property, device);
// printf("\nDevice %s: \n", device_property.name);
// device_property.name 获取 GPU 型号
std::cout << "The type of hardware GPU is: " << device_property.name << std::endl;
// 获取 CUDA 驱动版本号
cudaDriverGetVersion(&driver_version);
std::cout << "CUDA Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// 获取运行时引擎版本
cudaRuntimeGetVersion(&runtime_version);
std::cout << "CUDA Runtime Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// GPU 显存容量
// printf("Total amount of global memory: %.0f MBytes (%llu bytes)\n", (float)device_property.totalGlobalMem / 1048576.0f,
// (unsigned long long)device_property.totalGlobalMem);
std::cout << "Total amount of global memory: " << (float)device_property.totalGlobalMem / 1048576.0f << " MBytes" << std::endl;
// 具有最多流处理器的设备,如果有多个设备
printf(" (%2d) mutilprocessors\n", device_property.multiProcessorCount);
// std::cout << device_property.mutilProcessorCount << "mutilprocessors" << std::endl;
// GPU 时钟速率，以 KHz 为单位进行返回
// printf("GPU max clock rate: %.0f MHz (%.2f GHz)\n", device_property.clockRate * 1e-3f, device_property.clockRate * 1e-6f);
std::cout << "GPU max clock rate: " << device_property.clockRate * 1e-6f << " GHz" << std::endl;
// 显存频率
// printf("Memory clock rate: %.0f MHz\n", device_property.memoryClockRate * 1e-3f);
std::cout << "Memory clock rate: " << device_property.memoryClockRate * 1e-3f << " MHz" << std::endl;
// 显存位宽
// printf("Memory Bus Width: %d-bit\n", device_property.memoryBusWidth);
std::cout << "Memory Bus Width: " << device_property.memoryBusWidth << "-bit" << std::endl;
// L2 缓存
if (device_property.l2CacheSize)
{
// printf("L2 Cache size: %d bytes\n", device_property.l2CacheSize);
std::cout << "L2 Cache size: " << device_property.l2CacheSize << " bytes" << std::endl;
}
// 常量内存
// printf("Toal amount of constant memory: %lu bytes\n", device_property.totalConstMem);
std::cout << "Toal amount of constant memory: " << device_property.totalConstMem << " bytes" << std::endl;
// 共享内存
// printf("Toal amount of shared memory per block: %lu bytes\n", device_property.sharedMemPerBlock);
std::cout << "Toal amount of shared memory per block: " << device_property.sharedMemPerBlock << " bytes" << std::endl;
// 每一个块可用寄存器总数
// printf("Toal amount of registers available per block: %d\n", device_property.regsPerBlock);
std::cout << "Toal amount of registers available per block: " << device_property.regsPerBlock << std::endl;
// 网格grid 块block 线程thread 可以时多维的，每一个维度中可用并行启动多少个线程和块
// 这对于内核参数的配置十分重要
// printf("Maximum number of threads per multiprocessor: %d\n", device_property.maxThreadsPerMutilProcessor);
// std::cout << "Maximum number of threads per multiprocessor: " << device_property.maxThreadsPerMutilProcessor << std::endl;
// printf("Maximum number of threads per block: %d\n", device_property.maxThreadsPerBlock);
std::cout << "Maximum number of threads per block: " << device_property.maxThreadsPerBlock << std::endl;
// printf("Max dimension size of a thread block (x, y, z): (%d, %d, %d)\n",
// device_property.maxThreadsDim[0],
// device_property.maxThreadsDim[1],
// device_property.maxThreadsDim[2]);
std::cout << "Max dimension size of a thread block (x, y, z): " << "(" <<
device_property.maxThreadsDim[0] << "," <<
device_property.maxThreadsDim[1] << "," <<
device_property.maxThreadsDim[2] << ")" << std::endl;
// printf("Max dimension size of a grid size (x, y, z): (%d, %d, %d)\n",
// device_property.maxGridSize[0],
// device_property.maxGridSize[1],
// device_property.maxGridSize[2]);
std::cout << "Max dimension size of a grid size (x, y, z): " << "(" <<
device_property.maxGridSize[0] << "," <<
device_property.maxGridSize[1] << "," <<
device_property.maxGridSize[2] << ")" << std::endl;
// 查看设备是否支持双精度浮点操作，并为应用程序设置该设备
memset(&device_property, 0, sizeof(cudaDeviceProp));
// if major > 1 and minor > 3, then the device supports double precision.
device_property.major = 1;
device_property.minor = 3;
// 选择特定属性的设备
cudaChooseDevice(&device, &device_property);
// printf("ID of device which supports double precision is: %d\n", device);
std::cout << "ID of device which supports double precision is: " << device << std::endl;
// 设置设备为应用程序所用设备
cudaSetDevice(device);
return 0;
} | .file "tmpxft_00016514_00000000-6_2_04_device_information.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "There are no available devices that support CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Detected "
.LC2:
.string " CUDA Capable devices.\n"
.LC3:
.string "ID of device: "
.LC4:
.string "The type of hardware GPU is: "
.LC5:
.string "CUDA Driver Version is: CUDA "
.LC6:
.string "."
.section .rodata.str1.8
.align 8
.LC7:
.string "CUDA Runtime Driver Version is: CUDA "
.align 8
.LC8:
.string "Total amount of global memory: "
.section .rodata.str1.1
.LC10:
.string " MBytes"
.LC11:
.string " (%2d) mutilprocessors\n"
.LC12:
.string "GPU max clock rate: "
.LC14:
.string " GHz"
.LC15:
.string "Memory clock rate: "
.LC17:
.string " MHz"
.LC18:
.string "Memory Bus Width: "
.LC19:
.string "-bit"
.LC20:
.string "L2 Cache size: "
.LC21:
.string " bytes"
.section .rodata.str1.8
.align 8
.LC22:
.string "Toal amount of constant memory: "
.align 8
.LC23:
.string "Toal amount of shared memory per block: "
.align 8
.LC24:
.string "Toal amount of registers available per block: "
.align 8
.LC25:
.string "Maximum number of threads per block: "
.align 8
.LC26:
.string "Max dimension size of a thread block (x, y, z): "
.section .rodata.str1.1
.LC27:
.string "("
.LC28:
.string ","
.LC29:
.string ")"
.section .rodata.str1.8
.align 8
.LC30:
.string "Max dimension size of a grid size (x, y, z): "
.align 8
.LC31:
.string "ID of device which supports double precision is: "
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movq %rsp, %rdi
call cudaGetDeviceCount@PLT
cmpl $0, (%rsp)
jne .L4
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L5:
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rbp
movl 4(%rsp), %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %edx
movslq %edx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %edx
movslq %edx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rdx
testq %rdx, %rdx
js .L6
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L7:
mulss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 404(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LC16(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 628(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 632(%rsp)
jne .L11
.L8:
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 368(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 312(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC24(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 320(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC25(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 336(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC26(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC27(%rip), %r13
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 340(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC28(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 344(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 348(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC29(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC30(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 352(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 356(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 360(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rsi
movl $129, %ecx
movl $0, %eax
movq %rsi, %rdi
rep stosq
movl $1, 376(%rsp)
movl $3, 380(%rsp)
leaq 4(%rsp), %rdi
call cudaChooseDevice@PLT
leaq .LC31(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 4(%rsp), %edi
call cudaSetDevice@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.L6:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L7
.L11:
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 632(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L8
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 897581056
.align 4
.LC13:
.long 897988541
.align 4
.LC16:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <memory>
#include <cuda_runtime.h>
/** 设备属性
* 了解 GPU 硬件设备的各项属性，有利于高效的利用 GPU 资源。
* 针对特定的硬件设备 GPU，为应用程序开发分配合理的资源。
* 具体使用的时候，需要查 CUDA 编程手册以及对应 GPU 硬件资源信息。
*
* D:\Nvidia\Samples\1_Utilities\deviceQuery\deviceQuery.cpp
*/
int main(int argc, char **argv)
{
int device_count = 0; // 可用设备数量
int device; // 设备名称编号
int driver_version; // CUDA 驱动版本号
int runtime_version; // 运行时引擎版本
// 通过查询 cudaDeviceProp 结构体来找到每个设备的相关信息，该结构体返回所有设备的属性。
// 如果有多个可用设备，可使用 for 循环遍历所有设备属性。
// get count of the avaiable CUDA hardware device in system.
cudaGetDeviceCount(&device_count);
// This function returns count of number of CUDA enable devices and 0 if there are no CUDA capable devices.
if (device_count == 0)
{
// printf("There are no available devices that support CUDA.\n");
std::cout << "There are no available devices that support CUDA.\n";
}
else
{
// printf("Detected %d CUDA Capable devices.\n", device_count);
std::cout << "Detected " << device_count << " CUDA Capable devices.\n";
}
/**通用设备信息
* cudaDeviceProp 结构体提供可以用来识别设备以及确认使用的版本信息的属性，name属性以字符串形式返回设备名称。
* cudaDriverGetVersion 获取设备使用的 CUDA Driver。
* cudaRuntimeGetVersion 获取设备运行时引擎的版本。
* clockRate属性获取 GPU 的时钟速率。
* multiProcessorCount属性用于判断设备上流多处理器的个数。
*/
// 获取设备名称编号
cudaGetDevice(&device);
// printf("ID of device: %d\n", device);
std::cout << "ID of device: " << device << std::endl;
// 获取设备结构体信息
cudaDeviceProp device_property;
cudaGetDeviceProperties(&device_property, device);
// printf("\nDevice %s: \n", device_property.name);
// device_property.name 获取 GPU 型号
std::cout << "The type of hardware GPU is: " << device_property.name << std::endl;
// 获取 CUDA 驱动版本号
cudaDriverGetVersion(&driver_version);
std::cout << "CUDA Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// 获取运行时引擎版本
cudaRuntimeGetVersion(&runtime_version);
std::cout << "CUDA Runtime Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// GPU 显存容量
// printf("Total amount of global memory: %.0f MBytes (%llu bytes)\n", (float)device_property.totalGlobalMem / 1048576.0f,
// (unsigned long long)device_property.totalGlobalMem);
std::cout << "Total amount of global memory: " << (float)device_property.totalGlobalMem / 1048576.0f << " MBytes" << std::endl;
// 具有最多流处理器的设备,如果有多个设备
printf(" (%2d) mutilprocessors\n", device_property.multiProcessorCount);
// std::cout << device_property.mutilProcessorCount << "mutilprocessors" << std::endl;
// GPU 时钟速率，以 KHz 为单位进行返回
// printf("GPU max clock rate: %.0f MHz (%.2f GHz)\n", device_property.clockRate * 1e-3f, device_property.clockRate * 1e-6f);
std::cout << "GPU max clock rate: " << device_property.clockRate * 1e-6f << " GHz" << std::endl;
// 显存频率
// printf("Memory clock rate: %.0f MHz\n", device_property.memoryClockRate * 1e-3f);
std::cout << "Memory clock rate: " << device_property.memoryClockRate * 1e-3f << " MHz" << std::endl;
// 显存位宽
// printf("Memory Bus Width: %d-bit\n", device_property.memoryBusWidth);
std::cout << "Memory Bus Width: " << device_property.memoryBusWidth << "-bit" << std::endl;
// L2 缓存
if (device_property.l2CacheSize)
{
// printf("L2 Cache size: %d bytes\n", device_property.l2CacheSize);
std::cout << "L2 Cache size: " << device_property.l2CacheSize << " bytes" << std::endl;
}
// 常量内存
// printf("Toal amount of constant memory: %lu bytes\n", device_property.totalConstMem);
std::cout << "Toal amount of constant memory: " << device_property.totalConstMem << " bytes" << std::endl;
// 共享内存
// printf("Toal amount of shared memory per block: %lu bytes\n", device_property.sharedMemPerBlock);
std::cout << "Toal amount of shared memory per block: " << device_property.sharedMemPerBlock << " bytes" << std::endl;
// 每一个块可用寄存器总数
// printf("Toal amount of registers available per block: %d\n", device_property.regsPerBlock);
std::cout << "Toal amount of registers available per block: " << device_property.regsPerBlock << std::endl;
// 网格grid 块block 线程thread 可以时多维的，每一个维度中可用并行启动多少个线程和块
// 这对于内核参数的配置十分重要
// printf("Maximum number of threads per multiprocessor: %d\n", device_property.maxThreadsPerMutilProcessor);
// std::cout << "Maximum number of threads per multiprocessor: " << device_property.maxThreadsPerMutilProcessor << std::endl;
// printf("Maximum number of threads per block: %d\n", device_property.maxThreadsPerBlock);
std::cout << "Maximum number of threads per block: " << device_property.maxThreadsPerBlock << std::endl;
// printf("Max dimension size of a thread block (x, y, z): (%d, %d, %d)\n",
// device_property.maxThreadsDim[0],
// device_property.maxThreadsDim[1],
// device_property.maxThreadsDim[2]);
std::cout << "Max dimension size of a thread block (x, y, z): " << "(" <<
device_property.maxThreadsDim[0] << "," <<
device_property.maxThreadsDim[1] << "," <<
device_property.maxThreadsDim[2] << ")" << std::endl;
// printf("Max dimension size of a grid size (x, y, z): (%d, %d, %d)\n",
// device_property.maxGridSize[0],
// device_property.maxGridSize[1],
// device_property.maxGridSize[2]);
std::cout << "Max dimension size of a grid size (x, y, z): " << "(" <<
device_property.maxGridSize[0] << "," <<
device_property.maxGridSize[1] << "," <<
device_property.maxGridSize[2] << ")" << std::endl;
// 查看设备是否支持双精度浮点操作，并为应用程序设置该设备
memset(&device_property, 0, sizeof(cudaDeviceProp));
// if major > 1 and minor > 3, then the device supports double precision.
device_property.major = 1;
device_property.minor = 3;
// 选择特定属性的设备
cudaChooseDevice(&device, &device_property);
// printf("ID of device which supports double precision is: %d\n", device);
std::cout << "ID of device which supports double precision is: " << device << std::endl;
// 设置设备为应用程序所用设备
cudaSetDevice(device);
return 0;
} | #include <iostream>
#include <memory>
#include <hip/hip_runtime.h>
/** 设备属性
* 了解 GPU 硬件设备的各项属性，有利于高效的利用 GPU 资源。
* 针对特定的硬件设备 GPU，为应用程序开发分配合理的资源。
* 具体使用的时候，需要查 CUDA 编程手册以及对应 GPU 硬件资源信息。
*
* D:\Nvidia\Samples\1_Utilities\deviceQuery\deviceQuery.cpp
*/
int main(int argc, char **argv)
{
int device_count = 0; // 可用设备数量
int device; // 设备名称编号
int driver_version; // CUDA 驱动版本号
int runtime_version; // 运行时引擎版本
// 通过查询 cudaDeviceProp 结构体来找到每个设备的相关信息，该结构体返回所有设备的属性。
// 如果有多个可用设备，可使用 for 循环遍历所有设备属性。
// get count of the avaiable CUDA hardware device in system.
hipGetDeviceCount(&device_count);
// This function returns count of number of CUDA enable devices and 0 if there are no CUDA capable devices.
if (device_count == 0)
{
// printf("There are no available devices that support CUDA.\n");
std::cout << "There are no available devices that support CUDA.\n";
}
else
{
// printf("Detected %d CUDA Capable devices.\n", device_count);
std::cout << "Detected " << device_count << " CUDA Capable devices.\n";
}
/**通用设备信息
* cudaDeviceProp 结构体提供可以用来识别设备以及确认使用的版本信息的属性，name属性以字符串形式返回设备名称。
* cudaDriverGetVersion 获取设备使用的 CUDA Driver。
* cudaRuntimeGetVersion 获取设备运行时引擎的版本。
* clockRate属性获取 GPU 的时钟速率。
* multiProcessorCount属性用于判断设备上流多处理器的个数。
*/
// 获取设备名称编号
hipGetDevice(&device);
// printf("ID of device: %d\n", device);
std::cout << "ID of device: " << device << std::endl;
// 获取设备结构体信息
hipDeviceProp_t device_property;
hipGetDeviceProperties(&device_property, device);
// printf("\nDevice %s: \n", device_property.name);
// device_property.name 获取 GPU 型号
std::cout << "The type of hardware GPU is: " << device_property.name << std::endl;
// 获取 CUDA 驱动版本号
hipDriverGetVersion(&driver_version);
std::cout << "CUDA Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// 获取运行时引擎版本
hipRuntimeGetVersion(&runtime_version);
std::cout << "CUDA Runtime Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// GPU 显存容量
// printf("Total amount of global memory: %.0f MBytes (%llu bytes)\n", (float)device_property.totalGlobalMem / 1048576.0f,
// (unsigned long long)device_property.totalGlobalMem);
std::cout << "Total amount of global memory: " << (float)device_property.totalGlobalMem / 1048576.0f << " MBytes" << std::endl;
// 具有最多流处理器的设备,如果有多个设备
printf(" (%2d) mutilprocessors\n", device_property.multiProcessorCount);
// std::cout << device_property.mutilProcessorCount << "mutilprocessors" << std::endl;
// GPU 时钟速率，以 KHz 为单位进行返回
// printf("GPU max clock rate: %.0f MHz (%.2f GHz)\n", device_property.clockRate * 1e-3f, device_property.clockRate * 1e-6f);
std::cout << "GPU max clock rate: " << device_property.clockRate * 1e-6f << " GHz" << std::endl;
// 显存频率
// printf("Memory clock rate: %.0f MHz\n", device_property.memoryClockRate * 1e-3f);
std::cout << "Memory clock rate: " << device_property.memoryClockRate * 1e-3f << " MHz" << std::endl;
// 显存位宽
// printf("Memory Bus Width: %d-bit\n", device_property.memoryBusWidth);
std::cout << "Memory Bus Width: " << device_property.memoryBusWidth << "-bit" << std::endl;
// L2 缓存
if (device_property.l2CacheSize)
{
// printf("L2 Cache size: %d bytes\n", device_property.l2CacheSize);
std::cout << "L2 Cache size: " << device_property.l2CacheSize << " bytes" << std::endl;
}
// 常量内存
// printf("Toal amount of constant memory: %lu bytes\n", device_property.totalConstMem);
std::cout << "Toal amount of constant memory: " << device_property.totalConstMem << " bytes" << std::endl;
// 共享内存
// printf("Toal amount of shared memory per block: %lu bytes\n", device_property.sharedMemPerBlock);
std::cout << "Toal amount of shared memory per block: " << device_property.sharedMemPerBlock << " bytes" << std::endl;
// 每一个块可用寄存器总数
// printf("Toal amount of registers available per block: %d\n", device_property.regsPerBlock);
std::cout << "Toal amount of registers available per block: " << device_property.regsPerBlock << std::endl;
// 网格grid 块block 线程thread 可以时多维的，每一个维度中可用并行启动多少个线程和块
// 这对于内核参数的配置十分重要
// printf("Maximum number of threads per multiprocessor: %d\n", device_property.maxThreadsPerMutilProcessor);
// std::cout << "Maximum number of threads per multiprocessor: " << device_property.maxThreadsPerMutilProcessor << std::endl;
// printf("Maximum number of threads per block: %d\n", device_property.maxThreadsPerBlock);
std::cout << "Maximum number of threads per block: " << device_property.maxThreadsPerBlock << std::endl;
// printf("Max dimension size of a thread block (x, y, z): (%d, %d, %d)\n",
// device_property.maxThreadsDim[0],
// device_property.maxThreadsDim[1],
// device_property.maxThreadsDim[2]);
std::cout << "Max dimension size of a thread block (x, y, z): " << "(" <<
device_property.maxThreadsDim[0] << "," <<
device_property.maxThreadsDim[1] << "," <<
device_property.maxThreadsDim[2] << ")" << std::endl;
// printf("Max dimension size of a grid size (x, y, z): (%d, %d, %d)\n",
// device_property.maxGridSize[0],
// device_property.maxGridSize[1],
// device_property.maxGridSize[2]);
std::cout << "Max dimension size of a grid size (x, y, z): " << "(" <<
device_property.maxGridSize[0] << "," <<
device_property.maxGridSize[1] << "," <<
device_property.maxGridSize[2] << ")" << std::endl;
// 查看设备是否支持双精度浮点操作，并为应用程序设置该设备
memset(&device_property, 0, sizeof(hipDeviceProp_t));
// if major > 1 and minor > 3, then the device supports double precision.
device_property.major = 1;
device_property.minor = 3;
// 选择特定属性的设备
hipChooseDevice(&device, &device_property);
// printf("ID of device which supports double precision is: %d\n", device);
std::cout << "ID of device which supports double precision is: " << device << std::endl;
// 设置设备为应用程序所用设备
hipSetDevice(device);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <memory>
#include <hip/hip_runtime.h>
/** 设备属性
* 了解 GPU 硬件设备的各项属性，有利于高效的利用 GPU 资源。
* 针对特定的硬件设备 GPU，为应用程序开发分配合理的资源。
* 具体使用的时候，需要查 CUDA 编程手册以及对应 GPU 硬件资源信息。
*
* D:\Nvidia\Samples\1_Utilities\deviceQuery\deviceQuery.cpp
*/
int main(int argc, char **argv)
{
int device_count = 0; // 可用设备数量
int device; // 设备名称编号
int driver_version; // CUDA 驱动版本号
int runtime_version; // 运行时引擎版本
// 通过查询 cudaDeviceProp 结构体来找到每个设备的相关信息，该结构体返回所有设备的属性。
// 如果有多个可用设备，可使用 for 循环遍历所有设备属性。
// get count of the avaiable CUDA hardware device in system.
hipGetDeviceCount(&device_count);
// This function returns count of number of CUDA enable devices and 0 if there are no CUDA capable devices.
if (device_count == 0)
{
// printf("There are no available devices that support CUDA.\n");
std::cout << "There are no available devices that support CUDA.\n";
}
else
{
// printf("Detected %d CUDA Capable devices.\n", device_count);
std::cout << "Detected " << device_count << " CUDA Capable devices.\n";
}
/**通用设备信息
* cudaDeviceProp 结构体提供可以用来识别设备以及确认使用的版本信息的属性，name属性以字符串形式返回设备名称。
* cudaDriverGetVersion 获取设备使用的 CUDA Driver。
* cudaRuntimeGetVersion 获取设备运行时引擎的版本。
* clockRate属性获取 GPU 的时钟速率。
* multiProcessorCount属性用于判断设备上流多处理器的个数。
*/
// 获取设备名称编号
hipGetDevice(&device);
// printf("ID of device: %d\n", device);
std::cout << "ID of device: " << device << std::endl;
// 获取设备结构体信息
hipDeviceProp_t device_property;
hipGetDeviceProperties(&device_property, device);
// printf("\nDevice %s: \n", device_property.name);
// device_property.name 获取 GPU 型号
std::cout << "The type of hardware GPU is: " << device_property.name << std::endl;
// 获取 CUDA 驱动版本号
hipDriverGetVersion(&driver_version);
std::cout << "CUDA Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// 获取运行时引擎版本
hipRuntimeGetVersion(&runtime_version);
std::cout << "CUDA Runtime Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// GPU 显存容量
// printf("Total amount of global memory: %.0f MBytes (%llu bytes)\n", (float)device_property.totalGlobalMem / 1048576.0f,
// (unsigned long long)device_property.totalGlobalMem);
std::cout << "Total amount of global memory: " << (float)device_property.totalGlobalMem / 1048576.0f << " MBytes" << std::endl;
// 具有最多流处理器的设备,如果有多个设备
printf(" (%2d) mutilprocessors\n", device_property.multiProcessorCount);
// std::cout << device_property.mutilProcessorCount << "mutilprocessors" << std::endl;
// GPU 时钟速率，以 KHz 为单位进行返回
// printf("GPU max clock rate: %.0f MHz (%.2f GHz)\n", device_property.clockRate * 1e-3f, device_property.clockRate * 1e-6f);
std::cout << "GPU max clock rate: " << device_property.clockRate * 1e-6f << " GHz" << std::endl;
// 显存频率
// printf("Memory clock rate: %.0f MHz\n", device_property.memoryClockRate * 1e-3f);
std::cout << "Memory clock rate: " << device_property.memoryClockRate * 1e-3f << " MHz" << std::endl;
// 显存位宽
// printf("Memory Bus Width: %d-bit\n", device_property.memoryBusWidth);
std::cout << "Memory Bus Width: " << device_property.memoryBusWidth << "-bit" << std::endl;
// L2 缓存
if (device_property.l2CacheSize)
{
// printf("L2 Cache size: %d bytes\n", device_property.l2CacheSize);
std::cout << "L2 Cache size: " << device_property.l2CacheSize << " bytes" << std::endl;
}
// 常量内存
// printf("Toal amount of constant memory: %lu bytes\n", device_property.totalConstMem);
std::cout << "Toal amount of constant memory: " << device_property.totalConstMem << " bytes" << std::endl;
// 共享内存
// printf("Toal amount of shared memory per block: %lu bytes\n", device_property.sharedMemPerBlock);
std::cout << "Toal amount of shared memory per block: " << device_property.sharedMemPerBlock << " bytes" << std::endl;
// 每一个块可用寄存器总数
// printf("Toal amount of registers available per block: %d\n", device_property.regsPerBlock);
std::cout << "Toal amount of registers available per block: " << device_property.regsPerBlock << std::endl;
// 网格grid 块block 线程thread 可以时多维的，每一个维度中可用并行启动多少个线程和块
// 这对于内核参数的配置十分重要
// printf("Maximum number of threads per multiprocessor: %d\n", device_property.maxThreadsPerMutilProcessor);
// std::cout << "Maximum number of threads per multiprocessor: " << device_property.maxThreadsPerMutilProcessor << std::endl;
// printf("Maximum number of threads per block: %d\n", device_property.maxThreadsPerBlock);
std::cout << "Maximum number of threads per block: " << device_property.maxThreadsPerBlock << std::endl;
// printf("Max dimension size of a thread block (x, y, z): (%d, %d, %d)\n",
// device_property.maxThreadsDim[0],
// device_property.maxThreadsDim[1],
// device_property.maxThreadsDim[2]);
std::cout << "Max dimension size of a thread block (x, y, z): " << "(" <<
device_property.maxThreadsDim[0] << "," <<
device_property.maxThreadsDim[1] << "," <<
device_property.maxThreadsDim[2] << ")" << std::endl;
// printf("Max dimension size of a grid size (x, y, z): (%d, %d, %d)\n",
// device_property.maxGridSize[0],
// device_property.maxGridSize[1],
// device_property.maxGridSize[2]);
std::cout << "Max dimension size of a grid size (x, y, z): " << "(" <<
device_property.maxGridSize[0] << "," <<
device_property.maxGridSize[1] << "," <<
device_property.maxGridSize[2] << ")" << std::endl;
// 查看设备是否支持双精度浮点操作，并为应用程序设置该设备
memset(&device_property, 0, sizeof(hipDeviceProp_t));
// if major > 1 and minor > 3, then the device supports double precision.
device_property.major = 1;
device_property.minor = 3;
// 选择特定属性的设备
hipChooseDevice(&device, &device_property);
// printf("ID of device which supports double precision is: %d\n", device);
std::cout << "ID of device which supports double precision is: " << device << std::endl;
// 设置设备为应用程序所用设备
hipSetDevice(device);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <memory>
#include <hip/hip_runtime.h>
/** 设备属性
* 了解 GPU 硬件设备的各项属性，有利于高效的利用 GPU 资源。
* 针对特定的硬件设备 GPU，为应用程序开发分配合理的资源。
* 具体使用的时候，需要查 CUDA 编程手册以及对应 GPU 硬件资源信息。
*
* D:\Nvidia\Samples\1_Utilities\deviceQuery\deviceQuery.cpp
*/
int main(int argc, char **argv)
{
int device_count = 0; // 可用设备数量
int device; // 设备名称编号
int driver_version; // CUDA 驱动版本号
int runtime_version; // 运行时引擎版本
// 通过查询 cudaDeviceProp 结构体来找到每个设备的相关信息，该结构体返回所有设备的属性。
// 如果有多个可用设备，可使用 for 循环遍历所有设备属性。
// get count of the avaiable CUDA hardware device in system.
hipGetDeviceCount(&device_count);
// This function returns count of number of CUDA enable devices and 0 if there are no CUDA capable devices.
if (device_count == 0)
{
// printf("There are no available devices that support CUDA.\n");
std::cout << "There are no available devices that support CUDA.\n";
}
else
{
// printf("Detected %d CUDA Capable devices.\n", device_count);
std::cout << "Detected " << device_count << " CUDA Capable devices.\n";
}
/**通用设备信息
* cudaDeviceProp 结构体提供可以用来识别设备以及确认使用的版本信息的属性，name属性以字符串形式返回设备名称。
* cudaDriverGetVersion 获取设备使用的 CUDA Driver。
* cudaRuntimeGetVersion 获取设备运行时引擎的版本。
* clockRate属性获取 GPU 的时钟速率。
* multiProcessorCount属性用于判断设备上流多处理器的个数。
*/
// 获取设备名称编号
hipGetDevice(&device);
// printf("ID of device: %d\n", device);
std::cout << "ID of device: " << device << std::endl;
// 获取设备结构体信息
hipDeviceProp_t device_property;
hipGetDeviceProperties(&device_property, device);
// printf("\nDevice %s: \n", device_property.name);
// device_property.name 获取 GPU 型号
std::cout << "The type of hardware GPU is: " << device_property.name << std::endl;
// 获取 CUDA 驱动版本号
hipDriverGetVersion(&driver_version);
std::cout << "CUDA Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// 获取运行时引擎版本
hipRuntimeGetVersion(&runtime_version);
std::cout << "CUDA Runtime Driver Version is: CUDA " << driver_version / 1000 << "." << (driver_version % 100) / 10 << std::endl;
// GPU 显存容量
// printf("Total amount of global memory: %.0f MBytes (%llu bytes)\n", (float)device_property.totalGlobalMem / 1048576.0f,
// (unsigned long long)device_property.totalGlobalMem);
std::cout << "Total amount of global memory: " << (float)device_property.totalGlobalMem / 1048576.0f << " MBytes" << std::endl;
// 具有最多流处理器的设备,如果有多个设备
printf(" (%2d) mutilprocessors\n", device_property.multiProcessorCount);
// std::cout << device_property.mutilProcessorCount << "mutilprocessors" << std::endl;
// GPU 时钟速率，以 KHz 为单位进行返回
// printf("GPU max clock rate: %.0f MHz (%.2f GHz)\n", device_property.clockRate * 1e-3f, device_property.clockRate * 1e-6f);
std::cout << "GPU max clock rate: " << device_property.clockRate * 1e-6f << " GHz" << std::endl;
// 显存频率
// printf("Memory clock rate: %.0f MHz\n", device_property.memoryClockRate * 1e-3f);
std::cout << "Memory clock rate: " << device_property.memoryClockRate * 1e-3f << " MHz" << std::endl;
// 显存位宽
// printf("Memory Bus Width: %d-bit\n", device_property.memoryBusWidth);
std::cout << "Memory Bus Width: " << device_property.memoryBusWidth << "-bit" << std::endl;
// L2 缓存
if (device_property.l2CacheSize)
{
// printf("L2 Cache size: %d bytes\n", device_property.l2CacheSize);
std::cout << "L2 Cache size: " << device_property.l2CacheSize << " bytes" << std::endl;
}
// 常量内存
// printf("Toal amount of constant memory: %lu bytes\n", device_property.totalConstMem);
std::cout << "Toal amount of constant memory: " << device_property.totalConstMem << " bytes" << std::endl;
// 共享内存
// printf("Toal amount of shared memory per block: %lu bytes\n", device_property.sharedMemPerBlock);
std::cout << "Toal amount of shared memory per block: " << device_property.sharedMemPerBlock << " bytes" << std::endl;
// 每一个块可用寄存器总数
// printf("Toal amount of registers available per block: %d\n", device_property.regsPerBlock);
std::cout << "Toal amount of registers available per block: " << device_property.regsPerBlock << std::endl;
// 网格grid 块block 线程thread 可以时多维的，每一个维度中可用并行启动多少个线程和块
// 这对于内核参数的配置十分重要
// printf("Maximum number of threads per multiprocessor: %d\n", device_property.maxThreadsPerMutilProcessor);
// std::cout << "Maximum number of threads per multiprocessor: " << device_property.maxThreadsPerMutilProcessor << std::endl;
// printf("Maximum number of threads per block: %d\n", device_property.maxThreadsPerBlock);
std::cout << "Maximum number of threads per block: " << device_property.maxThreadsPerBlock << std::endl;
// printf("Max dimension size of a thread block (x, y, z): (%d, %d, %d)\n",
// device_property.maxThreadsDim[0],
// device_property.maxThreadsDim[1],
// device_property.maxThreadsDim[2]);
std::cout << "Max dimension size of a thread block (x, y, z): " << "(" <<
device_property.maxThreadsDim[0] << "," <<
device_property.maxThreadsDim[1] << "," <<
device_property.maxThreadsDim[2] << ")" << std::endl;
// printf("Max dimension size of a grid size (x, y, z): (%d, %d, %d)\n",
// device_property.maxGridSize[0],
// device_property.maxGridSize[1],
// device_property.maxGridSize[2]);
std::cout << "Max dimension size of a grid size (x, y, z): " << "(" <<
device_property.maxGridSize[0] << "," <<
device_property.maxGridSize[1] << "," <<
device_property.maxGridSize[2] << ")" << std::endl;
// 查看设备是否支持双精度浮点操作，并为应用程序设置该设备
memset(&device_property, 0, sizeof(hipDeviceProp_t));
// if major > 1 and minor > 3, then the device supports double precision.
device_property.major = 1;
device_property.minor = 3;
// 选择特定属性的设备
hipChooseDevice(&device, &device_property);
// printf("ID of device which supports double precision is: %d\n", device);
std::cout << "ID of device which supports double precision is: " << device << std::endl;
// 设置设备为应用程序所用设备
hipSetDevice(device);
return 0;
} | .text
.file "2_04_device_information.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.LCPI0_1:
.long 0x358637bd # float 9.99999997E-7
.LCPI0_2:
.long 0x3a83126f # float 0.00100000005
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 16(%rsp)
leaq 16(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 16(%rsp)
je .LBB0_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $23, %edx
movq %rax, %rdi
jmp .LBB0_3
.LBB0_1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $50, %edx
.LBB0_3:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 8(%rsp), %rdi
callq hipGetDevice
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB0_7
.LBB0_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 8(%rsp), %esi
leaq 24(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB0_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB0_11
.LBB0_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 12(%rsp), %rdi
callq hipDriverGetVersion
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rsi # imm = 0x66666667
movq %rsi, %rax
shrq $63, %rax
sarq $34, %rsi
addl %eax, %esi
movq %rbx, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB0_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB0_15
.LBB0_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 20(%rsp), %rdi
callq hipRuntimeGetVersion
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rsi # imm = 0x66666667
movq %rsi, %rax
shrq $63, %rax
sarq $34, %rsi
addl %eax, %esi
movq %rbx, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%rbx)
je .LBB0_18
# %bb.17:
movzbl 67(%rbx), %ecx
jmp .LBB0_19
.LBB0_18:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 312(%rsp), %rax
testq %rax, %rax
js .LBB0_20
# %bb.21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
cvtsi2ss %rax, %xmm0
jmp .LBB0_22
.LBB0_20:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.9, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r14)
je .LBB0_25
# %bb.24:
movzbl 67(%r14), %eax
jmp .LBB0_26
.LBB0_25:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 412(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ssl 372(%rsp), %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.12, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r14)
je .LBB0_29
# %bb.28:
movzbl 67(%r14), %eax
jmp .LBB0_30
.LBB0_29:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ssl 632(%rsp), %xmm0
mulss .LCPI0_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.14, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r14)
je .LBB0_33
# %bb.32:
movzbl 67(%r14), %eax
jmp .LBB0_34
.LBB0_33:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 636(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.16, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%r14)
je .LBB0_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB0_38
.LBB0_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 640(%rsp)
je .LBB0_44
# %bb.39:
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 640(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.18, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.40: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%r14)
je .LBB0_42
# %bb.41:
movzbl 67(%r14), %eax
jmp .LBB0_43
.LBB0_42:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_43: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_44:
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 376(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.18, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%r14)
je .LBB0_47
# %bb.46:
movzbl 67(%r14), %eax
jmp .LBB0_48
.LBB0_47:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 320(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.18, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB0_51
# %bb.50:
movzbl 67(%r14), %eax
jmp .LBB0_52
.LBB0_51:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52
cmpb $0, 56(%rbx)
je .LBB0_55
# %bb.54:
movzbl 67(%rbx), %ecx
jmp .LBB0_56
.LBB0_55:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_56: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit55
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.22, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 344(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.57: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i57
cmpb $0, 56(%rbx)
je .LBB0_59
# %bb.58:
movzbl 67(%rbx), %ecx
jmp .LBB0_60
.LBB0_59:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_60: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit60
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.23, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.24, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 348(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 352(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 356(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.26, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.61: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%r14)
je .LBB0_63
# %bb.62:
movzbl 67(%r14), %eax
jmp .LBB0_64
.LBB0_63:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_64: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit65
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.27, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.24, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 360(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 364(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.26, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.65: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r14)
je .LBB0_67
# %bb.66:
movzbl 67(%r14), %eax
jmp .LBB0_68
.LBB0_67:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_68: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit70
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 24(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $12884901889, %rax # imm = 0x300000001
movq %rax, 384(%rsp)
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipChooseDeviceR0600
movl $_ZSt4cout, %edi
movl $.L.str.28, %esi
movl $49, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.69: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
cmpb $0, 56(%rbx)
je .LBB0_71
# %bb.70:
movzbl 67(%rbx), %ecx
jmp .LBB0_72
.LBB0_71:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_72: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit75
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 8(%rsp), %edi
callq hipSetDevice
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_73:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There are no available devices that support CUDA.\n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Detected "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " CUDA Capable devices.\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ID of device: "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "The type of hardware GPU is: "
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Driver Version is: CUDA "
.size .L.str.5, 30
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "."
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA Runtime Driver Version is: CUDA "
.size .L.str.7, 38
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Total amount of global memory: "
.size .L.str.8, 32
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " MBytes"
.size .L.str.9, 8
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " (%2d) mutilprocessors\n"
.size .L.str.10, 24
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "GPU max clock rate: "
.size .L.str.11, 21
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " GHz"
.size .L.str.12, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Memory clock rate: "
.size .L.str.13, 20
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " MHz"
.size .L.str.14, 5
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Memory Bus Width: "
.size .L.str.15, 19
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "-bit"
.size .L.str.16, 5
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "L2 Cache size: "
.size .L.str.17, 16
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " bytes"
.size .L.str.18, 7
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Toal amount of constant memory: "
.size .L.str.19, 33
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Toal amount of shared memory per block: "
.size .L.str.20, 41
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Toal amount of registers available per block: "
.size .L.str.21, 47
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Maximum number of threads per block: "
.size .L.str.22, 38
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Max dimension size of a thread block (x, y, z): "
.size .L.str.23, 49
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "("
.size .L.str.24, 2
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz ","
.size .L.str.25, 2
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz ")"
.size .L.str.26, 2
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "Max dimension size of a grid size (x, y, z): "
.size .L.str.27, 46
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "ID of device which supports double precision is: "
.size .L.str.28, 50
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00016514_00000000-6_2_04_device_information.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "There are no available devices that support CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Detected "
.LC2:
.string " CUDA Capable devices.\n"
.LC3:
.string "ID of device: "
.LC4:
.string "The type of hardware GPU is: "
.LC5:
.string "CUDA Driver Version is: CUDA "
.LC6:
.string "."
.section .rodata.str1.8
.align 8
.LC7:
.string "CUDA Runtime Driver Version is: CUDA "
.align 8
.LC8:
.string "Total amount of global memory: "
.section .rodata.str1.1
.LC10:
.string " MBytes"
.LC11:
.string " (%2d) mutilprocessors\n"
.LC12:
.string "GPU max clock rate: "
.LC14:
.string " GHz"
.LC15:
.string "Memory clock rate: "
.LC17:
.string " MHz"
.LC18:
.string "Memory Bus Width: "
.LC19:
.string "-bit"
.LC20:
.string "L2 Cache size: "
.LC21:
.string " bytes"
.section .rodata.str1.8
.align 8
.LC22:
.string "Toal amount of constant memory: "
.align 8
.LC23:
.string "Toal amount of shared memory per block: "
.align 8
.LC24:
.string "Toal amount of registers available per block: "
.align 8
.LC25:
.string "Maximum number of threads per block: "
.align 8
.LC26:
.string "Max dimension size of a thread block (x, y, z): "
.section .rodata.str1.1
.LC27:
.string "("
.LC28:
.string ","
.LC29:
.string ")"
.section .rodata.str1.8
.align 8
.LC30:
.string "Max dimension size of a grid size (x, y, z): "
.align 8
.LC31:
.string "ID of device which supports double precision is: "
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movq %rsp, %rdi
call cudaGetDeviceCount@PLT
cmpl $0, (%rsp)
jne .L4
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L5:
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rbp
movl 4(%rsp), %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %edx
movslq %edx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %edx
movslq %edx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rdx
testq %rdx, %rdx
js .L6
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L7:
mulss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 404(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LC16(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 628(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 632(%rsp)
jne .L11
.L8:
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 368(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 312(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC24(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 320(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC25(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 336(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC26(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC27(%rip), %r13
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 340(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC28(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 344(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 348(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC29(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC30(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 352(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 356(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 360(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rsi
movl $129, %ecx
movl $0, %eax
movq %rsi, %rdi
rep stosq
movl $1, 376(%rsp)
movl $3, 380(%rsp)
leaq 4(%rsp), %rdi
call cudaChooseDevice@PLT
leaq .LC31(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 4(%rsp), %edi
call cudaSetDevice@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.L6:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L7
.L11:
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 632(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L8
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 897581056
.align 4
.LC13:
.long 897988541
.align 4
.LC16:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2_04_device_information.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.LCPI0_1:
.long 0x358637bd # float 9.99999997E-7
.LCPI0_2:
.long 0x3a83126f # float 0.00100000005
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 16(%rsp)
leaq 16(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 16(%rsp)
je .LBB0_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $23, %edx
movq %rax, %rdi
jmp .LBB0_3
.LBB0_1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $50, %edx
.LBB0_3:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 8(%rsp), %rdi
callq hipGetDevice
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB0_7
.LBB0_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 8(%rsp), %esi
leaq 24(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB0_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB0_11
.LBB0_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 12(%rsp), %rdi
callq hipDriverGetVersion
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rsi # imm = 0x66666667
movq %rsi, %rax
shrq $63, %rax
sarq $34, %rsi
addl %eax, %esi
movq %rbx, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB0_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB0_15
.LBB0_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 20(%rsp), %rdi
callq hipRuntimeGetVersion
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 12(%rsp), %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rsi # imm = 0x66666667
movq %rsi, %rax
shrq $63, %rax
sarq $34, %rsi
addl %eax, %esi
movq %rbx, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%rbx)
je .LBB0_18
# %bb.17:
movzbl 67(%rbx), %ecx
jmp .LBB0_19
.LBB0_18:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 312(%rsp), %rax
testq %rax, %rax
js .LBB0_20
# %bb.21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
cvtsi2ss %rax, %xmm0
jmp .LBB0_22
.LBB0_20:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.9, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r14)
je .LBB0_25
# %bb.24:
movzbl 67(%r14), %eax
jmp .LBB0_26
.LBB0_25:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 412(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ssl 372(%rsp), %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.12, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r14)
je .LBB0_29
# %bb.28:
movzbl 67(%r14), %eax
jmp .LBB0_30
.LBB0_29:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ssl 632(%rsp), %xmm0
mulss .LCPI0_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.14, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r14)
je .LBB0_33
# %bb.32:
movzbl 67(%r14), %eax
jmp .LBB0_34
.LBB0_33:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 636(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.16, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%r14)
je .LBB0_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB0_38
.LBB0_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 640(%rsp)
je .LBB0_44
# %bb.39:
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 640(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.18, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.40: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%r14)
je .LBB0_42
# %bb.41:
movzbl 67(%r14), %eax
jmp .LBB0_43
.LBB0_42:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_43: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_44:
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 376(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.18, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%r14)
je .LBB0_47
# %bb.46:
movzbl 67(%r14), %eax
jmp .LBB0_48
.LBB0_47:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 320(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.18, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB0_51
# %bb.50:
movzbl 67(%r14), %eax
jmp .LBB0_52
.LBB0_51:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52
cmpb $0, 56(%rbx)
je .LBB0_55
# %bb.54:
movzbl 67(%rbx), %ecx
jmp .LBB0_56
.LBB0_55:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_56: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit55
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.22, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 344(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.57: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i57
cmpb $0, 56(%rbx)
je .LBB0_59
# %bb.58:
movzbl 67(%rbx), %ecx
jmp .LBB0_60
.LBB0_59:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_60: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit60
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.23, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.24, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 348(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 352(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 356(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.26, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.61: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%r14)
je .LBB0_63
# %bb.62:
movzbl 67(%r14), %eax
jmp .LBB0_64
.LBB0_63:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_64: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit65
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.27, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.24, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 360(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 364(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.26, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_73
# %bb.65: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r14)
je .LBB0_67
# %bb.66:
movzbl 67(%r14), %eax
jmp .LBB0_68
.LBB0_67:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_68: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit70
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 24(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $12884901889, %rax # imm = 0x300000001
movq %rax, 384(%rsp)
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipChooseDeviceR0600
movl $_ZSt4cout, %edi
movl $.L.str.28, %esi
movl $49, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_73
# %bb.69: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
cmpb $0, 56(%rbx)
je .LBB0_71
# %bb.70:
movzbl 67(%rbx), %ecx
jmp .LBB0_72
.LBB0_71:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_72: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit75
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 8(%rsp), %edi
callq hipSetDevice
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_73:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There are no available devices that support CUDA.\n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Detected "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " CUDA Capable devices.\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ID of device: "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "The type of hardware GPU is: "
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Driver Version is: CUDA "
.size .L.str.5, 30
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "."
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA Runtime Driver Version is: CUDA "
.size .L.str.7, 38
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Total amount of global memory: "
.size .L.str.8, 32
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " MBytes"
.size .L.str.9, 8
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " (%2d) mutilprocessors\n"
.size .L.str.10, 24
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "GPU max clock rate: "
.size .L.str.11, 21
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " GHz"
.size .L.str.12, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Memory clock rate: "
.size .L.str.13, 20
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " MHz"
.size .L.str.14, 5
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Memory Bus Width: "
.size .L.str.15, 19
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "-bit"
.size .L.str.16, 5
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "L2 Cache size: "
.size .L.str.17, 16
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " bytes"
.size .L.str.18, 7
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Toal amount of constant memory: "
.size .L.str.19, 33
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Toal amount of shared memory per block: "
.size .L.str.20, 41
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Toal amount of registers available per block: "
.size .L.str.21, 47
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Maximum number of threads per block: "
.size .L.str.22, 38
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Max dimension size of a thread block (x, y, z): "
.size .L.str.23, 49
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "("
.size .L.str.24, 2
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz ","
.size .L.str.25, 2
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz ")"
.size .L.str.26, 2
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "Max dimension size of a grid size (x, y, z): "
.size .L.str.27, 46
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "ID of device which supports double precision is: "
.size .L.str.28, 50
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <bits/stdc++.h>
using namespace std;
#define THREADS_PER_BLOCK 1024//1024
void initData(int* M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
M[cols * i + j] = 2;
}
}
}
void displayData(int *M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
cout<< M[cols * i + j]<<" ";
}
cout<<endl;
}
cout<<endl;
}
__global__ void sum(int *a, int *b, int *r, int tam) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if( index < tam){
r[index] = a[index] + b[index];
}
}
void matrixAdd(int *A, int *B, int* R, int rows, int cols){
int *d_A, *d_B, *d_R;
int nElem = rows * cols;
int size = nElem * sizeof(int);
//Allocate device memory for matrices
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
cudaMalloc((void **) &d_R, size);
//Copy B and C to device memory
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
sum<<<(nElem+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_A, d_B, d_R, nElem);//run
cudaMemcpy(R, d_R, size, cudaMemcpyDeviceToHost);
//Free device matrices
cudaFree(d_B);
cudaFree(d_A);
cudaFree(d_R);
}
int run(){
int rows = 10;
int cols = 10;
int nElem = rows * cols;
int * A = (int *) malloc(nElem * sizeof(int));
int * B = (int *) malloc(nElem * sizeof(int));
int * R = (int *) malloc(nElem * sizeof(int));
initData(B, rows, cols);
initData(A, rows, cols);
matrixAdd(A, B, R, rows, cols);
//displayData(A, rows, cols);
//displayData(B, rows, cols);
displayData(R, rows, cols);
free(A); free(B); free(R);
}
int main(){
run();
return 0;
} | code for sm_80
Function : _Z3sumPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <bits/stdc++.h>
using namespace std;
#define THREADS_PER_BLOCK 1024//1024
void initData(int* M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
M[cols * i + j] = 2;
}
}
}
void displayData(int *M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
cout<< M[cols * i + j]<<" ";
}
cout<<endl;
}
cout<<endl;
}
__global__ void sum(int *a, int *b, int *r, int tam) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if( index < tam){
r[index] = a[index] + b[index];
}
}
void matrixAdd(int *A, int *B, int* R, int rows, int cols){
int *d_A, *d_B, *d_R;
int nElem = rows * cols;
int size = nElem * sizeof(int);
//Allocate device memory for matrices
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
cudaMalloc((void **) &d_R, size);
//Copy B and C to device memory
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
sum<<<(nElem+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_A, d_B, d_R, nElem);//run
cudaMemcpy(R, d_R, size, cudaMemcpyDeviceToHost);
//Free device matrices
cudaFree(d_B);
cudaFree(d_A);
cudaFree(d_R);
}
int run(){
int rows = 10;
int cols = 10;
int nElem = rows * cols;
int * A = (int *) malloc(nElem * sizeof(int));
int * B = (int *) malloc(nElem * sizeof(int));
int * R = (int *) malloc(nElem * sizeof(int));
initData(B, rows, cols);
initData(A, rows, cols);
matrixAdd(A, B, R, rows, cols);
//displayData(A, rows, cols);
//displayData(B, rows, cols);
displayData(R, rows, cols);
free(A); free(B); free(R);
}
int main(){
run();
return 0;
} | .file "tmpxft_0003ea09_00000000-6_suma_matriz_vector-mode.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10866:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10866:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initDataPiii
.type _Z8initDataPiii, @function
_Z8initDataPiii:
.LFB10859:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movl $0, %r9d
movl $0, %r8d
movslq %edx, %r10
jmp .L5
.L7:
movslq %r9d, %rcx
leaq (%rdi,%rcx,4), %rax
addq %r10, %rcx
leaq (%rdi,%rcx,4), %rcx
.L6:
movl $2, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r8d
addl %edx, %r9d
cmpl %r8d, %esi
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE10859:
.size _Z8initDataPiii, .-_Z8initDataPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z11displayDataPiii
.type _Z11displayDataPiii, @function
_Z11displayDataPiii:
.LFB10860:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
testl %esi, %esi
jle .L11
movl $0, %r15d
movl $0, %r14d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L12
.L24:
call _ZSt16__throw_bad_castv@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, 12(%rsp)
je .L11
.L12:
cmpl $0, 8(%rsp)
jle .L18
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %r12
.L13:
movl (%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
.L18:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L24
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %esi
jmp .L16
.L11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L20
movzbl 67(%rbx), %eax
.L21:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L20:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L21
.cfi_endproc
.LFE10860:
.size _Z11displayDataPiii, .-_Z11displayDataPiii
.globl _Z27__device_stub__Z3sumPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3sumPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3sumPiS_S_iPiS_S_i:
.LFB10888:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10888:
.size _Z27__device_stub__Z3sumPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3sumPiS_S_iPiS_S_i
.globl _Z3sumPiS_S_i
.type _Z3sumPiS_S_i, @function
_Z3sumPiS_S_i:
.LFB10889:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3sumPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10889:
.size _Z3sumPiS_S_i, .-_Z3sumPiS_S_i
.globl _Z9matrixAddPiS_S_ii
.type _Z9matrixAddPiS_S_ii, @function
_Z9matrixAddPiS_S_ii:
.LFB10861:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
imull %r8d, %ecx
movl %ecx, %ebp
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
leal 2046(%rbp), %eax
movl %ebp, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3sumPiS_S_iPiS_S_i
jmp .L35
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10861:
.size _Z9matrixAddPiS_S_ii, .-_Z9matrixAddPiS_S_ii
.globl _Z3runv
.type _Z3runv, @function
_Z3runv:
.LFB10862:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $400, %edi
call malloc@PLT
movq %rax, %r12
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $10, %edx
movl $10, %esi
movq %rbp, %rdi
call _Z8initDataPiii
movl $10, %edx
movl $10, %esi
movq %r12, %rdi
call _Z8initDataPiii
movl $10, %r8d
movl $10, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z9matrixAddPiS_S_ii
movl $10, %edx
movl $10, %esi
movq %rbx, %rdi
call _Z11displayDataPiii
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
.cfi_endproc
.LFE10862:
.size _Z3runv, .-_Z3runv
.globl main
.type main, @function
main:
.LFB10863:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z3runv
.cfi_endproc
.LFE10863:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3sumPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10891:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10891:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <bits/stdc++.h>
using namespace std;
#define THREADS_PER_BLOCK 1024//1024
void initData(int* M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
M[cols * i + j] = 2;
}
}
}
void displayData(int *M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
cout<< M[cols * i + j]<<" ";
}
cout<<endl;
}
cout<<endl;
}
__global__ void sum(int *a, int *b, int *r, int tam) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if( index < tam){
r[index] = a[index] + b[index];
}
}
void matrixAdd(int *A, int *B, int* R, int rows, int cols){
int *d_A, *d_B, *d_R;
int nElem = rows * cols;
int size = nElem * sizeof(int);
//Allocate device memory for matrices
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
cudaMalloc((void **) &d_R, size);
//Copy B and C to device memory
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
sum<<<(nElem+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_A, d_B, d_R, nElem);//run
cudaMemcpy(R, d_R, size, cudaMemcpyDeviceToHost);
//Free device matrices
cudaFree(d_B);
cudaFree(d_A);
cudaFree(d_R);
}
int run(){
int rows = 10;
int cols = 10;
int nElem = rows * cols;
int * A = (int *) malloc(nElem * sizeof(int));
int * B = (int *) malloc(nElem * sizeof(int));
int * R = (int *) malloc(nElem * sizeof(int));
initData(B, rows, cols);
initData(A, rows, cols);
matrixAdd(A, B, R, rows, cols);
//displayData(A, rows, cols);
//displayData(B, rows, cols);
displayData(R, rows, cols);
free(A); free(B); free(R);
}
int main(){
run();
return 0;
} | #include <hip/hip_runtime.h>
#include <bits/stdc++.h>
using namespace std;
#define THREADS_PER_BLOCK 1024//1024
void initData(int* M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
M[cols * i + j] = 2;
}
}
}
void displayData(int *M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
cout<< M[cols * i + j]<<" ";
}
cout<<endl;
}
cout<<endl;
}
__global__ void sum(int *a, int *b, int *r, int tam) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if( index < tam){
r[index] = a[index] + b[index];
}
}
void matrixAdd(int *A, int *B, int* R, int rows, int cols){
int *d_A, *d_B, *d_R;
int nElem = rows * cols;
int size = nElem * sizeof(int);
//Allocate device memory for matrices
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
hipMalloc((void **) &d_R, size);
//Copy B and C to device memory
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
sum<<<(nElem+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_A, d_B, d_R, nElem);//run
hipMemcpy(R, d_R, size, hipMemcpyDeviceToHost);
//Free device matrices
hipFree(d_B);
hipFree(d_A);
hipFree(d_R);
}
int run(){
int rows = 10;
int cols = 10;
int nElem = rows * cols;
int * A = (int *) malloc(nElem * sizeof(int));
int * B = (int *) malloc(nElem * sizeof(int));
int * R = (int *) malloc(nElem * sizeof(int));
initData(B, rows, cols);
initData(A, rows, cols);
matrixAdd(A, B, R, rows, cols);
//displayData(A, rows, cols);
//displayData(B, rows, cols);
displayData(R, rows, cols);
free(A); free(B); free(R);
}
int main(){
run();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <bits/stdc++.h>
using namespace std;
#define THREADS_PER_BLOCK 1024//1024
void initData(int* M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
M[cols * i + j] = 2;
}
}
}
void displayData(int *M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
cout<< M[cols * i + j]<<" ";
}
cout<<endl;
}
cout<<endl;
}
__global__ void sum(int *a, int *b, int *r, int tam) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if( index < tam){
r[index] = a[index] + b[index];
}
}
void matrixAdd(int *A, int *B, int* R, int rows, int cols){
int *d_A, *d_B, *d_R;
int nElem = rows * cols;
int size = nElem * sizeof(int);
//Allocate device memory for matrices
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
hipMalloc((void **) &d_R, size);
//Copy B and C to device memory
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
sum<<<(nElem+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_A, d_B, d_R, nElem);//run
hipMemcpy(R, d_R, size, hipMemcpyDeviceToHost);
//Free device matrices
hipFree(d_B);
hipFree(d_A);
hipFree(d_R);
}
int run(){
int rows = 10;
int cols = 10;
int nElem = rows * cols;
int * A = (int *) malloc(nElem * sizeof(int));
int * B = (int *) malloc(nElem * sizeof(int));
int * R = (int *) malloc(nElem * sizeof(int));
initData(B, rows, cols);
initData(A, rows, cols);
matrixAdd(A, B, R, rows, cols);
//displayData(A, rows, cols);
//displayData(B, rows, cols);
displayData(R, rows, cols);
free(A); free(B); free(R);
}
int main(){
run();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_S_i
.globl _Z3sumPiS_S_i
.p2align 8
.type _Z3sumPiS_S_i,@function
_Z3sumPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_S_i, .Lfunc_end0-_Z3sumPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <bits/stdc++.h>
using namespace std;
#define THREADS_PER_BLOCK 1024//1024
void initData(int* M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
M[cols * i + j] = 2;
}
}
}
void displayData(int *M, int rows, int cols){
for (int i=0; i<rows; i++){
for(int j=0; j<cols; j++){
cout<< M[cols * i + j]<<" ";
}
cout<<endl;
}
cout<<endl;
}
__global__ void sum(int *a, int *b, int *r, int tam) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if( index < tam){
r[index] = a[index] + b[index];
}
}
void matrixAdd(int *A, int *B, int* R, int rows, int cols){
int *d_A, *d_B, *d_R;
int nElem = rows * cols;
int size = nElem * sizeof(int);
//Allocate device memory for matrices
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
hipMalloc((void **) &d_R, size);
//Copy B and C to device memory
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
sum<<<(nElem+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_A, d_B, d_R, nElem);//run
hipMemcpy(R, d_R, size, hipMemcpyDeviceToHost);
//Free device matrices
hipFree(d_B);
hipFree(d_A);
hipFree(d_R);
}
int run(){
int rows = 10;
int cols = 10;
int nElem = rows * cols;
int * A = (int *) malloc(nElem * sizeof(int));
int * B = (int *) malloc(nElem * sizeof(int));
int * R = (int *) malloc(nElem * sizeof(int));
initData(B, rows, cols);
initData(A, rows, cols);
matrixAdd(A, B, R, rows, cols);
//displayData(A, rows, cols);
//displayData(B, rows, cols);
displayData(R, rows, cols);
free(A); free(B); free(R);
}
int main(){
run();
return 0;
} | .text
.file "suma_matriz_vector-mode.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initDataPiii # -- Begin function _Z8initDataPiii
.p2align 4, 0x90
.type _Z8initDataPiii,@function
_Z8initDataPiii: # @_Z8initDataPiii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge13
retq
.Lfunc_end0:
.size _Z8initDataPiii, .Lfunc_end0-_Z8initDataPiii
.cfi_endproc
# -- End function
.globl _Z11displayDataPiii # -- Begin function _Z11displayDataPiii
.p2align 4, 0x90
.type _Z11displayDataPiii,@function
_Z11displayDataPiii: # @_Z11displayDataPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_8
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r13d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
addl %ebx, %ebp
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_8
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_15
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_13
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_14
.LBB1_8: # %._crit_edge18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_15:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z11displayDataPiii, .Lfunc_end1-_Z11displayDataPiii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPiS_S_i # -- Begin function _Z18__device_stub__sumPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_S_i,@function
_Z18__device_stub__sumPiS_S_i: # @_Z18__device_stub__sumPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__sumPiS_S_i, .Lfunc_end2-_Z18__device_stub__sumPiS_S_i
.cfi_endproc
# -- End function
.globl _Z9matrixAddPiS_S_ii # -- Begin function _Z9matrixAddPiS_S_ii
.p2align 4, 0x90
.type _Z9matrixAddPiS_S_ii,@function
_Z9matrixAddPiS_S_ii: # @_Z9matrixAddPiS_S_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
imull %r8d, %r15d
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 1023(%r15), %eax
leal 2046(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3sumPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9matrixAddPiS_S_ii, .Lfunc_end3-_Z9matrixAddPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z3runv # -- Begin function _Z3runv
.p2align 4, 0x90
.type _Z3runv,@function
_Z3runv: # @_Z3runv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq %r15, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%rcx,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB4_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB4_1 Depth=1
incq %rax
addq $40, %rcx
cmpq $10, %rax
jne .LBB4_1
# %bb.4: # %.preheader.i18.preheader
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_5: # %.preheader.i18
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%rcx,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB4_6
# %bb.7: # %._crit_edge.i23
# in Loop: Header=BB4_5 Depth=1
incq %rax
addq $40, %rcx
cmpq $10, %rax
jne .LBB4_5
# %bb.8: # %_Z8initDataPiii.exit26
movq %rbx, %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $10, %ecx
movl $10, %r8d
callq _Z9matrixAddPiS_S_ii
movq %r14, %rdi
movl $10, %esi
movl $10, %edx
callq _Z11displayDataPiii
.Lfunc_end4:
.size _Z3runv, .Lfunc_end4-_Z3runv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z3runv
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z3sumPiS_S_i,@object # @_Z3sumPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3sumPiS_S_i
.p2align 3, 0x0
_Z3sumPiS_S_i:
.quad _Z18__device_stub__sumPiS_S_i
.size _Z3sumPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3sumPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z3sumPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_S_i
.globl _Z3sumPiS_S_i
.p2align 8
.type _Z3sumPiS_S_i,@function
_Z3sumPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_S_i, .Lfunc_end0-_Z3sumPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003ea09_00000000-6_suma_matriz_vector-mode.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10866:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10866:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initDataPiii
.type _Z8initDataPiii, @function
_Z8initDataPiii:
.LFB10859:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movl $0, %r9d
movl $0, %r8d
movslq %edx, %r10
jmp .L5
.L7:
movslq %r9d, %rcx
leaq (%rdi,%rcx,4), %rax
addq %r10, %rcx
leaq (%rdi,%rcx,4), %rcx
.L6:
movl $2, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r8d
addl %edx, %r9d
cmpl %r8d, %esi
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE10859:
.size _Z8initDataPiii, .-_Z8initDataPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z11displayDataPiii
.type _Z11displayDataPiii, @function
_Z11displayDataPiii:
.LFB10860:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
testl %esi, %esi
jle .L11
movl $0, %r15d
movl $0, %r14d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L12
.L24:
call _ZSt16__throw_bad_castv@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, 12(%rsp)
je .L11
.L12:
cmpl $0, 8(%rsp)
jle .L18
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %r12
.L13:
movl (%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
.L18:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L24
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %esi
jmp .L16
.L11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L20
movzbl 67(%rbx), %eax
.L21:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L20:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L21
.cfi_endproc
.LFE10860:
.size _Z11displayDataPiii, .-_Z11displayDataPiii
.globl _Z27__device_stub__Z3sumPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3sumPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3sumPiS_S_iPiS_S_i:
.LFB10888:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10888:
.size _Z27__device_stub__Z3sumPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3sumPiS_S_iPiS_S_i
.globl _Z3sumPiS_S_i
.type _Z3sumPiS_S_i, @function
_Z3sumPiS_S_i:
.LFB10889:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3sumPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10889:
.size _Z3sumPiS_S_i, .-_Z3sumPiS_S_i
.globl _Z9matrixAddPiS_S_ii
.type _Z9matrixAddPiS_S_ii, @function
_Z9matrixAddPiS_S_ii:
.LFB10861:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
imull %r8d, %ecx
movl %ecx, %ebp
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
leal 2046(%rbp), %eax
movl %ebp, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3sumPiS_S_iPiS_S_i
jmp .L35
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10861:
.size _Z9matrixAddPiS_S_ii, .-_Z9matrixAddPiS_S_ii
.globl _Z3runv
.type _Z3runv, @function
_Z3runv:
.LFB10862:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $400, %edi
call malloc@PLT
movq %rax, %r12
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $10, %edx
movl $10, %esi
movq %rbp, %rdi
call _Z8initDataPiii
movl $10, %edx
movl $10, %esi
movq %r12, %rdi
call _Z8initDataPiii
movl $10, %r8d
movl $10, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z9matrixAddPiS_S_ii
movl $10, %edx
movl $10, %esi
movq %rbx, %rdi
call _Z11displayDataPiii
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
.cfi_endproc
.LFE10862:
.size _Z3runv, .-_Z3runv
.globl main
.type main, @function
main:
.LFB10863:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z3runv
.cfi_endproc
.LFE10863:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3sumPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10891:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10891:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "suma_matriz_vector-mode.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initDataPiii # -- Begin function _Z8initDataPiii
.p2align 4, 0x90
.type _Z8initDataPiii,@function
_Z8initDataPiii: # @_Z8initDataPiii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge13
retq
.Lfunc_end0:
.size _Z8initDataPiii, .Lfunc_end0-_Z8initDataPiii
.cfi_endproc
# -- End function
.globl _Z11displayDataPiii # -- Begin function _Z11displayDataPiii
.p2align 4, 0x90
.type _Z11displayDataPiii,@function
_Z11displayDataPiii: # @_Z11displayDataPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_8
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r13d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
addl %ebx, %ebp
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_8
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_15
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_13
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_14
.LBB1_8: # %._crit_edge18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %eax
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_15:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z11displayDataPiii, .Lfunc_end1-_Z11displayDataPiii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPiS_S_i # -- Begin function _Z18__device_stub__sumPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_S_i,@function
_Z18__device_stub__sumPiS_S_i: # @_Z18__device_stub__sumPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__sumPiS_S_i, .Lfunc_end2-_Z18__device_stub__sumPiS_S_i
.cfi_endproc
# -- End function
.globl _Z9matrixAddPiS_S_ii # -- Begin function _Z9matrixAddPiS_S_ii
.p2align 4, 0x90
.type _Z9matrixAddPiS_S_ii,@function
_Z9matrixAddPiS_S_ii: # @_Z9matrixAddPiS_S_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
imull %r8d, %r15d
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 1023(%r15), %eax
leal 2046(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3sumPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9matrixAddPiS_S_ii, .Lfunc_end3-_Z9matrixAddPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z3runv # -- Begin function _Z3runv
.p2align 4, 0x90
.type _Z3runv,@function
_Z3runv: # @_Z3runv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq %r15, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%rcx,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB4_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB4_1 Depth=1
incq %rax
addq $40, %rcx
cmpq $10, %rax
jne .LBB4_1
# %bb.4: # %.preheader.i18.preheader
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_5: # %.preheader.i18
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%rcx,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB4_6
# %bb.7: # %._crit_edge.i23
# in Loop: Header=BB4_5 Depth=1
incq %rax
addq $40, %rcx
cmpq $10, %rax
jne .LBB4_5
# %bb.8: # %_Z8initDataPiii.exit26
movq %rbx, %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $10, %ecx
movl $10, %r8d
callq _Z9matrixAddPiS_S_ii
movq %r14, %rdi
movl $10, %esi
movl $10, %edx
callq _Z11displayDataPiii
.Lfunc_end4:
.size _Z3runv, .Lfunc_end4-_Z3runv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z3runv
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z3sumPiS_S_i,@object # @_Z3sumPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3sumPiS_S_i
.p2align 3, 0x0
_Z3sumPiS_S_i:
.quad _Z18__device_stub__sumPiS_S_i
.size _Z3sumPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3sumPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z3sumPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // nnIndex: B*N*K;
// nnCount: B*N;
// input: B*M*C;
// output: B*N*C (N>M)
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
}
__global__ void mean_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]/nnSize);
}
}
}
}
__global__ void weighted_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]*w;
}
}
}
}
__global__ void weighted_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]*w);
}
}
}
}
void meanInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, float* output)
{
mean_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, output);
//cudaDeviceSynchronize();
}
void meanInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, float* gradInput)
{
mean_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, gradInput);
}
void weightedInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
weighted_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, weight, output);
}
void weightedInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
weighted_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, weight, gradInput);
} | .file "tmpxft_000fd6e2_00000000-6_tf_unpool3d_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.type _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, @function
_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 224(%rsp), %rax
movq %rax, 24(%rsp)
movq 232(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, .-_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, @function
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, .-_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.globl _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.type _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf, @function
_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf, .-_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.globl _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.type _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, @function
_Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf:
.LFB2057:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 224(%rsp), %rax
movq %rax, 24(%rsp)
movq 232(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, .-_Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.globl _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.type _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, @function
_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, .-_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.globl _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.type _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf, @function
_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2028:
.size _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf, .-_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.globl _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.type _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, @function
_Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf:
.LFB2059:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, .-_Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.globl _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.type _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, @function
_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, .-_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.globl _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.type _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf, @function
_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2029:
.size _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf, .-_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.globl _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.type _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, @function
_Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf:
.LFB2061:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, .-_Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.globl _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.type _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, @function
_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, .-_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.globl _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.type _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf, @function
_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf:
.LFB2030:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L47
.cfi_endproc
.LFE2030:
.size _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf, .-_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf"
.align 8
.LC1:
.string "_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf"
.align 8
.LC2:
.string "_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf"
.align 8
.LC3:
.string "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // nnIndex: B*N*K;
// nnCount: B*N;
// input: B*M*C;
// output: B*N*C (N>M)
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
}
__global__ void mean_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]/nnSize);
}
}
}
}
__global__ void weighted_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]*w;
}
}
}
}
__global__ void weighted_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]*w);
}
}
}
}
void meanInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, float* output)
{
mean_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, output);
//cudaDeviceSynchronize();
}
void meanInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, float* gradInput)
{
mean_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, gradInput);
}
void weightedInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
weighted_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, weight, output);
}
void weightedInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
weighted_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, weight, gradInput);
} | #include <hip/hip_runtime.h>
// nnIndex: B*N*K;
// nnCount: B*N;
// input: B*M*C;
// output: B*N*C (N>M)
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
}
__global__ void mean_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]/nnSize);
}
}
}
}
__global__ void weighted_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]*w;
}
}
}
}
__global__ void weighted_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]*w);
}
}
}
}
void meanInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, float* output)
{
mean_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, output);
//cudaDeviceSynchronize();
}
void meanInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, float* gradInput)
{
mean_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, gradInput);
}
void weightedInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
weighted_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, weight, output);
}
void weightedInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
weighted_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, weight, gradInput);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// nnIndex: B*N*K;
// nnCount: B*N;
// input: B*M*C;
// output: B*N*C (N>M)
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
}
__global__ void mean_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]/nnSize);
}
}
}
}
__global__ void weighted_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]*w;
}
}
}
}
__global__ void weighted_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]*w);
}
}
}
}
void meanInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, float* output)
{
mean_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, output);
//cudaDeviceSynchronize();
}
void meanInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, float* gradInput)
{
mean_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, gradInput);
}
void weightedInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
weighted_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, weight, output);
}
void weightedInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
weighted_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, weight, gradInput);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 8
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf,@function
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_9
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x4
s_load_b32 s20, s[0:1], 0x38
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s13, s18, 31
s_mul_i32 s21, s18, s16
s_add_i32 s4, s18, s13
s_mul_i32 s22, s15, s16
s_xor_b32 s14, s4, s13
s_mul_i32 s23, s20, s16
v_cvt_f32_u32_e32 v1, s14
s_sub_i32 s4, 0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s4, v1
s_load_b256 s[4:11], s[0:1], 0x18
v_cmp_gt_i32_e64 s0, s21, v0
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v6, v1, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s24
s_add_i32 s15, s20, s15
s_add_i32 s22, s22, s23
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_3)
s_and_saveexec_b32 s24, s0
s_cbranch_execz .LBB0_2
s_load_b32 s1, s[2:3], 0xc
v_mov_b32_e32 v7, v0
s_mul_i32 s25, s15, s16
s_mul_i32 s26, s15, s17
s_mul_i32 s27, s25, s18
s_mov_b32 s29, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s28, s1, 0xffff
s_branch .LBB0_6
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s30
v_add_nc_u32_e32 v7, s28, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s21, v7
s_or_b32 s29, vcc_lo, s29
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_2
.LBB0_6:
v_ashrrev_i32_e32 v1, 31, v7
s_mov_b32 s30, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v7, v1
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v6
v_mul_lo_u32 v4, v3, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v3
v_subrev_nc_u32_e32 v5, s14, v2
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v3, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_xor_b32_e32 v3, s13, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v4
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v4, v5, vcc_lo
v_xor_b32_e32 v5, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v5, v3
v_add_nc_u32_e32 v1, s25, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v8, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v8
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v1, s27, v7
v_add_nc_u32_e32 v5, s22, v5
v_mul_lo_u32 v10, v4, s18
s_mov_b32 s31, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_sub_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mul_lo_u32 v3, s19, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
global_load_b32 v9, v[1:2], off
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_sub_nc_u32_e32 v3, v7, v10
v_cvt_f32_i32_e32 v10, v8
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
global_load_b32 v11, v[4:5], off
v_add_nc_u32_e32 v8, -1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s1, 0, v8
s_or_b32 s31, s1, s31
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v13, s26, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, s18, v[3:4]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v12, null, v10, v10, v11
v_div_scale_f32 v15, vcc_lo, v11, v10, v11
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v12, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v12, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v14, v15
v_div_fmas_f32 v12, v12, v13, v14
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v11, v12, v10, v11
v_add_f32_e32 v9, v9, v11
global_store_b32 v[1:2], v9, off
s_and_not1_b32 exec_lo, exec_lo, s31
s_cbranch_execnz .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, .Lfunc_end0-_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.globl _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.p2align 8
.type _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf,@function
_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf:
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB1_11
s_load_b128 s[16:19], s[0:1], 0x4
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s13, s18, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s18, s13
s_xor_b32 s14, s4, s13
s_load_b256 s[4:11], s[0:1], 0x18
v_cvt_f32_u32_e32 v1, s14
s_sub_i32 s20, 0, s14
s_load_b32 s1, s[0:1], 0x38
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s20, v1
s_mul_i32 s20, s18, s16
v_cmp_gt_i32_e64 s0, s20, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v8, v1, v2
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s21
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s1, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB1_11
.LBB1_3:
s_delay_alu instid0(VALU_DEP_3)
s_and_saveexec_b32 s21, s0
s_cbranch_execz .LBB1_2
s_load_b32 s25, s[2:3], 0xc
v_mov_b32_e32 v9, v0
s_mul_i32 s22, s15, s16
s_mul_i32 s23, s15, s17
s_mul_i32 s24, s22, s18
s_mov_b32 s26, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s25, s25, 0xffff
s_branch .LBB1_6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s27
v_add_nc_u32_e32 v9, s25, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s20, v9
s_or_b32 s26, vcc_lo, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB1_2
.LBB1_6:
v_ashrrev_i32_e32 v1, 31, v9
s_mov_b32 s27, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v9, v1
v_xor_b32_e32 v2, v2, v1
v_xor_b32_e32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v8
v_mul_lo_u32 v4, v3, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v3
v_subrev_nc_u32_e32 v5, s14, v2
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v5
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s14, v2
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s22, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v10, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v10
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v4, s24, v9
v_mul_lo_u32 v6, v3, s18
v_mul_lo_u32 v11, v1, s19
v_cvt_f32_i32_e32 v12, v10
s_mov_b32 s28, 0
v_ashrrev_i32_e32 v5, 31, v4
s_mov_b32 s29, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v9, v6
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB1_8:
v_add_nc_u32_e32 v4, s29, v11
s_mov_b32 s30, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v13, null, v12, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v14, v13
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v13, v14, 1.0
v_dual_fmac_f32 v14, v15, v14 :: v_dual_add_nc_u32 v7, s23, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v7, s18, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_div_scale_f32 v15, vcc_lo, v6, v12, v6
global_load_b32 v7, v[4:5], off
v_mul_f32_e32 v16, v15, v14
v_fma_f32 v17, -v13, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v17, v14
v_fma_f32 v13, -v13, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v13, v13, v14, v16
v_div_fixup_f32 v13, v13, v12, v6
.LBB1_9:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v7, v13
global_atomic_cmpswap_b32 v6, v[4:5], v[6:7], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v6, v7
v_mov_b32_e32 v7, v6
s_or_b32 s30, vcc_lo, s30
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s30
s_cbranch_execnz .LBB1_9
s_or_b32 exec_lo, exec_lo, s30
s_add_i32 s29, s29, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s29, v10
s_or_b32 s28, vcc_lo, s28
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execnz .LBB1_8
s_branch .LBB1_5
.LBB1_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 31
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, .Lfunc_end1-_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.globl _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.p2align 8
.type _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf,@function
_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf:
s_load_b32 s14, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB2_9
s_load_b128 s[16:19], s[0:1], 0x4
s_add_u32 s2, s0, 64
s_addc_u32 s3, s1, 0
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x38
s_load_b32 s22, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_ashr_i32 s20, s18, 31
s_mul_i32 s23, s18, s16
s_add_i32 s4, s18, s20
v_cmp_gt_i32_e32 vcc_lo, s23, v0
s_xor_b32 s21, s4, s20
s_mul_i32 s24, s15, s16
v_cvt_f32_u32_e32 v1, s21
s_sub_i32 s4, 0, s21
s_mul_i32 s25, s22, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v1
s_load_b256 s[4:11], s[0:1], 0x18
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v8, v1, v2
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s26
s_add_i32 s15, s22, s15
s_add_i32 s24, s24, s25
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB2_9
.LBB2_3:
s_and_saveexec_b32 s26, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b32 s0, s[2:3], 0xc
v_mov_b32_e32 v9, v0
s_mul_i32 s27, s15, s16
s_mul_i32 s28, s15, s17
s_mul_i32 s29, s27, s18
s_mov_b32 s31, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s30, s0, 0xffff
s_branch .LBB2_6
.LBB2_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s33
v_add_nc_u32_e32 v9, s30, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s23, v9
s_or_b32 s31, s0, s31
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s31
s_cbranch_execz .LBB2_2
.LBB2_6:
v_ashrrev_i32_e32 v1, 31, v9
s_mov_b32 s33, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v9, v1
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v8
v_mul_lo_u32 v4, v3, s21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v3
v_subrev_nc_u32_e32 v5, s21, v2
v_cmp_le_u32_e64 s0, s21, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v3, v4, s0
v_cndmask_b32_e64 v2, v2, v5, s0
v_xor_b32_e32 v3, s20, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v4
v_cmp_le_u32_e64 s0, s21, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, v4, v5, s0
v_xor_b32_e32 v5, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v5, v3
v_add_nc_u32_e32 v1, s27, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s6, v1
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
global_load_b32 v10, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v10
s_cbranch_execz .LBB2_5
v_add_nc_u32_e32 v1, s29, v9
v_add_nc_u32_e32 v5, s24, v5
s_mov_b32 s34, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_sub_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mul_lo_u32 v5, s19, v3
v_mul_lo_u32 v3, v4, s18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s12, v1
v_add_co_ci_u32_e64 v2, s0, s13, v2, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_sub_nc_u32_e32 v3, v9, v3
global_load_b32 v11, v[1:2], off
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v6
v_add_co_ci_u32_e64 v5, s0, s5, v7, s0
v_add_co_u32 v6, s0, s10, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s11, v7, s0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_8:
global_load_b32 v12, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v14, s28, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, s18, v[3:4]
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, s0, s8, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s9, v13, s0
v_add_co_u32 v4, s0, v4, 4
global_load_b32 v14, v[6:7], off
global_load_b32 v12, v[12:13], off
v_add_nc_u32_e32 v10, -1, v10
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
v_add_co_u32 v6, s0, v6, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, v14, v12
v_cmp_eq_u32_e64 s1, 0, v10
global_store_b32 v[1:2], v11, off
s_or_b32 s34, s1, s34
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s34
s_cbranch_execnz .LBB2_8
s_branch .LBB2_5
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 35
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, .Lfunc_end2-_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.globl _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.p2align 8
.type _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf,@function
_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf:
s_load_b32 s14, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB3_11
s_load_b128 s[16:19], s[0:1], 0x4
s_add_u32 s2, s0, 64
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s20, s18, 31
s_mul_i32 s22, s18, s16
s_add_i32 s4, s18, s20
v_cmp_gt_i32_e32 vcc_lo, s22, v0
s_xor_b32 s21, s4, s20
s_load_b256 s[4:11], s[0:1], 0x18
v_cvt_f32_u32_e32 v1, s21
s_sub_i32 s12, 0, s21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s12, v1
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x38
s_load_b32 s1, s[0:1], 0x40
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v8, v1, v2
s_branch .LBB3_3
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s23
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s1, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB3_11
.LBB3_3:
s_and_saveexec_b32 s23, vcc_lo
s_cbranch_execz .LBB3_2
s_load_b32 s0, s[2:3], 0xc
v_mov_b32_e32 v9, v0
s_mul_i32 s24, s15, s16
s_mul_i32 s25, s15, s17
s_mul_i32 s26, s24, s18
s_mov_b32 s28, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s27, s0, 0xffff
s_branch .LBB3_6
.LBB3_5:
s_or_b32 exec_lo, exec_lo, s29
v_add_nc_u32_e32 v9, s27, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s22, v9
s_or_b32 s28, s0, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execz .LBB3_2
.LBB3_6:
v_ashrrev_i32_e32 v1, 31, v9
s_mov_b32 s29, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v9, v1
v_xor_b32_e32 v2, v2, v1
v_xor_b32_e32 v1, s20, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v8
v_mul_lo_u32 v4, v3, s21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v3
v_subrev_nc_u32_e32 v5, s21, v2
v_cmp_le_u32_e64 s0, s21, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cndmask_b32_e64 v2, v2, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v3
v_cmp_le_u32_e64 s0, s21, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v3, v4, s0
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v2, v1
v_add_nc_u32_e32 v1, s24, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s6, v4
v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
global_load_b32 v10, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v10
s_cbranch_execz .LBB3_5
v_add_nc_u32_e32 v4, s26, v9
v_mul_lo_u32 v6, v3, s18
v_mul_lo_u32 v11, v1, s19
s_mov_b32 s30, 0
s_mov_b32 s31, 0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v9, v6
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s8, v2
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
.LBB3_8:
v_add_nc_u32_e32 v4, s31, v11
s_mov_b32 s33, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v4
v_add_co_ci_u32_e64 v7, s0, s5, v5, s0
v_add_co_u32 v4, s0, s10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s11, v5, s0
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v12, s25, v6
v_mad_u64_u32 v[6:7], null, v12, s18, v[1:2]
global_load_b32 v12, v[4:5], off
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v4, s0, s12, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s13, v7, s0
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v12, v12, v6
.LBB3_9:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v12
global_atomic_cmpswap_b32 v6, v[4:5], v[6:7], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v6, v7
v_mov_b32_e32 v7, v6
s_or_b32 s33, s0, s33
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s33
s_cbranch_execnz .LBB3_9
s_or_b32 exec_lo, exec_lo, s33
s_add_i32 s31, s31, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s31, v10
s_or_b32 s30, s0, s30
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s30
s_cbranch_execnz .LBB3_8
s_branch .LBB3_5
.LBB3_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 34
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, .Lfunc_end3-_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.private_segment_fixed_size: 0
.sgpr_count: 33
.sgpr_spill_count: 0
.symbol: _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 37
.sgpr_spill_count: 0
.symbol: _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// nnIndex: B*N*K;
// nnCount: B*N;
// input: B*M*C;
// output: B*N*C (N>M)
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
}
__global__ void mean_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex,
const int* nnCount, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]/nnSize);
}
}
}
}
__global__ void weighted_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]*w;
}
}
}
}
__global__ void weighted_interpolate_backward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
float w = weight[i*N*K+n*K+k];
atomicAdd(&gradInput[i*M*C+m*C+c],gradOutput[i*N*C+j]*w);
}
}
}
}
void meanInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, float* output)
{
mean_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, output);
//cudaDeviceSynchronize();
}
void meanInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, float* gradInput)
{
mean_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, gradInput);
}
void weightedInterpolateLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* input, const float* weight, float* output)
{
weighted_interpolate_forward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, input, weight, output);
}
void weightedInterpolateGradLauncher(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount,
const float* gradOutput, const float* weight, float* gradInput)
{
weighted_interpolate_backward<<<B,1024>>>(B, N, M, C, K, nnIndex, nnCount, gradOutput, weight, gradInput);
} | .text
.file "tf_unpool3d_gpu.hip"
.globl _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf # -- Begin function _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf,@function
_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf: # @_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf, .Lfunc_end0-_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf # -- Begin function _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf,@function
_Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf: # @_Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf, .Lfunc_end1-_Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf # -- Begin function _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf,@function
_Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf: # @_Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, .Lfunc_end2-_Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.globl _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf # -- Begin function _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf,@function
_Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf: # @_Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, .Lfunc_end3-_Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.globl _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf # -- Begin function _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf,@function
_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf: # @_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf, .Lfunc_end4-_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf # -- Begin function _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf,@function
_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf: # @_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf, .Lfunc_end5-_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf # -- Begin function _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf,@function
_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf: # @_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf, .Lfunc_end6-_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.globl _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf # -- Begin function _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf,@function
_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf: # @_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf, .Lfunc_end7-_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf,@object # @_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .rodata,"a",@progbits
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 3, 0x0
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.quad _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, 8
.type _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf,@object # @_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.globl _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.p2align 3, 0x0
_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf:
.quad _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.size _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, 8
.type _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf,@object # @_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.globl _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.p2align 3, 0x0
_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf:
.quad _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.size _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, 8
.type _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf,@object # @_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.globl _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.p2align 3, 0x0
_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf:
.quad _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.size _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.size .L__unnamed_1, 45
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf"
.size .L__unnamed_2, 46
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf"
.size .L__unnamed_3, 52
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf"
.size .L__unnamed_4, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fd6e2_00000000-6_tf_unpool3d_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.type _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, @function
_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 224(%rsp), %rax
movq %rax, 24(%rsp)
movq 232(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, .-_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, @function
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, .-_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.globl _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.type _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf, @function
_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf, .-_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.globl _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.type _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, @function
_Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf:
.LFB2057:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 224(%rsp), %rax
movq %rax, 24(%rsp)
movq 232(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, .-_Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.globl _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.type _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, @function
_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, .-_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.globl _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.type _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf, @function
_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z59__device_stub__Z25mean_interpolate_backwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2028:
.size _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf, .-_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.globl _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.type _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, @function
_Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf:
.LFB2059:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, .-_Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.globl _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.type _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, @function
_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, .-_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.globl _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.type _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf, @function
_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z65__device_stub__Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2029:
.size _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf, .-_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.globl _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.type _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, @function
_Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf:
.LFB2061:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf, .-_Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
.globl _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.type _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, @function
_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, .-_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.globl _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.type _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf, @function
_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf:
.LFB2030:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z66__device_stub__Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_PfiiiiiPKiS0_PKfS2_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L47
.cfi_endproc
.LFE2030:
.size _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf, .-_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf"
.align 8
.LC1:
.string "_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf"
.align 8
.LC2:
.string "_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf"
.align 8
.LC3:
.string "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tf_unpool3d_gpu.hip"
.globl _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf # -- Begin function _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf,@function
_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf: # @_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf, .Lfunc_end0-_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf # -- Begin function _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf,@function
_Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf: # @_Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf, .Lfunc_end1-_Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf # -- Begin function _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf,@function
_Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf: # @_Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, .Lfunc_end2-_Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.globl _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf # -- Begin function _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf,@function
_Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf: # @_Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, .Lfunc_end3-_Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.globl _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf # -- Begin function _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf,@function
_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf: # @_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf, .Lfunc_end4-_Z23meanInterpolateLauncheriiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf # -- Begin function _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf,@function
_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf: # @_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf, .Lfunc_end5-_Z27meanInterpolateGradLauncheriiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.globl _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf # -- Begin function _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf,@function
_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf: # @_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf, .Lfunc_end6-_Z27weightedInterpolateLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.globl _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf # -- Begin function _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.p2align 4, 0x90
.type _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf,@function
_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf: # @_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf, .Lfunc_end7-_Z31weightedInterpolateGradLauncheriiiiiPKiS0_PKfS2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf,@object # @_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .rodata,"a",@progbits
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 3, 0x0
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.quad _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, 8
.type _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf,@object # @_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.globl _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.p2align 3, 0x0
_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf:
.quad _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.size _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf, 8
.type _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf,@object # @_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.globl _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.p2align 3, 0x0
_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf:
.quad _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.size _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf, 8
.type _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf,@object # @_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.globl _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.p2align 3, 0x0
_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf:
.quad _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.size _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.size .L__unnamed_1, 45
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf"
.size .L__unnamed_2, 46
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf"
.size .L__unnamed_3, 52
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf"
.size .L__unnamed_4, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z40__device_stub__mean_interpolate_backwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z43__device_stub__weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym _Z44__device_stub__weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z25mean_interpolate_backwardiiiiiPKiS0_PKfPf
.addrsig_sym _Z28weighted_interpolate_forwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym _Z29weighted_interpolate_backwardiiiiiPKiS0_PKfS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define SIZE 1024
#define START_SCALE 1.5f
#define MAXIT 256
#define C_RE -0.8f
#define C_IM 0.156f
#define ZOOM 200
//======================================================================
/*This function checks whether a point
belongs to the filled julia set. It
returns 0 if the value 'escaped', and
one if the maximal numer of iterations
has been reached. It is a function on the
device, but it can't be called like a
kernel from the host. It is used by the
kernel 'construct_julia_set' below. Note that
the kernel has the 'global' attribute rather
than the 'device' attribute.*/
__device__ int julia( int i, int j, float scale)
{
//rescale grid to actual scale
float x = scale * (float)(SIZE/2 - i)/(SIZE/2);
float y = scale * (float)(SIZE/2 - j)/(SIZE/2);
//real and imaginary part of point in question
float z_re=x;
float z_im=y;
float z_re_old;
//compute Z(n+1) = Zn^2 + C
for (int k=0; k<MAXIT;k++)
{
z_re_old = z_re; //store old real value
z_re =(z_re*z_re-z_im*z_im) + (C_RE); //compute Re(Z(n+1))
z_im = 2.0f*z_re_old*z_im + (C_IM); //compute Im(Z(n+1))
if ( sqrt(z_re*z_re+z_im*z_im) > SIZE) //check if point escaped
{
return 0; //point escaped
}
}
return 1; //point in set
}
//======================================================================
/* This function uses the one defined above
to construct an array called 'set' with ones and zeroes,
defining the elements of the julia set. This is the
kernel function to be called from the host and exectued
on the device. It thus carries the 'global' attribute.*/
__global__ void construct_julia_set( int *set, float scale)
{
// int i = blockIdx.x*blockDim.x + threadIdx.x; //determine thread id i
// int j = blockIdx.y*blockDim.y + threadIdx.y; //determine thread id j
int i = blockIdx.x;
int j = blockIdx.y;
int pos = i + j * SIZE; //remap to 1-dim array
set[pos] = julia( i, j, scale); //fill the set
}
//======================================================================
int main( void )
{
using namespace std;
int set[SIZE*SIZE]; //the result array on the host
int *set_d; //the result array on the device
int written; //aux variable for writing file
int num; //numbering of output file
float x; //Re part in complex Z plane
float y; //Im part in complez Z plane
float scale; //initial scale for zoom
char buffer[32]; //buffer for filenames
FILE *out; //output file
//dim3 threadsPerBlock(16,16); //number of threads per block and grid size
//dim3 numBlocks(SIZE/threadsPerBlock.x,SIZE/threadsPerBlock.y);
dim3 grid(SIZE,SIZE);
for(int k=0; k<SIZE*SIZE; k++)
{
set[k] = 0;
}
cudaMalloc(&set_d, SIZE*SIZE*sizeof(int)); //allocate memory for set on device
/*The variable 'written' allows us to introduce a newline
after each row that has been written to the outpur file.
This allows for more freedom in printing the set using
gnuplot.*/
written=0; //reset 'written' value
for( int k=0; k<ZOOM; k++ ) //k...number of zoom slices to produce
{ //vary scale for zoom
scale = START_SCALE *(400.0f-(float)k)/400.0f + 0.01;
cudaMemcpy(set_d, set, SIZE*SIZE*sizeof(int), cudaMemcpyHostToDevice); //init set on device
// construct_julia_set<<<numBlocks,threadsPerBlock>>>(set_d, scale); //construct julia set on GPU
construct_julia_set<<<grid,1>>>(set_d, scale); //construct julia set on GPU
cudaDeviceSynchronize();
cudaMemcpy(set, set_d, SIZE*SIZE*sizeof(int), cudaMemcpyDeviceToHost); //copy resultto host
num = k; //out: 'julia_000.dat', 'julia_001.dat',...
snprintf(buffer, sizeof(char)*32, "julia_%03i.dat", num);
out = fopen( buffer, "wt" ); //write in text mode (wt)
for (int i=0; i<SIZE; i++) //actual grid values x and y
{
x = scale * (float)(SIZE/2 - i)/(SIZE/2);
for (int j=0; j<SIZE; j++)
{
y = scale * (float)(SIZE/2 - j)/(SIZE/2);
int pos = i + j * SIZE; //position in array
if(set[pos]==1) //write only if part of set
{
fprintf(out,"%f %f \n",x,y);
written = 1; //set written to 1
}
}//end inner grid loop (j)
if( written == 1 )
{
fprintf(out,"\n"); //add newline if row content not empty
}
written=0; //reset written value
}//end outer grid loop (i)
fclose(out); //close file
}//end zoom loop (k)
cudaFree( set_d ); //deallocate
} | .file "tmpxft_00151588_00000000-6_julia_set.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5juliaiif
.type _Z5juliaiif, @function
_Z5juliaiif:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5juliaiif, .-_Z5juliaiif
.globl _Z40__device_stub__Z19construct_julia_setPifPif
.type _Z40__device_stub__Z19construct_julia_setPifPif, @function
_Z40__device_stub__Z19construct_julia_setPifPif:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19construct_julia_setPif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z19construct_julia_setPifPif, .-_Z40__device_stub__Z19construct_julia_setPifPif
.globl _Z19construct_julia_setPif
.type _Z19construct_julia_setPif, @function
_Z19construct_julia_setPif:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19construct_julia_setPifPif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19construct_julia_setPif, .-_Z19construct_julia_setPif
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "julia_%03i.dat"
.LC4:
.string "wt"
.LC6:
.string "%f %f \n"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194360
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $120, %rsp
.cfi_def_cfa_offset 4194480
movq %fs:40, %rax
movq %rax, 4194408(%rsp)
xorl %eax, %eax
movl $1024, 40(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 8(%rsp)
leaq 4194368(%rsp), %rdx
.L14:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, 20(%rsp)
leaq 64(%rsp), %rax
movq %rax, 24(%rsp)
jmp .L20
.L31:
movss 4(%rsp), %xmm0
movq 32(%rsp), %rdi
call _Z40__device_stub__Z19construct_julia_setPifPif
jmp .L15
.L16:
addq $4096, %rbp
subl $1, %ebx
cmpl $-512, %ebx
je .L27
.L17:
movl 0(%rbp), %r12d
cmpl $1, %r12d
jne .L16
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
mulss 4(%rsp), %xmm1
mulss .LC5(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
cvtss2sd %xmm1, %xmm1
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $2, %eax
call __fprintf_chk@PLT
movl %r12d, %eax
jmp .L16
.L27:
cmpl $1, %eax
je .L28
.L18:
addq $1, %r15
cmpq $1024, %r15
je .L29
.L19:
movl $512, %eax
subl %r15d, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss 4(%rsp), %xmm0
mulss .LC5(%rip), %xmm0
movss %xmm0, 16(%rsp)
movq 8(%rsp), %rax
leaq (%rax,%r15,4), %rbp
movl $512, %ebx
movl $0, %eax
jmp .L17
.L28:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L29:
movq %r13, %rdi
call fclose@PLT
addl $1, 20(%rsp)
movl 20(%rsp), %eax
cmpl $200, %eax
je .L30
.L20:
pxor %xmm1, %xmm1
cvtsi2ssl 20(%rsp), %xmm1
movss .LC0(%rip), %xmm0
subss %xmm1, %xmm0
mulss .LC1(%rip), %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC2(%rip), %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 4(%rsp)
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L15:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4194368(%rsp), %rbx
movl 20(%rsp), %r9d
leaq .LC3(%rip), %r8
movl $32, %ecx
movl $2, %edx
movl $32, %esi
movq %rbx, %rdi
movl $0, %eax
call __snprintf_chk@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %r15d
leaq .LC6(%rip), %r14
jmp .L19
.L30:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 4194408(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $4194424, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z19construct_julia_setPif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z19construct_julia_setPif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1137180672
.align 4
.LC1:
.long 1069547520
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 1202590843
.long 1065646817
.section .rodata.cst4
.align 4
.LC5:
.long 989855744
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define SIZE 1024
#define START_SCALE 1.5f
#define MAXIT 256
#define C_RE -0.8f
#define C_IM 0.156f
#define ZOOM 200
//======================================================================
/*This function checks whether a point
belongs to the filled julia set. It
returns 0 if the value 'escaped', and
one if the maximal numer of iterations
has been reached. It is a function on the
device, but it can't be called like a
kernel from the host. It is used by the
kernel 'construct_julia_set' below. Note that
the kernel has the 'global' attribute rather
than the 'device' attribute.*/
__device__ int julia( int i, int j, float scale)
{
//rescale grid to actual scale
float x = scale * (float)(SIZE/2 - i)/(SIZE/2);
float y = scale * (float)(SIZE/2 - j)/(SIZE/2);
//real and imaginary part of point in question
float z_re=x;
float z_im=y;
float z_re_old;
//compute Z(n+1) = Zn^2 + C
for (int k=0; k<MAXIT;k++)
{
z_re_old = z_re; //store old real value
z_re =(z_re*z_re-z_im*z_im) + (C_RE); //compute Re(Z(n+1))
z_im = 2.0f*z_re_old*z_im + (C_IM); //compute Im(Z(n+1))
if ( sqrt(z_re*z_re+z_im*z_im) > SIZE) //check if point escaped
{
return 0; //point escaped
}
}
return 1; //point in set
}
//======================================================================
/* This function uses the one defined above
to construct an array called 'set' with ones and zeroes,
defining the elements of the julia set. This is the
kernel function to be called from the host and exectued
on the device. It thus carries the 'global' attribute.*/
__global__ void construct_julia_set( int *set, float scale)
{
// int i = blockIdx.x*blockDim.x + threadIdx.x; //determine thread id i
// int j = blockIdx.y*blockDim.y + threadIdx.y; //determine thread id j
int i = blockIdx.x;
int j = blockIdx.y;
int pos = i + j * SIZE; //remap to 1-dim array
set[pos] = julia( i, j, scale); //fill the set
}
//======================================================================
int main( void )
{
using namespace std;
int set[SIZE*SIZE]; //the result array on the host
int *set_d; //the result array on the device
int written; //aux variable for writing file
int num; //numbering of output file
float x; //Re part in complex Z plane
float y; //Im part in complez Z plane
float scale; //initial scale for zoom
char buffer[32]; //buffer for filenames
FILE *out; //output file
//dim3 threadsPerBlock(16,16); //number of threads per block and grid size
//dim3 numBlocks(SIZE/threadsPerBlock.x,SIZE/threadsPerBlock.y);
dim3 grid(SIZE,SIZE);
for(int k=0; k<SIZE*SIZE; k++)
{
set[k] = 0;
}
cudaMalloc(&set_d, SIZE*SIZE*sizeof(int)); //allocate memory for set on device
/*The variable 'written' allows us to introduce a newline
after each row that has been written to the outpur file.
This allows for more freedom in printing the set using
gnuplot.*/
written=0; //reset 'written' value
for( int k=0; k<ZOOM; k++ ) //k...number of zoom slices to produce
{ //vary scale for zoom
scale = START_SCALE *(400.0f-(float)k)/400.0f + 0.01;
cudaMemcpy(set_d, set, SIZE*SIZE*sizeof(int), cudaMemcpyHostToDevice); //init set on device
// construct_julia_set<<<numBlocks,threadsPerBlock>>>(set_d, scale); //construct julia set on GPU
construct_julia_set<<<grid,1>>>(set_d, scale); //construct julia set on GPU
cudaDeviceSynchronize();
cudaMemcpy(set, set_d, SIZE*SIZE*sizeof(int), cudaMemcpyDeviceToHost); //copy resultto host
num = k; //out: 'julia_000.dat', 'julia_001.dat',...
snprintf(buffer, sizeof(char)*32, "julia_%03i.dat", num);
out = fopen( buffer, "wt" ); //write in text mode (wt)
for (int i=0; i<SIZE; i++) //actual grid values x and y
{
x = scale * (float)(SIZE/2 - i)/(SIZE/2);
for (int j=0; j<SIZE; j++)
{
y = scale * (float)(SIZE/2 - j)/(SIZE/2);
int pos = i + j * SIZE; //position in array
if(set[pos]==1) //write only if part of set
{
fprintf(out,"%f %f \n",x,y);
written = 1; //set written to 1
}
}//end inner grid loop (j)
if( written == 1 )
{
fprintf(out,"\n"); //add newline if row content not empty
}
written=0; //reset written value
}//end outer grid loop (i)
fclose(out); //close file
}//end zoom loop (k)
cudaFree( set_d ); //deallocate
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIZE 1024
#define START_SCALE 1.5f
#define MAXIT 256
#define C_RE -0.8f
#define C_IM 0.156f
#define ZOOM 200
//======================================================================
/*This function checks whether a point
belongs to the filled julia set. It
returns 0 if the value 'escaped', and
one if the maximal numer of iterations
has been reached. It is a function on the
device, but it can't be called like a
kernel from the host. It is used by the
kernel 'construct_julia_set' below. Note that
the kernel has the 'global' attribute rather
than the 'device' attribute.*/
__device__ int julia( int i, int j, float scale)
{
//rescale grid to actual scale
float x = scale * (float)(SIZE/2 - i)/(SIZE/2);
float y = scale * (float)(SIZE/2 - j)/(SIZE/2);
//real and imaginary part of point in question
float z_re=x;
float z_im=y;
float z_re_old;
//compute Z(n+1) = Zn^2 + C
for (int k=0; k<MAXIT;k++)
{
z_re_old = z_re; //store old real value
z_re =(z_re*z_re-z_im*z_im) + (C_RE); //compute Re(Z(n+1))
z_im = 2.0f*z_re_old*z_im + (C_IM); //compute Im(Z(n+1))
if ( sqrt(z_re*z_re+z_im*z_im) > SIZE) //check if point escaped
{
return 0; //point escaped
}
}
return 1; //point in set
}
//======================================================================
/* This function uses the one defined above
to construct an array called 'set' with ones and zeroes,
defining the elements of the julia set. This is the
kernel function to be called from the host and exectued
on the device. It thus carries the 'global' attribute.*/
__global__ void construct_julia_set( int *set, float scale)
{
// int i = blockIdx.x*blockDim.x + threadIdx.x; //determine thread id i
// int j = blockIdx.y*blockDim.y + threadIdx.y; //determine thread id j
int i = blockIdx.x;
int j = blockIdx.y;
int pos = i + j * SIZE; //remap to 1-dim array
set[pos] = julia( i, j, scale); //fill the set
}
//======================================================================
int main( void )
{
using namespace std;
int set[SIZE*SIZE]; //the result array on the host
int *set_d; //the result array on the device
int written; //aux variable for writing file
int num; //numbering of output file
float x; //Re part in complex Z plane
float y; //Im part in complez Z plane
float scale; //initial scale for zoom
char buffer[32]; //buffer for filenames
FILE *out; //output file
//dim3 threadsPerBlock(16,16); //number of threads per block and grid size
//dim3 numBlocks(SIZE/threadsPerBlock.x,SIZE/threadsPerBlock.y);
dim3 grid(SIZE,SIZE);
for(int k=0; k<SIZE*SIZE; k++)
{
set[k] = 0;
}
hipMalloc(&set_d, SIZE*SIZE*sizeof(int)); //allocate memory for set on device
/*The variable 'written' allows us to introduce a newline
after each row that has been written to the outpur file.
This allows for more freedom in printing the set using
gnuplot.*/
written=0; //reset 'written' value
for( int k=0; k<ZOOM; k++ ) //k...number of zoom slices to produce
{ //vary scale for zoom
scale = START_SCALE *(400.0f-(float)k)/400.0f + 0.01;
hipMemcpy(set_d, set, SIZE*SIZE*sizeof(int), hipMemcpyHostToDevice); //init set on device
// construct_julia_set<<<numBlocks,threadsPerBlock>>>(set_d, scale); //construct julia set on GPU
construct_julia_set<<<grid,1>>>(set_d, scale); //construct julia set on GPU
hipDeviceSynchronize();
hipMemcpy(set, set_d, SIZE*SIZE*sizeof(int), hipMemcpyDeviceToHost); //copy resultto host
num = k; //out: 'julia_000.dat', 'julia_001.dat',...
snprintf(buffer, sizeof(char)*32, "julia_%03i.dat", num);
out = fopen( buffer, "wt" ); //write in text mode (wt)
for (int i=0; i<SIZE; i++) //actual grid values x and y
{
x = scale * (float)(SIZE/2 - i)/(SIZE/2);
for (int j=0; j<SIZE; j++)
{
y = scale * (float)(SIZE/2 - j)/(SIZE/2);
int pos = i + j * SIZE; //position in array
if(set[pos]==1) //write only if part of set
{
fprintf(out,"%f %f \n",x,y);
written = 1; //set written to 1
}
}//end inner grid loop (j)
if( written == 1 )
{
fprintf(out,"\n"); //add newline if row content not empty
}
written=0; //reset written value
}//end outer grid loop (i)
fclose(out); //close file
}//end zoom loop (k)
hipFree( set_d ); //deallocate
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIZE 1024
#define START_SCALE 1.5f
#define MAXIT 256
#define C_RE -0.8f
#define C_IM 0.156f
#define ZOOM 200
//======================================================================
/*This function checks whether a point
belongs to the filled julia set. It
returns 0 if the value 'escaped', and
one if the maximal numer of iterations
has been reached. It is a function on the
device, but it can't be called like a
kernel from the host. It is used by the
kernel 'construct_julia_set' below. Note that
the kernel has the 'global' attribute rather
than the 'device' attribute.*/
__device__ int julia( int i, int j, float scale)
{
//rescale grid to actual scale
float x = scale * (float)(SIZE/2 - i)/(SIZE/2);
float y = scale * (float)(SIZE/2 - j)/(SIZE/2);
//real and imaginary part of point in question
float z_re=x;
float z_im=y;
float z_re_old;
//compute Z(n+1) = Zn^2 + C
for (int k=0; k<MAXIT;k++)
{
z_re_old = z_re; //store old real value
z_re =(z_re*z_re-z_im*z_im) + (C_RE); //compute Re(Z(n+1))
z_im = 2.0f*z_re_old*z_im + (C_IM); //compute Im(Z(n+1))
if ( sqrt(z_re*z_re+z_im*z_im) > SIZE) //check if point escaped
{
return 0; //point escaped
}
}
return 1; //point in set
}
//======================================================================
/* This function uses the one defined above
to construct an array called 'set' with ones and zeroes,
defining the elements of the julia set. This is the
kernel function to be called from the host and exectued
on the device. It thus carries the 'global' attribute.*/
__global__ void construct_julia_set( int *set, float scale)
{
// int i = blockIdx.x*blockDim.x + threadIdx.x; //determine thread id i
// int j = blockIdx.y*blockDim.y + threadIdx.y; //determine thread id j
int i = blockIdx.x;
int j = blockIdx.y;
int pos = i + j * SIZE; //remap to 1-dim array
set[pos] = julia( i, j, scale); //fill the set
}
//======================================================================
int main( void )
{
using namespace std;
int set[SIZE*SIZE]; //the result array on the host
int *set_d; //the result array on the device
int written; //aux variable for writing file
int num; //numbering of output file
float x; //Re part in complex Z plane
float y; //Im part in complez Z plane
float scale; //initial scale for zoom
char buffer[32]; //buffer for filenames
FILE *out; //output file
//dim3 threadsPerBlock(16,16); //number of threads per block and grid size
//dim3 numBlocks(SIZE/threadsPerBlock.x,SIZE/threadsPerBlock.y);
dim3 grid(SIZE,SIZE);
for(int k=0; k<SIZE*SIZE; k++)
{
set[k] = 0;
}
hipMalloc(&set_d, SIZE*SIZE*sizeof(int)); //allocate memory for set on device
/*The variable 'written' allows us to introduce a newline
after each row that has been written to the outpur file.
This allows for more freedom in printing the set using
gnuplot.*/
written=0; //reset 'written' value
for( int k=0; k<ZOOM; k++ ) //k...number of zoom slices to produce
{ //vary scale for zoom
scale = START_SCALE *(400.0f-(float)k)/400.0f + 0.01;
hipMemcpy(set_d, set, SIZE*SIZE*sizeof(int), hipMemcpyHostToDevice); //init set on device
// construct_julia_set<<<numBlocks,threadsPerBlock>>>(set_d, scale); //construct julia set on GPU
construct_julia_set<<<grid,1>>>(set_d, scale); //construct julia set on GPU
hipDeviceSynchronize();
hipMemcpy(set, set_d, SIZE*SIZE*sizeof(int), hipMemcpyDeviceToHost); //copy resultto host
num = k; //out: 'julia_000.dat', 'julia_001.dat',...
snprintf(buffer, sizeof(char)*32, "julia_%03i.dat", num);
out = fopen( buffer, "wt" ); //write in text mode (wt)
for (int i=0; i<SIZE; i++) //actual grid values x and y
{
x = scale * (float)(SIZE/2 - i)/(SIZE/2);
for (int j=0; j<SIZE; j++)
{
y = scale * (float)(SIZE/2 - j)/(SIZE/2);
int pos = i + j * SIZE; //position in array
if(set[pos]==1) //write only if part of set
{
fprintf(out,"%f %f \n",x,y);
written = 1; //set written to 1
}
}//end inner grid loop (j)
if( written == 1 )
{
fprintf(out,"\n"); //add newline if row content not empty
}
written=0; //reset written value
}//end outer grid loop (i)
fclose(out); //close file
}//end zoom loop (k)
hipFree( set_d ); //deallocate
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19construct_julia_setPif
.globl _Z19construct_julia_setPif
.p2align 8
.type _Z19construct_julia_setPif,@function
_Z19construct_julia_setPif:
s_load_b32 s2, s[0:1], 0x8
s_sub_i32 s3, 0x200, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v0, s3
s_sub_i32 s3, 0x200, s14
v_cvt_f32_i32_e32 v1, s3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v0, s2, v0 :: v_dual_mul_f32 v1, s2, v1
v_dual_mul_f32 v0, 0x3b000000, v0 :: v_dual_mul_f32 v1, 0x3b000000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v2, v0, v0 :: v_dual_add_f32 v3, v1, v1
v_fma_f32 v2, v1, v1, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v0, v0, v3, 0x3e1fbe77
v_add_f32_e32 v1, 0xbf4ccccd, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v1, v1
v_fmac_f32_e32 v2, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s2, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s2
v_cmp_lt_f32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s2
s_mov_b32 s2, 0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, 0x44800000, v2
v_mov_b32_e32 v2, 0
s_cbranch_vccz .LBB0_2
s_branch .LBB0_5
.LBB0_1:
v_mul_f32_e32 v2, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v2, v1, v1, -v2
v_add_f32_e32 v1, v1, v1
v_fmaak_f32 v0, v0, v1, 0x3e1fbe77
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, 0xbf4ccccd, v2
v_mul_f32_e32 v1, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v0, v0
v_mul_f32_e32 v3, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
v_sqrt_f32_e32 v3, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v3, v1
v_fma_f32 v7, -v5, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v3, v3, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v3, v3, v5, s2
s_add_i32 s2, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v3, v1, vcc_lo
v_cmp_lt_f32_e64 s4, 0x44800000, v1
v_mov_b32_e32 v1, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_4
.LBB0_2:
s_mov_b32 s3, s2
s_cmpk_eq_i32 s2, 0xff
s_cbranch_scc0 .LBB0_1
.LBB0_4:
s_cmpk_gt_u32 s3, 0xfe
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, 0, 1, s2
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b32 s2, s15, 10
v_mov_b32_e32 v0, 0
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19construct_julia_setPif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19construct_julia_setPif, .Lfunc_end0-_Z19construct_julia_setPif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19construct_julia_setPif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19construct_julia_setPif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIZE 1024
#define START_SCALE 1.5f
#define MAXIT 256
#define C_RE -0.8f
#define C_IM 0.156f
#define ZOOM 200
//======================================================================
/*This function checks whether a point
belongs to the filled julia set. It
returns 0 if the value 'escaped', and
one if the maximal numer of iterations
has been reached. It is a function on the
device, but it can't be called like a
kernel from the host. It is used by the
kernel 'construct_julia_set' below. Note that
the kernel has the 'global' attribute rather
than the 'device' attribute.*/
__device__ int julia( int i, int j, float scale)
{
//rescale grid to actual scale
float x = scale * (float)(SIZE/2 - i)/(SIZE/2);
float y = scale * (float)(SIZE/2 - j)/(SIZE/2);
//real and imaginary part of point in question
float z_re=x;
float z_im=y;
float z_re_old;
//compute Z(n+1) = Zn^2 + C
for (int k=0; k<MAXIT;k++)
{
z_re_old = z_re; //store old real value
z_re =(z_re*z_re-z_im*z_im) + (C_RE); //compute Re(Z(n+1))
z_im = 2.0f*z_re_old*z_im + (C_IM); //compute Im(Z(n+1))
if ( sqrt(z_re*z_re+z_im*z_im) > SIZE) //check if point escaped
{
return 0; //point escaped
}
}
return 1; //point in set
}
//======================================================================
/* This function uses the one defined above
to construct an array called 'set' with ones and zeroes,
defining the elements of the julia set. This is the
kernel function to be called from the host and exectued
on the device. It thus carries the 'global' attribute.*/
__global__ void construct_julia_set( int *set, float scale)
{
// int i = blockIdx.x*blockDim.x + threadIdx.x; //determine thread id i
// int j = blockIdx.y*blockDim.y + threadIdx.y; //determine thread id j
int i = blockIdx.x;
int j = blockIdx.y;
int pos = i + j * SIZE; //remap to 1-dim array
set[pos] = julia( i, j, scale); //fill the set
}
//======================================================================
int main( void )
{
using namespace std;
int set[SIZE*SIZE]; //the result array on the host
int *set_d; //the result array on the device
int written; //aux variable for writing file
int num; //numbering of output file
float x; //Re part in complex Z plane
float y; //Im part in complez Z plane
float scale; //initial scale for zoom
char buffer[32]; //buffer for filenames
FILE *out; //output file
//dim3 threadsPerBlock(16,16); //number of threads per block and grid size
//dim3 numBlocks(SIZE/threadsPerBlock.x,SIZE/threadsPerBlock.y);
dim3 grid(SIZE,SIZE);
for(int k=0; k<SIZE*SIZE; k++)
{
set[k] = 0;
}
hipMalloc(&set_d, SIZE*SIZE*sizeof(int)); //allocate memory for set on device
/*The variable 'written' allows us to introduce a newline
after each row that has been written to the outpur file.
This allows for more freedom in printing the set using
gnuplot.*/
written=0; //reset 'written' value
for( int k=0; k<ZOOM; k++ ) //k...number of zoom slices to produce
{ //vary scale for zoom
scale = START_SCALE *(400.0f-(float)k)/400.0f + 0.01;
hipMemcpy(set_d, set, SIZE*SIZE*sizeof(int), hipMemcpyHostToDevice); //init set on device
// construct_julia_set<<<numBlocks,threadsPerBlock>>>(set_d, scale); //construct julia set on GPU
construct_julia_set<<<grid,1>>>(set_d, scale); //construct julia set on GPU
hipDeviceSynchronize();
hipMemcpy(set, set_d, SIZE*SIZE*sizeof(int), hipMemcpyDeviceToHost); //copy resultto host
num = k; //out: 'julia_000.dat', 'julia_001.dat',...
snprintf(buffer, sizeof(char)*32, "julia_%03i.dat", num);
out = fopen( buffer, "wt" ); //write in text mode (wt)
for (int i=0; i<SIZE; i++) //actual grid values x and y
{
x = scale * (float)(SIZE/2 - i)/(SIZE/2);
for (int j=0; j<SIZE; j++)
{
y = scale * (float)(SIZE/2 - j)/(SIZE/2);
int pos = i + j * SIZE; //position in array
if(set[pos]==1) //write only if part of set
{
fprintf(out,"%f %f \n",x,y);
written = 1; //set written to 1
}
}//end inner grid loop (j)
if( written == 1 )
{
fprintf(out,"\n"); //add newline if row content not empty
}
written=0; //reset written value
}//end outer grid loop (i)
fclose(out); //close file
}//end zoom loop (k)
hipFree( set_d ); //deallocate
} | .text
.file "julia_set.hip"
.globl _Z34__device_stub__construct_julia_setPif # -- Begin function _Z34__device_stub__construct_julia_setPif
.p2align 4, 0x90
.type _Z34__device_stub__construct_julia_setPif,@function
_Z34__device_stub__construct_julia_setPif: # @_Z34__device_stub__construct_julia_setPif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19construct_julia_setPif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__construct_julia_setPif, .Lfunc_end0-_Z34__device_stub__construct_julia_setPif
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x43c80000 # float 400
.LCPI1_1:
.long 0x3fc00000 # float 1.5
.LCPI1_3:
.long 0x3b000000 # float 0.001953125
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f847ae147ae147b # double 0.01
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $4194456, %rsp # imm = 0x400098
.cfi_def_cfa_offset 4194512
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 144(%rsp), %rbx
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %r12d, %r12d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_1 Depth=1
movq %r13, %rdi
callq fclose
incl %r12d
cmpl $200, %r12d
leaq 144(%rsp), %rbx
je .LBB1_12
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_5 Depth 3
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
mulss .LCPI1_1(%rip), %xmm1
divss %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
addsd .LCPI1_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4398046512128, %rdi # imm = 0x40000000400
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z19construct_julia_setPif, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $32, %esi
movl $.L.str, %edx
leaq 112(%rsp), %r14
movq %r14, %rdi
movl %r12d, %ecx
xorl %eax, %eax
callq snprintf
movl $.L.str.1, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r13
xorl %r15d, %r15d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_4 Depth=2
incq %r15
addq $4, %rbx
cmpq $1024, %r15 # imm = 0x400
je .LBB1_11
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_5 Depth 3
movl $512, %ebp # imm = 0x200
movl $512, %eax # imm = 0x200
subl %r15d, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %eax, %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=3
decl %ebp
addq $4096, %r14 # imm = 0x1000
cmpq $4194304, %r14 # imm = 0x400000
je .LBB1_8
.LBB1_5: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
cmpl $1, (%rbx,%r14)
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=3
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_3(%rip), %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str.2, %esi
movq %r13, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq fprintf
movl $1, %eax
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_4 Depth=2
cmpl $1, %eax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_4 Depth=2
movl $10, %edi
movq %r13, %rsi
callq fputc@PLT
jmp .LBB1_10
.LBB1_12:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4194456, %rsp # imm = 0x400098
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19construct_julia_setPif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19construct_julia_setPif,@object # @_Z19construct_julia_setPif
.section .rodata,"a",@progbits
.globl _Z19construct_julia_setPif
.p2align 3, 0x0
_Z19construct_julia_setPif:
.quad _Z34__device_stub__construct_julia_setPif
.size _Z19construct_julia_setPif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "julia_%03i.dat"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "wt"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f %f \n"
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19construct_julia_setPif"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__construct_julia_setPif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19construct_julia_setPif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00151588_00000000-6_julia_set.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5juliaiif
.type _Z5juliaiif, @function
_Z5juliaiif:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5juliaiif, .-_Z5juliaiif
.globl _Z40__device_stub__Z19construct_julia_setPifPif
.type _Z40__device_stub__Z19construct_julia_setPifPif, @function
_Z40__device_stub__Z19construct_julia_setPifPif:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19construct_julia_setPif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z19construct_julia_setPifPif, .-_Z40__device_stub__Z19construct_julia_setPifPif
.globl _Z19construct_julia_setPif
.type _Z19construct_julia_setPif, @function
_Z19construct_julia_setPif:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19construct_julia_setPifPif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19construct_julia_setPif, .-_Z19construct_julia_setPif
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "julia_%03i.dat"
.LC4:
.string "wt"
.LC6:
.string "%f %f \n"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194360
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $120, %rsp
.cfi_def_cfa_offset 4194480
movq %fs:40, %rax
movq %rax, 4194408(%rsp)
xorl %eax, %eax
movl $1024, 40(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 8(%rsp)
leaq 4194368(%rsp), %rdx
.L14:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, 20(%rsp)
leaq 64(%rsp), %rax
movq %rax, 24(%rsp)
jmp .L20
.L31:
movss 4(%rsp), %xmm0
movq 32(%rsp), %rdi
call _Z40__device_stub__Z19construct_julia_setPifPif
jmp .L15
.L16:
addq $4096, %rbp
subl $1, %ebx
cmpl $-512, %ebx
je .L27
.L17:
movl 0(%rbp), %r12d
cmpl $1, %r12d
jne .L16
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
mulss 4(%rsp), %xmm1
mulss .LC5(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
cvtss2sd %xmm1, %xmm1
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $2, %eax
call __fprintf_chk@PLT
movl %r12d, %eax
jmp .L16
.L27:
cmpl $1, %eax
je .L28
.L18:
addq $1, %r15
cmpq $1024, %r15
je .L29
.L19:
movl $512, %eax
subl %r15d, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss 4(%rsp), %xmm0
mulss .LC5(%rip), %xmm0
movss %xmm0, 16(%rsp)
movq 8(%rsp), %rax
leaq (%rax,%r15,4), %rbp
movl $512, %ebx
movl $0, %eax
jmp .L17
.L28:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L29:
movq %r13, %rdi
call fclose@PLT
addl $1, 20(%rsp)
movl 20(%rsp), %eax
cmpl $200, %eax
je .L30
.L20:
pxor %xmm1, %xmm1
cvtsi2ssl 20(%rsp), %xmm1
movss .LC0(%rip), %xmm0
subss %xmm1, %xmm0
mulss .LC1(%rip), %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC2(%rip), %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 4(%rsp)
movl $1, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L15:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4194368(%rsp), %rbx
movl 20(%rsp), %r9d
leaq .LC3(%rip), %r8
movl $32, %ecx
movl $2, %edx
movl $32, %esi
movq %rbx, %rdi
movl $0, %eax
call __snprintf_chk@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %r15d
leaq .LC6(%rip), %r14
jmp .L19
.L30:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 4194408(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $4194424, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z19construct_julia_setPif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z19construct_julia_setPif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1137180672
.align 4
.LC1:
.long 1069547520
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 1202590843
.long 1065646817
.section .rodata.cst4
.align 4
.LC5:
.long 989855744
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "julia_set.hip"
.globl _Z34__device_stub__construct_julia_setPif # -- Begin function _Z34__device_stub__construct_julia_setPif
.p2align 4, 0x90
.type _Z34__device_stub__construct_julia_setPif,@function
_Z34__device_stub__construct_julia_setPif: # @_Z34__device_stub__construct_julia_setPif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19construct_julia_setPif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__construct_julia_setPif, .Lfunc_end0-_Z34__device_stub__construct_julia_setPif
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x43c80000 # float 400
.LCPI1_1:
.long 0x3fc00000 # float 1.5
.LCPI1_3:
.long 0x3b000000 # float 0.001953125
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f847ae147ae147b # double 0.01
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $4194456, %rsp # imm = 0x400098
.cfi_def_cfa_offset 4194512
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 144(%rsp), %rbx
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %r12d, %r12d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_1 Depth=1
movq %r13, %rdi
callq fclose
incl %r12d
cmpl $200, %r12d
leaq 144(%rsp), %rbx
je .LBB1_12
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_5 Depth 3
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
mulss .LCPI1_1(%rip), %xmm1
divss %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
addsd .LCPI1_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4398046512128, %rdi # imm = 0x40000000400
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z19construct_julia_setPif, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $32, %esi
movl $.L.str, %edx
leaq 112(%rsp), %r14
movq %r14, %rdi
movl %r12d, %ecx
xorl %eax, %eax
callq snprintf
movl $.L.str.1, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r13
xorl %r15d, %r15d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_4 Depth=2
incq %r15
addq $4, %rbx
cmpq $1024, %r15 # imm = 0x400
je .LBB1_11
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_5 Depth 3
movl $512, %ebp # imm = 0x200
movl $512, %eax # imm = 0x200
subl %r15d, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %eax, %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=3
decl %ebp
addq $4096, %r14 # imm = 0x1000
cmpq $4194304, %r14 # imm = 0x400000
je .LBB1_8
.LBB1_5: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
cmpl $1, (%rbx,%r14)
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=3
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI1_3(%rip), %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str.2, %esi
movq %r13, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq fprintf
movl $1, %eax
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_4 Depth=2
cmpl $1, %eax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_4 Depth=2
movl $10, %edi
movq %r13, %rsi
callq fputc@PLT
jmp .LBB1_10
.LBB1_12:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4194456, %rsp # imm = 0x400098
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19construct_julia_setPif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19construct_julia_setPif,@object # @_Z19construct_julia_setPif
.section .rodata,"a",@progbits
.globl _Z19construct_julia_setPif
.p2align 3, 0x0
_Z19construct_julia_setPif:
.quad _Z34__device_stub__construct_julia_setPif
.size _Z19construct_julia_setPif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "julia_%03i.dat"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "wt"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f %f \n"
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19construct_julia_setPif"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__construct_julia_setPif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19construct_julia_setPif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
//------------------------------------------------------------------------------
void print_array(int *array, int size) {
printf("{ ");
for (int i=0; i<size; i++) {
printf("%d ", array[i]);
}
printf(" }");
}
//------------------------------------------------------------------------------
__global__ void increment_naive(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// Wrap thread to array size
i = i % ARRAY_SIZE;
g[i] = g[i] + 1;
}
//------------------------------------------------------------------------------
__global__ void increment_atomic(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// wrap thread to array size
i = i % ARRAY_SIZE;
atomicAdd(&g[i], 1);
}
//------------------------------------------------------------------------------
int main(int argc, char **argv) {
printf("%d threads in %d blocks writing %d elements\n",
NUM_THREADS,
NUM_THREADS / BLOCK_WIDTH,
ARRAY_SIZE);
// array on host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// array on GPU
int *d_array;
cudaMalloc((void **) &d_array, ARRAY_BYTES);
cudaMemset((void *) d_array, 0, ARRAY_BYTES);
//increment_naive<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
// copy results back from GPU
cudaMemcpy(h_array, d_array, ARRAY_BYTES, cudaMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
// free GPU memory
cudaFree(d_array);
return 0;
} | code for sm_80
Function : _Z16increment_atomicPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.HI R2, R0, 0x51eb851f, RZ ; /* 0x51eb851f00027827 */
/* 0x000fca00078e02ff */
/*0070*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0080*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fe200078fdaff */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*00a0*/ IMAD R3, R3, -0x64, R0 ; /* 0xffffff9c03037824 */
/* 0x000fcc00078e0200 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15increment_naivePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD.HI R2, R0, 0x51eb851f, RZ ; /* 0x51eb851f00027827 */
/* 0x000fca00078e02ff */
/*0060*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0070*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fe200078fdaff */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*0090*/ IMAD R3, R3, -0x64, R0 ; /* 0xffffff9c03037824 */
/* 0x000fcc00078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
//------------------------------------------------------------------------------
void print_array(int *array, int size) {
printf("{ ");
for (int i=0; i<size; i++) {
printf("%d ", array[i]);
}
printf(" }");
}
//------------------------------------------------------------------------------
__global__ void increment_naive(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// Wrap thread to array size
i = i % ARRAY_SIZE;
g[i] = g[i] + 1;
}
//------------------------------------------------------------------------------
__global__ void increment_atomic(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// wrap thread to array size
i = i % ARRAY_SIZE;
atomicAdd(&g[i], 1);
}
//------------------------------------------------------------------------------
int main(int argc, char **argv) {
printf("%d threads in %d blocks writing %d elements\n",
NUM_THREADS,
NUM_THREADS / BLOCK_WIDTH,
ARRAY_SIZE);
// array on host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// array on GPU
int *d_array;
cudaMalloc((void **) &d_array, ARRAY_BYTES);
cudaMemset((void *) d_array, 0, ARRAY_BYTES);
//increment_naive<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
// copy results back from GPU
cudaMemcpy(h_array, d_array, ARRAY_BYTES, cudaMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
// free GPU memory
cudaFree(d_array);
return 0;
} | .file "tmpxft_001a32a1_00000000-6_sync_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{ "
.LC1:
.string "%d "
.LC2:
.string " }"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z35__device_stub__Z15increment_naivePiPi
.type _Z35__device_stub__Z15increment_naivePiPi, @function
_Z35__device_stub__Z15increment_naivePiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15increment_naivePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z15increment_naivePiPi, .-_Z35__device_stub__Z15increment_naivePiPi
.globl _Z15increment_naivePi
.type _Z15increment_naivePi, @function
_Z15increment_naivePi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15increment_naivePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15increment_naivePi, .-_Z15increment_naivePi
.globl _Z36__device_stub__Z16increment_atomicPiPi
.type _Z36__device_stub__Z16increment_atomicPiPi, @function
_Z36__device_stub__Z16increment_atomicPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_atomicPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z16increment_atomicPiPi, .-_Z36__device_stub__Z16increment_atomicPiPi
.globl _Z16increment_atomicPi
.type _Z16increment_atomicPi, @function
_Z16increment_atomicPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16increment_atomicPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z16increment_atomicPi, .-_Z16increment_atomicPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "%d threads in %d blocks writing %d elements\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $448, %rsp
.cfi_def_cfa_offset 464
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
movl $100, %r8d
movl $1000, %ecx
movl $1000000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $400, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $1000, 20(%rsp)
movl $1, 24(%rsp)
movl $1000, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $400, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $100, %esi
movq %rbx, %rdi
call _Z11print_arrayPii
movq (%rsp), %rdi
call cudaFree@PLT
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $448, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq (%rsp), %rdi
call _Z36__device_stub__Z16increment_atomicPiPi
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z16increment_atomicPi"
.LC5:
.string "_Z15increment_naivePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_atomicPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15increment_naivePi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
//------------------------------------------------------------------------------
void print_array(int *array, int size) {
printf("{ ");
for (int i=0; i<size; i++) {
printf("%d ", array[i]);
}
printf(" }");
}
//------------------------------------------------------------------------------
__global__ void increment_naive(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// Wrap thread to array size
i = i % ARRAY_SIZE;
g[i] = g[i] + 1;
}
//------------------------------------------------------------------------------
__global__ void increment_atomic(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// wrap thread to array size
i = i % ARRAY_SIZE;
atomicAdd(&g[i], 1);
}
//------------------------------------------------------------------------------
int main(int argc, char **argv) {
printf("%d threads in %d blocks writing %d elements\n",
NUM_THREADS,
NUM_THREADS / BLOCK_WIDTH,
ARRAY_SIZE);
// array on host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// array on GPU
int *d_array;
cudaMalloc((void **) &d_array, ARRAY_BYTES);
cudaMemset((void *) d_array, 0, ARRAY_BYTES);
//increment_naive<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
// copy results back from GPU
cudaMemcpy(h_array, d_array, ARRAY_BYTES, cudaMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
// free GPU memory
cudaFree(d_array);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
//------------------------------------------------------------------------------
void print_array(int *array, int size) {
printf("{ ");
for (int i=0; i<size; i++) {
printf("%d ", array[i]);
}
printf(" }");
}
//------------------------------------------------------------------------------
__global__ void increment_naive(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// Wrap thread to array size
i = i % ARRAY_SIZE;
g[i] = g[i] + 1;
}
//------------------------------------------------------------------------------
__global__ void increment_atomic(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// wrap thread to array size
i = i % ARRAY_SIZE;
atomicAdd(&g[i], 1);
}
//------------------------------------------------------------------------------
int main(int argc, char **argv) {
printf("%d threads in %d blocks writing %d elements\n",
NUM_THREADS,
NUM_THREADS / BLOCK_WIDTH,
ARRAY_SIZE);
// array on host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// array on GPU
int *d_array;
hipMalloc((void **) &d_array, ARRAY_BYTES);
hipMemset((void *) d_array, 0, ARRAY_BYTES);
//increment_naive<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
// copy results back from GPU
hipMemcpy(h_array, d_array, ARRAY_BYTES, hipMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
// free GPU memory
hipFree(d_array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
//------------------------------------------------------------------------------
void print_array(int *array, int size) {
printf("{ ");
for (int i=0; i<size; i++) {
printf("%d ", array[i]);
}
printf(" }");
}
//------------------------------------------------------------------------------
__global__ void increment_naive(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// Wrap thread to array size
i = i % ARRAY_SIZE;
g[i] = g[i] + 1;
}
//------------------------------------------------------------------------------
__global__ void increment_atomic(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// wrap thread to array size
i = i % ARRAY_SIZE;
atomicAdd(&g[i], 1);
}
//------------------------------------------------------------------------------
int main(int argc, char **argv) {
printf("%d threads in %d blocks writing %d elements\n",
NUM_THREADS,
NUM_THREADS / BLOCK_WIDTH,
ARRAY_SIZE);
// array on host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// array on GPU
int *d_array;
hipMalloc((void **) &d_array, ARRAY_BYTES);
hipMemset((void *) d_array, 0, ARRAY_BYTES);
//increment_naive<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
// copy results back from GPU
hipMemcpy(h_array, d_array, ARRAY_BYTES, hipMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
// free GPU memory
hipFree(d_array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15increment_naivePi
.globl _Z15increment_naivePi
.p2align 8
.type _Z15increment_naivePi,@function
_Z15increment_naivePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 0x64
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15increment_naivePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15increment_naivePi, .Lfunc_end0-_Z15increment_naivePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 8
.type _Z16increment_atomicPi,@function
_Z16increment_atomicPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 0x64
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_atomicPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16increment_atomicPi, .Lfunc_end1-_Z16increment_atomicPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15increment_naivePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15increment_naivePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_atomicPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_atomicPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
//------------------------------------------------------------------------------
void print_array(int *array, int size) {
printf("{ ");
for (int i=0; i<size; i++) {
printf("%d ", array[i]);
}
printf(" }");
}
//------------------------------------------------------------------------------
__global__ void increment_naive(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// Wrap thread to array size
i = i % ARRAY_SIZE;
g[i] = g[i] + 1;
}
//------------------------------------------------------------------------------
__global__ void increment_atomic(int *g) {
// determine thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
// wrap thread to array size
i = i % ARRAY_SIZE;
atomicAdd(&g[i], 1);
}
//------------------------------------------------------------------------------
int main(int argc, char **argv) {
printf("%d threads in %d blocks writing %d elements\n",
NUM_THREADS,
NUM_THREADS / BLOCK_WIDTH,
ARRAY_SIZE);
// array on host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// array on GPU
int *d_array;
hipMalloc((void **) &d_array, ARRAY_BYTES);
hipMemset((void *) d_array, 0, ARRAY_BYTES);
//increment_naive<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
// copy results back from GPU
hipMemcpy(h_array, d_array, ARRAY_BYTES, hipMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
// free GPU memory
hipFree(d_array);
return 0;
} | .text
.file "sync_array.hip"
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $.L.str.2, %edi
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11print_arrayPii, .Lfunc_end0-_Z11print_arrayPii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__increment_naivePi # -- Begin function _Z30__device_stub__increment_naivePi
.p2align 4, 0x90
.type _Z30__device_stub__increment_naivePi,@function
_Z30__device_stub__increment_naivePi: # @_Z30__device_stub__increment_naivePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15increment_naivePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z30__device_stub__increment_naivePi, .Lfunc_end1-_Z30__device_stub__increment_naivePi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__increment_atomicPi # -- Begin function _Z31__device_stub__increment_atomicPi
.p2align 4, 0x90
.type _Z31__device_stub__increment_atomicPi,@function
_Z31__device_stub__increment_atomicPi: # @_Z31__device_stub__increment_atomicPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z31__device_stub__increment_atomicPi, .Lfunc_end2-_Z31__device_stub__increment_atomicPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -16
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
movl $1000, %edx # imm = 0x3E8
movl $100, %ecx
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
xorl %esi, %esi
callq hipMemset
movabsq $4294968296, %rdi # imm = 0x1000003E8
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16increment_atomicPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB3_3
# %bb.4: # %_Z11print_arrayPii.exit
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15increment_naivePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_atomicPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "{ "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " }"
.size .L.str.2, 3
.type _Z15increment_naivePi,@object # @_Z15increment_naivePi
.section .rodata,"a",@progbits
.globl _Z15increment_naivePi
.p2align 3, 0x0
_Z15increment_naivePi:
.quad _Z30__device_stub__increment_naivePi
.size _Z15increment_naivePi, 8
.type _Z16increment_atomicPi,@object # @_Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 3, 0x0
_Z16increment_atomicPi:
.quad _Z31__device_stub__increment_atomicPi
.size _Z16increment_atomicPi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d threads in %d blocks writing %d elements\n"
.size .L.str.3, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15increment_naivePi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16increment_atomicPi"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__increment_naivePi
.addrsig_sym _Z31__device_stub__increment_atomicPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15increment_naivePi
.addrsig_sym _Z16increment_atomicPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16increment_atomicPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.HI R2, R0, 0x51eb851f, RZ ; /* 0x51eb851f00027827 */
/* 0x000fca00078e02ff */
/*0070*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0080*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fe200078fdaff */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*00a0*/ IMAD R3, R3, -0x64, R0 ; /* 0xffffff9c03037824 */
/* 0x000fcc00078e0200 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15increment_naivePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD.HI R2, R0, 0x51eb851f, RZ ; /* 0x51eb851f00027827 */
/* 0x000fca00078e02ff */
/*0060*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0070*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fe200078fdaff */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*0090*/ IMAD R3, R3, -0x64, R0 ; /* 0xffffff9c03037824 */
/* 0x000fcc00078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15increment_naivePi
.globl _Z15increment_naivePi
.p2align 8
.type _Z15increment_naivePi,@function
_Z15increment_naivePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 0x64
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15increment_naivePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15increment_naivePi, .Lfunc_end0-_Z15increment_naivePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 8
.type _Z16increment_atomicPi,@function
_Z16increment_atomicPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 0x64
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_atomicPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16increment_atomicPi, .Lfunc_end1-_Z16increment_atomicPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15increment_naivePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15increment_naivePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_atomicPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_atomicPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a32a1_00000000-6_sync_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{ "
.LC1:
.string "%d "
.LC2:
.string " }"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z35__device_stub__Z15increment_naivePiPi
.type _Z35__device_stub__Z15increment_naivePiPi, @function
_Z35__device_stub__Z15increment_naivePiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15increment_naivePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z15increment_naivePiPi, .-_Z35__device_stub__Z15increment_naivePiPi
.globl _Z15increment_naivePi
.type _Z15increment_naivePi, @function
_Z15increment_naivePi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15increment_naivePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15increment_naivePi, .-_Z15increment_naivePi
.globl _Z36__device_stub__Z16increment_atomicPiPi
.type _Z36__device_stub__Z16increment_atomicPiPi, @function
_Z36__device_stub__Z16increment_atomicPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_atomicPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z16increment_atomicPiPi, .-_Z36__device_stub__Z16increment_atomicPiPi
.globl _Z16increment_atomicPi
.type _Z16increment_atomicPi, @function
_Z16increment_atomicPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16increment_atomicPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z16increment_atomicPi, .-_Z16increment_atomicPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "%d threads in %d blocks writing %d elements\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $448, %rsp
.cfi_def_cfa_offset 464
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
movl $100, %r8d
movl $1000, %ecx
movl $1000000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $400, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $1000, 20(%rsp)
movl $1, 24(%rsp)
movl $1000, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $400, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $100, %esi
movq %rbx, %rdi
call _Z11print_arrayPii
movq (%rsp), %rdi
call cudaFree@PLT
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $448, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq (%rsp), %rdi
call _Z36__device_stub__Z16increment_atomicPiPi
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z16increment_atomicPi"
.LC5:
.string "_Z15increment_naivePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_atomicPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15increment_naivePi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sync_array.hip"
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $.L.str.2, %edi
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11print_arrayPii, .Lfunc_end0-_Z11print_arrayPii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__increment_naivePi # -- Begin function _Z30__device_stub__increment_naivePi
.p2align 4, 0x90
.type _Z30__device_stub__increment_naivePi,@function
_Z30__device_stub__increment_naivePi: # @_Z30__device_stub__increment_naivePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15increment_naivePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z30__device_stub__increment_naivePi, .Lfunc_end1-_Z30__device_stub__increment_naivePi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__increment_atomicPi # -- Begin function _Z31__device_stub__increment_atomicPi
.p2align 4, 0x90
.type _Z31__device_stub__increment_atomicPi,@function
_Z31__device_stub__increment_atomicPi: # @_Z31__device_stub__increment_atomicPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z31__device_stub__increment_atomicPi, .Lfunc_end2-_Z31__device_stub__increment_atomicPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -16
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
movl $1000, %edx # imm = 0x3E8
movl $100, %ecx
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
xorl %esi, %esi
callq hipMemset
movabsq $4294968296, %rdi # imm = 0x1000003E8
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16increment_atomicPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB3_3
# %bb.4: # %_Z11print_arrayPii.exit
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15increment_naivePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_atomicPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "{ "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " }"
.size .L.str.2, 3
.type _Z15increment_naivePi,@object # @_Z15increment_naivePi
.section .rodata,"a",@progbits
.globl _Z15increment_naivePi
.p2align 3, 0x0
_Z15increment_naivePi:
.quad _Z30__device_stub__increment_naivePi
.size _Z15increment_naivePi, 8
.type _Z16increment_atomicPi,@object # @_Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 3, 0x0
_Z16increment_atomicPi:
.quad _Z31__device_stub__increment_atomicPi
.size _Z16increment_atomicPi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d threads in %d blocks writing %d elements\n"
.size .L.str.3, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15increment_naivePi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16increment_atomicPi"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__increment_naivePi
.addrsig_sym _Z31__device_stub__increment_atomicPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15increment_naivePi
.addrsig_sym _Z16increment_atomicPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
__global__ void matadd(int *d_a,int *d_b,int *d_c, int n){
int idx=threadIdx.x;
if(idx<n)
d_c[idx]=d_a[idx]+d_b[idx];
}
int main(){
int n;
scanf("%d",&n);
cudaEvent_t start,stop;
float escap_time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
cudaStream_t stream;
cudaStreamCreate(&stream);
int *h_a,*h_b,*h_c;
cudaHostAlloc((void**)&h_a,20*n*sizeof(int),cudaHostAllocDefault);
cudaHostAlloc((void**)&h_b,20*n*sizeof(int),cudaHostAllocDefault);
cudaHostAlloc((void**)&h_c,20*n*sizeof(int),cudaHostAllocDefault);
for(int i=0; i<20*n; i++){
h_a[i]=i;
h_b[i]=i+1;
}
int *d_a,*d_b,*d_c;
cudaMalloc((void**)&d_a,n*sizeof(int));
cudaMalloc((void**)&d_b,n*sizeof(int));
cudaMalloc((void**)&d_c,n*sizeof(int));
for(int i=0; i<20*n; i+=n){
cudaMemcpyAsync(d_a,h_a+i,n*sizeof(int),cudaMemcpyHostToDevice,stream);
cudaMemcpyAsync(d_b,h_b+i,n*sizeof(int),cudaMemcpyHostToDevice,stream);
matadd<<<1,n,0,stream>>>(d_a,d_b,d_c,n);
cudaMemcpyAsync(h_c+i,d_c,n*sizeof(int),cudaMemcpyDeviceToHost,stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&escap_time,start,stop);
printf("Time:%3.1f\n",escap_time);
for(int i=0; i<20*n; i++)
printf("%d ",h_c[i]);
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(h_a);
cudaFree(h_b);
cudaFree(h_c);
cudaStreamDestroy(stream);
return 0;
} | code for sm_80
Function : _Z6mataddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
__global__ void matadd(int *d_a,int *d_b,int *d_c, int n){
int idx=threadIdx.x;
if(idx<n)
d_c[idx]=d_a[idx]+d_b[idx];
}
int main(){
int n;
scanf("%d",&n);
cudaEvent_t start,stop;
float escap_time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
cudaStream_t stream;
cudaStreamCreate(&stream);
int *h_a,*h_b,*h_c;
cudaHostAlloc((void**)&h_a,20*n*sizeof(int),cudaHostAllocDefault);
cudaHostAlloc((void**)&h_b,20*n*sizeof(int),cudaHostAllocDefault);
cudaHostAlloc((void**)&h_c,20*n*sizeof(int),cudaHostAllocDefault);
for(int i=0; i<20*n; i++){
h_a[i]=i;
h_b[i]=i+1;
}
int *d_a,*d_b,*d_c;
cudaMalloc((void**)&d_a,n*sizeof(int));
cudaMalloc((void**)&d_b,n*sizeof(int));
cudaMalloc((void**)&d_c,n*sizeof(int));
for(int i=0; i<20*n; i+=n){
cudaMemcpyAsync(d_a,h_a+i,n*sizeof(int),cudaMemcpyHostToDevice,stream);
cudaMemcpyAsync(d_b,h_b+i,n*sizeof(int),cudaMemcpyHostToDevice,stream);
matadd<<<1,n,0,stream>>>(d_a,d_b,d_c,n);
cudaMemcpyAsync(h_c+i,d_c,n*sizeof(int),cudaMemcpyDeviceToHost,stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&escap_time,start,stop);
printf("Time:%3.1f\n",escap_time);
for(int i=0; i<20*n; i++)
printf("%d ",h_c[i]);
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(h_a);
cudaFree(h_b);
cudaFree(h_c);
cudaStreamDestroy(stream);
return 0;
} | .file "tmpxft_00017114_00000000-6_stream_bhanu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6mataddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6mataddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
.globl _Z6mataddPiS_S_i
.type _Z6mataddPiS_S_i, @function
_Z6mataddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6mataddPiS_S_i, .-_Z6mataddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "Time:%3.1f\n"
.LC2:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
call cudaStreamCreate@PLT
movl 4(%rsp), %eax
leal (%rax,%rax,4), %esi
sall $2, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
movl $0, %edx
call cudaHostAlloc@PLT
movl 4(%rsp), %eax
leal (%rax,%rax,4), %esi
sall $2, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
movl $0, %edx
call cudaHostAlloc@PLT
movl 4(%rsp), %eax
leal (%rax,%rax,4), %esi
sall $2, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
movl $0, %edx
call cudaHostAlloc@PLT
movl 4(%rsp), %esi
testl %esi, %esi
jle .L12
movl $0, %edx
movl $0, %eax
.L13:
movq 32(%rsp), %rcx
movl %eax, (%rcx,%rdx)
addl $1, %eax
movq 40(%rsp), %rcx
movl %eax, (%rcx,%rdx)
movl 4(%rsp), %esi
addq $4, %rdx
leal (%rsi,%rsi,4), %ecx
sall $2, %ecx
cmpl %ecx, %eax
jl .L13
.L12:
movslq %esi, %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %edx
testl %edx, %edx
jle .L14
movl $0, %ebp
jmp .L16
.L15:
movslq 4(%rsp), %rdx
salq $2, %rdx
addq 48(%rsp), %rbx
movq %rbx, %rdi
movq 24(%rsp), %r8
movl $2, %ecx
movq 72(%rsp), %rsi
call cudaMemcpyAsync@PLT
movl 4(%rsp), %edx
addl %edx, %ebp
leal (%rdx,%rdx,4), %eax
sall $2, %eax
cmpl %ebp, %eax
jle .L14
.L16:
movslq %ebp, %rbx
salq $2, %rbx
movslq %edx, %rdx
salq $2, %rdx
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 24(%rsp), %r8
movl $1, %ecx
movq 56(%rsp), %rdi
call cudaMemcpyAsync@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 24(%rsp), %r8
movl $1, %ecx
movq 64(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl 4(%rsp), %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movq 24(%rsp), %r9
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl 4(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
jmp .L15
.L14:
movq 24(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L17
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L18:
movq 48(%rsp), %rax
movl (%rax,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
movl 4(%rsp), %eax
leal (%rax,%rax,4), %eax
sall $2, %eax
cmpl %ebx, %eax
jg .L18
.L17:
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6mataddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mataddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
__global__ void matadd(int *d_a,int *d_b,int *d_c, int n){
int idx=threadIdx.x;
if(idx<n)
d_c[idx]=d_a[idx]+d_b[idx];
}
int main(){
int n;
scanf("%d",&n);
cudaEvent_t start,stop;
float escap_time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
cudaStream_t stream;
cudaStreamCreate(&stream);
int *h_a,*h_b,*h_c;
cudaHostAlloc((void**)&h_a,20*n*sizeof(int),cudaHostAllocDefault);
cudaHostAlloc((void**)&h_b,20*n*sizeof(int),cudaHostAllocDefault);
cudaHostAlloc((void**)&h_c,20*n*sizeof(int),cudaHostAllocDefault);
for(int i=0; i<20*n; i++){
h_a[i]=i;
h_b[i]=i+1;
}
int *d_a,*d_b,*d_c;
cudaMalloc((void**)&d_a,n*sizeof(int));
cudaMalloc((void**)&d_b,n*sizeof(int));
cudaMalloc((void**)&d_c,n*sizeof(int));
for(int i=0; i<20*n; i+=n){
cudaMemcpyAsync(d_a,h_a+i,n*sizeof(int),cudaMemcpyHostToDevice,stream);
cudaMemcpyAsync(d_b,h_b+i,n*sizeof(int),cudaMemcpyHostToDevice,stream);
matadd<<<1,n,0,stream>>>(d_a,d_b,d_c,n);
cudaMemcpyAsync(h_c+i,d_c,n*sizeof(int),cudaMemcpyDeviceToHost,stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&escap_time,start,stop);
printf("Time:%3.1f\n",escap_time);
for(int i=0; i<20*n; i++)
printf("%d ",h_c[i]);
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(h_a);
cudaFree(h_b);
cudaFree(h_c);
cudaStreamDestroy(stream);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void matadd(int *d_a,int *d_b,int *d_c, int n){
int idx=threadIdx.x;
if(idx<n)
d_c[idx]=d_a[idx]+d_b[idx];
}
int main(){
int n;
scanf("%d",&n);
hipEvent_t start,stop;
float escap_time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
hipStream_t stream;
hipStreamCreate(&stream);
int *h_a,*h_b,*h_c;
hipHostAlloc((void**)&h_a,20*n*sizeof(int),hipHostMallocDefault);
hipHostAlloc((void**)&h_b,20*n*sizeof(int),hipHostMallocDefault);
hipHostAlloc((void**)&h_c,20*n*sizeof(int),hipHostMallocDefault);
for(int i=0; i<20*n; i++){
h_a[i]=i;
h_b[i]=i+1;
}
int *d_a,*d_b,*d_c;
hipMalloc((void**)&d_a,n*sizeof(int));
hipMalloc((void**)&d_b,n*sizeof(int));
hipMalloc((void**)&d_c,n*sizeof(int));
for(int i=0; i<20*n; i+=n){
hipMemcpyAsync(d_a,h_a+i,n*sizeof(int),hipMemcpyHostToDevice,stream);
hipMemcpyAsync(d_b,h_b+i,n*sizeof(int),hipMemcpyHostToDevice,stream);
matadd<<<1,n,0,stream>>>(d_a,d_b,d_c,n);
hipMemcpyAsync(h_c+i,d_c,n*sizeof(int),hipMemcpyDeviceToHost,stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&escap_time,start,stop);
printf("Time:%3.1f\n",escap_time);
for(int i=0; i<20*n; i++)
printf("%d ",h_c[i]);
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(h_a);
hipFree(h_b);
hipFree(h_c);
hipStreamDestroy(stream);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void matadd(int *d_a,int *d_b,int *d_c, int n){
int idx=threadIdx.x;
if(idx<n)
d_c[idx]=d_a[idx]+d_b[idx];
}
int main(){
int n;
scanf("%d",&n);
hipEvent_t start,stop;
float escap_time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
hipStream_t stream;
hipStreamCreate(&stream);
int *h_a,*h_b,*h_c;
hipHostAlloc((void**)&h_a,20*n*sizeof(int),hipHostMallocDefault);
hipHostAlloc((void**)&h_b,20*n*sizeof(int),hipHostMallocDefault);
hipHostAlloc((void**)&h_c,20*n*sizeof(int),hipHostMallocDefault);
for(int i=0; i<20*n; i++){
h_a[i]=i;
h_b[i]=i+1;
}
int *d_a,*d_b,*d_c;
hipMalloc((void**)&d_a,n*sizeof(int));
hipMalloc((void**)&d_b,n*sizeof(int));
hipMalloc((void**)&d_c,n*sizeof(int));
for(int i=0; i<20*n; i+=n){
hipMemcpyAsync(d_a,h_a+i,n*sizeof(int),hipMemcpyHostToDevice,stream);
hipMemcpyAsync(d_b,h_b+i,n*sizeof(int),hipMemcpyHostToDevice,stream);
matadd<<<1,n,0,stream>>>(d_a,d_b,d_c,n);
hipMemcpyAsync(h_c+i,d_c,n*sizeof(int),hipMemcpyDeviceToHost,stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&escap_time,start,stop);
printf("Time:%3.1f\n",escap_time);
for(int i=0; i<20*n; i++)
printf("%d ",h_c[i]);
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(h_a);
hipFree(h_b);
hipFree(h_c);
hipStreamDestroy(stream);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6mataddPiS_S_i
.globl _Z6mataddPiS_S_i
.p2align 8
.type _Z6mataddPiS_S_i,@function
_Z6mataddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6mataddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6mataddPiS_S_i, .Lfunc_end0-_Z6mataddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6mataddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6mataddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void matadd(int *d_a,int *d_b,int *d_c, int n){
int idx=threadIdx.x;
if(idx<n)
d_c[idx]=d_a[idx]+d_b[idx];
}
int main(){
int n;
scanf("%d",&n);
hipEvent_t start,stop;
float escap_time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
hipStream_t stream;
hipStreamCreate(&stream);
int *h_a,*h_b,*h_c;
hipHostAlloc((void**)&h_a,20*n*sizeof(int),hipHostMallocDefault);
hipHostAlloc((void**)&h_b,20*n*sizeof(int),hipHostMallocDefault);
hipHostAlloc((void**)&h_c,20*n*sizeof(int),hipHostMallocDefault);
for(int i=0; i<20*n; i++){
h_a[i]=i;
h_b[i]=i+1;
}
int *d_a,*d_b,*d_c;
hipMalloc((void**)&d_a,n*sizeof(int));
hipMalloc((void**)&d_b,n*sizeof(int));
hipMalloc((void**)&d_c,n*sizeof(int));
for(int i=0; i<20*n; i+=n){
hipMemcpyAsync(d_a,h_a+i,n*sizeof(int),hipMemcpyHostToDevice,stream);
hipMemcpyAsync(d_b,h_b+i,n*sizeof(int),hipMemcpyHostToDevice,stream);
matadd<<<1,n,0,stream>>>(d_a,d_b,d_c,n);
hipMemcpyAsync(h_c+i,d_c,n*sizeof(int),hipMemcpyDeviceToHost,stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&escap_time,start,stop);
printf("Time:%3.1f\n",escap_time);
for(int i=0; i<20*n; i++)
printf("%d ",h_c[i]);
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(h_a);
hipFree(h_b);
hipFree(h_c);
hipStreamDestroy(stream);
return 0;
} | .text
.file "stream_bhanu.hip"
.globl _Z21__device_stub__mataddPiS_S_i # -- Begin function _Z21__device_stub__mataddPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__mataddPiS_S_i,@function
_Z21__device_stub__mataddPiS_S_i: # @_Z21__device_stub__mataddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6mataddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__mataddPiS_S_i, .Lfunc_end0-_Z21__device_stub__mataddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 8(%rsp), %rdi
callq hipStreamCreate
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,4), %rsi
leaq 32(%rsp), %rdi
xorl %edx, %edx
callq hipHostAlloc
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,4), %rsi
leaq 24(%rsp), %rdi
xorl %edx, %edx
callq hipHostAlloc
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,4), %rsi
leaq 16(%rsp), %rdi
xorl %edx, %edx
callq hipHostAlloc
movl 4(%rsp), %edx
testl %edx, %edx
jle .LBB1_3
# %bb.1: # %.lr.ph
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %esi, (%rax,%rsi,4)
leaq 1(%rsi), %rdi
movl %edi, (%rcx,%rsi,4)
movslq 4(%rsp), %rdx
leaq (,%rdx,4), %rsi
leaq (%rsi,%rsi,4), %r8
movq %rdi, %rsi
cmpq %r8, %rdi
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %edx, %rsi
shlq $2, %rsi
leaq 80(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_8
# %bb.4: # %.lr.ph24
xorl %r15d, %r15d
movabsq $4294967296, %r12 # imm = 0x100000000
leaq 1(%r12), %rbx
leaq 88(%rsp), %r13
leaq 160(%rsp), %rbp
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
addq 16(%rsp), %r14
movq 64(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq 8(%rsp), %r8
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpyAsync
movl 4(%rsp), %eax
addl %eax, %r15d
leal (,%rax,4), %ecx
leal (%rcx,%rcx,4), %ecx
cmpl %ecx, %r15d
jge .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 80(%rsp), %rdi
movslq %r15d, %r14
shlq $2, %r14
movq 32(%rsp), %rsi
addq %r14, %rsi
movslq %eax, %rdx
shlq $2, %rdx
movq 8(%rsp), %r8
movl $1, %ecx
callq hipMemcpyAsync
movq 72(%rsp), %rdi
movq 24(%rsp), %rsi
addq %r14, %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq 8(%rsp), %r8
movl $1, %ecx
callq hipMemcpyAsync
movl 4(%rsp), %edx
movq 8(%rsp), %r9
orq %r12, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 80(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %esi, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z6mataddPiS_S_i, %edi
movq %rbp, %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge25
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpl $0, 4(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph28.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph28
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,4), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge29
movq 32(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipStreamDestroy
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mataddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mataddPiS_S_i,@object # @_Z6mataddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6mataddPiS_S_i
.p2align 3, 0x0
_Z6mataddPiS_S_i:
.quad _Z21__device_stub__mataddPiS_S_i
.size _Z6mataddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time:%3.1f\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6mataddPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mataddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mataddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6mataddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6mataddPiS_S_i
.globl _Z6mataddPiS_S_i
.p2align 8
.type _Z6mataddPiS_S_i,@function
_Z6mataddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6mataddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6mataddPiS_S_i, .Lfunc_end0-_Z6mataddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6mataddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6mataddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017114_00000000-6_stream_bhanu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6mataddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6mataddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
.globl _Z6mataddPiS_S_i
.type _Z6mataddPiS_S_i, @function
_Z6mataddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6mataddPiS_S_i, .-_Z6mataddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "Time:%3.1f\n"
.LC2:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
call cudaStreamCreate@PLT
movl 4(%rsp), %eax
leal (%rax,%rax,4), %esi
sall $2, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
movl $0, %edx
call cudaHostAlloc@PLT
movl 4(%rsp), %eax
leal (%rax,%rax,4), %esi
sall $2, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
movl $0, %edx
call cudaHostAlloc@PLT
movl 4(%rsp), %eax
leal (%rax,%rax,4), %esi
sall $2, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
movl $0, %edx
call cudaHostAlloc@PLT
movl 4(%rsp), %esi
testl %esi, %esi
jle .L12
movl $0, %edx
movl $0, %eax
.L13:
movq 32(%rsp), %rcx
movl %eax, (%rcx,%rdx)
addl $1, %eax
movq 40(%rsp), %rcx
movl %eax, (%rcx,%rdx)
movl 4(%rsp), %esi
addq $4, %rdx
leal (%rsi,%rsi,4), %ecx
sall $2, %ecx
cmpl %ecx, %eax
jl .L13
.L12:
movslq %esi, %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %edx
testl %edx, %edx
jle .L14
movl $0, %ebp
jmp .L16
.L15:
movslq 4(%rsp), %rdx
salq $2, %rdx
addq 48(%rsp), %rbx
movq %rbx, %rdi
movq 24(%rsp), %r8
movl $2, %ecx
movq 72(%rsp), %rsi
call cudaMemcpyAsync@PLT
movl 4(%rsp), %edx
addl %edx, %ebp
leal (%rdx,%rdx,4), %eax
sall $2, %eax
cmpl %ebp, %eax
jle .L14
.L16:
movslq %ebp, %rbx
salq $2, %rbx
movslq %edx, %rdx
salq $2, %rdx
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 24(%rsp), %r8
movl $1, %ecx
movq 56(%rsp), %rdi
call cudaMemcpyAsync@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 24(%rsp), %r8
movl $1, %ecx
movq 64(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl 4(%rsp), %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movq 24(%rsp), %r9
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl 4(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z30__device_stub__Z6mataddPiS_S_iPiS_S_i
jmp .L15
.L14:
movq 24(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L17
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L18:
movq 48(%rsp), %rax
movl (%rax,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
movl 4(%rsp), %eax
leal (%rax,%rax,4), %eax
sall $2, %eax
cmpl %ebx, %eax
jg .L18
.L17:
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6mataddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mataddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stream_bhanu.hip"
.globl _Z21__device_stub__mataddPiS_S_i # -- Begin function _Z21__device_stub__mataddPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__mataddPiS_S_i,@function
_Z21__device_stub__mataddPiS_S_i: # @_Z21__device_stub__mataddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6mataddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__mataddPiS_S_i, .Lfunc_end0-_Z21__device_stub__mataddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 8(%rsp), %rdi
callq hipStreamCreate
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,4), %rsi
leaq 32(%rsp), %rdi
xorl %edx, %edx
callq hipHostAlloc
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,4), %rsi
leaq 24(%rsp), %rdi
xorl %edx, %edx
callq hipHostAlloc
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,4), %rsi
leaq 16(%rsp), %rdi
xorl %edx, %edx
callq hipHostAlloc
movl 4(%rsp), %edx
testl %edx, %edx
jle .LBB1_3
# %bb.1: # %.lr.ph
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %esi, (%rax,%rsi,4)
leaq 1(%rsi), %rdi
movl %edi, (%rcx,%rsi,4)
movslq 4(%rsp), %rdx
leaq (,%rdx,4), %rsi
leaq (%rsi,%rsi,4), %r8
movq %rdi, %rsi
cmpq %r8, %rdi
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %edx, %rsi
shlq $2, %rsi
leaq 80(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_8
# %bb.4: # %.lr.ph24
xorl %r15d, %r15d
movabsq $4294967296, %r12 # imm = 0x100000000
leaq 1(%r12), %rbx
leaq 88(%rsp), %r13
leaq 160(%rsp), %rbp
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
addq 16(%rsp), %r14
movq 64(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq 8(%rsp), %r8
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpyAsync
movl 4(%rsp), %eax
addl %eax, %r15d
leal (,%rax,4), %ecx
leal (%rcx,%rcx,4), %ecx
cmpl %ecx, %r15d
jge .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 80(%rsp), %rdi
movslq %r15d, %r14
shlq $2, %r14
movq 32(%rsp), %rsi
addq %r14, %rsi
movslq %eax, %rdx
shlq $2, %rdx
movq 8(%rsp), %r8
movl $1, %ecx
callq hipMemcpyAsync
movq 72(%rsp), %rdi
movq 24(%rsp), %rsi
addq %r14, %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq 8(%rsp), %r8
movl $1, %ecx
callq hipMemcpyAsync
movl 4(%rsp), %edx
movq 8(%rsp), %r9
orq %r12, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 80(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %esi, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z6mataddPiS_S_i, %edi
movq %rbp, %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge25
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpl $0, 4(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph28.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph28
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,4), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge29
movq 32(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipStreamDestroy
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mataddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mataddPiS_S_i,@object # @_Z6mataddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6mataddPiS_S_i
.p2align 3, 0x0
_Z6mataddPiS_S_i:
.quad _Z21__device_stub__mataddPiS_S_i
.size _Z6mataddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time:%3.1f\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6mataddPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mataddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mataddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
__global__ void helloWorld()
{
printf("Hello World! My threadId is %d\n", threadIdx.x);
}
int main()
{
helloWorld<<<1, 256>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10helloWorldv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
__global__ void helloWorld()
{
printf("Hello World! My threadId is %d\n", threadIdx.x);
}
int main()
{
helloWorld<<<1, 256>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000f4a5f_00000000-6_exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10helloWorldvv
.type _Z29__device_stub__Z10helloWorldvv, @function
_Z29__device_stub__Z10helloWorldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10helloWorldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10helloWorldvv, .-_Z29__device_stub__Z10helloWorldvv
.globl _Z10helloWorldv
.type _Z10helloWorldv, @function
_Z10helloWorldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10helloWorldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloWorldv, .-_Z10helloWorldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10helloWorldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10helloWorldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloWorldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
__global__ void helloWorld()
{
printf("Hello World! My threadId is %d\n", threadIdx.x);
}
int main()
{
helloWorld<<<1, 256>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void helloWorld()
{
printf("Hello World! My threadId is %d\n", threadIdx.x);
}
int main()
{
helloWorld<<<1, 256>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void helloWorld()
{
printf("Hello World! My threadId is %d\n", threadIdx.x);
}
int main()
{
helloWorld<<<1, 256>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "exercise_1.hip"
.globl _Z25__device_stub__helloWorldv # -- Begin function _Z25__device_stub__helloWorldv
.p2align 4, 0x90
.type _Z25__device_stub__helloWorldv,@function
_Z25__device_stub__helloWorldv: # @_Z25__device_stub__helloWorldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__helloWorldv, .Lfunc_end0-_Z25__device_stub__helloWorldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloWorldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloWorldv,@object # @_Z10helloWorldv
.section .rodata,"a",@progbits
.globl _Z10helloWorldv
.p2align 3, 0x0
_Z10helloWorldv:
.quad _Z25__device_stub__helloWorldv
.size _Z10helloWorldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10helloWorldv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloWorldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloWorldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f4a5f_00000000-6_exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10helloWorldvv
.type _Z29__device_stub__Z10helloWorldvv, @function
_Z29__device_stub__Z10helloWorldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10helloWorldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10helloWorldvv, .-_Z29__device_stub__Z10helloWorldvv
.globl _Z10helloWorldv
.type _Z10helloWorldv, @function
_Z10helloWorldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10helloWorldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloWorldv, .-_Z10helloWorldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10helloWorldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10helloWorldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloWorldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_1.hip"
.globl _Z25__device_stub__helloWorldv # -- Begin function _Z25__device_stub__helloWorldv
.p2align 4, 0x90
.type _Z25__device_stub__helloWorldv,@function
_Z25__device_stub__helloWorldv: # @_Z25__device_stub__helloWorldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__helloWorldv, .Lfunc_end0-_Z25__device_stub__helloWorldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloWorldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloWorldv,@object # @_Z10helloWorldv
.section .rodata,"a",@progbits
.globl _Z10helloWorldv
.p2align 3, 0x0
_Z10helloWorldv:
.quad _Z25__device_stub__helloWorldv
.size _Z10helloWorldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10helloWorldv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloWorldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloWorldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void copy(int *dst, int *input_itemsets, int max_rows, int max_cols, int lb0, int lb1, int ub0, int ub1)
{
int r, c;
r = blockIdx.y*blockDim.y+threadIdx.y+lb0;
c = blockIdx.x*blockDim.x+threadIdx.x+lb1;
if( r >= ub0 || c >= ub1) return;
int idx = r*max_cols+c;
dst[idx] = input_itemsets[idx];
} | code for sm_80
Function : _Z4copyPiS_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fc400078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fc600078e0203 */
/*0070*/ IADD3 R3, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002037a10 */
/* 0x000fe40007ffe0ff */
/*0080*/ IADD3 R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe40007ffe0ff */
/*0090*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fc80003f06270 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fda0000706670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fe200078e0203 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0120*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void copy(int *dst, int *input_itemsets, int max_rows, int max_cols, int lb0, int lb1, int ub0, int ub1)
{
int r, c;
r = blockIdx.y*blockDim.y+threadIdx.y+lb0;
c = blockIdx.x*blockDim.x+threadIdx.x+lb1;
if( r >= ub0 || c >= ub1) return;
int idx = r*max_cols+c;
dst[idx] = input_itemsets[idx];
} | .file "tmpxft_001b96d5_00000000-6_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii
.type _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii, @function
_Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4copyPiS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii, .-_Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii
.globl _Z4copyPiS_iiiiii
.type _Z4copyPiS_iiiiii, @function
_Z4copyPiS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4copyPiS_iiiiii, .-_Z4copyPiS_iiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4copyPiS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPiS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void copy(int *dst, int *input_itemsets, int max_rows, int max_cols, int lb0, int lb1, int ub0, int ub1)
{
int r, c;
r = blockIdx.y*blockDim.y+threadIdx.y+lb0;
c = blockIdx.x*blockDim.x+threadIdx.x+lb1;
if( r >= ub0 || c >= ub1) return;
int idx = r*max_cols+c;
dst[idx] = input_itemsets[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copy(int *dst, int *input_itemsets, int max_rows, int max_cols, int lb0, int lb1, int ub0, int ub1)
{
int r, c;
r = blockIdx.y*blockDim.y+threadIdx.y+lb0;
c = blockIdx.x*blockDim.x+threadIdx.x+lb1;
if( r >= ub0 || c >= ub1) return;
int idx = r*max_cols+c;
dst[idx] = input_itemsets[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copy(int *dst, int *input_itemsets, int max_rows, int max_cols, int lb0, int lb1, int ub0, int ub1)
{
int r, c;
r = blockIdx.y*blockDim.y+threadIdx.y+lb0;
c = blockIdx.x*blockDim.x+threadIdx.x+lb1;
if( r >= ub0 || c >= ub1) return;
int idx = r*max_cols+c;
dst[idx] = input_itemsets[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPiS_iiiiii
.globl _Z4copyPiS_iiiiii
.p2align 8
.type _Z4copyPiS_iiiiii,@function
_Z4copyPiS_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add3_u32 v1, s15, s4, v1
v_add3_u32 v0, s14, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v1
v_cmp_gt_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPiS_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPiS_iiiiii, .Lfunc_end0-_Z4copyPiS_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPiS_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPiS_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copy(int *dst, int *input_itemsets, int max_rows, int max_cols, int lb0, int lb1, int ub0, int ub1)
{
int r, c;
r = blockIdx.y*blockDim.y+threadIdx.y+lb0;
c = blockIdx.x*blockDim.x+threadIdx.x+lb1;
if( r >= ub0 || c >= ub1) return;
int idx = r*max_cols+c;
dst[idx] = input_itemsets[idx];
} | .text
.file "copy.hip"
.globl _Z19__device_stub__copyPiS_iiiiii # -- Begin function _Z19__device_stub__copyPiS_iiiiii
.p2align 4, 0x90
.type _Z19__device_stub__copyPiS_iiiiii,@function
_Z19__device_stub__copyPiS_iiiiii: # @_Z19__device_stub__copyPiS_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4copyPiS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPiS_iiiiii, .Lfunc_end0-_Z19__device_stub__copyPiS_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPiS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPiS_iiiiii,@object # @_Z4copyPiS_iiiiii
.section .rodata,"a",@progbits
.globl _Z4copyPiS_iiiiii
.p2align 3, 0x0
_Z4copyPiS_iiiiii:
.quad _Z19__device_stub__copyPiS_iiiiii
.size _Z4copyPiS_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4copyPiS_iiiiii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPiS_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPiS_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4copyPiS_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fc400078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fc600078e0203 */
/*0070*/ IADD3 R3, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002037a10 */
/* 0x000fe40007ffe0ff */
/*0080*/ IADD3 R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe40007ffe0ff */
/*0090*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fc80003f06270 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fda0000706670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fe200078e0203 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0120*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPiS_iiiiii
.globl _Z4copyPiS_iiiiii
.p2align 8
.type _Z4copyPiS_iiiiii,@function
_Z4copyPiS_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add3_u32 v1, s15, s4, v1
v_add3_u32 v0, s14, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v1
v_cmp_gt_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPiS_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPiS_iiiiii, .Lfunc_end0-_Z4copyPiS_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPiS_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPiS_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b96d5_00000000-6_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii
.type _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii, @function
_Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4copyPiS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii, .-_Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii
.globl _Z4copyPiS_iiiiii
.type _Z4copyPiS_iiiiii, @function
_Z4copyPiS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z31__device_stub__Z4copyPiS_iiiiiiPiS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4copyPiS_iiiiii, .-_Z4copyPiS_iiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4copyPiS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPiS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy.hip"
.globl _Z19__device_stub__copyPiS_iiiiii # -- Begin function _Z19__device_stub__copyPiS_iiiiii
.p2align 4, 0x90
.type _Z19__device_stub__copyPiS_iiiiii,@function
_Z19__device_stub__copyPiS_iiiiii: # @_Z19__device_stub__copyPiS_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4copyPiS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPiS_iiiiii, .Lfunc_end0-_Z19__device_stub__copyPiS_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPiS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPiS_iiiiii,@object # @_Z4copyPiS_iiiiii
.section .rodata,"a",@progbits
.globl _Z4copyPiS_iiiiii
.p2align 3, 0x0
_Z4copyPiS_iiiiii:
.quad _Z19__device_stub__copyPiS_iiiiii
.size _Z4copyPiS_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4copyPiS_iiiiii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPiS_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPiS_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define UPPERTHRESHOLD 90
#define LOWERTHRESHOLD 30
const float G_x[3 * 3] = {
-1, 0, 1,
-2, 0, 2,
-1, 0, 1
};
const float G_y[3 * 3] = {
1, 2, 1,
0, 0, 0,
-1, -2, -1
};
const float gaussian[5 * 5] = {
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
5.f/159, 12.f/159, 15.f/159, 12.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159
};
__global__ void nonMaxSuppression(int N, int width, int height, unsigned char * in, unsigned char * out) {
int D = 1;
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int angle = in[y * width + x];
switch(angle) {
case 0:
if (out[y * width + x] < out[(y + D) * width + x] || out[y * width + x] < out[(y - D) * width + x]) {
out[y * width + x] = 0;
}
break;
case 45:
if (out[y * width + x] < out[(y + D) * width + x - D] || out[y * width + x] < out[(y - D) * width + x + D]) {
out[y * width + x] = 0;
}
break;
case 90:
if (out[y * width + x] < out[y * width + x + D] || out[y * width + x] < out[y * width + x - D]) {
out[y * width + x] = 0;
}
break;
case 135:
if (out[y * width + x] < out[(y + D) * width + x + D] || out[y * width + x] < out[(y - D) * width + x - D]) {
out[y * width + x] = 0;
}
break;
default:
break;
}
} | code for sm_80
Function : _Z17nonMaxSuppressioniiiPhS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x164], P0 ; /* 0x0000590000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R3, c[0x0][0x164], R0 ; /* 0x0000590003027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ SHF.R.S32.HI R10, RZ, 0x1f, R2 ; /* 0x0000001fff0a7819 */
/* 0x000fe40000011402 */
/*00d0*/ IADD3 R8, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002087a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R9, R10, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000a097a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R2, P1, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fc60007f3e0ff */
/*0120*/ IMAD R3, R3, R4, c[0x0][0x164] ; /* 0x0000590003037624 */
/* 0x000fe400078e0204 */
/*0130*/ IMAD.MOV R4, RZ, RZ, -c[0x0][0x164] ; /* 0x80005900ff047624 */
/* 0x000fe400078e02ff */
/*0140*/ IMAD.IADD R5, R0, 0x1, R3.reuse ; /* 0x0000000100057824 */
/* 0x100fe400078e0203 */
/*0150*/ IMAD R7, R4, 0x2, R3 ; /* 0x0000000204077824 */
/* 0x000fe200078e0203 */
/*0160*/ IADD3.X R3, R10, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000a037a10 */
/* 0x000fe40000ffe4ff */
/*0170*/ IADD3 R4, P2, R5, c[0x0][0x178], RZ ; /* 0x00005e0005047a10 */
/* 0x000fe20007f5e0ff */
/*0180*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x000fc600078e0207 */
/*0190*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x17c], 0x1, P2 ; /* 0x00005f0005057a11 */
/* 0x000fe400010f0eff */
/*01a0*/ IADD3 R6, P3, R7, c[0x0][0x178], RZ ; /* 0x00005e0007067a10 */
/* 0x000fc80007f7e0ff */
/*01b0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x17c], 0x1, P3 ; /* 0x00005f0007077a11 */
/* 0x000fe400018f0eff */
/*01c0*/ ISETP.GT.AND P0, PT, R8, 0x59, PT ; /* 0x000000590800780c */
/* 0x004fda0003f04270 */
/*01d0*/ @P0 BRA 0x380 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*01f0*/ @!P0 BRA 0x2d0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.NE.AND P0, PT, R8, 0x2d, PT ; /* 0x0000002d0800780c */
/* 0x000fda0003f05270 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E.U8 R5, [R4.64+-0x1] ; /* 0xffffff0404057981 */
/* 0x000ea8000c1e1100 */
/*0230*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1100 */
/*0240*/ BSSY B0, 0x2b0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f06070 */
/*0260*/ @!P0 BRA 0x2a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.U8 R7, [R6.64+0x1] ; /* 0x0000010406077981 */
/* 0x000ea4000c1e1100 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f06070 */
/*0290*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1100 */
/*02e0*/ LDG.E.U8 R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1100 */
/*02f0*/ BSSY B0, 0x360 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x004fda0003f06070 */
/*0310*/ @!P0 BRA 0x350 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0320*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1100 */
/*0330*/ ISETP.GE.U32.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fda0003f06070 */
/*0340*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ ISETP.NE.AND P0, PT, R8, 0x5a, PT ; /* 0x0000005a0800780c */
/* 0x000fda0003f05270 */
/*0390*/ @!P0 BRA 0x470 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.NE.AND P0, PT, R8, 0x87, PT ; /* 0x000000870800780c */
/* 0x000fda0003f05270 */
/*03b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E.U8 R4, [R4.64+0x1] ; /* 0x0000010404047981 */
/* 0x000ea8000c1e1100 */
/*03d0*/ LDG.E.U8 R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1100 */
/*03e0*/ BSSY B0, 0x450 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x004fda0003f06070 */
/*0400*/ @!P0 BRA 0x440 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E.U8 R6, [R6.64+-0x1] ; /* 0xffffff0406067981 */
/* 0x000ea4000c1e1100 */
/*0420*/ ISETP.GE.U32.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fda0003f06070 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1100 */
/*0480*/ LDG.E.U8 R0, [R2.64+0x1] ; /* 0x0000010402007981 */
/* 0x000ea2000c1e1100 */
/*0490*/ BSSY B0, 0x500 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*04a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f06070 */
/*04b0*/ @!P0 BRA 0x4f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E.U8 R0, [R2.64+-0x1] ; /* 0xffffff0402007981 */
/* 0x000ea4000c1e1100 */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f06070 */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define UPPERTHRESHOLD 90
#define LOWERTHRESHOLD 30
const float G_x[3 * 3] = {
-1, 0, 1,
-2, 0, 2,
-1, 0, 1
};
const float G_y[3 * 3] = {
1, 2, 1,
0, 0, 0,
-1, -2, -1
};
const float gaussian[5 * 5] = {
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
5.f/159, 12.f/159, 15.f/159, 12.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159
};
__global__ void nonMaxSuppression(int N, int width, int height, unsigned char * in, unsigned char * out) {
int D = 1;
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int angle = in[y * width + x];
switch(angle) {
case 0:
if (out[y * width + x] < out[(y + D) * width + x] || out[y * width + x] < out[(y - D) * width + x]) {
out[y * width + x] = 0;
}
break;
case 45:
if (out[y * width + x] < out[(y + D) * width + x - D] || out[y * width + x] < out[(y - D) * width + x + D]) {
out[y * width + x] = 0;
}
break;
case 90:
if (out[y * width + x] < out[y * width + x + D] || out[y * width + x] < out[y * width + x - D]) {
out[y * width + x] = 0;
}
break;
case 135:
if (out[y * width + x] < out[(y + D) * width + x + D] || out[y * width + x] < out[(y - D) * width + x - D]) {
out[y * width + x] = 0;
}
break;
default:
break;
}
} | .file "tmpxft_0000e0a4_00000000-6_nonMaxSuppression.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_
.type _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_, @function
_Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17nonMaxSuppressioniiiPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_, .-_Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_
.globl _Z17nonMaxSuppressioniiiPhS_
.type _Z17nonMaxSuppressioniiiPhS_, @function
_Z17nonMaxSuppressioniiiPhS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17nonMaxSuppressioniiiPhS_, .-_Z17nonMaxSuppressioniiiPhS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17nonMaxSuppressioniiiPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17nonMaxSuppressioniiiPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define UPPERTHRESHOLD 90
#define LOWERTHRESHOLD 30
const float G_x[3 * 3] = {
-1, 0, 1,
-2, 0, 2,
-1, 0, 1
};
const float G_y[3 * 3] = {
1, 2, 1,
0, 0, 0,
-1, -2, -1
};
const float gaussian[5 * 5] = {
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
5.f/159, 12.f/159, 15.f/159, 12.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159
};
__global__ void nonMaxSuppression(int N, int width, int height, unsigned char * in, unsigned char * out) {
int D = 1;
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int angle = in[y * width + x];
switch(angle) {
case 0:
if (out[y * width + x] < out[(y + D) * width + x] || out[y * width + x] < out[(y - D) * width + x]) {
out[y * width + x] = 0;
}
break;
case 45:
if (out[y * width + x] < out[(y + D) * width + x - D] || out[y * width + x] < out[(y - D) * width + x + D]) {
out[y * width + x] = 0;
}
break;
case 90:
if (out[y * width + x] < out[y * width + x + D] || out[y * width + x] < out[y * width + x - D]) {
out[y * width + x] = 0;
}
break;
case 135:
if (out[y * width + x] < out[(y + D) * width + x + D] || out[y * width + x] < out[(y - D) * width + x - D]) {
out[y * width + x] = 0;
}
break;
default:
break;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define UPPERTHRESHOLD 90
#define LOWERTHRESHOLD 30
const float G_x[3 * 3] = {
-1, 0, 1,
-2, 0, 2,
-1, 0, 1
};
const float G_y[3 * 3] = {
1, 2, 1,
0, 0, 0,
-1, -2, -1
};
const float gaussian[5 * 5] = {
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
5.f/159, 12.f/159, 15.f/159, 12.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159
};
__global__ void nonMaxSuppression(int N, int width, int height, unsigned char * in, unsigned char * out) {
int D = 1;
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int angle = in[y * width + x];
switch(angle) {
case 0:
if (out[y * width + x] < out[(y + D) * width + x] || out[y * width + x] < out[(y - D) * width + x]) {
out[y * width + x] = 0;
}
break;
case 45:
if (out[y * width + x] < out[(y + D) * width + x - D] || out[y * width + x] < out[(y - D) * width + x + D]) {
out[y * width + x] = 0;
}
break;
case 90:
if (out[y * width + x] < out[y * width + x + D] || out[y * width + x] < out[y * width + x - D]) {
out[y * width + x] = 0;
}
break;
case 135:
if (out[y * width + x] < out[(y + D) * width + x + D] || out[y * width + x] < out[(y - D) * width + x - D]) {
out[y * width + x] = 0;
}
break;
default:
break;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define UPPERTHRESHOLD 90
#define LOWERTHRESHOLD 30
const float G_x[3 * 3] = {
-1, 0, 1,
-2, 0, 2,
-1, 0, 1
};
const float G_y[3 * 3] = {
1, 2, 1,
0, 0, 0,
-1, -2, -1
};
const float gaussian[5 * 5] = {
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
5.f/159, 12.f/159, 15.f/159, 12.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159
};
__global__ void nonMaxSuppression(int N, int width, int height, unsigned char * in, unsigned char * out) {
int D = 1;
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int angle = in[y * width + x];
switch(angle) {
case 0:
if (out[y * width + x] < out[(y + D) * width + x] || out[y * width + x] < out[(y - D) * width + x]) {
out[y * width + x] = 0;
}
break;
case 45:
if (out[y * width + x] < out[(y + D) * width + x - D] || out[y * width + x] < out[(y - D) * width + x + D]) {
out[y * width + x] = 0;
}
break;
case 90:
if (out[y * width + x] < out[y * width + x + D] || out[y * width + x] < out[y * width + x - D]) {
out[y * width + x] = 0;
}
break;
case 135:
if (out[y * width + x] < out[(y + D) * width + x + D] || out[y * width + x] < out[(y - D) * width + x - D]) {
out[y * width + x] = 0;
}
break;
default:
break;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17nonMaxSuppressioniiiPhS_
.globl _Z17nonMaxSuppressioniiiPhS_
.p2align 8
.type _Z17nonMaxSuppressioniiiPhS_,@function
_Z17nonMaxSuppressioniiiPhS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_31
s_load_b128 s[0:3], s[0:1], 0x10
v_mad_u64_u32 v[6:7], null, v4, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s0, 0
s_mov_b32 s1, exec_lo
global_load_u8 v8, v[0:1], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0x59, v8
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_15
s_mov_b32 s5, exec_lo
v_cmpx_lt_i16_e32 0x86, v8
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_8
s_mov_b32 s6, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u16_e32 0x87, v8
s_cbranch_execz .LBB0_7
v_mul_lo_u32 v0, s4, v4
s_mov_b32 s7, -1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v3, v0, s4, v2
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
v_ashrrev_i32_e32 v8, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v5, v[5:6], off offset:1
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v3, v5
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
global_load_u8 v2, v[4:5], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v3, v2
s_or_not1_b32 s7, vcc_lo, exec_lo
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s7, exec_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s6, exec_lo
.LBB0_8:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_14
s_mov_b32 s7, s0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0x5a, v8
s_cbranch_execz .LBB0_13
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s7, -1
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_u8 v2, v[0:1], off
global_load_u8 v3, v[0:1], off offset:1
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v2, v3
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_12
global_load_u8 v3, v[0:1], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v2, v3
s_or_not1_b32 s7, vcc_lo, exec_lo
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s8, s0, exec_lo
s_and_b32 s7, s7, exec_lo
s_or_b32 s7, s8, s7
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s6, s7, exec_lo
s_or_b32 s0, s0, s6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
.LBB0_15:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_29
s_mov_b32 s5, s0
s_mov_b32 s6, exec_lo
v_cmpx_lt_i16_e32 44, v8
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_22
s_mov_b32 s7, s0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u16_e32 45, v8
s_cbranch_execz .LBB0_21
v_mul_lo_u32 v0, s4, v4
s_mov_b32 s8, -1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v3, v0, s4, v2
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
v_ashrrev_i32_e32 v8, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v5, v[5:6], off offset:-1
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v3, v5
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_20
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
global_load_u8 v2, v[4:5], off offset:1
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v3, v2
s_or_not1_b32 s8, vcc_lo, exec_lo
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s7, s0, exec_lo
s_and_b32 s8, s8, exec_lo
s_or_b32 s7, s7, s8
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s5, s0, exec_lo
s_and_b32 s7, s7, exec_lo
s_or_b32 s5, s5, s7
.LBB0_22:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_28
s_mov_b32 s8, s5
s_mov_b32 s7, exec_lo
v_cmpx_eq_u16_e32 0, v8
s_cbranch_execz .LBB0_27
v_mul_lo_u32 v0, s4, v4
s_mov_b32 s9, -1
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v3, v0, s4, v2
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
v_ashrrev_i32_e32 v8, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v3, v5
s_cbranch_execz .LBB0_26
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
global_load_u8 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v3, v2
s_or_not1_b32 s9, vcc_lo, exec_lo
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s5, exec_lo
s_and_b32 s3, s9, exec_lo
s_or_b32 s8, s2, s3
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s5, exec_lo
s_and_b32 s3, s8, exec_lo
s_or_b32 s5, s2, s3
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, s5, exec_lo
s_or_b32 s0, s0, s2
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_31
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_31:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17nonMaxSuppressioniiiPhS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17nonMaxSuppressioniiiPhS_, .Lfunc_end0-_Z17nonMaxSuppressioniiiPhS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17nonMaxSuppressioniiiPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17nonMaxSuppressioniiiPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define UPPERTHRESHOLD 90
#define LOWERTHRESHOLD 30
const float G_x[3 * 3] = {
-1, 0, 1,
-2, 0, 2,
-1, 0, 1
};
const float G_y[3 * 3] = {
1, 2, 1,
0, 0, 0,
-1, -2, -1
};
const float gaussian[5 * 5] = {
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
5.f/159, 12.f/159, 15.f/159, 12.f/159, 2.f/159,
4.f/159, 9.f/159, 12.f/159, 9.f/159, 4.f/159,
2.f/159, 4.f/159, 5.f/159, 4.f/159, 2.f/159
};
__global__ void nonMaxSuppression(int N, int width, int height, unsigned char * in, unsigned char * out) {
int D = 1;
int x = (blockIdx.x * blockDim.x) + threadIdx.x;
int y = (blockIdx.y * blockDim.y) + threadIdx.y;
if (x >= width || y >= height) {
return;
}
int angle = in[y * width + x];
switch(angle) {
case 0:
if (out[y * width + x] < out[(y + D) * width + x] || out[y * width + x] < out[(y - D) * width + x]) {
out[y * width + x] = 0;
}
break;
case 45:
if (out[y * width + x] < out[(y + D) * width + x - D] || out[y * width + x] < out[(y - D) * width + x + D]) {
out[y * width + x] = 0;
}
break;
case 90:
if (out[y * width + x] < out[y * width + x + D] || out[y * width + x] < out[y * width + x - D]) {
out[y * width + x] = 0;
}
break;
case 135:
if (out[y * width + x] < out[(y + D) * width + x + D] || out[y * width + x] < out[(y - D) * width + x - D]) {
out[y * width + x] = 0;
}
break;
default:
break;
}
} | .text
.file "nonMaxSuppression.hip"
.globl _Z32__device_stub__nonMaxSuppressioniiiPhS_ # -- Begin function _Z32__device_stub__nonMaxSuppressioniiiPhS_
.p2align 4, 0x90
.type _Z32__device_stub__nonMaxSuppressioniiiPhS_,@function
_Z32__device_stub__nonMaxSuppressioniiiPhS_: # @_Z32__device_stub__nonMaxSuppressioniiiPhS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17nonMaxSuppressioniiiPhS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__nonMaxSuppressioniiiPhS_, .Lfunc_end0-_Z32__device_stub__nonMaxSuppressioniiiPhS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17nonMaxSuppressioniiiPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17nonMaxSuppressioniiiPhS_,@object # @_Z17nonMaxSuppressioniiiPhS_
.section .rodata,"a",@progbits
.globl _Z17nonMaxSuppressioniiiPhS_
.p2align 3, 0x0
_Z17nonMaxSuppressioniiiPhS_:
.quad _Z32__device_stub__nonMaxSuppressioniiiPhS_
.size _Z17nonMaxSuppressioniiiPhS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17nonMaxSuppressioniiiPhS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__nonMaxSuppressioniiiPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17nonMaxSuppressioniiiPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17nonMaxSuppressioniiiPhS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x164], P0 ; /* 0x0000590000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R3, c[0x0][0x164], R0 ; /* 0x0000590003027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ SHF.R.S32.HI R10, RZ, 0x1f, R2 ; /* 0x0000001fff0a7819 */
/* 0x000fe40000011402 */
/*00d0*/ IADD3 R8, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002087a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R9, R10, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000a097a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R2, P1, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fc60007f3e0ff */
/*0120*/ IMAD R3, R3, R4, c[0x0][0x164] ; /* 0x0000590003037624 */
/* 0x000fe400078e0204 */
/*0130*/ IMAD.MOV R4, RZ, RZ, -c[0x0][0x164] ; /* 0x80005900ff047624 */
/* 0x000fe400078e02ff */
/*0140*/ IMAD.IADD R5, R0, 0x1, R3.reuse ; /* 0x0000000100057824 */
/* 0x100fe400078e0203 */
/*0150*/ IMAD R7, R4, 0x2, R3 ; /* 0x0000000204077824 */
/* 0x000fe200078e0203 */
/*0160*/ IADD3.X R3, R10, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000a037a10 */
/* 0x000fe40000ffe4ff */
/*0170*/ IADD3 R4, P2, R5, c[0x0][0x178], RZ ; /* 0x00005e0005047a10 */
/* 0x000fe20007f5e0ff */
/*0180*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x000fc600078e0207 */
/*0190*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x17c], 0x1, P2 ; /* 0x00005f0005057a11 */
/* 0x000fe400010f0eff */
/*01a0*/ IADD3 R6, P3, R7, c[0x0][0x178], RZ ; /* 0x00005e0007067a10 */
/* 0x000fc80007f7e0ff */
/*01b0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x17c], 0x1, P3 ; /* 0x00005f0007077a11 */
/* 0x000fe400018f0eff */
/*01c0*/ ISETP.GT.AND P0, PT, R8, 0x59, PT ; /* 0x000000590800780c */
/* 0x004fda0003f04270 */
/*01d0*/ @P0 BRA 0x380 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*01f0*/ @!P0 BRA 0x2d0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.NE.AND P0, PT, R8, 0x2d, PT ; /* 0x0000002d0800780c */
/* 0x000fda0003f05270 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E.U8 R5, [R4.64+-0x1] ; /* 0xffffff0404057981 */
/* 0x000ea8000c1e1100 */
/*0230*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1100 */
/*0240*/ BSSY B0, 0x2b0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f06070 */
/*0260*/ @!P0 BRA 0x2a0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.U8 R7, [R6.64+0x1] ; /* 0x0000010406077981 */
/* 0x000ea4000c1e1100 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f06070 */
/*0290*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1100 */
/*02e0*/ LDG.E.U8 R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1100 */
/*02f0*/ BSSY B0, 0x360 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x004fda0003f06070 */
/*0310*/ @!P0 BRA 0x350 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0320*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1100 */
/*0330*/ ISETP.GE.U32.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fda0003f06070 */
/*0340*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ ISETP.NE.AND P0, PT, R8, 0x5a, PT ; /* 0x0000005a0800780c */
/* 0x000fda0003f05270 */
/*0390*/ @!P0 BRA 0x470 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.NE.AND P0, PT, R8, 0x87, PT ; /* 0x000000870800780c */
/* 0x000fda0003f05270 */
/*03b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E.U8 R4, [R4.64+0x1] ; /* 0x0000010404047981 */
/* 0x000ea8000c1e1100 */
/*03d0*/ LDG.E.U8 R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1100 */
/*03e0*/ BSSY B0, 0x450 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x004fda0003f06070 */
/*0400*/ @!P0 BRA 0x440 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E.U8 R6, [R6.64+-0x1] ; /* 0xffffff0406067981 */
/* 0x000ea4000c1e1100 */
/*0420*/ ISETP.GE.U32.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fda0003f06070 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1100 */
/*0480*/ LDG.E.U8 R0, [R2.64+0x1] ; /* 0x0000010402007981 */
/* 0x000ea2000c1e1100 */
/*0490*/ BSSY B0, 0x500 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*04a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f06070 */
/*04b0*/ @!P0 BRA 0x4f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E.U8 R0, [R2.64+-0x1] ; /* 0xffffff0402007981 */
/* 0x000ea4000c1e1100 */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f06070 */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17nonMaxSuppressioniiiPhS_
.globl _Z17nonMaxSuppressioniiiPhS_
.p2align 8
.type _Z17nonMaxSuppressioniiiPhS_,@function
_Z17nonMaxSuppressioniiiPhS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_31
s_load_b128 s[0:3], s[0:1], 0x10
v_mad_u64_u32 v[6:7], null, v4, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s0, 0
s_mov_b32 s1, exec_lo
global_load_u8 v8, v[0:1], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0x59, v8
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_15
s_mov_b32 s5, exec_lo
v_cmpx_lt_i16_e32 0x86, v8
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_8
s_mov_b32 s6, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u16_e32 0x87, v8
s_cbranch_execz .LBB0_7
v_mul_lo_u32 v0, s4, v4
s_mov_b32 s7, -1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v3, v0, s4, v2
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
v_ashrrev_i32_e32 v8, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v5, v[5:6], off offset:1
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v3, v5
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
global_load_u8 v2, v[4:5], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v3, v2
s_or_not1_b32 s7, vcc_lo, exec_lo
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s7, exec_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s6, exec_lo
.LBB0_8:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_14
s_mov_b32 s7, s0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u16_e32 0x5a, v8
s_cbranch_execz .LBB0_13
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s7, -1
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_u8 v2, v[0:1], off
global_load_u8 v3, v[0:1], off offset:1
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v2, v3
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_12
global_load_u8 v3, v[0:1], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v2, v3
s_or_not1_b32 s7, vcc_lo, exec_lo
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s8, s0, exec_lo
s_and_b32 s7, s7, exec_lo
s_or_b32 s7, s8, s7
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s6, s7, exec_lo
s_or_b32 s0, s0, s6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
.LBB0_15:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_29
s_mov_b32 s5, s0
s_mov_b32 s6, exec_lo
v_cmpx_lt_i16_e32 44, v8
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_22
s_mov_b32 s7, s0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u16_e32 45, v8
s_cbranch_execz .LBB0_21
v_mul_lo_u32 v0, s4, v4
s_mov_b32 s8, -1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v3, v0, s4, v2
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
v_ashrrev_i32_e32 v8, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v5, v[5:6], off offset:-1
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v3, v5
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_20
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
global_load_u8 v2, v[4:5], off offset:1
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v3, v2
s_or_not1_b32 s8, vcc_lo, exec_lo
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s7, s0, exec_lo
s_and_b32 s8, s8, exec_lo
s_or_b32 s7, s7, s8
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s5, s0, exec_lo
s_and_b32 s7, s7, exec_lo
s_or_b32 s5, s5, s7
.LBB0_22:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_28
s_mov_b32 s8, s5
s_mov_b32 s7, exec_lo
v_cmpx_eq_u16_e32 0, v8
s_cbranch_execz .LBB0_27
v_mul_lo_u32 v0, s4, v4
s_mov_b32 s9, -1
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v3, v0, s4, v2
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
v_ashrrev_i32_e32 v8, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_ge_u16_e64 v3, v5
s_cbranch_execz .LBB0_26
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
global_load_u8 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, v3, v2
s_or_not1_b32 s9, vcc_lo, exec_lo
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s5, exec_lo
s_and_b32 s3, s9, exec_lo
s_or_b32 s8, s2, s3
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s5, exec_lo
s_and_b32 s3, s8, exec_lo
s_or_b32 s5, s2, s3
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, s5, exec_lo
s_or_b32 s0, s0, s2
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_31
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_31:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17nonMaxSuppressioniiiPhS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17nonMaxSuppressioniiiPhS_, .Lfunc_end0-_Z17nonMaxSuppressioniiiPhS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17nonMaxSuppressioniiiPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17nonMaxSuppressioniiiPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000e0a4_00000000-6_nonMaxSuppression.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_
.type _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_, @function
_Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17nonMaxSuppressioniiiPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_, .-_Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_
.globl _Z17nonMaxSuppressioniiiPhS_
.type _Z17nonMaxSuppressioniiiPhS_, @function
_Z17nonMaxSuppressioniiiPhS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17nonMaxSuppressioniiiPhS_iiiPhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17nonMaxSuppressioniiiPhS_, .-_Z17nonMaxSuppressioniiiPhS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17nonMaxSuppressioniiiPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17nonMaxSuppressioniiiPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nonMaxSuppression.hip"
.globl _Z32__device_stub__nonMaxSuppressioniiiPhS_ # -- Begin function _Z32__device_stub__nonMaxSuppressioniiiPhS_
.p2align 4, 0x90
.type _Z32__device_stub__nonMaxSuppressioniiiPhS_,@function
_Z32__device_stub__nonMaxSuppressioniiiPhS_: # @_Z32__device_stub__nonMaxSuppressioniiiPhS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17nonMaxSuppressioniiiPhS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__nonMaxSuppressioniiiPhS_, .Lfunc_end0-_Z32__device_stub__nonMaxSuppressioniiiPhS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17nonMaxSuppressioniiiPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17nonMaxSuppressioniiiPhS_,@object # @_Z17nonMaxSuppressioniiiPhS_
.section .rodata,"a",@progbits
.globl _Z17nonMaxSuppressioniiiPhS_
.p2align 3, 0x0
_Z17nonMaxSuppressioniiiPhS_:
.quad _Z32__device_stub__nonMaxSuppressioniiiPhS_
.size _Z17nonMaxSuppressioniiiPhS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17nonMaxSuppressioniiiPhS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__nonMaxSuppressioniiiPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17nonMaxSuppressioniiiPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __global__ void nvrtc_add_kernel(const float* input, float* output, int n, float val) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) {
output[i] = input[i]+ val;
}
} | code for sm_80
Function : nvrtc_add_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FADD R7, R2, c[0x0][0x174] ; /* 0x00005d0002077621 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void nvrtc_add_kernel(const float* input, float* output, int n, float val) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) {
output[i] = input[i]+ val;
}
} | .file "tmpxft_000cc018_00000000-6_cuda_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif
.type _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif, @function
_Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq nvrtc_add_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif, .-_Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif
.globl nvrtc_add_kernel
.type nvrtc_add_kernel, @function
nvrtc_add_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size nvrtc_add_kernel, .-nvrtc_add_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "nvrtc_add_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq nvrtc_add_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void nvrtc_add_kernel(const float* input, float* output, int n, float val) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) {
output[i] = input[i]+ val;
}
} | #include <hip/hip_runtime.h>
extern "C" __global__ void nvrtc_add_kernel(const float* input, float* output, int n, float val) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) {
output[i] = input[i]+ val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void nvrtc_add_kernel(const float* input, float* output, int n, float val) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) {
output[i] = input[i]+ val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected nvrtc_add_kernel
.globl nvrtc_add_kernel
.p2align 8
.type nvrtc_add_kernel,@function
nvrtc_add_kernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel nvrtc_add_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size nvrtc_add_kernel, .Lfunc_end0-nvrtc_add_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: nvrtc_add_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: nvrtc_add_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void nvrtc_add_kernel(const float* input, float* output, int n, float val) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) {
output[i] = input[i]+ val;
}
} | .text
.file "cuda_add.hip"
.globl __device_stub__nvrtc_add_kernel # -- Begin function __device_stub__nvrtc_add_kernel
.p2align 4, 0x90
.type __device_stub__nvrtc_add_kernel,@function
__device_stub__nvrtc_add_kernel: # @__device_stub__nvrtc_add_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $nvrtc_add_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__nvrtc_add_kernel, .Lfunc_end0-__device_stub__nvrtc_add_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $nvrtc_add_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type nvrtc_add_kernel,@object # @nvrtc_add_kernel
.section .rodata,"a",@progbits
.globl nvrtc_add_kernel
.p2align 3, 0x0
nvrtc_add_kernel:
.quad __device_stub__nvrtc_add_kernel
.size nvrtc_add_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "nvrtc_add_kernel"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__nvrtc_add_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nvrtc_add_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : nvrtc_add_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FADD R7, R2, c[0x0][0x174] ; /* 0x00005d0002077621 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected nvrtc_add_kernel
.globl nvrtc_add_kernel
.p2align 8
.type nvrtc_add_kernel,@function
nvrtc_add_kernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel nvrtc_add_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size nvrtc_add_kernel, .Lfunc_end0-nvrtc_add_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: nvrtc_add_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: nvrtc_add_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cc018_00000000-6_cuda_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif
.type _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif, @function
_Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq nvrtc_add_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif, .-_Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif
.globl nvrtc_add_kernel
.type nvrtc_add_kernel, @function
nvrtc_add_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16nvrtc_add_kernelPKfPfifPKfPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size nvrtc_add_kernel, .-nvrtc_add_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "nvrtc_add_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq nvrtc_add_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_add.hip"
.globl __device_stub__nvrtc_add_kernel # -- Begin function __device_stub__nvrtc_add_kernel
.p2align 4, 0x90
.type __device_stub__nvrtc_add_kernel,@function
__device_stub__nvrtc_add_kernel: # @__device_stub__nvrtc_add_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $nvrtc_add_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__nvrtc_add_kernel, .Lfunc_end0-__device_stub__nvrtc_add_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $nvrtc_add_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type nvrtc_add_kernel,@object # @nvrtc_add_kernel
.section .rodata,"a",@progbits
.globl nvrtc_add_kernel
.p2align 3, 0x0
nvrtc_add_kernel:
.quad __device_stub__nvrtc_add_kernel
.size nvrtc_add_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "nvrtc_add_kernel"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__nvrtc_add_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nvrtc_add_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by Peter Rigole on 2019-03-08.
//
#include "Managed.cuh"
__host__
void *Managed::operator new(size_t len) {
void *ptr;
cudaMallocManaged(&ptr, len);
return ptr;
}
__host__
void Managed::operator delete(void *ptr) {
cudaFree(ptr);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by Peter Rigole on 2019-03-08.
//
#include "Managed.cuh"
__host__
void *Managed::operator new(size_t len) {
void *ptr;
cudaMallocManaged(&ptr, len);
return ptr;
}
__host__
void Managed::operator delete(void *ptr) {
cudaFree(ptr);
} | .file "tmpxft_0002af93_00000000-6_Managed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN7ManagednwEm
.type _ZN7ManagednwEm, @function
_ZN7ManagednwEm:
.LFB2027:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _ZN7ManagednwEm, .-_ZN7ManagednwEm
.globl _ZN7ManageddlEPv
.type _ZN7ManageddlEPv, @function
_ZN7ManageddlEPv:
.LFB2028:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _ZN7ManageddlEPv, .-_ZN7ManageddlEPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by Peter Rigole on 2019-03-08.
//
#include "Managed.cuh"
__host__
void *Managed::operator new(size_t len) {
void *ptr;
cudaMallocManaged(&ptr, len);
return ptr;
}
__host__
void Managed::operator delete(void *ptr) {
cudaFree(ptr);
} | //
// Created by Peter Rigole on 2019-03-08.
//
#include <hip/hip_runtime.h>
#include <stddef.h>
#ifndef AXONBITS_MANAGED_H
#define AXONBITS_MANAGED_H
// Managed Base Class -- inherit from this to automatically
// allocate objects in Unified Memory
class Managed {
public:
__host__
void *operator new(size_t);
__host__
void operator delete(void *);
};
#endif //AXONBITS_MANAGED_H |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by Peter Rigole on 2019-03-08.
//
#include <hip/hip_runtime.h>
#include <stddef.h>
#ifndef AXONBITS_MANAGED_H
#define AXONBITS_MANAGED_H
// Managed Base Class -- inherit from this to automatically
// allocate objects in Unified Memory
class Managed {
public:
__host__
void *operator new(size_t);
__host__
void operator delete(void *);
};
#endif //AXONBITS_MANAGED_H | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by Peter Rigole on 2019-03-08.
//
#include <hip/hip_runtime.h>
#include <stddef.h>
#ifndef AXONBITS_MANAGED_H
#define AXONBITS_MANAGED_H
// Managed Base Class -- inherit from this to automatically
// allocate objects in Unified Memory
class Managed {
public:
__host__
void *operator new(size_t);
__host__
void operator delete(void *);
};
#endif //AXONBITS_MANAGED_H | .text
.file "Managed.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002af93_00000000-6_Managed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN7ManagednwEm
.type _ZN7ManagednwEm, @function
_ZN7ManagednwEm:
.LFB2027:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _ZN7ManagednwEm, .-_ZN7ManagednwEm
.globl _ZN7ManageddlEPv
.type _ZN7ManageddlEPv, @function
_ZN7ManageddlEPv:
.LFB2028:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _ZN7ManageddlEPv, .-_ZN7ManageddlEPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Managed.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // From Appendix B.16 of the CUDA-C Programming Guide.
#include "stdio.h"
#include "cuda.h"
__global__ void helloCUDA(float f) {
printf("Hello thread %d, f=%f\n", threadIdx.x, f);
}
int main() {
helloCUDA<<<1, 5>>>(1.2345f);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z9helloCUDAf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ F2F.F64.F32 R2, c[0x0][0x160] ; /* 0x0000580000027b10 */
/* 0x000e620000201800 */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0080*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0004e60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0025e80000100a00 */
/*00b0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0015e60000100800 */
/*00c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x004fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fc40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0120*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0130*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x008fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // From Appendix B.16 of the CUDA-C Programming Guide.
#include "stdio.h"
#include "cuda.h"
__global__ void helloCUDA(float f) {
printf("Hello thread %d, f=%f\n", threadIdx.x, f);
}
int main() {
helloCUDA<<<1, 5>>>(1.2345f);
cudaDeviceReset();
return 0;
} | .file "tmpxft_000c9db2_00000000-6_b16-hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9helloCUDAff
.type _Z27__device_stub__Z9helloCUDAff, @function
_Z27__device_stub__Z9helloCUDAff:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9helloCUDAf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9helloCUDAff, .-_Z27__device_stub__Z9helloCUDAff
.globl _Z9helloCUDAf
.type _Z9helloCUDAf, @function
_Z9helloCUDAf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9helloCUDAff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9helloCUDAf, .-_Z9helloCUDAf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss .LC0(%rip), %xmm0
call _Z27__device_stub__Z9helloCUDAff
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9helloCUDAf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9helloCUDAf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1067320345
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // From Appendix B.16 of the CUDA-C Programming Guide.
#include "stdio.h"
#include "cuda.h"
__global__ void helloCUDA(float f) {
printf("Hello thread %d, f=%f\n", threadIdx.x, f);
}
int main() {
helloCUDA<<<1, 5>>>(1.2345f);
cudaDeviceReset();
return 0;
} | // From Appendix B.16 of the CUDA-C Programming Guide.
#include "stdio.h"
#include "hip/hip_runtime.h"
__global__ void helloCUDA(float f) {
printf("Hello thread %d, f=%f\n", threadIdx.x, f);
}
int main() {
helloCUDA<<<1, 5>>>(1.2345f);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // From Appendix B.16 of the CUDA-C Programming Guide.
#include "stdio.h"
#include "hip/hip_runtime.h"
__global__ void helloCUDA(float f) {
printf("Hello thread %d, f=%f\n", threadIdx.x, f);
}
int main() {
helloCUDA<<<1, 5>>>(1.2345f);
hipDeviceReset();
return 0;
} | .text
.file "b16-hello.hip"
.globl _Z24__device_stub__helloCUDAf # -- Begin function _Z24__device_stub__helloCUDAf
.p2align 4, 0x90
.type _Z24__device_stub__helloCUDAf,@function
_Z24__device_stub__helloCUDAf: # @_Z24__device_stub__helloCUDAf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9helloCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__helloCUDAf, .Lfunc_end0-_Z24__device_stub__helloCUDAf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $1067320345, 12(%rsp) # imm = 0x3F9E0419
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9helloCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9helloCUDAf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9helloCUDAf,@object # @_Z9helloCUDAf
.section .rodata,"a",@progbits
.globl _Z9helloCUDAf
.p2align 3, 0x0
_Z9helloCUDAf:
.quad _Z24__device_stub__helloCUDAf
.size _Z9helloCUDAf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9helloCUDAf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__helloCUDAf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9helloCUDAf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c9db2_00000000-6_b16-hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9helloCUDAff
.type _Z27__device_stub__Z9helloCUDAff, @function
_Z27__device_stub__Z9helloCUDAff:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9helloCUDAf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9helloCUDAff, .-_Z27__device_stub__Z9helloCUDAff
.globl _Z9helloCUDAf
.type _Z9helloCUDAf, @function
_Z9helloCUDAf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9helloCUDAff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9helloCUDAf, .-_Z9helloCUDAf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss .LC0(%rip), %xmm0
call _Z27__device_stub__Z9helloCUDAff
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9helloCUDAf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9helloCUDAf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1067320345
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "b16-hello.hip"
.globl _Z24__device_stub__helloCUDAf # -- Begin function _Z24__device_stub__helloCUDAf
.p2align 4, 0x90
.type _Z24__device_stub__helloCUDAf,@function
_Z24__device_stub__helloCUDAf: # @_Z24__device_stub__helloCUDAf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9helloCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__helloCUDAf, .Lfunc_end0-_Z24__device_stub__helloCUDAf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $1067320345, 12(%rsp) # imm = 0x3F9E0419
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9helloCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9helloCUDAf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9helloCUDAf,@object # @_Z9helloCUDAf
.section .rodata,"a",@progbits
.globl _Z9helloCUDAf
.p2align 3, 0x0
_Z9helloCUDAf:
.quad _Z24__device_stub__helloCUDAf
.size _Z9helloCUDAf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9helloCUDAf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__helloCUDAf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9helloCUDAf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#include <time.h>
/********************************************************************
CUDA Kernel
*********************************************************************/
__global__ void matrixMul (float* C, float* A, float* B, int TA)
{
/* calcul des coordonnees du point de C a calculer */
int i = blockIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
/* calcul de C[i][j] */
int cc = 0;
for (int k = 0; k < TA; ++ k)
cc += A[i * TA + k] * B[k * TA + j];
/* stockage */
C[i * TA + j] = cc;
}
/********************************************************************
Programme main
*********************************************************************/
int main (int argc, char** argv)
{
int i, j, TM, GRID_SIZE_X, GRID_SIZE_Y, BLOCK_SIZE_X;
cudaError_t cerror;
const int THREADS_PER_BLOCK = 1024;
//
/* pour le calcul du temps de traitement sur GPU */
float tc;
cudaEvent_t depart, arret;
cudaEventCreate(&depart);
cudaEventCreate(&arret);
/* valeurs par defaut */
TM = 2048;
/* TM peut etre lu comme arg1 de la commande */
if (argc > 1) {
TM = atoi(argv[1]);
}
GRID_SIZE_X = TM / THREADS_PER_BLOCK;
GRID_SIZE_Y = TM;
BLOCK_SIZE_X = THREADS_PER_BLOCK;
/* definiton de la grille et des blocs */
dim3 grid(GRID_SIZE_X, GRID_SIZE_Y);
dim3 block(BLOCK_SIZE_X);
printf("taille grille : %d - %d \n", GRID_SIZE_X, GRID_SIZE_Y);
printf("taille bloc : %d \n", BLOCK_SIZE_X);
/* allocation des matrices sur CPU */
unsigned int msize_A = TM * TM * sizeof(float);
unsigned int msize_B = TM * TM * sizeof(float);
unsigned int msize_C = TM * TM * sizeof(float);
float* h_A = (float*) malloc(msize_A);
float* h_B = (float*) malloc(msize_B);
float* h_C = (float*) malloc(msize_C);
/* initialisation des matrices avec des valeurs permettant de verifier le resultat*/
for (i = 0; i < TM; i++){
for (j = 0; j < TM; j++){
h_A[i * TM + j] = 1.0;
h_B[i * TM + j] = 1.0;
h_C[i * TM + j] = 0.0;
if (i == j) {
h_A[i * TM + j] = (float) (i + 1);
h_B[i * TM + j] = (float) (i + 1);
}
}
}
/* allocation des matrices sur GPU */
float *d_A; cudaMalloc((void**) &d_A, msize_A);
float *d_B; cudaMalloc((void**) &d_B, msize_B);
float *d_C; cudaMalloc((void**) &d_C, msize_C);
/* mesure du temps : top depart */
cudaEventRecord(depart, 0);
/* copie des matrives A et B depuis le CPU vers le GPU */
cudaMemcpy(d_A, h_A, msize_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, msize_B, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, msize_C, cudaMemcpyHostToDevice);
/* lancement des threads */
matrixMul<<< grid, block >>>(d_C, d_A, d_B, TM);
/* Recuperation valeur de retour GPU */
cerror = cudaGetLastError();
printf(" retour %d \n", (int) cerror);
/* copie de la matrice C depuis le GPU */
cudaMemcpy(h_C, d_C, msize_C, cudaMemcpyDeviceToHost);
/* mesure du temps */
cudaEventRecord(arret, 0);
cudaEventSynchronize(arret);
cudaEventElapsedTime(&tc, depart, arret);
printf("Temps calcul : %f seconde\n", tc / 1000.0);
/* verification du resultat */
for (i = 0; i < TM; i++) {
for (j = 0; j < TM; j++) {
if ((i == j) && (h_C[i * TM + j] != (float)((i + 1) * (i + 1) + TM - 1))) {
printf("Erreur i: %d j: %d %f\n", i, j, h_C[i * TM + j] ); exit(1);
}
else if ((i != j) && (h_C[i * TM + j] != (float)(i + j + TM))) {
printf("Erreur i: %d j: %d\n", i, j);
exit(1);
}
}
}
/* liberation de la memoire */
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaEventDestroy(depart);
cudaEventDestroy(arret);
} | code for sm_80
Function : _Z9matrixMulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002600 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*0090*/ IMAD R3, R4, c[0x0][0x178], RZ ; /* 0x00005e0004037a24 */
/* 0x002fce00078e02ff */
/*00a0*/ @!P0 BRA 0xf60 ; /* 0x00000eb000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00e0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fd20000000f00 */
/*0100*/ @!P0 BRA 0xe40 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0130*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0140*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0150*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0160*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fc60000000f00 */
/*0180*/ IMAD.WIDE R16, R2, R17, c[0x0][0x170] ; /* 0x00005c0002107625 */
/* 0x000fcc00078e0211 */
/*0190*/ @!P0 BRA 0xc30 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x870 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x0010a2000c1e1900 */
/*0200*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*0210*/ IMAD.WIDE R14, R3, 0x4, R12 ; /* 0x00000004030e7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0240*/ LDG.E R28, [R14.64+0x4] ; /* 0x000004040e1c7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0022e2000c1e1900 */
/*0260*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0270*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000b28000c1e1900 */
/*0290*/ LDG.E R21, [R14.64+0xc] ; /* 0x00000c040e157981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R9, [R14.64+0x10] ; /* 0x000010040e097981 */
/* 0x000ee2000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x020fc600078e020c */
/*02c0*/ LDG.E R18, [R14.64+0x14] ; /* 0x000014040e127981 */
/* 0x002f68000c1e1900 */
/*02d0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x0002e2000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x001fc600078e020c */
/*02f0*/ LDG.E R26, [R14.64+0x18] ; /* 0x000018040e1a7981 */
/* 0x000ee8000c1e1900 */
/*0300*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000124000c1e1900 */
/*0310*/ IMAD.WIDE R16, R0, 0x4, R16 ; /* 0x0000000400107825 */
/* 0x001fca00078e0210 */
/*0320*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000162000c1e1900 */
/*0330*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x002fc800078e0210 */
/*0340*/ FFMA R29, R25, R11, R10 ; /* 0x0000000b191d7223 */
/* 0x004fe4000000000a */
/*0350*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x0002a8000c1e1900 */
/*0360*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f100 */
/*0370*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fce00078e020c */
/*0380*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x001ee40000201400 */
/*0390*/ FFMA R29, R27, R28, R29 ; /* 0x0000001c1b1d7223 */
/* 0x008fe4000000001d */
/*03a0*/ LDG.E R28, [R14.64+0x1c] ; /* 0x00001c040e1c7981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x0000e2000c1e1900 */
/*03c0*/ F2I.TRUNC.NTZ R16, R29 ; /* 0x0000001d00107305 */
/* 0x000e70000020f100 */
/*03d0*/ I2F R12, R16 ; /* 0x00000010000c7306 */
/* 0x0023240000201400 */
/*03e0*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x002fc800078e020a */
/*03f0*/ FFMA R12, R23, R24, R12 ; /* 0x00000018170c7223 */
/* 0x010fe4000000000c */
/*0400*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000322000c1e1900 */
/*0420*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0430*/ I2F R10, R12 ; /* 0x0000000c000a7306 */
/* 0x0010640000201400 */
/*0440*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x001fca00078e0210 */
/*0450*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000122000c1e1900 */
/*0460*/ FFMA R20, R20, R21, R10 ; /* 0x0000001514147223 */
/* 0x002fc6000000000a */
/*0470*/ LDG.E R10, [R14.64+0x24] ; /* 0x000024040e0a7981 */
/* 0x000f22000c1e1900 */
/*0480*/ F2I.TRUNC.NTZ R29, R20 ; /* 0x00000014001d7305 */
/* 0x000e70000020f100 */
/*0490*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x002e620000201400 */
/*04a0*/ IMAD.WIDE R20, R0, 0x4, R12 ; /* 0x0000000400147825 */
/* 0x000fc400078e020c */
/*04b0*/ LDG.E R13, [R14.64+0x2c] ; /* 0x00002c040e0d7981 */
/* 0x001f24000c1e1900 */
/*04c0*/ FFMA R29, R22, R9, R29 ; /* 0x00000009161d7223 */
/* 0x002fe4000000001d */
/*04d0*/ LDG.E R9, [R14.64+0x28] ; /* 0x000028040e097981 */
/* 0x000f28000c1e1900 */
/*04e0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000122000c1e1900 */
/*04f0*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e62000020f100 */
/*0500*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fce00078e0214 */
/*0510*/ I2F R12, R29 ; /* 0x0000001d000c7306 */
/* 0x002f640000201400 */
/*0520*/ FFMA R18, R19, R18, R12 ; /* 0x0000001213127223 */
/* 0x020fe4000000000c */
/*0530*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000368000c1e1900 */
/*0540*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*0550*/ I2F R20, R18 ; /* 0x0000001200147306 */
/* 0x0010a40000201400 */
/*0560*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0570*/ FFMA R20, R25, R26, R20 ; /* 0x0000001a19147223 */
/* 0x004fe40000000014 */
/*0580*/ LDG.E R25, [R14.64+0x30] ; /* 0x000030040e197981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x0000a2000c1e1900 */
/*05a0*/ F2I.TRUNC.NTZ R29, R20 ; /* 0x00000014001d7305 */
/* 0x000e30000020f100 */
/*05b0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x001ee20000201400 */
/*05c0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc800078e0212 */
/*05d0*/ FFMA R29, R27, R28, R29 ; /* 0x0000001c1b1d7223 */
/* 0x008fe4000000001d */
/*05e0*/ LDG.E R28, [R14.64+0x34] ; /* 0x000034040e1c7981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x0008e2000c1e1900 */
/*0600*/ F2I.TRUNC.NTZ R17, R29 ; /* 0x0000001d00117305 */
/* 0x002e30000020f100 */
/*0610*/ I2F R18, R17 ; /* 0x0000001100127306 */
/* 0x0011240000201400 */
/*0620*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x001fc800078e0214 */
/*0630*/ FFMA R21, R24, R23, R18 ; /* 0x0000001718157223 */
/* 0x010fe40000000012 */
/*0640*/ LDG.E R24, [R14.64+0x38] ; /* 0x000038040e187981 */
/* 0x000f28000c1e1900 */
/*0650*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000122000c1e1900 */
/*0660*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fca00078e0210 */
/*0670*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x000f28000c1e1900 */
/*0680*/ LDG.E R16, [R14.64+0x3c] ; /* 0x00003c040e107981 */
/* 0x001f22000c1e1900 */
/*0690*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e30000020f100 */
/*06a0*/ I2F R20, R21 ; /* 0x0000001500147306 */
/* 0x001e240000201400 */
/*06b0*/ FFMA R10, R11, R10, R20 ; /* 0x0000000a0b0a7223 */
/* 0x001fcc0000000014 */
/*06c0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*06d0*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e240000201400 */
/*06e0*/ FFMA R9, R22, R9, R11 ; /* 0x0000000916097223 */
/* 0x001fcc000000000b */
/*06f0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0700*/ I2F R11, R9 ; /* 0x00000009000b7306 */
/* 0x001f640000201400 */
/*0710*/ FFMA R11, R12, R13, R11 ; /* 0x0000000d0c0b7223 */
/* 0x020fcc000000000b */
/*0720*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0730*/ I2F R12, R11 ; /* 0x0000000b000c7306 */
/* 0x001ea40000201400 */
/*0740*/ FFMA R12, R26, R25, R12 ; /* 0x000000191a0c7223 */
/* 0x004fcc000000000c */
/*0750*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0760*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001ee40000201400 */
/*0770*/ FFMA R13, R27, R28, R13 ; /* 0x0000001c1b0d7223 */
/* 0x008fcc000000000d */
/*0780*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0790*/ I2F R10, R13 ; /* 0x0000000d000a7306 */
/* 0x001f240000201400 */
/*07a0*/ FFMA R23, R23, R24, R10 ; /* 0x0000001817177223 */
/* 0x010fcc000000000a */
/*07b0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e30000020f100 */
/*07c0*/ I2F R9, R23 ; /* 0x0000001700097306 */
/* 0x001e220000201400 */
/*07d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ FFMA R9, R29, R16, R9 ; /* 0x000000101d097223 */
/* 0x001fcc0000000009 */
/*07f0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e22000020f100 */
/*0800*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0810*/ IADD3 R4, P2, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fe20007f5e0ff */
/*0820*/ IMAD.WIDE R16, R0, 0x4, R18 ; /* 0x0000000400107825 */
/* 0x000fc800078e0212 */
/*0830*/ I2F R10, R9 ; /* 0x00000009000a7306 */
/* 0x0010620000201400 */
/*0840*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fc600017fe4ff */
/*0860*/ @P1 BRA 0x1e0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0870*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0880*/ @!P1 BRA 0xc10 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0890*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*08a0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0004e2000c1e1900 */
/*08b0*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*08c0*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*08d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ee2000c1e1900 */
/*08e0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*08f0*/ LDG.E R9, [R12.64+0x4] ; /* 0x000004040c097981 */
/* 0x001f28000c1e1900 */
/*0900*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000122000c1e1900 */
/*0910*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0920*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f68000c1e1900 */
/*0930*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*0940*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*0950*/ LDG.E R27, [R12.64+0xc] ; /* 0x00000c040c1b7981 */
/* 0x000f28000c1e1900 */
/*0960*/ LDG.E R26, [R20.64] ; /* 0x00000004141a7981 */
/* 0x000322000c1e1900 */
/*0970*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x004fc600078e0214 */
/*0980*/ LDG.E R29, [R12.64+0x10] ; /* 0x000010040c1d7981 */
/* 0x0004a8000c1e1900 */
/*0990*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*09a0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0210 */
/*09b0*/ LDG.E R17, [R12.64+0x14] ; /* 0x000014040c117981 */
/* 0x0024a8000c1e1900 */
/*09c0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x0000a2000c1e1900 */
/*09d0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fcc00078e020e */
/*09e0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fe200078e0212 */
/*09f0*/ LDG.E R14, [R12.64+0x1c] ; /* 0x00001c040c0e7981 */
/* 0x0014a6000c1e1900 */
/*0a00*/ FFMA R15, R11, R23, R10 ; /* 0x000000170b0f7223 */
/* 0x008fe4000000000a */
/*0a10*/ LDG.E R11, [R12.64+0x18] ; /* 0x000018040c0b7981 */
/* 0x0004e8000c1e1900 */
/*0a20*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000e8000c1e1900 */
/*0a30*/ LDG.E R23, [R20.64] ; /* 0x0000000414177981 */
/* 0x000ee2000c1e1900 */
/*0a40*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*0a50*/ I2F R18, R15 ; /* 0x0000000f00127306 */
/* 0x001f240000201400 */
/*0a60*/ FFMA R9, R22, R9, R18 ; /* 0x0000000916097223 */
/* 0x010fcc0000000012 */
/*0a70*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0a80*/ I2F R22, R9 ; /* 0x0000000900167306 */
/* 0x001f640000201400 */
/*0a90*/ FFMA R22, R25, R24, R22 ; /* 0x0000001819167223 */
/* 0x020fcc0000000016 */
/*0aa0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e30000020f100 */
/*0ab0*/ I2F R18, R22 ; /* 0x0000001600127306 */
/* 0x001e240000201400 */
/*0ac0*/ FFMA R18, R26, R27, R18 ; /* 0x0000001b1a127223 */
/* 0x001fcc0000000012 */
/*0ad0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000eb0000020f100 */
/*0ae0*/ I2F R12, R18 ; /* 0x00000012000c7306 */
/* 0x004e240000201400 */
/*0af0*/ FFMA R12, R28, R29, R12 ; /* 0x0000001d1c0c7223 */
/* 0x001fcc000000000c */
/*0b00*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0b10*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001e240000201400 */
/*0b20*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x001fcc000000000d */
/*0b30*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0b40*/ I2F R9, R13 ; /* 0x0000000d00097306 */
/* 0x001ee20000201400 */
/*0b50*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fe20007f3e0ff */
/*0b60*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fe200078e0214 */
/*0b70*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0b80*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R9, R10, R11, R9 ; /* 0x0000000b0a097223 */
/* 0x008fcc0000000009 */
/*0bc0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0bd0*/ I2F R10, R9 ; /* 0x00000009000a7306 */
/* 0x001e240000201400 */
/*0be0*/ FFMA R14, R23, R14, R10 ; /* 0x0000000e170e7223 */
/* 0x001fcc000000000a */
/*0bf0*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0c00*/ I2F R10, R14 ; /* 0x0000000e000a7306 */
/* 0x0010640000201400 */
/*0c10*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0c20*/ @!P0 BRA 0xe40 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c30*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*0c40*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0010a2000c1e1900 */
/*0c50*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0c70*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0c80*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c90*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ee8000c1e1900 */
/*0ca0*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ee2000c1e1900 */
/*0cb0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*0cc0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*0cd0*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x000f22000c1e1900 */
/*0ce0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0214 */
/*0cf0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000f68000c1e1900 */
/*0d00*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x000f62000c1e1900 */
/*0d10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0d20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0d30*/ IADD3 R4, P1, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007f3e0ff */
/*0d40*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x001fe200078e020e */
/*0d50*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007ffe0ff */
/*0d60*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d70*/ FFMA R9, R9, R11, R10 ; /* 0x0000000b09097223 */
/* 0x006fcc000000000a */
/*0d80*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0d90*/ I2F R10, R9 ; /* 0x00000009000a7306 */
/* 0x001ee40000201400 */
/*0da0*/ FFMA R22, R23, R22, R10 ; /* 0x0000001617167223 */
/* 0x008fcc000000000a */
/*0db0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e30000020f100 */
/*0dc0*/ I2F R10, R22 ; /* 0x00000016000a7306 */
/* 0x001f240000201400 */
/*0dd0*/ FFMA R24, R25, R24, R10 ; /* 0x0000001819187223 */
/* 0x010fcc000000000a */
/*0de0*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e30000020f100 */
/*0df0*/ I2F R10, R24 ; /* 0x00000018000a7306 */
/* 0x001f640000201400 */
/*0e00*/ FFMA R26, R27, R26, R10 ; /* 0x0000001a1b1a7223 */
/* 0x020fcc000000000a */
/*0e10*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e30000020f100 */
/*0e20*/ I2F R10, R26 ; /* 0x0000001a000a7306 */
/* 0x0010640000201400 */
/*0e30*/ @P0 BRA 0xc30 ; /* 0xfffffdf000000947 */
/* 0x003fea000383ffff */
/*0e40*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e50*/ @!P0 BRA 0xf60 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0e60*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fe200000001ff */
/*0e70*/ IADD3 R6, R3, R8, RZ ; /* 0x0000000803067210 */
/* 0x000fe20007ffe0ff */
/*0e80*/ IMAD R8, R8, c[0x0][0x178], R2 ; /* 0x00005e0008087a24 */
/* 0x000fd000078e0202 */
/*0e90*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0ea0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fca00078e0209 */
/*0eb0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0ec0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0006a2000c1e1900 */
/*0ed0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ee0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ef0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0f00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x008fc80007f3e0ff */
/*0f10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0f20*/ FFMA R4, R11, R4, R10 ; /* 0x000000040b047223 */
/* 0x006fcc000000000a */
/*0f30*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0f40*/ I2F R10, R4 ; /* 0x00000004000a7306 */
/* 0x0010620000201400 */
/*0f50*/ @P0 BRA 0xeb0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0f60*/ IADD3 R2, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x000fe40007ffe0ff */
/*0f70*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0f80*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0f90*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe2000c101904 */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#include <time.h>
/********************************************************************
CUDA Kernel
*********************************************************************/
__global__ void matrixMul (float* C, float* A, float* B, int TA)
{
/* calcul des coordonnees du point de C a calculer */
int i = blockIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
/* calcul de C[i][j] */
int cc = 0;
for (int k = 0; k < TA; ++ k)
cc += A[i * TA + k] * B[k * TA + j];
/* stockage */
C[i * TA + j] = cc;
}
/********************************************************************
Programme main
*********************************************************************/
int main (int argc, char** argv)
{
int i, j, TM, GRID_SIZE_X, GRID_SIZE_Y, BLOCK_SIZE_X;
cudaError_t cerror;
const int THREADS_PER_BLOCK = 1024;
//
/* pour le calcul du temps de traitement sur GPU */
float tc;
cudaEvent_t depart, arret;
cudaEventCreate(&depart);
cudaEventCreate(&arret);
/* valeurs par defaut */
TM = 2048;
/* TM peut etre lu comme arg1 de la commande */
if (argc > 1) {
TM = atoi(argv[1]);
}
GRID_SIZE_X = TM / THREADS_PER_BLOCK;
GRID_SIZE_Y = TM;
BLOCK_SIZE_X = THREADS_PER_BLOCK;
/* definiton de la grille et des blocs */
dim3 grid(GRID_SIZE_X, GRID_SIZE_Y);
dim3 block(BLOCK_SIZE_X);
printf("taille grille : %d - %d \n", GRID_SIZE_X, GRID_SIZE_Y);
printf("taille bloc : %d \n", BLOCK_SIZE_X);
/* allocation des matrices sur CPU */
unsigned int msize_A = TM * TM * sizeof(float);
unsigned int msize_B = TM * TM * sizeof(float);
unsigned int msize_C = TM * TM * sizeof(float);
float* h_A = (float*) malloc(msize_A);
float* h_B = (float*) malloc(msize_B);
float* h_C = (float*) malloc(msize_C);
/* initialisation des matrices avec des valeurs permettant de verifier le resultat*/
for (i = 0; i < TM; i++){
for (j = 0; j < TM; j++){
h_A[i * TM + j] = 1.0;
h_B[i * TM + j] = 1.0;
h_C[i * TM + j] = 0.0;
if (i == j) {
h_A[i * TM + j] = (float) (i + 1);
h_B[i * TM + j] = (float) (i + 1);
}
}
}
/* allocation des matrices sur GPU */
float *d_A; cudaMalloc((void**) &d_A, msize_A);
float *d_B; cudaMalloc((void**) &d_B, msize_B);
float *d_C; cudaMalloc((void**) &d_C, msize_C);
/* mesure du temps : top depart */
cudaEventRecord(depart, 0);
/* copie des matrives A et B depuis le CPU vers le GPU */
cudaMemcpy(d_A, h_A, msize_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, msize_B, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, msize_C, cudaMemcpyHostToDevice);
/* lancement des threads */
matrixMul<<< grid, block >>>(d_C, d_A, d_B, TM);
/* Recuperation valeur de retour GPU */
cerror = cudaGetLastError();
printf(" retour %d \n", (int) cerror);
/* copie de la matrice C depuis le GPU */
cudaMemcpy(h_C, d_C, msize_C, cudaMemcpyDeviceToHost);
/* mesure du temps */
cudaEventRecord(arret, 0);
cudaEventSynchronize(arret);
cudaEventElapsedTime(&tc, depart, arret);
printf("Temps calcul : %f seconde\n", tc / 1000.0);
/* verification du resultat */
for (i = 0; i < TM; i++) {
for (j = 0; j < TM; j++) {
if ((i == j) && (h_C[i * TM + j] != (float)((i + 1) * (i + 1) + TM - 1))) {
printf("Erreur i: %d j: %d %f\n", i, j, h_C[i * TM + j] ); exit(1);
}
else if ((i != j) && (h_C[i * TM + j] != (float)(i + j + TM))) {
printf("Erreur i: %d j: %d\n", i, j);
exit(1);
}
}
}
/* liberation de la memoire */
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaEventDestroy(depart);
cudaEventDestroy(arret);
} | .file "tmpxft_00080773_00000000-6_mul_mat_v1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
.globl _Z9matrixMulPfS_S_i
.type _Z9matrixMulPfS_S_i, @function
_Z9matrixMulPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9matrixMulPfS_S_i, .-_Z9matrixMulPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "taille grille : %d - %d \n"
.LC1:
.string "taille bloc : %d \n"
.LC4:
.string " retour %d \n"
.LC6:
.string "Temps calcul : %f seconde\n"
.LC7:
.string "Erreur i: %d j: %d %f\n"
.LC8:
.string "Erreur i: %d j: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %r12d
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $2048, %ebp
cmpl $1, %r12d
jg .L37
.L12:
leal 1023(%rbp), %edx
testl %ebp, %ebp
cmovns %ebp, %edx
sarl $10, %edx
movl %ebp, %r12d
movl %edx, 48(%rsp)
movl %ebp, 52(%rsp)
movl $1, 56(%rsp)
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %eax
imull %ebp, %eax
leal 0(,%rax,4), %r15d
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
testl %ebp, %ebp
jle .L13
movslq %ebp, %r8
leaq 0(,%r8,4), %r9
movq %r14, %rsi
movq %r13, %rcx
movq %rax, %rdi
movl $0, %edx
movss .LC2(%rip), %xmm0
jmp .L14
.L37:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L12
.L15:
addq $1, %rax
cmpq %r8, %rax
je .L38
.L16:
movss %xmm0, (%rsi,%rax,4)
movss %xmm0, (%rcx,%rax,4)
movl $0x00000000, (%rdi,%rax,4)
cmpl %eax, %edx
jne .L15
pxor %xmm1, %xmm1
cvtsi2ssl %r10d, %xmm1
movss %xmm1, (%rsi,%rax,4)
movss %xmm1, (%rcx,%rax,4)
jmp .L15
.L38:
addl $1, %edx
addq %r9, %rsi
addq %r9, %rcx
addq %r9, %rdi
cmpl %edx, %ebp
je .L13
.L14:
movl $0, %eax
leal 1(%rdx), %r10d
jmp .L16
.L13:
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L17:
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %r12d, %edi
movl $0, %esi
movl $0, %edx
leal -1(%r12), %r10d
movl $0, %r9d
testl %ebp, %ebp
jg .L18
.L19:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %ebp, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
jmp .L17
.L42:
leal (%rcx,%rsi), %eax
cltq
movss (%rbx,%rax,4), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r8d, %xmm1
ucomiss %xmm1, %xmm0
jp .L29
jne .L29
.L21:
leal 1(%rcx), %eax
cmpl %eax, %ebp
je .L41
movl %eax, %ecx
.L24:
cmpl %ecx, %edx
je .L42
leal (%rcx,%rsi), %eax
cltq
leal (%rcx,%rdi), %r11d
pxor %xmm0, %xmm0
cvtsi2ssl %r11d, %xmm0
ucomiss (%rbx,%rax,4), %xmm0
jp .L30
je .L21
.L30:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
leal 1(%rdx), %eax
addl %r12d, %esi
addl $1, %edi
cmpl %ecx, %edx
je .L19
movl %eax, %edx
.L18:
leal 1(%rdx), %r8d
imull %r8d, %r8d
addl %r10d, %r8d
movl %r9d, %ecx
jmp .L24
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9matrixMulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#include <time.h>
/********************************************************************
CUDA Kernel
*********************************************************************/
__global__ void matrixMul (float* C, float* A, float* B, int TA)
{
/* calcul des coordonnees du point de C a calculer */
int i = blockIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
/* calcul de C[i][j] */
int cc = 0;
for (int k = 0; k < TA; ++ k)
cc += A[i * TA + k] * B[k * TA + j];
/* stockage */
C[i * TA + j] = cc;
}
/********************************************************************
Programme main
*********************************************************************/
int main (int argc, char** argv)
{
int i, j, TM, GRID_SIZE_X, GRID_SIZE_Y, BLOCK_SIZE_X;
cudaError_t cerror;
const int THREADS_PER_BLOCK = 1024;
//
/* pour le calcul du temps de traitement sur GPU */
float tc;
cudaEvent_t depart, arret;
cudaEventCreate(&depart);
cudaEventCreate(&arret);
/* valeurs par defaut */
TM = 2048;
/* TM peut etre lu comme arg1 de la commande */
if (argc > 1) {
TM = atoi(argv[1]);
}
GRID_SIZE_X = TM / THREADS_PER_BLOCK;
GRID_SIZE_Y = TM;
BLOCK_SIZE_X = THREADS_PER_BLOCK;
/* definiton de la grille et des blocs */
dim3 grid(GRID_SIZE_X, GRID_SIZE_Y);
dim3 block(BLOCK_SIZE_X);
printf("taille grille : %d - %d \n", GRID_SIZE_X, GRID_SIZE_Y);
printf("taille bloc : %d \n", BLOCK_SIZE_X);
/* allocation des matrices sur CPU */
unsigned int msize_A = TM * TM * sizeof(float);
unsigned int msize_B = TM * TM * sizeof(float);
unsigned int msize_C = TM * TM * sizeof(float);
float* h_A = (float*) malloc(msize_A);
float* h_B = (float*) malloc(msize_B);
float* h_C = (float*) malloc(msize_C);
/* initialisation des matrices avec des valeurs permettant de verifier le resultat*/
for (i = 0; i < TM; i++){
for (j = 0; j < TM; j++){
h_A[i * TM + j] = 1.0;
h_B[i * TM + j] = 1.0;
h_C[i * TM + j] = 0.0;
if (i == j) {
h_A[i * TM + j] = (float) (i + 1);
h_B[i * TM + j] = (float) (i + 1);
}
}
}
/* allocation des matrices sur GPU */
float *d_A; cudaMalloc((void**) &d_A, msize_A);
float *d_B; cudaMalloc((void**) &d_B, msize_B);
float *d_C; cudaMalloc((void**) &d_C, msize_C);
/* mesure du temps : top depart */
cudaEventRecord(depart, 0);
/* copie des matrives A et B depuis le CPU vers le GPU */
cudaMemcpy(d_A, h_A, msize_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, msize_B, cudaMemcpyHostToDevice);
cudaMemcpy(d_C, h_C, msize_C, cudaMemcpyHostToDevice);
/* lancement des threads */
matrixMul<<< grid, block >>>(d_C, d_A, d_B, TM);
/* Recuperation valeur de retour GPU */
cerror = cudaGetLastError();
printf(" retour %d \n", (int) cerror);
/* copie de la matrice C depuis le GPU */
cudaMemcpy(h_C, d_C, msize_C, cudaMemcpyDeviceToHost);
/* mesure du temps */
cudaEventRecord(arret, 0);
cudaEventSynchronize(arret);
cudaEventElapsedTime(&tc, depart, arret);
printf("Temps calcul : %f seconde\n", tc / 1000.0);
/* verification du resultat */
for (i = 0; i < TM; i++) {
for (j = 0; j < TM; j++) {
if ((i == j) && (h_C[i * TM + j] != (float)((i + 1) * (i + 1) + TM - 1))) {
printf("Erreur i: %d j: %d %f\n", i, j, h_C[i * TM + j] ); exit(1);
}
else if ((i != j) && (h_C[i * TM + j] != (float)(i + j + TM))) {
printf("Erreur i: %d j: %d\n", i, j);
exit(1);
}
}
}
/* liberation de la memoire */
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaEventDestroy(depart);
cudaEventDestroy(arret);
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <time.h>
/********************************************************************
CUDA Kernel
*********************************************************************/
__global__ void matrixMul (float* C, float* A, float* B, int TA)
{
/* calcul des coordonnees du point de C a calculer */
int i = blockIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
/* calcul de C[i][j] */
int cc = 0;
for (int k = 0; k < TA; ++ k)
cc += A[i * TA + k] * B[k * TA + j];
/* stockage */
C[i * TA + j] = cc;
}
/********************************************************************
Programme main
*********************************************************************/
int main (int argc, char** argv)
{
int i, j, TM, GRID_SIZE_X, GRID_SIZE_Y, BLOCK_SIZE_X;
hipError_t cerror;
const int THREADS_PER_BLOCK = 1024;
//
/* pour le calcul du temps de traitement sur GPU */
float tc;
hipEvent_t depart, arret;
hipEventCreate(&depart);
hipEventCreate(&arret);
/* valeurs par defaut */
TM = 2048;
/* TM peut etre lu comme arg1 de la commande */
if (argc > 1) {
TM = atoi(argv[1]);
}
GRID_SIZE_X = TM / THREADS_PER_BLOCK;
GRID_SIZE_Y = TM;
BLOCK_SIZE_X = THREADS_PER_BLOCK;
/* definiton de la grille et des blocs */
dim3 grid(GRID_SIZE_X, GRID_SIZE_Y);
dim3 block(BLOCK_SIZE_X);
printf("taille grille : %d - %d \n", GRID_SIZE_X, GRID_SIZE_Y);
printf("taille bloc : %d \n", BLOCK_SIZE_X);
/* allocation des matrices sur CPU */
unsigned int msize_A = TM * TM * sizeof(float);
unsigned int msize_B = TM * TM * sizeof(float);
unsigned int msize_C = TM * TM * sizeof(float);
float* h_A = (float*) malloc(msize_A);
float* h_B = (float*) malloc(msize_B);
float* h_C = (float*) malloc(msize_C);
/* initialisation des matrices avec des valeurs permettant de verifier le resultat*/
for (i = 0; i < TM; i++){
for (j = 0; j < TM; j++){
h_A[i * TM + j] = 1.0;
h_B[i * TM + j] = 1.0;
h_C[i * TM + j] = 0.0;
if (i == j) {
h_A[i * TM + j] = (float) (i + 1);
h_B[i * TM + j] = (float) (i + 1);
}
}
}
/* allocation des matrices sur GPU */
float *d_A; hipMalloc((void**) &d_A, msize_A);
float *d_B; hipMalloc((void**) &d_B, msize_B);
float *d_C; hipMalloc((void**) &d_C, msize_C);
/* mesure du temps : top depart */
hipEventRecord(depart, 0);
/* copie des matrives A et B depuis le CPU vers le GPU */
hipMemcpy(d_A, h_A, msize_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, msize_B, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, msize_C, hipMemcpyHostToDevice);
/* lancement des threads */
matrixMul<<< grid, block >>>(d_C, d_A, d_B, TM);
/* Recuperation valeur de retour GPU */
cerror = hipGetLastError();
printf(" retour %d \n", (int) cerror);
/* copie de la matrice C depuis le GPU */
hipMemcpy(h_C, d_C, msize_C, hipMemcpyDeviceToHost);
/* mesure du temps */
hipEventRecord(arret, 0);
hipEventSynchronize(arret);
hipEventElapsedTime(&tc, depart, arret);
printf("Temps calcul : %f seconde\n", tc / 1000.0);
/* verification du resultat */
for (i = 0; i < TM; i++) {
for (j = 0; j < TM; j++) {
if ((i == j) && (h_C[i * TM + j] != (float)((i + 1) * (i + 1) + TM - 1))) {
printf("Erreur i: %d j: %d %f\n", i, j, h_C[i * TM + j] ); exit(1);
}
else if ((i != j) && (h_C[i * TM + j] != (float)(i + j + TM))) {
printf("Erreur i: %d j: %d\n", i, j);
exit(1);
}
}
}
/* liberation de la memoire */
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventDestroy(depart);
hipEventDestroy(arret);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <time.h>
/********************************************************************
CUDA Kernel
*********************************************************************/
__global__ void matrixMul (float* C, float* A, float* B, int TA)
{
/* calcul des coordonnees du point de C a calculer */
int i = blockIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
/* calcul de C[i][j] */
int cc = 0;
for (int k = 0; k < TA; ++ k)
cc += A[i * TA + k] * B[k * TA + j];
/* stockage */
C[i * TA + j] = cc;
}
/********************************************************************
Programme main
*********************************************************************/
int main (int argc, char** argv)
{
int i, j, TM, GRID_SIZE_X, GRID_SIZE_Y, BLOCK_SIZE_X;
hipError_t cerror;
const int THREADS_PER_BLOCK = 1024;
//
/* pour le calcul du temps de traitement sur GPU */
float tc;
hipEvent_t depart, arret;
hipEventCreate(&depart);
hipEventCreate(&arret);
/* valeurs par defaut */
TM = 2048;
/* TM peut etre lu comme arg1 de la commande */
if (argc > 1) {
TM = atoi(argv[1]);
}
GRID_SIZE_X = TM / THREADS_PER_BLOCK;
GRID_SIZE_Y = TM;
BLOCK_SIZE_X = THREADS_PER_BLOCK;
/* definiton de la grille et des blocs */
dim3 grid(GRID_SIZE_X, GRID_SIZE_Y);
dim3 block(BLOCK_SIZE_X);
printf("taille grille : %d - %d \n", GRID_SIZE_X, GRID_SIZE_Y);
printf("taille bloc : %d \n", BLOCK_SIZE_X);
/* allocation des matrices sur CPU */
unsigned int msize_A = TM * TM * sizeof(float);
unsigned int msize_B = TM * TM * sizeof(float);
unsigned int msize_C = TM * TM * sizeof(float);
float* h_A = (float*) malloc(msize_A);
float* h_B = (float*) malloc(msize_B);
float* h_C = (float*) malloc(msize_C);
/* initialisation des matrices avec des valeurs permettant de verifier le resultat*/
for (i = 0; i < TM; i++){
for (j = 0; j < TM; j++){
h_A[i * TM + j] = 1.0;
h_B[i * TM + j] = 1.0;
h_C[i * TM + j] = 0.0;
if (i == j) {
h_A[i * TM + j] = (float) (i + 1);
h_B[i * TM + j] = (float) (i + 1);
}
}
}
/* allocation des matrices sur GPU */
float *d_A; hipMalloc((void**) &d_A, msize_A);
float *d_B; hipMalloc((void**) &d_B, msize_B);
float *d_C; hipMalloc((void**) &d_C, msize_C);
/* mesure du temps : top depart */
hipEventRecord(depart, 0);
/* copie des matrives A et B depuis le CPU vers le GPU */
hipMemcpy(d_A, h_A, msize_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, msize_B, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, msize_C, hipMemcpyHostToDevice);
/* lancement des threads */
matrixMul<<< grid, block >>>(d_C, d_A, d_B, TM);
/* Recuperation valeur de retour GPU */
cerror = hipGetLastError();
printf(" retour %d \n", (int) cerror);
/* copie de la matrice C depuis le GPU */
hipMemcpy(h_C, d_C, msize_C, hipMemcpyDeviceToHost);
/* mesure du temps */
hipEventRecord(arret, 0);
hipEventSynchronize(arret);
hipEventElapsedTime(&tc, depart, arret);
printf("Temps calcul : %f seconde\n", tc / 1000.0);
/* verification du resultat */
for (i = 0; i < TM; i++) {
for (j = 0; j < TM; j++) {
if ((i == j) && (h_C[i * TM + j] != (float)((i + 1) * (i + 1) + TM - 1))) {
printf("Erreur i: %d j: %d %f\n", i, j, h_C[i * TM + j] ); exit(1);
}
else if ((i != j) && (h_C[i * TM + j] != (float)(i + j + TM))) {
printf("Erreur i: %d j: %d\n", i, j);
exit(1);
}
}
}
/* liberation de la memoire */
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventDestroy(depart);
hipEventDestroy(arret);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPfS_S_i
.globl _Z9matrixMulPfS_S_i
.p2align 8
.type _Z9matrixMulPfS_S_i,@function
_Z9matrixMulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s8, 1
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
s_mul_i32 s2, s15, s8
v_mov_b32_e32 v0, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v2, v1
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_mov_b32 s4, s8
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
s_load_b32 s5, s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_i32_e32 v0, v0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 4
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s8, v2
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPfS_S_i, .Lfunc_end0-_Z9matrixMulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <time.h>
/********************************************************************
CUDA Kernel
*********************************************************************/
__global__ void matrixMul (float* C, float* A, float* B, int TA)
{
/* calcul des coordonnees du point de C a calculer */
int i = blockIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
/* calcul de C[i][j] */
int cc = 0;
for (int k = 0; k < TA; ++ k)
cc += A[i * TA + k] * B[k * TA + j];
/* stockage */
C[i * TA + j] = cc;
}
/********************************************************************
Programme main
*********************************************************************/
int main (int argc, char** argv)
{
int i, j, TM, GRID_SIZE_X, GRID_SIZE_Y, BLOCK_SIZE_X;
hipError_t cerror;
const int THREADS_PER_BLOCK = 1024;
//
/* pour le calcul du temps de traitement sur GPU */
float tc;
hipEvent_t depart, arret;
hipEventCreate(&depart);
hipEventCreate(&arret);
/* valeurs par defaut */
TM = 2048;
/* TM peut etre lu comme arg1 de la commande */
if (argc > 1) {
TM = atoi(argv[1]);
}
GRID_SIZE_X = TM / THREADS_PER_BLOCK;
GRID_SIZE_Y = TM;
BLOCK_SIZE_X = THREADS_PER_BLOCK;
/* definiton de la grille et des blocs */
dim3 grid(GRID_SIZE_X, GRID_SIZE_Y);
dim3 block(BLOCK_SIZE_X);
printf("taille grille : %d - %d \n", GRID_SIZE_X, GRID_SIZE_Y);
printf("taille bloc : %d \n", BLOCK_SIZE_X);
/* allocation des matrices sur CPU */
unsigned int msize_A = TM * TM * sizeof(float);
unsigned int msize_B = TM * TM * sizeof(float);
unsigned int msize_C = TM * TM * sizeof(float);
float* h_A = (float*) malloc(msize_A);
float* h_B = (float*) malloc(msize_B);
float* h_C = (float*) malloc(msize_C);
/* initialisation des matrices avec des valeurs permettant de verifier le resultat*/
for (i = 0; i < TM; i++){
for (j = 0; j < TM; j++){
h_A[i * TM + j] = 1.0;
h_B[i * TM + j] = 1.0;
h_C[i * TM + j] = 0.0;
if (i == j) {
h_A[i * TM + j] = (float) (i + 1);
h_B[i * TM + j] = (float) (i + 1);
}
}
}
/* allocation des matrices sur GPU */
float *d_A; hipMalloc((void**) &d_A, msize_A);
float *d_B; hipMalloc((void**) &d_B, msize_B);
float *d_C; hipMalloc((void**) &d_C, msize_C);
/* mesure du temps : top depart */
hipEventRecord(depart, 0);
/* copie des matrives A et B depuis le CPU vers le GPU */
hipMemcpy(d_A, h_A, msize_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, msize_B, hipMemcpyHostToDevice);
hipMemcpy(d_C, h_C, msize_C, hipMemcpyHostToDevice);
/* lancement des threads */
matrixMul<<< grid, block >>>(d_C, d_A, d_B, TM);
/* Recuperation valeur de retour GPU */
cerror = hipGetLastError();
printf(" retour %d \n", (int) cerror);
/* copie de la matrice C depuis le GPU */
hipMemcpy(h_C, d_C, msize_C, hipMemcpyDeviceToHost);
/* mesure du temps */
hipEventRecord(arret, 0);
hipEventSynchronize(arret);
hipEventElapsedTime(&tc, depart, arret);
printf("Temps calcul : %f seconde\n", tc / 1000.0);
/* verification du resultat */
for (i = 0; i < TM; i++) {
for (j = 0; j < TM; j++) {
if ((i == j) && (h_C[i * TM + j] != (float)((i + 1) * (i + 1) + TM - 1))) {
printf("Erreur i: %d j: %d %f\n", i, j, h_C[i * TM + j] ); exit(1);
}
else if ((i != j) && (h_C[i * TM + j] != (float)(i + j + TM))) {
printf("Erreur i: %d j: %d\n", i, j);
exit(1);
}
}
}
/* liberation de la memoire */
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventDestroy(depart);
hipEventDestroy(arret);
} | .text
.file "mul_mat_v1.hip"
.globl _Z24__device_stub__matrixMulPfS_S_i # -- Begin function _Z24__device_stub__matrixMulPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPfS_S_i,@function
_Z24__device_stub__matrixMulPfS_S_i: # @_Z24__device_stub__matrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPfS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $2048, %edx # imm = 0x800
cmpl $2, %ebp
jl .LBB1_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rdx
.LBB1_2:
movq %rdx, 8(%rsp) # 8-byte Spill
leal 1023(%rdx), %esi
testl %edx, %edx
cmovnsl %edx, %esi
sarl $10, %esi
movq %rdx, %rax
shlq $32, %rax
orq %rsi, %rax
movq %rax, 88(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %ebx
imull %ebx, %ebx
shll $2, %ebx
movq %rbx, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, 96(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq 8(%rsp), %rcx # 8-byte Reload
movq %rax, 80(%rsp) # 8-byte Spill
movl %ecx, %r13d
testl %ecx, %ecx
jle .LBB1_9
# %bb.3: # %.preheader110.lr.ph
leaq (,%r13,4), %rbp
xorl %r15d, %r15d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_4 Depth=1
incq %r15
movq 8(%rsp), %rcx # 8-byte Reload
addl %ecx, %r14d
cmpq %r13, %r15
je .LBB1_9
.LBB1_4: # %.preheader110
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movl %r14d, %eax
movq 32(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq 40(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %rbx
movl %ecx, %eax
imull %r15d, %eax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdi
leal 1(%r15), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 72(%rsp) # 4-byte Spill
xorl %esi, %esi
movq %rbp, %rdx
callq memset@PLT
xorl %eax, %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=2
incq %rax
cmpq %rax, %r13
je .LBB1_8
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1065353216, (%r12,%rax,4) # imm = 0x3F800000
cmpq %rax, %r15
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=2
movss 72(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx,%rax,4)
movss %xmm0, (%r12,%rax,4)
jmp .LBB1_7
.LBB1_9: # %._crit_edge117
leaq 56(%rsp), %rdi
movq 96(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
movq 88(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 16(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z9matrixMulPfS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
callq hipGetLastError
xorl %ebp, %ebp
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 8(%rsp), %r10 # 8-byte Reload
testl %r10d, %r10d
jle .LBB1_20
# %bb.12: # %.preheader.lr.ph
leal -1(%r10), %eax
movq %r13, %rcx
xorl %edi, %edi
xorl %esi, %esi
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_19: # %._crit_edge120
# in Loop: Header=BB1_13 Depth=1
incq %rsi
addl %r10d, %ebp
decq %rdi
incq %rcx
cmpq %r13, %rsi
je .LBB1_20
.LBB1_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
movl %ebp, %edx
leaq (%rbx,%rdx,4), %r8
leal 1(%rsi), %edx
imull %edx, %edx
addl %eax, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
xorl %edx, %edx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_17: # %.critedge
# in Loop: Header=BB1_14 Depth=2
leal (%rcx,%rdx), %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9d, %xmm1
movss (%r8,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm2
jne .LBB1_22
jp .LBB1_22
.LBB1_18: # in Loop: Header=BB1_14 Depth=2
incq %rdx
cmpq %rdx, %r13
je .LBB1_19
.LBB1_14: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
movq %rdi, %r9
addq %rdx, %r9
jne .LBB1_17
# %bb.15: # in Loop: Header=BB1_14 Depth=2
movss (%r8,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_21
jp .LBB1_21
# %bb.16: # in Loop: Header=BB1_14 Depth=2
testq %r9, %r9
jne .LBB1_17
jmp .LBB1_18
.LBB1_20: # %._crit_edge122
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 272
movl $.L.str.5, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_21:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
movb $1, %al
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPfS_S_i,@object # @_Z9matrixMulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixMulPfS_S_i
.p2align 3, 0x0
_Z9matrixMulPfS_S_i:
.quad _Z24__device_stub__matrixMulPfS_S_i
.size _Z9matrixMulPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "taille grille : %d - %d \n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "taille bloc : %d \n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " retour %d \n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Temps calcul : %f seconde\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Erreur i: %d j: %d %f\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Erreur i: %d j: %d\n"
.size .L.str.5, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002600 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*0090*/ IMAD R3, R4, c[0x0][0x178], RZ ; /* 0x00005e0004037a24 */
/* 0x002fce00078e02ff */
/*00a0*/ @!P0 BRA 0xf60 ; /* 0x00000eb000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00e0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fd20000000f00 */
/*0100*/ @!P0 BRA 0xe40 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0130*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0140*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0150*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0160*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fc60000000f00 */
/*0180*/ IMAD.WIDE R16, R2, R17, c[0x0][0x170] ; /* 0x00005c0002107625 */
/* 0x000fcc00078e0211 */
/*0190*/ @!P0 BRA 0xc30 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x870 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x0010a2000c1e1900 */
/*0200*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*0210*/ IMAD.WIDE R14, R3, 0x4, R12 ; /* 0x00000004030e7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0240*/ LDG.E R28, [R14.64+0x4] ; /* 0x000004040e1c7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0022e2000c1e1900 */
/*0260*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0270*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000b28000c1e1900 */
/*0290*/ LDG.E R21, [R14.64+0xc] ; /* 0x00000c040e157981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R9, [R14.64+0x10] ; /* 0x000010040e097981 */
/* 0x000ee2000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x020fc600078e020c */
/*02c0*/ LDG.E R18, [R14.64+0x14] ; /* 0x000014040e127981 */
/* 0x002f68000c1e1900 */
/*02d0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x0002e2000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x001fc600078e020c */
/*02f0*/ LDG.E R26, [R14.64+0x18] ; /* 0x000018040e1a7981 */
/* 0x000ee8000c1e1900 */
/*0300*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000124000c1e1900 */
/*0310*/ IMAD.WIDE R16, R0, 0x4, R16 ; /* 0x0000000400107825 */
/* 0x001fca00078e0210 */
/*0320*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000162000c1e1900 */
/*0330*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x002fc800078e0210 */
/*0340*/ FFMA R29, R25, R11, R10 ; /* 0x0000000b191d7223 */
/* 0x004fe4000000000a */
/*0350*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x0002a8000c1e1900 */
/*0360*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f100 */
/*0370*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fce00078e020c */
/*0380*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x001ee40000201400 */
/*0390*/ FFMA R29, R27, R28, R29 ; /* 0x0000001c1b1d7223 */
/* 0x008fe4000000001d */
/*03a0*/ LDG.E R28, [R14.64+0x1c] ; /* 0x00001c040e1c7981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x0000e2000c1e1900 */
/*03c0*/ F2I.TRUNC.NTZ R16, R29 ; /* 0x0000001d00107305 */
/* 0x000e70000020f100 */
/*03d0*/ I2F R12, R16 ; /* 0x00000010000c7306 */
/* 0x0023240000201400 */
/*03e0*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x002fc800078e020a */
/*03f0*/ FFMA R12, R23, R24, R12 ; /* 0x00000018170c7223 */
/* 0x010fe4000000000c */
/*0400*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000322000c1e1900 */
/*0420*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0430*/ I2F R10, R12 ; /* 0x0000000c000a7306 */
/* 0x0010640000201400 */
/*0440*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x001fca00078e0210 */
/*0450*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000122000c1e1900 */
/*0460*/ FFMA R20, R20, R21, R10 ; /* 0x0000001514147223 */
/* 0x002fc6000000000a */
/*0470*/ LDG.E R10, [R14.64+0x24] ; /* 0x000024040e0a7981 */
/* 0x000f22000c1e1900 */
/*0480*/ F2I.TRUNC.NTZ R29, R20 ; /* 0x00000014001d7305 */
/* 0x000e70000020f100 */
/*0490*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x002e620000201400 */
/*04a0*/ IMAD.WIDE R20, R0, 0x4, R12 ; /* 0x0000000400147825 */
/* 0x000fc400078e020c */
/*04b0*/ LDG.E R13, [R14.64+0x2c] ; /* 0x00002c040e0d7981 */
/* 0x001f24000c1e1900 */
/*04c0*/ FFMA R29, R22, R9, R29 ; /* 0x00000009161d7223 */
/* 0x002fe4000000001d */
/*04d0*/ LDG.E R9, [R14.64+0x28] ; /* 0x000028040e097981 */
/* 0x000f28000c1e1900 */
/*04e0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000122000c1e1900 */
/*04f0*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e62000020f100 */
/*0500*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fce00078e0214 */
/*0510*/ I2F R12, R29 ; /* 0x0000001d000c7306 */
/* 0x002f640000201400 */
/*0520*/ FFMA R18, R19, R18, R12 ; /* 0x0000001213127223 */
/* 0x020fe4000000000c */
/*0530*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000368000c1e1900 */
/*0540*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*0550*/ I2F R20, R18 ; /* 0x0000001200147306 */
/* 0x0010a40000201400 */
/*0560*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0570*/ FFMA R20, R25, R26, R20 ; /* 0x0000001a19147223 */
/* 0x004fe40000000014 */
/*0580*/ LDG.E R25, [R14.64+0x30] ; /* 0x000030040e197981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x0000a2000c1e1900 */
/*05a0*/ F2I.TRUNC.NTZ R29, R20 ; /* 0x00000014001d7305 */
/* 0x000e30000020f100 */
/*05b0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x001ee20000201400 */
/*05c0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc800078e0212 */
/*05d0*/ FFMA R29, R27, R28, R29 ; /* 0x0000001c1b1d7223 */
/* 0x008fe4000000001d */
/*05e0*/ LDG.E R28, [R14.64+0x34] ; /* 0x000034040e1c7981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x0008e2000c1e1900 */
/*0600*/ F2I.TRUNC.NTZ R17, R29 ; /* 0x0000001d00117305 */
/* 0x002e30000020f100 */
/*0610*/ I2F R18, R17 ; /* 0x0000001100127306 */
/* 0x0011240000201400 */
/*0620*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x001fc800078e0214 */
/*0630*/ FFMA R21, R24, R23, R18 ; /* 0x0000001718157223 */
/* 0x010fe40000000012 */
/*0640*/ LDG.E R24, [R14.64+0x38] ; /* 0x000038040e187981 */
/* 0x000f28000c1e1900 */
/*0650*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000122000c1e1900 */
/*0660*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fca00078e0210 */
/*0670*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x000f28000c1e1900 */
/*0680*/ LDG.E R16, [R14.64+0x3c] ; /* 0x00003c040e107981 */
/* 0x001f22000c1e1900 */
/*0690*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e30000020f100 */
/*06a0*/ I2F R20, R21 ; /* 0x0000001500147306 */
/* 0x001e240000201400 */
/*06b0*/ FFMA R10, R11, R10, R20 ; /* 0x0000000a0b0a7223 */
/* 0x001fcc0000000014 */
/*06c0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*06d0*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e240000201400 */
/*06e0*/ FFMA R9, R22, R9, R11 ; /* 0x0000000916097223 */
/* 0x001fcc000000000b */
/*06f0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0700*/ I2F R11, R9 ; /* 0x00000009000b7306 */
/* 0x001f640000201400 */
/*0710*/ FFMA R11, R12, R13, R11 ; /* 0x0000000d0c0b7223 */
/* 0x020fcc000000000b */
/*0720*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0730*/ I2F R12, R11 ; /* 0x0000000b000c7306 */
/* 0x001ea40000201400 */
/*0740*/ FFMA R12, R26, R25, R12 ; /* 0x000000191a0c7223 */
/* 0x004fcc000000000c */
/*0750*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0760*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001ee40000201400 */
/*0770*/ FFMA R13, R27, R28, R13 ; /* 0x0000001c1b0d7223 */
/* 0x008fcc000000000d */
/*0780*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0790*/ I2F R10, R13 ; /* 0x0000000d000a7306 */
/* 0x001f240000201400 */
/*07a0*/ FFMA R23, R23, R24, R10 ; /* 0x0000001817177223 */
/* 0x010fcc000000000a */
/*07b0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e30000020f100 */
/*07c0*/ I2F R9, R23 ; /* 0x0000001700097306 */
/* 0x001e220000201400 */
/*07d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ FFMA R9, R29, R16, R9 ; /* 0x000000101d097223 */
/* 0x001fcc0000000009 */
/*07f0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e22000020f100 */
/*0800*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0810*/ IADD3 R4, P2, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fe20007f5e0ff */
/*0820*/ IMAD.WIDE R16, R0, 0x4, R18 ; /* 0x0000000400107825 */
/* 0x000fc800078e0212 */
/*0830*/ I2F R10, R9 ; /* 0x00000009000a7306 */
/* 0x0010620000201400 */
/*0840*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fc600017fe4ff */
/*0860*/ @P1 BRA 0x1e0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0870*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0880*/ @!P1 BRA 0xc10 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0890*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*08a0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0004e2000c1e1900 */
/*08b0*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*08c0*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*08d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ee2000c1e1900 */
/*08e0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*08f0*/ LDG.E R9, [R12.64+0x4] ; /* 0x000004040c097981 */
/* 0x001f28000c1e1900 */
/*0900*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000122000c1e1900 */
/*0910*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0920*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f68000c1e1900 */
/*0930*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*0940*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*0950*/ LDG.E R27, [R12.64+0xc] ; /* 0x00000c040c1b7981 */
/* 0x000f28000c1e1900 */
/*0960*/ LDG.E R26, [R20.64] ; /* 0x00000004141a7981 */
/* 0x000322000c1e1900 */
/*0970*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x004fc600078e0214 */
/*0980*/ LDG.E R29, [R12.64+0x10] ; /* 0x000010040c1d7981 */
/* 0x0004a8000c1e1900 */
/*0990*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*09a0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0210 */
/*09b0*/ LDG.E R17, [R12.64+0x14] ; /* 0x000014040c117981 */
/* 0x0024a8000c1e1900 */
/*09c0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x0000a2000c1e1900 */
/*09d0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fcc00078e020e */
/*09e0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fe200078e0212 */
/*09f0*/ LDG.E R14, [R12.64+0x1c] ; /* 0x00001c040c0e7981 */
/* 0x0014a6000c1e1900 */
/*0a00*/ FFMA R15, R11, R23, R10 ; /* 0x000000170b0f7223 */
/* 0x008fe4000000000a */
/*0a10*/ LDG.E R11, [R12.64+0x18] ; /* 0x000018040c0b7981 */
/* 0x0004e8000c1e1900 */
/*0a20*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000e8000c1e1900 */
/*0a30*/ LDG.E R23, [R20.64] ; /* 0x0000000414177981 */
/* 0x000ee2000c1e1900 */
/*0a40*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*0a50*/ I2F R18, R15 ; /* 0x0000000f00127306 */
/* 0x001f240000201400 */
/*0a60*/ FFMA R9, R22, R9, R18 ; /* 0x0000000916097223 */
/* 0x010fcc0000000012 */
/*0a70*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0a80*/ I2F R22, R9 ; /* 0x0000000900167306 */
/* 0x001f640000201400 */
/*0a90*/ FFMA R22, R25, R24, R22 ; /* 0x0000001819167223 */
/* 0x020fcc0000000016 */
/*0aa0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e30000020f100 */
/*0ab0*/ I2F R18, R22 ; /* 0x0000001600127306 */
/* 0x001e240000201400 */
/*0ac0*/ FFMA R18, R26, R27, R18 ; /* 0x0000001b1a127223 */
/* 0x001fcc0000000012 */
/*0ad0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000eb0000020f100 */
/*0ae0*/ I2F R12, R18 ; /* 0x00000012000c7306 */
/* 0x004e240000201400 */
/*0af0*/ FFMA R12, R28, R29, R12 ; /* 0x0000001d1c0c7223 */
/* 0x001fcc000000000c */
/*0b00*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0b10*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001e240000201400 */
/*0b20*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x001fcc000000000d */
/*0b30*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0b40*/ I2F R9, R13 ; /* 0x0000000d00097306 */
/* 0x001ee20000201400 */
/*0b50*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fe20007f3e0ff */
/*0b60*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fe200078e0214 */
/*0b70*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0b80*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R9, R10, R11, R9 ; /* 0x0000000b0a097223 */
/* 0x008fcc0000000009 */
/*0bc0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0bd0*/ I2F R10, R9 ; /* 0x00000009000a7306 */
/* 0x001e240000201400 */
/*0be0*/ FFMA R14, R23, R14, R10 ; /* 0x0000000e170e7223 */
/* 0x001fcc000000000a */
/*0bf0*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e30000020f100 */
/*0c00*/ I2F R10, R14 ; /* 0x0000000e000a7306 */
/* 0x0010640000201400 */
/*0c10*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0c20*/ @!P0 BRA 0xe40 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c30*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe20000000f00 */
/*0c40*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0010a2000c1e1900 */
/*0c50*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0c70*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0c80*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c90*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ee8000c1e1900 */
/*0ca0*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ee2000c1e1900 */
/*0cb0*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc600078e0212 */
/*0cc0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*0cd0*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x000f22000c1e1900 */
/*0ce0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0214 */
/*0cf0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000f68000c1e1900 */
/*0d00*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x000f62000c1e1900 */
/*0d10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0d20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0d30*/ IADD3 R4, P1, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007f3e0ff */
/*0d40*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x001fe200078e020e */
/*0d50*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007ffe0ff */
/*0d60*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d70*/ FFMA R9, R9, R11, R10 ; /* 0x0000000b09097223 */
/* 0x006fcc000000000a */
/*0d80*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0d90*/ I2F R10, R9 ; /* 0x00000009000a7306 */
/* 0x001ee40000201400 */
/*0da0*/ FFMA R22, R23, R22, R10 ; /* 0x0000001617167223 */
/* 0x008fcc000000000a */
/*0db0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e30000020f100 */
/*0dc0*/ I2F R10, R22 ; /* 0x00000016000a7306 */
/* 0x001f240000201400 */
/*0dd0*/ FFMA R24, R25, R24, R10 ; /* 0x0000001819187223 */
/* 0x010fcc000000000a */
/*0de0*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e30000020f100 */
/*0df0*/ I2F R10, R24 ; /* 0x00000018000a7306 */
/* 0x001f640000201400 */
/*0e00*/ FFMA R26, R27, R26, R10 ; /* 0x0000001a1b1a7223 */
/* 0x020fcc000000000a */
/*0e10*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e30000020f100 */
/*0e20*/ I2F R10, R26 ; /* 0x0000001a000a7306 */
/* 0x0010640000201400 */
/*0e30*/ @P0 BRA 0xc30 ; /* 0xfffffdf000000947 */
/* 0x003fea000383ffff */
/*0e40*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e50*/ @!P0 BRA 0xf60 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0e60*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fe200000001ff */
/*0e70*/ IADD3 R6, R3, R8, RZ ; /* 0x0000000803067210 */
/* 0x000fe20007ffe0ff */
/*0e80*/ IMAD R8, R8, c[0x0][0x178], R2 ; /* 0x00005e0008087a24 */
/* 0x000fd000078e0202 */
/*0e90*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0ea0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fca00078e0209 */
/*0eb0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0ec0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0006a2000c1e1900 */
/*0ed0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ee0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ef0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0f00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x008fc80007f3e0ff */
/*0f10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0f20*/ FFMA R4, R11, R4, R10 ; /* 0x000000040b047223 */
/* 0x006fcc000000000a */
/*0f30*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0f40*/ I2F R10, R4 ; /* 0x00000004000a7306 */
/* 0x0010620000201400 */
/*0f50*/ @P0 BRA 0xeb0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0f60*/ IADD3 R2, R2, R3, RZ ; /* 0x0000000302027210 */
/* 0x000fe40007ffe0ff */
/*0f70*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0f80*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0f90*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe2000c101904 */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPfS_S_i
.globl _Z9matrixMulPfS_S_i
.p2align 8
.type _Z9matrixMulPfS_S_i,@function
_Z9matrixMulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s8, 1
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
s_mul_i32 s2, s15, s8
v_mov_b32_e32 v0, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v2, v1
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_mov_b32 s4, s8
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
s_load_b32 s5, s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_i32_e32 v0, v0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 4
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s8, v2
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPfS_S_i, .Lfunc_end0-_Z9matrixMulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00080773_00000000-6_mul_mat_v1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
.globl _Z9matrixMulPfS_S_i
.type _Z9matrixMulPfS_S_i, @function
_Z9matrixMulPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9matrixMulPfS_S_i, .-_Z9matrixMulPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "taille grille : %d - %d \n"
.LC1:
.string "taille bloc : %d \n"
.LC4:
.string " retour %d \n"
.LC6:
.string "Temps calcul : %f seconde\n"
.LC7:
.string "Erreur i: %d j: %d %f\n"
.LC8:
.string "Erreur i: %d j: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %r12d
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $2048, %ebp
cmpl $1, %r12d
jg .L37
.L12:
leal 1023(%rbp), %edx
testl %ebp, %ebp
cmovns %ebp, %edx
sarl $10, %edx
movl %ebp, %r12d
movl %edx, 48(%rsp)
movl %ebp, 52(%rsp)
movl $1, 56(%rsp)
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %eax
imull %ebp, %eax
leal 0(,%rax,4), %r15d
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
testl %ebp, %ebp
jle .L13
movslq %ebp, %r8
leaq 0(,%r8,4), %r9
movq %r14, %rsi
movq %r13, %rcx
movq %rax, %rdi
movl $0, %edx
movss .LC2(%rip), %xmm0
jmp .L14
.L37:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L12
.L15:
addq $1, %rax
cmpq %r8, %rax
je .L38
.L16:
movss %xmm0, (%rsi,%rax,4)
movss %xmm0, (%rcx,%rax,4)
movl $0x00000000, (%rdi,%rax,4)
cmpl %eax, %edx
jne .L15
pxor %xmm1, %xmm1
cvtsi2ssl %r10d, %xmm1
movss %xmm1, (%rsi,%rax,4)
movss %xmm1, (%rcx,%rax,4)
jmp .L15
.L38:
addl $1, %edx
addq %r9, %rsi
addq %r9, %rcx
addq %r9, %rdi
cmpl %edx, %ebp
je .L13
.L14:
movl $0, %eax
leal 1(%rdx), %r10d
jmp .L16
.L13:
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L17:
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %r12d, %edi
movl $0, %esi
movl $0, %edx
leal -1(%r12), %r10d
movl $0, %r9d
testl %ebp, %ebp
jg .L18
.L19:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %ebp, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPfS_S_iPfS_S_i
jmp .L17
.L42:
leal (%rcx,%rsi), %eax
cltq
movss (%rbx,%rax,4), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r8d, %xmm1
ucomiss %xmm1, %xmm0
jp .L29
jne .L29
.L21:
leal 1(%rcx), %eax
cmpl %eax, %ebp
je .L41
movl %eax, %ecx
.L24:
cmpl %ecx, %edx
je .L42
leal (%rcx,%rsi), %eax
cltq
leal (%rcx,%rdi), %r11d
pxor %xmm0, %xmm0
cvtsi2ssl %r11d, %xmm0
ucomiss (%rbx,%rax,4), %xmm0
jp .L30
je .L21
.L30:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
leal 1(%rdx), %eax
addl %r12d, %esi
addl $1, %edi
cmpl %ecx, %edx
je .L19
movl %eax, %edx
.L18:
leal 1(%rdx), %r8d
imull %r8d, %r8d
addl %r10d, %r8d
movl %r9d, %ecx
jmp .L24
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9matrixMulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mul_mat_v1.hip"
.globl _Z24__device_stub__matrixMulPfS_S_i # -- Begin function _Z24__device_stub__matrixMulPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPfS_S_i,@function
_Z24__device_stub__matrixMulPfS_S_i: # @_Z24__device_stub__matrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPfS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $2048, %edx # imm = 0x800
cmpl $2, %ebp
jl .LBB1_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rdx
.LBB1_2:
movq %rdx, 8(%rsp) # 8-byte Spill
leal 1023(%rdx), %esi
testl %edx, %edx
cmovnsl %edx, %esi
sarl $10, %esi
movq %rdx, %rax
shlq $32, %rax
orq %rsi, %rax
movq %rax, 88(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %ebx
imull %ebx, %ebx
shll $2, %ebx
movq %rbx, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %rbx, 96(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq 8(%rsp), %rcx # 8-byte Reload
movq %rax, 80(%rsp) # 8-byte Spill
movl %ecx, %r13d
testl %ecx, %ecx
jle .LBB1_9
# %bb.3: # %.preheader110.lr.ph
leaq (,%r13,4), %rbp
xorl %r15d, %r15d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_4 Depth=1
incq %r15
movq 8(%rsp), %rcx # 8-byte Reload
addl %ecx, %r14d
cmpq %r13, %r15
je .LBB1_9
.LBB1_4: # %.preheader110
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movl %r14d, %eax
movq 32(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq 40(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %rbx
movl %ecx, %eax
imull %r15d, %eax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdi
leal 1(%r15), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 72(%rsp) # 4-byte Spill
xorl %esi, %esi
movq %rbp, %rdx
callq memset@PLT
xorl %eax, %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=2
incq %rax
cmpq %rax, %r13
je .LBB1_8
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1065353216, (%r12,%rax,4) # imm = 0x3F800000
cmpq %rax, %r15
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=2
movss 72(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx,%rax,4)
movss %xmm0, (%r12,%rax,4)
jmp .LBB1_7
.LBB1_9: # %._crit_edge117
leaq 56(%rsp), %rdi
movq 96(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 80(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
movq 88(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 16(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z9matrixMulPfS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
callq hipGetLastError
xorl %ebp, %ebp
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 8(%rsp), %r10 # 8-byte Reload
testl %r10d, %r10d
jle .LBB1_20
# %bb.12: # %.preheader.lr.ph
leal -1(%r10), %eax
movq %r13, %rcx
xorl %edi, %edi
xorl %esi, %esi
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_19: # %._crit_edge120
# in Loop: Header=BB1_13 Depth=1
incq %rsi
addl %r10d, %ebp
decq %rdi
incq %rcx
cmpq %r13, %rsi
je .LBB1_20
.LBB1_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
movl %ebp, %edx
leaq (%rbx,%rdx,4), %r8
leal 1(%rsi), %edx
imull %edx, %edx
addl %eax, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
xorl %edx, %edx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_17: # %.critedge
# in Loop: Header=BB1_14 Depth=2
leal (%rcx,%rdx), %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9d, %xmm1
movss (%r8,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm2
jne .LBB1_22
jp .LBB1_22
.LBB1_18: # in Loop: Header=BB1_14 Depth=2
incq %rdx
cmpq %rdx, %r13
je .LBB1_19
.LBB1_14: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
movq %rdi, %r9
addq %rdx, %r9
jne .LBB1_17
# %bb.15: # in Loop: Header=BB1_14 Depth=2
movss (%r8,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_21
jp .LBB1_21
# %bb.16: # in Loop: Header=BB1_14 Depth=2
testq %r9, %r9
jne .LBB1_17
jmp .LBB1_18
.LBB1_20: # %._crit_edge122
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 272
movl $.L.str.5, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_21:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
movb $1, %al
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPfS_S_i,@object # @_Z9matrixMulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixMulPfS_S_i
.p2align 3, 0x0
_Z9matrixMulPfS_S_i:
.quad _Z24__device_stub__matrixMulPfS_S_i
.size _Z9matrixMulPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "taille grille : %d - %d \n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "taille bloc : %d \n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " retour %d \n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Temps calcul : %f seconde\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Erreur i: %d j: %d %f\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Erreur i: %d j: %d\n"
.size .L.str.5, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
*this file exercise matrix multiplication with shared memory and use
*the thought of dividing matrix to sub_matrix
*/
#include<time.h>
#include<stdlib.h>
#include<stdio.h>
#include<assert.h>
#include<cuda_profiler_api.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 64
typedef struct {
int width;
int height;
float *vals;
} Matrix;
float& GetElement(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__device__ float& GetElementKernel(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
//__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
//__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
int range = A.width / BLOCK_SIZE;
float c_value = 0.0f;
for (int k = 0; k < range; ++k) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[threadIdx.x][threadIdx.y] = GetElementKernel(A, blockIdx.x * BLOCK_SIZE + threadIdx.x, k * BLOCK_SIZE + threadIdx.y);
Bs[threadIdx.x][threadIdx.y] = GetElementKernel(B, k * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y);
__syncthreads();
float tmp = 0.0f;
for (int block_k = 0; block_k < BLOCK_SIZE; ++block_k) {
tmp += As[threadIdx.x][block_k] * Bs[block_k][threadIdx.y];
}
c_value += tmp;
__syncthreads();
}
GetElementKernel(C, blockIdx.x * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y) = c_value;
}
void MatMulUsual(const Matrix A, const Matrix B, Matrix C) {
for (int i = 0; i < C.height; ++i) {
for (int j = 0; j < C.width; ++j) {
float res = 0.0f;
for (int k = 0; k < A.width; ++k) {
res += GetElement(A, i, k) * GetElement(B, k, j);
}
GetElement(C, i, j) = res;
}
}
}
void checkCUDAError(const char *msg);
int main() {
size_t memSize = MATRIX_SIZE * MATRIX_SIZE * sizeof(float);
//initialize two matrix
srand(time(NULL));
float *valsA = (float*)malloc(memSize);
float *valsB = (float*)malloc(memSize);
for (int i = 1; i <= MATRIX_SIZE; ++i) {
for (int j = 1; j <= MATRIX_SIZE; ++j) {
valsA[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
valsB[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
}
}
Matrix matrixA = {MATRIX_SIZE, MATRIX_SIZE, valsA};
Matrix matrixB = {MATRIX_SIZE, MATRIX_SIZE, valsB};
//multiplicate with CPU
float *valsC_CPU = (float*)malloc(memSize);
Matrix matrixC_CPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_CPU};
MatMulUsual(matrixA, matrixB, matrixC_CPU);
//multiplicate withGPU
float *valsC_GPU = (float*)malloc(memSize);
Matrix matrixC_GPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_GPU};
//no use
// int numBlocks = 8 * 8;
//int numThreadsPerBlock = MATRIX_SIZE * MATRIX_SIZE / numBlocks;
float *valsA_d, *valsB_d, *valsC_d;
cudaMalloc(&valsA_d, memSize);
cudaMemcpy(valsA_d, valsA, memSize, cudaMemcpyHostToDevice);
cudaMalloc(&valsB_d, memSize);
cudaMemcpy(valsB_d, valsB, memSize, cudaMemcpyHostToDevice);
cudaMalloc(&valsC_d, memSize);
Matrix A_d = {MATRIX_SIZE, MATRIX_SIZE, valsA_d};
Matrix B_d = {MATRIX_SIZE, MATRIX_SIZE, valsB_d};
Matrix C_d = {MATRIX_SIZE, MATRIX_SIZE, valsC_d};
//launch kernel
dim3 dimGrid(MATRIX_SIZE / BLOCK_SIZE, MATRIX_SIZE / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
MatMulKernel<<<dimGrid, dimBlock>>>(A_d, B_d, C_d);
//block until the device has completed
cudaThreadSynchronize();
//check errors
checkCUDAError("kernel invocation");
//data fetch
cudaMemcpy(valsC_GPU, valsC_d, memSize, cudaMemcpyDeviceToHost);
checkCUDAError("memcpy");
//verify the data
for (int i = 0; i < MATRIX_SIZE; ++i) {
for (int j = 0; j < MATRIX_SIZE; ++j) {
assert(GetElement(matrixC_CPU, i, j) == GetElement(matrixC_GPU, i, j));
}
}
cudaFree(valsA_d);
cudaFree(valsB_d);
cudaFree(valsC_d);
free(valsA);
free(valsB);
free(valsC_CPU);
free(valsC_GPU);
printf("Correct!\n");
cudaProfilerStop();
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ ISETP.GT.AND P0, PT, R2, 0x7, PT ; /* 0x000000070200780c */
/* 0x000fe40003f04270 */
/*0040*/ SHF.R.S32.HI R0, RZ, 0x1f, R2 ; /* 0x0000001fff007819 */
/* 0x000fc80000011402 */
/*0050*/ LEA.HI R0, R0, c[0x0][0x160], RZ, 0x3 ; /* 0x0000580000007a11 */
/* 0x000fce00078f18ff */
/*0060*/ @!P0 MOV R24, RZ ; /* 0x000000ff00188202 */
/* 0x000fe20000000f00 */
/*0070*/ @!P0 BRA 0x7c0 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*0080*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0090*/ LOP3.LUT R2, R2, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff802027812 */
/* 0x000fe200078ec0ff */
/*00a0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.R.S32.HI R0, RZ, 0x3, R0 ; /* 0x00000003ff007819 */
/* 0x000fe20000011400 */
/*00c0*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e220000002100 */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x8, PT ; /* 0x000000080200780c */
/* 0x000fe40003f05270 */
/*00e0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe20000000f00 */
/*00f0*/ S2R R18, SR_TID.Y ; /* 0x0000000000127919 */
/* 0x000e620000002200 */
/*0100*/ LOP3.LUT R21, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100157812 */
/* 0x000fc600078ec0ff */
/*0110*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ea20000002600 */
/*0120*/ LEA R23, R4, R17, 0x3 ; /* 0x0000001104177211 */
/* 0x001fe400078e18ff */
/*0130*/ SHF.L.U32 R19, R17, 0x5, RZ ; /* 0x0000000511137819 */
/* 0x000fc600000006ff */
/*0140*/ IMAD R23, R23, c[0x0][0x160], R18 ; /* 0x0000580017177a24 */
/* 0x002fe200078e0212 */
/*0150*/ LEA R22, R18, R19, 0x2 ; /* 0x0000001312167211 */
/* 0x000fe400078e10ff */
/*0160*/ LEA R20, R3, R18, 0x3 ; /* 0x0000001203147211 */
/* 0x004fe200078e18ff */
/*0170*/ @!P0 BRA 0x5b0 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R25, R0, -R21, RZ ; /* 0x8000001500197210 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fc60000000f00 */
/*01b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*01c0*/ LEA R13, R16.reuse, R17, 0x3 ; /* 0x00000011100d7211 */
/* 0x040fe400078e18ff */
/*01d0*/ LEA R3, R16, R23, 0x3 ; /* 0x0000001710037211 */
/* 0x000fc600078e18ff */
/*01e0*/ IMAD R5, R13, c[0x0][0x170], R20 ; /* 0x00005c000d057a24 */
/* 0x000fc800078e0214 */
/*01f0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fc800078e0200 */
/*0200*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe400078e0200 */
/*0210*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0230*/ IADD3 R13, R13, 0x8, RZ ; /* 0x000000080d0d7810 */
/* 0x000fc60007ffe0ff */
/*0240*/ STS [R22+0x100], R5 ; /* 0x0001000516007388 */
/* 0x004fe80000000800 */
/*0250*/ STS [R22], R7 ; /* 0x0000000716007388 */
/* 0x008fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R15, [R18.X4+0x100] ; /* 0x00010000120f7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R8, [R19] ; /* 0x0000000013087984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R6, [R18.X4+0x120] ; /* 0x0001200012067984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R12, [R18.X4+0x140] ; /* 0x00014000120c7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R28, [R18.X4+0x160] ; /* 0x00016000121c7984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R29, [R18.X4+0x180] ; /* 0x00018000121d7984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS R27, [R18.X4+0x1c0] ; /* 0x0001c000121b7984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS R26, [R18.X4+0x1e0] ; /* 0x0001e000121a7984 */
/* 0x000fe20000004800 */
/*02f0*/ FFMA R8, R15, R8, RZ ; /* 0x000000080f087223 */
/* 0x001fc400000000ff */
/*0300*/ IMAD R15, R13, c[0x0][0x170], R20 ; /* 0x00005c000d0f7a24 */
/* 0x000fe400078e0214 */
/*0310*/ FFMA R13, R6, R9, R8 ; /* 0x00000009060d7223 */
/* 0x002fe40000000008 */
/*0320*/ IMAD.WIDE R8, R15, R0, c[0x0][0x178] ; /* 0x00005e000f087625 */
/* 0x000fe200078e0200 */
/*0330*/ LDS.128 R4, [R19+0x10] ; /* 0x0000100013047984 */
/* 0x000e280000000c00 */
/*0340*/ LDS R0, [R18.X4+0x1a0] ; /* 0x0001a00012007984 */
/* 0x000e680000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ LDG.E R3, [R2.64+0x20] ; /* 0x0000200402037981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f62000c1e1900 */
/*0380*/ FFMA R10, R12, R10, R13 ; /* 0x0000000a0c0a7223 */
/* 0x004fc8000000000d */
/*0390*/ FFMA R10, R28, R11, R10 ; /* 0x0000000b1c0a7223 */
/* 0x008fc8000000000a */
/*03a0*/ FFMA R4, R29, R4, R10 ; /* 0x000000041d047223 */
/* 0x001fe2000000000a */
/*03b0*/ IADD3 R25, R25, -0x2, RZ ; /* 0xfffffffe19197810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ FFMA R0, R0, R5, R4 ; /* 0x0000000500007223 */
/* 0x002fe20000000004 */
/*03d0*/ ISETP.NE.AND P0, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fc60003f05270 */
/*03e0*/ FFMA R0, R27, R6, R0 ; /* 0x000000061b007223 */
/* 0x000fc80000000000 */
/*03f0*/ FFMA R7, R26, R7, R0 ; /* 0x000000071a077223 */
/* 0x000fc80000000000 */
/*0400*/ FADD R7, R7, R24 ; /* 0x0000001807077221 */
/* 0x000fe20000000000 */
/*0410*/ IADD3 R16, R16, 0x2, RZ ; /* 0x0000000210107810 */
/* 0x000fe20007ffe0ff */
/*0420*/ STS [R22], R3 ; /* 0x0000000316007388 */
/* 0x010fe80000000800 */
/*0430*/ STS [R22+0x100], R9 ; /* 0x0001000916007388 */
/* 0x020fe80000000800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0450*/ LDS R2, [R18.X4+0x100] ; /* 0x0001000012027984 */
/* 0x000fe80000004800 */
/*0460*/ LDS.128 R12, [R19] ; /* 0x00000000130c7984 */
/* 0x000e280000000c00 */
/*0470*/ LDS R28, [R18.X4+0x120] ; /* 0x00012000121c7984 */
/* 0x000e680000004800 */
/*0480*/ LDS R11, [R18.X4+0x140] ; /* 0x00014000120b7984 */
/* 0x000ea80000004800 */
/*0490*/ LDS R3, [R18.X4+0x180] ; /* 0x0001800012037984 */
/* 0x000fe20000004800 */
/*04a0*/ FFMA R12, R2, R12, RZ ; /* 0x0000000c020c7223 */
/* 0x001fc600000000ff */
/*04b0*/ LDS R2, [R18.X4+0x160] ; /* 0x0001600012027984 */
/* 0x000e220000004800 */
/*04c0*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x002fc6000000000c */
/*04d0*/ LDS R13, [R18.X4+0x1c0] ; /* 0x0001c000120d7984 */
/* 0x000fe20000004800 */
/*04e0*/ FFMA R12, R11, R14, R12 ; /* 0x0000000e0b0c7223 */
/* 0x004fc6000000000c */
/*04f0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000e680000000c00 */
/*0500*/ LDS R14, [R18.X4+0x1a0] ; /* 0x0001a000120e7984 */
/* 0x000ea20000004800 */
/*0510*/ FFMA R12, R2, R15, R12 ; /* 0x0000000f020c7223 */
/* 0x001fc6000000000c */
/*0520*/ LDS R2, [R18.X4+0x1e0] ; /* 0x0001e00012027984 */
/* 0x000e220000004800 */
/*0530*/ FFMA R8, R3, R8, R12 ; /* 0x0000000803087223 */
/* 0x002fc8000000000c */
/*0540*/ FFMA R8, R14, R9, R8 ; /* 0x000000090e087223 */
/* 0x004fc80000000008 */
/*0550*/ FFMA R8, R13, R10, R8 ; /* 0x0000000a0d087223 */
/* 0x000fc80000000008 */
/*0560*/ FFMA R2, R2, R11, R8 ; /* 0x0000000b02027223 */
/* 0x001fc80000000008 */
/*0570*/ FADD R24, R7, R2 ; /* 0x0000000207187221 */
/* 0x000fe20000000000 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0590*/ @P0 BRA 0x1b0 ; /* 0xfffffc1000000947 */
/* 0x000fea000383ffff */
/*05a0*/ SHF.L.U32 R16, R16, 0x3, RZ ; /* 0x0000000310107819 */
/* 0x000fe400000006ff */
/*05b0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 BRA 0x7c0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R17, R17, R16.reuse, RZ ; /* 0x0000001011117210 */
/* 0x080fe40007ffe0ff */
/*05e0*/ IADD3 R2, R23, R16, RZ ; /* 0x0000001017027210 */
/* 0x000fe40007ffe0ff */
/*05f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD R12, R17, c[0x0][0x170], R20 ; /* 0x00005c00110c7a24 */
/* 0x000fc800078e0214 */
/*0610*/ IMAD.WIDE R2, R2, R13, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e020d */
/*0620*/ IMAD.WIDE R12, R12, R13, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fe400078e020d */
/*0630*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee8000c1e1900 */
/*0650*/ STS [R22], R3 ; /* 0x0000000316007388 */
/* 0x004fe80000000800 */
/*0660*/ STS [R22+0x100], R13 ; /* 0x0001000d16007388 */
/* 0x008fe80000000800 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ LDS R15, [R18.X4+0x100] ; /* 0x00010000120f7984 */
/* 0x000fe80000004800 */
/*0690*/ LDS.128 R4, [R19] ; /* 0x0000000013047984 */
/* 0x000e280000000c00 */
/*06a0*/ LDS R0, [R18.X4+0x120] ; /* 0x0001200012007984 */
/* 0x000e680000004800 */
/*06b0*/ LDS R14, [R18.X4+0x140] ; /* 0x00014000120e7984 */
/* 0x000ea80000004800 */
/*06c0*/ LDS R16, [R18.X4+0x160] ; /* 0x0001600012107984 */
/* 0x000ee80000004800 */
/*06d0*/ LDS R17, [R18.X4+0x180] ; /* 0x0001800012117984 */
/* 0x000fe80000004800 */
/*06e0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000f280000000c00 */
/*06f0*/ LDS R2, [R18.X4+0x1a0] ; /* 0x0001a00012027984 */
/* 0x000f680000004800 */
/*0700*/ LDS R3, [R18.X4+0x1c0] ; /* 0x0001c00012037984 */
/* 0x000f680000004800 */
/*0710*/ LDS R12, [R18.X4+0x1e0] ; /* 0x0001e000120c7984 */
/* 0x000f620000004800 */
/*0720*/ FFMA R4, R15, R4, RZ ; /* 0x000000040f047223 */
/* 0x001fc800000000ff */
/*0730*/ FFMA R5, R0, R5, R4 ; /* 0x0000000500057223 */
/* 0x002fc80000000004 */
/*0740*/ FFMA R6, R14, R6, R5 ; /* 0x000000060e067223 */
/* 0x004fc80000000005 */
/*0750*/ FFMA R7, R16, R7, R6 ; /* 0x0000000710077223 */
/* 0x008fc80000000006 */
/*0760*/ FFMA R8, R17, R8, R7 ; /* 0x0000000811087223 */
/* 0x010fc80000000007 */
/*0770*/ FFMA R9, R2, R9, R8 ; /* 0x0000000902097223 */
/* 0x020fc80000000008 */
/*0780*/ FFMA R10, R3, R10, R9 ; /* 0x0000000a030a7223 */
/* 0x000fc80000000009 */
/*0790*/ FFMA R11, R12, R11, R10 ; /* 0x0000000b0c0b7223 */
/* 0x000fc8000000000a */
/*07a0*/ FADD R24, R24, R11 ; /* 0x0000000b18187221 */
/* 0x000fe20000000000 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*07d0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*07e0*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*07f0*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0800*/ LEA R0, R0, R3, 0x3 ; /* 0x0000000300007211 */
/* 0x001fe200078e18ff */
/*0810*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0820*/ LEA R5, R2, R5, 0x3 ; /* 0x0000000502057211 */
/* 0x002fca00078e18ff */
/*0830*/ IMAD R2, R0, c[0x0][0x180], R5 ; /* 0x0000600000027a24 */
/* 0x000fc800078e0205 */
/*0840*/ IMAD.WIDE R2, R2, R3, c[0x0][0x188] ; /* 0x0000620002027625 */
/* 0x000fca00078e0203 */
/*0850*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0860*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
*this file exercise matrix multiplication with shared memory and use
*the thought of dividing matrix to sub_matrix
*/
#include<time.h>
#include<stdlib.h>
#include<stdio.h>
#include<assert.h>
#include<cuda_profiler_api.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 64
typedef struct {
int width;
int height;
float *vals;
} Matrix;
float& GetElement(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__device__ float& GetElementKernel(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
//__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
//__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
int range = A.width / BLOCK_SIZE;
float c_value = 0.0f;
for (int k = 0; k < range; ++k) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[threadIdx.x][threadIdx.y] = GetElementKernel(A, blockIdx.x * BLOCK_SIZE + threadIdx.x, k * BLOCK_SIZE + threadIdx.y);
Bs[threadIdx.x][threadIdx.y] = GetElementKernel(B, k * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y);
__syncthreads();
float tmp = 0.0f;
for (int block_k = 0; block_k < BLOCK_SIZE; ++block_k) {
tmp += As[threadIdx.x][block_k] * Bs[block_k][threadIdx.y];
}
c_value += tmp;
__syncthreads();
}
GetElementKernel(C, blockIdx.x * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y) = c_value;
}
void MatMulUsual(const Matrix A, const Matrix B, Matrix C) {
for (int i = 0; i < C.height; ++i) {
for (int j = 0; j < C.width; ++j) {
float res = 0.0f;
for (int k = 0; k < A.width; ++k) {
res += GetElement(A, i, k) * GetElement(B, k, j);
}
GetElement(C, i, j) = res;
}
}
}
void checkCUDAError(const char *msg);
int main() {
size_t memSize = MATRIX_SIZE * MATRIX_SIZE * sizeof(float);
//initialize two matrix
srand(time(NULL));
float *valsA = (float*)malloc(memSize);
float *valsB = (float*)malloc(memSize);
for (int i = 1; i <= MATRIX_SIZE; ++i) {
for (int j = 1; j <= MATRIX_SIZE; ++j) {
valsA[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
valsB[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
}
}
Matrix matrixA = {MATRIX_SIZE, MATRIX_SIZE, valsA};
Matrix matrixB = {MATRIX_SIZE, MATRIX_SIZE, valsB};
//multiplicate with CPU
float *valsC_CPU = (float*)malloc(memSize);
Matrix matrixC_CPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_CPU};
MatMulUsual(matrixA, matrixB, matrixC_CPU);
//multiplicate withGPU
float *valsC_GPU = (float*)malloc(memSize);
Matrix matrixC_GPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_GPU};
//no use
// int numBlocks = 8 * 8;
//int numThreadsPerBlock = MATRIX_SIZE * MATRIX_SIZE / numBlocks;
float *valsA_d, *valsB_d, *valsC_d;
cudaMalloc(&valsA_d, memSize);
cudaMemcpy(valsA_d, valsA, memSize, cudaMemcpyHostToDevice);
cudaMalloc(&valsB_d, memSize);
cudaMemcpy(valsB_d, valsB, memSize, cudaMemcpyHostToDevice);
cudaMalloc(&valsC_d, memSize);
Matrix A_d = {MATRIX_SIZE, MATRIX_SIZE, valsA_d};
Matrix B_d = {MATRIX_SIZE, MATRIX_SIZE, valsB_d};
Matrix C_d = {MATRIX_SIZE, MATRIX_SIZE, valsC_d};
//launch kernel
dim3 dimGrid(MATRIX_SIZE / BLOCK_SIZE, MATRIX_SIZE / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
MatMulKernel<<<dimGrid, dimBlock>>>(A_d, B_d, C_d);
//block until the device has completed
cudaThreadSynchronize();
//check errors
checkCUDAError("kernel invocation");
//data fetch
cudaMemcpy(valsC_GPU, valsC_d, memSize, cudaMemcpyDeviceToHost);
checkCUDAError("memcpy");
//verify the data
for (int i = 0; i < MATRIX_SIZE; ++i) {
for (int j = 0; j < MATRIX_SIZE; ++j) {
assert(GetElement(matrixC_CPU, i, j) == GetElement(matrixC_GPU, i, j));
}
}
cudaFree(valsA_d);
cudaFree(valsB_d);
cudaFree(valsC_d);
free(valsA);
free(valsB);
free(valsC_CPU);
free(valsC_GPU);
printf("Correct!\n");
cudaProfilerStop();
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .file "tmpxft_000012e1_00000000-6_matrixMulti_fast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10GetElement6Matrixii
.type _Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB2057:
.cfi_startproc
endbr64
imull %edi, %edx
addl %ecx, %edx
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %rax
ret
.cfi_endproc
.LFE2057:
.size _Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
.globl _Z16GetElementKernel6Matrixii
.type _Z16GetElementKernel6Matrixii, @function
_Z16GetElementKernel6Matrixii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z16GetElementKernel6Matrixii, .-_Z16GetElementKernel6Matrixii
.globl _Z11MatMulUsual6MatrixS_S_
.type _Z11MatMulUsual6MatrixS_S_, @function
_Z11MatMulUsual6MatrixS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rcx, -24(%rsp)
movq %r9, -16(%rsp)
movq %r8, %rcx
sarq $32, %rcx
movl %ecx, -32(%rsp)
testl %ecx, %ecx
jle .L6
movq %rsi, %rbp
movq %rdx, %rax
movl %edi, %r11d
movl %r8d, %r15d
movl %edi, -28(%rsp)
cltq
leaq 0(,%rax,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %r8d, %rbx
movslq %edi, %rax
movq %rax, -8(%rsp)
movl %r8d, %ecx
jmp .L8
.L9:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L9
.L11:
movss %xmm1, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %rbx, %r8
je .L16
.L12:
movq %r9, %rdx
movq %r14, %rax
pxor %xmm1, %xmm1
testl %r11d, %r11d
jg .L9
jmp .L11
.L16:
movl -36(%rsp), %edx
.L10:
addl $1, %edx
addl %r15d, %r12d
movl -28(%rsp), %eax
addl %eax, %r13d
cmpl %edx, -32(%rsp)
je .L6
.L8:
testl %ecx, %ecx
jle .L10
movq -24(%rsp), %r9
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r14
movq -8(%rsp), %rdi
addq %rdi, %rax
leaq 0(%rbp,%rax,4), %rdi
movslq %r12d, %rax
movq -16(%rsp), %r10
leaq (%r10,%rax,4), %r10
movl $0, %r8d
movl %edx, -36(%rsp)
jmp .L12
.L6:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11MatMulUsual6MatrixS_S_, .-_Z11MatMulUsual6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.section .rodata.str1.1
.LC2:
.string "kernel invocation"
.LC3:
.string "memcpy"
.LC4:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $16384, %edi
call malloc@PLT
movq %rax, %rbx
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
leaq 256(%rbx), %r13
leaq 256(%rax), %r14
leaq 16640(%rbx), %r15
.L32:
movl $0, %r12d
.L33:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -256(%r13,%r12)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -256(%r14,%r12)
addq $4, %r12
cmpq $256, %r12
jne .L33
addq $256, %r13
addq $256, %r14
cmpq %r15, %r13
jne .L32
movabsq $274877906944, %r12
movq %r12, %r13
orq $64, %r13
movl $16384, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r13, %r8
movq %rax, %r9
movq %r13, %rdx
movq %rbp, %rcx
movq %r13, %rdi
movq %rbx, %rsi
call _Z11MatMulUsual6MatrixS_S_
movl $16384, %edi
call malloc@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movq 16(%rsp), %r14
movq 24(%rsp), %r13
movq 32(%rsp), %r12
movl $8, 40(%rsp)
movl $8, 44(%rsp)
movl $8, 52(%rsp)
movl $8, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L35:
call cudaThreadSynchronize@PLT
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $16384, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $64, %edx
.L36:
movl $64, %eax
.L37:
subl $1, %eax
jne .L37
subl $1, %edx
jne .L36
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaProfilerStop@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movl $64, 64(%rsp)
movl $64, 68(%rsp)
movq %r14, 72(%rsp)
movl $64, 80(%rsp)
movl $64, 84(%rsp)
movq %r13, 88(%rsp)
movl $64, 96(%rsp)
movl $64, 100(%rsp)
movq %r12, 104(%rsp)
leaq 96(%rsp), %rdx
leaq 80(%rsp), %rsi
leaq 64(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
jmp .L35
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
*this file exercise matrix multiplication with shared memory and use
*the thought of dividing matrix to sub_matrix
*/
#include<time.h>
#include<stdlib.h>
#include<stdio.h>
#include<assert.h>
#include<cuda_profiler_api.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 64
typedef struct {
int width;
int height;
float *vals;
} Matrix;
float& GetElement(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__device__ float& GetElementKernel(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
//__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
//__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
int range = A.width / BLOCK_SIZE;
float c_value = 0.0f;
for (int k = 0; k < range; ++k) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[threadIdx.x][threadIdx.y] = GetElementKernel(A, blockIdx.x * BLOCK_SIZE + threadIdx.x, k * BLOCK_SIZE + threadIdx.y);
Bs[threadIdx.x][threadIdx.y] = GetElementKernel(B, k * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y);
__syncthreads();
float tmp = 0.0f;
for (int block_k = 0; block_k < BLOCK_SIZE; ++block_k) {
tmp += As[threadIdx.x][block_k] * Bs[block_k][threadIdx.y];
}
c_value += tmp;
__syncthreads();
}
GetElementKernel(C, blockIdx.x * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y) = c_value;
}
void MatMulUsual(const Matrix A, const Matrix B, Matrix C) {
for (int i = 0; i < C.height; ++i) {
for (int j = 0; j < C.width; ++j) {
float res = 0.0f;
for (int k = 0; k < A.width; ++k) {
res += GetElement(A, i, k) * GetElement(B, k, j);
}
GetElement(C, i, j) = res;
}
}
}
void checkCUDAError(const char *msg);
int main() {
size_t memSize = MATRIX_SIZE * MATRIX_SIZE * sizeof(float);
//initialize two matrix
srand(time(NULL));
float *valsA = (float*)malloc(memSize);
float *valsB = (float*)malloc(memSize);
for (int i = 1; i <= MATRIX_SIZE; ++i) {
for (int j = 1; j <= MATRIX_SIZE; ++j) {
valsA[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
valsB[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
}
}
Matrix matrixA = {MATRIX_SIZE, MATRIX_SIZE, valsA};
Matrix matrixB = {MATRIX_SIZE, MATRIX_SIZE, valsB};
//multiplicate with CPU
float *valsC_CPU = (float*)malloc(memSize);
Matrix matrixC_CPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_CPU};
MatMulUsual(matrixA, matrixB, matrixC_CPU);
//multiplicate withGPU
float *valsC_GPU = (float*)malloc(memSize);
Matrix matrixC_GPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_GPU};
//no use
// int numBlocks = 8 * 8;
//int numThreadsPerBlock = MATRIX_SIZE * MATRIX_SIZE / numBlocks;
float *valsA_d, *valsB_d, *valsC_d;
cudaMalloc(&valsA_d, memSize);
cudaMemcpy(valsA_d, valsA, memSize, cudaMemcpyHostToDevice);
cudaMalloc(&valsB_d, memSize);
cudaMemcpy(valsB_d, valsB, memSize, cudaMemcpyHostToDevice);
cudaMalloc(&valsC_d, memSize);
Matrix A_d = {MATRIX_SIZE, MATRIX_SIZE, valsA_d};
Matrix B_d = {MATRIX_SIZE, MATRIX_SIZE, valsB_d};
Matrix C_d = {MATRIX_SIZE, MATRIX_SIZE, valsC_d};
//launch kernel
dim3 dimGrid(MATRIX_SIZE / BLOCK_SIZE, MATRIX_SIZE / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
MatMulKernel<<<dimGrid, dimBlock>>>(A_d, B_d, C_d);
//block until the device has completed
cudaThreadSynchronize();
//check errors
checkCUDAError("kernel invocation");
//data fetch
cudaMemcpy(valsC_GPU, valsC_d, memSize, cudaMemcpyDeviceToHost);
checkCUDAError("memcpy");
//verify the data
for (int i = 0; i < MATRIX_SIZE; ++i) {
for (int j = 0; j < MATRIX_SIZE; ++j) {
assert(GetElement(matrixC_CPU, i, j) == GetElement(matrixC_GPU, i, j));
}
}
cudaFree(valsA_d);
cudaFree(valsB_d);
cudaFree(valsC_d);
free(valsA);
free(valsB);
free(valsC_CPU);
free(valsC_GPU);
printf("Correct!\n");
cudaProfilerStop();
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | /*
*this file exercise matrix multiplication with shared memory and use
*the thought of dividing matrix to sub_matrix
*/
#include <hip/hip_runtime.h>
#include<time.h>
#include<stdlib.h>
#include<stdio.h>
#include<assert.h>
#include<hip/hip_runtime_api.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 64
typedef struct {
int width;
int height;
float *vals;
} Matrix;
float& GetElement(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__device__ float& GetElementKernel(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
//__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
//__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
int range = A.width / BLOCK_SIZE;
float c_value = 0.0f;
for (int k = 0; k < range; ++k) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[threadIdx.x][threadIdx.y] = GetElementKernel(A, blockIdx.x * BLOCK_SIZE + threadIdx.x, k * BLOCK_SIZE + threadIdx.y);
Bs[threadIdx.x][threadIdx.y] = GetElementKernel(B, k * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y);
__syncthreads();
float tmp = 0.0f;
for (int block_k = 0; block_k < BLOCK_SIZE; ++block_k) {
tmp += As[threadIdx.x][block_k] * Bs[block_k][threadIdx.y];
}
c_value += tmp;
__syncthreads();
}
GetElementKernel(C, blockIdx.x * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y) = c_value;
}
void MatMulUsual(const Matrix A, const Matrix B, Matrix C) {
for (int i = 0; i < C.height; ++i) {
for (int j = 0; j < C.width; ++j) {
float res = 0.0f;
for (int k = 0; k < A.width; ++k) {
res += GetElement(A, i, k) * GetElement(B, k, j);
}
GetElement(C, i, j) = res;
}
}
}
void checkCUDAError(const char *msg);
int main() {
size_t memSize = MATRIX_SIZE * MATRIX_SIZE * sizeof(float);
//initialize two matrix
srand(time(NULL));
float *valsA = (float*)malloc(memSize);
float *valsB = (float*)malloc(memSize);
for (int i = 1; i <= MATRIX_SIZE; ++i) {
for (int j = 1; j <= MATRIX_SIZE; ++j) {
valsA[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
valsB[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
}
}
Matrix matrixA = {MATRIX_SIZE, MATRIX_SIZE, valsA};
Matrix matrixB = {MATRIX_SIZE, MATRIX_SIZE, valsB};
//multiplicate with CPU
float *valsC_CPU = (float*)malloc(memSize);
Matrix matrixC_CPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_CPU};
MatMulUsual(matrixA, matrixB, matrixC_CPU);
//multiplicate withGPU
float *valsC_GPU = (float*)malloc(memSize);
Matrix matrixC_GPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_GPU};
//no use
// int numBlocks = 8 * 8;
//int numThreadsPerBlock = MATRIX_SIZE * MATRIX_SIZE / numBlocks;
float *valsA_d, *valsB_d, *valsC_d;
hipMalloc(&valsA_d, memSize);
hipMemcpy(valsA_d, valsA, memSize, hipMemcpyHostToDevice);
hipMalloc(&valsB_d, memSize);
hipMemcpy(valsB_d, valsB, memSize, hipMemcpyHostToDevice);
hipMalloc(&valsC_d, memSize);
Matrix A_d = {MATRIX_SIZE, MATRIX_SIZE, valsA_d};
Matrix B_d = {MATRIX_SIZE, MATRIX_SIZE, valsB_d};
Matrix C_d = {MATRIX_SIZE, MATRIX_SIZE, valsC_d};
//launch kernel
dim3 dimGrid(MATRIX_SIZE / BLOCK_SIZE, MATRIX_SIZE / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
MatMulKernel<<<dimGrid, dimBlock>>>(A_d, B_d, C_d);
//block until the device has completed
hipDeviceSynchronize();
//check errors
checkCUDAError("kernel invocation");
//data fetch
hipMemcpy(valsC_GPU, valsC_d, memSize, hipMemcpyDeviceToHost);
checkCUDAError("memcpy");
//verify the data
for (int i = 0; i < MATRIX_SIZE; ++i) {
for (int j = 0; j < MATRIX_SIZE; ++j) {
assert(GetElement(matrixC_CPU, i, j) == GetElement(matrixC_GPU, i, j));
}
}
hipFree(valsA_d);
hipFree(valsB_d);
hipFree(valsC_d);
free(valsA);
free(valsB);
free(valsC_CPU);
free(valsC_GPU);
printf("Correct!\n");
hipProfilerStop();
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
*this file exercise matrix multiplication with shared memory and use
*the thought of dividing matrix to sub_matrix
*/
#include <hip/hip_runtime.h>
#include<time.h>
#include<stdlib.h>
#include<stdio.h>
#include<assert.h>
#include<hip/hip_runtime_api.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 64
typedef struct {
int width;
int height;
float *vals;
} Matrix;
float& GetElement(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__device__ float& GetElementKernel(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
//__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
//__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
int range = A.width / BLOCK_SIZE;
float c_value = 0.0f;
for (int k = 0; k < range; ++k) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[threadIdx.x][threadIdx.y] = GetElementKernel(A, blockIdx.x * BLOCK_SIZE + threadIdx.x, k * BLOCK_SIZE + threadIdx.y);
Bs[threadIdx.x][threadIdx.y] = GetElementKernel(B, k * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y);
__syncthreads();
float tmp = 0.0f;
for (int block_k = 0; block_k < BLOCK_SIZE; ++block_k) {
tmp += As[threadIdx.x][block_k] * Bs[block_k][threadIdx.y];
}
c_value += tmp;
__syncthreads();
}
GetElementKernel(C, blockIdx.x * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y) = c_value;
}
void MatMulUsual(const Matrix A, const Matrix B, Matrix C) {
for (int i = 0; i < C.height; ++i) {
for (int j = 0; j < C.width; ++j) {
float res = 0.0f;
for (int k = 0; k < A.width; ++k) {
res += GetElement(A, i, k) * GetElement(B, k, j);
}
GetElement(C, i, j) = res;
}
}
}
void checkCUDAError(const char *msg);
int main() {
size_t memSize = MATRIX_SIZE * MATRIX_SIZE * sizeof(float);
//initialize two matrix
srand(time(NULL));
float *valsA = (float*)malloc(memSize);
float *valsB = (float*)malloc(memSize);
for (int i = 1; i <= MATRIX_SIZE; ++i) {
for (int j = 1; j <= MATRIX_SIZE; ++j) {
valsA[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
valsB[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
}
}
Matrix matrixA = {MATRIX_SIZE, MATRIX_SIZE, valsA};
Matrix matrixB = {MATRIX_SIZE, MATRIX_SIZE, valsB};
//multiplicate with CPU
float *valsC_CPU = (float*)malloc(memSize);
Matrix matrixC_CPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_CPU};
MatMulUsual(matrixA, matrixB, matrixC_CPU);
//multiplicate withGPU
float *valsC_GPU = (float*)malloc(memSize);
Matrix matrixC_GPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_GPU};
//no use
// int numBlocks = 8 * 8;
//int numThreadsPerBlock = MATRIX_SIZE * MATRIX_SIZE / numBlocks;
float *valsA_d, *valsB_d, *valsC_d;
hipMalloc(&valsA_d, memSize);
hipMemcpy(valsA_d, valsA, memSize, hipMemcpyHostToDevice);
hipMalloc(&valsB_d, memSize);
hipMemcpy(valsB_d, valsB, memSize, hipMemcpyHostToDevice);
hipMalloc(&valsC_d, memSize);
Matrix A_d = {MATRIX_SIZE, MATRIX_SIZE, valsA_d};
Matrix B_d = {MATRIX_SIZE, MATRIX_SIZE, valsB_d};
Matrix C_d = {MATRIX_SIZE, MATRIX_SIZE, valsC_d};
//launch kernel
dim3 dimGrid(MATRIX_SIZE / BLOCK_SIZE, MATRIX_SIZE / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
MatMulKernel<<<dimGrid, dimBlock>>>(A_d, B_d, C_d);
//block until the device has completed
hipDeviceSynchronize();
//check errors
checkCUDAError("kernel invocation");
//data fetch
hipMemcpy(valsC_GPU, valsC_d, memSize, hipMemcpyDeviceToHost);
checkCUDAError("memcpy");
//verify the data
for (int i = 0; i < MATRIX_SIZE; ++i) {
for (int j = 0; j < MATRIX_SIZE; ++j) {
assert(GetElement(matrixC_CPU, i, j) == GetElement(matrixC_GPU, i, j));
}
}
hipFree(valsA_d);
hipFree(valsB_d);
hipFree(valsC_d);
free(valsA);
free(valsB);
free(valsC_CPU);
free(valsC_GPU);
printf("Correct!\n");
hipProfilerStop();
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x1
s_load_b32 s9, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_mov_b32_e32 v4, 0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 8
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s8, s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x18
v_and_b32_e32 v5, 0x3ff, v0
v_lshlrev_b32_e32 v4, 2, v1
s_ashr_i32 s10, s9, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s10, s10, 29
v_lshl_add_u32 v8, s14, 3, v5
v_lshlrev_b32_e32 v6, 5, v5
v_add_nc_u32_e32 v7, 0x100, v4
s_add_i32 s10, s9, s10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, s9, v8, v[1:2]
v_add_nc_u32_e32 v8, v6, v4
v_mov_b32_e32 v4, 0
v_lshl_add_u32 v3, s15, 3, v1
v_add_nc_u32_e32 v9, v7, v6
s_ashr_i32 s9, s10, 3
s_mov_b32 s10, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s11, s10, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s11, v5
v_add_nc_u32_e32 v10, s11, v2
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v11, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v14, v[10:11], off
global_load_b32 v12, v[12:13], off
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, v7
s_waitcnt vmcnt(1)
ds_store_b32 v8, v14
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s11, v6
s_add_i32 s11, s11, 4
ds_load_b32 v13, v10
ds_load_b32 v12, v12
v_add_nc_u32_e32 v10, 32, v10
s_cmp_eq_u32 s11, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v11, v12, v13
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v4, v4, v11
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s10, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x20
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, s14, 3, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, s0, v0
s_lshl_b32 s0, s15, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
*this file exercise matrix multiplication with shared memory and use
*the thought of dividing matrix to sub_matrix
*/
#include <hip/hip_runtime.h>
#include<time.h>
#include<stdlib.h>
#include<stdio.h>
#include<assert.h>
#include<hip/hip_runtime_api.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 64
typedef struct {
int width;
int height;
float *vals;
} Matrix;
float& GetElement(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__device__ float& GetElementKernel(const Matrix A, int row, int col) {
return A.vals[row * A.width + col];
}
__global__ void MatMulKernel(const Matrix A, const Matrix B, Matrix C) {
//__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
//__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
int range = A.width / BLOCK_SIZE;
float c_value = 0.0f;
for (int k = 0; k < range; ++k) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[threadIdx.x][threadIdx.y] = GetElementKernel(A, blockIdx.x * BLOCK_SIZE + threadIdx.x, k * BLOCK_SIZE + threadIdx.y);
Bs[threadIdx.x][threadIdx.y] = GetElementKernel(B, k * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y);
__syncthreads();
float tmp = 0.0f;
for (int block_k = 0; block_k < BLOCK_SIZE; ++block_k) {
tmp += As[threadIdx.x][block_k] * Bs[block_k][threadIdx.y];
}
c_value += tmp;
__syncthreads();
}
GetElementKernel(C, blockIdx.x * BLOCK_SIZE + threadIdx.x, blockIdx.y * BLOCK_SIZE + threadIdx.y) = c_value;
}
void MatMulUsual(const Matrix A, const Matrix B, Matrix C) {
for (int i = 0; i < C.height; ++i) {
for (int j = 0; j < C.width; ++j) {
float res = 0.0f;
for (int k = 0; k < A.width; ++k) {
res += GetElement(A, i, k) * GetElement(B, k, j);
}
GetElement(C, i, j) = res;
}
}
}
void checkCUDAError(const char *msg);
int main() {
size_t memSize = MATRIX_SIZE * MATRIX_SIZE * sizeof(float);
//initialize two matrix
srand(time(NULL));
float *valsA = (float*)malloc(memSize);
float *valsB = (float*)malloc(memSize);
for (int i = 1; i <= MATRIX_SIZE; ++i) {
for (int j = 1; j <= MATRIX_SIZE; ++j) {
valsA[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
valsB[(i - 1) * MATRIX_SIZE + (j - 1)] = (float)(rand()%100);
}
}
Matrix matrixA = {MATRIX_SIZE, MATRIX_SIZE, valsA};
Matrix matrixB = {MATRIX_SIZE, MATRIX_SIZE, valsB};
//multiplicate with CPU
float *valsC_CPU = (float*)malloc(memSize);
Matrix matrixC_CPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_CPU};
MatMulUsual(matrixA, matrixB, matrixC_CPU);
//multiplicate withGPU
float *valsC_GPU = (float*)malloc(memSize);
Matrix matrixC_GPU = {MATRIX_SIZE, MATRIX_SIZE, valsC_GPU};
//no use
// int numBlocks = 8 * 8;
//int numThreadsPerBlock = MATRIX_SIZE * MATRIX_SIZE / numBlocks;
float *valsA_d, *valsB_d, *valsC_d;
hipMalloc(&valsA_d, memSize);
hipMemcpy(valsA_d, valsA, memSize, hipMemcpyHostToDevice);
hipMalloc(&valsB_d, memSize);
hipMemcpy(valsB_d, valsB, memSize, hipMemcpyHostToDevice);
hipMalloc(&valsC_d, memSize);
Matrix A_d = {MATRIX_SIZE, MATRIX_SIZE, valsA_d};
Matrix B_d = {MATRIX_SIZE, MATRIX_SIZE, valsB_d};
Matrix C_d = {MATRIX_SIZE, MATRIX_SIZE, valsC_d};
//launch kernel
dim3 dimGrid(MATRIX_SIZE / BLOCK_SIZE, MATRIX_SIZE / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
MatMulKernel<<<dimGrid, dimBlock>>>(A_d, B_d, C_d);
//block until the device has completed
hipDeviceSynchronize();
//check errors
checkCUDAError("kernel invocation");
//data fetch
hipMemcpy(valsC_GPU, valsC_d, memSize, hipMemcpyDeviceToHost);
checkCUDAError("memcpy");
//verify the data
for (int i = 0; i < MATRIX_SIZE; ++i) {
for (int j = 0; j < MATRIX_SIZE; ++j) {
assert(GetElement(matrixC_CPU, i, j) == GetElement(matrixC_GPU, i, j));
}
}
hipFree(valsA_d);
hipFree(valsB_d);
hipFree(valsC_d);
free(valsA);
free(valsB);
free(valsC_CPU);
free(valsC_GPU);
printf("Correct!\n");
hipProfilerStop();
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.file "matrixMulti_fast.hip"
.globl _Z10GetElement6Matrixii # -- Begin function _Z10GetElement6Matrixii
.p2align 4, 0x90
.type _Z10GetElement6Matrixii,@function
_Z10GetElement6Matrixii: # @_Z10GetElement6Matrixii
.cfi_startproc
# %bb.0:
imull %edx, %edi
addl %ecx, %edi
movslq %edi, %rax
leaq (%rsi,%rax,4), %rax
retq
.Lfunc_end0:
.size _Z10GetElement6Matrixii, .Lfunc_end0-_Z10GetElement6Matrixii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z11MatMulUsual6MatrixS_S_ # -- Begin function _Z11MatMulUsual6MatrixS_S_
.p2align 4, 0x90
.type _Z11MatMulUsual6MatrixS_S_,@function
_Z11MatMulUsual6MatrixS_S_: # @_Z11MatMulUsual6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rcx, -16(%rsp) # 8-byte Spill
movq %r8, %rax
shrq $32, %rax
testl %eax, %eax
jle .LBB2_9
# %bb.1: # %.preheader28.lr.ph
movslq %edx, %rdx
movslq %edi, %r10
movslq %r8d, %r11
movl %r11d, %ebx
movl %r10d, %r14d
shlq $2, %r10
shlq $2, %rdx
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge32
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r10, %rsi
cmpq %rax, %r15
je .LBB2_9
.LBB2_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r8d, %r8d
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rcx
imulq %r11, %rcx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rcx,4), %r12
movq -16(%rsp), %rcx # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movss %xmm0, (%r12,%rbp,4)
incq %rbp
addq $4, %rcx
cmpq %rbx, %rbp
je .LBB2_8
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
xorps %xmm0, %xmm0
testl %edi, %edi
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movq %rcx, %r13
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
incq %r9
addq %rdx, %r13
cmpq %r9, %r14
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge34
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11MatMulUsual6MatrixS_S_, .Lfunc_end2-_Z11MatMulUsual6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movl $1, %r15d
movq %rax, %r12
movq %rbx, %r13
.p2align 4, 0x90
.LBB3_1: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rbp,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq $64, %rbp
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r15
addq $256, %r13 # imm = 0x100
addq $256, %r12 # imm = 0x100
cmpq $65, %r15
jne .LBB3_1
# %bb.4: # %.preheader28.i.preheader
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 24(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 16(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 24(%rsp), %rbp
movq 16(%rsp), %r13
movq 8(%rsp), %r12
movabsq $34359738376, %rdi # imm = 0x800000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movabsq $274877907008, %rax # imm = 0x4000000040
movq %rax, 112(%rsp)
movq %rbp, 120(%rsp)
movq %rax, 96(%rsp)
movq %r13, 104(%rsp)
movq %rax, 80(%rsp)
movq %r12, 88(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_7
# %bb.9: # %_Z14checkCUDAErrorPKc.exit
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %.preheader.preheader
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
callq hipProfilerStop
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
jmp .LBB3_8
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.1, %edx
.LBB3_8:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB4_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z14checkCUDAErrorPKc, .Lfunc_end4-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel invocation"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ ISETP.GT.AND P0, PT, R2, 0x7, PT ; /* 0x000000070200780c */
/* 0x000fe40003f04270 */
/*0040*/ SHF.R.S32.HI R0, RZ, 0x1f, R2 ; /* 0x0000001fff007819 */
/* 0x000fc80000011402 */
/*0050*/ LEA.HI R0, R0, c[0x0][0x160], RZ, 0x3 ; /* 0x0000580000007a11 */
/* 0x000fce00078f18ff */
/*0060*/ @!P0 MOV R24, RZ ; /* 0x000000ff00188202 */
/* 0x000fe20000000f00 */
/*0070*/ @!P0 BRA 0x7c0 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*0080*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0090*/ LOP3.LUT R2, R2, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff802027812 */
/* 0x000fe200078ec0ff */
/*00a0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.R.S32.HI R0, RZ, 0x3, R0 ; /* 0x00000003ff007819 */
/* 0x000fe20000011400 */
/*00c0*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e220000002100 */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x8, PT ; /* 0x000000080200780c */
/* 0x000fe40003f05270 */
/*00e0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe20000000f00 */
/*00f0*/ S2R R18, SR_TID.Y ; /* 0x0000000000127919 */
/* 0x000e620000002200 */
/*0100*/ LOP3.LUT R21, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100157812 */
/* 0x000fc600078ec0ff */
/*0110*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ea20000002600 */
/*0120*/ LEA R23, R4, R17, 0x3 ; /* 0x0000001104177211 */
/* 0x001fe400078e18ff */
/*0130*/ SHF.L.U32 R19, R17, 0x5, RZ ; /* 0x0000000511137819 */
/* 0x000fc600000006ff */
/*0140*/ IMAD R23, R23, c[0x0][0x160], R18 ; /* 0x0000580017177a24 */
/* 0x002fe200078e0212 */
/*0150*/ LEA R22, R18, R19, 0x2 ; /* 0x0000001312167211 */
/* 0x000fe400078e10ff */
/*0160*/ LEA R20, R3, R18, 0x3 ; /* 0x0000001203147211 */
/* 0x004fe200078e18ff */
/*0170*/ @!P0 BRA 0x5b0 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R25, R0, -R21, RZ ; /* 0x8000001500197210 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fc60000000f00 */
/*01b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*01c0*/ LEA R13, R16.reuse, R17, 0x3 ; /* 0x00000011100d7211 */
/* 0x040fe400078e18ff */
/*01d0*/ LEA R3, R16, R23, 0x3 ; /* 0x0000001710037211 */
/* 0x000fc600078e18ff */
/*01e0*/ IMAD R5, R13, c[0x0][0x170], R20 ; /* 0x00005c000d057a24 */
/* 0x000fc800078e0214 */
/*01f0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fc800078e0200 */
/*0200*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe400078e0200 */
/*0210*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0230*/ IADD3 R13, R13, 0x8, RZ ; /* 0x000000080d0d7810 */
/* 0x000fc60007ffe0ff */
/*0240*/ STS [R22+0x100], R5 ; /* 0x0001000516007388 */
/* 0x004fe80000000800 */
/*0250*/ STS [R22], R7 ; /* 0x0000000716007388 */
/* 0x008fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R15, [R18.X4+0x100] ; /* 0x00010000120f7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R8, [R19] ; /* 0x0000000013087984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R6, [R18.X4+0x120] ; /* 0x0001200012067984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R12, [R18.X4+0x140] ; /* 0x00014000120c7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R28, [R18.X4+0x160] ; /* 0x00016000121c7984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R29, [R18.X4+0x180] ; /* 0x00018000121d7984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS R27, [R18.X4+0x1c0] ; /* 0x0001c000121b7984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS R26, [R18.X4+0x1e0] ; /* 0x0001e000121a7984 */
/* 0x000fe20000004800 */
/*02f0*/ FFMA R8, R15, R8, RZ ; /* 0x000000080f087223 */
/* 0x001fc400000000ff */
/*0300*/ IMAD R15, R13, c[0x0][0x170], R20 ; /* 0x00005c000d0f7a24 */
/* 0x000fe400078e0214 */
/*0310*/ FFMA R13, R6, R9, R8 ; /* 0x00000009060d7223 */
/* 0x002fe40000000008 */
/*0320*/ IMAD.WIDE R8, R15, R0, c[0x0][0x178] ; /* 0x00005e000f087625 */
/* 0x000fe200078e0200 */
/*0330*/ LDS.128 R4, [R19+0x10] ; /* 0x0000100013047984 */
/* 0x000e280000000c00 */
/*0340*/ LDS R0, [R18.X4+0x1a0] ; /* 0x0001a00012007984 */
/* 0x000e680000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ LDG.E R3, [R2.64+0x20] ; /* 0x0000200402037981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f62000c1e1900 */
/*0380*/ FFMA R10, R12, R10, R13 ; /* 0x0000000a0c0a7223 */
/* 0x004fc8000000000d */
/*0390*/ FFMA R10, R28, R11, R10 ; /* 0x0000000b1c0a7223 */
/* 0x008fc8000000000a */
/*03a0*/ FFMA R4, R29, R4, R10 ; /* 0x000000041d047223 */
/* 0x001fe2000000000a */
/*03b0*/ IADD3 R25, R25, -0x2, RZ ; /* 0xfffffffe19197810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ FFMA R0, R0, R5, R4 ; /* 0x0000000500007223 */
/* 0x002fe20000000004 */
/*03d0*/ ISETP.NE.AND P0, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fc60003f05270 */
/*03e0*/ FFMA R0, R27, R6, R0 ; /* 0x000000061b007223 */
/* 0x000fc80000000000 */
/*03f0*/ FFMA R7, R26, R7, R0 ; /* 0x000000071a077223 */
/* 0x000fc80000000000 */
/*0400*/ FADD R7, R7, R24 ; /* 0x0000001807077221 */
/* 0x000fe20000000000 */
/*0410*/ IADD3 R16, R16, 0x2, RZ ; /* 0x0000000210107810 */
/* 0x000fe20007ffe0ff */
/*0420*/ STS [R22], R3 ; /* 0x0000000316007388 */
/* 0x010fe80000000800 */
/*0430*/ STS [R22+0x100], R9 ; /* 0x0001000916007388 */
/* 0x020fe80000000800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0450*/ LDS R2, [R18.X4+0x100] ; /* 0x0001000012027984 */
/* 0x000fe80000004800 */
/*0460*/ LDS.128 R12, [R19] ; /* 0x00000000130c7984 */
/* 0x000e280000000c00 */
/*0470*/ LDS R28, [R18.X4+0x120] ; /* 0x00012000121c7984 */
/* 0x000e680000004800 */
/*0480*/ LDS R11, [R18.X4+0x140] ; /* 0x00014000120b7984 */
/* 0x000ea80000004800 */
/*0490*/ LDS R3, [R18.X4+0x180] ; /* 0x0001800012037984 */
/* 0x000fe20000004800 */
/*04a0*/ FFMA R12, R2, R12, RZ ; /* 0x0000000c020c7223 */
/* 0x001fc600000000ff */
/*04b0*/ LDS R2, [R18.X4+0x160] ; /* 0x0001600012027984 */
/* 0x000e220000004800 */
/*04c0*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x002fc6000000000c */
/*04d0*/ LDS R13, [R18.X4+0x1c0] ; /* 0x0001c000120d7984 */
/* 0x000fe20000004800 */
/*04e0*/ FFMA R12, R11, R14, R12 ; /* 0x0000000e0b0c7223 */
/* 0x004fc6000000000c */
/*04f0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000e680000000c00 */
/*0500*/ LDS R14, [R18.X4+0x1a0] ; /* 0x0001a000120e7984 */
/* 0x000ea20000004800 */
/*0510*/ FFMA R12, R2, R15, R12 ; /* 0x0000000f020c7223 */
/* 0x001fc6000000000c */
/*0520*/ LDS R2, [R18.X4+0x1e0] ; /* 0x0001e00012027984 */
/* 0x000e220000004800 */
/*0530*/ FFMA R8, R3, R8, R12 ; /* 0x0000000803087223 */
/* 0x002fc8000000000c */
/*0540*/ FFMA R8, R14, R9, R8 ; /* 0x000000090e087223 */
/* 0x004fc80000000008 */
/*0550*/ FFMA R8, R13, R10, R8 ; /* 0x0000000a0d087223 */
/* 0x000fc80000000008 */
/*0560*/ FFMA R2, R2, R11, R8 ; /* 0x0000000b02027223 */
/* 0x001fc80000000008 */
/*0570*/ FADD R24, R7, R2 ; /* 0x0000000207187221 */
/* 0x000fe20000000000 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0590*/ @P0 BRA 0x1b0 ; /* 0xfffffc1000000947 */
/* 0x000fea000383ffff */
/*05a0*/ SHF.L.U32 R16, R16, 0x3, RZ ; /* 0x0000000310107819 */
/* 0x000fe400000006ff */
/*05b0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 BRA 0x7c0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R17, R17, R16.reuse, RZ ; /* 0x0000001011117210 */
/* 0x080fe40007ffe0ff */
/*05e0*/ IADD3 R2, R23, R16, RZ ; /* 0x0000001017027210 */
/* 0x000fe40007ffe0ff */
/*05f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD R12, R17, c[0x0][0x170], R20 ; /* 0x00005c00110c7a24 */
/* 0x000fc800078e0214 */
/*0610*/ IMAD.WIDE R2, R2, R13, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e020d */
/*0620*/ IMAD.WIDE R12, R12, R13, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fe400078e020d */
/*0630*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee8000c1e1900 */
/*0650*/ STS [R22], R3 ; /* 0x0000000316007388 */
/* 0x004fe80000000800 */
/*0660*/ STS [R22+0x100], R13 ; /* 0x0001000d16007388 */
/* 0x008fe80000000800 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ LDS R15, [R18.X4+0x100] ; /* 0x00010000120f7984 */
/* 0x000fe80000004800 */
/*0690*/ LDS.128 R4, [R19] ; /* 0x0000000013047984 */
/* 0x000e280000000c00 */
/*06a0*/ LDS R0, [R18.X4+0x120] ; /* 0x0001200012007984 */
/* 0x000e680000004800 */
/*06b0*/ LDS R14, [R18.X4+0x140] ; /* 0x00014000120e7984 */
/* 0x000ea80000004800 */
/*06c0*/ LDS R16, [R18.X4+0x160] ; /* 0x0001600012107984 */
/* 0x000ee80000004800 */
/*06d0*/ LDS R17, [R18.X4+0x180] ; /* 0x0001800012117984 */
/* 0x000fe80000004800 */
/*06e0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000f280000000c00 */
/*06f0*/ LDS R2, [R18.X4+0x1a0] ; /* 0x0001a00012027984 */
/* 0x000f680000004800 */
/*0700*/ LDS R3, [R18.X4+0x1c0] ; /* 0x0001c00012037984 */
/* 0x000f680000004800 */
/*0710*/ LDS R12, [R18.X4+0x1e0] ; /* 0x0001e000120c7984 */
/* 0x000f620000004800 */
/*0720*/ FFMA R4, R15, R4, RZ ; /* 0x000000040f047223 */
/* 0x001fc800000000ff */
/*0730*/ FFMA R5, R0, R5, R4 ; /* 0x0000000500057223 */
/* 0x002fc80000000004 */
/*0740*/ FFMA R6, R14, R6, R5 ; /* 0x000000060e067223 */
/* 0x004fc80000000005 */
/*0750*/ FFMA R7, R16, R7, R6 ; /* 0x0000000710077223 */
/* 0x008fc80000000006 */
/*0760*/ FFMA R8, R17, R8, R7 ; /* 0x0000000811087223 */
/* 0x010fc80000000007 */
/*0770*/ FFMA R9, R2, R9, R8 ; /* 0x0000000902097223 */
/* 0x020fc80000000008 */
/*0780*/ FFMA R10, R3, R10, R9 ; /* 0x0000000a030a7223 */
/* 0x000fc80000000009 */
/*0790*/ FFMA R11, R12, R11, R10 ; /* 0x0000000b0c0b7223 */
/* 0x000fc8000000000a */
/*07a0*/ FADD R24, R24, R11 ; /* 0x0000000b18187221 */
/* 0x000fe20000000000 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*07d0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*07e0*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*07f0*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0800*/ LEA R0, R0, R3, 0x3 ; /* 0x0000000300007211 */
/* 0x001fe200078e18ff */
/*0810*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0820*/ LEA R5, R2, R5, 0x3 ; /* 0x0000000502057211 */
/* 0x002fca00078e18ff */
/*0830*/ IMAD R2, R0, c[0x0][0x180], R5 ; /* 0x0000600000027a24 */
/* 0x000fc800078e0205 */
/*0840*/ IMAD.WIDE R2, R2, R3, c[0x0][0x188] ; /* 0x0000620002027625 */
/* 0x000fca00078e0203 */
/*0850*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0860*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x1
s_load_b32 s9, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_mov_b32_e32 v4, 0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 8
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s8, s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x18
v_and_b32_e32 v5, 0x3ff, v0
v_lshlrev_b32_e32 v4, 2, v1
s_ashr_i32 s10, s9, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s10, s10, 29
v_lshl_add_u32 v8, s14, 3, v5
v_lshlrev_b32_e32 v6, 5, v5
v_add_nc_u32_e32 v7, 0x100, v4
s_add_i32 s10, s9, s10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, s9, v8, v[1:2]
v_add_nc_u32_e32 v8, v6, v4
v_mov_b32_e32 v4, 0
v_lshl_add_u32 v3, s15, 3, v1
v_add_nc_u32_e32 v9, v7, v6
s_ashr_i32 s9, s10, 3
s_mov_b32 s10, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s11, s10, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s11, v5
v_add_nc_u32_e32 v10, s11, v2
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v11, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v14, v[10:11], off
global_load_b32 v12, v[12:13], off
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, v7
s_waitcnt vmcnt(1)
ds_store_b32 v8, v14
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s11, v6
s_add_i32 s11, s11, 4
ds_load_b32 v13, v10
ds_load_b32 v12, v12
v_add_nc_u32_e32 v10, 32, v10
s_cmp_eq_u32 s11, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v11, v12, v13
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v4, v4, v11
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s10, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x20
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, s14, 3, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, s0, v0
s_lshl_b32 s0, s15, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000012e1_00000000-6_matrixMulti_fast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10GetElement6Matrixii
.type _Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB2057:
.cfi_startproc
endbr64
imull %edi, %edx
addl %ecx, %edx
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %rax
ret
.cfi_endproc
.LFE2057:
.size _Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
.globl _Z16GetElementKernel6Matrixii
.type _Z16GetElementKernel6Matrixii, @function
_Z16GetElementKernel6Matrixii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z16GetElementKernel6Matrixii, .-_Z16GetElementKernel6Matrixii
.globl _Z11MatMulUsual6MatrixS_S_
.type _Z11MatMulUsual6MatrixS_S_, @function
_Z11MatMulUsual6MatrixS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rcx, -24(%rsp)
movq %r9, -16(%rsp)
movq %r8, %rcx
sarq $32, %rcx
movl %ecx, -32(%rsp)
testl %ecx, %ecx
jle .L6
movq %rsi, %rbp
movq %rdx, %rax
movl %edi, %r11d
movl %r8d, %r15d
movl %edi, -28(%rsp)
cltq
leaq 0(,%rax,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %r8d, %rbx
movslq %edi, %rax
movq %rax, -8(%rsp)
movl %r8d, %ecx
jmp .L8
.L9:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L9
.L11:
movss %xmm1, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %rbx, %r8
je .L16
.L12:
movq %r9, %rdx
movq %r14, %rax
pxor %xmm1, %xmm1
testl %r11d, %r11d
jg .L9
jmp .L11
.L16:
movl -36(%rsp), %edx
.L10:
addl $1, %edx
addl %r15d, %r12d
movl -28(%rsp), %eax
addl %eax, %r13d
cmpl %edx, -32(%rsp)
je .L6
.L8:
testl %ecx, %ecx
jle .L10
movq -24(%rsp), %r9
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r14
movq -8(%rsp), %rdi
addq %rdi, %rax
leaq 0(%rbp,%rax,4), %rdi
movslq %r12d, %rax
movq -16(%rsp), %r10
leaq (%r10,%rax,4), %r10
movl $0, %r8d
movl %edx, -36(%rsp)
jmp .L12
.L6:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11MatMulUsual6MatrixS_S_, .-_Z11MatMulUsual6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.section .rodata.str1.1
.LC2:
.string "kernel invocation"
.LC3:
.string "memcpy"
.LC4:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $16384, %edi
call malloc@PLT
movq %rax, %rbx
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
leaq 256(%rbx), %r13
leaq 256(%rax), %r14
leaq 16640(%rbx), %r15
.L32:
movl $0, %r12d
.L33:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -256(%r13,%r12)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -256(%r14,%r12)
addq $4, %r12
cmpq $256, %r12
jne .L33
addq $256, %r13
addq $256, %r14
cmpq %r15, %r13
jne .L32
movabsq $274877906944, %r12
movq %r12, %r13
orq $64, %r13
movl $16384, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r13, %r8
movq %rax, %r9
movq %r13, %rdx
movq %rbp, %rcx
movq %r13, %rdi
movq %rbx, %rsi
call _Z11MatMulUsual6MatrixS_S_
movl $16384, %edi
call malloc@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movq 16(%rsp), %r14
movq 24(%rsp), %r13
movq 32(%rsp), %r12
movl $8, 40(%rsp)
movl $8, 44(%rsp)
movl $8, 52(%rsp)
movl $8, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L35:
call cudaThreadSynchronize@PLT
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $16384, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $64, %edx
.L36:
movl $64, %eax
.L37:
subl $1, %eax
jne .L37
subl $1, %edx
jne .L36
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaProfilerStop@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movl $64, 64(%rsp)
movl $64, 68(%rsp)
movq %r14, 72(%rsp)
movl $64, 80(%rsp)
movl $64, 84(%rsp)
movq %r13, 88(%rsp)
movl $64, 96(%rsp)
movl $64, 100(%rsp)
movq %r12, 104(%rsp)
leaq 96(%rsp), %rdx
leaq 80(%rsp), %rsi
leaq 64(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_RK6MatrixS1_RS_
jmp .L35
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMulti_fast.hip"
.globl _Z10GetElement6Matrixii # -- Begin function _Z10GetElement6Matrixii
.p2align 4, 0x90
.type _Z10GetElement6Matrixii,@function
_Z10GetElement6Matrixii: # @_Z10GetElement6Matrixii
.cfi_startproc
# %bb.0:
imull %edx, %edi
addl %ecx, %edi
movslq %edi, %rax
leaq (%rsi,%rax,4), %rax
retq
.Lfunc_end0:
.size _Z10GetElement6Matrixii, .Lfunc_end0-_Z10GetElement6Matrixii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z11MatMulUsual6MatrixS_S_ # -- Begin function _Z11MatMulUsual6MatrixS_S_
.p2align 4, 0x90
.type _Z11MatMulUsual6MatrixS_S_,@function
_Z11MatMulUsual6MatrixS_S_: # @_Z11MatMulUsual6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rcx, -16(%rsp) # 8-byte Spill
movq %r8, %rax
shrq $32, %rax
testl %eax, %eax
jle .LBB2_9
# %bb.1: # %.preheader28.lr.ph
movslq %edx, %rdx
movslq %edi, %r10
movslq %r8d, %r11
movl %r11d, %ebx
movl %r10d, %r14d
shlq $2, %r10
shlq $2, %rdx
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge32
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r10, %rsi
cmpq %rax, %r15
je .LBB2_9
.LBB2_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r8d, %r8d
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rcx
imulq %r11, %rcx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rcx,4), %r12
movq -16(%rsp), %rcx # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movss %xmm0, (%r12,%rbp,4)
incq %rbp
addq $4, %rcx
cmpq %rbx, %rbp
je .LBB2_8
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
xorps %xmm0, %xmm0
testl %edi, %edi
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movq %rcx, %r13
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
incq %r9
addq %rdx, %r13
cmpq %r9, %r14
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge34
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11MatMulUsual6MatrixS_S_, .Lfunc_end2-_Z11MatMulUsual6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movl $1, %r15d
movq %rax, %r12
movq %rbx, %r13
.p2align 4, 0x90
.LBB3_1: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rbp,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq $64, %rbp
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r15
addq $256, %r13 # imm = 0x100
addq $256, %r12 # imm = 0x100
cmpq $65, %r15
jne .LBB3_1
# %bb.4: # %.preheader28.i.preheader
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 24(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 16(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 24(%rsp), %rbp
movq 16(%rsp), %r13
movq 8(%rsp), %r12
movabsq $34359738376, %rdi # imm = 0x800000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movabsq $274877907008, %rax # imm = 0x4000000040
movq %rax, 112(%rsp)
movq %rbp, 120(%rsp)
movq %rax, 96(%rsp)
movq %r13, 104(%rsp)
movq %rax, 80(%rsp)
movq %r12, 88(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_7
# %bb.9: # %_Z14checkCUDAErrorPKc.exit
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %.preheader.preheader
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
callq hipProfilerStop
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
jmp .LBB3_8
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.1, %edx
.LBB3_8:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB4_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z14checkCUDAErrorPKc, .Lfunc_end4-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel invocation"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define ARRAY_SIZE 10000
#define CUDA_CALL(x) { const cudaError_t a = (x); if(a != cudaSuccess) { printf("\nCuda Error: %s (err_num=%d) at line:%d\n", cudaGetErrorString(a), a, __LINE__); cudaDeviceReset(); assert(0);}}
void init_array(int arr[ARRAY_SIZE])
{
for(int i = 0 ; i < ARRAY_SIZE ; ++i)
arr[i] = rand()/10000;
}
static __global__ void cuda_noPath(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
if (threadIdx.x % (i*2) == 0 && tid + i < size)
arr[tid] = max(arr[tid], arr[tid + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
static __global__ void cuda_Path(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
int base = blockIdx.x * blockDim.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
int off = threadIdx.x * i*2;
int idx = base + off;
if ( off < blockDim.x && idx + i < size)
arr[tid] = max(arr[idx], arr[idx + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
extern "C" void cuda_2(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
cudaEvent_t start,stop;
CUDA_CALL(cudaMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(cudaMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(cudaMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, cudaMemcpyHostToDevice));
float dev_time = 0.f;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_Path<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&dev_time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("[CUDA Path] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(cudaMemcpy(res, arr_dev, sizeof(int), cudaMemcpyDeviceToHost));
CUDA_CALL( cudaDeviceSynchronize() );
CUDA_CALL(cudaFree(arr_dev));
CUDA_CALL(cudaFree(output_dev));
}
extern "C" void cuda_1(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
cudaEvent_t start,stop;
CUDA_CALL(cudaMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(cudaMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(cudaMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, cudaMemcpyHostToDevice));
float dev_time = 0.f;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_noPath<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&dev_time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("[CUDA noPath] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(cudaMemcpy(res, arr_dev, sizeof(int), cudaMemcpyDeviceToHost));
CUDA_CALL( cudaDeviceSynchronize() );
CUDA_CALL(cudaFree(arr_dev));
CUDA_CALL(cudaFree(output_dev));
}
int arr[ARRAY_SIZE],
res_cuda1,
res_cuda2;
int main(int argc, char *argv[])
{
init_array(arr);
cuda_1(&res_cuda1,arr);
cuda_2(&res_cuda2,arr);
return 0;
} | code for sm_80
Function : _Z9cuda_PathPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R2, R13, c[0x0][0x0], R8 ; /* 0x000000000d027a24 */
/* 0x001fc800078e0208 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd000078e0203 */
/*0090*/ @!P0 BRA 0x1f0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD R4, R0, R9, RZ ; /* 0x0000000900047224 */
/* 0x000fe200078e02ff */
/*00d0*/ BSSY B0, 0x1b0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*00e0*/ IMAD R6, R13, c[0x0][0x0], R4 ; /* 0x000000000d067a24 */
/* 0x000fca00078e0204 */
/*00f0*/ IADD3 R5, R6, R9, RZ ; /* 0x0000000906057210 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06270 */
/*0110*/ ISETP.GE.U32.OR P0, PT, R4, c[0x0][0x0], P0 ; /* 0x0000000004007a0c */
/* 0x000fda0000706470 */
/*0120*/ @P0 BRA 0x1a0 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fcc00078e0205 */
/*0150*/ IMAD.WIDE R6, R9, 0x4, R4 ; /* 0x0000000409067825 */
/* 0x000fe400078e0204 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IMNMX R11, R6, R5, !PT ; /* 0x00000005060b7217 */
/* 0x004fca0007800200 */
/*0190*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ SHF.L.U32 R9, R9, 0x1, RZ ; /* 0x0000000109097819 */
/* 0x000fe200000006ff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @!P0 BRA 0xc0 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*01f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea2000c1e1900 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.WIDE.U32 R4, R13, R4, c[0x0][0x168] ; /* 0x00005a000d047625 */
/* 0x000fca00078e0004 */
/*0240*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11cuda_noPathPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fca00078e0209 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fce00078e0203 */
/*0090*/ @!P0 BRA 0x2c0 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fca00078e00ff */
/*00b0*/ SHF.L.U32 R12, R7, 0x1, RZ ; /* 0x00000001070c7819 */
/* 0x000fe200000006ff */
/*00c0*/ BSSY B0, 0x280 ; /* 0x000001b000007945 */
/* 0x000fe60003800000 */
/*00d0*/ I2F.U32.RP R6, R12 ; /* 0x0000000c00067306 */
/* 0x000e220000209000 */
/*00e0*/ IMAD.MOV R11, RZ, RZ, -R12 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0c */
/*00f0*/ ISETP.NE.U32.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fcc0003f25070 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R11, R11, R5, RZ ; /* 0x000000050b0b7224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fe200078e0004 */
/*0160*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fca0007ffe0ff */
/*0170*/ IMAD.HI.U32 R5, R5, R9, RZ ; /* 0x0000000905057227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R10, RZ, RZ, -R5 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a05 */
/*0190*/ IMAD R5, R12, R10, R9 ; /* 0x0000000a0c057224 */
/* 0x000fca00078e0209 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R5, R12, PT ; /* 0x0000000c0500720c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R5, -R12, R5, RZ ; /* 0x000000050c050210 */
/* 0x000fc80007ffe1ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R5, R12, PT ; /* 0x0000000c0500720c */
/* 0x000fda0003f06070 */
/*01d0*/ @P0 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a0c */
/*01e0*/ @!P1 LOP3.LUT R5, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff059212 */
/* 0x000fc800078e33ff */
/*01f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*0200*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x000fda0000706670 */
/*0210*/ @P0 BRA 0x270 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*0230*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000eaa000c1e1900 */
/*0240*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0250*/ IMNMX R7, R6, R5, !PT ; /* 0x0000000506077217 */
/* 0x004fca0007800200 */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GE.U32.AND P0, PT, R12, c[0x0][0x0], PT ; /* 0x000000000c007a0c */
/* 0x000fe20003f06070 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff077224 */
/* 0x001fd800078e000c */
/*02b0*/ @!P0 BRA 0xb0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*02c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*02d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0310*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define ARRAY_SIZE 10000
#define CUDA_CALL(x) { const cudaError_t a = (x); if(a != cudaSuccess) { printf("\nCuda Error: %s (err_num=%d) at line:%d\n", cudaGetErrorString(a), a, __LINE__); cudaDeviceReset(); assert(0);}}
void init_array(int arr[ARRAY_SIZE])
{
for(int i = 0 ; i < ARRAY_SIZE ; ++i)
arr[i] = rand()/10000;
}
static __global__ void cuda_noPath(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
if (threadIdx.x % (i*2) == 0 && tid + i < size)
arr[tid] = max(arr[tid], arr[tid + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
static __global__ void cuda_Path(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
int base = blockIdx.x * blockDim.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
int off = threadIdx.x * i*2;
int idx = base + off;
if ( off < blockDim.x && idx + i < size)
arr[tid] = max(arr[idx], arr[idx + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
extern "C" void cuda_2(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
cudaEvent_t start,stop;
CUDA_CALL(cudaMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(cudaMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(cudaMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, cudaMemcpyHostToDevice));
float dev_time = 0.f;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_Path<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&dev_time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("[CUDA Path] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(cudaMemcpy(res, arr_dev, sizeof(int), cudaMemcpyDeviceToHost));
CUDA_CALL( cudaDeviceSynchronize() );
CUDA_CALL(cudaFree(arr_dev));
CUDA_CALL(cudaFree(output_dev));
}
extern "C" void cuda_1(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
cudaEvent_t start,stop;
CUDA_CALL(cudaMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(cudaMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(cudaMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, cudaMemcpyHostToDevice));
float dev_time = 0.f;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_noPath<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&dev_time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("[CUDA noPath] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(cudaMemcpy(res, arr_dev, sizeof(int), cudaMemcpyDeviceToHost));
CUDA_CALL( cudaDeviceSynchronize() );
CUDA_CALL(cudaFree(arr_dev));
CUDA_CALL(cudaFree(output_dev));
}
int arr[ARRAY_SIZE],
res_cuda1,
res_cuda2;
int main(int argc, char *argv[])
{
init_array(arr);
cuda_1(&res_cuda1,arr);
cuda_2(&res_cuda2,arr);
return 0;
} | .file "tmpxft_0019be2d_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i, @function
_ZL31__device_stub__Z9cuda_PathPiS_iPiS_i:
.LFB2087:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL9cuda_PathPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i, .-_ZL31__device_stub__Z9cuda_PathPiS_iPiS_i
.type _ZL9cuda_PathPiS_i, @function
_ZL9cuda_PathPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL9cuda_PathPiS_i, .-_ZL9cuda_PathPiS_i
.type _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i, @function
_ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i:
.LFB2085:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL11cuda_noPathPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i, .-_ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i
.type _ZL11cuda_noPathPiS_i, @function
_ZL11cuda_noPathPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL11cuda_noPathPiS_i, .-_ZL11cuda_noPathPiS_i
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_arrayPi
.type _Z10init_arrayPi, @function
_Z10init_arrayPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq 40000(%rdi), %rbp
.L20:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
sarl $31, %eax
subl %eax, %edx
movl %edx, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10init_arrayPi, .-_Z10init_arrayPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nCuda Error: %s (err_num=%d) at line:%d\n"
.align 8
.LC3:
.string "[CUDA Path] Elapsed Time : %.5f (sec).\n"
.text
.globl cuda_2
.type cuda_2, @function
cuda_2:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
.L24:
leaq 16(%rsp), %rdi
movl $160, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
.L25:
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L38
.L26:
movl $0x00000000, 12(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ebp
movl $40, %ebx
movl $10000, %r13d
.L28:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L27:
movq 24(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 24(%rsp)
movq %rax, 16(%rsp)
leal 510(%rbx), %eax
movl %ebx, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %ebx, %r13d
subl $1, %ebp
jne .L34
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movss 12(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
.L29:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
.L30:
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L42
.L31:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $60, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L24
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $61, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L25
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $64, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L26
.L34:
movl %eax, %ebx
jmp .L28
.L39:
movl %r13d, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i
jmp .L27
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $96, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L29
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $97, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L30
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $99, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L31
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $100, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L23
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size cuda_2, .-cuda_2
.section .rodata.str1.8
.align 8
.LC4:
.string "[CUDA noPath] Elapsed Time : %.5f (sec).\n"
.text
.globl cuda_1
.type cuda_1, @function
cuda_1:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
.L46:
leaq 16(%rsp), %rdi
movl $160, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L59
.L47:
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L60
.L48:
movl $0x00000000, 12(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ebp
movl $40, %ebx
movl $10000, %r13d
.L50:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L49:
movq 24(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 24(%rsp)
movq %rax, 16(%rsp)
leal 510(%rbx), %eax
movl %ebx, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %ebx, %r13d
subl $1, %ebp
jne .L56
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movss 12(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
.L51:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
.L52:
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
.L53:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
.L45:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $116, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L46
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $117, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L47
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $120, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L48
.L56:
movl %eax, %ebx
jmp .L50
.L61:
movl %r13d, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i
jmp .L49
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $152, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L51
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $153, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L52
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $155, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L53
.L65:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $156, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L45
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size cuda_1, .-cuda_1
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq arr(%rip), %rbx
movq %rbx, %rdi
call _Z10init_arrayPi
movq %rbx, %rsi
leaq res_cuda1(%rip), %rdi
call cuda_1
movq %rbx, %rsi
leaq res_cuda2(%rip), %rdi
call cuda_2
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z9cuda_PathPiS_i"
.LC6:
.string "_Z11cuda_noPathPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9cuda_PathPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11cuda_noPathPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res_cuda2
.bss
.align 4
.type res_cuda2, @object
.size res_cuda2, 4
res_cuda2:
.zero 4
.globl res_cuda1
.align 4
.type res_cuda1, @object
.size res_cuda1, 4
res_cuda1:
.zero 4
.globl arr
.align 32
.type arr, @object
.size arr, 40000
arr:
.zero 40000
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define ARRAY_SIZE 10000
#define CUDA_CALL(x) { const cudaError_t a = (x); if(a != cudaSuccess) { printf("\nCuda Error: %s (err_num=%d) at line:%d\n", cudaGetErrorString(a), a, __LINE__); cudaDeviceReset(); assert(0);}}
void init_array(int arr[ARRAY_SIZE])
{
for(int i = 0 ; i < ARRAY_SIZE ; ++i)
arr[i] = rand()/10000;
}
static __global__ void cuda_noPath(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
if (threadIdx.x % (i*2) == 0 && tid + i < size)
arr[tid] = max(arr[tid], arr[tid + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
static __global__ void cuda_Path(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
int base = blockIdx.x * blockDim.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
int off = threadIdx.x * i*2;
int idx = base + off;
if ( off < blockDim.x && idx + i < size)
arr[tid] = max(arr[idx], arr[idx + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
extern "C" void cuda_2(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
cudaEvent_t start,stop;
CUDA_CALL(cudaMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(cudaMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(cudaMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, cudaMemcpyHostToDevice));
float dev_time = 0.f;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_Path<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&dev_time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("[CUDA Path] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(cudaMemcpy(res, arr_dev, sizeof(int), cudaMemcpyDeviceToHost));
CUDA_CALL( cudaDeviceSynchronize() );
CUDA_CALL(cudaFree(arr_dev));
CUDA_CALL(cudaFree(output_dev));
}
extern "C" void cuda_1(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
cudaEvent_t start,stop;
CUDA_CALL(cudaMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(cudaMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(cudaMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, cudaMemcpyHostToDevice));
float dev_time = 0.f;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_noPath<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&dev_time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("[CUDA noPath] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(cudaMemcpy(res, arr_dev, sizeof(int), cudaMemcpyDeviceToHost));
CUDA_CALL( cudaDeviceSynchronize() );
CUDA_CALL(cudaFree(arr_dev));
CUDA_CALL(cudaFree(output_dev));
}
int arr[ARRAY_SIZE],
res_cuda1,
res_cuda2;
int main(int argc, char *argv[])
{
init_array(arr);
cuda_1(&res_cuda1,arr);
cuda_2(&res_cuda2,arr);
return 0;
} | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define ARRAY_SIZE 10000
#define CUDA_CALL(x) { const hipError_t a = (x); if(a != hipSuccess) { printf("\nCuda Error: %s (err_num=%d) at line:%d\n", hipGetErrorString(a), a, __LINE__); hipDeviceReset(); assert(0);}}
void init_array(int arr[ARRAY_SIZE])
{
for(int i = 0 ; i < ARRAY_SIZE ; ++i)
arr[i] = rand()/10000;
}
static __global__ void cuda_noPath(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
if (threadIdx.x % (i*2) == 0 && tid + i < size)
arr[tid] = max(arr[tid], arr[tid + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
static __global__ void cuda_Path(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
int base = blockIdx.x * blockDim.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
int off = threadIdx.x * i*2;
int idx = base + off;
if ( off < blockDim.x && idx + i < size)
arr[tid] = max(arr[idx], arr[idx + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
extern "C" void cuda_2(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
hipEvent_t start,stop;
CUDA_CALL(hipMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(hipMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(hipMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, hipMemcpyHostToDevice));
float dev_time = 0.f;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_Path<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&dev_time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("[CUDA Path] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(hipMemcpy(res, arr_dev, sizeof(int), hipMemcpyDeviceToHost));
CUDA_CALL( hipDeviceSynchronize() );
CUDA_CALL(hipFree(arr_dev));
CUDA_CALL(hipFree(output_dev));
}
extern "C" void cuda_1(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
hipEvent_t start,stop;
CUDA_CALL(hipMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(hipMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(hipMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, hipMemcpyHostToDevice));
float dev_time = 0.f;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_noPath<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&dev_time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("[CUDA noPath] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(hipMemcpy(res, arr_dev, sizeof(int), hipMemcpyDeviceToHost));
CUDA_CALL( hipDeviceSynchronize() );
CUDA_CALL(hipFree(arr_dev));
CUDA_CALL(hipFree(output_dev));
}
int arr[ARRAY_SIZE],
res_cuda1,
res_cuda2;
int main(int argc, char *argv[])
{
init_array(arr);
cuda_1(&res_cuda1,arr);
cuda_2(&res_cuda2,arr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define ARRAY_SIZE 10000
#define CUDA_CALL(x) { const hipError_t a = (x); if(a != hipSuccess) { printf("\nCuda Error: %s (err_num=%d) at line:%d\n", hipGetErrorString(a), a, __LINE__); hipDeviceReset(); assert(0);}}
void init_array(int arr[ARRAY_SIZE])
{
for(int i = 0 ; i < ARRAY_SIZE ; ++i)
arr[i] = rand()/10000;
}
static __global__ void cuda_noPath(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
if (threadIdx.x % (i*2) == 0 && tid + i < size)
arr[tid] = max(arr[tid], arr[tid + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
static __global__ void cuda_Path(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
int base = blockIdx.x * blockDim.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
int off = threadIdx.x * i*2;
int idx = base + off;
if ( off < blockDim.x && idx + i < size)
arr[tid] = max(arr[idx], arr[idx + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
extern "C" void cuda_2(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
hipEvent_t start,stop;
CUDA_CALL(hipMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(hipMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(hipMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, hipMemcpyHostToDevice));
float dev_time = 0.f;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_Path<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&dev_time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("[CUDA Path] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(hipMemcpy(res, arr_dev, sizeof(int), hipMemcpyDeviceToHost));
CUDA_CALL( hipDeviceSynchronize() );
CUDA_CALL(hipFree(arr_dev));
CUDA_CALL(hipFree(output_dev));
}
extern "C" void cuda_1(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
hipEvent_t start,stop;
CUDA_CALL(hipMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(hipMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(hipMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, hipMemcpyHostToDevice));
float dev_time = 0.f;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_noPath<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&dev_time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("[CUDA noPath] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(hipMemcpy(res, arr_dev, sizeof(int), hipMemcpyDeviceToHost));
CUDA_CALL( hipDeviceSynchronize() );
CUDA_CALL(hipFree(arr_dev));
CUDA_CALL(hipFree(output_dev));
}
int arr[ARRAY_SIZE],
res_cuda1,
res_cuda2;
int main(int argc, char *argv[])
{
init_array(arr);
cuda_1(&res_cuda1,arr);
cuda_2(&res_cuda2,arr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL11cuda_noPathPiS_i,"axG",@progbits,_ZL11cuda_noPathPiS_i,comdat
.globl _ZL11cuda_noPathPiS_i
.p2align 8
.type _ZL11cuda_noPathPiS_i,@function
_ZL11cuda_noPathPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_5
s_load_b32 s5, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s8, 1
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_ge_u32 s8, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s2, s8
s_lshl_b32 s8, s8, 1
v_add_nc_u32_e32 v5, s2, v1
s_add_i32 s9, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v6, s9, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_and_b32 s9, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v5, v7, v5
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11cuda_noPathPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11cuda_noPathPiS_i,"axG",@progbits,_ZL11cuda_noPathPiS_i,comdat
.Lfunc_end0:
.size _ZL11cuda_noPathPiS_i, .Lfunc_end0-_ZL11cuda_noPathPiS_i
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL9cuda_PathPiS_i,"axG",@progbits,_ZL9cuda_PathPiS_i,comdat
.globl _ZL9cuda_PathPiS_i
.p2align 8
.type _ZL9cuda_PathPiS_i,@function
_ZL9cuda_PathPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s5, s15, s3
s_cmp_lt_u32 s3, 2
v_add_nc_u32_e32 v1, s5, v0
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB1_5
s_load_b32 s8, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b32_e32 v9, 1, v0
s_mov_b32 s9, 1
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s9, s9, 1
s_waitcnt_vscnt null, 0x0
s_cmp_ge_u32 s9, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_3:
v_mul_lo_u32 v6, v9, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s5, v6
v_cmp_gt_u32_e32 vcc_lo, s3, v6
v_add_nc_u32_e32 v5, s9, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s8, v5
s_and_b32 s10, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s10
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[7:8], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v5, v7, v5
global_store_b32 v[3:4], v5, off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL9cuda_PathPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL9cuda_PathPiS_i,"axG",@progbits,_ZL9cuda_PathPiS_i,comdat
.Lfunc_end1:
.size _ZL9cuda_PathPiS_i, .Lfunc_end1-_ZL9cuda_PathPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11cuda_noPathPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11cuda_noPathPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL9cuda_PathPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL9cuda_PathPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define ARRAY_SIZE 10000
#define CUDA_CALL(x) { const hipError_t a = (x); if(a != hipSuccess) { printf("\nCuda Error: %s (err_num=%d) at line:%d\n", hipGetErrorString(a), a, __LINE__); hipDeviceReset(); assert(0);}}
void init_array(int arr[ARRAY_SIZE])
{
for(int i = 0 ; i < ARRAY_SIZE ; ++i)
arr[i] = rand()/10000;
}
static __global__ void cuda_noPath(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
if (threadIdx.x % (i*2) == 0 && tid + i < size)
arr[tid] = max(arr[tid], arr[tid + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
static __global__ void cuda_Path(int *arr, int *output, int size)
{
int tid = blockIdx.x* blockDim.x + threadIdx.x;
int base = blockIdx.x * blockDim.x;
for(int i = 1 ; i < blockDim.x ; i *= 2)
{
int off = threadIdx.x * i*2;
int idx = base + off;
if ( off < blockDim.x && idx + i < size)
arr[tid] = max(arr[idx], arr[idx + i]);
__syncthreads();
}
if( threadIdx.x == 0)
output[blockIdx.x] = arr[tid];
}
extern "C" void cuda_2(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
hipEvent_t start,stop;
CUDA_CALL(hipMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(hipMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(hipMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, hipMemcpyHostToDevice));
float dev_time = 0.f;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_Path<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&dev_time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("[CUDA Path] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(hipMemcpy(res, arr_dev, sizeof(int), hipMemcpyDeviceToHost));
CUDA_CALL( hipDeviceSynchronize() );
CUDA_CALL(hipFree(arr_dev));
CUDA_CALL(hipFree(output_dev));
}
extern "C" void cuda_1(int *res, int arr[ARRAY_SIZE] )
{
void *output_dev, *arr_dev;
int thread_num = 256;
int size = ARRAY_SIZE;
int block_num = (size + thread_num - 1) / thread_num;
hipEvent_t start,stop;
CUDA_CALL(hipMalloc((void**)&arr_dev, sizeof(int) * ARRAY_SIZE));
CUDA_CALL(hipMalloc((void**)&output_dev, sizeof(int) * block_num));
// transfer data from host to device.
CUDA_CALL(hipMemcpy(arr_dev, arr, sizeof(int) * ARRAY_SIZE, hipMemcpyHostToDevice));
float dev_time = 0.f;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
do {
//CHECK_TIME_START_GPU();
cuda_noPath<<<block_num, thread_num>>>((int*)arr_dev, (int*)output_dev, size);
//CHECK_TIME_END_GPU(device_time);
{
void *tmp = arr_dev;
arr_dev = output_dev;
output_dev = tmp;
}
size = block_num;
block_num = (size + thread_num - 1) / thread_num;
} while (size > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&dev_time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("[CUDA noPath] Elapsed Time : %.5f (sec).\n", dev_time/1000);
// transfer result from device to host.
CUDA_CALL(hipMemcpy(res, arr_dev, sizeof(int), hipMemcpyDeviceToHost));
CUDA_CALL( hipDeviceSynchronize() );
CUDA_CALL(hipFree(arr_dev));
CUDA_CALL(hipFree(output_dev));
}
int arr[ARRAY_SIZE],
res_cuda1,
res_cuda2;
int main(int argc, char *argv[])
{
init_array(arr);
cuda_1(&res_cuda1,arr);
cuda_2(&res_cuda2,arr);
return 0;
} | .text
.file "cuda.hip"
.globl _Z10init_arrayPi # -- Begin function _Z10init_arrayPi
.p2align 4, 0x90
.type _Z10init_arrayPi,@function
_Z10init_arrayPi: # @_Z10init_arrayPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rax # imm = 0x68DB8BAD
movq %rax, %rcx
shrq $63, %rcx
sarq $44, %rax
addl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB0_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10init_arrayPi, .Lfunc_end0-_Z10init_arrayPi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function cuda_2
.LCPI1_0:
.long 0x447a0000 # float 1000
.text
.globl cuda_2
.p2align 4, 0x90
.type cuda_2,@function
cuda_2: # @cuda_2
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, 56(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB1_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $60, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_2:
leaq 32(%rsp), %rdi
movl $160, %esi
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $61, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_4:
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $64, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_6:
movabsq $4294967296, %r15 # imm = 0x100000000
movl $0, 20(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10000, %r13d # imm = 0x2710
movl $40, %eax
movb $1, %r12b
leaq 256(%r15), %r14
leaq 128(%rsp), %rbx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 32(%rsp)
movl $1, %eax
movl %ebp, %r13d
testb $1, %r12b
movl $0, %r12d
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl %eax, %ebp
movl %eax, %edi
orq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r13d, 52(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_ZL9cuda_PathPiS_i, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $4, %edx
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_12
# %bb.11:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $96, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_12:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $97, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_14:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_16
# %bb.15:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $99, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_16:
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_18
# %bb.17:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $100, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_18:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_2, .Lfunc_end1-cuda_2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL24__device_stub__cuda_PathPiS_i
.type _ZL24__device_stub__cuda_PathPiS_i,@function
_ZL24__device_stub__cuda_PathPiS_i: # @_ZL24__device_stub__cuda_PathPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL9cuda_PathPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _ZL24__device_stub__cuda_PathPiS_i, .Lfunc_end2-_ZL24__device_stub__cuda_PathPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function cuda_1
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl cuda_1
.p2align 4, 0x90
.type cuda_1,@function
cuda_1: # @cuda_1
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, 56(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB3_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $116, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_2:
leaq 32(%rsp), %rdi
movl $160, %esi
callq hipMalloc
testl %eax, %eax
je .LBB3_4
# %bb.3:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $117, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_4:
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_6
# %bb.5:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $120, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_6:
movabsq $4294967296, %r15 # imm = 0x100000000
movl $0, 20(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10000, %r13d # imm = 0x2710
movl $40, %eax
movb $1, %r12b
leaq 256(%r15), %r14
leaq 128(%rsp), %rbx
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 32(%rsp)
movl $1, %eax
movl %ebp, %r13d
testb $1, %r12b
movl $0, %r12d
je .LBB3_10
.LBB3_7: # =>This Inner Loop Header: Depth=1
movl %eax, %ebp
movl %eax, %edi
orq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r13d, 52(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_ZL11cuda_noPathPiS_i, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_9
.LBB3_10:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $4, %edx
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_12
# %bb.11:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $152, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_12:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB3_14
# %bb.13:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $153, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_14:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB3_16
# %bb.15:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $155, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_16:
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB3_18
# %bb.17:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $156, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_18:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size cuda_1, .Lfunc_end3-cuda_1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__cuda_noPathPiS_i
.type _ZL26__device_stub__cuda_noPathPiS_i,@function
_ZL26__device_stub__cuda_noPathPiS_i: # @_ZL26__device_stub__cuda_noPathPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL11cuda_noPathPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _ZL26__device_stub__cuda_noPathPiS_i, .Lfunc_end4-_ZL26__device_stub__cuda_noPathPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq $-40000, %rbx # imm = 0xFFFF63C0
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rax # imm = 0x68DB8BAD
movq %rax, %rcx
shrq $63, %rcx
sarq $44, %rax
addl %ecx, %eax
movl %eax, arr+40000(%rbx)
addq $4, %rbx
jne .LBB5_1
# %bb.2: # %_Z10init_arrayPi.exit
movl $res_cuda1, %edi
movl $arr, %esi
callq cuda_1
movl $res_cuda2, %edi
movl $arr, %esi
callq cuda_2
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL9cuda_PathPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11cuda_noPathPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nCuda Error: %s (err_num=%d) at line:%d\n"
.size .L.str, 41
.type _ZL9cuda_PathPiS_i,@object # @_ZL9cuda_PathPiS_i
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL9cuda_PathPiS_i:
.quad _ZL24__device_stub__cuda_PathPiS_i
.size _ZL9cuda_PathPiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "[CUDA Path] Elapsed Time : %.5f (sec).\n"
.size .L.str.1, 40
.type _ZL11cuda_noPathPiS_i,@object # @_ZL11cuda_noPathPiS_i
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL11cuda_noPathPiS_i:
.quad _ZL26__device_stub__cuda_noPathPiS_i
.size _ZL11cuda_noPathPiS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "[CUDA noPath] Elapsed Time : %.5f (sec).\n"
.size .L.str.2, 42
.type arr,@object # @arr
.bss
.globl arr
.p2align 4, 0x0
arr:
.zero 40000
.size arr, 40000
.type res_cuda1,@object # @res_cuda1
.globl res_cuda1
.p2align 2, 0x0
res_cuda1:
.long 0 # 0x0
.size res_cuda1, 4
.type res_cuda2,@object # @res_cuda2
.globl res_cuda2
.p2align 2, 0x0
res_cuda2:
.long 0 # 0x0
.size res_cuda2, 4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL9cuda_PathPiS_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL11cuda_noPathPiS_i"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL24__device_stub__cuda_PathPiS_i
.addrsig_sym _ZL26__device_stub__cuda_noPathPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL9cuda_PathPiS_i
.addrsig_sym _ZL11cuda_noPathPiS_i
.addrsig_sym arr
.addrsig_sym res_cuda1
.addrsig_sym res_cuda2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9cuda_PathPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R2, R13, c[0x0][0x0], R8 ; /* 0x000000000d027a24 */
/* 0x001fc800078e0208 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd000078e0203 */
/*0090*/ @!P0 BRA 0x1f0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD R4, R0, R9, RZ ; /* 0x0000000900047224 */
/* 0x000fe200078e02ff */
/*00d0*/ BSSY B0, 0x1b0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*00e0*/ IMAD R6, R13, c[0x0][0x0], R4 ; /* 0x000000000d067a24 */
/* 0x000fca00078e0204 */
/*00f0*/ IADD3 R5, R6, R9, RZ ; /* 0x0000000906057210 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06270 */
/*0110*/ ISETP.GE.U32.OR P0, PT, R4, c[0x0][0x0], P0 ; /* 0x0000000004007a0c */
/* 0x000fda0000706470 */
/*0120*/ @P0 BRA 0x1a0 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fcc00078e0205 */
/*0150*/ IMAD.WIDE R6, R9, 0x4, R4 ; /* 0x0000000409067825 */
/* 0x000fe400078e0204 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IMNMX R11, R6, R5, !PT ; /* 0x00000005060b7217 */
/* 0x004fca0007800200 */
/*0190*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ SHF.L.U32 R9, R9, 0x1, RZ ; /* 0x0000000109097819 */
/* 0x000fe200000006ff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R9, c[0x0][0x0], PT ; /* 0x0000000009007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @!P0 BRA 0xc0 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*01f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea2000c1e1900 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.WIDE.U32 R4, R13, R4, c[0x0][0x168] ; /* 0x00005a000d047625 */
/* 0x000fca00078e0004 */
/*0240*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11cuda_noPathPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fca00078e0209 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fce00078e0203 */
/*0090*/ @!P0 BRA 0x2c0 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fca00078e00ff */
/*00b0*/ SHF.L.U32 R12, R7, 0x1, RZ ; /* 0x00000001070c7819 */
/* 0x000fe200000006ff */
/*00c0*/ BSSY B0, 0x280 ; /* 0x000001b000007945 */
/* 0x000fe60003800000 */
/*00d0*/ I2F.U32.RP R6, R12 ; /* 0x0000000c00067306 */
/* 0x000e220000209000 */
/*00e0*/ IMAD.MOV R11, RZ, RZ, -R12 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0c */
/*00f0*/ ISETP.NE.U32.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fcc0003f25070 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R11, R11, R5, RZ ; /* 0x000000050b0b7224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fe200078e0004 */
/*0160*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fca0007ffe0ff */
/*0170*/ IMAD.HI.U32 R5, R5, R9, RZ ; /* 0x0000000905057227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R10, RZ, RZ, -R5 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a05 */
/*0190*/ IMAD R5, R12, R10, R9 ; /* 0x0000000a0c057224 */
/* 0x000fca00078e0209 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R5, R12, PT ; /* 0x0000000c0500720c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R5, -R12, R5, RZ ; /* 0x000000050c050210 */
/* 0x000fc80007ffe1ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R5, R12, PT ; /* 0x0000000c0500720c */
/* 0x000fda0003f06070 */
/*01d0*/ @P0 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a0c */
/*01e0*/ @!P1 LOP3.LUT R5, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff059212 */
/* 0x000fc800078e33ff */
/*01f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05270 */
/*0200*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x000fda0000706670 */
/*0210*/ @P0 BRA 0x270 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*0230*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000eaa000c1e1900 */
/*0240*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0250*/ IMNMX R7, R6, R5, !PT ; /* 0x0000000506077217 */
/* 0x004fca0007800200 */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GE.U32.AND P0, PT, R12, c[0x0][0x0], PT ; /* 0x000000000c007a0c */
/* 0x000fe20003f06070 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff077224 */
/* 0x001fd800078e000c */
/*02b0*/ @!P0 BRA 0xb0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*02c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*02d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0310*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL11cuda_noPathPiS_i,"axG",@progbits,_ZL11cuda_noPathPiS_i,comdat
.globl _ZL11cuda_noPathPiS_i
.p2align 8
.type _ZL11cuda_noPathPiS_i,@function
_ZL11cuda_noPathPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_5
s_load_b32 s5, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s8, 1
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_ge_u32 s8, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s2, s8
s_lshl_b32 s8, s8, 1
v_add_nc_u32_e32 v5, s2, v1
s_add_i32 s9, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v6, s9, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_and_b32 s9, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v5, v7, v5
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11cuda_noPathPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11cuda_noPathPiS_i,"axG",@progbits,_ZL11cuda_noPathPiS_i,comdat
.Lfunc_end0:
.size _ZL11cuda_noPathPiS_i, .Lfunc_end0-_ZL11cuda_noPathPiS_i
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL9cuda_PathPiS_i,"axG",@progbits,_ZL9cuda_PathPiS_i,comdat
.globl _ZL9cuda_PathPiS_i
.p2align 8
.type _ZL9cuda_PathPiS_i,@function
_ZL9cuda_PathPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s5, s15, s3
s_cmp_lt_u32 s3, 2
v_add_nc_u32_e32 v1, s5, v0
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB1_5
s_load_b32 s8, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b32_e32 v9, 1, v0
s_mov_b32 s9, 1
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s9, s9, 1
s_waitcnt_vscnt null, 0x0
s_cmp_ge_u32 s9, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_3:
v_mul_lo_u32 v6, v9, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s5, v6
v_cmp_gt_u32_e32 vcc_lo, s3, v6
v_add_nc_u32_e32 v5, s9, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s8, v5
s_and_b32 s10, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s10
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[7:8], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v5, v7, v5
global_store_b32 v[3:4], v5, off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL9cuda_PathPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL9cuda_PathPiS_i,"axG",@progbits,_ZL9cuda_PathPiS_i,comdat
.Lfunc_end1:
.size _ZL9cuda_PathPiS_i, .Lfunc_end1-_ZL9cuda_PathPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
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.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
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.size: 2
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.size: 2
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.size: 8
.value_kind: hidden_global_offset_x
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.size: 8
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.size: 8
.value_kind: hidden_global_offset_z
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.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11cuda_noPathPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11cuda_noPathPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
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.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL9cuda_PathPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL9cuda_PathPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019be2d_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i, @function
_ZL31__device_stub__Z9cuda_PathPiS_iPiS_i:
.LFB2087:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL9cuda_PathPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i, .-_ZL31__device_stub__Z9cuda_PathPiS_iPiS_i
.type _ZL9cuda_PathPiS_i, @function
_ZL9cuda_PathPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL9cuda_PathPiS_i, .-_ZL9cuda_PathPiS_i
.type _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i, @function
_ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i:
.LFB2085:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL11cuda_noPathPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i, .-_ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i
.type _ZL11cuda_noPathPiS_i, @function
_ZL11cuda_noPathPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL11cuda_noPathPiS_i, .-_ZL11cuda_noPathPiS_i
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_arrayPi
.type _Z10init_arrayPi, @function
_Z10init_arrayPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq 40000(%rdi), %rbp
.L20:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
sarl $31, %eax
subl %eax, %edx
movl %edx, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10init_arrayPi, .-_Z10init_arrayPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nCuda Error: %s (err_num=%d) at line:%d\n"
.align 8
.LC3:
.string "[CUDA Path] Elapsed Time : %.5f (sec).\n"
.text
.globl cuda_2
.type cuda_2, @function
cuda_2:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
.L24:
leaq 16(%rsp), %rdi
movl $160, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
.L25:
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L38
.L26:
movl $0x00000000, 12(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ebp
movl $40, %ebx
movl $10000, %r13d
.L28:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L27:
movq 24(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 24(%rsp)
movq %rax, 16(%rsp)
leal 510(%rbx), %eax
movl %ebx, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %ebx, %r13d
subl $1, %ebp
jne .L34
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movss 12(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
.L29:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
.L30:
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L42
.L31:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $60, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L24
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $61, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L25
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $64, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L26
.L34:
movl %eax, %ebx
jmp .L28
.L39:
movl %r13d, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _ZL31__device_stub__Z9cuda_PathPiS_iPiS_i
jmp .L27
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $96, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L29
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $97, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L30
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $99, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L31
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $100, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L23
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size cuda_2, .-cuda_2
.section .rodata.str1.8
.align 8
.LC4:
.string "[CUDA noPath] Elapsed Time : %.5f (sec).\n"
.text
.globl cuda_1
.type cuda_1, @function
cuda_1:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
.L46:
leaq 16(%rsp), %rdi
movl $160, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L59
.L47:
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L60
.L48:
movl $0x00000000, 12(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ebp
movl $40, %ebx
movl $10000, %r13d
.L50:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L49:
movq 24(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 24(%rsp)
movq %rax, 16(%rsp)
leal 510(%rbx), %eax
movl %ebx, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %ebx, %r13d
subl $1, %ebp
jne .L56
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movss 12(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
.L51:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
.L52:
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
.L53:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
.L45:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $116, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L46
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $117, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L47
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $120, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L48
.L56:
movl %eax, %ebx
jmp .L50
.L61:
movl %r13d, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _ZL34__device_stub__Z11cuda_noPathPiS_iPiS_i
jmp .L49
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $152, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L51
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $153, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L52
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $155, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L53
.L65:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $156, %r8d
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L45
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size cuda_1, .-cuda_1
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq arr(%rip), %rbx
movq %rbx, %rdi
call _Z10init_arrayPi
movq %rbx, %rsi
leaq res_cuda1(%rip), %rdi
call cuda_1
movq %rbx, %rsi
leaq res_cuda2(%rip), %rdi
call cuda_2
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z9cuda_PathPiS_i"
.LC6:
.string "_Z11cuda_noPathPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9cuda_PathPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11cuda_noPathPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res_cuda2
.bss
.align 4
.type res_cuda2, @object
.size res_cuda2, 4
res_cuda2:
.zero 4
.globl res_cuda1
.align 4
.type res_cuda1, @object
.size res_cuda1, 4
res_cuda1:
.zero 4
.globl arr
.align 32
.type arr, @object
.size arr, 40000
arr:
.zero 40000
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z10init_arrayPi # -- Begin function _Z10init_arrayPi
.p2align 4, 0x90
.type _Z10init_arrayPi,@function
_Z10init_arrayPi: # @_Z10init_arrayPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rax # imm = 0x68DB8BAD
movq %rax, %rcx
shrq $63, %rcx
sarq $44, %rax
addl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB0_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10init_arrayPi, .Lfunc_end0-_Z10init_arrayPi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function cuda_2
.LCPI1_0:
.long 0x447a0000 # float 1000
.text
.globl cuda_2
.p2align 4, 0x90
.type cuda_2,@function
cuda_2: # @cuda_2
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, 56(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB1_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $60, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_2:
leaq 32(%rsp), %rdi
movl $160, %esi
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $61, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_4:
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $64, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_6:
movabsq $4294967296, %r15 # imm = 0x100000000
movl $0, 20(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10000, %r13d # imm = 0x2710
movl $40, %eax
movb $1, %r12b
leaq 256(%r15), %r14
leaq 128(%rsp), %rbx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 32(%rsp)
movl $1, %eax
movl %ebp, %r13d
testb $1, %r12b
movl $0, %r12d
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl %eax, %ebp
movl %eax, %edi
orq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r13d, 52(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_ZL9cuda_PathPiS_i, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $4, %edx
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_12
# %bb.11:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $96, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_12:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $97, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_14:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_16
# %bb.15:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $99, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_16:
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_18
# %bb.17:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $100, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB1_18:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_2, .Lfunc_end1-cuda_2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL24__device_stub__cuda_PathPiS_i
.type _ZL24__device_stub__cuda_PathPiS_i,@function
_ZL24__device_stub__cuda_PathPiS_i: # @_ZL24__device_stub__cuda_PathPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL9cuda_PathPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _ZL24__device_stub__cuda_PathPiS_i, .Lfunc_end2-_ZL24__device_stub__cuda_PathPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function cuda_1
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl cuda_1
.p2align 4, 0x90
.type cuda_1,@function
cuda_1: # @cuda_1
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, 56(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB3_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $116, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_2:
leaq 32(%rsp), %rdi
movl $160, %esi
callq hipMalloc
testl %eax, %eax
je .LBB3_4
# %bb.3:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebp, %edx
movl $117, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_4:
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_6
# %bb.5:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $120, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_6:
movabsq $4294967296, %r15 # imm = 0x100000000
movl $0, 20(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10000, %r13d # imm = 0x2710
movl $40, %eax
movb $1, %r12b
leaq 256(%r15), %r14
leaq 128(%rsp), %rbx
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 32(%rsp)
movl $1, %eax
movl %ebp, %r13d
testb $1, %r12b
movl $0, %r12d
je .LBB3_10
.LBB3_7: # =>This Inner Loop Header: Depth=1
movl %eax, %ebp
movl %eax, %edi
orq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r13d, 52(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_ZL11cuda_noPathPiS_i, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_9
.LBB3_10:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $4, %edx
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_12
# %bb.11:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $152, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_12:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB3_14
# %bb.13:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $153, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_14:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB3_16
# %bb.15:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $155, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_16:
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB3_18
# %bb.17:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $156, %ecx
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB3_18:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size cuda_1, .Lfunc_end3-cuda_1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__cuda_noPathPiS_i
.type _ZL26__device_stub__cuda_noPathPiS_i,@function
_ZL26__device_stub__cuda_noPathPiS_i: # @_ZL26__device_stub__cuda_noPathPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL11cuda_noPathPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _ZL26__device_stub__cuda_noPathPiS_i, .Lfunc_end4-_ZL26__device_stub__cuda_noPathPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq $-40000, %rbx # imm = 0xFFFF63C0
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rax # imm = 0x68DB8BAD
movq %rax, %rcx
shrq $63, %rcx
sarq $44, %rax
addl %ecx, %eax
movl %eax, arr+40000(%rbx)
addq $4, %rbx
jne .LBB5_1
# %bb.2: # %_Z10init_arrayPi.exit
movl $res_cuda1, %edi
movl $arr, %esi
callq cuda_1
movl $res_cuda2, %edi
movl $arr, %esi
callq cuda_2
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL9cuda_PathPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11cuda_noPathPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nCuda Error: %s (err_num=%d) at line:%d\n"
.size .L.str, 41
.type _ZL9cuda_PathPiS_i,@object # @_ZL9cuda_PathPiS_i
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL9cuda_PathPiS_i:
.quad _ZL24__device_stub__cuda_PathPiS_i
.size _ZL9cuda_PathPiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "[CUDA Path] Elapsed Time : %.5f (sec).\n"
.size .L.str.1, 40
.type _ZL11cuda_noPathPiS_i,@object # @_ZL11cuda_noPathPiS_i
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL11cuda_noPathPiS_i:
.quad _ZL26__device_stub__cuda_noPathPiS_i
.size _ZL11cuda_noPathPiS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "[CUDA noPath] Elapsed Time : %.5f (sec).\n"
.size .L.str.2, 42
.type arr,@object # @arr
.bss
.globl arr
.p2align 4, 0x0
arr:
.zero 40000
.size arr, 40000
.type res_cuda1,@object # @res_cuda1
.globl res_cuda1
.p2align 2, 0x0
res_cuda1:
.long 0 # 0x0
.size res_cuda1, 4
.type res_cuda2,@object # @res_cuda2
.globl res_cuda2
.p2align 2, 0x0
res_cuda2:
.long 0 # 0x0
.size res_cuda2, 4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL9cuda_PathPiS_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL11cuda_noPathPiS_i"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL24__device_stub__cuda_PathPiS_i
.addrsig_sym _ZL26__device_stub__cuda_noPathPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL9cuda_PathPiS_i
.addrsig_sym _ZL11cuda_noPathPiS_i
.addrsig_sym arr
.addrsig_sym res_cuda1
.addrsig_sym res_cuda2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* purpose: just a demo to show how vector addition can be done on
* the GPU with just a single thread block
* compilation: nvcc ./single_thread_block_vector_addition.cu
* usage: ./a.out
*/
#include <stdio.h>
#define N 100
/*
* GPU kernel
*/
__global__ void VecAdd(float *A, float *B, float *C)
{
int i;
i = threadIdx.x;
C[i] = A[i] + B[i];
}
/*
* host main
*/
int main()
{
int i;
dim3 numBlocks, threadsPerBlock;
float *A, *B, *C;
/*
* using CUDA unified memory, first allocate
* the memory then initialize with some dummy content
*/
cudaMallocManaged(&A, N * sizeof(float));
cudaMallocManaged(&B, N * sizeof(float));
cudaMallocManaged(&C, N * sizeof(float));
for (i = 0; i < N; i++) {
A[i] = (float) i;
B[i] = (float) (N - i);
C[i] = (float) 0;
}
/*
* set up GPU kernel execution configuration
* however, this time we send in explicit parameters
* directly
*/
threadsPerBlock.x = N;
numBlocks.x = 1;
/* launch the GPU kernel */
VecAdd<<<1, N>>>(A, B, C);
cudaDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
printf("%d %f\n", i, C[i]);
}
/* make clean */
cudaFree(C);
cudaFree(B);
cudaFree(A);
return(0);
} | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* purpose: just a demo to show how vector addition can be done on
* the GPU with just a single thread block
* compilation: nvcc ./single_thread_block_vector_addition.cu
* usage: ./a.out
*/
#include <stdio.h>
#define N 100
/*
* GPU kernel
*/
__global__ void VecAdd(float *A, float *B, float *C)
{
int i;
i = threadIdx.x;
C[i] = A[i] + B[i];
}
/*
* host main
*/
int main()
{
int i;
dim3 numBlocks, threadsPerBlock;
float *A, *B, *C;
/*
* using CUDA unified memory, first allocate
* the memory then initialize with some dummy content
*/
cudaMallocManaged(&A, N * sizeof(float));
cudaMallocManaged(&B, N * sizeof(float));
cudaMallocManaged(&C, N * sizeof(float));
for (i = 0; i < N; i++) {
A[i] = (float) i;
B[i] = (float) (N - i);
C[i] = (float) 0;
}
/*
* set up GPU kernel execution configuration
* however, this time we send in explicit parameters
* directly
*/
threadsPerBlock.x = N;
numBlocks.x = 1;
/* launch the GPU kernel */
VecAdd<<<1, N>>>(A, B, C);
cudaDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
printf("%d %f\n", i, C[i]);
}
/* make clean */
cudaFree(C);
cudaFree(B);
cudaFree(A);
return(0);
} | .file "tmpxft_001087e7_00000000-6_single_thread_block_vector_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $400, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $400, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $400, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movl $100, %ecx
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
movl %ecx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
movq 24(%rsp), %rdx
movl $0x00000000, (%rdx,%rax,4)
addq $1, %rax
cmpq $100, %rax
jne .L12
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L14:
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100, %rbx
jne .L14
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* purpose: just a demo to show how vector addition can be done on
* the GPU with just a single thread block
* compilation: nvcc ./single_thread_block_vector_addition.cu
* usage: ./a.out
*/
#include <stdio.h>
#define N 100
/*
* GPU kernel
*/
__global__ void VecAdd(float *A, float *B, float *C)
{
int i;
i = threadIdx.x;
C[i] = A[i] + B[i];
}
/*
* host main
*/
int main()
{
int i;
dim3 numBlocks, threadsPerBlock;
float *A, *B, *C;
/*
* using CUDA unified memory, first allocate
* the memory then initialize with some dummy content
*/
cudaMallocManaged(&A, N * sizeof(float));
cudaMallocManaged(&B, N * sizeof(float));
cudaMallocManaged(&C, N * sizeof(float));
for (i = 0; i < N; i++) {
A[i] = (float) i;
B[i] = (float) (N - i);
C[i] = (float) 0;
}
/*
* set up GPU kernel execution configuration
* however, this time we send in explicit parameters
* directly
*/
threadsPerBlock.x = N;
numBlocks.x = 1;
/* launch the GPU kernel */
VecAdd<<<1, N>>>(A, B, C);
cudaDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
printf("%d %f\n", i, C[i]);
}
/* make clean */
cudaFree(C);
cudaFree(B);
cudaFree(A);
return(0);
} | /*
* purpose: just a demo to show how vector addition can be done on
* the GPU with just a single thread block
* compilation: nvcc ./single_thread_block_vector_addition.cu
* usage: ./a.out
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 100
/*
* GPU kernel
*/
__global__ void VecAdd(float *A, float *B, float *C)
{
int i;
i = threadIdx.x;
C[i] = A[i] + B[i];
}
/*
* host main
*/
int main()
{
int i;
dim3 numBlocks, threadsPerBlock;
float *A, *B, *C;
/*
* using CUDA unified memory, first allocate
* the memory then initialize with some dummy content
*/
hipMallocManaged(&A, N * sizeof(float));
hipMallocManaged(&B, N * sizeof(float));
hipMallocManaged(&C, N * sizeof(float));
for (i = 0; i < N; i++) {
A[i] = (float) i;
B[i] = (float) (N - i);
C[i] = (float) 0;
}
/*
* set up GPU kernel execution configuration
* however, this time we send in explicit parameters
* directly
*/
threadsPerBlock.x = N;
numBlocks.x = 1;
/* launch the GPU kernel */
VecAdd<<<1, N>>>(A, B, C);
hipDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
printf("%d %f\n", i, C[i]);
}
/* make clean */
hipFree(C);
hipFree(B);
hipFree(A);
return(0);
} |
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